- fixed some bugs

git-svn-id: http://moon:8086/svn/vhdl/trunk@124 cc03376c-175c-47c8-b038-4cd826a8556b

lib/filter/src/fir_parallel.vhd

@@ -86,18 +86,19 @@ architecture Behavioral of fir_parallel is
 		h_in		: in sfixed;
 		out_valid	: out std_logic;
 		x_out		: out sfixed;
-		y_out		: out sfixed
+		y_out		: out sfixed;
+		y_out_clr	: in std_logic
 	);
 	END COMPONENT;
 
 	-------------------------------------------------------------------------------
-	type coeff_array_t is array (natural range <>) of sfixed(SFix_high(nbits_stages, nbits_stages_frac) downto SFix_low(nbits_stages, nbits_stages_frac));
+	type coeff_array_t is array (natural range <>) of sfixed(sproto(nbits_stages, nbits_stages_frac)'high downto sproto(nbits_stages, nbits_stages_frac)'low);
-	type stages_array_t is array (natural range <>) of sfixed(SFix_high(nbits_stages, nbits_stages_frac) downto SFix_low(nbits_stages, nbits_stages_frac));
+	type stages_array_t is array (natural range <>) of sfixed(sproto(nbits_stages, nbits_stages_frac)'high downto sproto(nbits_stages, nbits_stages_frac)'low);
 
 	constant zero_in : sfixed := to_sfixed(0, nbits_in, nbits_in_frac);
 	constant fir_stage_mode : fir_stage_mode_t := transposed;
 
-	SIGNAL x_out       : sfixed(SFix_high(nbits_out, nbits_out_frac) downto SFix_low(nbits_out, nbits_out_frac));
+	SIGNAL x_out       : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
 
 	SIGNAL x    	   : stages_array_t(0 to ntaps-2);
 	SIGNAL y           : stages_array_t(0 to ntaps-2);
@@ -139,7 +140,8 @@ begin
 			h_in		=> h(ntaps-1),
 			out_valid	=> out_valid,
 			x_out		=> x(0),
-			y_out		=> y(0)
+			y_out		=> y(0),
+			y_out_clr	=> '0'
 		);
 
 	----------------------------------------
@@ -169,7 +171,8 @@ begin
 			h_in		=> h(ntaps-i-1),
 			out_valid	=> open,
 			x_out		=> x(i),
-			y_out		=> y(i)
+			y_out		=> y(i),
+			y_out_clr	=> '0'
 		);
 	end generate;
 	
@@ -198,7 +201,8 @@ begin
 			h_in		=> h(0),
 			out_valid	=> open,
 			x_out		=> x_out,
-			y_out		=> d_out
+			y_out		=> d_out,
+			y_out_clr	=> '0'
 		);
 
 	----------------------------------------

lib/filter/src/fir_parallel_pkg.vhd

@@ -4,6 +4,7 @@ use IEEE.STD_LOGIC_1164.ALL;
 use ieee.numeric_std.all;
 use work.fixed_pkg.all;
 use work.filter_pkg.all;
+use work.fir_stage_pkg.all;
 
 -------------------------------------------------------------------------------
 package fir_parallel_pkg is
@@ -40,7 +41,7 @@ package body fir_parallel_pkg is
 
 	---------------------------------------------------------------------------
 	function to_sfixed_array(x : real_array_t; nbits, nbits_int : integer) return sfixed_array_t is
-	variable p : sfixed(SFix_high(nbits, nbits_int) downto SFix_low(nbits, nbits_int));
+	variable p : sfixed(sproto(nbits, nbits_int)'high downto sproto(nbits, nbits_int)'low);
 	begin
 		return to_sfixed_array(x, p);
 	end to_sfixed_array;	

lib/filter/src/tb_fir_parallel.vhd

@@ -19,6 +19,7 @@ use std.textio.all; --  Imports the standard textio package.
 
 library work;
 use work.fixed_pkg.all;
+use work.fir_stage_pkg.all;
 use work.fir_parallel_pkg.all;
 use work.filter_pkg.all;
 
@@ -83,16 +84,16 @@ ARCHITECTURE behavior OF tb_fir_parallel IS
 	SIGNAL clk         : std_logic := '0';
 	SIGNAL srst        : std_logic := '1';
 	SIGNAL in_valid    : std_logic := '0';
-	SIGNAL x_in        : sfixed(SFix_high(nbits_in, nbits_in_frac) downto SFix_low(nbits_in, nbits_in_frac));
+	SIGNAL x_in        : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
 
 	--Outputs
-	SIGNAL y_out       : sfixed(SFix_high(nbits_out, nbits_out_frac) downto SFix_low(nbits_out, nbits_out_frac));
+	SIGNAL y_out       : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
 	SIGNAL out_valid   : std_logic := '0';
 
 	SIGNAL fileout_enable   : std_logic := '1';
 	
 	-- Test coefficients
-	SIGNAL coeff_in : sfixed_array_t(0 to ntaps-1, SFix_high(nbits_stages, nbits_stages_frac) downto SFix_low(nbits_stages, nbits_stages_frac)) := to_sfixed_array(FilterCoef_Lowpass(ntaps, 0.125, 0.125), nbits_stages, nbits_stages_frac);
+	SIGNAL coeff_in : sfixed_array_t(0 to ntaps-1, sproto(nbits_stages, nbits_stages_frac)'high downto sproto(nbits_stages, nbits_stages_frac)'low) := to_sfixed_array(FilterCoef_Lowpass(ntaps, 0.125, 0.125), nbits_stages, nbits_stages_frac);
 	
 	SIGNAL xi, yo : real := 0.0;
 	

lib/filter/src/tb_fir_stage.vhd

@@ -69,7 +69,8 @@ ARCHITECTURE behavior OF tb_fir_stage IS
 		h_in		: in sfixed;
 		out_valid	: out std_logic;
 		x_out		: out sfixed;
-		y_out		: out sfixed
+		y_out		: out sfixed;
+		y_out_clr	: in std_logic
 	);
 	END COMPONENT;
 
@@ -135,6 +136,7 @@ BEGIN
 		PORT MAP
 		(
 			srst		=> srst,
+			y_out_clr	=> '0',
 			clk			=> clk,
 			in_valid	=> in_valid,
 			x_in		=> x_in,
@@ -165,6 +167,7 @@ BEGIN
 		PORT MAP
 		(
 			srst		=> srst,
+			y_out_clr	=> '0',
 			clk			=> clk,
 			in_valid	=> in_valid,
 			x_in		=> x(i-1),
@@ -194,6 +197,7 @@ BEGIN
 		PORT MAP
 		(
 			srst		=> srst,
+			y_out_clr	=> '0',
 			clk			=> clk,
 			in_valid	=> in_valid,
 			x_in		=> x(ntaps-2),