From c104c6e67d7d055561f3b39dbabe0aaa1e645081 Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Fri, 17 Oct 2008 17:41:44 +0000 Subject: [PATCH] - Intital revision git-svn-id: http://moon:8086/svn/vhdl/trunk@68 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/FIFO/src/fifo_sync_dist.vhd | 117 ++++++++++++++++++++++++++++++++ 1 file changed, 117 insertions(+) create mode 100644 lib/FIFO/src/fifo_sync_dist.vhd diff --git a/lib/FIFO/src/fifo_sync_dist.vhd b/lib/FIFO/src/fifo_sync_dist.vhd new file mode 100644 index 0000000..5914cd9 --- /dev/null +++ b/lib/FIFO/src/fifo_sync_dist.vhd @@ -0,0 +1,117 @@ +------------------------------------------------------------------------- +-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL +-- This file: Dual-ported register file with asynchrous read + +-- Copyright (C) 2007 J. Ahrensfeld + +-- This library is free software; you can redistribute it and/or +-- modify it under the terms of the GNU Lesser General Public +-- License as published by the Free Software Foundation; either +-- version 2.1 of the License, or (at your option) any later version. + +-- This library is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +-- Lesser General Public License for more details. + +-- You should have received a copy of the GNU Lesser General Public +-- License along with this library; if not, write to the Free Software +-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + +-- For questions and ideas, please contact the author at jens@jayfield.org + +----------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.NUMERIC_STD.ALL; + +use work.fifo_ctrl_pkg.all; + +entity fifo_sync_dist is + Generic ( + addr_width : natural := 4; + data_width : natural := 8; + almost_full_thresh : integer := 12; + almost_empty_thresh : integer := 4 + ); + Port + ( + rst : in STD_LOGIC; + clk : in STD_LOGIC; + we : in STD_LOGIC; + re : in STD_LOGIC; + fifo_full : out STD_LOGIC; + fifo_empty : out STD_LOGIC; + fifo_afull : out STD_LOGIC; + fifo_aempty : out STD_LOGIC; + data_w : in unsigned (data_width-1 downto 0); + data_r : out unsigned (data_width-1 downto 0) + ); +end fifo_sync_dist; + +architecture Behavioral of fifo_sync_dist is + + signal mem_wr_en : STD_LOGIC; + signal mem_rd_en : STD_LOGIC; + signal ptr_w : unsigned (addr_width-1 downto 0); + signal ptr_r : unsigned (addr_width-1 downto 0); + signal full : STD_LOGIC; + signal empty : STD_LOGIC; + signal almost_full : STD_LOGIC; + signal almost_empty : STD_LOGIC; + signal pre_full : STD_LOGIC; + signal pre_empty : STD_LOGIC; + +begin + + mem_wr_en <= not full; + mem_rd_en <= not pre_empty; + fifo_full <= full; + fifo_empty <= empty; + fifo_afull <= almost_full; + fifo_aempty <= almost_empty; + + inst_sync_fifo_ctrl: entity work.sync_fifo_ctrl + GENERIC MAP + ( + addr_width => addr_width, + almost_full_thresh => almost_full_thresh, + almost_empty_thresh => almost_empty_thresh + ) + PORT MAP + ( + rst => rst, + clk => clk, + we => we, + re => re, + ptr_w => ptr_w, + ptr_r => ptr_r, + fifo_full => full, + fifo_empty => empty, + fifo_pre_full => pre_full, + fifo_pre_empty => pre_empty, + fifo_afull => almost_full, + fifo_aempty => almost_empty + + ); + + inst_dpram_1w1r: entity work.dpram_1w1r_dist + GENERIC MAP ( + addr_width => addr_width, + data_width => data_width + ) + PORT MAP( + clka => clk, + clkb => clk, + en_a => mem_wr_en, + en_b => mem_rd_en, + we_a => we, + addr_a => ptr_w, + addr_b => ptr_r, + din_a => data_w, + dout_b => data_r + ); + +end Behavioral; +