From c10463c9617a58e76679cd5eae16d0ee609fcebd Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Sun, 4 Jan 2009 16:13:58 +0000 Subject: [PATCH] - removed reset from fir_stage_sys git-svn-id: http://moon:8086/svn/vhdl/trunk@201 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/filter/src/fir_semi_parallel.vhd | 18 ++++++++------ lib/filter/src/fir_stage_sys.vhd | 37 ++++++++++++++-------------- lib/filter/src/tb_fir_stage_sys.vhd | 11 ++++----- 3 files changed, 35 insertions(+), 31 deletions(-) diff --git a/lib/filter/src/fir_semi_parallel.vhd b/lib/filter/src/fir_semi_parallel.vhd index 41d03e3..672f6cf 100644 --- a/lib/filter/src/fir_semi_parallel.vhd +++ b/lib/filter/src/fir_semi_parallel.vhd @@ -105,6 +105,7 @@ architecture Behavioral of fir_semi_parallel is begin assert ntaps_per_stage = NextPowerOfTwo(ntaps_per_stage) report "ntaps_per_stage must be of form 2**R!" severity failure; + assert ntaps_per_stage >= 4 report "ntaps_per_stage must be greater than 4" severity failure; coef_addr <= to_unsigned(h_addr, coef_addr_nbits); stage_addr <= coef_addr(coef_addr'left downto NextExpBaseTwo(ntaps_per_stage)); @@ -156,10 +157,12 @@ coef_read: variable i : natural range 0 to nstages-1; begin - if rising_edge(clk) and en = '1' then - for i in 0 to nstages-1 loop - coef_stage(i) <= coef_array(i)(count_array(i)); - end loop; + if rising_edge(clk) then + if en = '1' then + for i in 0 to nstages-1 loop + coef_stage(i) <= coef_array(i)(count_array(i)); + end loop; + end if; end if; end process; @@ -194,8 +197,10 @@ counter: cnt_pipe: process(clk) begin - if rising_edge(clk) and en = '1' then - count_array <= count_array(count_array'left-1 downto 0) & count0; + if rising_edge(clk) then + if en = '1' then + count_array <= count_array(count_array'left-1 downto 0) & count0; + end if; end if; end process; @@ -227,7 +232,6 @@ gen_stages: ) PORT MAP ( - rst => rst, clk => clk, ce => en, x_in => x(i+1), diff --git a/lib/filter/src/fir_stage_sys.vhd b/lib/filter/src/fir_stage_sys.vhd index 8dd2b70..75a9a1a 100644 --- a/lib/filter/src/fir_stage_sys.vhd +++ b/lib/filter/src/fir_stage_sys.vhd @@ -48,7 +48,6 @@ Generic ); Port ( - rst : in std_logic; clk : in std_logic; ce : in std_logic; x_in : in sfixed; @@ -97,10 +96,12 @@ begin proc_xin: process(clk, x_in) begin x_pipe(0) <= resize(x_in, x_pipe(0)); - if rising_edge(clk) and ce = '1' then - for i in 1 to input_latency loop - x_pipe(i) <= x_pipe(i-1); - end loop; + if rising_edge(clk) then + if ce = '1' then + for i in 1 to input_latency loop + x_pipe(i) <= x_pipe(i-1); + end loop; + end if; end if; end process; @@ -109,10 +110,12 @@ begin proc_hin: process(clk, h_in) begin h_pipe(0) <= resize(h_in, h_pipe(0)); - if rising_edge(clk) and ce = '1' then - for i in 1 to coef_latency loop - h_pipe(i) <= h_pipe(i-1); - end loop; + if rising_edge(clk) then + if ce = '1' then + for i in 1 to coef_latency loop + h_pipe(i) <= h_pipe(i-1); + end loop; + end if; end if; end process; @@ -121,10 +124,12 @@ begin proc_pipe_reg: process(clk, xin, hin) begin mult_pipe(0) <= resize(xin * hin, mult_pipe(0)); - if rising_edge(clk) and ce = '1' then - for i in 1 to mult_latency loop - mult_pipe(i) <= mult_pipe(i-1); - end loop; + if rising_edge(clk) then + if ce = '1' then + for i in 1 to mult_latency loop + mult_pipe(i) <= mult_pipe(i-1); + end loop; + end if; end if; end process; @@ -134,11 +139,7 @@ begin begin if rising_edge(clk) then yout := resize(yin + prod, yout, fixed_wrap, fixed_truncate); - if rst = '1' then - y_out <= to_sfixed(0, yout); - elsif ce = '1' then - y_out <= yout; - end if; + y_out <= yout; end if; end process; diff --git a/lib/filter/src/tb_fir_stage_sys.vhd b/lib/filter/src/tb_fir_stage_sys.vhd index f421049..b0afe32 100644 --- a/lib/filter/src/tb_fir_stage_sys.vhd +++ b/lib/filter/src/tb_fir_stage_sys.vhd @@ -57,8 +57,8 @@ ARCHITECTURE behavior OF tb_fir_stage_sys IS ); PORT ( - rst : in std_logic; clk : in std_logic; + ce : in std_logic; x_in : in sfixed; y_in : in sfixed; h_in : in sfixed; @@ -74,7 +74,7 @@ ARCHITECTURE behavior OF tb_fir_stage_sys IS constant zero_in : sfixed := to_sfixed(0, nbits_in, nbits_in_frac); --Inputs - SIGNAL rst : std_logic := '1'; + SIGNAL ce : std_logic := '1'; SIGNAL clk : std_logic := '0'; SIGNAL x_in : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac)); @@ -123,8 +123,8 @@ BEGIN ) PORT MAP ( - rst => rst, clk => clk, + ce => ce, x_in => x_in, y_in => zero_in, h_in => h(ntaps-1), @@ -148,8 +148,8 @@ BEGIN ) PORT MAP ( - rst => rst, clk => clk, + ce => ce, x_in => x(i-1), y_in => y(i-1), h_in => h(ntaps-i-1), @@ -172,8 +172,8 @@ BEGIN ) PORT MAP ( - rst => rst, clk => clk, + ce => ce, x_in => x(ntaps-2), y_in => y(ntaps-2), h_in => h(0), @@ -196,7 +196,6 @@ BEGIN -- Wait 100 ns for global reset to finish wait for 4*PERIOD; - rst <= '0'; x_in <= to_sfixed(0.0, x_in); wait for 40*PERIOD;