From c0592b8ef42777d6732991ae11bc0ffb85da2219 Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Sun, 22 Nov 2009 22:38:25 +0000 Subject: [PATCH] - added full support for VGA-master 64-bit read/write to SDRAM Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@679 cc03376c-175c-47c8-b038-4cd826a8556b --- projects/mips_sys/src/mips_sys.vhd | 53 ++++++++++++++---------------- 1 file changed, 24 insertions(+), 29 deletions(-) diff --git a/projects/mips_sys/src/mips_sys.vhd b/projects/mips_sys/src/mips_sys.vhd index d9a5ce3..9fee083 100644 --- a/projects/mips_sys/src/mips_sys.vhd +++ b/projects/mips_sys/src/mips_sys.vhd @@ -359,9 +359,9 @@ ARCHITECTURE behavior OF mips_sys IS signal RST_O : std_logic; signal INT : unsigned(5 downto 0); signal MDAT_I : word_t; - signal MDAT_O : word_t; + signal MDAT_O : unsigned(63 downto 0); signal ADDR_O : word_t; - signal SEL_O : unsigned(3 downto 0); + signal SEL_O : unsigned(7 downto 0); signal WE_O : std_logic; signal CYC_O : std_logic; signal STB_O : std_logic; @@ -407,8 +407,6 @@ ARCHITECTURE behavior OF mips_sys IS signal ACK_O_sdram : std_logic; signal SRDY_O_sdram : std_logic; signal SDAT_O_sdram : unsigned(63 downto 0); - signal SDAT_I_sdram : unsigned(63 downto 0); - signal SEL_I_sdram : unsigned(7 downto 0); signal CYC_I_rom : std_logic; signal ACK_O_rom : std_logic; @@ -500,9 +498,6 @@ BEGIN RST_O <= not dcm_lock; - SDAT_I_sdram <= MDAT_O & MDAT_O; - SEL_I_sdram <= "0000" & SEL_O; - sys_flash_ac97_rstn <= ac97_rstn and flash_rstn; sys_uart1_tx <= uart1_tx; sys_uart2_tx <= uart1_tx; @@ -514,9 +509,9 @@ BEGIN --------------------------------------------------------------- -- Arbiter MRDY_O <= MRDY_O_cpu when arb_gnt(0) = '1' else MRDY_O_vga when arb_gnt(1) = '1' else '0'; - MDAT_O <= MDAT_O_cpu when arb_gnt(0) = '1' else MDAT_O_vga(31 downto 0) when arb_gnt(1) = '1' else (others => '0'); + MDAT_O <= (MDAT_O_cpu & MDAT_O_cpu) when arb_gnt(0) = '1' else MDAT_O_vga when arb_gnt(1) = '1' else (others => '0'); ADDR_O <= ADDR_O_cpu when arb_gnt(0) = '1' else ADDR_O_vga when arb_gnt(1) = '1' else (others => '0'); - SEL_O <= SEL_O_cpu when arb_gnt(0) = '1' else SEL_O_vga(3 downto 0) when arb_gnt(1) = '1' else (others => '0'); + SEL_O <= ("0000" & SEL_O_cpu) when arb_gnt(0) = '1' else SEL_O_vga when arb_gnt(1) = '1' else (others => '0'); WE_O <= WE_O_cpu when arb_gnt(0) = '1' else WE_O_vga when arb_gnt(1) = '1' else '0'; CYC_O <= CYC_O_cpu when arb_gnt(0) = '1' else CYC_O_vga when arb_gnt(1) = '1' else '0'; STB_O <= STB_O_cpu when arb_gnt(0) = '1' else STB_O_vga when arb_gnt(1) = '1' else '0'; @@ -528,7 +523,7 @@ BEGIN arb_req(0) <= CYC_O_cpu; arb_req(1) <= CYC_O_vga; - MDAT_I_vga <= SDAT_O_sdram(63 downto 32) & MDAT_I; + MDAT_I_vga <= SDAT_O_sdram; arbiter_proc: process(CLK_O) @@ -727,13 +722,13 @@ inst_gpio_wb : gpio_wb RST_I => RST_O, CYC_I => CYC_I_gpio, STB_I => STB_O, - SEL_I => SEL_O, + SEL_I => SEL_O(3 downto 0), WE_I => WE_O, ACK_O => ACK_O_gpio, SRDY_O => SRDY_O_gpio, MRDY_I => MRDY_O, ADDR_I => ADDR_O, - DAT_I => MDAT_O, + DAT_I => MDAT_O(31 downto 0), DAT_O => SDAT_O_gpio, INT_TIM_O => int_timer, @@ -761,9 +756,9 @@ inst_flash_port : async_port_wb ACK_O => ACK_O_flash, SRDY_O => SRDY_O_flash, MRDY_I => MRDY_O, - SEL_I => SEL_O, + SEL_I => SEL_O(3 downto 0), ADDR_I => ADDR_O, - DAT_I => MDAT_O, + DAT_I => MDAT_O(31 downto 0), DAT_O => SDAT_O_flash, page_mode_en => flash_page_mode_en, async_a => flash_addr, @@ -793,9 +788,9 @@ inst_usb_port : async_port_wb ACK_O => ACK_O_usb, SRDY_O => SRDY_O_usb, MRDY_I => MRDY_O, - SEL_I => SEL_O, + SEL_I => SEL_O(3 downto 0), ADDR_I => ADDR_O, - DAT_I => MDAT_O, + DAT_I => MDAT_O(31 downto 0), DAT_O => SDAT_O_usb, page_mode_en => '0', async_a => usb_addr, @@ -814,13 +809,13 @@ inst_uart_wb_0 : uart_wb RST_I => RST_O, CYC_I => CYC_I_uart0, STB_I => STB_O, - SEL_I => SEL_O, + SEL_I => SEL_O(3 downto 0), WE_I => WE_O, ACK_O => ACK_O_uart0, SRDY_O => SRDY_O_uart0, MRDY_I => MRDY_O, ADDR_I => ADDR_O, - DAT_I => MDAT_O, + DAT_I => MDAT_O(31 downto 0), DAT_O => SDAT_O_uart0, INT_O => int_uart0, ser_rx => sys_uart0_rx, @@ -834,13 +829,13 @@ inst_uart_wb_1 : uart_wb RST_I => RST_O, CYC_I => CYC_I_uart1, STB_I => STB_O, - SEL_I => SEL_O, + SEL_I => SEL_O(3 downto 0), WE_I => WE_O, ACK_O => ACK_O_uart1, SRDY_O => SRDY_O_uart1, MRDY_I => MRDY_O, ADDR_I => ADDR_O, - DAT_I => MDAT_O, + DAT_I => MDAT_O(31 downto 0), DAT_O => SDAT_O_uart1, INT_O => int_uart1, ser_rx => uart1_rx, @@ -890,13 +885,13 @@ inst_sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend64_wb CYC_I => CYC_I_sdram, STB_I => STB_O, - SEL_I => SEL_I_sdram, + SEL_I => SEL_O, WE_I => WE_O, ACK_O => ACK_O_sdram, MRDY_I => MRDY_O, SRDY_O => SRDY_O_sdram, ADDR_I => ADDR_O, - DAT_I => SDAT_I_sdram, + DAT_I => MDAT_O, DAT_O => SDAT_O_sdram, -- SDRAM signals @@ -946,12 +941,12 @@ inst_vga_frontend : vga_frontend64 CYC_I => CYC_I_vga, STB_I => STB_O, WE_I => WE_O, - SEL_I => SEL_O, + SEL_I => SEL_O(3 downto 0), ACK_O => ACK_O_vga, SRDY_O => SRDY_O_vga, MRDY_I => MRDY_O, ADDR_I => ADDR_O, - SDAT_I => MDAT_O, + SDAT_I => MDAT_O(31 downto 0), SDAT_O => SDAT_O_vga, -- VGA signals @@ -983,7 +978,7 @@ inst_ac97_wb : entity work.ac97_wb SRDY_O => SRDY_O_ac97, MRDY_I => MRDY_O, ADDR_I => ADDR_O, - DAT_I => MDAT_O, + DAT_I => MDAT_O(31 downto 0), DAT_O => SDAT_O_ac97, INT_O => INT_O_ac97, @@ -1006,13 +1001,13 @@ inst_ps2_wb_0: entity work.ps2_wb RST_I => RST_O, CYC_I => CYC_I_ps2_0, STB_I => STB_O, - SEL_I => SEL_O, + SEL_I => SEL_O(3 downto 0), WE_I => WE_O, ACK_O => ACK_O_ps2_0, SRDY_O => SRDY_O_ps2_0, MRDY_I => MRDY_O, ADDR_I => ADDR_O, - DAT_I => MDAT_O, + DAT_I => MDAT_O(31 downto 0), DAT_O => SDAT_O_ps2_0, INT_O => INT_O_ps2_0, clk_rx => ps2_0_clk_rx, @@ -1045,13 +1040,13 @@ inst_ps2_wb_1: entity work.ps2_wb RST_I => RST_O, CYC_I => CYC_I_ps2_1, STB_I => STB_O, - SEL_I => SEL_O, + SEL_I => SEL_O(3 downto 0), WE_I => WE_O, ACK_O => ACK_O_ps2_1, SRDY_O => SRDY_O_ps2_1, MRDY_I => MRDY_O, ADDR_I => ADDR_O, - DAT_I => MDAT_O, + DAT_I => MDAT_O(31 downto 0), DAT_O => SDAT_O_ps2_1, INT_O => INT_O_ps2_1, clk_rx => ps2_1_clk_rx,