From c00c2546360ebe2d80c326a0a90a02d3043a5086 Mon Sep 17 00:00:00 2001
From: Jens Ahrensfeld <jens@jayfield.org>
Date: Thu, 8 Apr 2010 16:52:47 +0000
Subject: [PATCH] - never ending PISO story Committed on the Free edition of
 March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and
 support: http://march-hare.com/cvsnt/

git-svn-id: http://moon:8086/svn/vhdl/trunk@883 cc03376c-175c-47c8-b038-4cd826a8556b
---
 lib/emac/src/piso.vhd | 66 ++++++++++++++++---------------------------
 1 file changed, 24 insertions(+), 42 deletions(-)

diff --git a/lib/emac/src/piso.vhd b/lib/emac/src/piso.vhd
index 037ff3f..1c27e8d 100644
--- a/lib/emac/src/piso.vhd
+++ b/lib/emac/src/piso.vhd
@@ -31,19 +31,18 @@ ARCHITECTURE behavior OF piso IS
 
 	constant num_shifts		: natural := data_width_in/data_width_out;
 	signal pre_fin			: STD_LOGIC;
-	signal rdy				: STD_LOGIC;
 	signal shift_cnt_pipe	: unsigned(num_shifts-1 downto 0);
 	signal shift_pipe		: unsigned(data_width_in-1 downto 0);
 	signal vld_pipe			: unsigned(num_shifts-1 downto 0);
 	signal din_reg			: unsigned(data_width_in-1 downto 0);
 	signal din_be_reg		: unsigned(num_shifts-1 downto 0);
-	signal din_vld_reg		: STD_LOGIC;
+	signal din_reg_empty	: STD_LOGIC;
 	
 --------------------------------------------------------------------------
 begin
 
 	pre_fin		<= shift_cnt_pipe(shift_cnt_pipe'left-1);
-	din_rdy		<= rdy;
+	din_rdy		<= din_reg_empty;
 	dout_vld	<= vld_pipe(vld_pipe'left) when msb_first else vld_pipe(0);
 	dout		<= 		shift_pipe(shift_pipe'left downto shift_pipe'left-data_width_out+1) when msb_first
 				else	shift_pipe(data_width_out-1 downto 0);
@@ -53,11 +52,13 @@ process(clk)
 begin
 	if rising_edge(clk) then
 		if rst = '1' then
-			rdy			<= '0';
-		elsif pre_fin = '1' and rdy = '0' then
-			rdy		<= '1';
-		elsif din_vld = '1' then
-			rdy			<= '0';
+			din_reg_empty	<= '1';
+		elsif din_reg_empty = '1' then
+			if din_vld = '1' then
+				din_reg_empty	<= '0';
+			end if;
+		elsif pre_fin = '1' and dout_en = '1' then
+			din_reg_empty	<= '1';
 		end if;
 	end if;
 end process;
@@ -65,18 +66,7 @@ end process;
 process(clk)
 begin
 	if rising_edge(clk) then
-		if rst = '1' then
-			din_vld_reg	<= '0';
-		elsif (pre_fin = '1' and dout_en = '1') or din_vld_reg = '0' then
-			din_vld_reg	<= din_vld;
-		end if;
-	end if;
-end process;
-
-process(clk)
-begin
-	if rising_edge(clk) then
-		if din_vld = '1' and rdy = '1' then
+		if din_vld = '1' and din_reg_empty = '1' then
 			din_reg		<= din;
 			din_be_reg	<= din_be;
 		end if;
@@ -88,14 +78,10 @@ begin
 	if rising_edge(clk) then
 		if rst = '1' then
 			shift_cnt_pipe	<= (others => '1');
-		elsif (din_vld = '1' and din_vld_reg = '0') then
+		elsif (pre_fin = '1' and dout_en = '1' and din_reg_empty = '0') then
 			shift_cnt_pipe	<= (others => '0');
 		elsif dout_en = '1' then
-			if (pre_fin = '1' and din_vld_reg = '1') then
-				shift_cnt_pipe	<= (others => '0');
-			else
-				shift_cnt_pipe	<= shift_cnt_pipe(shift_cnt_pipe'left-1 downto 0)  & '1';
-			end if;
+			shift_cnt_pipe	<= shift_cnt_pipe(shift_cnt_pipe'left-1 downto 0)  & '1';
 		end if;
 	end if;
 end process;
@@ -104,15 +90,13 @@ end process;
 process(clk)
 begin
 	if rising_edge(clk) then
-		if dout_en = '1' then
-			if pre_fin = '1' and din_vld_reg = '1' then
-				shift_pipe		<= din_reg;
-			else	
-				if (msb_first) then
-					shift_pipe		<= shift_pipe(shift_pipe'left-data_width_out downto 0) & (data_width_out-1 downto 0 => '0');
-				else
-					shift_pipe		<= (data_width_out-1 downto 0 => '0') & shift_pipe(shift_pipe'left downto data_width_out);
-				end if;
+		if (pre_fin = '1' and dout_en = '1' and din_reg_empty = '0') then
+			shift_pipe		<= din_reg;
+		elsif dout_en = '1' then
+			if (msb_first) then
+				shift_pipe		<= shift_pipe(shift_pipe'left-data_width_out downto 0) & (data_width_out-1 downto 0 => '0');
+			else
+				shift_pipe		<= (data_width_out-1 downto 0 => '0') & shift_pipe(shift_pipe'left downto data_width_out);
 			end if;
 		end if;
 	end if;
@@ -124,15 +108,13 @@ begin
 	if rising_edge(clk) then
 		if rst = '1' then
 			vld_pipe	<= (others => '0');
+		elsif (pre_fin = '1' and dout_en = '1' and din_reg_empty = '0') then
+			vld_pipe		<= din_be_reg;
 		elsif dout_en = '1' then
-			if pre_fin = '1' and din_vld_reg = '1' then
-				vld_pipe		<= din_be_reg;
+			if (msb_first) then
+				vld_pipe		<= vld_pipe(vld_pipe'left-1 downto 0) & '0';
 			else
-				if (msb_first) then
-					vld_pipe		<= vld_pipe(vld_pipe'left-1 downto 0) & '0';
-				else
-					vld_pipe		<= '0' & vld_pipe(vld_pipe'left downto 1);
-				end if;
+				vld_pipe		<= '0' & vld_pipe(vld_pipe'left downto 1);
 			end if;
 		end if;
 	end if;