diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend64_wb.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend64_wb.vhd
index ed64e0e..1de777d 100644
--- a/lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend64_wb.vhd
+++ b/lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend64_wb.vhd
@@ -152,7 +152,7 @@ inst_clockgen : entity work.clockgen
 	(
 		BL 				=> BURST_LEN,
 		f_sysclk 		=> 100E6,
-		fifo_depth		=> 3
+		fifo_depth		=> 4
 	)
 	PORT MAP
 	(
diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend_wb.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend_wb.vhd
index eae70cd..2a9d9bf 100644
--- a/lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend_wb.vhd
+++ b/lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend_wb.vhd
@@ -147,7 +147,7 @@ inst_clockgen : entity work.clockgen
 	(
 		BL 				=> BURST_LEN,
 		f_sysclk 		=> 100E6,
-		fifo_depth		=> 5
+		fifo_depth		=> 4
 	)
 	PORT MAP
 	(