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git-svn-id: http://moon:8086/svn/vhdl/trunk@1424 cc03376c-175c-47c8-b038-4cd826a8556b
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jens
2021-03-21 11:37:55 +00:00
parent 73cfd45401
commit bdb8fec295
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projects/dlx/syn/ise/project/dlx_test.prj
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vhdl work "E:/work/lib/HDL/Cores/CPUs/DLX/dlx_types.vhdl"
vhdl work "E:/work/lib/HDL/Cores/CPUs/DLX/dlx_instr.vhdl"
vhdl work "E:/work/lib/HDL/Cores/CPUs/DLX/alu_types.vhdl"
vhdl work "E:/work/lib/HDL/Cores/CPUs/DLX/reg_multiple_plus_one_out_reset.vhdl"
vhdl work "E:/work/lib/HDL/Cores/CPUs/DLX/reg_multiple_plus_one_out.vhdl"
vhdl work "E:/work/lib/HDL/Cores/CPUs/DLX/reg_multiple_out.vhdl"
vhdl work "E:/work/lib/HDL/Cores/CPUs/DLX/reg_file.vhdl"
vhdl work "E:/work/lib/HDL/Cores/CPUs/DLX/reg.vhdl"
vhdl work "E:/work/lib/HDL/Cores/CPUs/DLX/mux2.vhdl"
vhdl work "E:/work/lib/HDL/Cores/CPUs/DLX/ir_extender.vhdl"
vhdl work "E:/work/lib/HDL/Cores/CPUs/DLX/controller.vhdl"
vhdl work "E:/work/lib/HDL/Cores/CPUs/DLX/alu.vhdl"
vhdl work "E:/work/lib/HDL/Cores/CPUs/DLX/reg_multiple_plus_one_out_reset-behavior.vhdl"
vhdl work "E:/work/lib/HDL/Cores/CPUs/DLX/reg_multiple_plus_one_out-behavior.vhdl"
vhdl work "E:/work/lib/HDL/Cores/CPUs/DLX/reg_multiple_out-behavior.vhdl"
vhdl work "E:/work/lib/HDL/Cores/CPUs/DLX/reg_file-behavior.vhdl"
vhdl work "E:/work/lib/HDL/Cores/CPUs/DLX/reg-behavior.vhdl"
vhdl work "E:/work/lib/HDL/Cores/CPUs/DLX/mux2-behavior.vhdl"
vhdl work "E:/work/lib/HDL/Cores/CPUs/DLX/ir_extender-behavior.vhdl"
vhdl work "E:/work/lib/HDL/Cores/CPUs/DLX/controller-behavior.vhdl"
vhdl work "E:/work/lib/HDL/Cores/CPUs/DLX/alu-behavior.vhdl"
vhdl work "E:/work/lib/HDL/Cores/CPUs/DLX/memory.vhdl"
vhdl work "E:/work/lib/HDL/Cores/CPUs/DLX/dlx.vhdl"
vhdl work "E:/work/lib/HDL/Cores/CPUs/DLX/clock_gen.vhdl"
vhdl work "E:/work/lib/HDL/Cores/CPUs/DLX/memory-file_loaded.vhdl"
vhdl work "E:/work/lib/HDL/Cores/CPUs/DLX/dlx-rtl.vhdl"
vhdl work "E:/work/lib/HDL/Cores/CPUs/DLX/clock_gen-behavior.vhdl"
vhdl work "E:/work/lib/HDL/Cores/CPUs/DLX/dlx_test-verifier.vhdl"