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git-svn-id: http://moon:8086/svn/vhdl/trunk@1424 cc03376c-175c-47c8-b038-4cd826a8556b
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--------------------------------------------------------------------------
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--
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-- Copyright (C) 1993, Peter J. Ashenden
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-- Mail: Dept. Computer Science
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-- University of Adelaide, SA 5005, Australia
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-- e-mail: petera@cs.adelaide.edu.au
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 1, or (at your option)
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-- any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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--
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--------------------------------------------------------------------------
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--
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-- $RCSfile: memory_test-bench.vhdl,v $ $Revision: 2.1 $ $Date: 1993/10/31 21:10:12 $
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--
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--------------------------------------------------------------------------
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--
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-- Architecture for test bench for behavioural architecture of memory
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--
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use std.textio.all,
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work.dlx_types.all,
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work.mem_types.all,
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work.bv_arithmetic.bv_addu,
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work.images.image_hex;
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architecture bench of memory_test is
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component clock_gen
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port (phi1, phi2 : out bit;
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reset : out bit);
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end component;
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component memory
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port (phi1, phi2 : in bit;
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a : in dlx_address;
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d : inout dlx_word_bus bus;
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width : in mem_width;
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write_enable : in bit;
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burst : in bit;
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mem_enable : in bit;
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ready : out bit);
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end component;
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for cg : clock_gen
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use entity work.clock_gen(behaviour)
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generic map (Tpw => 8 ns, Tps => 2 ns);
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for mem : memory
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use entity work.memory(behaviour)
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generic map (mem_size => 65536,
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Tac1 => 95 ns, Tacb => 15 ns, Tpd_clk_out => 2 ns);
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signal phi1, phi2, reset : bit;
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signal a : dlx_address;
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signal d : dlx_word_bus bus;
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signal width : mem_width;
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signal write_enable, mem_enable, burst, ifetch, ready : bit;
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begin
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cg : clock_gen
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port map (phi1, phi2, reset);
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mem : memory
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port map (phi1, phi2, a, d, width, write_enable, burst, mem_enable, ready);
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test: process
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variable data_word : dlx_word;
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variable L : line;
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VARIABLE blk : dlx_word_array(1 to 4);
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procedure write (address : in dlx_address;
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data_width : in mem_width;
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data : in dlx_word;
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Tpd_clk_out : in time -- clock to output delay
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) is
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begin -- write
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wait until phi1 = '1';
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if reset = '1' then
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return;
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end if;
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a <= address after Tpd_clk_out;
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width <= data_width after Tpd_clk_out;
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d <= data after Tpd_clk_out;
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write_enable <= '1' after Tpd_clk_out;
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burst <= '0' after Tpd_Clk_Out;
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mem_enable <= '1' after Tpd_clk_out;
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ifetch <= '0' after Tpd_clk_out;
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loop
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wait until phi2 = '0';
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exit when ready = '1' or reset = '1';
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end loop;
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d <= null after Tpd_clk_out;
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write_enable <= '0' after Tpd_clk_out;
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mem_enable <= '0' after Tpd_clk_out;
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end write;
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procedure read (address : in dlx_address;
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data_width : in mem_width;
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instr_fetch : in boolean;
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data : out dlx_word;
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Tpd_clk_out : in time -- clock to output delay
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) is
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begin -- read
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wait until phi1 = '1';
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if reset = '1' then
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return;
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end if;
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a <= address after Tpd_clk_out;
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width <= data_width after Tpd_clk_out;
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write_enable <= '0' after Tpd_clk_out;
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burst <= '0' after Tpd_Clk_Out;
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mem_enable <= '1' after Tpd_clk_out;
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ifetch <= bit'val(boolean'pos(instr_fetch)) after Tpd_clk_out;
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loop
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wait until phi2 = '0';
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exit when ready = '1' or reset = '1';
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end loop;
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data := d;
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mem_enable <= '0' after Tpd_clk_out;
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end read;
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procedure write_burst (address : in dlx_address;
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data : in dlx_word_array;
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Tpd_clk_out : in time -- clock to output delay
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) is
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VARIABLE next_address : dlx_address := address;
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VARIABLE ignore_overflow : boolean;
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VARIABLE index : natural;
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begin -- write_burst
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wait until phi1 = '1';
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if reset = '1' then
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return;
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end if;
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width <= width_word after Tpd_clk_out;
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write_enable <= '1' after Tpd_clk_out;
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mem_enable <= '1' after Tpd_clk_out;
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ifetch <= '0' after Tpd_clk_out;
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burst <= '1' after Tpd_Clk_Out;
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index := data'left;
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burst_loop : LOOP
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IF (index = data'right) THEN
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burst <= '0' after Tpd_Clk_Out;
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END IF;
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a <= next_address after Tpd_clk_out;
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d <= data(index) after Tpd_clk_out;
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wait_loop : LOOP
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WAIT UNTIL phi2 = '0';
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EXIT burst_loop WHEN reset = '1' OR (ready = '1' AND index = data'right);
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EXIT wait_loop WHEN ready = '1';
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END LOOP wait_loop;
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index := index + 1;
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bv_addu(next_address, X"00000004", next_address, ignore_overflow);
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END LOOP burst_loop;
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d <= null after Tpd_clk_out;
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write_enable <= '0' after Tpd_clk_out;
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mem_enable <= '0' after Tpd_clk_out;
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end write_burst;
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procedure read_burst (address : in dlx_address;
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data : out dlx_word_array;
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Tpd_clk_out : in time -- clock to output delay
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) is
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VARIABLE next_address : dlx_address := address;
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VARIABLE ignore_overflow : boolean;
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VARIABLE index : natural;
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begin -- read_burst
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wait until phi1 = '1';
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if reset = '1' then
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return;
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end if;
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width <= width_word after Tpd_clk_out;
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write_enable <= '0' after Tpd_clk_out;
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mem_enable <= '1' after Tpd_clk_out;
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ifetch <= '0' after Tpd_clk_out;
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burst <= '1' after Tpd_Clk_Out;
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index := data'left;
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burst_loop : LOOP
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IF (index = data'right) THEN
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burst <= '0' after Tpd_Clk_Out;
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END IF;
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a <= next_address after Tpd_clk_out;
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wait_loop : LOOP
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WAIT UNTIL phi2 = '0';
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data(index) := d;
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EXIT burst_loop WHEN reset = '1' OR (ready = '1' AND index = data'right);
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EXIT wait_loop WHEN ready = '1';
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END LOOP wait_loop;
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index := index + 1;
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bv_addu(next_address, X"00000004", next_address, ignore_overflow);
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END LOOP burst_loop;
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mem_enable <= '0' after Tpd_clk_out;
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end read_burst;
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begin
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wait until reset = '0';
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write(L, string'("Write word X""00000004"" to 4:"));
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writeline(output, L);
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write(X"0000_0004", width_word, X"00000004", 2 ns);
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--
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write(L, string'("Read word from X""00000004"":"));
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writeline(output, L);
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data_word := X"0000_0000";
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read(X"0000_0004", width_word, false, data_word, 2 ns);
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write(L, string'(" result:"));
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write(L, image_hex(data_word));
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writeline(output, L);
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--
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write(L, string'("Write halfword X""2222"" to 0:"));
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writeline(output, L);
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write(X"0000_0000", width_halfword, X"2222_0000", 2 ns);
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--
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write(L, string'("Write halfword X""3333"" to 2:"));
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writeline(output, L);
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write(X"0000_0002", width_halfword, X"0000_3333", 2 ns);
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--
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write(L, string'("Read word from X""00000000"":"));
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writeline(output, L);
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data_word := X"0000_0000";
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read(X"0000_0000", width_word, false, data_word, 2 ns);
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write(L, string'(" result:"));
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write(L, image_hex(data_word));
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writeline(output, L);
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--
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write(L, string'("Read halfword from X""00000003"":"));
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writeline(output, L);
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data_word := X"0000_0000";
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read(X"0000_0003", width_halfword, false, data_word, 2 ns);
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write(L, string'(" result:"));
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write(L, image_hex(data_word));
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writeline(output, L);
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--
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write(L, string'("Write bytes X""44"" to 4, X""55"" to 5, X""66"" to 6, X""77"" to 7:"));
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writeline(output, L);
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write(X"0000_0004", width_byte, X"44_00_00_00", 2 ns);
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write(X"0000_0005", width_byte, X"00_55_00_00", 2 ns);
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write(X"0000_0006", width_byte, X"00_00_66_00", 2 ns);
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write(X"0000_0007", width_byte, X"00_00_00_77", 2 ns);
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--
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write(L, string'("Read word from X""00000004"":"));
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writeline(output, L);
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data_word := X"0000_0000";
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read(X"0000_0004", width_word, false, data_word, 2 ns);
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write(L, string'(" result:"));
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write(L, image_hex(data_word));
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writeline(output, L);
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--
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write(L, string'("Read byte from X""00000004"":"));
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writeline(output, L);
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data_word := X"0000_0000";
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read(X"0000_0004", width_byte, false, data_word, 2 ns);
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write(L, string'(" result:"));
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write(L, image_hex(data_word));
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writeline(output, L);
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--
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write(L, string'("Read byte from X""00000005"":"));
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writeline(output, L);
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data_word := X"0000_0000";
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read(X"0000_0005", width_byte, false, data_word, 2 ns);
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write(L, string'(" result:"));
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write(L, image_hex(data_word));
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writeline(output, L);
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--
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write(L, string'("Read byte from X""00000006"":"));
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writeline(output, L);
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data_word := X"0000_0000";
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read(X"0000_0006", width_byte, false, data_word, 2 ns);
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write(L, string'(" result:"));
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write(L, image_hex(data_word));
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writeline(output, L);
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--
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write(L, string'("Read byte from X""00000007"":"));
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writeline(output, L);
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data_word := X"0000_0000";
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read(X"0000_0007", width_byte, false, data_word, 2 ns);
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write(L, string'(" result:"));
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write(L, image_hex(data_word));
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writeline(output, L);
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--
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write(L, string'("Write burst to 8..11:"));
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writeline(output, L);
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blk := (X"88888888", X"99999999", X"AAAAAAAA", X"BBBBBBBB");
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write_burst(X"0000_0008", blk, 2 ns);
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--
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write(L, string'("Read burst from 8..11:"));
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writeline(output, L);
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blk := (OTHERS => X"0000_0000");
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read_burst(X"0000_0008", blk, 2 ns);
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write(L, string'(" result: ("));
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FOR i IN blk'range LOOP
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write(L, image_hex(blk(i)));
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IF (i /= blk'right) THEN
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write(L, string'(", "));
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END IF;
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END LOOP; -- i
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write(L, ')');
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writeline(output, L);
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--
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-- This should hang
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write(L, string'("Read word from X""00100000"":"));
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writeline(output, L);
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data_word := X"0000_0000";
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read(X"0010_0000", width_word, false, data_word, 2 ns);
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write(L, string'(" result:"));
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write(L, data_word);
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writeline(output, L);
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--
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end process test;
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end bench;
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