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- added ethernet MAC

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git-svn-id: http://moon:8086/svn/vhdl/trunk@850 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2010-03-30 10:22:46 +00:00
parent 25b57a30fe
commit bd90e641cf
2 changed files with 189 additions and 266 deletions
Download Patch File Download Diff File Expand all files Collapse all files
projects/mips_sys/src/mips_sys_sim.vhd
+132 -261
View File
@@ -131,6 +131,23 @@ PORT
sys_ps2_clk : inout std_logic; sys_ps2_clk : inout std_logic;
sys_ps2_data : inout std_logic; sys_ps2_data : inout std_logic;
sys_phy_rstn : out std_logic;
sys_phy_mdc : out std_logic;
sys_phy_mdio : inout std_logic;
sys_phy_int : in std_logic;
sys_phy_rx_clk : in STD_LOGIC;
sys_phy_rx_dv : in STD_LOGIC;
sys_phy_rx_er : in STD_LOGIC;
sys_phy_rx : in unsigned(7 downto 0);
sys_phy_tx_clk : in STD_LOGIC;
sys_phy_tx_en : out STD_LOGIC;
sys_phy_tx_er : out STD_LOGIC;
sys_phy_tx : out unsigned(7 downto 0);
sys_phy_gtx_clk : out STD_LOGIC;
sys_phy_crs : in STD_LOGIC;
sys_phy_col : in STD_LOGIC;
sys_error : out unsigned(1 downto 0) -- indicates Errors sys_error : out unsigned(1 downto 0) -- indicates Errors
); );
@@ -142,228 +159,6 @@ END mips_sys;
ARCHITECTURE behavior OF mips_sys IS ARCHITECTURE behavior OF mips_sys IS
COMPONENT mips_top
Port
(
debug : out unsigned(1 downto 0);
eb : in STD_LOGIC;
nmi : in STD_LOGIC;
cpu_clk : in STD_LOGIC;
RST_I : in STD_LOGIC;
CLK_I : in STD_LOGIC;
ACK_I : in STD_LOGIC;
SRDY_I : in STD_LOGIC;
ADDR_O : out word_t;
DAT_I : in word_t;
DAT_O : out word_t;
WE_O : out STD_LOGIC;
SEL_O : out unsigned(3 downto 0);
CYC_O : out STD_LOGIC;
STB_O : out STD_LOGIC;
MRDY_O : out STD_LOGIC;
INT : in unsigned (5 downto 0)
);
END COMPONENT;
COMPONENT rom_wb
PORT
(
CLK_I : in STD_LOGIC;
RST_I : in STD_LOGIC;
CYC_I : in STD_LOGIC;
STB_I : in STD_LOGIC;
ACK_O : out STD_LOGIC;
MRDY_I : in STD_LOGIC;
SRDY_O : out STD_LOGIC;
ADDR_I : in unsigned(31 downto 0);
DAT_O : out unsigned(31 downto 0)
);
END COMPONENT;
COMPONENT lcd_port
PORT
(
rst : in std_logic;
clk : in std_logic;
we : in std_logic;
din : in unsigned(7 downto 0);
dout : out unsigned(7 downto 0);
lcd_d : inout unsigned(3 downto 0);
lcd_e : out std_logic;
lcd_rs : out std_logic;
lcd_rw : out std_logic
);
END COMPONENT;
COMPONENT async_port_wb
GENERIC
(
f_sysclk : real := sys_freq;
addr_width : natural := 32;
data_width : natural := 32;
byte_sel_width : natural := 4;
async_timespec : async_timespec_t
);
PORT
(
CLK_I : in STD_LOGIC;
RST_I : in STD_LOGIC;
CYC_I : in STD_LOGIC;
STB_I : in STD_LOGIC;
WE_I : in STD_LOGIC;
ACK_O : out STD_LOGIC;
SRDY_O : out STD_LOGIC;
MRDY_I : in STD_LOGIC;
SEL_I : in unsigned(3 downto 0);
ADDR_I : in unsigned(31 downto 0);
DAT_I : in unsigned(31 downto 0);
DAT_O : out unsigned(31 downto 0);
page_mode_en : in STD_LOGIC;
async_a : out unsigned(addr_width-1 downto 0);
async_d : inout unsigned(data_width-1 downto 0);
async_cs : out std_logic;
async_wr : out std_logic;
async_rd : out std_logic;
async_be : out unsigned(byte_sel_width-1 downto 0);
async_rst : out std_logic
);
END COMPONENT;
COMPONENT flash_port_wb
GENERIC
(
f_sysclk : real := sys_freq;
addr_width : natural := 32;
data_width : natural := 32;
async_timespec : async_timespec_t
);
PORT
(
CLK_I : in STD_LOGIC;
RST_I : in STD_LOGIC;
CYC_I : in STD_LOGIC;
STB_I : in STD_LOGIC;
WE_I : in STD_LOGIC;
ACK_O : out STD_LOGIC;
SRDY_O : out STD_LOGIC;
MRDY_I : in STD_LOGIC;
ADDR_I : in unsigned(31 downto 0);
DAT_I : in unsigned(31 downto 0);
DAT_O : out unsigned(31 downto 0);
port_bsyo : out std_logic;
port_bsyi : in std_logic;
port_a : out unsigned(addr_width-1 downto 0);
port_di : in unsigned(data_width-1 downto 0);
port_do : out unsigned(data_width-1 downto 0);
port_d_drv : out STD_LOGIC;
port_wr : out STD_LOGIC;
port_rd : out STD_LOGIC;
flash_cs : out std_logic;
flash_rst : out std_logic
);
END COMPONENT;
COMPONENT uart_wb
PORT
(
CLK_I : in STD_LOGIC;
RST_I : in STD_LOGIC;
CYC_I : in STD_LOGIC;
STB_I : in STD_LOGIC;
SEL_I : in unsigned(3 downto 0);
WE_I : in STD_LOGIC;
ACK_O : out STD_LOGIC;
SRDY_O : out STD_LOGIC;
MRDY_I : in STD_LOGIC;
ADDR_I : in unsigned(31 downto 0);
DAT_I : in unsigned(31 downto 0);
DAT_O : out unsigned(31 downto 0);
INT_O : out STD_LOGIC;
ser_rx : in std_logic;
ser_tx : out std_logic
);
END COMPONENT;
COMPONENT gpio_wb
Generic
(
f_sysclk : real := sys_freq
);
PORT
(
CLK_I : in STD_LOGIC;
RST_I : in STD_LOGIC;
CYC_I : in STD_LOGIC;
STB_I : in STD_LOGIC;
SEL_I : in unsigned(3 downto 0);
WE_I : in STD_LOGIC;
ACK_O : out STD_LOGIC;
SRDY_O : out STD_LOGIC;
MRDY_I : in STD_LOGIC;
ADDR_I : in unsigned(31 downto 0);
DAT_I : in unsigned(31 downto 0);
DAT_O : out unsigned(31 downto 0);
INT_TIM_O : out STD_LOGIC;
sys_gpo0 : out unsigned(31 downto 0);
sys_gpo1 : out unsigned(31 downto 0);
sys_gpi0 : in unsigned(31 downto 0);
sys_gpi1 : in unsigned(31 downto 0)
);
END COMPONENT;
COMPONENT vga_frontend64
GENERIC
(
fifo_depth : integer;
fifo_almost_full_thresh : natural;
fifo_almost_empty_thresh : natural;
tsvga : vga_timespec_t
);
PORT
(
-- System signals
RST_I : in STD_LOGIC;
CLK_I : in STD_LOGIC;
-- JBUS Master signals
CYC_O : out STD_LOGIC;
STB_O : out STD_LOGIC;
WE_O : out STD_LOGIC;
SEL_O : out unsigned(7 downto 0);
ACK_I : in STD_LOGIC;
SRDY_I : in STD_LOGIC;
MRDY_O : out STD_LOGIC;
ADDR_O : out unsigned(31 downto 0);
MDAT_I : in unsigned(63 downto 0);
MDAT_O : out unsigned(63 downto 0);
-- JBUS Slave signals
CYC_I : in STD_LOGIC;
STB_I : in STD_LOGIC;
WE_I : in STD_LOGIC;
SEL_I : in unsigned(3 downto 0);
ACK_O : out STD_LOGIC;
SRDY_O : out STD_LOGIC;
MRDY_I : in STD_LOGIC;
ADDR_I : in unsigned(31 downto 0);
SDAT_I : in unsigned(31 downto 0);
SDAT_O : out unsigned(31 downto 0);
-- VGA signals
vga_clk_in : in std_logic;
vga_clk_ce : in std_logic;
vga_red : out unsigned(7 downto 0);
vga_green : out unsigned(7 downto 0);
vga_blue : out unsigned(7 downto 0);
vga_blank_n : out std_logic;
vga_sync_n : out std_logic;
vga_hsync : out std_logic;
vga_vsync : out std_logic
);
END COMPONENT;
signal cpu_clk : std_logic; signal cpu_clk : std_logic;
signal nmi : std_logic; signal nmi : std_logic;
signal eb : std_logic; signal eb : std_logic;
@@ -509,10 +304,18 @@ ARCHITECTURE behavior OF mips_sys IS
signal SRDY_O_ps2 : std_logic; signal SRDY_O_ps2 : std_logic;
signal SDAT_O_ps2 : unsigned(31 downto 0); signal SDAT_O_ps2 : unsigned(31 downto 0);
signal gpo0 : unsigned(31 downto 0); signal INT_O_emac : std_logic;
signal gpo1 : unsigned(31 downto 0); signal CYC_I_emac : std_logic;
signal gpi0 : unsigned(31 downto 0); signal ACK_O_emac : std_logic;
signal gpi1 : unsigned(31 downto 0); signal SRDY_O_emac : std_logic;
signal SDAT_O_emac : unsigned(31 downto 0);
signal gpi_0 : unsigned(31 downto 0);
signal gpo_0 : unsigned(31 downto 0);
signal ac97_inten : std_logic;
signal usb_inten : std_logic;
signal phy_inten : std_logic;
signal debug : unsigned(1 downto 0); signal debug : unsigned(1 downto 0);
@@ -526,28 +329,51 @@ ARCHITECTURE behavior OF mips_sys IS
-- attribute rom_style of cpu_cpu_write_fifo_dout: signal is "DISTRIBUTED"; -- attribute rom_style of cpu_cpu_write_fifo_dout: signal is "DISTRIBUTED";
-- attribute rom_style of cpu_read_fifo_dout: signal is "DISTRIBUTED"; -- attribute rom_style of cpu_read_fifo_dout: signal is "DISTRIBUTED";
type mem_area_t is (mem_dead, mem_flash, mem_ssram, mem_usb, mem_rom, mem_gpio, mem_uart0, mem_uart1, mem_uart2, mem_uart, mem_sdram, mem_vga, mem_ac97); type mem_area_t is (mem_dead, mem_flash, mem_ssram, mem_usb, mem_rom, mem_gpio, mem_uart0, mem_uart1, mem_uart2, mem_uart, mem_sdram, mem_vga, mem_ac97, mem_emac);
signal mem_area : mem_area_t; signal mem_area : mem_area_t;
BEGIN BEGIN
eb <= sys_dip(7); ------------------------------------
gpi0(4 downto 0) <= sys_btn; -- GPIO_0 bits used for
gpi1(7 downto 0) <= sys_dip; -- 8.. 0 = O: LED 8..0
sys_led <= gpo0(8 downto 0); -- 11.. 9 = free
sys_error <= debug; -- 12 = O: USB RST
nmi <= not sys_rst_n_in; -- 13 = O: USB INTEN
rst_in <= not sys_rst_n_in and sys_btn(0) and sys_btn(2); -- 14 = free
sys_usb_rstn <= not gpo1(0); -- 15 = O: AC97 INTEN
sys_flash_byten <= '1'; -- 32..16 = I: DIP 7..0
ADDR_I_usb <= X"0000000" & "00" & ADDR_O(3 downto 2); -- 28..24 = I: BTN 4..0
ADDR_I_ssram <= ("0000000000000" & ADDR_O(19 downto 2)) & '0'; -- 29 = O: PHY RESET
-- 30 = O: PHY MDC
-- 31 = IO: PHY MDIO
------------------------------------
gpi_0(28 downto 24) <= sys_btn;
gpi_0(23 downto 16) <= sys_dip;
gpi_0(31) <= sys_phy_mdio;
sys_led <= gpo_0(8 downto 0);
sys_usb_rstn <= not gpo_0(12);
usb_inten <= gpo_0(13);
phy_inten <= gpo_0(14);
ac97_inten <= gpo_0(15);
sys_phy_rstn <= not gpo_0(29);
sys_phy_mdc <= gpo_0(30);
sys_phy_mdio <= gpo_0(31);
SDAT_I_sdram <= MDAT_O & MDAT_O; eb <= sys_dip(7);
SEL_I_sdram <= "0000" & SEL_O; sys_error <= debug;
nmi <= not sys_rst_n_in;
rst_in <= not sys_rst_n_in and sys_btn(0) and sys_btn(2);
sys_flash_byten <= '1';
ADDR_I_usb <= X"0000000" & "00" & ADDR_O(3 downto 2);
ADDR_I_ssram <= ("0000000000000" & ADDR_O(19 downto 2)) & '0';
sys_flash_ac97_rstn <= ac97_rstn and flash_rstn; SDAT_I_sdram <= MDAT_O & MDAT_O;
vga_ce <= not RST_O; SEL_I_sdram <= "0000" & SEL_O;
sys_flash_ac97_rstn <= ac97_rstn and flash_rstn;
vga_ce <= not RST_O;
sys_flash_ssram_out: sys_flash_ssram_out:
process(CLK_O) process(CLK_O)
@@ -617,7 +443,7 @@ int_sample:
process(CLK_O) process(CLK_O)
begin begin
if rising_edge(CLK_O) then if rising_edge(CLK_O) then
INT <= int_timer & '0' & (gpo1(2) and INT_O_ac97) & (gpo1(1) and sys_usb_int) & (int_uart0 or int_uart1 or int_uart2) & sys_btn(4); INT <= int_timer & (INT_O_ps2 or INT_O_emac) & (ac97_inten and INT_O_ac97) & (usb_inten and sys_usb_int) & (int_uart0 or int_uart1 or int_uart2) & sys_btn(4);
end if; end if;
end process; end process;
@@ -647,6 +473,8 @@ mem_mux:
mem_area <= mem_vga; mem_area <= mem_vga;
elsif ADDR_O(18 downto 16) = "100" then elsif ADDR_O(18 downto 16) = "100" then
mem_area <= mem_ac97; mem_area <= mem_ac97;
elsif ADDR_O(18 downto 16) = "101" then
mem_area <= mem_emac;
end if; end if;
elsif ADDR_O(27 downto 26) = "01" then elsif ADDR_O(27 downto 26) = "01" then
mem_area <= mem_flash; mem_area <= mem_flash;
@@ -655,8 +483,6 @@ mem_mux:
end if; end if;
elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '0') then elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '0') then
mem_area <= mem_rom; mem_area <= mem_rom;
-- elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '1') then
-- kernel sram
elsif (ADDR_O(31 downto 28) = X"8" or ADDR_O(30) = '1') then elsif (ADDR_O(31 downto 28) = X"8" or ADDR_O(30) = '1') then
mem_area <= mem_sdram; mem_area <= mem_sdram;
end if; end if;
@@ -677,6 +503,7 @@ signal_mux:
CYC_I_vga <= '0'; CYC_I_vga <= '0';
CYC_I_ssram <= '0'; CYC_I_ssram <= '0';
CYC_I_ac97 <= '0'; CYC_I_ac97 <= '0';
CYC_I_emac <= '0';
case mem_area is case mem_area is
@@ -710,6 +537,9 @@ signal_mux:
when mem_ac97 => when mem_ac97 =>
CYC_I_ac97 <= CYC_O; CYC_I_ac97 <= CYC_O;
when mem_emac =>
CYC_I_emac <= CYC_O;
when mem_ssram => when mem_ssram =>
CYC_I_ssram <= CYC_O; CYC_I_ssram <= CYC_O;
@@ -720,8 +550,8 @@ signal_mux:
end process; end process;
------------------------------------------------------------------ ------------------------------------------------------------------
SRDY_I <= SRDY_O_flash or SRDY_O_ssram or SRDY_O_usb or SRDY_O_sdram or SRDY_O_rom or SRDY_O_uart0 or SRDY_O_uart1 or SRDY_O_uart2 or SRDY_O_gpio or SRDY_O_vga or SRDY_O_ac97; SRDY_I <= SRDY_O_flash or SRDY_O_ssram or SRDY_O_usb or SRDY_O_sdram or SRDY_O_rom or SRDY_O_uart0 or SRDY_O_uart1 or SRDY_O_uart2 or SRDY_O_gpio or SRDY_O_vga or SRDY_O_ac97 or SRDY_O_emac;
ACK_I <= ACK_O_flash or ACK_O_usb or ACK_O_sdram or ACK_O_ssram or ACK_O_rom or ACK_O_uart0 or ACK_O_uart1 or ACK_O_uart2 or ACK_O_gpio or ACK_O_vga or ACK_O_ac97; ACK_I <= ACK_O_flash or ACK_O_usb or ACK_O_sdram or ACK_O_ssram or ACK_O_rom or ACK_O_uart0 or ACK_O_uart1 or ACK_O_uart2 or ACK_O_gpio or ACK_O_vga or ACK_O_ac97 or ACK_O_emac;
MDAT_I <= SDAT_O_ssram when CYC_I_ssram = '1' else MDAT_I <= SDAT_O_ssram when CYC_I_ssram = '1' else
SDAT_O_sdram(31 downto 0) when CYC_I_sdram = '1' else SDAT_O_sdram(31 downto 0) when CYC_I_sdram = '1' else
SDAT_O_rom when CYC_I_rom = '1' else SDAT_O_rom when CYC_I_rom = '1' else
@@ -732,10 +562,11 @@ signal_mux:
SDAT_O_uart2 when CYC_I_uart2 = '1' else SDAT_O_uart2 when CYC_I_uart2 = '1' else
SDAT_O_vga when CYC_I_vga = '1' else SDAT_O_vga when CYC_I_vga = '1' else
SDAT_O_ac97 when CYC_I_ac97 = '1' else SDAT_O_ac97 when CYC_I_ac97 = '1' else
SDAT_O_emac when CYC_I_emac = '1' else
SDAT_O_gpio when CYC_I_gpio = '1' else X"DEADBEEF"; SDAT_O_gpio when CYC_I_gpio = '1' else X"DEADBEEF";
------------------------------------------------------------------ ------------------------------------------------------------------
inst_mips_top: mips_top inst_mips_top: entity work.mips_top
PORT MAP PORT MAP
( (
debug => debug, debug => debug,
@@ -757,7 +588,7 @@ inst_mips_top: mips_top
INT => INT INT => INT
); );
inst_rom_wb : rom_wb inst_rom_wb : entity work.rom_wb
PORT MAP PORT MAP
( (
CLK_I => CLK_O, CLK_I => CLK_O,
@@ -772,7 +603,7 @@ inst_rom_wb : rom_wb
); );
inst_lcd_port: lcd_port inst_lcd_port: entity work.lcd_port
PORT MAP PORT MAP
( (
clk => CLK_O, clk => CLK_O,
@@ -786,7 +617,7 @@ inst_lcd_port: lcd_port
lcd_rw => sys_lcd_rw lcd_rw => sys_lcd_rw
); );
inst_gpio_wb : gpio_wb inst_gpio_wb : entity work.gpio_wb
GENERIC MAP GENERIC MAP
( (
f_sysclk => sys_freq f_sysclk => sys_freq
@@ -807,13 +638,11 @@ inst_gpio_wb : gpio_wb
DAT_O => SDAT_O_gpio, DAT_O => SDAT_O_gpio,
INT_TIM_O => int_timer, INT_TIM_O => int_timer,
sys_gpo0 => gpo0, sys_gpi_0 => gpi_0,
sys_gpo1 => gpo1, sys_gpo_0 => gpo_0
sys_gpi0 => gpi0,
sys_gpi1 => gpi1
); );
inst_flash_port : flash_port_wb inst_flash_port : entity work.flash_port_wb
GENERIC MAP GENERIC MAP
( (
f_sysclk => sys_freq, f_sysclk => sys_freq,
@@ -846,7 +675,7 @@ inst_flash_port : flash_port_wb
flash_rst => flash_rstn flash_rst => flash_rstn
); );
inst_usb_port : async_port_wb inst_usb_port : entity work.async_port_wb
GENERIC MAP GENERIC MAP
( (
f_sysclk => sys_freq, f_sysclk => sys_freq,
@@ -879,7 +708,11 @@ inst_usb_port : async_port_wb
async_rst => open async_rst => open
); );
inst_uart_wb_0 : uart_wb inst_uart_wb_0 : entity work.uart_wb
GENERIC MAP
(
simulate_tx => true
)
PORT MAP PORT MAP
( (
CLK_I => CLK_O, CLK_I => CLK_O,
@@ -899,7 +732,11 @@ inst_uart_wb_0 : uart_wb
ser_tx => sys_uart0_tx ser_tx => sys_uart0_tx
); );
inst_uart_wb_1 : uart_wb inst_uart_wb_1 : entity work.uart_wb
GENERIC MAP
(
simulate_tx => true
)
PORT MAP PORT MAP
( (
CLK_I => CLK_O, CLK_I => CLK_O,
@@ -919,7 +756,11 @@ inst_uart_wb_1 : uart_wb
ser_tx => sys_uart1_tx ser_tx => sys_uart1_tx
); );
inst_uart_wb_2 : uart_wb inst_uart_wb_2 : entity work.uart_wb
GENERIC MAP
(
simulate_tx => true
)
PORT MAP PORT MAP
( (
CLK_I => CLK_O, CLK_I => CLK_O,
@@ -1051,7 +892,7 @@ inst_sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend64_wb
); );
inst_vga_frontend : vga_frontend64 inst_vga_frontend : entity work.vga_frontend64
GENERIC MAP GENERIC MAP
( (
fifo_depth => 2048, fifo_depth => 2048,
@@ -1169,6 +1010,36 @@ inst_ps2_phy: entity work.ps2_phy
tx_data => ps2_data_tx tx_data => ps2_data_tx
); );
inst_emac_jb : entity work.emac_top_jb
PORT MAP
(
CLK_I => CLK_O,
RST_I => RST_O,
INT_O => INT_O_emac,
CYC_I => CYC_I_emac,
STB_I => STB_O,
SEL_I => SEL_O,
WE_I => WE_O,
ACK_O => ACK_O_emac,
SRDY_O => SRDY_O_emac,
MRDY_I => MRDY_O,
ADDR_I => ADDR_O,
DAT_I => MDAT_O,
DAT_O => SDAT_O_emac,
mii_rx_clk => sys_phy_rx_clk,
mii_rx_dv => sys_phy_rx_dv,
mii_rx_er => sys_phy_rx_er,
mii_rx => sys_phy_rx,
mii_tx_clk => sys_phy_tx_clk,
mii_tx_en => sys_phy_tx_en,
mii_tx_er => sys_phy_tx_er,
mii_tx => sys_phy_tx,
mii_gtx_clk => sys_phy_gtx_clk,
mii_crs => sys_phy_crs,
mii_col => sys_phy_col
);
------------------------------------------------------------------ ------------------------------------------------------------------
END; END;
projects/mips_sys/src/tb_mips_sys.vhd
+57 -5
View File
@@ -40,6 +40,7 @@ ARCHITECTURE behavior OF tb_mips_sys IS
constant CLK_PERIOD : time := 10 ns; constant CLK_PERIOD : time := 10 ns;
constant AC97_CLK_PERIOD : time := 83 ns; constant AC97_CLK_PERIOD : time := 83 ns;
constant ETH_CLK_PERIOD : time := 40.7 ns;
signal sys_rst_n_in : std_logic := '0'; signal sys_rst_n_in : std_logic := '0';
signal sys_clk_in : std_logic := '1'; signal sys_clk_in : std_logic := '1';
signal dip : unsigned(7 downto 0) := (others => '0'); signal dip : unsigned(7 downto 0) := (others => '0');
@@ -107,11 +108,29 @@ ARCHITECTURE behavior OF tb_mips_sys IS
SIGNAL sys_ac97_ssync : std_logic; SIGNAL sys_ac97_ssync : std_logic;
SIGNAL sys_ac97_sdata_in : std_logic; SIGNAL sys_ac97_sdata_in : std_logic;
SIGNAL sys_ps2_clk : std_logic := 'Z'; SIGNAL sys_ps2_clk : std_logic := 'H';
SIGNAL sys_ps2_data : std_logic := 'Z'; SIGNAL sys_ps2_data : std_logic := 'H';
SIGNAL sys_phy_rstn : std_logic;
SIGNAL sys_phy_mdc : std_logic;
SIGNAL sys_phy_mdio : std_logic := 'H';
SIGNAL sys_phy_int : std_logic := '0';
SIGNAL sys_phy_rx_clk : STD_LOGIC := '0';
SIGNAL sys_phy_rx_dv : STD_LOGIC := '0';
SIGNAL sys_phy_rx_er : STD_LOGIC := '0';
SIGNAL sys_phy_rx : unsigned(7 downto 0) := (others => '0');
SIGNAL sys_phy_tx_clk : STD_LOGIC := '0';
SIGNAL sys_phy_tx_en : STD_LOGIC;
SIGNAL sys_phy_tx_er : STD_LOGIC;
SIGNAL sys_phy_tx : unsigned(7 downto 0);
SIGNAL sys_phy_gtx_clk : STD_LOGIC;
SIGNAL sys_phy_crs : STD_LOGIC := '0';
SIGNAL sys_phy_col : STD_LOGIC := '0';
signal flash_reg : word_t; signal flash_reg : word_t;
signal eth_tx_reg : unsigned(7 downto 0);
type flash_data_t is array (natural range 0 to 2**16-1) of word_t; type flash_data_t is array (natural range 0 to 2**16-1) of word_t;
signal flash_data : flash_data_t; signal flash_data : flash_data_t;
@@ -197,6 +216,23 @@ uut: entity work.mips_sys
sys_ps2_clk => sys_ps2_clk, sys_ps2_clk => sys_ps2_clk,
sys_ps2_data => sys_ps2_data, sys_ps2_data => sys_ps2_data,
sys_phy_rstn => sys_phy_rstn,
sys_phy_mdc => sys_phy_mdc,
sys_phy_mdio => sys_phy_mdio,
sys_phy_int => sys_phy_int,
sys_phy_rx_clk => sys_phy_rx_clk,
sys_phy_rx_dv => sys_phy_rx_dv,
sys_phy_rx_er => sys_phy_rx_er,
sys_phy_rx => sys_phy_rx,
sys_phy_tx_clk => sys_phy_tx_clk,
sys_phy_tx_en => sys_phy_tx_en,
sys_phy_tx_er => sys_phy_tx_er,
sys_phy_tx => sys_phy_tx,
sys_phy_gtx_clk => sys_phy_gtx_clk,
sys_phy_crs => sys_phy_crs,
sys_phy_col => sys_phy_col,
sys_error => sys_error sys_error => sys_error
); );
@@ -270,6 +306,22 @@ CLK_GEN: process
sys_clk_in <= not sys_clk_in; sys_clk_in <= not sys_clk_in;
end process; end process;
ETH_CLK_GEN: process
begin
wait for ETH_CLK_PERIOD/2;
sys_phy_rx_clk <= not sys_phy_rx_clk;
sys_phy_tx_clk <= not sys_phy_tx_clk;
end process;
ETH_TX_REGISTER:
PROCESS(sys_phy_tx_clk)
begin
if rising_edge(sys_phy_tx_clk) then
if (sys_phy_tx_en = '1') then
eth_tx_reg <= sys_phy_tx;
end if;
end if;
end process;
sys_ac97_sdata_in <= ac_frame_reg(ac_frame_reg'left); --sys_ac97_sdata_out; sys_ac97_sdata_in <= ac_frame_reg(ac_frame_reg'left); --sys_ac97_sdata_out;
@@ -306,7 +358,7 @@ ac97_clk_gen : PROCESS
FLASH_READ: process(sys_rst_n_in, sys_flash_ce, sys_flash_ssram_oe_n, sys_flash_ssram_a) FLASH_READ: process(sys_rst_n_in, sys_flash_ce, sys_flash_ssram_oe_n, sys_flash_ssram_a)
type file_t is file of integer; type file_t is file of integer;
file load_flash : file_t open read_mode is "dhry.elf.flash.bin"; file load_flash : file_t open read_mode is "test_emac_sim.elf.flash.bin";
variable instr : integer; variable instr : integer;
variable index : natural; variable index : natural;
variable temp : signed(31 downto 0); variable temp : signed(31 downto 0);
@@ -346,7 +398,7 @@ STIMULUS: process
sys_rst_n_in <= '1'; sys_rst_n_in <= '1';
btn(0) <= '0'; btn(0) <= '0';
btn(2) <= '0'; btn(2) <= '0';
wait for 200000*CLK_PERIOD; wait for 20000000*CLK_PERIOD;
loop loop
wait for 251*CLK_PERIOD; wait for 251*CLK_PERIOD;