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- added ethernet MAC

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git-svn-id: http://moon:8086/svn/vhdl/trunk@850 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2010-03-30 10:22:46 +00:00
parent 25b57a30fe
commit bd90e641cf
2 changed files with 189 additions and 266 deletions
Download Patch File Download Diff File Expand all files Collapse all files
projects/mips_sys/src/tb_mips_sys.vhd
+57 -5
View File
@@ -40,6 +40,7 @@ ARCHITECTURE behavior OF tb_mips_sys IS
constant CLK_PERIOD : time := 10 ns;
constant AC97_CLK_PERIOD : time := 83 ns;
constant ETH_CLK_PERIOD : time := 40.7 ns;
signal sys_rst_n_in : std_logic := '0';
signal sys_clk_in : std_logic := '1';
signal dip : unsigned(7 downto 0) := (others => '0');
@@ -107,11 +108,29 @@ ARCHITECTURE behavior OF tb_mips_sys IS
SIGNAL sys_ac97_ssync : std_logic;
SIGNAL sys_ac97_sdata_in : std_logic;
SIGNAL sys_ps2_clk : std_logic := 'Z';
SIGNAL sys_ps2_data : std_logic := 'Z';
SIGNAL sys_ps2_clk : std_logic := 'H';
SIGNAL sys_ps2_data : std_logic := 'H';
SIGNAL sys_phy_rstn : std_logic;
SIGNAL sys_phy_mdc : std_logic;
SIGNAL sys_phy_mdio : std_logic := 'H';
SIGNAL sys_phy_int : std_logic := '0';
SIGNAL sys_phy_rx_clk : STD_LOGIC := '0';
SIGNAL sys_phy_rx_dv : STD_LOGIC := '0';
SIGNAL sys_phy_rx_er : STD_LOGIC := '0';
SIGNAL sys_phy_rx : unsigned(7 downto 0) := (others => '0');
SIGNAL sys_phy_tx_clk : STD_LOGIC := '0';
SIGNAL sys_phy_tx_en : STD_LOGIC;
SIGNAL sys_phy_tx_er : STD_LOGIC;
SIGNAL sys_phy_tx : unsigned(7 downto 0);
SIGNAL sys_phy_gtx_clk : STD_LOGIC;
SIGNAL sys_phy_crs : STD_LOGIC := '0';
SIGNAL sys_phy_col : STD_LOGIC := '0';
signal flash_reg : word_t;
signal eth_tx_reg : unsigned(7 downto 0);
type flash_data_t is array (natural range 0 to 2**16-1) of word_t;
signal flash_data : flash_data_t;
@@ -197,6 +216,23 @@ uut: entity work.mips_sys
sys_ps2_clk => sys_ps2_clk,
sys_ps2_data => sys_ps2_data,
sys_phy_rstn => sys_phy_rstn,
sys_phy_mdc => sys_phy_mdc,
sys_phy_mdio => sys_phy_mdio,
sys_phy_int => sys_phy_int,
sys_phy_rx_clk => sys_phy_rx_clk,
sys_phy_rx_dv => sys_phy_rx_dv,
sys_phy_rx_er => sys_phy_rx_er,
sys_phy_rx => sys_phy_rx,
sys_phy_tx_clk => sys_phy_tx_clk,
sys_phy_tx_en => sys_phy_tx_en,
sys_phy_tx_er => sys_phy_tx_er,
sys_phy_tx => sys_phy_tx,
sys_phy_gtx_clk => sys_phy_gtx_clk,
sys_phy_crs => sys_phy_crs,
sys_phy_col => sys_phy_col,
sys_error => sys_error
);
@@ -270,6 +306,22 @@ CLK_GEN: process
sys_clk_in <= not sys_clk_in;
end process;
ETH_CLK_GEN: process
begin
wait for ETH_CLK_PERIOD/2;
sys_phy_rx_clk <= not sys_phy_rx_clk;
sys_phy_tx_clk <= not sys_phy_tx_clk;
end process;
ETH_TX_REGISTER:
PROCESS(sys_phy_tx_clk)
begin
if rising_edge(sys_phy_tx_clk) then
if (sys_phy_tx_en = '1') then
eth_tx_reg <= sys_phy_tx;
end if;
end if;
end process;
sys_ac97_sdata_in <= ac_frame_reg(ac_frame_reg'left); --sys_ac97_sdata_out;
@@ -306,7 +358,7 @@ ac97_clk_gen : PROCESS
FLASH_READ: process(sys_rst_n_in, sys_flash_ce, sys_flash_ssram_oe_n, sys_flash_ssram_a)
type file_t is file of integer;
file load_flash : file_t open read_mode is "dhry.elf.flash.bin";
file load_flash : file_t open read_mode is "test_emac_sim.elf.flash.bin";
variable instr : integer;
variable index : natural;
variable temp : signed(31 downto 0);
@@ -346,7 +398,7 @@ STIMULUS: process
sys_rst_n_in <= '1';
btn(0) <= '0';
btn(2) <= '0';
wait for 200000*CLK_PERIOD;
wait for 20000000*CLK_PERIOD;
loop
wait for 251*CLK_PERIOD;