- adedd single data rate SDRAM

git-svn-id: http://moon:8086/svn/vhdl/trunk@1211 cc03376c-175c-47c8-b038-4cd826a8556b
2015-05-24 12:54:57 +00:00
parent fa8fadd8cc
commit bd65d611dd
9 changed files with 3136 additions and 0 deletions
@@ -0,0 +1,32 @@
+## NOTE:  Do not edit this file.
+##
+if {[file exists work]} {vdel -lib work -all}
+
+vlib work
+vcom -explicit  -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
+vcom -explicit  -93 "../../../rams/dpram_1w1r2c_ra_sim.vhd"
+vcom -explicit  -93 "../../../FIFO/src/gray_counter.vhd"
+vcom -explicit  -93 "../../../FIFO/src/fifo_async_ctrl.vhd"
+vcom -explicit  -93 "../../../FIFO/src/fifo_async.vhd"
+vcom -explicit  -93 "../../../FIFO/src/fifo_sync_ctrl.vhd"
+vcom -explicit  -93 "../../../FIFO/src/fifo_sync.vhd"
+vcom -explicit  -93 "../../../misc/utils_pkg.vhd"
+vcom -explicit  -93 "../src/sdram_config_mt48lc16m16.vhd"
+vcom -explicit  -93 "../src/sdram_types.vhd"
+vcom -explicit  -93 "../src/sdram_cmd.vhd"
+vcom -explicit  -93 "../src/sdram_ctrl.vhd"
+vcom -explicit  -93 "../src/ddr_clk_virtex4.vhd"
+vcom -explicit  -93 "../src/sdr_phy_virtex4.vhd"
+vcom -explicit  -93 "../src/sdram_ctrl_top.vhd"
+vcom -explicit  -93 "../src/sdram_ctrl_frontend_wb16.vhd"
+vcom -explicit  -93 "../src/ctrl_sdr_wb32.vhd"
+vcom -explicit  -93 "../src/mti_pkg.vhd"
+vcom -explicit  -93 "../src/mt48lc16m16a2.vhd"
+vcom -explicit  -93 "../src/tb_ctrl_sdr_wb32.vhd"
+
+vsim -t 1ps   -lib work tb_ctrl_sdr_wb32
+do {tb_ctrl_sdr_wb32.wdo}
+view wave
+view structure
+view signals
+run 200us
@@ -0,0 +1,82 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -divider J-Bus
+add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/clk_o
+add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/rst_o
+add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/cyc_o
+add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/stb_o
+add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/we_o
+add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/sel_o
+add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/ack_i
+add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/mrdy_o
+add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/srdy_i
+add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_sdr_wb32/addr_o
+add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_sdr_wb32/dat_i
+add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_sdr_wb32/dat_o
+add wave -noupdate -divider SDRAM
+add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/sdclk
+add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/sdclk_fb
+add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/part_clk
+add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/part_cke
+add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/part_cs_n
+add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/part_we_n
+add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/part_ras_n
+add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/part_cas_n
+add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/part_ba
+add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/part_dqm
+add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_sdr_wb32/part_addr
+add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_sdr_wb32/part_data
+add wave -noupdate -divider PHY
+add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/f_sdrclk
+add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/rst
+add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/clk
+add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/clk_fb
+add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/clk0_out
+add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/rst0_out
+add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/phy_in
+add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/phy_out
+add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/phy_ctrl
+add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/part_clk
+add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/part_dqm
+add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/part_data
+add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/part_ba
+add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/part_addr
+add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/part_cs_n
+add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/part_we_n
+add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/part_cas_n
+add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/part_ras_n
+add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/part_cke
+add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/drive
+add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/data_reg_r
+add wave -noupdate -format Literal -expand /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/part_ctrl_reg
+add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/we_reg
+add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/read_en
+add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/clk0
+add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/clk0_s
+add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/rst0
+add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/clk_rd
+add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/clk_wr
+add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/locked
+add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/error
+add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/u_tag_pipe
+add wave -noupdate -divider Test
+add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/dout_rst
+add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_sdr_wb32/dout_reg
+add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/dout_cnt
+add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/sd_cmd
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {3554765 ps} 0}
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+update
+WaveRestoreZoom {0 ps} {210 us}