From bce7ba16b772402c19513337a5411ad3fae56950 Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Sun, 11 Jan 2009 15:44:07 +0000 Subject: [PATCH] - Uses decimating CFIR (decimate by 2) git-svn-id: http://moon:8086/svn/vhdl/trunk@226 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/radio/ddc/src/ddc.vhd | 77 +++++++++++++++++++++++------------- lib/radio/ddc/src/tb_ddc.vhd | 18 ++++----- 2 files changed, 59 insertions(+), 36 deletions(-) diff --git a/lib/radio/ddc/src/ddc.vhd b/lib/radio/ddc/src/ddc.vhd index 73b8ac0..959f213 100644 --- a/lib/radio/ddc/src/ddc.vhd +++ b/lib/radio/ddc/src/ddc.vhd @@ -111,6 +111,29 @@ ARCHITECTURE behavior OF ddc IS ); END COMPONENT; + COMPONENT fifo_sync + GENERIC + ( + addr_width : natural; + data_width : natural; + almost_full_thresh : integer; + almost_empty_thresh : integer + ); + PORT + ( + rst : in STD_LOGIC; + clk : in STD_LOGIC; + we : in STD_LOGIC; + re : in STD_LOGIC; + fifo_full : out STD_LOGIC; + fifo_empty : out STD_LOGIC; + fifo_afull : out STD_LOGIC; + fifo_aempty : out STD_LOGIC; + data_w : in unsigned (data_width-1 downto 0); + data_r : out unsigned (data_width-1 downto 0) + ); + END COMPONENT; + COMPONENT fir_semi_parallel GENERIC ( @@ -161,6 +184,15 @@ ARCHITECTURE behavior OF ddc IS constant cfir_ntaps_per_stage : integer := NextPowerOfTwo(cfir_ntaps)/cfir_nstages; + SIGNAL mix_dout_i : sfixed(shi(lo_nbits_out, lo_nbits_out_frac) downto slo(lo_nbits_out, lo_nbits_out_frac)); + SIGNAL mix_dout_q : sfixed(shi(lo_nbits_out, lo_nbits_out_frac) downto slo(lo_nbits_out, lo_nbits_out_frac)); + SIGNAL mix_dout_vld : std_logic; + + SIGNAL dec_dout_i : sfixed(shi(cic_nbits_out, cic_nbits_out_frac) downto slo(cic_nbits_out, cic_nbits_out_frac)); + SIGNAL dec_dout_q : sfixed(shi(cic_nbits_out, cic_nbits_out_frac) downto slo(cic_nbits_out, cic_nbits_out_frac)); + SIGNAL dec_dout_vld_i : std_logic; + SIGNAL dec_dout_vld_q : std_logic; + SIGNAL cfir_h_data : sfixed(shi(cfir_nbits_stages, cfir_nbits_stages_frac) downto slo(cfir_nbits_stages, cfir_nbits_stages_frac)); SIGNAL cfir_h_addr : natural range 0 to NextPowerOfTwo(cfir_ntaps)-1; SIGNAL cfir_dout_i : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac)); @@ -205,15 +237,6 @@ ARCHITECTURE behavior OF ddc IS SIGNAL hclr_mode : std_logic; CONSTANT h_mem : h_mem_t := to_h_mem(cfir_coef, cfir_ntaps, cfir_h_data); - SIGNAL mix_dout_i : sfixed(shi(lo_nbits_out, lo_nbits_out_frac) downto slo(lo_nbits_out, lo_nbits_out_frac)); - SIGNAL mix_dout_q : sfixed(shi(lo_nbits_out, lo_nbits_out_frac) downto slo(lo_nbits_out, lo_nbits_out_frac)); - SIGNAL mix_dout_vld : std_logic; - - SIGNAL dec_dout_i : sfixed(shi(cic_nbits_out, cic_nbits_out_frac) downto slo(cic_nbits_out, cic_nbits_out_frac)); - SIGNAL dec_dout_q : sfixed(shi(cic_nbits_out, cic_nbits_out_frac) downto slo(cic_nbits_out, cic_nbits_out_frac)); - SIGNAL dec_dout_vld_i : std_logic; - SIGNAL dec_dout_vld_q : std_logic; - BEGIN -- assert false report "cfir_h_addr_i'length = " & natural'image(cfir_h_addr_i'length) & "." severity note; @@ -352,18 +375,18 @@ BEGIN dout => cfir_dout_q ); --- cfir_din_vld_i <= not fifo_empty_i and cfir_ready_i and cfir_write_i; --- cfir_start_i <= fifo_empty_i and cfir_write_i; + cfir_din_vld_i <= not fifo_empty_i and cfir_ready_i and cfir_write_i; + cfir_start_i <= fifo_empty_i and cfir_write_i; --- fifo_din_i <= to_unsigned(ufixed(dec_dout_i)); --- cfir_din_i <= sfixed(fifo_dout_i); + fifo_din_i <= to_unsigned(ufixed(dec_dout_i)); + cfir_din_i <= sfixed(fifo_dout_i); - cfir_din_vld_i <= dec_dout_vld_i; - cfir_start_i <= dec_dout_vld_i; - - cfir_din_i <= dec_dout_i; +-- cfir_din_vld_i <= dec_dout_vld_i; +-- cfir_start_i <= dec_dout_vld_i; +-- +-- cfir_din_i <= dec_dout_i; -inst_fifo_sync_i : entity work.fifo_sync +inst_fifo_sync_i : fifo_sync GENERIC MAP ( addr_width => 1, @@ -385,18 +408,18 @@ inst_fifo_sync_i : entity work.fifo_sync data_r => fifo_dout_i ); --- cfir_din_vld_q <= not fifo_empty_q and cfir_ready_q and cfir_write_q; --- cfir_start_q <= fifo_empty_q and cfir_write_q; + cfir_din_vld_q <= not fifo_empty_q and cfir_ready_q and cfir_write_q; + cfir_start_q <= fifo_empty_q and cfir_write_q; --- fifo_din_q <= to_unsigned(ufixed(dec_dout_q)); --- cfir_din_q <= sfixed(fifo_dout_q); + fifo_din_q <= to_unsigned(ufixed(dec_dout_q)); + cfir_din_q <= sfixed(fifo_dout_q); - cfir_din_vld_q <= dec_dout_vld_q; - cfir_start_q <= dec_dout_vld_q; +-- cfir_din_vld_q <= dec_dout_vld_q; +-- cfir_start_q <= dec_dout_vld_q; +-- +-- cfir_din_q <= dec_dout_q; - cfir_din_q <= dec_dout_q; - -inst_fifo_sync_q : entity work.fifo_sync +inst_fifo_sync_q : fifo_sync GENERIC MAP ( addr_width => 1, diff --git a/lib/radio/ddc/src/tb_ddc.vhd b/lib/radio/ddc/src/tb_ddc.vhd index 7afe05a..37d6fca 100644 --- a/lib/radio/ddc/src/tb_ddc.vhd +++ b/lib/radio/ddc/src/tb_ddc.vhd @@ -31,13 +31,13 @@ ENTITY tb_ddc IS ( nbits_in : integer := 16; nbits_in_frac : integer := 14; - nbits_out : integer := 24; - nbits_out_frac : integer := 22; + nbits_out : integer := 32; + nbits_out_frac : integer := 30; lo_nbits_phase : integer := 20; lo_nbits_freq : integer := 20; - cic_nstages : integer := 3; - cic_ratio : integer := 50; - cic_scale_nbits : integer := 16; + cic_nstages : integer := 5; + cic_ratio : integer := 25; + cic_scale_nbits : integer := 22; rfgen_nbits_phase : integer := 20; rfgen_nbits_freq : integer := 20 ); @@ -109,10 +109,10 @@ ARCHITECTURE behavior OF tb_ddc IS --Constants constant fa : REAL := 100.0E6; - constant frf1 : REAL := 1.99E6; - constant frf2 : REAL := 1.00E6; - constant frf3 : REAL := 1.01E6; - constant flo : REAL := 1.00E6; + constant frf1 : REAL := 33.99E6; + constant frf2 : REAL := 2.1E6; + constant frf3 : REAL := 19.01E6; + constant flo : REAL := 2.00E6; constant PERIOD : time := 10 ns; SIGNAL rfgen1_freq_word : integer := integer(frf1/fa*2.0**rfgen_nbits_freq);