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- minor mods to vld_pipe

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git-svn-id: http://moon:8086/svn/vhdl/trunk@194 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2009-01-03 20:33:42 +00:00
parent d28b2225a7
commit bc4c015150
3 changed files with 22 additions and 20 deletions
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lib/filter/sim/tb_fir_semi_parallel.wdo
+1 -2
View File
@@ -9,7 +9,6 @@ add wave -noupdate -format Logic /tb_fir_semi_parallel/din_vld
add wave -noupdate -format Logic /tb_fir_semi_parallel/dout_vld add wave -noupdate -format Logic /tb_fir_semi_parallel/dout_vld
add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/d_in add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/d_in
add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/d_out add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/d_out
add wave -noupdate -format Literal /tb_fir_semi_parallel/uut/vld_pipe
add wave -noupdate -format Logic /tb_fir_semi_parallel/rdy add wave -noupdate -format Logic /tb_fir_semi_parallel/rdy
add wave -noupdate -divider {Real out} add wave -noupdate -divider {Real out}
add wave -noupdate -format Analog-Step -height 50 -scale 50.0 /tb_fir_semi_parallel/xi add wave -noupdate -format Analog-Step -height 50 -scale 50.0 /tb_fir_semi_parallel/xi
@@ -41,7 +40,7 @@ add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/uut/gen_
add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/uut/gen_stages__1/inst_fir_stage/x_out add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/uut/gen_stages__1/inst_fir_stage/x_out
add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/uut/gen_stages__1/inst_fir_stage/y_out add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/uut/gen_stages__1/inst_fir_stage/y_out
TreeUpdate [SetDefaultTree] TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {126110000 ps} 0} WaveRestoreCursors {{Cursor 1} {256495124 ps} 0}
configure wave -namecolwidth 150 configure wave -namecolwidth 150
configure wave -valuecolwidth 100 configure wave -valuecolwidth 100
configure wave -justifyvalue left configure wave -justifyvalue left
lib/filter/src/fir_semi_parallel.vhd
+1 -1
View File
@@ -97,7 +97,7 @@ architecture Behavioral of fir_semi_parallel is
signal accu_load : std_logic; signal accu_load : std_logic;
signal accu_ld_pipe : unsigned(nstages+input_latency+coef_latency+pipe_latency downto 0); signal accu_ld_pipe : unsigned(nstages+input_latency+coef_latency+pipe_latency downto 0);
signal vld_pipe : unsigned((1+ntaps_per_stage)*nstages downto 0); signal vld_pipe : unsigned(1 downto 0);
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
begin begin
lib/filter/src/tb_fir_semi_parallel.vhd
+20 -17
View File
@@ -31,8 +31,8 @@ use work.PCK_FIO.all;
ENTITY tb_fir_semi_parallel IS ENTITY tb_fir_semi_parallel IS
Generic Generic
( (
ntaps_per_stage : integer := 64; ntaps_per_stage : integer := 32;
nstages : integer := 2; nstages : integer := 4;
nbits_in : integer := 32; nbits_in : integer := 32;
nbits_in_frac : integer := 30; nbits_in_frac : integer := 30;
nbits_stages : integer := 32; nbits_stages : integer := 32;
@@ -134,7 +134,7 @@ BEGIN
wait for PERIOD/2; wait for PERIOD/2;
END PROCESS; END PROCESS;
din_vld <= rdy; -- din_vld <= rdy;
tb : PROCESS tb : PROCESS
file fi : file_t open read_mode is "wav_in.dat"; file fi : file_t open read_mode is "wav_in.dat";
@@ -163,26 +163,29 @@ BEGIN
wait until rising_edge(clk); wait until rising_edge(clk);
for i in 0 to 19 loop for i in 0 to 19 loop
wait until rising_edge(clk); wait until rising_edge(clk) and rdy = '1';
-- din_vld <= rdy; din_vld <= '1';
d_in <= to_sfixed(real(i)*0.01, d_in); d_in <= to_sfixed(real(i)*0.01, d_in);
wait until rising_edge(clk);
-- din_vld <= '0';
wait for (ntaps_per_stage-1)*PERIOD;
end loop; end loop;
wait until rising_edge(clk); wait until rising_edge(clk) and rdy = '1';
------------------------------------------ ------------------------------------------
-- din_vld <= '0'; din_vld <= '1';
d_in <= to_sfixed(0.0, d_in); d_in <= to_sfixed(0.0, d_in);
wait for 64*ntaps*PERIOD; wait for 64*ntaps*PERIOD;
wait until rising_edge(clk); wait until rising_edge(clk) and rdy = '1';
-- din_vld <= '1'; din_vld <= '0';
d_in <= to_sfixed(1.0, d_in);
wait until rising_edge(clk); wait for 64*ntaps*PERIOD;
-- din_vld <= '0'; wait until rising_edge(clk) and rdy = '1';
wait for (ntaps_per_stage-1)*PERIOD; din_vld <= '1';
d_in <= to_sfixed(0.0, d_in); d_in <= to_sfixed(0.0, d_in);
wait until rising_edge(clk) and rdy = '1';
d_in <= to_sfixed(1.0, d_in);
wait until rising_edge(clk) and rdy = '1';
d_in <= to_sfixed(0.0, d_in);
wait for 64*ntaps*PERIOD;
wait until rising_edge(clk) and rdy = '1';
din_vld <= '0';
wait for 40*PERIOD; wait for 40*PERIOD;