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This commit was manufactured by cvs2svn to create tag 'EMAC_R01'.

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git-svn-id: http://moon:8086/svn/vhdl/tags/EMAC_R01@910 cc03376c-175c-47c8-b038-4cd826a8556b
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jens
2010-04-10 12:04:19 +00:00
parent 197e65fc28
commit bb8751e751
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lib/misc/async_port_wb.vhd
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-----------------------------------------------------------------------
-- $Header: /tmp/cvsroot/VHDL/lib/misc/async_port_wb.vhd,v 1.16 2010-02-09 09:56:37 Jens Exp $
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.async_types.all;
------------------------------------------------------------------
entity async_port_wb is
Generic
(
f_sysclk : real := 100.0;
addr_width : natural := 32;
data_width : natural := 32;
byte_sel_width : natural := 4;
async_timespec : async_timespec_t
);
Port
(
CLK_I : in STD_LOGIC;
RST_I : in STD_LOGIC;
CYC_I : in STD_LOGIC;
STB_I : in STD_LOGIC;
WE_I : in STD_LOGIC;
ACK_O : out STD_LOGIC;
SRDY_O : out STD_LOGIC;
MRDY_I : in STD_LOGIC;
SEL_I : in unsigned(3 downto 0);
ADDR_I : in unsigned(31 downto 0);
DAT_I : in unsigned(31 downto 0);
DAT_O : out unsigned(31 downto 0);
page_mode_en : in STD_LOGIC;
async_a : out unsigned(addr_width-1 downto 0);
async_d : inout unsigned(data_width-1 downto 0);
async_cs : out std_logic;
async_wr : out std_logic;
async_rd : out std_logic;
async_be : out unsigned(byte_sel_width-1 downto 0);
async_rst : out std_logic
);
end async_port_wb;
architecture Behavioral of async_port_wb is
type async_t is record
cs : std_logic;
wr : std_logic;
rd : std_logic;
rst : std_logic;
drive_d : std_logic;
end record;
type async_state_t is (start, reset, idle, leadin, pulse, leadout, release);
signal s, sn : async_state_t;
signal as : async_t;
signal ack : std_logic;
signal cc_rst : std_logic;
signal cycle_cnt : natural range 0 to 31;
signal cycle_reload : natural range 0 to 31;
signal rdy : std_logic;
signal rdyo : std_logic;
signal en : std_logic;
signal is_idle : std_logic;
signal DAT_I_r : unsigned(data_width-1 downto 0);
signal SEL_I_r : unsigned(byte_sel_width-1 downto 0);
signal WE_I_r : std_logic;
signal ADDR_I_r : unsigned(addr_width-1 downto 0);
signal page_mode_en_r : std_logic;
signal do_page_read : std_logic;
------------------------------------------------------------------
begin
ASSERT to_cycles(async_timespec.T_pulse_rd, f_sysclk) > 0 report "Read pulse length must be greater than zero!" severity failure;
ASSERT to_cycles(async_timespec.T_pulse_wr, f_sysclk) > 0 report "Write pulse length must be greater than zero!" severity failure;
ASSERT (not async_timespec.can_page_rd OR (to_cycles(async_timespec.T_pulse_page_rd, f_sysclk) > 1)) report "Read page pulse length must be greater than one!" severity failure;
SRDY_O <= CYC_I and rdyo;
en <= CYC_I and STB_I;
do_page_read <= '1' when (async_timespec.can_page_rd and (WE_I = '0') and (WE_I_r = '0') and (ADDR_I(addr_width-1 downto async_timespec.nbits_page_rd) = ADDR_I_r(addr_width-1 downto async_timespec.nbits_page_rd))) else '0';
proc_cycle_counter:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if cc_rst = '1' then
cycle_cnt <= cycle_reload;
elsif cycle_cnt /= 0 then
cycle_cnt <= cycle_cnt - 1;
end if;
end if;
end process;
------------------------------------------------------------------
proc_state_next:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if RST_I = '1' then
s <= start;
else
s <= sn;
end if;
end if;
end process;
proc_state:
process(s, cycle_cnt, en, WE_I, WE_I_r, do_page_read)
begin
cycle_reload <= to_cycles(async_timespec.T_pulse_rst, f_sysclk);
cc_rst <= '0';
as.rst <= '0';
as.cs <= '0';
as.wr <= '0';
as.rd <= '0';
as.drive_d <= '0';
ack <= '0';
rdy <= '0';
is_idle <= '0';
sn <= s;
case s is
when start =>
cc_rst <= '1';
sn <= reset;
when reset =>
as.rst <= '1';
if cycle_cnt = 0 then
sn <= idle;
end if;
when idle =>
rdy <= '1';
is_idle <= '1';
if en = '1' then
as.cs <= '1';
cc_rst <= '1';
if to_cycles(async_timespec.T_leadin, f_sysclk) = 0 then
sn <= pulse;
if WE_I = '1' then
cycle_reload <= 0;
sn <= leadin; -- always lead-in for writes
else
cycle_reload <= to_cycles(async_timespec.T_pulse_rd, f_sysclk) - 1;
as.rd <= '1';
end if;
else
cycle_reload <= to_cycles(async_timespec.T_leadin, f_sysclk) - 1;
sn <= leadin;
end if;
end if;
when leadin =>
as.cs <= '1';
as.rd <= not WE_I_r;
as.drive_d <= WE_I_r;
as.wr <= WE_I_r;
if cycle_cnt = 0 then
cc_rst <= '1';
sn <= pulse;
if WE_I_r = '1' then
cycle_reload <= to_cycles(async_timespec.T_pulse_wr, f_sysclk) - 1;
else
cycle_reload <= to_cycles(async_timespec.T_pulse_rd, f_sysclk) - 1;
end if;
end if;
when pulse =>
as.cs <= '1';
as.rd <= not WE_I_r;
as.drive_d <= WE_I_r;
as.wr <= WE_I_r;
if cycle_cnt = 0 then
as.wr <= '0';
cc_rst <= '1';
ack <= not WE_I_r;
rdy <= do_page_read;
if en = '1' and do_page_read = '1' then
cycle_reload <= to_cycles(async_timespec.T_pulse_page_rd, f_sysclk) - 1;
sn <= pulse;
elsif to_cycles(async_timespec.T_leadout, f_sysclk) = 0 then
if to_cycles(async_timespec.T_release, f_sysclk) = 0 then
sn <= idle;
else
cycle_reload <= to_cycles(async_timespec.T_release, f_sysclk) - 1;
sn <= release;
end if;
else
cycle_reload <= to_cycles(async_timespec.T_leadout, f_sysclk) - 1;
sn <= leadout;
end if;
end if;
when leadout =>
as.cs <= '1';
as.drive_d <= WE_I_r;
if cycle_cnt = 0 then
cc_rst <= '1';
if to_cycles(async_timespec.T_release, f_sysclk) = 0 then
sn <= idle;
else
cycle_reload <= to_cycles(async_timespec.T_release, f_sysclk) - 1;
sn <= release;
end if;
end if;
when release =>
if cycle_cnt = 0 then
sn <= idle;
end if;
when others =>
sn <= idle;
end case;
end process;
------------------------------------------------------------------
output_ctrl:
process(CLK_I)
begin
if rising_edge(CLK_I) then
async_cs <= (not async_timespec.pol_cs) xor as.cs;
async_wr <= (not async_timespec.pol_we) xor as.wr;
async_rd <= (not async_timespec.pol_oe) xor as.rd;
async_rst <= (not async_timespec.pol_rst) xor as.rst;
end if;
end process;
------------------------------------------------------------------
din_register:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if as.rd = '1' then
DAT_O(data_width-1 downto 0) <= async_d;
end if;
end if;
end process;
------------------------------------------------------------------
output_addr:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if RST_I = '1' then
async_a <= (others => '0');
SEL_I_r <= (others => '0');
elsif en = '1' and rdy = '1' then
async_a <= ADDR_I(addr_width-1 downto 0);
async_be <= (byte_sel_width-1 downto 0 => not async_timespec.pol_be) xor ((byte_sel_width-1 downto 0 => as.cs) and SEL_I(byte_sel_width-1 downto 0));
SEL_I_r <= SEL_I(byte_sel_width-1 downto 0);
if is_idle = '1' then
ADDR_I_r <= ADDR_I(addr_width-1 downto 0);
end if;
end if;
end if;
end process;
------------------------------------------------------------------
data_register:
process(CLK_I)
begin
if rising_edge(CLK_I) then
page_mode_en_r <= page_mode_en;
if en = '1' and rdy = '1' then
DAT_I_r <= DAT_I(data_width-1 downto 0);
WE_I_r <= WE_I;
end if;
end if;
end process;
------------------------------------------------------------------
output_SRDY:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if RST_I = '1' then
rdyo <= '1';
elsif en = '1' then
rdyo <= rdy and not rdyo;
end if;
end if;
end process;
------------------------------------------------------------------
output_ACK:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if RST_I = '1' then
ACK_O <= '0';
else
ACK_O <= ack;
end if;
end if;
end process;
------------------------------------------------------------------
output_data:
process(CLK_I)
begin
if rising_edge(CLK_I) then
async_d <= (others => 'Z');
if as.drive_d = '1' then
async_d <= DAT_I_r;
end if;
end if;
end process;
------------------------------------------------------------------
end Behavioral;
lib/misc/async_types.vhd
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-------------------------------------------------------------------------
-- Project: MIPS System controller
-- This file:
--
-- Copyright (C) 2008 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------
library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.MATH_REAL.ALL;
package async_types is
type async_timespec_t is record
T_leadin : real;
T_pulse_rd : real;
T_pulse_wr : real;
T_leadout : real;
T_release : real;
T_pulse_rst : real;
T_pulse_page_rd : real;
can_page_rd : boolean;
nbits_page_rd : natural;
pol_cs : std_logic;
pol_oe : std_logic;
pol_we : std_logic;
pol_be : std_logic;
pol_rst : std_logic;
end record;
function to_cycles(T_ns : real; f_Mhz : real) return natural;
end async_types;
package body async_types is
function to_cycles(T_ns : real; f_Mhz : real) return natural is
begin
return natural(ceil(1.0E-3*T_ns*f_Mhz));
end to_cycles;
end async_types;
lib/misc/bbfifo.vhd
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-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: Dual-ported register file with asynchrous read
-- Copyright (C) 2007 J. Ahrensfeld
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This library is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
-- For questions and ideas, please contact the author at jens@jayfield.org
-----------------------------------------------------------------------
-- $Header: /tmp/cvsroot/VHDL/lib/misc/bbfifo.vhd,v 1.1 2008-10-20 19:26:01 Jens Exp $
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
entity bbfifo is
Generic
(
depth : integer := 2;
data_width : integer := 8
);
Port
(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
re : in STD_LOGIC;
we : in STD_LOGIC;
ready : out STD_LOGIC;
avail : out STD_LOGIC;
din : in unsigned(data_width-1 downto 0);
dout : out unsigned(data_width-1 downto 0)
);
end bbfifo;
architecture Behavioral of bbfifo is
type bucket_array_t is array (0 to depth) of unsigned(data_width-1 downto 0);
signal req : unsigned(0 to depth);
signal rdy : unsigned(1 to depth+1);
signal bucket_array : bucket_array_t;
signal ce_in : unsigned(1 to depth);
signal ce_out : unsigned(1 to depth);
begin
req(0) <= we;
rdy(depth+1) <= re;
ready <= '1' when req(0 to depth-1) /= (0 to depth-1 => '1') else '0';
avail <= req(depth);
bucket_array(0) <= din;
dout <= bucket_array(depth);
gen_ce:
for i in 1 to depth generate
begin
process (rdy, req)
begin
ce_in(i) <= not req(i) and req(i-1);
end process;
end generate;
gen_rdy:
for i in 1 to depth generate
begin
process (clk)
begin
if rising_edge(clk) then
if rst = '1' then
rdy(i) <= '1';
elsif req(i-1) = '1' then
rdy(i) <= rdy(i+1);
end if;
end if;
end process;
end generate;
gen_req:
for i in 1 to depth generate
begin
process (clk)
begin
if rising_edge(clk) then
if rst = '1' then
req(i) <= '0';
elsif rdy(i+1) = '1' then
req(i) <= req(i-1);
end if;
end if;
end process;
end generate;
gen_data:
for i in 1 to depth generate
begin
process (clk)
begin
if rising_edge(clk) then
if rst = '1' then
bucket_array(i) <= (others => '0');
elsif req(i-1) = '1' then
bucket_array(i) <= bucket_array(i-1);
end if;
end if;
end process;
end generate;
end Behavioral;
lib/misc/clockgen_virtex4.vhd
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-------------------------------------------------------------------------
-- Project: SDRAM controller
-- This file: Clock generator (Virtex-4 specific)
--
-- Copyright (C) 2007 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------
library ieee, work;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE WORK.utils_pkg.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;
entity clockgen is
generic
(
clk_in_freq : real := 100.0;
clk0_out_phaseshift : integer := 0;
clk1_out_phaseshift : integer := 0
);
port
(
-- Clocks and Reset
rst : in std_logic; -- external async reset, low active
clk_in : in std_logic; -- system clock (e.g. 100MHz), from board
clk_fb_in : in std_logic; -- feedback clock
clk0_0_out : out std_logic; -- System clock #0, dcm#0 output 0°
clk0_270_out : out std_logic; -- System clock #0, dcm#0 output 270°
clk1_0_out : out std_logic; -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0°
clk1_270_out : out std_logic; -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270°
locked_out : out std_logic; -- DCM locked status
error_out : out std_logic -- indicates DCM Errors
);
end;
architecture tech of clockgen is
signal locked : unsigned(1 downto 0);
signal dcm_rst : unsigned(1 downto 0);
signal clk1_0 : std_logic;
signal clk1_270 : std_logic;
signal clk1_0_bufg : std_logic;
signal clk1_270_bufg : std_logic;
signal clk0_0 : std_logic;
signal clk0_270 : std_logic;
signal clk0_0_bufg : std_logic;
signal clk0_270_bufg : std_logic;
signal dcm1_locked, dcm2_locked : unsigned(2 downto 0);
signal cnt_q : unsigned(4 downto 0);
type STATE_TYPE is (s0, s1, s2, s3, s4);
signal state_q : STATE_TYPE;
begin
clk1_0_out <= clk1_0_bufg;
clk1_270_out <= clk1_270_bufg;
clk0_0_out <= clk0_0_bufg;
clk0_270_out <= clk0_270_bufg;
bufg11: bufg
port map
(
o => clk0_0_bufg,
i => clk0_0
);
bufg12: bufg
port map (
o => clk0_270_bufg,
i => clk0_270
);
bufg13: bufg
port map
(
o => clk1_0_bufg,
i => clk1_0
);
bufg14: bufg
port map (
o => clk1_270_bufg,
i => clk1_270
);
-------------------------------------------------------------------------------------------------------
-- Clock generation
-------------------------------------------------------------------------------------------------------
inst_DCM_BASE_0 : DCM_BASE
generic map (
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
-- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => 4, -- Can be any integer from 2 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => UTILS_PERIOD_NS(clk_in_freq), -- Specify period of input clock in ns from 1.25 to 1000.00
CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift mode of NONE or FIXED
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X
DCM_AUTOCALIBRATION => TRUE, -- DCM calibrartion circuitry TRUE/FALSE
DCM_PERFORMANCE_MODE => "MAX_SPEED", -- Can be MAX_SPEED or MAX_RANGE
DESKEW_ADJUST => "SOURCE_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
-- an integer from 0 to 15
DFS_FREQUENCY_MODE => "LOW", -- LOW or HIGH frequency mode for frequency synthesis
DLL_FREQUENCY_MODE => "LOW", -- LOW, HIGH, or HIGH_SER frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"F0F0", -- FACTORY JF Values Suggested to be set to X"F0F0"
PHASE_SHIFT => clk0_out_phaseshift, -- Amount of fixed phase shift from -255 to 1023
STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
port map (
CLK0 => clk0_0, -- 0 degree DCM CLK ouptput
CLK180 => open, -- 180 degree DCM CLK output
CLK270 => clk0_270, -- 270 degree DCM CLK output
CLK2X => open, -- 2X DCM CLK output
CLK2X180 => open, -- 2X, 180 degree DCM CLK out
CLK90 => open, -- 90 degree DCM CLK output
CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
CLKFX => open, -- DCM CLK synthesis out (M/D)
CLKFX180 => open, -- 180 degree CLK synthesis out
LOCKED => locked(0), -- DCM LOCK status output
CLKFB => clk_fb_in, -- DCM clock feedback
CLKIN => clk_in, -- Clock input (from IBUFG, BUFG or DCM)
RST => dcm_rst(0) -- DCM asynchronous reset input
);
inst_DCM_BASE_1 : DCM_BASE
generic map (
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
-- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => 4, -- Can be any integer from 2 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => UTILS_PERIOD_NS(clk_in_freq), -- Specify period of input clock in ns from 1.25 to 1000.00
CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift mode of NONE or FIXED
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X
DCM_AUTOCALIBRATION => TRUE, -- DCM calibrartion circuitry TRUE/FALSE
DCM_PERFORMANCE_MODE => "MAX_SPEED", -- Can be MAX_SPEED or MAX_RANGE
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
-- an integer from 0 to 15
DFS_FREQUENCY_MODE => "LOW", -- LOW or HIGH frequency mode for frequency synthesis
DLL_FREQUENCY_MODE => "LOW", -- LOW, HIGH, or HIGH_SER frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"F0F0", -- FACTORY JF Values Suggested to be set to X"F0F0"
PHASE_SHIFT => clk1_out_phaseshift, -- Amount of fixed phase shift from -255 to 1023
STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
port map (
CLK0 => clk1_0, -- 0 degree DCM CLK ouptput
CLK180 => open, -- 180 degree DCM CLK output
CLK270 => clk1_270, -- 270 degree DCM CLK output
CLK2X => open, -- 2X DCM CLK output
CLK2X180 => open, -- 2X, 180 degree DCM CLK out
CLK90 => open, -- 90 degree DCM CLK output
CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
CLKFX => open, -- DCM CLK synthesis out (M/D)
CLKFX180 => open, -- 180 degree CLK synthesis out
LOCKED => locked(1), -- DCM LOCK status output
CLKFB => clk1_0_bufg, -- DCM clock feedback
CLKIN => clk_fb_in, -- Clock input (from IBUFG, BUFG or DCM)
RST => dcm_rst(1) -- DCM asynchronous reset input
);
dcm_rst(1) <= not locked(0);
dcm_fsm:
process(rst, clk_in)
begin
if rst = '1' then
state_q <= s0;
dcm_rst(0) <= '0';
cnt_q <= "11111";
error_out <= '0';
locked_out <= '0';
dcm1_locked <= (others => '0');
dcm2_locked <= (others => '0');
elsif rising_edge(clk_in) then
case state_q is
when s0 =>
state_q <= s1;
when s1 =>
cnt_q <= cnt_q - 1;
if cnt_q = 0 then
dcm_rst(0) <= '1';
state_q <= s2;
end if;
when s2 =>
cnt_q <= cnt_q - 1;
if cnt_q = 0 then
dcm_rst(0) <= '0';
state_q <= s3;
end if;
when s3 =>
if dcm1_locked(2)='1' and dcm2_locked(2)='1' then
state_q <= s4;
error_out <= '0';
end if;
when s4 =>
if dcm1_locked(2)='1' and dcm2_locked(2)='1' then
locked_out <= '1';
else
error_out <= '1';
end if;
end case;
-- synchronize 'dcm1_locked'
dcm1_locked <= dcm1_locked(1 downto 0) & locked(0);
dcm2_locked <= dcm2_locked(1 downto 0) & locked(1);
end if;
end process;
end architecture tech;
lib/misc/debounce.vhd
-91
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--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:34:24 10/23/05
-- Design Name:
-- Module Name: debounce - Behavioral
-- Project Name:
-- Target Device:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-----------------------------------------------------------------------
-- $Header: /tmp/cvsroot/VHDL/lib/misc/debounce.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity debounce is
Generic ( ncyc_latency : integer := 100);
Port ( rst : in std_logic;
clk : in std_logic;
input : in std_logic;
output : out std_logic);
end debounce;
architecture Behavioral of debounce is
type debounce_state_t is (init_st, wait_st, rel_st);
signal debounce_cs : debounce_state_t;
signal debounce_ns : debounce_state_t;
signal count : integer range 0 to ncyc_latency;
signal input_last : std_logic;
begin
debounce_clk: process(rst, clk, debounce_ns, debounce_cs, input)
begin
if (rst = '1') then
count <= 0;
output <= input;
input_last <= input;
else
if rising_edge(clk) then
debounce_cs <= debounce_ns;
if (debounce_cs = wait_st) then
if (count /= 0) then
count <= count - 1;
end if;
else
count <= ncyc_latency;
if (debounce_cs = rel_st) then
output <= input;
input_last <= input;
end if;
end if;
end if;
end if;
end process;
debounce_in: process(rst, clk, input, input_last, debounce_cs, count)
begin
debounce_ns <= debounce_cs;
case debounce_cs is
when init_st =>
if (input /= input_last) then
debounce_ns <= wait_st;
end if;
when wait_st =>
if (count = 0) then
debounce_ns <= rel_st;
end if;
when others =>
debounce_ns <= init_st;
end case;
end process;
end Behavioral;
lib/misc/debounce2.vhd
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-------------------------------------------------
-- Signal Debouncer
-- Jeff Bazinet
-- February 14, 2002
-----------------------------------------------------------------------
-- $Header: /tmp/cvsroot/VHDL/lib/misc/debounce2.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library lpm;
use lpm.lpm_components.lpm_counter;
entity debounce is
generic(BUFFER_WIDTH: positive:= 30;
CLOCK_DIV: positive:= 15
);
port( clock: in std_logic;
reset: in std_logic;
signal_in: in std_logic;
signal_out: out std_logic
);
end entity debounce;
architecture rtl of debounce is
---------------------------------------------------------------
-- SIGNAL DECLARATION
---------------------------------------------------------------
-- General
signal reset_n: std_logic;
-- SLOW CLOCK GENERATION
signal clock_reg: std_logic_vector(CLOCK_DIV-1 downto 0);
signal clock_reg_high: std_logic_vector(CLOCK_DIV-1 downto 1);
signal clock_slow: std_logic;
signal clock_slow_wire: std_logic;
-- DATA BUFFER FILL
signal counter_reg: std_logic_vector(BUFFER_WIDTH-1 downto 0);
signal data_buffer_reg: std_logic_vector(BUFFER_WIDTH-1 downto 0);
-- CHECK FOR DEBOUNCE STABILITY
signal stable: std_logic;
signal stable_old: std_logic;
signal stable_state_reg:std_logic_vector(BUFFER_WIDTH-1 downto 0);
-- PUSH BUTTON ENABLE
signal button_pushed: std_logic;
begin
---------------------------------------------------------------
-- SLOW CLOCK GENERATION
---------------------------------------------------------------
COUNTER_1: lpm_counter
generic map (lpm_width => CLOCK_DIV)
port map (
clock => clock,
sclr => reset_n,
cout => clock_slow_wire
);
process (clock) is
begin
clock_slow <= clock_slow_wire;
end process;
---------------------------------------------------------------
-- DATA BUFFER FILL
---------------------------------------------------------------
process (clock) is
begin
if (reset = '0') then
-- Initialization
data_buffer_reg <= (others => '1');
elsif rising_edge(clock_slow) then
data_buffer_reg <= data_buffer_reg(BUFFER_WIDTH-2 downto 0) & signal_in;
end if;
end process;
---------------------------------------------------------------
-- CHECK FOR DEBOUNCE STABILITY
---------------------------------------------------------------
process (clock) is
begin
if (reset = '0') then
-- Initialization
stable <= '0';
stable_old <= '0';
stable_state_reg <= (others => '0');
elsif rising_edge(clock) then
if (data_buffer_reg = stable_state_reg) then
stable <= '1';
stable_state_reg <= (others => '0');
else
stable <= '0';
end if;
stable_old <= stable;
end if;
end process;
---------------------------------------------------------------
-- PUSH BUTTON ENABLE
---------------------------------------------------------------
process (clock) is
begin
if (reset = '0') then
-- Initialization
button_pushed <= '0';
elsif rising_edge(clock) then
if (stable_old = '0' and stable = '1') then
button_pushed <= '1';
else
button_pushed <= '0';
end if;
end if;
end process;
---------------------------------------------------------------
---------------------------------------------------------------
signal_out <= button_pushed;
reset_n <= not reset;
end rtl;
lib/misc/dpram_1w1r_dist.vhd
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-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: Dual-ported register file with asynchrous read
-- Copyright (C) 2007 J. Ahrensfeld
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This library is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
-- For questions and ideas, please contact the author at jens@jayfield.org
-----------------------------------------------------------------------
-- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_1w1r_dist.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
-----------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
entity dpram_1w1r_dist is
Generic
(
addr_width : integer := 3;
data_width : integer := 8
);
Port
(
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
en_a : in STD_LOGIC;
en_b : in STD_LOGIC;
we_a : in STD_LOGIC;
addr_a : in unsigned (addr_width-1 downto 0);
addr_b : in unsigned (addr_width-1 downto 0);
din_a : in unsigned (data_width-1 downto 0);
dout_b : out unsigned (data_width-1 downto 0)
);
end dpram_1w1r_dist;
architecture Behavioral of dpram_1w1r_dist is
constant depth : integer := 2**addr_width;
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
signal RAM : RAMtype;
attribute ram_style : string;
attribute ram_style of RAM: signal is "distributed";
begin
process (clka)
begin
if clka'event and clka = '1' then
if en_a = '1' then
if we_a = '1' then
RAM(to_integer(addr_a)) <= din_a;
end if;
end if;
end if;
end process;
process (clkb)
begin
if clkb'event and clkb = '1' then
if en_b = '1' then
dout_b <= RAM(to_integer(addr_b));
end if;
end if;
end process;
end Behavioral;
lib/misc/flash_port_wb.vhd
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-----------------------------------------------------------------------
-- $Header: /tmp/cvsroot/VHDL/lib/misc/flash_port_wb.vhd,v 1.2 2010-03-13 11:06:43 Jens Exp $
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.async_types.all;
------------------------------------------------------------------
entity flash_port_wb is
Generic
(
f_sysclk : real := 100.0;
addr_width : natural := 32;
data_width : natural := 32;
async_timespec : async_timespec_t
);
Port
(
CLK_I : in STD_LOGIC;
RST_I : in STD_LOGIC;
CYC_I : in STD_LOGIC;
STB_I : in STD_LOGIC;
WE_I : in STD_LOGIC;
ACK_O : out STD_LOGIC;
SRDY_O : out STD_LOGIC;
MRDY_I : in STD_LOGIC;
ADDR_I : in unsigned(31 downto 0);
DAT_I : in unsigned(31 downto 0);
DAT_O : out unsigned(31 downto 0);
port_bsyi : in std_logic;
port_bsyo : out std_logic;
port_a : out unsigned(addr_width-1 downto 0);
port_di : in unsigned(data_width-1 downto 0);
port_do : out unsigned(data_width-1 downto 0);
port_d_drv : out STD_LOGIC;
port_wr : out STD_LOGIC;
port_rd : out STD_LOGIC;
flash_cs : out std_logic;
flash_rst : out std_logic
);
end flash_port_wb;
architecture Behavioral of flash_port_wb is
type async_t is record
cs : std_logic;
wr : std_logic;
rd : std_logic;
rst : std_logic;
drive_d : std_logic;
end record;
type async_state_t is (start, reset, idle, go, leadin_rd, read, leadin_wr, write, leadout_rd, leadout_wr, release);
signal s, sn : async_state_t;
signal as : async_t;
signal ack : std_logic;
signal cc_rst : std_logic;
signal cycle_cnt : natural range 0 to 31;
signal cycle_reload : natural range 0 to 31;
signal rdy : std_logic;
signal rdyo : std_logic;
signal en : std_logic;
signal we_reg : std_logic;
signal data_reg : unsigned(data_width-1 downto 0);
signal addr_reg : unsigned(addr_width-1 downto 0);
------------------------------------------------------------------
begin
SRDY_O <= CYC_I and rdyo;
en <= CYC_I and STB_I;
port_a <= addr_reg;
port_do <= data_reg;
port_d_drv <= as.drive_d;
port_wr <= (not async_timespec.pol_we) xor as.wr;
port_rd <= (not async_timespec.pol_oe) xor as.rd;
proc_cycle_counter:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if cc_rst = '1' then
cycle_cnt <= cycle_reload;
elsif cycle_cnt /= 0 then
cycle_cnt <= cycle_cnt - 1;
end if;
end if;
end process;
------------------------------------------------------------------
proc_state_next:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if RST_I = '1' then
s <= start;
else
s <= sn;
end if;
end if;
end process;
proc_state:
process(s, cycle_cnt, en, we_reg, port_bsyi)
begin
cycle_reload <= to_cycles(async_timespec.T_pulse_rst, f_sysclk);
cc_rst <= '0';
as.rst <= '0';
as.cs <= '0';
as.wr <= '0';
as.rd <= '0';
as.drive_d <= '0';
ack <= '0';
rdy <= '0';
port_bsyo <= '1';
sn <= s;
case s is
when start =>
cc_rst <= '1';
sn <= reset;
when reset =>
as.rst <= '1';
if cycle_cnt = 0 then
sn <= idle;
end if;
when idle =>
port_bsyo <= '0';
rdy <= '1';
if en = '1' then
sn <= go;
end if;
when go =>
port_bsyo <= '0';
if port_bsyi = '0' then
as.cs <= '1';
cc_rst <= '1';
cycle_reload <= to_cycles(async_timespec.T_leadin, f_sysclk)-1;
if we_reg = '0' then
sn <= leadin_rd;
else
sn <= leadin_wr;
end if;
end if;
when leadin_rd =>
as.cs <= '1';
if cycle_cnt = 0 then
cc_rst <= '1';
cycle_reload <= to_cycles(async_timespec.T_pulse_rd, f_sysclk)-1;
as.rd <= '1';
sn <= read;
end if;
when leadin_wr =>
as.cs <= '1';
if cycle_cnt = 0 then
cc_rst <= '1';
cycle_reload <= to_cycles(async_timespec.T_pulse_wr, f_sysclk)-1;
as.wr <= '1';
as.drive_d <= '1';
sn <= write;
end if;
when read =>
as.cs <= '1';
as.rd <= '1';
if cycle_cnt = 0 then
cc_rst <= '1';
cycle_reload <= to_cycles(async_timespec.T_leadout, f_sysclk)-1;
-- as.rd <= '0';
sn <= leadout_rd;
ack <= '1';
end if;
when write =>
as.drive_d <= '1';
as.cs <= '1';
as.wr <= '1';
if cycle_cnt = 0 then
as.wr <= '0';
cc_rst <= '1';
cycle_reload <= to_cycles(async_timespec.T_leadout, f_sysclk)-1;
sn <= leadout_wr;
-- ack <= '1';
end if;
when leadout_rd =>
as.cs <= '1';
if cycle_cnt = 0 then
cc_rst <= '1';
cycle_reload <= to_cycles(async_timespec.T_release, f_sysclk)-1;
sn <= release;
as.cs <= '0';
end if;
when leadout_wr =>
as.cs <= '1';
as.drive_d <= '1';
if cycle_cnt = 0 then
cc_rst <= '1';
cycle_reload <= to_cycles(async_timespec.T_release, f_sysclk)-1;
sn <= release;
as.cs <= '0';
end if;
when release =>
if cycle_cnt = 0 then
sn <= idle;
end if;
when others =>
sn <= idle;
end case;
end process;
------------------------------------------------------------------
output_ctrl:
process(CLK_I)
begin
if rising_edge(CLK_I) then
flash_cs <= (not async_timespec.pol_cs) xor as.cs;
flash_rst <= (not async_timespec.pol_rst) xor as.rst;
end if;
end process;
------------------------------------------------------------------
din_register:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if as.rd = '1' then
DAT_O(data_width-1 downto 0) <= port_di;
end if;
end if;
end process;
------------------------------------------------------------------
data_register:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if en = '1' and rdy = '1' then
we_reg <= WE_I;
data_reg <= DAT_I(data_width-1 downto 0);
end if;
end if;
end process;
------------------------------------------------------------------
addr_register:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if en = '1' and rdy = '1' then
addr_reg <= ADDR_I(addr_width-1 downto 0);
end if;
end if;
end process;
------------------------------------------------------------------
output_SRDY:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if RST_I = '1' then
rdyo <= '1';
elsif en = '1' then
rdyo <= rdy and not rdyo;
end if;
end if;
end process;
------------------------------------------------------------------
output_ACK:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if RST_I = '1' then
ACK_O <= '0';
else
ACK_O <= ack;
end if;
end if;
end process;
------------------------------------------------------------------
end Behavioral;
lib/misc/gpio_wb.vhd
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY gpio_wb IS
Generic
(
f_sysclk : real := 100.0
);
Port
(
CLK_I : in STD_LOGIC;
RST_I : in STD_LOGIC;
CYC_I : in STD_LOGIC;
STB_I : in STD_LOGIC;
SEL_I : in unsigned(3 downto 0);
WE_I : in STD_LOGIC;
ACK_O : out STD_LOGIC;
SRDY_O : out STD_LOGIC;
MRDY_I : in STD_LOGIC;
ADDR_I : in unsigned(31 downto 0);
DAT_I : in unsigned(31 downto 0);
DAT_O : out unsigned(31 downto 0);
INT_TIM_O : out STD_LOGIC;
sys_gpi_0 : in unsigned(31 downto 0);
sys_gpo_0 : out unsigned(31 downto 0)
);
END gpio_wb;
ARCHITECTURE behavior OF gpio_wb IS
constant num_timers : natural := 2;
constant ncycles_usec : natural := natural(f_sysclk);
signal gpio_0_dout_reg : unsigned(31 downto 0);
signal gpio_0_dir_reg : unsigned(31 downto 0);
signal gpio_0_din_reg : unsigned(31 downto 0);
-- Signals to form an timer generating an interrupt every microsecond
subtype tick_usec_t is natural range 0 to ncycles_usec-1;
signal tick_usec : tick_usec_t := 0;
signal cnt_usec : unsigned(31 downto 0);
signal cnt_sec : unsigned(31 downto 0);
signal cnt_usec_preset : unsigned(31 downto 0);
signal cnt_sec_preset : unsigned(31 downto 0);
signal cnt_usec_en : std_logic;
signal cnt_usec_we : std_logic;
signal cnt_sec_en : std_logic;
signal cnt_sec_we : std_logic;
type timer_array_t is array (0 to num_timers-1) of unsigned(31 downto 0);
signal timer_cnt : timer_array_t;
signal timer_cmp : timer_array_t;
signal timer_en : unsigned(0 to num_timers-1);
signal timer_inten : unsigned(0 to num_timers-1);
signal timer_irq : unsigned(0 to num_timers-1);
signal timer_ovl : unsigned(0 to num_timers-1);
signal timer_irq_ack : unsigned(0 to num_timers-1);
signal timer_cnt_we : unsigned(0 to num_timers-1);
signal timer_cmp_we : unsigned(0 to num_timers-1);
signal reg_data_wr : unsigned(31 downto 0);
begin
SRDY_O <= CYC_I;
tim_irq:
process(timer_irq)
variable irq : std_logic;
begin
irq := '0';
for i in 0 to num_timers-1 loop
irq := irq or timer_irq(i);
end loop;
INT_TIM_O <= irq;
end process;
------------------------------------------------------------------
gpio_0_out:
process(gpio_0_dir_reg, gpio_0_dout_reg)
begin
for i in 0 to 31 loop
sys_gpo_0(i) <= 'Z';
if gpio_0_dir_reg(i) = '1' then
sys_gpo_0(i) <= gpio_0_dout_reg(i);
end if;
end loop;
end process;
------------------------------------------------------------------
gpio_0_in:
process(CLK_I)
begin
if rising_edge(CLK_I) then
for i in 0 to 31 loop
if gpio_0_dir_reg(i) = '1' then
gpio_0_din_reg(i) <= gpio_0_dout_reg(i);
else
gpio_0_din_reg(i) <= sys_gpi_0(i);
end if;
end loop;
end if;
end process;
------------------------------------------------------------------
registers_write:
process(CLK_I)
begin
if rising_edge(CLK_I) then
cnt_usec_we <= '0';
cnt_sec_we <= '0';
timer_cnt_we <= (others => '0');
timer_cmp_we <= (others => '0');
timer_irq_ack <= (others => '0');
if RST_I = '1' then
gpio_0_dout_reg <= (others => '0');
gpio_0_dir_reg <= (others => '0');
timer_en <= (others => '0');
timer_inten <= (others => '0');
elsif (STB_I and CYC_I and WE_I) = '1' then
reg_data_wr <= DAT_I;
case ADDR_I(6 downto 2) is
when "00000" =>
gpio_0_dout_reg <= DAT_I;
when "00001" =>
gpio_0_dir_reg <= DAT_I;
when "00010" =>
cnt_usec_we <= '1';
when "00011" =>
cnt_sec_we <= '1';
when "00110" => -- timer control
for i in 0 to num_timers-1 loop
timer_en(i) <= DAT_I(2*i+0);
timer_inten(i) <= DAT_I(2*i+1);
end loop;
when "00111" => -- timer status
for i in 0 to num_timers-1 loop
timer_irq_ack(i) <= DAT_I(2*i); -- IRQ acknowledge
end loop;
when "01000" => -- timer count 0
timer_cnt_we(0) <= '1';
when "01001" => -- timer count 1
timer_cnt_we(1) <= '1';
when "01100" => -- timer compare 0
timer_cmp_we(0) <= '1';
when "01101" => -- timer compare 1
timer_cmp_we(1) <= '1';
when others => null;
end case;
end if;
end if;
end process;
registers_read:
process(CLK_I)
begin
if rising_edge(CLK_I) then
ACK_O <= '0';
if (STB_I and CYC_I) = '1' then
ACK_O <= not WE_I;
DAT_O <= (others => '0');
case ADDR_I(6 downto 2) is
when "00000" =>
DAT_O <= gpio_0_din_reg;
when "00001" =>
DAT_O <= gpio_0_dir_reg;
when "00010" =>
DAT_O <= cnt_usec;
when "00011" =>
DAT_O <= cnt_sec;
when "00110" => -- timer control
for i in 0 to num_timers-1 loop
DAT_O(2*i+0) <= timer_en(i);
DAT_O(2*i+1) <= timer_inten(i);
end loop;
when "00111" => -- timer status
for i in 0 to num_timers-1 loop
DAT_O(2*i+0) <= timer_irq(i);
DAT_O(2*i+1) <= timer_ovl(i);
end loop;
when "01000" => -- timer count 0
DAT_O <= timer_cnt(0);
when "01001" => -- timer count 1
DAT_O <= timer_cnt(1);
when "01100" => -- timer compare 0
DAT_O <= timer_cmp(0);
when "01101" => -- timer compare 1
DAT_O <= timer_cmp(1);
when others => null;
end case;
end if;
end if;
end process;
cnt_usec_tick:
process(CLK_I)
begin
if rising_edge(CLK_I) then
cnt_usec_en <= '0';
if tick_usec >= tick_usec_t'high then
tick_usec <= 0;
cnt_usec_en <= '1';
else
tick_usec <= tick_usec + 1;
end if;
end if;
end process;
-- H/W Clock
cnt_usec_clock:
process(CLK_I)
begin
if rising_edge(CLK_I) then
cnt_sec_en <= '0';
if cnt_usec_we = '1' then
cnt_usec <= reg_data_wr;
elsif cnt_usec_en = '1' then
if to_01(cnt_usec) >= to_unsigned(1E6 - 1, 32) then
cnt_usec <= (others => '0');
cnt_sec_en <= '1';
else
cnt_usec <= cnt_usec + 1;
end if;
end if;
end if;
end process;
cnt_sec_clock:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if cnt_sec_we = '1' then
cnt_sec <= reg_data_wr;
elsif cnt_sec_en = '1' then
cnt_sec <= cnt_sec + 1;
end if;
end if;
end process;
-- Interrupt timer
proc_int_timer:
process(CLK_I)
begin
if rising_edge(CLK_I) then
for i in 0 to num_timers-1 loop
if RST_I = '1' then
timer_ovl(i) <= '0';
timer_irq(i) <= '0';
elsif timer_irq_ack(i) = '1' then
timer_ovl(i) <= '0';
timer_irq(i) <= '0';
elsif timer_cnt_we(i) = '1' then
timer_cnt(i) <= reg_data_wr;
elsif timer_en(i) = '1' then
if to_01(timer_cnt(i)) >= timer_cmp(i) then
timer_cnt(i) <= (others => '0');
if timer_inten(i) = '1' then
if timer_irq(i) = '1' then
timer_ovl(i) <= '1';
end if;
timer_irq(i) <= '1';
end if;
else
timer_cnt(i) <= timer_cnt(i) + 1;
end if;
end if;
end loop;
end if;
end process;
proc_int_timer_reload:
process(CLK_I)
begin
if rising_edge(CLK_I) then
for i in 0 to num_timers-1 loop
if timer_cmp_we(i) = '1' then
timer_cmp(i) <= reg_data_wr;
end if;
end loop;
end if;
end process;
------------------------------------------------------------------
end behavior;
lib/misc/lcd_port.vhd
-69
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@@ -1,69 +0,0 @@
-----------------------------------------------------------------------
-- $Header: /tmp/cvsroot/VHDL/lib/misc/lcd_port.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
------------------------------------------------------------------
entity lcd_port is
Port (
rst : in std_logic;
clk : in std_logic;
we : in std_logic;
din : in unsigned(7 downto 0);
dout : out unsigned(7 downto 0);
lcd_d : inout unsigned(3 downto 0);
lcd_e : out std_logic;
lcd_rs : out std_logic;
lcd_rw : out std_logic
);
end lcd_port;
architecture Behavioral of lcd_port is
constant clcd_e : integer := 7;
constant clcd_rs : integer := 6;
constant clcd_rw : integer := 5;
type lcd_t is record
d : unsigned(3 downto 0);
e : std_logic;
rs : std_logic;
rw : std_logic;
end record;
------------------------------------------------------------------
begin
proc_lcd_port:
process(rst, clk)
variable vlcd : lcd_t;
begin
if (rst = '1') then
dout <= (others => '0');
vlcd.d := (others => '0');
vlcd.e := '0';
vlcd.rw := '1';
vlcd.rs := '0';
elsif rising_edge(clk) then
dout <= unsigned("0000" & lcd_d);
if we = '1' then
vlcd.d := din(3 downto 0);
vlcd.e := din(clcd_e);
vlcd.rs := din(clcd_rs);
vlcd.rw := din(clcd_rw);
end if;
end if;
if vlcd.rw = '0' then
lcd_d <= unsigned(vlcd.d);
else
lcd_d <= (others => 'Z');
end if;
lcd_e <= vlcd.e;
lcd_rs <= vlcd.rs;
lcd_rw <= vlcd.rw;
end process;
------------------------------------------------------------------
end Behavioral;
lib/misc/mult_signed.vhd
-62
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@@ -1,62 +0,0 @@
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
entity signed_mult is
generic
(
latency : natural := 2;
data_width : natural := 16
);
port
(
clk : in std_logic;
ce : in std_logic;
a : in signed (data_width-1 downto 0);
b : in signed (data_width-1 downto 0);
result : out signed (2*data_width-1 downto 0)
);
end signed_mult;
architecture rtl of signed_mult is
constant in_latency : natural := latency - 1;
constant out_latency : natural := latency - in_latency;
subtype in_t is signed (data_width-1 downto 0);
subtype out_t is signed (2*data_width-1 downto 0);
type in_pipe_t is array (in_latency downto 1) of in_t;
type out_pipe_t is array (out_latency downto 1) of out_t;
signal a_pipe : in_pipe_t;
signal b_pipe : in_pipe_t;
signal out_pipe : out_pipe_t;
begin
result <= out_pipe(out_latency);
input_pipe_reg:
process(clk)
begin
if rising_edge(clk) then
if ce = '1' then
a_pipe <= a_pipe(in_latency-1 downto 1) & a;
b_pipe <= b_pipe(in_latency-1 downto 1) & b;
end if;
end if;
end process;
mult_pipe_reg:
process (clk)
variable res : out_t;
begin
if rising_edge(clk) then
res := a_pipe(in_latency) * b_pipe(in_latency);
if ce = '1' then
out_pipe <= out_pipe(out_latency-1 downto 1) & res;
end if;
end if;
end process;
end rtl;
lib/misc/oneshot.vhd
-223
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@@ -1,223 +0,0 @@
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:52:19 10/22/05
-- Design Name:
-- Module Name: oneshot - Behavioral
-- Project Name:
-- Target Device:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-----------------------------------------------------------------------
-- $Header: /tmp/cvsroot/VHDL/lib/misc/oneshot.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
-----------------------------------------------------------------------
-- Component Template
--
-- COMPONENT oneshot
-- GENERIC (mode : integer);
-- PORT(
-- rst : IN std_logic;
-- clk : IN std_logic;
-- input : IN std_logic;
-- output : OUT std_logic
-- );
-- END COMPONENT;
--
-- Instantation Template
--
-- oneshot_int: oneshot
-- GENERIC MAP (
-- mode => 1)
-- PORT MAP(
-- rst => ,
-- clk => ,
-- input => ,
-- output =>
-- );
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity oneshot is
Generic ( mode : integer range 0 to 2 := 1);
Port ( rst : in std_logic;
clk : in std_logic;
input : in std_logic;
output : out std_logic);
end oneshot;
architecture Behavioral of oneshot is
type shot_state_t is (shot_pos_st, shot_neg_st, release_pos_st, release_neg_st);
signal shot_cs : shot_state_t;
signal shot_ns : shot_state_t;
begin
mode_0:
if mode = 0 generate
begin
shot_clk: process(rst, clk, shot_ns, input)
begin
if (rst = '1') then
if (input = '1') then
shot_cs <= release_pos_st;
else
shot_cs <= release_neg_st;
end if;
else
if rising_edge(clk) then
shot_cs <= shot_ns;
end if;
end if;
end process;
shot_in: process(rst, clk, input, shot_cs)
begin
shot_ns <= shot_cs;
case shot_cs is
when release_pos_st =>
if (input = '0') then
shot_ns <= shot_neg_st;
end if;
when shot_neg_st =>
shot_ns <= release_neg_st;
when release_neg_st =>
if (input = '1') then
shot_ns <= release_pos_st;
end if;
when others => null;
end case;
end process;
shot_out: process(shot_cs)
begin
output <= '0';
case shot_cs is
when shot_pos_st =>
output <= '1';
when shot_neg_st =>
output <= '1';
when others => null;
end case;
end process;
end generate;
mode_1:
if mode = 1 generate
begin
shot_clk: process(rst, clk, shot_ns, input)
begin
if (rst = '1') then
if (input = '1') then
shot_cs <= release_pos_st;
else
shot_cs <= release_neg_st;
end if;
else
if rising_edge(clk) then
shot_cs <= shot_ns;
end if;
end if;
end process;
shot_in: process(rst, clk, input, shot_cs)
begin
shot_ns <= shot_cs;
case shot_cs is
when shot_pos_st =>
shot_ns <= release_pos_st;
when release_pos_st =>
if (input = '0') then
shot_ns <= release_neg_st;
end if;
when release_neg_st =>
if (input = '1') then
shot_ns <= shot_pos_st;
end if;
when others => null;
end case;
end process;
shot_out: process(shot_cs)
begin
output <= '0';
case shot_cs is
when shot_pos_st =>
output <= '1';
when shot_neg_st =>
output <= '1';
when others => null;
end case;
end process;
end generate;
mode_2:
if mode = 2 generate
begin
shot_clk: process(rst, clk, shot_ns, input)
begin
if (rst = '1') then
if (input = '1') then
shot_cs <= release_pos_st;
else
shot_cs <= release_neg_st;
end if;
else
if rising_edge(clk) then
shot_cs <= shot_ns;
end if;
end if;
end process;
shot_in: process(rst, clk, input, shot_cs)
begin
shot_ns <= shot_cs;
case shot_cs is
when shot_pos_st =>
shot_ns <= release_pos_st;
when release_pos_st =>
if (input = '0') then
shot_ns <= shot_neg_st;
end if;
when shot_neg_st =>
shot_ns <= release_neg_st;
when release_neg_st =>
if (input = '1') then
shot_ns <= shot_pos_st;
end if;
end case;
end process;
shot_out: process(shot_cs)
begin
output <= '0';
case shot_cs is
when shot_pos_st =>
output <= '1';
when shot_neg_st =>
output <= '1';
when others => null;
end case;
end process;
end generate;
end Behavioral;
lib/misc/pkg_template.vhd
-18
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@@ -1,18 +0,0 @@
-----------------------------------------------------------------------
-- $Header: /tmp/cvsroot/VHDL/lib/misc/pkg_template.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
-----------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
package template_pkg is
-- Constants
-- Types
-- Functions
end template_pkg;
package body template_pkg is
end template_pkg;
lib/misc/ram_sim.vhd
-88
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@@ -1,88 +0,0 @@
-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: The ROM file for use in your VHDL design
--
-- Copyright (C) 2007 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY ram IS
Generic
(
word_addr_width : integer := 6
);
Port
(
clk : in STD_LOGIC;
ce : in STD_LOGIC;
we : in unsigned(3 downto 0);
addr : in unsigned(31 downto 0);
din : in unsigned(31 downto 0);
dout : out unsigned(31 downto 0)
);
END ram;
ARCHITECTURE behavior OF ram IS
constant depth : natural := 2**word_addr_width;
type sram_t is array (0 to depth-1) of unsigned(31 downto 0);
function sram_clear return sram_t is
variable result : sram_t;
begin
for i in 0 to sram_t'length-1 loop
result(i) := (others => '0');
end loop;
return result;
end sram_clear;
signal sram : sram_t := sram_clear;
BEGIN
SRAM_RW:
process(clk)
variable index : natural range 0 to depth-1;
begin
if rising_edge(clk) and ce = '1' then
index := to_integer(addr(word_addr_width+1 downto 2));
if we(0) = '1' then
sram(index)(7 downto 0) <= din(7 downto 0);
end if;
if we(1) = '1' then
sram(index)(15 downto 8) <= din(15 downto 8);
end if;
if we(2) = '1' then
sram(index)(23 downto 16) <= din(23 downto 16);
end if;
if we(3) = '1' then
sram(index)(31 downto 24) <= din(31 downto 24);
end if;
dout <= sram(index);
end if;
end process;
end behavior;
lib/misc/ram_wb.vhd
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@@ -1,80 +0,0 @@
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY ram_wb IS
Port
(
CLK_I : in STD_LOGIC;
RST_I : in STD_LOGIC;
CYC_I : in STD_LOGIC;
STB_I : in STD_LOGIC;
SEL_I : in unsigned(3 downto 0);
WE_I : in STD_LOGIC;
ACK_O : out STD_LOGIC;
SRDY_O : out STD_LOGIC;
MRDY_I : in STD_LOGIC;
ADDR_I : in unsigned(31 downto 0);
DAT_I : in unsigned(31 downto 0);
DAT_O : out unsigned(31 downto 0)
);
END ram_wb;
ARCHITECTURE behavior OF ram_wb IS
COMPONENT ram
GENERIC
(
word_addr_width : integer
);
PORT
(
clk : in STD_LOGIC;
ce : in STD_LOGIC;
we : in unsigned(3 downto 0);
addr : in unsigned(31 downto 0);
din : in unsigned(31 downto 0);
dout : out unsigned(31 downto 0)
);
END COMPONENT;
signal data_en : std_logic;
signal we : unsigned(3 downto 0);
begin
we <= SEL_I and (3 downto 0 => WE_I);
data_en <= CYC_I and STB_I and MRDY_I;
SRDY_O <= CYC_I;
data_valid_register:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if RST_I = '1' then
ACK_O <= '0';
else
ACK_O <= data_en and not WE_I;
end if;
end if;
end process;
inst_ram : ram
GENERIC MAP
(
word_addr_width => 6
)
PORT MAP
(
clk => CLK_I,
ce => data_en,
we => we,
addr => ADDR_I,
din => DAT_I,
dout => DAT_O
);
end behavior;
lib/misc/rom_sim.vhd
-2082
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lib/misc/rom_wb.vhd
-61
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@@ -1,61 +0,0 @@
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY rom_wb IS
Port
(
CLK_I : in STD_LOGIC;
RST_I : in STD_LOGIC;
CYC_I : in STD_LOGIC;
STB_I : in STD_LOGIC;
ACK_O : out STD_LOGIC;
MRDY_I : in STD_LOGIC;
SRDY_O : out STD_LOGIC;
ADDR_I : in unsigned(31 downto 0);
DAT_O : out unsigned(31 downto 0)
);
END rom_wb;
ARCHITECTURE behavior OF rom_wb IS
COMPONENT rom
PORT
(
clk : in STD_LOGIC;
ce : in STD_LOGIC;
addr : in unsigned(31 downto 0);
dout : out unsigned(31 downto 0)
);
END COMPONENT;
signal data_en : std_logic;
begin
data_en <= CYC_I and STB_I and MRDY_I;
SRDY_O <= CYC_I;
data_valid_register:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if RST_I = '1' then
ACK_O <= '0';
else
ACK_O <= data_en; -- and not WE_I;
end if;
end if;
end process;
inst_rom : rom
PORT MAP
(
clk => CLK_I,
ce => data_en,
addr => ADDR_I,
dout => DAT_O
);
end behavior;
lib/misc/sim/ModelSim SE .lnk
BIN
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lib/misc/sim/tb_bbfifo.fdo
-14
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@@ -1,14 +0,0 @@
## NOTE: Do not edit this file.
##
vlib work
vcom -explicit -93 "../bbfifo.vhd"
vcom -explicit -93 "../tb_bbfifo.vhd"
#restart -force
vsim -t 1ps -lib work tb_bbfifo
do {tb_bbfifo.wdo}
view wave
view structure
view signals
run 1us
lib/misc/sim/tb_bbfifo.wdo
-31
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@@ -1,31 +0,0 @@
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Logic /tb_bbfifo/rst
add wave -noupdate -format Logic /tb_bbfifo/clk
add wave -noupdate -format Logic /tb_bbfifo/re
add wave -noupdate -format Logic /tb_bbfifo/we
add wave -noupdate -format Logic /tb_bbfifo/ready
add wave -noupdate -format Logic /tb_bbfifo/avail
add wave -noupdate -format Literal -radix hexadecimal /tb_bbfifo/din
add wave -noupdate -format Literal -radix hexadecimal /tb_bbfifo/dout
add wave -noupdate -format Literal /tb_bbfifo/inst_bbfifo/req
add wave -noupdate -format Literal /tb_bbfifo/inst_bbfifo/rdy
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_bbfifo/inst_bbfifo/bucket_array
add wave -noupdate -format Literal /tb_bbfifo/inst_bbfifo/ce_in
add wave -noupdate -format Literal /tb_bbfifo/inst_bbfifo/ce_out
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {170000 ps} 0}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
update
WaveRestoreZoom {76738 ps} {299465 ps}
lib/misc/sim/tb_ram_wb.fdo
-16
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@@ -1,16 +0,0 @@
## NOTE: Do not edit this file.
##
vlib work
# Top and TB
vcom -explicit -93 "../ram_sim.vhd"
vcom -explicit -93 "../ram_wb.vhd"
vcom -explicit -93 "../tb_ram_wb.vhd"
vsim -t 1ps -lib work tb_ram_wb
do {tb_ram_wb.wdo}
view wave
view structure
view signals
run 1.5us
lib/misc/sim/tb_ram_wb.wdo
-32
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@@ -1,32 +0,0 @@
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Logic /tb_ram_wb/clk_o
add wave -noupdate -format Logic /tb_ram_wb/rst_o
add wave -noupdate -format Logic /tb_ram_wb/cyc_o
add wave -noupdate -format Logic /tb_ram_wb/stb_o
add wave -noupdate -format Logic /tb_ram_wb/we_o
add wave -noupdate -format Literal /tb_ram_wb/sel_o
add wave -noupdate -format Logic /tb_ram_wb/ack_i
add wave -noupdate -format Logic /tb_ram_wb/mrdy_o
add wave -noupdate -format Logic /tb_ram_wb/srdy_i
add wave -noupdate -format Literal -radix hexadecimal /tb_ram_wb/addr_o
add wave -noupdate -format Literal -radix hexadecimal /tb_ram_wb/dat_i
add wave -noupdate -format Literal -radix hexadecimal /tb_ram_wb/dat_o
add wave -noupdate -format Literal -radix hexadecimal /tb_ram_wb/dout_reg
add wave -noupdate -format Literal /tb_ram_wb/dout_cnt
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {950000 ps} 0}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
update
WaveRestoreZoom {0 ps} {1575 ns}
lib/misc/sim/tb_rom_wb.fdo
-16
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@@ -1,16 +0,0 @@
## NOTE: Do not edit this file.
##
vlib work
# Top and TB
vcom -explicit -93 "../rom_sim.vhd"
vcom -explicit -93 "../rom_wb.vhd"
vcom -explicit -93 "../tb_rom_wb.vhd"
vsim -t 1ps -lib work tb_rom_wb
do {tb_rom_wb.wdo}
view wave
view structure
view signals
run 1us
lib/misc/sim/tb_rom_wb.wdo
-29
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@@ -1,29 +0,0 @@
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Logic /tb_rom_wb/clk_o
add wave -noupdate -format Logic /tb_rom_wb/rst_o
add wave -noupdate -format Logic /tb_rom_wb/cyc_o
add wave -noupdate -format Logic /tb_rom_wb/stb_o
add wave -noupdate -format Logic /tb_rom_wb/ack_i
add wave -noupdate -format Logic /tb_rom_wb/mrdy_o
add wave -noupdate -format Logic /tb_rom_wb/srdy_i
add wave -noupdate -format Literal -radix hexadecimal /tb_rom_wb/addr_o
add wave -noupdate -format Literal -radix hexadecimal /tb_rom_wb/dat_i
add wave -noupdate -format Literal -radix hexadecimal /tb_rom_wb/dout_reg
add wave -noupdate -format Literal /tb_rom_wb/dout_cnt
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {796036 ps} 0}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
update
WaveRestoreZoom {0 ps} {1050 ns}
lib/misc/singleshot.vhd
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@@ -1,155 +0,0 @@
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:52:19 10/22/05
-- Design Name:
-- Module Name: singleshot - Behavioral
-- Project Name:
-- Target Device:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-----------------------------------------------------------------------
-- $Header: /tmp/cvsroot/VHDL/lib/misc/singleshot.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
-----------------------------------------------------------------------
-- Component Template
--
-- COMPONENT singleshot
-- GENERIC (mode : integer);
-- PORT(
-- rst : IN std_logic;
-- clk : IN std_logic;
-- input : IN std_logic;
-- output : OUT std_logic
-- );
-- END COMPONENT;
--
-- Instantation Template
--
-- singleshot_int: oneshot
-- GENERIC MAP (
-- mode => 1)
-- PORT MAP(
-- rst => ,
-- clk => ,
-- input => ,
-- output =>
-- );
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity singleshot is
Generic ( mode : integer range 0 to 2 := 1);
Port ( rst : in std_logic;
clk : in std_logic;
input : in std_logic;
output : out std_logic);
end singleshot;
architecture Behavioral of singleshot is
type s_t is (idle, shot_in, active, shot_out);
signal s, sn : s_t;
begin
process (rst, clk, sn)
begin
if rising_edge(clk) then
if rst = '1' then
s <= idle;
else
s <= sn;
end if;
end if;
end process;
mode_1:
if mode = 1 generate
begin
process (input, s)
begin
output <= '0';
sn <= s;
case s is
when idle =>
if input = '1' then
sn <= shot_in;
end if;
when shot_in =>
output <= '1';
sn <= active;
when active =>
if input = '0' then
sn <= shot_out;
end if;
when shot_out =>
sn <= idle;
when others => null;
end case;
end process;
end generate;
mode_0:
if mode = 0 generate
begin
process (input, s)
begin
output <= '0';
sn <= s;
case s is
when idle =>
if input = '1' then
sn <= shot_in;
end if;
when shot_in =>
sn <= active;
when active =>
if input = '0' then
sn <= shot_out;
end if;
when shot_out =>
output <= '1';
sn <= idle;
when others => null;
end case;
end process;
end generate;
mode_2:
if mode = 2 generate
begin
process (input, s)
begin
output <= '0';
sn <= s;
case s is
when idle =>
if input = '1' then
sn <= shot_in;
end if;
when shot_in =>
output <= '1';
sn <= active;
when active =>
if input = '0' then
sn <= shot_out;
end if;
when shot_out =>
output <= '1';
sn <= idle;
when others => null;
end case;
end process;
end generate;
end Behavioral;
lib/misc/tb_bbfifo.vhd
-136
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@@ -1,136 +0,0 @@
-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: cpu_embedded using cpu_core and rom
--
-- Copyright (C) 2007 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
entity tb_bbfifo is
end;
architecture behave of tb_bbfifo is
-- Number of user data words for simulation
constant CLK_PERIOD : time := 10 ns;
signal rst : std_logic := '1';
signal clk : std_logic := '1';
signal re : std_logic := '0';
signal we : std_logic := '0';
signal ready : std_logic;
signal avail : std_logic;
signal din : unsigned(7 downto 0) := (others => '0');
signal dout : unsigned(7 downto 0);
signal dout_reg : unsigned(7 downto 0);
begin
inst_bbfifo : entity work.bbfifo
GENERIC MAP
(
depth => 4,
data_width => 8
)
PORT MAP
(
rst => rst,
clk => clk,
re => re,
we => we,
ready => ready,
avail => avail,
din => din,
dout => dout
);
CLK_GEN: process
begin
wait for CLK_PERIOD/2;
clk <= not clk;
end process;
RE_GEN: process
begin
wait for 2*CLK_PERIOD;
wait until rising_edge(clk) and avail = '1';
re <= '0';
dout_reg <= dout;
wait until rising_edge(clk);
re <= '0';
end process;
------------------------------------------------------------------------------------------
STIMULUS: process
begin
wait for 3*CLK_PERIOD;
rst <= '0';
din <= X"10";
wait until rising_edge(clk) and ready = '1';
we <= '1';
wait until rising_edge(clk) and ready = '1';
din <= din + 1;
wait until rising_edge(clk) and ready = '1';
we <= '0';
wait until rising_edge(clk) and ready = '1';
wait until rising_edge(clk) and ready = '1';
we <= '1';
din <= din + 1;
wait until rising_edge(clk) and ready = '1';
din <= din + 1;
wait until rising_edge(clk) and ready = '1';
we <= '0';
wait until rising_edge(clk) and ready = '1';
wait until rising_edge(clk) and ready = '1';
wait until rising_edge(clk) and ready = '1';
wait until rising_edge(clk) and ready = '1';
we <= '1';
din <= din + 1;
wait until rising_edge(clk) and ready = '1';
we <= '1';
din <= din + 1;
wait until rising_edge(clk) and ready = '1';
we <= '1';
din <= din + 1;
wait until rising_edge(clk) and ready = '1';
we <= '1';
din <= din + 1;
wait until rising_edge(clk) and ready = '1';
we <= '1';
din <= din + 1;
wait until rising_edge(clk) and ready = '1';
we <= '1';
din <= din + 1;
wait until rising_edge(clk) and ready = '1';
wait;
end process;
end architecture behave;
lib/misc/tb_ram_wb.vhd
-408
View File
@@ -1,408 +0,0 @@
-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: testbench for system test using Xilinx ML-402
-- Copyright (C) 2007 J. Ahrensfeld
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This library is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
-- For questions and ideas, please contact the author at jens@jayfield.org
-----------------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
use std.textio.all; -- Imports the standard textio package.
ENTITY tb_ram_wb IS
END tb_ram_wb;
ARCHITECTURE behavior OF tb_ram_wb IS
constant CLK_PERIOD : time := 10 ns;
signal CLK_O : std_logic := '1';
signal RST_O : std_logic := '1';
signal CYC_O : std_logic := '0';
signal STB_O : std_logic := '0';
signal WE_O : std_logic := '0';
signal SEL_O : unsigned(3 downto 0) := (others => '1');
signal ACK_I : std_logic;
signal MRDY_O : std_logic := '1';
signal SRDY_I : std_logic;
signal ADDR_O : unsigned(31 downto 0) := (others => '-');
signal DAT_I : unsigned(31 downto 0);
signal DAT_O : unsigned(31 downto 0) := (others => '-');
signal dout_rst : std_logic := '0';
signal dout_reg : unsigned(31 downto 0);
signal dout_cnt : natural range 0 to 255;
BEGIN
inst_ram_wb : entity work.ram_wb
PORT MAP
(
RST_I => RST_O,
CLK_I => CLK_O,
CYC_I => CYC_O,
STB_I => STB_O,
SEL_I => SEL_O,
WE_I => WE_O,
ACK_O => ACK_I,
SRDY_O => SRDY_I,
MRDY_I => MRDY_O,
ADDR_I => ADDR_O,
DAT_I => DAT_O,
DAT_O => DAT_I
);
read_register:
process(CLK_O)
begin
if rising_edge(CLK_O) then
if dout_rst = '1' then
dout_cnt <= 0;
elsif ACK_I = '1' and WE_O = '0' then
dout_reg <= DAT_I;
dout_cnt <= dout_cnt + 1;
end if;
end if;
end process;
CLK_GEN: process
begin
wait for CLK_PERIOD/2;
CLK_O <= not CLK_O;
end process;
STIMULUS: process
begin
wait for 3*CLK_PERIOD;
RST_O <= '0';
-- 8 single cycles
CYC_O <= '1';
STB_O <= '1';
WE_O <= '1';
DAT_O <= X"1234_0000";
ADDR_O <= X"0000_0000";
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
wait until rising_edge(CLK_O) and ACK_I = '1';
CYC_O <= '0';
-- 8-word burst cycle
wait for 3*CLK_PERIOD;
dout_rst <= '1';
wait until rising_edge(CLK_O);
dout_rst <= '0';
CYC_O <= '1';
STB_O <= '1';
WE_O <= '0';
ADDR_O <= X"0000_0000";
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
wait until rising_edge(CLK_O) and dout_cnt = 7;
CYC_O <= '0';
wait for 3*CLK_PERIOD;
wait until rising_edge(CLK_O);
-- 1-word burst cycle
CYC_O <= '1';
STB_O <= '1';
WE_O <= '1';
SEL_O <= "0011";
ADDR_O <= X"0000_0080";
DAT_O <= X"DEADBEEF";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
wait until rising_edge(CLK_O) and ACK_I = '1';
CYC_O <= '0';
wait for 3*CLK_PERIOD;
wait until rising_edge(CLK_O);
-- 1-word burst cycle
CYC_O <= '1';
STB_O <= '1';
WE_O <= '0';
ADDR_O <= X"0000_0080";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
wait until rising_edge(CLK_O) and ACK_I = '1';
CYC_O <= '0';
-- 8-word burst cycle
wait for 3*CLK_PERIOD;
dout_rst <= '1';
wait until rising_edge(CLK_O);
dout_rst <= '0';
CYC_O <= '1';
STB_O <= '1';
WE_O <= '0';
ADDR_O <= X"0000_0000";
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
MRDY_O <= '0';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
MRDY_O <= '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
wait until rising_edge(CLK_O) and dout_cnt = 54;
CYC_O <= '0';
wait;
end process;
END;
lib/misc/tb_rom_wb.vhd
-223
View File
@@ -1,223 +0,0 @@
-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: testbench for system test using Xilinx ML-402
-- Copyright (C) 2007 J. Ahrensfeld
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This library is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
-- For questions and ideas, please contact the author at jens@jayfield.org
-----------------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
use std.textio.all; -- Imports the standard textio package.
ENTITY tb_rom_wb IS
END tb_rom_wb;
ARCHITECTURE behavior OF tb_rom_wb IS
constant CLK_PERIOD : time := 10 ns;
signal CLK_O : std_logic := '1';
signal RST_O : std_logic := '1';
signal CYC_O : std_logic := '0';
signal STB_O : std_logic := '0';
signal ACK_I : std_logic;
signal MRDY_O : std_logic := '1';
signal SRDY_I : std_logic;
signal ADDR_O : unsigned(31 downto 0) := (others => '-');
signal DAT_I : unsigned(31 downto 0);
signal dout_rst : std_logic := '0';
signal dout_reg : unsigned(31 downto 0);
signal dout_cnt : natural range 0 to 255;
BEGIN
inst_rom_wb : entity work.rom_wb
PORT MAP
(
RST_I => RST_O,
CLK_I => CLK_O,
CYC_I => CYC_O,
STB_I => STB_O,
ACK_O => ACK_I,
SRDY_O => SRDY_I,
MRDY_I => MRDY_O,
ADDR_I => ADDR_O,
DAT_O => DAT_I
);
read_register:
process(CLK_O)
begin
if rising_edge(CLK_O) then
if dout_rst = '1' then
dout_cnt <= 0;
elsif ACK_I = '1' then
dout_reg <= DAT_I;
dout_cnt <= dout_cnt + 1;
end if;
end if;
end process;
CLK_GEN: process
begin
wait for CLK_PERIOD/2;
CLK_O <= not CLK_O;
end process;
STIMULUS: process
begin
wait for 3*CLK_PERIOD;
RST_O <= '0';
-- 8-word burst cycle
wait for 3*CLK_PERIOD;
dout_rst <= '1';
wait until rising_edge(CLK_O);
dout_rst <= '0';
CYC_O <= '1';
STB_O <= '1';
ADDR_O <= X"0000_0180";
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
MRDY_O <= '0';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
MRDY_O <= '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
wait until rising_edge(CLK_O) and dout_cnt = 54;
CYC_O <= '0';
wait;
end process;
END;
lib/misc/tb_template.vhd
-63
View File
@@ -1,63 +0,0 @@
-----------------------------------------------------------------------
-- $Header: /tmp/cvsroot/VHDL/lib/misc/tb_template.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
-----------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.MATH_REAL.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE STD.TEXTIO.ALL;
-- LIBRARY WORK;
-- USE.YOURLIB.WHATELSE
ENTITY tb_template IS
END tb_template;
ARCHITECTURE behavior OF tb_template IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT your_comp
GENERIC
(
);
PORT
(
);
END COMPONENT;
--Constants
constant PERIOD : time := 10 ns;
--Inputs
signal clk : STD_LOGIC := '0';
--Outputs
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: your_comp
GENERIC MAP
(
)
PORT MAP
(
);
tb_clk : PROCESS
BEGIN
clk <= not clk;
wait for PERIOD/2;
END PROCESS;
BEGIN
-- Wait 100 ns for global reset to finish
wait for 4*PERIOD;
assert false report "Test finished" severity error;
wait;
END PROCESS;
END tb_template;