This commit was manufactured by cvs2svn to create tag 'EMAC_R01'.
git-svn-id: http://moon:8086/svn/vhdl/tags/EMAC_R01@910 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
@@ -1,13 +0,0 @@
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## NOTE: Do not edit this file.
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||||
##
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vlib work
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vcom -explicit -93 "../src/fifo_ctrl_pkg.vhd"
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vcom -explicit -93 "../src/gray_counter.vhd"
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vcom -explicit -93 "../src/tb_gray_counter.vhd"
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vsim -t 1ps -lib work tb_gray_counter
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||||
view wave
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||||
do {tb_gray_counter.wdo}
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view structure
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||||
view signals
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||||
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run 1us
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||||
@@ -1,29 +0,0 @@
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onerror {resume}
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||||
quietly WaveActivateNextPane {} 0
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||||
add wave -noupdate -format Logic /tb_gray_counter/rst
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||||
add wave -noupdate -format Logic /tb_gray_counter/ce
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||||
add wave -noupdate -format Logic /tb_gray_counter/clk
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||||
add wave -noupdate -divider <NULL>
|
||||
add wave -noupdate -format Literal /tb_gray_counter/bcnt
|
||||
add wave -noupdate -divider <NULL>
|
||||
add wave -noupdate -format Literal /tb_gray_counter/bnxt
|
||||
add wave -noupdate -divider <NULL>
|
||||
add wave -noupdate -format Literal /tb_gray_counter/gcnt
|
||||
add wave -noupdate -divider <NULL>
|
||||
add wave -noupdate -format Literal /tb_gray_counter/gnxt
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 1} {61919 ps} 0}
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||||
configure wave -namecolwidth 150
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configure wave -valuecolwidth 100
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||||
configure wave -justifyvalue left
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||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
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||||
configure wave -datasetprefix 0
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configure wave -rowmargin 4
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configure wave -childrowmargin 2
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configure wave -gridoffset 0
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configure wave -gridperiod 1
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||||
configure wave -griddelta 40
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configure wave -timeline 0
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||||
update
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||||
WaveRestoreZoom {915144 ps} {1004467 ps}
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@@ -1,77 +0,0 @@
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-------------------------------------------------------------------------
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||||
-- Project: FIFO, generic FIFOs written in VHDL
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||||
-- Release 1
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||||
--
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||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
--
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
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||||
--
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||||
-----------------------------------------------------------------------
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||||
|
||||
LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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||||
USE IEEE.NUMERIC_STD.ALL;
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entity dpram_1w1r is
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Generic (
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addr_width : integer := 3;
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||||
data_width : integer := 8
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||||
);
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Port (
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||||
clka : in STD_LOGIC;
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||||
clkb : in STD_LOGIC;
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||||
en_a : in STD_LOGIC;
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||||
en_b : in STD_LOGIC;
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||||
we_a : in STD_LOGIC;
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addr_a : in unsigned (addr_width-1 downto 0);
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||||
addr_b : in unsigned (addr_width-1 downto 0);
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din_a : in unsigned (data_width-1 downto 0);
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dout_b : out unsigned (data_width-1 downto 0)
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);
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end dpram_1w1r;
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architecture Behavioral of dpram_1w1r is
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constant depth : integer := 2**addr_width;
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type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
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signal RAM : RAMtype;
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begin
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process (clka)
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begin
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if clka'event and clka = '1' then
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if en_a = '1' then
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if we_a = '1' then
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RAM(to_integer(addr_a)) <= din_a;
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end if;
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end if;
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end if;
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end process;
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process (clkb)
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begin
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if clkb'event and clkb = '1' then
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if en_b = '1' then
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dout_b <= RAM(to_integer(addr_b));
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end if;
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end if;
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end process;
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||||
|
||||
|
||||
end Behavioral;
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||||
|
||||
@@ -1,117 +0,0 @@
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-------------------------------------------------------------------------
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||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
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||||
-- This file: Dual-ported register file with asynchrous read
|
||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
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||||
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||||
LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.NUMERIC_STD.ALL;
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use work.fifo_ctrl_pkg.all;
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entity fifo_sync_dist is
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Generic (
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addr_width : natural := 4;
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data_width : natural := 8;
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||||
almost_full_thresh : integer := 12;
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almost_empty_thresh : integer := 4
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||||
);
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Port
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||||
(
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rst : in STD_LOGIC;
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||||
clk : in STD_LOGIC;
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||||
we : in STD_LOGIC;
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||||
re : in STD_LOGIC;
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||||
fifo_full : out STD_LOGIC;
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||||
fifo_empty : out STD_LOGIC;
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||||
fifo_afull : out STD_LOGIC;
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||||
fifo_aempty : out STD_LOGIC;
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||||
data_w : in unsigned (data_width-1 downto 0);
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||||
data_r : out unsigned (data_width-1 downto 0)
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||||
);
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end fifo_sync_dist;
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||||
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||||
architecture Behavioral of fifo_sync_dist is
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||||
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||||
signal mem_wr_en : STD_LOGIC;
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signal mem_rd_en : STD_LOGIC;
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||||
signal ptr_w : unsigned (addr_width-1 downto 0);
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signal ptr_r : unsigned (addr_width-1 downto 0);
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signal full : STD_LOGIC;
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signal empty : STD_LOGIC;
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||||
signal almost_full : STD_LOGIC;
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||||
signal almost_empty : STD_LOGIC;
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||||
signal pre_full : STD_LOGIC;
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||||
signal pre_empty : STD_LOGIC;
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||||
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||||
begin
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||||
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||||
mem_wr_en <= not full;
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||||
mem_rd_en <= not pre_empty;
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fifo_full <= full;
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fifo_empty <= empty;
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||||
fifo_afull <= almost_full;
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||||
fifo_aempty <= almost_empty;
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||||
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||||
inst_fifo_sync_ctrl: entity work.fifo_sync_ctrl
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||||
GENERIC MAP
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||||
(
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||||
addr_width => addr_width,
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||||
almost_full_thresh => almost_full_thresh,
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||||
almost_empty_thresh => almost_empty_thresh
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||||
)
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||||
PORT MAP
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||||
(
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||||
rst => rst,
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||||
clk => clk,
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||||
we => we,
|
||||
re => re,
|
||||
ptr_w => ptr_w,
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||||
ptr_r => ptr_r,
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||||
fifo_full => full,
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||||
fifo_empty => empty,
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||||
fifo_pre_full => pre_full,
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||||
fifo_pre_empty => pre_empty,
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||||
fifo_afull => almost_full,
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||||
fifo_aempty => almost_empty
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||||
|
||||
);
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||||
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||||
inst_dpram_1w1r: entity work.dpram_1w1r_dist
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GENERIC MAP (
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||||
addr_width => addr_width,
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||||
data_width => data_width
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||||
)
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PORT MAP(
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clka => clk,
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clkb => clk,
|
||||
en_a => mem_wr_en,
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||||
en_b => mem_rd_en,
|
||||
we_a => we,
|
||||
addr_a => ptr_w,
|
||||
addr_b => ptr_r,
|
||||
din_a => data_w,
|
||||
dout_b => data_r
|
||||
);
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||||
|
||||
end Behavioral;
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||||
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||||
@@ -1,225 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: FIFO, generic FIFOs written in VHDL
|
||||
-- Release 1
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
--
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.MATH_REAL.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
USE STD.TEXTIO.ALL;
|
||||
|
||||
-- LIBRARY WORK;
|
||||
-- USE.YOURLIB.WHATELSE
|
||||
|
||||
ENTITY tb_fifo_async IS
|
||||
END tb_fifo_async;
|
||||
|
||||
ARCHITECTURE behavior OF tb_fifo_async IS
|
||||
|
||||
--Constants
|
||||
constant PERIOD_W : time := 10 ns;
|
||||
constant PERIOD_R : time := 7.5 ns;
|
||||
constant ADDR_WIDTH : integer := 3;
|
||||
constant DATA_WIDTH : integer := 8;
|
||||
|
||||
--Inputs
|
||||
signal rst : STD_LOGIC := '1';
|
||||
signal clk_w : STD_LOGIC := '0';
|
||||
signal clk_r : STD_LOGIC := '0';
|
||||
signal we : STD_LOGIC := '0';
|
||||
signal re : STD_LOGIC := '0';
|
||||
signal din : unsigned (7 downto 0);
|
||||
--Outputs
|
||||
|
||||
signal dout : unsigned (7 downto 0);
|
||||
signal fifo_full : STD_LOGIC;
|
||||
signal fifo_empty : STD_LOGIC;
|
||||
signal fifo_almost_full : STD_LOGIC;
|
||||
signal fifo_almost_empty : STD_LOGIC;
|
||||
|
||||
signal write_en : STD_LOGIC := '0';
|
||||
signal read_en : STD_LOGIC := '0';
|
||||
|
||||
signal ref_r : unsigned (7 downto 0);
|
||||
|
||||
BEGIN
|
||||
|
||||
-- Instantiate the Unit Under Test (UUT)
|
||||
uut: entity work.fifo_async
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => ADDR_WIDTH,
|
||||
data_width => DATA_WIDTH,
|
||||
almost_full_thresh => 6,
|
||||
almost_empty_thresh => 2,
|
||||
allow_full_writes => false,
|
||||
allow_empty_reads => false,
|
||||
do_last_read_update => false
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => rst,
|
||||
clk_w => clk_w,
|
||||
clk_r => clk_r,
|
||||
we => we,
|
||||
re => re,
|
||||
data_w => din,
|
||||
data_r => dout,
|
||||
fifo_full => fifo_full,
|
||||
fifo_empty => fifo_empty,
|
||||
fifo_afull => fifo_almost_full,
|
||||
fifo_aempty => fifo_almost_empty
|
||||
|
||||
);
|
||||
|
||||
tb_clk_w : PROCESS
|
||||
BEGIN
|
||||
clk_w <= not clk_w;
|
||||
wait for PERIOD_W/2;
|
||||
END PROCESS;
|
||||
|
||||
tb_clk_r : PROCESS
|
||||
BEGIN
|
||||
clk_r <= not clk_r;
|
||||
wait for PERIOD_R/2;
|
||||
END PROCESS;
|
||||
|
||||
tb_write : PROCESS
|
||||
BEGIN
|
||||
|
||||
-- Wait 100 ns for global reset to finish
|
||||
wait for 5*PERIOD_W;
|
||||
rst <= '0';
|
||||
wait for 7*PERIOD_W;
|
||||
write_en <= '1';
|
||||
wait for 25*PERIOD_W;
|
||||
write_en <= '0';
|
||||
wait for 7*PERIOD_W;
|
||||
write_en <= '1';
|
||||
wait for 25*PERIOD_W;
|
||||
write_en <= '0';
|
||||
wait for 7*PERIOD_W;
|
||||
write_en <= '1';
|
||||
wait for 1*PERIOD_W;
|
||||
write_en <= '0';
|
||||
wait for 1*PERIOD_W;
|
||||
write_en <= '1';
|
||||
wait for 1*PERIOD_W;
|
||||
write_en <= '0';
|
||||
wait for 3*PERIOD_W;
|
||||
write_en <= '1';
|
||||
wait for 4*PERIOD_W;
|
||||
write_en <= '0';
|
||||
wait for 17*PERIOD_W;
|
||||
write_en <= '1';
|
||||
wait for 55*PERIOD_W;
|
||||
write_en <= '0';
|
||||
wait for 1*PERIOD_W;
|
||||
write_en <= '1';
|
||||
wait for 1*PERIOD_W;
|
||||
write_en <= '0';
|
||||
wait for 3*PERIOD_W;
|
||||
write_en <= '1';
|
||||
wait for 44*PERIOD_W;
|
||||
write_en <= '0';
|
||||
|
||||
wait;
|
||||
|
||||
END PROCESS;
|
||||
|
||||
tb_read : PROCESS
|
||||
BEGIN
|
||||
|
||||
-- Wait 100 ns for global reset to finish
|
||||
wait for 25*PERIOD_R;
|
||||
read_en <= '1';
|
||||
wait for 25*PERIOD_R;
|
||||
read_en <= '0';
|
||||
wait for 25*PERIOD_R;
|
||||
read_en <= '1';
|
||||
wait for 1*PERIOD_R;
|
||||
read_en <= '0';
|
||||
wait for 5*PERIOD_R;
|
||||
read_en <= '1';
|
||||
wait for 1*PERIOD_R;
|
||||
read_en <= '0';
|
||||
wait for 5*PERIOD_R;
|
||||
read_en <= '1';
|
||||
wait for 1*PERIOD_R;
|
||||
read_en <= '0';
|
||||
wait for 5*PERIOD_R;
|
||||
read_en <= '1';
|
||||
wait for 1*PERIOD_R;
|
||||
read_en <= '0';
|
||||
wait for 5*PERIOD_R;
|
||||
read_en <= '1';
|
||||
wait for 1*PERIOD_R;
|
||||
read_en <= '0';
|
||||
wait for 5*PERIOD_R;
|
||||
read_en <= '1';
|
||||
wait for 1*PERIOD_R;
|
||||
read_en <= '0';
|
||||
wait for 5*PERIOD_R;
|
||||
read_en <= '1';
|
||||
wait for 1*PERIOD_R;
|
||||
read_en <= '0';
|
||||
wait for 7*PERIOD_R;
|
||||
read_en <= '1';
|
||||
wait for 15*PERIOD_R;
|
||||
read_en <= '0';
|
||||
wait;
|
||||
|
||||
END PROCESS;
|
||||
|
||||
we <= write_en;
|
||||
|
||||
tb_w : PROCESS(rst, clk_w)
|
||||
BEGIN
|
||||
|
||||
if rst = '1' then
|
||||
din <= (others => '0');
|
||||
elsif rising_edge(clk_w) then
|
||||
if we = '1' and fifo_full = '0' then
|
||||
din <= din + 1;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
END PROCESS;
|
||||
|
||||
re <= read_en;
|
||||
|
||||
tb_r : PROCESS(rst, clk_r)
|
||||
BEGIN
|
||||
|
||||
if rst = '1' then
|
||||
ref_r <= (others => '0');
|
||||
elsif rising_edge(clk_r) then
|
||||
if re = '1' and fifo_empty = '0' then
|
||||
assert ref_r = dout report "FIFO read error!" severity failure;
|
||||
ref_r <= ref_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
END PROCESS;
|
||||
|
||||
END behavior;
|
||||
@@ -1,206 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: FIFO, generic FIFOs written in VHDL
|
||||
-- Release 1
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
--
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.MATH_REAL.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
USE STD.TEXTIO.ALL;
|
||||
|
||||
-- LIBRARY WORK;
|
||||
-- USE.YOURLIB.WHATELSE
|
||||
|
||||
ENTITY tb_fifo_sync IS
|
||||
END tb_fifo_sync;
|
||||
|
||||
ARCHITECTURE behavior OF tb_fifo_sync IS
|
||||
|
||||
--Constants
|
||||
constant PERIOD : time := 10 ns;
|
||||
constant ADDR_WIDTH : integer := 3;
|
||||
constant DATA_WIDTH : integer := 8;
|
||||
|
||||
--Inputs
|
||||
signal rst : STD_LOGIC := '1';
|
||||
signal clk : STD_LOGIC := '0';
|
||||
signal we : STD_LOGIC := '0';
|
||||
signal re : STD_LOGIC := '0';
|
||||
signal din : unsigned (7 downto 0);
|
||||
--Outputs
|
||||
|
||||
signal dout : unsigned (7 downto 0);
|
||||
signal fifo_full : STD_LOGIC;
|
||||
signal fifo_empty : STD_LOGIC;
|
||||
signal fifo_almost_full : STD_LOGIC;
|
||||
signal fifo_almost_empty : STD_LOGIC;
|
||||
|
||||
signal write_en : STD_LOGIC := '0';
|
||||
signal read_en : STD_LOGIC := '0';
|
||||
|
||||
signal ref_r : unsigned (7 downto 0) := (others => '0');
|
||||
|
||||
BEGIN
|
||||
|
||||
-- Instantiate the Unit Under Test (UUT)
|
||||
uut: entity work.fifo_sync
|
||||
GENERIC MAP
|
||||
(
|
||||
data_width => DATA_WIDTH,
|
||||
addr_width => ADDR_WIDTH,
|
||||
almost_full_thresh => 6,
|
||||
almost_empty_thresh => 2
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
we => we,
|
||||
re => re,
|
||||
data_w => din,
|
||||
data_r => dout,
|
||||
fifo_full => fifo_full,
|
||||
fifo_empty => fifo_empty,
|
||||
fifo_afull => fifo_almost_full,
|
||||
fifo_aempty => fifo_almost_empty
|
||||
|
||||
);
|
||||
|
||||
tb_clk : PROCESS
|
||||
BEGIN
|
||||
clk <= not clk;
|
||||
wait for PERIOD/2;
|
||||
END PROCESS;
|
||||
|
||||
tb_write : PROCESS
|
||||
BEGIN
|
||||
|
||||
-- Wait 100 ns for global reset to finish
|
||||
wait for 5*PERIOD;
|
||||
rst <= '0';
|
||||
wait for 7*PERIOD;
|
||||
write_en <= '1';
|
||||
wait for 25*PERIOD;
|
||||
write_en <= '0';
|
||||
wait for 7*PERIOD;
|
||||
write_en <= '1';
|
||||
wait for 25*PERIOD;
|
||||
write_en <= '0';
|
||||
wait for 7*PERIOD;
|
||||
write_en <= '1';
|
||||
wait for 1*PERIOD;
|
||||
write_en <= '0';
|
||||
wait for 1*PERIOD;
|
||||
write_en <= '1';
|
||||
wait for 1*PERIOD;
|
||||
write_en <= '0';
|
||||
wait for 3*PERIOD;
|
||||
write_en <= '1';
|
||||
wait for 4*PERIOD;
|
||||
write_en <= '0';
|
||||
wait for 17*PERIOD;
|
||||
write_en <= '1';
|
||||
wait for 25*PERIOD;
|
||||
write_en <= '0';
|
||||
|
||||
wait;
|
||||
|
||||
END PROCESS;
|
||||
|
||||
tb_read : PROCESS
|
||||
BEGIN
|
||||
|
||||
-- Wait 100 ns for global reset to finish
|
||||
wait for 25*PERIOD;
|
||||
read_en <= '1';
|
||||
wait for 25*PERIOD;
|
||||
read_en <= '0';
|
||||
wait for 25*PERIOD;
|
||||
read_en <= '1';
|
||||
wait for 1*PERIOD;
|
||||
read_en <= '0';
|
||||
wait for 5*PERIOD;
|
||||
read_en <= '1';
|
||||
wait for 1*PERIOD;
|
||||
read_en <= '0';
|
||||
wait for 5*PERIOD;
|
||||
read_en <= '1';
|
||||
wait for 1*PERIOD;
|
||||
read_en <= '0';
|
||||
wait for 5*PERIOD;
|
||||
read_en <= '1';
|
||||
wait for 1*PERIOD;
|
||||
read_en <= '0';
|
||||
wait for 5*PERIOD;
|
||||
read_en <= '1';
|
||||
wait for 1*PERIOD;
|
||||
read_en <= '0';
|
||||
wait for 5*PERIOD;
|
||||
read_en <= '1';
|
||||
wait for 1*PERIOD;
|
||||
read_en <= '0';
|
||||
wait for 5*PERIOD;
|
||||
read_en <= '1';
|
||||
wait for 1*PERIOD;
|
||||
read_en <= '0';
|
||||
wait for 7*PERIOD;
|
||||
read_en <= '1';
|
||||
wait for 20*PERIOD;
|
||||
read_en <= '0';
|
||||
|
||||
wait;
|
||||
|
||||
END PROCESS;
|
||||
|
||||
we <= write_en and not fifo_full;
|
||||
|
||||
tb_w : PROCESS(rst, clk)
|
||||
BEGIN
|
||||
|
||||
if rst = '1' then
|
||||
din <= (others => '0');
|
||||
elsif rising_edge(clk) then
|
||||
if we = '1' then
|
||||
din <= din + 1;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
END PROCESS;
|
||||
|
||||
re <= read_en and not fifo_empty;
|
||||
|
||||
tb_r : PROCESS(rst, clk)
|
||||
BEGIN
|
||||
|
||||
if rst = '1' then
|
||||
ref_r <= (others => '0');
|
||||
elsif rising_edge(clk) then
|
||||
if re = '1' then
|
||||
assert ref_r = dout report "FIFO read error!" severity failure;
|
||||
ref_r <= ref_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
END PROCESS;
|
||||
|
||||
END behavior;
|
||||
@@ -1,85 +0,0 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 17:16:42 13.05.2007
|
||||
-- Design Name: tb_gray_counter
|
||||
-- Module Name: tb_gray_counter.vhd
|
||||
-- Project Name: gray_counter package
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: /tmp/cvsroot/VHDL/lib/FIFO/src/tb_gray_counter.vhd,v 1.2 2010-02-13 10:50:47 Jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.MATH_REAL.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
USE STD.TEXTIO.ALL;
|
||||
|
||||
LIBRARY WORK;
|
||||
USE WORK.FIFO_CTRL_PKG.ALL;
|
||||
|
||||
ENTITY tb_gray_counter IS
|
||||
END tb_gray_counter;
|
||||
|
||||
ARCHITECTURE behavior OF tb_gray_counter IS
|
||||
|
||||
constant PERIOD : time := 10 ns;
|
||||
constant WIDTH : integer := 3;
|
||||
|
||||
--Signals
|
||||
signal gcnt : unsigned (WIDTH-1 downto 0) := to_unsigned(0, WIDTH);
|
||||
signal bcnt : unsigned (WIDTH-1 downto 0) := to_unsigned(0, WIDTH);
|
||||
signal gnxt : unsigned (WIDTH-1 downto 0) := to_unsigned(0, WIDTH);
|
||||
signal bnxt : unsigned (WIDTH-1 downto 0) := to_unsigned(0, WIDTH);
|
||||
signal rst : STD_LOGIC := '1';
|
||||
signal clk : STD_LOGIC := '0';
|
||||
signal ce : STD_LOGIC := '0';
|
||||
|
||||
BEGIN
|
||||
|
||||
inst_gray_counter : entity work.gray_counter
|
||||
generic map (width => WIDTH)
|
||||
port map (
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
ce => ce,
|
||||
bcnt => bcnt,
|
||||
bnxt => bnxt,
|
||||
gcnt => gcnt,
|
||||
gnxt => gnxt
|
||||
);
|
||||
|
||||
tb_clk : PROCESS
|
||||
BEGIN
|
||||
clk <= not clk;
|
||||
wait for PERIOD/2;
|
||||
END PROCESS;
|
||||
|
||||
tb_counter : PROCESS
|
||||
|
||||
BEGIN
|
||||
|
||||
wait for 4*PERIOD;
|
||||
rst <= '0';
|
||||
wait until rising_edge(clk);
|
||||
ce <= '1';
|
||||
wait for 2*PERIOD;
|
||||
wait until rising_edge(clk);
|
||||
ce <= '0';
|
||||
wait for 3*PERIOD;
|
||||
wait until rising_edge(clk);
|
||||
ce <= '1';
|
||||
wait until rising_edge(clk);
|
||||
ce <= '0';
|
||||
wait until rising_edge(clk);
|
||||
ce <= '1';
|
||||
|
||||
wait;
|
||||
|
||||
END PROCESS;
|
||||
|
||||
END behavior;
|
||||
Reference in New Issue
Block a user