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- simplification for coef-array

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git-svn-id: http://moon:8086/svn/vhdl/trunk@190 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2009-01-02 16:48:36 +00:00
parent 0ed3e397f2
commit ba703d81df
1 changed files with 18 additions and 30 deletions
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lib/radio/ddc/src/ddc.vhd
+18 -30
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@@ -158,10 +158,12 @@ ARCHITECTURE behavior OF ddc IS
constant cfir_nbits_stages : integer := cfir_nbits_in; constant cfir_nbits_stages : integer := cfir_nbits_in;
constant cfir_nbits_stages_frac : integer := cfir_nbits_in_frac; constant cfir_nbits_stages_frac : integer := cfir_nbits_in_frac;
constant ntaps_needed : integer := ntaps_addr(cfir_ntaps, cfir_mode);
SIGNAL cfir_h_din_i : sfixed(shi(cfir_nbits_stages, cfir_nbits_stages_frac) downto slo(cfir_nbits_stages, cfir_nbits_stages_frac)); SIGNAL cfir_h_din_i : sfixed(shi(cfir_nbits_stages, cfir_nbits_stages_frac) downto slo(cfir_nbits_stages, cfir_nbits_stages_frac));
SIGNAL cfir_h_din_q : sfixed(shi(cfir_nbits_stages, cfir_nbits_stages_frac) downto slo(cfir_nbits_stages, cfir_nbits_stages_frac)); SIGNAL cfir_h_din_q : sfixed(shi(cfir_nbits_stages, cfir_nbits_stages_frac) downto slo(cfir_nbits_stages, cfir_nbits_stages_frac));
SIGNAL cfir_h_addr_i : natural range 0 to ntaps_addr(cfir_ntaps, cfir_mode)-1; SIGNAL cfir_h_addr_i : natural range 0 to ntaps_needed-1;
SIGNAL cfir_h_addr_q : natural range 0 to ntaps_addr(cfir_ntaps, cfir_mode)-1; SIGNAL cfir_h_addr_q : natural range 0 to ntaps_needed-1;
SIGNAL cfir_dout_i : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac)); SIGNAL cfir_dout_i : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
SIGNAL cfir_dout_q : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac)); SIGNAL cfir_dout_q : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
SIGNAL cfir_vld_i : std_logic; SIGNAL cfir_vld_i : std_logic;
@@ -169,36 +171,22 @@ ARCHITECTURE behavior OF ddc IS
SIGNAL cfir_ready_i : std_logic; SIGNAL cfir_ready_i : std_logic;
SIGNAL cfir_ready_q : std_logic; SIGNAL cfir_ready_q : std_logic;
type sfixed_array_t is array (natural range <>, integer range <>) of STD_LOGIC; constant cfir_coef : real_array_t(0 to ntaps_addr(cfir_ntaps, cfir_mode)-1) := FilterCoef_Lowpass(cfir_ntaps, 0.1, 1.0)(0 to ntaps_addr(cfir_ntaps, cfir_mode)-1);
function to_sfixed_array(x : real_array_t; proto : sfixed) return sfixed_array_t is
variable res : sfixed_array_t(0 to x'length-1, proto'range); type h_mem_t is array (0 to cfir_ntaps-1) of sfixed(shi(cfir_nbits_stages, cfir_nbits_stages_frac) downto slo(cfir_nbits_stages, cfir_nbits_stages_frac));
variable tt : sfixed(proto'range);
function to_h_mem(coef_real : real_array_t; ntaps : integer; proto : sfixed) return h_mem_t is
variable res : h_mem_t;
begin begin
for i in x'range loop for i in 0 to ntaps-1 loop
tt := to_sfixed(x(i), proto); res(i) := to_sfixed(coef_real(i), proto, fixed_wrap, fixed_round);
for j in proto'range loop
res(i,j) := tt(j);
end loop;
end loop; end loop;
return res; return res;
end to_sfixed_array; end to_h_mem;
-------------------------------------------------------------------------------
-- sfixed <= sfixed_array(i)
function to_sfixed(src : sfixed_array_t; index : integer) return sfixed is
variable dst : sfixed(src'range(2));
begin
for j in src'range(2) loop
dst(j) := src(index, j);
end loop;
return dst;
end to_sfixed;
constant cfir_coef : sfixed_array_t(0 to ntaps_addr(cfir_ntaps, cfir_mode)-1, shi(cfir_nbits_stages, cfir_nbits_stages_frac) downto slo(cfir_nbits_stages, cfir_nbits_stages_frac))
:= to_sfixed_array(FilterCoef_Lowpass(cfir_ntaps, 0.1, 1.0)(0 to ntaps_addr(cfir_ntaps, cfir_mode)-1), cfir_h_din_i);
CONSTANT h_mem_i : h_mem_t := to_h_mem(cfir_coef, ntaps_needed, cfir_h_din_i);
CONSTANT h_mem_q : h_mem_t := to_h_mem(cfir_coef, ntaps_needed, cfir_h_din_q);
SIGNAL mix_dout_i : sfixed(shi(lo_nbits_out, lo_nbits_out_frac) downto slo(lo_nbits_out, lo_nbits_out_frac)); SIGNAL mix_dout_i : sfixed(shi(lo_nbits_out, lo_nbits_out_frac) downto slo(lo_nbits_out, lo_nbits_out_frac));
SIGNAL mix_dout_q : sfixed(shi(lo_nbits_out, lo_nbits_out_frac) downto slo(lo_nbits_out, lo_nbits_out_frac)); SIGNAL mix_dout_q : sfixed(shi(lo_nbits_out, lo_nbits_out_frac) downto slo(lo_nbits_out, lo_nbits_out_frac));
@@ -347,7 +335,7 @@ cfir_coef_mem_i:
process(clk) process(clk)
begin begin
if rising_edge(clk) then if rising_edge(clk) then
cfir_h_din_i <= to_sfixed(cfir_coef, cfir_h_addr_i); cfir_h_din_i <= h_mem_i(cfir_h_addr_i);
end if; end if;
end process; end process;
@@ -355,7 +343,7 @@ cfir_coef_mem_q:
process(clk) process(clk)
begin begin
if rising_edge(clk) then if rising_edge(clk) then
cfir_h_din_q <= to_sfixed(cfir_coef, cfir_h_addr_q); cfir_h_din_q <= h_mem_q(cfir_h_addr_q);
end if; end if;
end process; end process;