diff --git a/Common/sim/ModelSim SE .lnk b/Common/sim/ModelSim SE .lnk new file mode 100644 index 0000000..ecadd02 Binary files /dev/null and b/Common/sim/ModelSim SE .lnk differ diff --git a/Common/sim/compile_simprim.do b/Common/sim/compile_simprim.do new file mode 100644 index 0000000..0d97d06 --- /dev/null +++ b/Common/sim/compile_simprim.do @@ -0,0 +1,8 @@ +vlib simprim + +set XILINX C:/Programme/Xilinx101/ISE + +vcom -93 -work simprim $XILINX/vhdl/src/simprims/simprim_Vcomponents_mti.vhd +vcom -93 -work simprim $XILINX/vhdl/src/simprims/simprim_Vpackage_mti.vhd +vcom -93 -work simprim $XILINX/vhdl/src/simprims/simprim_SMODEL_mti.vhd +vcom -93 -work simprim $XILINX/vhdl/src/simprims/simprim_VITAL_mti.vhd diff --git a/Common/sim/compile_unisim.do b/Common/sim/compile_unisim.do new file mode 100644 index 0000000..6e91db1 --- /dev/null +++ b/Common/sim/compile_unisim.do @@ -0,0 +1,8 @@ +vlib unisim + +set XILINX C:/Programme/Xilinx101/ISE + +vcom -93 -work unisim $XILINX/vhdl/src/unisims/unisim_vpkg.vhd +vcom -93 -work unisim $XILINX/vhdl/src/unisims/unisim_vcomp.vhd +vcom -93 -work unisim $XILINX/vhdl/src/unisims/unisim_smodel.vhd +vcom -93 -work unisim $XILINX/vhdl/src/unisims/unisim_vital.vhd diff --git a/Common/ucf/ml402.ucf b/Common/ucf/ml402.ucf new file mode 100644 index 0000000..318e778 --- /dev/null +++ b/Common/ucf/ml402.ucf @@ -0,0 +1,675 @@ +# +# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" +# SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR +# XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION +# AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION +# OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS +# IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, +# AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE +# FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY +# WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE +# IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR +# REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF +# INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE. +# +# (c) Copyright 2005 Xilinx, Inc. +# All rights reserved. +# + +# Bus clock nets +NET "sys_clk" TNM_NET = "sys_clk"; +NET "tft_clk" TNM_NET = "tft_clk"; +NET sys_clk_in TNM_NET = "sys_clk_in"; +TIMESPEC "TSSYSCLK" = PERIOD "sys_clk_in" 9.9 ns HIGH 50 %; + +NET sys_clk_in LOC = AE14; +NET sys_clk_in IOSTANDARD = LVCMOS33; +NET sys_rst_in LOC = D6; +NET sys_rst_in PULLUP; +NET sys_rst_in TIG; + +NET uart_RX LOC = W2; +NET uart_RX IOSTANDARD = LVCMOS33; +NET uart_RX TIG; +NET uart_TX LOC = W1; +NET uart_TX IOSTANDARD = LVCMOS33; +NET uart_TX TIG; + +NET ext_irq TIG; + +# Reset timing ignore - treat as async paths +NET sys_rst TIG; +NET opb_v20_0_OPB_Rst TIG; +NET lmb_v10_1_OPB_Rst TIG; +NET lmb_v10_0_OPB_Rst TIG; +NET opb_v20_0_Debug_SYS_Rst TIG; +NET Debug_Rst TIG; +NET plb_v34_0_PLB_Rst TIG; +NET dcm_locked TIG; + +# Locate DCM/BUFG - Tools can probably figure them out automatically +# but just LOC them down to be safe +INST dcm_0/dcm_0/DCM_ADV_INST LOC = DCM_ADV_X0Y2; +INST dcm_1/dcm_1/DCM_ADV_INST LOC = DCM_ADV_X0Y4; +INST dcm_2/dcm_2/DCM_ADV_INST LOC = DCM_ADV_X0Y1; + +INST dcm_0/dcm_0/CLK0_BUFG_INST LOC = BUFGCTRL_X0Y0; +INST dcm_0/dcm_0/CLK90_BUFG_INST LOC = BUFGCTRL_X0Y1; +INST dcm_0/dcm_0/CLKDV_BUFG_INST LOC = BUFGCTRL_X0Y2; + +INST dcm_1/dcm_1/CLK0_BUFG_INST LOC = BUFGCTRL_X0Y31; +INST dcm_1/dcm_1/CLK90_BUFG_INST LOC = BUFGCTRL_X0Y30; + +//////////////////////////////////////////////////////////////////////////// +// Buttons, LEDs, and DIP Switches +//////////////////////////////////////////////////////////////////////////// + +# GPLED 0-3 +NET gpio<0> LOC = G5; #GPLED0 +NET gpio<1> LOC = G6; #GPLED1 +NET gpio<2> LOC = A11; #GPLED2 +NET gpio<3> LOC = A12; #GPLED3 +# North-East-South-West-Center LEDs +NET gpio<4> LOC = C6; # C LED +NET gpio<5> LOC = F9; # W LED +NET gpio<6> LOC = A5; # S LED +NET gpio<7> LOC = E10; # E LED +NET gpio<8> LOC = E2; # N LED +# North-East-South-West-Center Buttons +NET gpio<9> LOC = B6; # C Button +NET gpio<10> LOC = E9; # W Button +NET gpio<11> LOC = A6; # S Button +NET gpio<12> LOC = F10; # E Button +NET gpio<13> LOC = E7; # N Button +# Dip Switches 1-8 +NET gpio<14> LOC = U24; # DIP SW 8 +NET gpio<15> LOC = U25; # DIP SW 7 +NET gpio<16> LOC = V23; # DIP SW 6 +NET gpio<17> LOC = U23; # DIP SW 5 +NET gpio<18> LOC = U26; # DIP SW 4 +NET gpio<19> LOC = T26; # DIP SW 3 +NET gpio<20> LOC = R19; # DIP SW 2 +NET gpio<21> LOC = R20; # DIP SW 1 +NET gpio<14> IOSTANDARD = LVCMOS33; +NET gpio<15> IOSTANDARD = LVCMOS33; +NET gpio<16> IOSTANDARD = LVCMOS33; +NET gpio<17> IOSTANDARD = LVCMOS33; +NET gpio<18> IOSTANDARD = LVCMOS33; +NET gpio<19> IOSTANDARD = LVCMOS33; +NET gpio<20> IOSTANDARD = LVCMOS33; +NET gpio<21> IOSTANDARD = LVCMOS33; +#SMA Connectors +NET gpio<22> LOC = C12; # SMA_IN_N +NET gpio<23> LOC = C13; # SMA_IN_P +NET gpio<24> LOC = D7; # SMA_OUT_N +NET gpio<25> LOC = D8; # SMA_OUT_P +NET gpio<26> LOC = AD12;# USERCLK +NET gpio<26> IOSTANDARD = LVCMOS33; + +NET "gpio<*>" PULLDOWN; +NET "gpio<*>" TIG; +NET "gpio<*>" SLEW = SLOW; +NET "gpio<*>" DRIVE = 2; + +NET "gpio<22>" SLEW = FAST; +NET "gpio<22>" DRIVE = 12; +NET "gpio<23>" SLEW = FAST; +NET "gpio<23>" DRIVE = 12; +NET "gpio<24>" SLEW = FAST; +NET "gpio<24>" DRIVE = 12; +NET "gpio<25>" SLEW = FAST; +NET "gpio<25>" DRIVE = 12; + +NET "gpio2_d_out<*>" TIG; +NET "gpio2_t_out<*>" TIG; +NET "gpio2_in<*>" TIG; + +#------------------------------------------------------------------------------ +# IO Pad Location Constraints / Properties for PS/2 Ports +#------------------------------------------------------------------------------ + +#Keyboard +NET ps2_keyb_clk LOC = D2; +NET ps2_keyb_clk SLEW = SLOW; +NET ps2_keyb_clk DRIVE = 2; +NET ps2_keyb_clk TIG; +NET ps2_keyb_data LOC = G9; +NET ps2_keyb_data SLEW = SLOW; +NET ps2_keyb_data DRIVE = 2; +NET ps2_keyb_data TIG; + +#Mouse +NET ps2_mouse_clk LOC = B14; +NET ps2_mouse_clk SLEW = SLOW; +NET ps2_mouse_clk DRIVE = 2; +NET ps2_mouse_clk TIG; +NET ps2_mouse_data LOC = C14; +NET ps2_mouse_data SLEW = SLOW; +NET ps2_mouse_data DRIVE = 2; +NET ps2_mouse_data TIG; + +#------------------------------------------------------------------------------ +# IO Pad Location Constraints / Properties for IIC Controller +#------------------------------------------------------------------------------ + +NET iic_scl LOC = A17; +NET iic_sda LOC = B17; +NET iic_scl SLEW = SLOW; +NET iic_scl DRIVE = 6; +NET iic_scl TIG; +NET iic_sda SLEW = SLOW; +NET iic_sda DRIVE = 6; +NET iic_sda TIG; + +#------------------------------------------------------------------------------ +# IO Pad Location Constraints / Properties for AC97 Sound Controller +#------------------------------------------------------------------------------ + +NET ac97_bit_clk LOC = AE10; +NET ac97_bit_clk IOSTANDARD = LVCMOS33; +NET ac97_bit_clk PERIOD = 80; +NET ac97_sdata_in LOC = AD16; +NET ac97_sdata_in IOSTANDARD = LVCMOS33; +NET ac97_reset_n LOC = AD10; +NET ac97_reset_n IOSTANDARD = LVCMOS33; +NET ac97_reset_n TIG; +NET ac97_sdata_out LOC = C8; +NET ac97_sync LOC = D9; + +#------------------------------------------------------------------------------ +# IO Pad Location Constraints / Properties for System ACE MPU / USB +#------------------------------------------------------------------------------ + +NET sysace_clk_in LOC = AF11; +NET sysace_clk_in IOSTANDARD = LVCMOS33; +NET sysace_clk_in TNM_NET = "sysace_clk_in"; +# Leave 1 ns margin +TIMESPEC "TSSYSACE" = PERIOD "sysace_clk_in" 29 ns; + +NET sace_usb_a<0> LOC = U22; +NET sace_usb_a<1> LOC = Y10; +NET sace_usb_a<2> LOC = AA10; +NET sace_usb_a<3> LOC = AC7; +NET sace_usb_a<4> LOC = Y7; +NET sace_usb_a<5> LOC = AA9; +NET sace_usb_a<6> LOC = Y9; +NET sace_usb_a<*> IOSTANDARD = LVCMOS33; +NET sace_usb_a<*> SLEW = FAST; +NET sace_usb_a<*> DRIVE = 8; +NET sace_mpce LOC = AD5; +NET sace_mpce IOSTANDARD = LVCMOS33; +NET sace_mpce SLEW = FAST; +NET sace_mpce DRIVE = 8; +NET sace_usb_d<0> LOC = AB7; +NET sace_usb_d<1> LOC = AC9; +NET sace_usb_d<2> LOC = AB9; +NET sace_usb_d<3> LOC = AE6; +NET sace_usb_d<4> LOC = AD6; +NET sace_usb_d<5> LOC = AF9; +NET sace_usb_d<6> LOC = AE9; +NET sace_usb_d<7> LOC = AD8; +NET sace_usb_d<8> LOC = AC8; +NET sace_usb_d<9> LOC = AF4; +NET sace_usb_d<10> LOC = AE4; +NET sace_usb_d<11> LOC = AD3; +NET sace_usb_d<12> LOC = AC3; +NET sace_usb_d<13> LOC = AF6; +NET sace_usb_d<14> LOC = AF5; +NET sace_usb_d<15> LOC = AA7; +NET sace_usb_d<*> IOSTANDARD = LVCMOS33; +NET sace_usb_d<*> SLEW = FAST; +NET sace_usb_d<*> DRIVE = 8; +NET sace_usb_d<*> PULLDOWN; +NET sace_usb_oen LOC = AA8; +NET sace_usb_oen IOSTANDARD = LVCMOS33; +NET sace_usb_oen SLEW = FAST; +NET sace_usb_oen DRIVE = 8; +NET sace_usb_wen LOC = Y8; +NET sace_usb_wen IOSTANDARD = LVCMOS33; +NET sace_usb_wen SLEW = FAST; +NET sace_usb_wen DRIVE = 8; +NET sysace_mpirq LOC = AD4; +NET sysace_mpirq IOSTANDARD = LVCMOS33; +NET sysace_mpirq TIG; +NET sysace_mpirq PULLDOWN; + +NET usb_csn LOC = AF10; +NET usb_csn IOSTANDARD = LVCMOS33; +NET usb_csn SLEW = FAST; +NET usb_csn DRIVE = 8; +NET usb_hpi_reset_n LOC = A7; +NET usb_hpi_reset_n IOSTANDARD = LVCMOS25; +NET usb_hpi_reset_n TIG; +NET usb_hpi_int LOC = V5; +NET usb_hpi_int IOSTANDARD = LVCMOS33; +NET usb_hpi_int TIG; +NET usb_hpi_int PULLDOWN; + +#------------------------------------------------------------------------------ +# IO Pad Location Constraints / Properties for DDR Controllers +#------------------------------------------------------------------------------ + +NET ddr_ad<0> LOC = C26; # DDR_A0 +NET ddr_ad<1> LOC = E17; # DDR_A1 +NET ddr_ad<2> LOC = D18; # DDR_A2 +NET ddr_ad<3> LOC = C19; # DDR_A3 +NET ddr_ad<4> LOC = F17; # DDR_A4 +NET ddr_ad<5> LOC = B18; # DDR_A5 +NET ddr_ad<6> LOC = B20; # DDR_A6 +NET ddr_ad<7> LOC = C20; # DDR_A7 +NET ddr_ad<8> LOC = D20; # DDR_A8 +NET ddr_ad<9> LOC = C21; # DDR_A9 +NET ddr_ad<10> LOC = A18; # DDR_A10 +NET ddr_ad<11> LOC = B21; # DDR_A11 +NET ddr_ad<12> LOC = A24; # DDR_A12 +NET ddr_ba<0> LOC = B12; # DDR_BA0 +NET ddr_ba<1> LOC = A16; # DDR_BA1 +NET ddr_casb LOC = F23; # DDR_CAS_N +NET ddr_cke LOC = G22; # DDR_CKE +NET ddr_csb LOC = G21; # DDR_CS_N +NET ddr_rasb LOC = F24; # DDR_RAS_N +NET ddr_web LOC = A23; # DDR_WE_N + +NET ddr_clk LOC = A10; # DDR_CK1_P +NET ddr_clk_fb LOC = B13; # DDR_CK1_P (FEEDBACK) +NET ddr_clkb LOC = B10; # DDR_CK1_N + +NET ddr_dm<0> LOC = G19; # DDR_DM0 +NET ddr_dm<1> LOC = G24; # DDR_DM1 +NET ddr_dm<2> LOC = G20; # DDR_DM2 +NET ddr_dm<3> LOC = C22; # DDR_DM3 + +NET ddr_dqs<0> LOC = D25; # DDR_DQS0 +NET ddr_dqs<1> LOC = G18; # DDR_DQS1 +NET ddr_dqs<2> LOC = G17; # DDR_DQS2 +NET ddr_dqs<3> LOC = D26; # DDR_DQS3 + +NET ddr_dq<0> LOC = H20; # DDR_D0 +NET ddr_dq<1> LOC = E23; # DDR_D1 +NET ddr_dq<2> LOC = H26; # DDR_D2 +NET ddr_dq<3> LOC = H22; # DDR_D3 +NET ddr_dq<4> LOC = E25; # DDR_D4 +NET ddr_dq<5> LOC = E26; # DDR_D5 +NET ddr_dq<6> LOC = F26; # DDR_D6 +NET ddr_dq<7> LOC = E24; # DDR_D7 +NET ddr_dq<8> LOC = E20; # DDR_D8 +NET ddr_dq<9> LOC = A22; # DDR_D9 +NET ddr_dq<10> LOC = C23; # DDR_D10 +NET ddr_dq<11> LOC = C24; # DDR_D11 +NET ddr_dq<12> LOC = A20; # DDR_D12 +NET ddr_dq<13> LOC = A21; # DDR_D13 +NET ddr_dq<14> LOC = D24; # DDR_D14 +NET ddr_dq<15> LOC = E18; # DDR_D15 +NET ddr_dq<16> LOC = F18; # DDR_D16 +NET ddr_dq<17> LOC = A19; # DDR_D17 +NET ddr_dq<18> LOC = F19; # DDR_D18 +NET ddr_dq<19> LOC = B23; # DDR_D19 +NET ddr_dq<20> LOC = E21; # DDR_D20 +NET ddr_dq<21> LOC = D22; # DDR_D21 +NET ddr_dq<22> LOC = D23; # DDR_D22 +NET ddr_dq<23> LOC = B24; # DDR_D23 +NET ddr_dq<24> LOC = E22; # DDR_D24 +NET ddr_dq<25> LOC = F20; # DDR_D25 +NET ddr_dq<26> LOC = H23; # DDR_D26 +NET ddr_dq<27> LOC = G25; # DDR_D27 +NET ddr_dq<28> LOC = G26; # DDR_D28 +NET ddr_dq<29> LOC = H25; # DDR_D29 +NET ddr_dq<30> LOC = H24; # DDR_D30 +NET ddr_dq<31> LOC = H21; # DDR_D31 + +NET ddr_ad<*> IOSTANDARD = SSTL2_I; +NET ddr_ba<*> IOSTANDARD = SSTL2_I; +NET ddr_casb IOSTANDARD = SSTL2_I; +NET ddr_cke IOSTANDARD = SSTL2_I; +NET ddr_clk IOSTANDARD = SSTL2_I; +NET ddr_clk_fb IOSTANDARD = LVCMOS25; +NET ddr_clkb IOSTANDARD = SSTL2_I; +NET ddr_casb IOSTANDARD = SSTL2_I; +NET ddr_csb IOSTANDARD = SSTL2_I; +NET ddr_rasb IOSTANDARD = SSTL2_I; +NET ddr_web IOSTANDARD = SSTL2_I; + +NET ddr_dqs<*> IOSTANDARD = SSTL2_II; +NET ddr_dm<*> IOSTANDARD = SSTL2_II; +NET ddr_dq<*> IOSTANDARD = SSTL2_II; + +// Timing Constraint for DDR Feedback Clock +NET "ddr_clk_fb" TNM_NET = "ddr_clk_fb"; +TIMESPEC "TSDDR_FB" = PERIOD "ddr_clk_fb" 9.9 ns; + +#------------------------------------------------------------------------------ +# IO Pad Location Constraints / Properties for TFT VGA LCD Controller +#------------------------------------------------------------------------------ + +NET tft_lcd_b<0> LOC = L26; # VGA_B2 +NET tft_lcd_b<0> IOSTANDARD = LVCMOS33; +NET tft_lcd_b<1> LOC = C5; # VGA_B3 +NET tft_lcd_b<2> LOC = C7; # VGA_B4 +NET tft_lcd_b<3> LOC = B7; # VGA_B5 +NET tft_lcd_b<4> LOC = G8; # VGA_B6 +NET tft_lcd_b<5> LOC = F8; # VGA_B7 +NET tft_lcd_b<*> SLEW = FAST; +NET tft_lcd_b<*> DRIVE = 8; + +NET tft_lcd_clk LOC = AF8; +NET tft_lcd_clk IOSTANDARD = LVDCI_33; +NET tft_lcd_clk SLEW = FAST; +NET tft_lcd_clk DRIVE = 8; + +NET tft_lcd_g<0> LOC = M20; # VGA_G2 +NET tft_lcd_g<0> IOSTANDARD = LVCMOS33; +NET tft_lcd_g<1> LOC = E4; # VGA_G3 +NET tft_lcd_g<2> LOC = D3; # VGA_G4 +NET tft_lcd_g<3> LOC = H7; # VGA_G5 +NET tft_lcd_g<4> LOC = H8; # VGA_G6 +NET tft_lcd_g<5> LOC = C1; # VGA_G7 +NET tft_lcd_g<*> SLEW = FAST; +NET tft_lcd_g<*> DRIVE = 8; + +NET tft_lcd_hsync LOC = C10; +NET tft_lcd_hsync SLEW = FAST; +NET tft_lcd_hsync DRIVE = 8; + +NET tft_lcd_r<0> LOC = N25; #VGA_R2 +NET tft_lcd_r<0> IOSTANDARD = LVCMOS33; +NET tft_lcd_r<1> LOC = C2; #VGA_R3 +NET tft_lcd_r<2> LOC = G7; #VGA_R4 +NET tft_lcd_r<3> LOC = F7; #VGA_R5 +NET tft_lcd_r<4> LOC = E5; #VGA_R6 +NET tft_lcd_r<5> LOC = E6; #VGA_R7 +NET tft_lcd_r<*> SLEW = FAST; +NET tft_lcd_r<*> DRIVE = 8; + +NET tft_lcd_vsync LOC = A8; +NET tft_lcd_vsync SLEW = FAST; +NET tft_lcd_vsync DRIVE = 8; + +TIMESPEC "TSPLB_TFT" = FROM "sys_clk" TO "tft_clk" TIG; +TIMESPEC "TSTFT_PLB" = FROM "tft_clk" TO "sys_clk" TIG; + +//////////////////////////////////////////////////////////////////////////// +// Misc Board Signals +//////////////////////////////////////////////////////////////////////////// + +NET plb_error LOC = L24; +NET plb_error IOSTANDARD = LVCMOS33; +NET plb_error TIG; +NET opb_error LOC = V6; +NET opb_error IOSTANDARD = LVCMOS33; +NET opb_error TIG; + +#------------------------------------------------------------------------------ +# IO Pad Location Constraints / Properties for Ethernet +#------------------------------------------------------------------------------ + +NET phy_col LOC = E3; +NET phy_crs LOC = D5; +NET phy_dv LOC = A9; +NET phy_rx_clk LOC = B15; +NET phy_rx_data<3> LOC = C4; +NET phy_rx_data<2> LOC = D4; +NET phy_rx_data<1> LOC = E1; +NET phy_rx_data<0> LOC = F1; + +NET phy_rx_er LOC = B9; +NET phy_tx_clk LOC = C15; +NET phy_mii_clk LOC = D1; +NET phy_mii_int_n LOC = H4; +NET phy_rst_n LOC = D10; +NET phy_tx_data<3> LOC = G1; +NET phy_tx_data<2> LOC = H3; +NET phy_tx_data<1> LOC = H2; +NET phy_tx_data<0> LOC = H1; +NET phy_tx_en LOC = F4; +NET phy_tx_er LOC = F3; +NET phy_mii_data LOC = G4; + +NET phy_mii_int_n PULLUP; + +NET phy_mii_int_n TIG; +NET phy_rst_n TIG; + +# Timing Constraints (these are recommended in documentation and +# are unaltered except for the TIG) +NET "phy_rx_clk" TNM_NET = "RXCLK_GRP"; +NET "phy_tx_clk" TNM_NET = "TXCLK_GRP"; +TIMESPEC "TSTXOUT" = FROM "TXCLK_GRP" TO "PADS" 10 ns; +TIMESPEC "TSRXIN" = FROM "PADS" TO "RXCLK_GRP" 6 ns; + +NET "phy_tx_clk" MAXSKEW= 1.0 ns; +NET "phy_rx_clk" MAXSKEW= 1.0 ns; +NET "phy_rx_clk" PERIOD = 40 ns HIGH 14 ns; +NET "phy_tx_clk" PERIOD = 40 ns HIGH 14 ns; + +NET "phy_rx_data<3>" IOBDELAY=NONE; +NET "phy_rx_data<2>" IOBDELAY=NONE; +NET "phy_rx_data<1>" IOBDELAY=NONE; +NET "phy_rx_data<0>" IOBDELAY=NONE; +NET "phy_dv" IOBDELAY=NONE; +NET "phy_rx_er" IOBDELAY=NONE; +NET "phy_crs" IOBDELAY=NONE; +NET "phy_col" IOBDELAY=NONE; + +# Workaround to help meet "phy_rx_clk MAXSKEW= 1.0 ns" constraint +INST "opb_ethernet_0/opb_ethernet_0/RX_FF_I0" IOB=FALSE; +INST "opb_ethernet_0/opb_ethernet_0/RX_FF_I1" IOB=FALSE; +INST "opb_ethernet_0/opb_ethernet_0/RX_FF_I2" IOB=FALSE; +INST "opb_ethernet_0/opb_ethernet_0/RX_FF_I3" IOB=FALSE; +INST "opb_ethernet_0/opb_ethernet_0/DVD_FF" IOB=FALSE; +INST "opb_ethernet_0/opb_ethernet_0/RER_FF" IOB=FALSE; + +# Timing ignores (to specify unconstrained paths) +TIMESPEC "TS_PHYTX_OPB" = FROM "TXCLK_GRP" TO "sys_clk" TIG; +TIMESPEC "TS_OPB_PHYTX" = FROM "sys_clk" TO "TXCLK_GRP" TIG; +TIMESPEC "TS_PHYRX_OPB" = FROM "RXCLK_GRP" TO "sys_clk" TIG; +TIMESPEC "TS_OPB_PHYRX" = FROM "sys_clk" TO "RXCLK_GRP" TIG; + +#------------------------------------------------------------------------------ +# IO Pad Location Constraints / Properties for SRAM/FLASH +#------------------------------------------------------------------------------ + +NET sram_clk LOC = AF7; +NET sram_clk_fb LOC = AD17; +NET flash_a23 LOC = T21; +NET sram_flash_addr<22> LOC = U20; +NET sram_flash_addr<21> LOC = T19; +NET sram_flash_addr<20> LOC = AC5; +NET sram_flash_addr<19> LOC = AB5; +NET sram_flash_addr<18> LOC = AC4; +NET sram_flash_addr<17> LOC = AB4; + +NET sram_flash_addr<16> LOC = AB3; +NET sram_flash_addr<15> LOC = AA4; +NET sram_flash_addr<14> LOC = AA3; +NET sram_flash_addr<13> LOC = W5; +NET sram_flash_addr<12> LOC = W6; +NET sram_flash_addr<11> LOC = W3; +NET sram_flash_addr<10> LOC = AF3; +NET sram_flash_addr<9> LOC = AE3; +NET sram_flash_addr<8> LOC = AD2; +NET sram_flash_addr<7> LOC = AD1; +NET sram_flash_addr<6> LOC = AC2; +NET sram_flash_addr<5> LOC = AC1; +NET sram_flash_addr<4> LOC = AB2; +NET sram_flash_addr<3> LOC = AB1; +NET sram_flash_addr<2> LOC = AA1; +NET sram_flash_addr<1> LOC = Y2; +NET sram_flash_addr<0> LOC = Y1; +NET sram_flash_data<31> LOC = F14; +NET sram_flash_data<30> LOC = F13; +NET sram_flash_data<29> LOC = F12; +NET sram_flash_data<28> LOC = F11; +NET sram_flash_data<27> LOC = F16; +NET sram_flash_data<26> LOC = F15; +NET sram_flash_data<25> LOC = D14; +NET sram_flash_data<24> LOC = D13; +NET sram_flash_data<23> LOC = D15; +NET sram_flash_data<22> LOC = E14; +NET sram_flash_data<21> LOC = C11; +NET sram_flash_data<20> LOC = D11; +NET sram_flash_data<19> LOC = D16; +NET sram_flash_data<18> LOC = C16; +NET sram_flash_data<17> LOC = E13; +NET sram_flash_data<16> LOC = D12; +NET sram_flash_data<15> LOC = AA14; +NET sram_flash_data<14> LOC = AB14; +NET sram_flash_data<13> LOC = AC12; +NET sram_flash_data<12> LOC = AC11; +NET sram_flash_data<11> LOC = AA16; +NET sram_flash_data<10> LOC = AA15; +NET sram_flash_data<9> LOC = AB13; +NET sram_flash_data<8> LOC = AA13; +NET sram_flash_data<7> LOC = AC14; +NET sram_flash_data<6> LOC = AD14; +NET sram_flash_data<5> LOC = AA12; +NET sram_flash_data<4> LOC = AA11; +NET sram_flash_data<3> LOC = AC16; +NET sram_flash_data<2> LOC = AC15; +NET sram_flash_data<1> LOC = AC13; +NET sram_flash_data<0> LOC = AD13; +NET sram_cen LOC = V7; +NET sram_flash_oe_n LOC = AC6; +NET sram_flash_we_n LOC = AB6; +NET sram_bw<3> LOC = Y3; #Y4; +NET sram_bw<2> LOC = Y4; #Y3; +NET sram_bw<1> LOC = Y5; #Y6; +NET sram_bw<0> LOC = Y6; #Y5; +NET flash_ce LOC = W7; +NET sram_adv_ld_n LOC = W4; +NET sram_mode LOC = V26; + +NET sram_clk IOSTANDARD = LVCMOS33; +NET sram_clk DRIVE = 16; +NET sram_clk SLEW = FAST; +NET sram_clk_fb IOSTANDARD = LVCMOS33; + +NET flash_a23 IOSTANDARD = LVDCI_33; +NET flash_a23 SLEW = FAST; +NET flash_a23 DRIVE = 8; + +NET sram_mode IOSTANDARD = LVDCI_33; +NET sram_mode SLEW = FAST; +NET sram_mode DRIVE = 8; + +NET sram_flash_addr<*> IOSTANDARD = LVDCI_33; +NET sram_flash_addr<*> SLEW = FAST; +NET sram_flash_addr<*> DRIVE = 8; + +NET sram_flash_data<*> IOSTANDARD = LVCMOS33; +NET sram_flash_data<*> DRIVE = 12; +NET sram_flash_data<*> SLEW = FAST; +NET sram_flash_data<*> PULLDOWN; + +NET sram_flash_oe_n IOSTANDARD = LVDCI_33; +NET sram_flash_oe_n SLEW = FAST; +NET sram_flash_oe_n DRIVE = 8; + +NET sram_flash_we_n IOSTANDARD = LVDCI_33; +NET sram_flash_we_n SLEW = FAST; +NET sram_flash_we_n DRIVE = 8; + +NET sram_bw<*> IOSTANDARD = LVDCI_33; +NET sram_bw<*> SLEW = FAST; +NET sram_bw<*> DRIVE = 8; + +NET flash_ce IOSTANDARD = LVDCI_33; +NET flash_ce SLEW = FAST; +NET flash_ce DRIVE = 8; + +NET sram_cen IOSTANDARD = LVDCI_33; +NET sram_cen SLEW = FAST; +NET sram_cen DRIVE = 8; + +NET sram_adv_ld_n IOSTANDARD = LVDCI_33; +NET sram_adv_ld_n SLEW = FAST; +NET sram_adv_ld_n DRIVE = 8; + +#------------------------------------------------------------------------------ +# IO Pad Location Constraints / Properties for Expansion Header GPIO +#------------------------------------------------------------------------------ + +NET gpio_exp_hdr1<31> LOC = AF24; # HDR1_64 +NET gpio_exp_hdr1<30> LOC = AE24; # HDR1_62 +NET gpio_exp_hdr1<29> LOC = AD22; # HDR1_8 +NET gpio_exp_hdr1<28> LOC = AB21; # HDR1_58 +NET gpio_exp_hdr1<27> LOC = W20; # HDR1_44 +NET gpio_exp_hdr1<26> LOC = W21; # HDR1_48 +NET gpio_exp_hdr1<25> LOC = AB22; # HDR1_14 +NET gpio_exp_hdr1<24> LOC = AD25; # HDR1_20 +NET gpio_exp_hdr1<23> LOC = W22; # HDR1_46 +NET gpio_exp_hdr1<22> LOC = V21; # HDR1_56 +NET gpio_exp_hdr1<21> LOC = V22; # HDR1_54 +NET gpio_exp_hdr1<20> LOC = AC22; # HDR1_16 +NET gpio_exp_hdr1<19> LOC = AD26; # HDR1_18 +NET gpio_exp_hdr1<18> LOC = AC26; # HDR1_34 +NET gpio_exp_hdr1<17> LOC = AD23; # HDR1_6 +NET gpio_exp_hdr1<16> LOC = AB25; # HDR1_30 +NET gpio_exp_hdr1<15> LOC = AC23; # HDR1_4 +NET gpio_exp_hdr1<14> LOC = AB26; # HDR1_24 +NET gpio_exp_hdr1<13> LOC = AC21; # HDR1_60 +NET gpio_exp_hdr1<12> LOC = AA23; # HDR1_10 +NET gpio_exp_hdr1<11> LOC = AA26; # HDR1_22 +NET gpio_exp_hdr1<10> LOC = Y25; # HDR1_40 +NET gpio_exp_hdr1<9> LOC = Y26; # HDR1_38 +NET gpio_exp_hdr1<8> LOC = W26; # HDR1_50 +NET gpio_exp_hdr1<7> LOC = AB23; # HDR1_12 +NET gpio_exp_hdr1<6> LOC = Y24; # HDR1_26 +NET gpio_exp_hdr1<5> LOC = AB24; # HDR1_32 +NET gpio_exp_hdr1<4> LOC = W25; # HDR1_52 +NET gpio_exp_hdr1<3> LOC = AC24; # HDR1_2 +NET gpio_exp_hdr1<2> LOC = AC25; # HDR1_36 +NET gpio_exp_hdr1<1> LOC = V20; # HDR1_42 +NET gpio_exp_hdr1<0> LOC = AA24; # HDR1_28 +NET gpio_exp_hdr1<*> TIG; +NET gpio_exp_hdr1<*> PULLDOWN; + +NET gpio_exp_hdr2<31> LOC = AF18; # HDR2_40 +NET gpio_exp_hdr2<30> LOC = AE18; # HDR2_38 +NET gpio_exp_hdr2<29> LOC = AF19; # HDR2_32 +NET gpio_exp_hdr2<28> LOC = AF20; # HDR2_30 +NET gpio_exp_hdr2<27> LOC = AF21; # HDR2_44 +NET gpio_exp_hdr2<26> LOC = AF22; # HDR2_42 +NET gpio_exp_hdr2<25> LOC = AF23; # HDR2_24 +NET gpio_exp_hdr2<24> LOC = AE23; # HDR2_22 +NET gpio_exp_hdr2<23> LOC = AC18; # HDR2_48 +NET gpio_exp_hdr2<22> LOC = AB18; # HDR2_46 +NET gpio_exp_hdr2<21> LOC = AD19; # HDR2_64 +NET gpio_exp_hdr2<20> LOC = AC19; # HDR2_62 +NET gpio_exp_hdr2<19> LOC = AE20; # HDR2_16 +NET gpio_exp_hdr2<18> LOC = AD20; # HDR2_14 +NET gpio_exp_hdr2<17> LOC = AE21; # HDR2_36 +NET gpio_exp_hdr2<16> LOC = AD21; # HDR2_34 +NET gpio_exp_hdr2<15> LOC = AB20; # HDR2_52 +NET gpio_exp_hdr2<14> LOC = AC20; # HDR2_50 +NET gpio_exp_hdr2<13> LOC = Y17; # HDR2_56 +NET gpio_exp_hdr2<12> LOC = AA17; # HDR2_54 +NET gpio_exp_hdr2<11> LOC = AA19; # HDR2_60 +NET gpio_exp_hdr2<10> LOC = AA20; # HDR2_58 +NET gpio_exp_hdr2<9> LOC = Y22; # HDR2_8 +NET gpio_exp_hdr2<8> LOC = Y23; # HDR2_6 +NET gpio_exp_hdr2<7> LOC = W23; # HDR2_12 +NET gpio_exp_hdr2<6> LOC = W24; # HDR2_10 +NET gpio_exp_hdr2<5> LOC = Y20; # HDR2_20 +NET gpio_exp_hdr2<4> LOC = Y21; # HDR2_18 +NET gpio_exp_hdr2<3> LOC = Y19; # HDR2_28 +NET gpio_exp_hdr2<2> LOC = W19; # HDR2_26 +NET gpio_exp_hdr2<1> LOC = AA18; # HDR2_4 +NET gpio_exp_hdr2<0> LOC = Y18; # HDR2_2 +NET gpio_exp_hdr2<*> TIG; +NET gpio_exp_hdr2<*> PULLDOWN; + +#------------------------------------------------------------------------------ +# IO Pad Location Constraints / Properties for Character LCD GPIO +#------------------------------------------------------------------------------ + +NET gpio_char_lcd<6> LOC = AE13; # LCD_E +NET gpio_char_lcd<5> LOC = AC17; # LCD_RS +NET gpio_char_lcd<4> LOC = AB17; # LCD_RW +NET gpio_char_lcd<3> LOC = AF12; # LCD_DB7 +NET gpio_char_lcd<2> LOC = AE12; # LCD_DB6 +NET gpio_char_lcd<1> LOC = AC10; # LCD_DB5 +NET gpio_char_lcd<0> LOC = AB10; # LCD_DB4 +NET gpio_char_lcd<*> IOSTANDARD = LVCMOS33; +NET gpio_char_lcd<*> TIG; +NET gpio_char_lcd<*> PULLDOWN;