From b6a07804630201e3cd16898bb36d4bfce00166aa Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Sun, 22 Sep 2013 10:43:18 +0000 Subject: [PATCH] This commit was manufactured by cvs2svn to create branch 'EMAC_BRANCH_DMA'. git-svn-id: http://moon:8086/svn/vhdl/branches/EMAC_BRANCH_DMA@1034 cc03376c-175c-47c8-b038-4cd826a8556b --- Common/sim/ModelSim SE .lnk | Bin 1441 -> 0 bytes Common/sim/compile_fixed.do | 13 - Common/sim/compile_simprim.do | 8 - Common/sim/compile_unisim.do | 8 - Common/ucf/ml402.ucf | 675 --- lib/CPUs/J1/doc/j1.pdf | Bin 124188 -> 0 bytes lib/CPUs/J1/sim/tb_j1.do | 15 - lib/CPUs/J1/sim/tb_j1.wave.do | 58 - lib/CPUs/J1/src/core/j1.v | 187 - lib/CPUs/J1/src/core/j1.vhd | 282 - lib/CPUs/J1/src/core/ram_2c_2r_2w.vhd | 84 - lib/CPUs/J1/src/tb_j1.vhd | 150 - lib/CPUs/JCpu/asm/dctest.jsm | 56 - lib/CPUs/JCpu/asm/dctest.tcl | 212 - lib/CPUs/JCpu/asm/itest.jsm | 858 --- lib/CPUs/JCpu/asm/itest.tcl | 3407 ----------- lib/CPUs/JCpu/asm/make | 50 - lib/CPUs/JCpu/asm/mul8x8.jsm | 29 - lib/CPUs/JCpu/asm/mul8x8.tcl | 154 - lib/CPUs/JCpu/asm/reti_issue.jsm | 50 - lib/CPUs/JCpu/asm/reti_issue.tcl | 157 - lib/CPUs/JCpu/doc/block_diagram.png | Bin 8026 -> 0 bytes lib/CPUs/JCpu/doc/memory_map.png | Bin 3545 -> 0 bytes lib/CPUs/JCpu/gpl-3.0.txt | 674 --- lib/CPUs/JCpu/sim/ModelSim SE .lnk | Bin 1455 -> 0 bytes lib/CPUs/JCpu/sim/tb_cpu.fdo | 22 - lib/CPUs/JCpu/sim/tb_cpu.wdo | 107 - lib/CPUs/JCpu/sim/tb_cpu_embedded.fdo | 22 - lib/CPUs/JCpu/sim/tb_cpu_embedded.wdo | 26 - lib/CPUs/JCpu/sim/tb_cpu_itest.fdo | 22 - lib/CPUs/JCpu/sim/tb_cpu_itest.wdo | 122 - lib/CPUs/JCpu/sim/tb_cpu_reti_issue.fdo | 22 - lib/CPUs/JCpu/sim/tb_cpu_reti_issue.wdo | 90 - lib/CPUs/JCpu/sim/tb_mul8x8.fdo | 22 - lib/CPUs/JCpu/sim/tb_mul8x8.wdo | 31 - lib/CPUs/JCpu/src/core/alu.vhd | 236 - lib/CPUs/JCpu/src/core/chipram.vhd | 85 - lib/CPUs/JCpu/src/core/chipreg.vhd | 117 - lib/CPUs/JCpu/src/core/cpu.vhd | 563 -- lib/CPUs/JCpu/src/core/cpu_pkg.vhd | 852 --- lib/CPUs/JCpu/src/core/dpath_ctrl.vhd | 87 - lib/CPUs/JCpu/src/core/int_ctrl.vhd | 138 - lib/CPUs/JCpu/src/core/pc.vhd | 70 - lib/CPUs/JCpu/src/core/reg_dual.vhd | 81 - lib/CPUs/JCpu/src/core/stack_ctrl.vhd | 73 - lib/CPUs/JCpu/src/cpu_embedded.vhd | 106 - lib/CPUs/JCpu/src/dctest_irom.vhdl | 79 - lib/CPUs/JCpu/src/dctest_irom_ld.vhdl | 1181 ---- lib/CPUs/JCpu/src/dctest_xrom.vhdl | 317 - lib/CPUs/JCpu/src/dctest_xrom_ld.vhdl | 413 -- lib/CPUs/JCpu/src/itest_irom.vhdl | 1086 ---- lib/CPUs/JCpu/src/itest_irom_ld.vhdl | 1181 ---- lib/CPUs/JCpu/src/itest_xrom.vhdl | 317 - lib/CPUs/JCpu/src/itest_xrom_ld.vhdl | 413 -- lib/CPUs/JCpu/src/mul8x8_irom.vhdl | 88 - lib/CPUs/JCpu/src/mul8x8_irom_ld.vhdl | 1181 ---- lib/CPUs/JCpu/src/mul8x8_xrom.vhdl | 317 - lib/CPUs/JCpu/src/mul8x8_xrom_ld.vhdl | 413 -- lib/CPUs/JCpu/src/reti_issue_irom.vhdl | 89 - lib/CPUs/JCpu/src/reti_issue_irom_ld.vhdl | 1181 ---- lib/CPUs/JCpu/src/reti_issue_xrom.vhdl | 317 - lib/CPUs/JCpu/src/reti_issue_xrom_ld.vhdl | 413 -- lib/CPUs/JCpu/src/tb_cpu_embedded.vhd | 126 - lib/CPUs/JCpu/src/tb_cpu_irq.vhd | 205 - lib/CPUs/JCpu/src/tb_cpu_itest.vhd | 200 - lib/CPUs/JCpu/syn/ise91/cpu_vhdl.prj | 10 - lib/CPUs/JCpu/tools/eval_scan.rb | 42 - lib/CPUs/JCpu/tools/insrom.rb | 46 - lib/CPUs/JCpu/tools/irom.vhd.tpl | 32 - lib/CPUs/JCpu/tools/irom_ld.vhd.tpl | 151 - lib/CPUs/JCpu/tools/jasm.bak.rb | 494 -- lib/CPUs/JCpu/tools/jasm.rb | 814 --- lib/CPUs/JCpu/tools/lib/cg.inc.jsm | 72 - lib/CPUs/JCpu/tools/lib/cregs.inc.jsm | 7 - lib/CPUs/JCpu/tools/lib/delays.inc.jsm | 64 - lib/CPUs/JCpu/tools/lib/lcd.inc.jsm | 208 - lib/CPUs/JCpu/tools/lib/mul8x8.inc.jsm | 42 - lib/CPUs/JCpu/tools/lib/uart.inc.jsm | 32 - lib/CPUs/JCpu/tools/lib/utils.inc.jsm | 32 - lib/CPUs/JCpu/tools/opc.list | 64 - lib/CPUs/JCpu/tools/regx.rb | 20 - lib/CPUs/JCpu/tools/rom.tcl.tpl | 61 - lib/CPUs/JCpu/tools/templates.rb | 44 - lib/CPUs/JCpu/tools/xrom.vhd.tpl | 32 - lib/CPUs/JCpu/tools/xrom_ld.vhd.tpl | 151 - lib/CPUs/MIPS/bsp/examples/.directory_history | 34 - lib/CPUs/MIPS/bsp/examples/Bessel.c | 87 - lib/CPUs/MIPS/bsp/examples/Makefile | 333 -- lib/CPUs/MIPS/bsp/examples/aes256.c | 359 -- lib/CPUs/MIPS/bsp/examples/aes256.h | 42 - lib/CPUs/MIPS/bsp/examples/aes256_1.c | 76 - lib/CPUs/MIPS/bsp/examples/barcode.c | 358 -- lib/CPUs/MIPS/bsp/examples/barcode.new.c | 322 - lib/CPUs/MIPS/bsp/examples/basicmath_small.c | 84 - lib/CPUs/MIPS/bsp/examples/bogomips.c | 71 - .../MIPS/bsp/examples/bootloader/Makefile | 47 - .../MIPS/bsp/examples/bootloader/bootloader.c | 247 - .../bsp/examples/bootloader/bootloader.ld | 53 - .../bootloader/bootloader_with_flash.c | 383 -- .../MIPS/bsp/examples/bootloader/init_boot.S | 19 - .../MIPS/bsp/examples/bootloader/jtag_upd.bat | 13 - .../bsp/examples/bootloader/kernel_boot.S | 46 - .../bsp/examples/bootloader/libsys_boot.c | 214 - .../bsp/examples/bootloader/libsys_boot.h | 54 - .../bsp/examples/bootloader/startup_boot.S | 43 - lib/CPUs/MIPS/bsp/examples/cfiflash.c | 415 -- lib/CPUs/MIPS/bsp/examples/cfiflash.h | 58 - lib/CPUs/MIPS/bsp/examples/crc32.c | 54 - lib/CPUs/MIPS/bsp/examples/crc32.h | 13 - lib/CPUs/MIPS/bsp/examples/cubic.c | 64 - lib/CPUs/MIPS/bsp/examples/dbg.c | 375 -- lib/CPUs/MIPS/bsp/examples/delay_mips.c | 15 - lib/CPUs/MIPS/bsp/examples/demo.c | 67 - lib/CPUs/MIPS/bsp/examples/dhry.h | 430 -- lib/CPUs/MIPS/bsp/examples/dhry_1.c | 402 -- lib/CPUs/MIPS/bsp/examples/dhry_2.c | 192 - lib/CPUs/MIPS/bsp/examples/dttl.c | 261 - lib/CPUs/MIPS/bsp/examples/gunzip.c | 198 - lib/CPUs/MIPS/bsp/examples/hashtest.c | 323 - lib/CPUs/MIPS/bsp/examples/hello.c | 19 - lib/CPUs/MIPS/bsp/examples/hpi.c | 949 --- lib/CPUs/MIPS/bsp/examples/hpi.h | 384 -- lib/CPUs/MIPS/bsp/examples/inflate.c | 504 -- lib/CPUs/MIPS/bsp/examples/inflate.h | 15 - lib/CPUs/MIPS/bsp/examples/irq.c | 92 - lib/CPUs/MIPS/bsp/examples/irq.h | 15 - lib/CPUs/MIPS/bsp/examples/isqrt.c | 89 - lib/CPUs/MIPS/bsp/examples/kernel.S | 184 - lib/CPUs/MIPS/bsp/examples/libsys.c | 1101 ---- lib/CPUs/MIPS/bsp/examples/libsys.h | 187 - .../bsp/examples/libsys/.directory_history | 70 - lib/CPUs/MIPS/bsp/examples/libsys/Makefile | 29 - lib/CPUs/MIPS/bsp/examples/libsys/mips_ps2.c | 268 - lib/CPUs/MIPS/bsp/examples/libsys/mips_ps2.h | 43 - lib/CPUs/MIPS/bsp/examples/libsys/syscalls.c | 86 - lib/CPUs/MIPS/bsp/examples/life.c | 251 - lib/CPUs/MIPS/bsp/examples/link/link.ld | 225 - lib/CPUs/MIPS/bsp/examples/lua_init.c | 1 - lib/CPUs/MIPS/bsp/examples/lwl.c | 46 - lib/CPUs/MIPS/bsp/examples/mandelbrot.c | 54 - lib/CPUs/MIPS/bsp/examples/mips_gfx.c | 566 -- lib/CPUs/MIPS/bsp/examples/mips_gfx.h | 91 - lib/CPUs/MIPS/bsp/examples/mipsdis.c | 625 -- lib/CPUs/MIPS/bsp/examples/mipsdis.h | 450 -- lib/CPUs/MIPS/bsp/examples/paranoia.c | 2302 -------- lib/CPUs/MIPS/bsp/examples/phrasen.c | 298 - lib/CPUs/MIPS/bsp/examples/pi.h | 13 - lib/CPUs/MIPS/bsp/examples/queens.c | 856 --- lib/CPUs/MIPS/bsp/examples/r3.c | 471 -- lib/CPUs/MIPS/bsp/examples/rad2deg.c | 39 - lib/CPUs/MIPS/bsp/examples/random.c | 86 - lib/CPUs/MIPS/bsp/examples/random.h | 6 - lib/CPUs/MIPS/bsp/examples/regdef.h | 81 - .../MIPS/bsp/examples/richards_benchmark.c | 408 -- lib/CPUs/MIPS/bsp/examples/rmd160.c | 294 - lib/CPUs/MIPS/bsp/examples/rmd160.h | 154 - lib/CPUs/MIPS/bsp/examples/rmd160_test.c | 113 - lib/CPUs/MIPS/bsp/examples/round.h | 55 - lib/CPUs/MIPS/bsp/examples/serdump.c | 83 - lib/CPUs/MIPS/bsp/examples/snipmath.h | 75 - lib/CPUs/MIPS/bsp/examples/sniptype.h | 37 - lib/CPUs/MIPS/bsp/examples/specs/specs | 147 - lib/CPUs/MIPS/bsp/examples/stanford.c | 1117 ---- lib/CPUs/MIPS/bsp/examples/startup.S | 87 - lib/CPUs/MIPS/bsp/examples/test_ac97.c | 310 - lib/CPUs/MIPS/bsp/examples/test_dcache.c | 61 - lib/CPUs/MIPS/bsp/examples/test_endianess.c | 64 - lib/CPUs/MIPS/bsp/examples/test_exception.c | 282 - lib/CPUs/MIPS/bsp/examples/test_flash.c | 94 - lib/CPUs/MIPS/bsp/examples/test_hpi.c | 848 --- lib/CPUs/MIPS/bsp/examples/test_irq.c | 335 -- lib/CPUs/MIPS/bsp/examples/test_mipsdis.c | 651 -- lib/CPUs/MIPS/bsp/examples/test_timer.c | 40 - lib/CPUs/MIPS/bsp/examples/test_vga.c | 206 - lib/CPUs/MIPS/bsp/examples/testbench.c | 1229 ---- lib/CPUs/MIPS/bsp/examples/testlibusb.c | 210 - lib/CPUs/MIPS/bsp/examples/ucb.c | 44 - lib/CPUs/MIPS/bsp/examples/whet.c | 265 - lib/CPUs/MIPS/bsp/examples/xcpt.c | 139 - lib/CPUs/MIPS/bsp/examples/xcpt.h | 55 - lib/CPUs/MIPS/bsp/examples/xcpt_asm.h | 67 - lib/CPUs/MIPS/dist/gpl-3.0.txt | 674 --- lib/CPUs/MIPS/dist/makedist.R12 | 32 - lib/CPUs/MIPS/dist/makedist.R13 | 32 - lib/CPUs/MIPS/dist/notes.txt | 100 - lib/CPUs/MIPS/doc/J-MIPS.txt | 109 - lib/CPUs/MIPS/doc/async_port_timing.pdf | Bin 10447 -> 0 bytes lib/CPUs/MIPS/doc/memory_map.pdf | Bin 2484 -> 0 bytes lib/CPUs/MIPS/doc/memory_map.vsd | Bin 36352 -> 0 bytes lib/CPUs/MIPS/doc/mips_biu.pdf | Bin 7079 -> 0 bytes lib/CPUs/MIPS/doc/mips_drawings.vsd | Bin 1437184 -> 0 bytes lib/CPUs/MIPS/doc/mips_jbus_timing.pdf | Bin 22419 -> 0 bytes lib/CPUs/MIPS/doc/mips_pipeline.pdf | Bin 16626 -> 0 bytes lib/CPUs/MIPS/doc/mips_pipeline_stages.pdf | Bin 9884 -> 0 bytes lib/CPUs/MIPS/doc/mips_sys.vsd | Bin 30720 -> 0 bytes lib/CPUs/MIPS/doc/mips_sys_ml402.pdf | Bin 7137 -> 0 bytes lib/CPUs/MIPS/doc/toolchain/howto_build.txt | 46 - lib/CPUs/MIPS/doc/toolchain/make.sh | 151 - .../doc/toolchain/newlib-1.16.0-jens.patch | 11 - .../doc/toolchain/newlib-1.17.0-jens.patch | 11 - lib/CPUs/MIPS/sim/ModelSim SE .lnk | Bin 1455 -> 0 bytes lib/CPUs/MIPS/sim/asm/exception.s | 249 - lib/CPUs/MIPS/sim/asm/faculty.c | 96 - lib/CPUs/MIPS/sim/asm/faculty.s | 255 - lib/CPUs/MIPS/sim/asm/fibonacci.c | 179 - lib/CPUs/MIPS/sim/asm/fibonacci.s | 555 -- lib/CPUs/MIPS/sim/asm/idata.ld | 24 - lib/CPUs/MIPS/sim/asm/init.s | 28 - lib/CPUs/MIPS/sim/asm/jtag.sh | 7 - lib/CPUs/MIPS/sim/asm/kernel.s | 251 - lib/CPUs/MIPS/sim/asm/link.ld | 47 - lib/CPUs/MIPS/sim/asm/load_store.c | 64 - lib/CPUs/MIPS/sim/asm/load_store.s | 64 - lib/CPUs/MIPS/sim/asm/make.sh | 30 - lib/CPUs/MIPS/sim/asm/mips_exception.s | 31 - lib/CPUs/MIPS/sim/asm/mips_load_store_.txt | 86 - lib/CPUs/MIPS/sim/asm/muldiv.c | 134 - lib/CPUs/MIPS/sim/asm/muldiv.s | 391 -- lib/CPUs/MIPS/sim/asm/mult.txt | 27 - lib/CPUs/MIPS/sim/asm/rmd160.s | 2482 -------- lib/CPUs/MIPS/sim/asm/rmd160_test.s | 556 -- lib/CPUs/MIPS/sim/asm/spim_load_store.s | 50 - lib/CPUs/MIPS/sim/asm/startup.s | 27 - lib/CPUs/MIPS/sim/asm/test1.s | 39 - lib/CPUs/MIPS/sim/asm/test2.s | 40 - lib/CPUs/MIPS/sim/asm/test3.s | 40 - lib/CPUs/MIPS/sim/asm/test4.s | 34 - lib/CPUs/MIPS/sim/asm/test5.s | 39 - lib/CPUs/MIPS/sim/asm/test6.s | 31 - lib/CPUs/MIPS/sim/asm/test7.s | 17 - lib/CPUs/MIPS/sim/asm/test_addsub.s | 76 - lib/CPUs/MIPS/sim/asm/test_muldiv.s | 17 - lib/CPUs/MIPS/sim/asm/test_slt.s | 57 - lib/CPUs/MIPS/sim/asm/test_slti.s | 57 - lib/CPUs/MIPS/sim/asm/test_sub.s | 57 - lib/CPUs/MIPS/sim/asm/testbench.c | 322 - lib/CPUs/MIPS/sim/asm/testbench.s | 924 --- lib/CPUs/MIPS/sim/asm/utils.c | 179 - lib/CPUs/MIPS/sim/asm/utils.h | 12 - lib/CPUs/MIPS/sim/asm/utils.s | 184 - lib/CPUs/MIPS/sim/hello.flash.bin | Bin 7936 -> 0 bytes lib/CPUs/MIPS/sim/tb_mips_muldiv.fdo | 15 - lib/CPUs/MIPS/sim/tb_mips_muldiv.wdo | 78 - lib/CPUs/MIPS/sim/tb_mips_sys.fdo | 42 - lib/CPUs/MIPS/sim/tb_mips_sys.wdo | 45 - lib/CPUs/MIPS/sim/tb_mips_top.fdo | 61 - lib/CPUs/MIPS/sim/tb_mips_top.wdo | 223 - lib/CPUs/MIPS/sim/tb_mips_top_syn.fdo | 55 - lib/CPUs/MIPS/sim/tb_mips_top_syn.wdo | 104 - lib/CPUs/MIPS/src/async_defs.vhd | 68 - lib/CPUs/MIPS/src/bootloader.ROM.vhd | 2082 ------- lib/CPUs/MIPS/src/bootloader.dis | 1467 ----- lib/CPUs/MIPS/src/core/.directory_history | 12 - lib/CPUs/MIPS/src/core/dcache.vhd | 513 -- lib/CPUs/MIPS/src/core/icache.vhd | 488 -- lib/CPUs/MIPS/src/core/mips_alu.vhd | 184 - lib/CPUs/MIPS/src/core/mips_bcu.vhd | 52 - lib/CPUs/MIPS/src/core/mips_bui.vhd | 552 -- lib/CPUs/MIPS/src/core/mips_cop.vhd | 546 -- lib/CPUs/MIPS/src/core/mips_instr.vhd | 1062 ---- lib/CPUs/MIPS/src/core/mips_muldiv.vhd | 454 -- lib/CPUs/MIPS/src/core/mips_pipeline.vhd | 867 --- lib/CPUs/MIPS/src/core/mips_reg.vhd | 72 - lib/CPUs/MIPS/src/core/mips_shifter.vhd | 117 - lib/CPUs/MIPS/src/core/mips_top.vhd | 308 - lib/CPUs/MIPS/src/core/mips_types.vhd | 673 --- lib/CPUs/MIPS/src/mips_sys.vhd | 341 -- lib/CPUs/MIPS/src/mips_top_syn.vhd | 100 - lib/CPUs/MIPS/src/tb_mips_muldiv.vhd | 332 -- lib/CPUs/MIPS/src/tb_mips_sys.vhd | 233 - lib/CPUs/MIPS/src/tb_mips_top.vhd | 460 -- .../MIPS/syn/ise101/constraints/mips_top.xcf | 13 - lib/CPUs/MIPS/syn/ise101/mips_top.prj | 21 - lib/CPUs/MIPS/syn/ise101/mips_top_vhdl.prj | 21 - lib/CPUs/MIPS/todo.txt | 35 - lib/CPUs/MIPS/tools/Makefile | 20 - lib/CPUs/MIPS/tools/flashgen.exe | Bin 12196 -> 0 bytes lib/CPUs/MIPS/tools/flashgen_big.exe | Bin 12301 -> 0 bytes lib/CPUs/MIPS/tools/flashgen_little.exe | Bin 12301 -> 0 bytes lib/CPUs/MIPS/tools/ramgen.exe | Bin 22930 -> 0 bytes lib/CPUs/MIPS/tools/romgen.exe | Bin 21906 -> 0 bytes lib/CPUs/MIPS/tools/src/flashgen.c | 140 - lib/CPUs/MIPS/tools/src/ramgen.c | 385 -- lib/CPUs/MIPS/tools/src/romgen.c | 428 -- lib/FIFO/sim/tb_fifo_async.fdo | 16 - lib/FIFO/sim/tb_fifo_async.wdo | 39 - lib/FIFO/sim/tb_fifo_sync.fdo | 15 - lib/FIFO/sim/tb_fifo_sync.wdo | 31 - lib/FIFO/sim/tb_gray_counter.fdo | 13 - lib/FIFO/sim/tb_gray_counter.wdo | 29 - lib/FIFO/src/.directory_history | 8 - lib/FIFO/src/async_fifo_ctrl.vhd | 248 - lib/FIFO/src/fifo_async.vhd | 124 - lib/FIFO/src/fifo_ctrl_pkg.vhd | 67 - lib/FIFO/src/fifo_sync.vhd | 123 - lib/FIFO/src/fifo_sync_dist.vhd | 117 - lib/FIFO/src/gray_counter.vhd | 84 - lib/FIFO/src/sync_fifo_ctrl.vhd | 198 - lib/FIFO/src/tb_fifo_async.vhd | 225 - lib/FIFO/src/tb_fifo_sync.vhd | 207 - lib/FIFO/src/tb_gray_counter.vhd | 85 - lib/JBUS/sim/tb_busmaster_async.fdo | 21 - lib/JBUS/sim/tb_busmaster_async.wdo | 59 - lib/JBUS/sim/tb_busmaster_sync.fdo | 20 - lib/JBUS/sim/tb_busmaster_sync.wdo | 54 - lib/JBUS/sim/tb_dmac.fdo | 21 - lib/JBUS/sim/tb_dmac.wdo | 177 - lib/JBUS/src/busmaster_async.vhd | 277 - lib/JBUS/src/busmaster_sync.vhd | 216 - lib/JBUS/src/busmaster_types.vhd | 31 - lib/JBUS/src/dmac.vhd | 229 - lib/JBUS/src/tb_busmaster_async.vhd | 451 -- lib/JBUS/src/tb_busmaster_sync.vhd | 446 -- lib/JBUS/src/tb_dmac.vhd | 540 -- lib/PCK_FIO-1.16/PCK_FIO.html | 297 - lib/PCK_FIO-1.16/PCK_FIO.out.gold | 206 - lib/PCK_FIO-1.16/PCK_FIO.vhd | 919 --- lib/PCK_FIO-1.16/README | 72 - lib/PCK_FIO-1.16/TB_PCK_FIO.vhd | 504 -- lib/PCK_FIO-2002.7/CHANGES | 86 - lib/PCK_FIO-2002.7/PCK_FIO.html | 339 -- lib/PCK_FIO-2002.7/PCK_FIO.out.gold | Bin 8979 -> 0 bytes lib/PCK_FIO-2002.7/PCK_FIO_1987.vhd | 105 - lib/PCK_FIO-2002.7/PCK_FIO_1987_BODY.vhd | 821 --- lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd | 108 - lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd | 814 --- lib/PCK_FIO-2002.7/README | 88 - lib/PCK_FIO-2002.7/TB_PCK_FIO_1987.vhd | 531 -- lib/PCK_FIO-2002.7/TB_PCK_FIO_1993.vhd | 536 -- .../msMakefile.TBE_PCK_FIO_TB.1987 | 34 - .../msMakefile.TBE_PCK_FIO_TB.1993 | 34 - lib/SDRAM/ddr_sdr_v1_4/doc/SDRAM_CTRL.vsd | Bin 71680 -> 0 bytes .../ddr_sdr_v1_4/ise9/sdram_ctrl_top_vhdl.prj | 13 - lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl.fdo | 27 - lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl.wdo | 93 - .../ddr_sdr_v1_4/sim/tb_sdr_ctrl_fifo.fdo | 27 - .../ddr_sdr_v1_4/sim/tb_sdr_ctrl_fifo.wdo | 68 - .../sim/tb_sdr_ctrl_lin_r_rand_w.fdo | 27 - .../sim/tb_sdr_ctrl_lin_r_rand_w.wdo | 87 - .../sim/tb_sdr_ctrl_lin_w_rand_r.fdo | 27 - .../sim/tb_sdr_ctrl_lin_w_rand_r.wdo | 87 - .../sim/tb_sdr_ctrl_rand_addr.fdo | 27 - .../sim/tb_sdr_ctrl_rand_addr.wdo | 82 - .../ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_rw.fdo | 27 - .../ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_rw.wdo | 84 - .../sim/tb_sdram_ctrl_frontend.fdo | 28 - .../sim/tb_sdram_ctrl_frontend.wdo | 48 - .../ddr_sdr_v1_4/src/clockgen_virtex4.vhd | 240 - .../ddr_sdr_v1_4/src/ddr_phy_virtex4.vhd | 389 -- lib/SDRAM/ddr_sdr_v1_4/src/fifo_sync.vhd | 111 - lib/SDRAM/ddr_sdr_v1_4/src/mt46v16m16.vhd | 1320 ----- lib/SDRAM/ddr_sdr_v1_4/src/reset_virtex4.vhd | 111 - lib/SDRAM/ddr_sdr_v1_4/src/sdram_cmd.vhd | 269 - lib/SDRAM/ddr_sdr_v1_4/src/sdram_config.vhd | 74 - lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl.vhd | 487 -- .../ddr_sdr_v1_4/src/sdram_ctrl_frontend.vhd | 293 - lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl_top.vhd | 289 - lib/SDRAM/ddr_sdr_v1_4/src/sdram_types.vhd | 133 - lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl.vhd | 336 -- .../ddr_sdr_v1_4/src/tb_sdr_ctrl_fifo.vhd | 420 -- .../src/tb_sdr_ctrl_lin_r_rand_w.vhd | 322 - .../src/tb_sdr_ctrl_lin_w_rand_r.vhd | 320 - .../src/tb_sdr_ctrl_rand_addr.vhd | 319 - .../ddr_sdr_v1_4/src/tb_sdr_ctrl_rand_rw.vhd | 333 -- .../src/tb_sdram_ctrl_frontend.vhd | 385 -- lib/SDRAM/ddr_sdr_v1_5/doc/SDRAM_CTRL.vsd | Bin 91648 -> 0 bytes lib/SDRAM/ddr_sdr_v1_5/sim/ModelSim SE .lnk | Bin 1473 -> 0 bytes .../sim/tb_sdram_ctrl_frontend64_wb.fdo | 30 - .../sim/tb_sdram_ctrl_frontend64_wb.wdo | 55 - .../sim/tb_sdram_ctrl_frontend_wb.fdo | 30 - .../sim/tb_sdram_ctrl_frontend_wb.wdo | 62 - .../ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd | 367 -- lib/SDRAM/ddr_sdr_v1_5/src/mt46v16m16.vhd | 1320 ----- lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd | 290 - lib/SDRAM/ddr_sdr_v1_5/src/sdram_config.vhd | 74 - lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd | 491 -- .../src/sdram_ctrl_frontend64_wb.vhd | 278 - .../src/sdram_ctrl_frontend_wb.vhd | 278 - lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd | 237 - lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd | 130 - .../src/tb_sdram_ctrl_frontend64_wb.vhd | 871 --- .../src/tb_sdram_ctrl_frontend_wb.vhd | 867 --- lib/SDRAM/ddr_sdr_v1_5/todo.txt | 7 - lib/SSRAM/sim/ModelSim SE .lnk | Bin 1447 -> 0 bytes lib/SSRAM/sim/tb_ssram_frontend_wb.fdo | 17 - lib/SSRAM/sim/tb_ssram_frontend_wb.wdo | 47 - lib/SSRAM/src/CY7C1354B.vhd | 388 -- lib/SSRAM/src/package_utility.vhd | 73 - lib/SSRAM/src/ssram_frontend_wb.vhd | 181 - lib/SSRAM/src/tb_ssram_frontend_wb.vhd | 457 -- lib/VGA_ctrl/sim/ModelSim SE .lnk | Bin 1453 -> 0 bytes lib/VGA_ctrl/sim/tb_vga_frontend.fdo | 26 - lib/VGA_ctrl/sim/tb_vga_frontend.wdo | 79 - lib/VGA_ctrl/sim/tb_vga_frontend64.fdo | 28 - lib/VGA_ctrl/sim/tb_vga_frontend64.wdo | 240 - lib/VGA_ctrl/src/char_gen.vhd | 547 -- lib/VGA_ctrl/src/clkgen_virtex4.vhd | 106 - lib/VGA_ctrl/src/fonts/Fixedsys_8x15.bff | Bin 33044 -> 0 bytes lib/VGA_ctrl/src/fonts/Fixedsys_8x16.bff | Bin 33044 -> 0 bytes lib/VGA_ctrl/src/fonts/Fixedsys_9x16.bff | Bin 33044 -> 0 bytes lib/VGA_ctrl/src/fonts/System_16x16.bff | Bin 65812 -> 0 bytes lib/VGA_ctrl/src/fonts/char_rom_c64.vhd | 540 -- lib/VGA_ctrl/src/fonts/char_rom_data.vhd | 539 -- lib/VGA_ctrl/src/fonts/char_rom_datasoft.vhd | 539 -- .../src/fonts/char_rom_demo_maker_m.vhd | 539 -- .../src/fonts/char_rom_fixedsys_8x15.vhd | 4383 -------------- .../src/fonts/char_rom_fixedsys_8x16.vhd | 4382 -------------- .../src/fonts/char_rom_fixedsys_9x16.vhd | 4351 -------------- .../src/fonts/char_rom_system_16x16.vhd | 4382 -------------- .../src/fonts/char_rom_the_goonies.vhd | 539 -- lib/VGA_ctrl/src/fonts/make_rom.bat | 6 - lib/VGA_ctrl/src/tb_vga_frontend.vhd | 322 - lib/VGA_ctrl/src/tb_vga_frontend64.vhd | 969 --- lib/VGA_ctrl/src/vga_backend.vhd | 177 - lib/VGA_ctrl/src/vga_frontend.vhd | 495 -- lib/VGA_ctrl/src/vga_frontend64.vhd | 1329 ----- lib/VGA_ctrl/src/vga_sync.vhd | 127 - lib/VGA_ctrl/src/vga_timing.vhd | 102 - lib/VGA_ctrl/src/vga_types.vhd | 158 - lib/VGA_ctrl/todo.txt | 21 - lib/ac97_ctrl/sim/tb_ac97_wb.fdo | 20 - lib/ac97_ctrl/sim/tb_ac97_wb.wdo | 77 - lib/ac97_ctrl/sim/tb_ac_in.fdo | 14 - lib/ac97_ctrl/sim/tb_ac_in.wdo | 43 - lib/ac97_ctrl/sim/tb_ac_io.fdo | 15 - lib/ac97_ctrl/sim/tb_ac_io.wdo | 51 - lib/ac97_ctrl/sim/tb_ac_out.fdo | 13 - lib/ac97_ctrl/sim/tb_ac_out.wdo | 41 - lib/ac97_ctrl/src/core/ac97_wb.vhd | 330 -- lib/ac97_ctrl/src/core/ac_in.vhd | 309 - lib/ac97_ctrl/src/core/ac_io.vhd | 189 - lib/ac97_ctrl/src/core/ac_out.vhd | 276 - lib/ac97_ctrl/src/tb_ac97_wb.vhd | 152 - lib/ac97_ctrl/src/tb_ac_in.vhd | 203 - lib/ac97_ctrl/src/tb_ac_io.vhd | 186 - lib/ac97_ctrl/src/tb_ac_out.vhd | 149 - lib/ac97_ctrl/todo.txt | 2 - lib/filter/sim/eval_lowpass.m | 37 - lib/filter/sim/lowpass.m | 20 - lib/filter/sim/tb_fir_iterative.fdo | 18 - lib/filter/sim/tb_fir_iterative.wdo | 144 - lib/filter/sim/tb_fir_parallel | Bin 1354927 -> 0 bytes lib/filter/sim/tb_fir_parallel.fdo | 18 - lib/filter/sim/tb_fir_parallel.wdo | 29 - lib/filter/sim/tb_fir_results.m | 10 - lib/filter/sim/tb_fir_semi_parallel.fdo | 20 - lib/filter/sim/tb_fir_semi_parallel.wdo | 57 - lib/filter/sim/tb_fir_stage.fdo | 17 - lib/filter/sim/tb_fir_stage.wdo | 31 - lib/filter/sim/tb_fir_stage_sys.fdo | 17 - lib/filter/sim/tb_fir_stage_sys.wdo | 28 - lib/filter/src/delay_line.vhd | 129 - lib/filter/src/filter_pkg.vhd | 219 - lib/filter/src/fir_iterative.vhd | 323 - lib/filter/src/fir_iterative_pkg.vhd | 52 - lib/filter/src/fir_parallel.vhd | 218 - lib/filter/src/fir_parallel_pkg.vhd | 29 - lib/filter/src/fir_pkg.vhd | 54 - lib/filter/src/fir_semi_parallel.vhd | 300 - lib/filter/src/fir_stage.vhd | 157 - lib/filter/src/fir_stage_pkg.vhd | 18 - lib/filter/src/fir_stage_sys.vhd | 109 - lib/filter/src/tb_fir_iterative.vhd | 234 - lib/filter/src/tb_fir_parallel.vhd | 193 - lib/filter/src/tb_fir_semi_parallel.vhd | 289 - lib/filter/src/tb_fir_stage.vhd | 276 - lib/filter/src/tb_fir_stage_sys.vhd | 230 - lib/fix_std/fix_std.vhd | 1007 ---- lib/fix_std/fix_stdb.vhd | 1910 ------ lib/fixed/fixed_util_pkg.vhd | 159 - lib/fixed_ja/fixed_ja.vhd | 322 - lib/fixed_ja/fixed_ja_body.vhd | 1921 ------ lib/jasm/cg.inc.jsm | 72 - lib/jasm/cregs.inc.jsm | 7 - lib/jasm/delays.inc.jsm | 64 - lib/jasm/lcd.inc.jsm | 208 - lib/jasm/mul8x8.inc.jsm | 42 - lib/jasm/uart.inc.jsm | 32 - lib/jasm/utils.inc.jsm | 32 - lib/misc/async_port_wb.vhd | 317 - lib/misc/async_types.vhd | 60 - lib/misc/bbfifo.vhd | 123 - lib/misc/clockgen_virtex4.vhd | 237 - lib/misc/debounce.vhd | 91 - lib/misc/debounce2.vhd | 142 - lib/misc/dpram_1w1r.vhd | 79 - lib/misc/dpram_1w1r1c_sim.vhd | 77 - lib/misc/dpram_1w1r1c_xil.vhd | 77 - lib/misc/dpram_1w1r2c_sim.vhd | 82 - lib/misc/dpram_1w1r2c_xil.vhd | 82 - lib/misc/dpram_1w1r_dist.vhd | 84 - lib/misc/dpram_1w2r1c_sim.vhd | 86 - lib/misc/dpram_1w2r1c_xil.vhd | 80 - lib/misc/dpram_2w2r.vhd | 88 - lib/misc/dpram_2w2r1c_sim.vhd | 88 - lib/misc/dpram_2w2r1c_xil.vhd | 82 - lib/misc/dpram_2w2r2c_sim.vhd | 95 - lib/misc/dpram_2w2r2c_xil.vhd | 93 - lib/misc/flash_port_wb.vhd | 293 - lib/misc/gpio_wb.vhd | 309 - lib/misc/lcd_port.vhd | 69 - lib/misc/mult_signed.vhd | 62 - lib/misc/oneshot.vhd | 223 - lib/misc/pkg_template.vhd | 18 - lib/misc/ram_sim.vhd | 88 - lib/misc/ram_wb.vhd | 87 - lib/misc/rom_sim.vhd | 2086 ------- lib/misc/rom_wb.vhd | 62 - lib/misc/sim/ModelSim SE .lnk | Bin 1477 -> 0 bytes lib/misc/sim/tb_bbfifo.fdo | 14 - lib/misc/sim/tb_bbfifo.wdo | 31 - lib/misc/sim/tb_ram_wb.fdo | 17 - lib/misc/sim/tb_ram_wb.wdo | 33 - lib/misc/sim/tb_rom_wb.fdo | 16 - lib/misc/sim/tb_rom_wb.wdo | 29 - lib/misc/singleshot.vhd | 155 - lib/misc/tb_bbfifo.vhd | 136 - lib/misc/tb_ram_wb.vhd | 414 -- lib/misc/tb_rom_wb.vhd | 223 - lib/misc/tb_template.vhd | 63 - lib/misc/utils_pkg.vhd | 196 - lib/misc/wire_delay.vhd | 42 - lib/ps2_port/sim/tb_ps2_core.fdo | 13 - lib/ps2_port/sim/tb_ps2_core.wdo | 48 - lib/ps2_port/src/debounce.vhd | 89 - lib/ps2_port/src/ps2_core.vhd | 620 -- lib/ps2_port/src/ps2_phy_virtex.vhd | 122 - lib/ps2_port/src/ps2_wb.vhd | 143 - lib/ps2_port/src/tb_ps2_core.vhd | 280 - lib/radio/cordic/eval_cordic.m | 171 - lib/radio/cordic/sim/eval_cordic.m | 10 - lib/radio/cordic/sim/tb_cordic_pipe_top.fdo | 18 - lib/radio/cordic/sim/tb_cordic_pipe_top.wdo | 37 - lib/radio/cordic/sim/tb_cordic_top.fdo | 19 - lib/radio/cordic/sim/tb_cordic_top.wdo | 64 - lib/radio/cordic/sim/tb_results.m | 34 - lib/radio/cordic/src/cordic_pipe_post.vhd | 107 - lib/radio/cordic/src/cordic_pipe_pre.vhd | 137 - lib/radio/cordic/src/cordic_pipe_stage.vhd | 115 - lib/radio/cordic/src/cordic_pipe_top.vhd | 319 - lib/radio/cordic/src/cordic_pkg.vhd | 208 - lib/radio/cordic/src/cordic_rom.vhd | 84 - lib/radio/cordic/src/cordic_stage.vhd | 291 - lib/radio/cordic/src/cordic_stage_post.vhd | 279 - lib/radio/cordic/src/cordic_stage_pre.vhd | 320 - lib/radio/cordic/src/cordic_top.vhd | 466 -- lib/radio/cordic/src/tb_cordic_pipe_top.vhd | 653 -- lib/radio/cordic/src/tb_cordic_top.vhd | 649 -- lib/radio/ddc/sim/tb_ddc.fdo | 34 - lib/radio/ddc/sim/tb_ddc.wdo | 126 - lib/radio/ddc/sim/tb_results.m | 57 - lib/radio/ddc/src/ddc.vhd | 508 -- lib/radio/ddc/src/syn_ddc.vhd | 419 -- lib/radio/ddc/src/tb_ddc.vhd | 397 -- lib/radio/decimator/CIC/sim/tb_cic_c_pipe.fdo | 14 - lib/radio/decimator/CIC/sim/tb_cic_c_pipe.wdo | 26 - .../decimator/CIC/sim/tb_cic_decim_pipe.fdo | 17 - .../decimator/CIC/sim/tb_cic_decim_pipe.wdo | 39 - lib/radio/decimator/CIC/sim/tb_cic_i_pipe.fdo | 14 - lib/radio/decimator/CIC/sim/tb_cic_i_pipe.wdo | 30 - lib/radio/decimator/CIC/src/cic_c_pipe.vhd | 104 - .../decimator/CIC/src/cic_decim_pipe.vhd | 203 - lib/radio/decimator/CIC/src/cic_i_pipe.vhd | 81 - .../decimator/CIC/src/syn_cic_c_pipe.vhd | 98 - .../decimator/CIC/src/syn_cic_i_pipe.vhd | 92 - lib/radio/decimator/CIC/src/tb_cic_c_pipe.vhd | 136 - .../decimator/CIC/src/tb_cic_decim_pipe.vhd | 153 - lib/radio/decimator/CIC/src/tb_cic_i_pipe.vhd | 126 - lib/radio/mix/sim/tb_mix_cpx.fdo | 15 - lib/radio/mix/sim/tb_mix_cpx.wdo | 42 - lib/radio/mix/sim/tb_mix_real.fdo | 15 - lib/radio/mix/sim/tb_mix_real.wdo | 36 - lib/radio/mix/sim/tb_undc_real.fdo | 15 - lib/radio/mix/sim/tb_undc_real.wdo | 38 - lib/radio/mix/src/mix_cpx.vhd | 171 - lib/radio/mix/src/mix_real.vhd | 160 - lib/radio/mix/src/tb_mix_cpx.vhd | 211 - lib/radio/mix/src/tb_mix_real.vhd | 200 - lib/radio/mix/src/tb_undc_real.vhd | 161 - lib/radio/mix/src/undc_real.vhd | 143 - lib/radio/nco/sim/tb_mix_cordic.fdo | 19 - lib/radio/nco/sim/tb_mix_cordic.wdo | 42 - lib/radio/nco/sim/tb_mix_results.m | 90 - lib/radio/nco/sim/tb_nco_cordic.fdo | 19 - lib/radio/nco/sim/tb_nco_cordic.wdo | 32 - lib/radio/nco/sim/tb_nco_lut.fdo | 17 - lib/radio/nco/sim/tb_nco_lut.wdo | 46 - lib/radio/nco/sim/tb_nco_results.m | 61 - lib/radio/nco/src/mix_cordic.vhd | 177 - lib/radio/nco/src/nco.vhd.bak | 240 - lib/radio/nco/src/nco_lut.vhd | 229 - lib/radio/nco/src/nco_lut_dbg.vhd | 259 - lib/radio/nco/src/nco_pkg.vhd | 95 - lib/radio/nco/src/tb_mix_cordic.vhd | 331 -- lib/radio/nco/src/tb_nco_cordic.vhd | 265 - lib/radio/nco/src/tb_nco_lut.vhd | 303 - lib/radio/nco/src/wavelut.vhd | 245 - lib/radio/nco/src/waverom_dual.vhd | 92 - lib/rams/dpram_1w1r2c_ra_sim.vhd | 82 - lib/rams/dpram_1w1r2c_ra_xil.vhd | 82 - lib/rams/dpram_1w1r2c_ro_sim.vhd | 80 - lib/rams/dpram_1w1r2c_ro_xil.vhd | 81 - lib/rams/dpram_2w2r2c_ra_sim.vhd | 95 - lib/rams/dpram_2w2r2c_ra_xil.vhd | 93 - lib/rams/dpram_2w2r2c_ro_sim.vhd | 88 - lib/rams/dpram_2w2r2c_ro_xil.vhd | 88 - lib/uart/bbfifo_16x8.vhd | 281 - lib/uart/kcuart_rx.vhd | 352 -- lib/uart/kcuart_tx.vhd | 394 -- lib/uart/uart_rx.vhd | 146 - lib/uart/uart_tx.vhd | 153 - lib/uart/uart_wb.vhd | 219 - .../mips_sys/ise101/mips_sys/mips_sys.par | 201 - .../mips_sys/ise101/mips_sys/mips_sys.prj | 47 - .../mips_sys/ise101/mips_sys/mips_sys.syr | 5227 ----------------- .../mips_sys/ise101/mips_sys/mips_sys.twr | 1177 ---- projects/mips_sys/ise101/mips_sys/mips_sys.ut | 33 - .../mips_sys/ise101/mips_sys/mips_sys.xst | 62 - .../mips_sys/ise101/mips_sys/mips_sys_map.mrp | 1792 ------ .../ise101/mips_sys/mips_sys_vhdl.prj | 47 - .../ise101/mips_sys/ucf/systest.ssram.ucf | 503 -- .../mips_sys/ise101/mips_sys/ucf/systest.ucf | 629 -- projects/mips_sys/ise92/mips_sys/mips_sys.prj | 43 - .../mips_sys/ise92/mips_sys/mips_sys_vhdl.prj | 43 - .../mips_sys/ise92/mips_sys/ucf/systest.ucf | 469 -- projects/mips_sys/sim/tb_mips_sys.fdo | 118 - projects/mips_sys/sim/tb_mips_sys.wdo | 457 -- projects/mips_sys/sim/tb_mips_sys_emac.fdo | 116 - projects/mips_sys/sim/tb_mips_sys_emac.wdo | 185 - projects/mips_sys/src/.directory_history | 4 - projects/mips_sys/src/async_defs_sim.vhd | 70 - projects/mips_sys/src/bootloader.ROM.vhd | 2082 ------- projects/mips_sys/src/bootloader.ROM_ld.vhd | 2174 ------- projects/mips_sys/src/bootloader.dis | 1466 ----- projects/mips_sys/src/clockgen_virtex4.vhd | 363 -- projects/mips_sys/src/mips_sys.vhd | 1169 ---- projects/mips_sys/src/mips_sys_sim.vhd | 1048 ---- projects/mips_sys/src/ram_ld.vhd | 173 - projects/mips_sys/src/ram_sim.vhd | 88 - projects/mips_sys/src/sdram_config.vhd | 74 - projects/mips_sys/src/sdram_config_sim.vhd | 74 - projects/mips_sys/src/sys_types.vhd | 70 - projects/mips_sys/src/tb_mips_sys.vhd | 420 -- projects/mips_sys/tools/insrom.rb | 46 - projects/mips_sys/tools/irom.vhd.tpl | 29 - projects/mips_sys/tools/irom_ld.vhd.tpl | 147 - projects/mips_sys/tools/make | 50 - projects/mips_sys/tools/rom.tcl.tpl | 61 - projects/mips_sys/tools/src/flashgen.c | 117 - projects/mips_sys/tools/src/ramgen.c | 385 -- projects/mips_sys/tools/src/romgen.c | 368 -- 651 files changed, 168762 deletions(-) delete mode 100644 Common/sim/ModelSim SE .lnk delete mode 100644 Common/sim/compile_fixed.do delete mode 100644 Common/sim/compile_simprim.do delete mode 100644 Common/sim/compile_unisim.do delete mode 100644 Common/ucf/ml402.ucf delete mode 100644 lib/CPUs/J1/doc/j1.pdf delete mode 100644 lib/CPUs/J1/sim/tb_j1.do delete mode 100644 lib/CPUs/J1/sim/tb_j1.wave.do delete mode 100644 lib/CPUs/J1/src/core/j1.v delete mode 100644 lib/CPUs/J1/src/core/j1.vhd delete mode 100644 lib/CPUs/J1/src/core/ram_2c_2r_2w.vhd delete mode 100644 lib/CPUs/J1/src/tb_j1.vhd delete mode 100644 lib/CPUs/JCpu/asm/dctest.jsm delete mode 100644 lib/CPUs/JCpu/asm/dctest.tcl delete mode 100644 lib/CPUs/JCpu/asm/itest.jsm delete mode 100644 lib/CPUs/JCpu/asm/itest.tcl delete mode 100644 lib/CPUs/JCpu/asm/make delete mode 100644 lib/CPUs/JCpu/asm/mul8x8.jsm delete mode 100644 lib/CPUs/JCpu/asm/mul8x8.tcl delete mode 100644 lib/CPUs/JCpu/asm/reti_issue.jsm delete mode 100644 lib/CPUs/JCpu/asm/reti_issue.tcl delete mode 100644 lib/CPUs/JCpu/doc/block_diagram.png delete mode 100644 lib/CPUs/JCpu/doc/memory_map.png delete mode 100644 lib/CPUs/JCpu/gpl-3.0.txt delete mode 100644 lib/CPUs/JCpu/sim/ModelSim SE .lnk delete mode 100644 lib/CPUs/JCpu/sim/tb_cpu.fdo delete mode 100644 lib/CPUs/JCpu/sim/tb_cpu.wdo delete mode 100644 lib/CPUs/JCpu/sim/tb_cpu_embedded.fdo delete mode 100644 lib/CPUs/JCpu/sim/tb_cpu_embedded.wdo delete mode 100644 lib/CPUs/JCpu/sim/tb_cpu_itest.fdo delete mode 100644 lib/CPUs/JCpu/sim/tb_cpu_itest.wdo delete mode 100644 lib/CPUs/JCpu/sim/tb_cpu_reti_issue.fdo delete mode 100644 lib/CPUs/JCpu/sim/tb_cpu_reti_issue.wdo delete mode 100644 lib/CPUs/JCpu/sim/tb_mul8x8.fdo delete mode 100644 lib/CPUs/JCpu/sim/tb_mul8x8.wdo delete mode 100644 lib/CPUs/JCpu/src/core/alu.vhd delete mode 100644 lib/CPUs/JCpu/src/core/chipram.vhd delete mode 100644 lib/CPUs/JCpu/src/core/chipreg.vhd delete mode 100644 lib/CPUs/JCpu/src/core/cpu.vhd delete mode 100644 lib/CPUs/JCpu/src/core/cpu_pkg.vhd delete mode 100644 lib/CPUs/JCpu/src/core/dpath_ctrl.vhd delete mode 100644 lib/CPUs/JCpu/src/core/int_ctrl.vhd delete mode 100644 lib/CPUs/JCpu/src/core/pc.vhd delete mode 100644 lib/CPUs/JCpu/src/core/reg_dual.vhd delete mode 100644 lib/CPUs/JCpu/src/core/stack_ctrl.vhd delete mode 100644 lib/CPUs/JCpu/src/cpu_embedded.vhd delete mode 100644 lib/CPUs/JCpu/src/dctest_irom.vhdl delete mode 100644 lib/CPUs/JCpu/src/dctest_irom_ld.vhdl delete mode 100644 lib/CPUs/JCpu/src/dctest_xrom.vhdl delete mode 100644 lib/CPUs/JCpu/src/dctest_xrom_ld.vhdl delete mode 100644 lib/CPUs/JCpu/src/itest_irom.vhdl delete mode 100644 lib/CPUs/JCpu/src/itest_irom_ld.vhdl delete mode 100644 lib/CPUs/JCpu/src/itest_xrom.vhdl delete mode 100644 lib/CPUs/JCpu/src/itest_xrom_ld.vhdl delete mode 100644 lib/CPUs/JCpu/src/mul8x8_irom.vhdl delete mode 100644 lib/CPUs/JCpu/src/mul8x8_irom_ld.vhdl delete mode 100644 lib/CPUs/JCpu/src/mul8x8_xrom.vhdl delete mode 100644 lib/CPUs/JCpu/src/mul8x8_xrom_ld.vhdl delete mode 100644 lib/CPUs/JCpu/src/reti_issue_irom.vhdl delete mode 100644 lib/CPUs/JCpu/src/reti_issue_irom_ld.vhdl delete mode 100644 lib/CPUs/JCpu/src/reti_issue_xrom.vhdl delete mode 100644 lib/CPUs/JCpu/src/reti_issue_xrom_ld.vhdl delete mode 100644 lib/CPUs/JCpu/src/tb_cpu_embedded.vhd delete mode 100644 lib/CPUs/JCpu/src/tb_cpu_irq.vhd delete mode 100644 lib/CPUs/JCpu/src/tb_cpu_itest.vhd delete mode 100644 lib/CPUs/JCpu/syn/ise91/cpu_vhdl.prj delete mode 100644 lib/CPUs/JCpu/tools/eval_scan.rb delete mode 100644 lib/CPUs/JCpu/tools/insrom.rb delete mode 100644 lib/CPUs/JCpu/tools/irom.vhd.tpl delete mode 100644 lib/CPUs/JCpu/tools/irom_ld.vhd.tpl delete mode 100644 lib/CPUs/JCpu/tools/jasm.bak.rb delete mode 100644 lib/CPUs/JCpu/tools/jasm.rb delete mode 100644 lib/CPUs/JCpu/tools/lib/cg.inc.jsm delete mode 100644 lib/CPUs/JCpu/tools/lib/cregs.inc.jsm delete mode 100644 lib/CPUs/JCpu/tools/lib/delays.inc.jsm delete mode 100644 lib/CPUs/JCpu/tools/lib/lcd.inc.jsm delete mode 100644 lib/CPUs/JCpu/tools/lib/mul8x8.inc.jsm delete mode 100644 lib/CPUs/JCpu/tools/lib/uart.inc.jsm delete mode 100644 lib/CPUs/JCpu/tools/lib/utils.inc.jsm delete mode 100644 lib/CPUs/JCpu/tools/opc.list delete mode 100644 lib/CPUs/JCpu/tools/regx.rb delete mode 100644 lib/CPUs/JCpu/tools/rom.tcl.tpl delete mode 100644 lib/CPUs/JCpu/tools/templates.rb delete mode 100644 lib/CPUs/JCpu/tools/xrom.vhd.tpl delete mode 100644 lib/CPUs/JCpu/tools/xrom_ld.vhd.tpl delete mode 100644 lib/CPUs/MIPS/bsp/examples/.directory_history delete mode 100644 lib/CPUs/MIPS/bsp/examples/Bessel.c delete mode 100644 lib/CPUs/MIPS/bsp/examples/Makefile delete mode 100644 lib/CPUs/MIPS/bsp/examples/aes256.c delete mode 100644 lib/CPUs/MIPS/bsp/examples/aes256.h delete mode 100644 lib/CPUs/MIPS/bsp/examples/aes256_1.c delete mode 100644 lib/CPUs/MIPS/bsp/examples/barcode.c delete mode 100644 lib/CPUs/MIPS/bsp/examples/barcode.new.c delete mode 100644 lib/CPUs/MIPS/bsp/examples/basicmath_small.c delete mode 100644 lib/CPUs/MIPS/bsp/examples/bogomips.c delete mode 100644 lib/CPUs/MIPS/bsp/examples/bootloader/Makefile delete mode 100644 lib/CPUs/MIPS/bsp/examples/bootloader/bootloader.c delete mode 100644 lib/CPUs/MIPS/bsp/examples/bootloader/bootloader.ld delete mode 100644 lib/CPUs/MIPS/bsp/examples/bootloader/bootloader_with_flash.c delete mode 100644 lib/CPUs/MIPS/bsp/examples/bootloader/init_boot.S delete mode 100644 lib/CPUs/MIPS/bsp/examples/bootloader/jtag_upd.bat delete mode 100644 lib/CPUs/MIPS/bsp/examples/bootloader/kernel_boot.S delete mode 100644 lib/CPUs/MIPS/bsp/examples/bootloader/libsys_boot.c delete mode 100644 lib/CPUs/MIPS/bsp/examples/bootloader/libsys_boot.h delete mode 100644 lib/CPUs/MIPS/bsp/examples/bootloader/startup_boot.S delete mode 100644 lib/CPUs/MIPS/bsp/examples/cfiflash.c delete mode 100644 lib/CPUs/MIPS/bsp/examples/cfiflash.h delete mode 100644 lib/CPUs/MIPS/bsp/examples/crc32.c delete mode 100644 lib/CPUs/MIPS/bsp/examples/crc32.h delete mode 100644 lib/CPUs/MIPS/bsp/examples/cubic.c delete mode 100644 lib/CPUs/MIPS/bsp/examples/dbg.c delete mode 100644 lib/CPUs/MIPS/bsp/examples/delay_mips.c delete mode 100644 lib/CPUs/MIPS/bsp/examples/demo.c delete mode 100644 lib/CPUs/MIPS/bsp/examples/dhry.h delete mode 100644 lib/CPUs/MIPS/bsp/examples/dhry_1.c delete mode 100644 lib/CPUs/MIPS/bsp/examples/dhry_2.c delete mode 100644 lib/CPUs/MIPS/bsp/examples/dttl.c delete mode 100644 lib/CPUs/MIPS/bsp/examples/gunzip.c delete mode 100644 lib/CPUs/MIPS/bsp/examples/hashtest.c delete mode 100644 lib/CPUs/MIPS/bsp/examples/hello.c delete mode 100644 lib/CPUs/MIPS/bsp/examples/hpi.c delete mode 100644 lib/CPUs/MIPS/bsp/examples/hpi.h delete mode 100644 lib/CPUs/MIPS/bsp/examples/inflate.c delete mode 100644 lib/CPUs/MIPS/bsp/examples/inflate.h delete mode 100644 lib/CPUs/MIPS/bsp/examples/irq.c delete mode 100644 lib/CPUs/MIPS/bsp/examples/irq.h delete mode 100644 lib/CPUs/MIPS/bsp/examples/isqrt.c delete mode 100644 lib/CPUs/MIPS/bsp/examples/kernel.S delete mode 100644 lib/CPUs/MIPS/bsp/examples/libsys.c delete mode 100644 lib/CPUs/MIPS/bsp/examples/libsys.h delete mode 100644 lib/CPUs/MIPS/bsp/examples/libsys/.directory_history delete mode 100644 lib/CPUs/MIPS/bsp/examples/libsys/Makefile delete mode 100644 lib/CPUs/MIPS/bsp/examples/libsys/mips_ps2.c delete mode 100644 lib/CPUs/MIPS/bsp/examples/libsys/mips_ps2.h delete mode 100644 lib/CPUs/MIPS/bsp/examples/libsys/syscalls.c delete mode 100644 lib/CPUs/MIPS/bsp/examples/life.c delete mode 100644 lib/CPUs/MIPS/bsp/examples/link/link.ld delete mode 100644 lib/CPUs/MIPS/bsp/examples/lua_init.c delete mode 100644 lib/CPUs/MIPS/bsp/examples/lwl.c delete mode 100644 lib/CPUs/MIPS/bsp/examples/mandelbrot.c delete mode 100644 lib/CPUs/MIPS/bsp/examples/mips_gfx.c delete mode 100644 lib/CPUs/MIPS/bsp/examples/mips_gfx.h delete mode 100644 lib/CPUs/MIPS/bsp/examples/mipsdis.c delete mode 100644 lib/CPUs/MIPS/bsp/examples/mipsdis.h delete mode 100644 lib/CPUs/MIPS/bsp/examples/paranoia.c delete mode 100644 lib/CPUs/MIPS/bsp/examples/phrasen.c delete mode 100644 lib/CPUs/MIPS/bsp/examples/pi.h delete mode 100644 lib/CPUs/MIPS/bsp/examples/queens.c delete mode 100644 lib/CPUs/MIPS/bsp/examples/r3.c delete mode 100644 lib/CPUs/MIPS/bsp/examples/rad2deg.c delete mode 100644 lib/CPUs/MIPS/bsp/examples/random.c delete mode 100644 lib/CPUs/MIPS/bsp/examples/random.h delete mode 100644 lib/CPUs/MIPS/bsp/examples/regdef.h delete mode 100644 lib/CPUs/MIPS/bsp/examples/richards_benchmark.c delete mode 100644 lib/CPUs/MIPS/bsp/examples/rmd160.c delete mode 100644 lib/CPUs/MIPS/bsp/examples/rmd160.h delete mode 100644 lib/CPUs/MIPS/bsp/examples/rmd160_test.c delete mode 100644 lib/CPUs/MIPS/bsp/examples/round.h delete mode 100644 lib/CPUs/MIPS/bsp/examples/serdump.c delete mode 100644 lib/CPUs/MIPS/bsp/examples/snipmath.h delete mode 100644 lib/CPUs/MIPS/bsp/examples/sniptype.h delete mode 100644 lib/CPUs/MIPS/bsp/examples/specs/specs delete mode 100644 lib/CPUs/MIPS/bsp/examples/stanford.c delete mode 100644 lib/CPUs/MIPS/bsp/examples/startup.S delete mode 100644 lib/CPUs/MIPS/bsp/examples/test_ac97.c delete mode 100644 lib/CPUs/MIPS/bsp/examples/test_dcache.c delete mode 100644 lib/CPUs/MIPS/bsp/examples/test_endianess.c delete mode 100644 lib/CPUs/MIPS/bsp/examples/test_exception.c delete mode 100644 lib/CPUs/MIPS/bsp/examples/test_flash.c delete mode 100644 lib/CPUs/MIPS/bsp/examples/test_hpi.c delete mode 100644 lib/CPUs/MIPS/bsp/examples/test_irq.c delete mode 100644 lib/CPUs/MIPS/bsp/examples/test_mipsdis.c delete mode 100644 lib/CPUs/MIPS/bsp/examples/test_timer.c delete mode 100644 lib/CPUs/MIPS/bsp/examples/test_vga.c delete mode 100644 lib/CPUs/MIPS/bsp/examples/testbench.c delete mode 100644 lib/CPUs/MIPS/bsp/examples/testlibusb.c delete mode 100644 lib/CPUs/MIPS/bsp/examples/ucb.c delete mode 100644 lib/CPUs/MIPS/bsp/examples/whet.c delete mode 100644 lib/CPUs/MIPS/bsp/examples/xcpt.c delete mode 100644 lib/CPUs/MIPS/bsp/examples/xcpt.h delete mode 100644 lib/CPUs/MIPS/bsp/examples/xcpt_asm.h delete mode 100644 lib/CPUs/MIPS/dist/gpl-3.0.txt delete mode 100644 lib/CPUs/MIPS/dist/makedist.R12 delete mode 100644 lib/CPUs/MIPS/dist/makedist.R13 delete mode 100644 lib/CPUs/MIPS/dist/notes.txt delete mode 100644 lib/CPUs/MIPS/doc/J-MIPS.txt delete mode 100644 lib/CPUs/MIPS/doc/async_port_timing.pdf delete mode 100644 lib/CPUs/MIPS/doc/memory_map.pdf delete mode 100644 lib/CPUs/MIPS/doc/memory_map.vsd delete mode 100644 lib/CPUs/MIPS/doc/mips_biu.pdf delete mode 100644 lib/CPUs/MIPS/doc/mips_drawings.vsd delete mode 100644 lib/CPUs/MIPS/doc/mips_jbus_timing.pdf delete mode 100644 lib/CPUs/MIPS/doc/mips_pipeline.pdf delete mode 100644 lib/CPUs/MIPS/doc/mips_pipeline_stages.pdf delete mode 100644 lib/CPUs/MIPS/doc/mips_sys.vsd delete mode 100644 lib/CPUs/MIPS/doc/mips_sys_ml402.pdf delete mode 100644 lib/CPUs/MIPS/doc/toolchain/howto_build.txt delete mode 100644 lib/CPUs/MIPS/doc/toolchain/make.sh delete mode 100644 lib/CPUs/MIPS/doc/toolchain/newlib-1.16.0-jens.patch delete mode 100644 lib/CPUs/MIPS/doc/toolchain/newlib-1.17.0-jens.patch delete mode 100644 lib/CPUs/MIPS/sim/ModelSim SE .lnk delete mode 100644 lib/CPUs/MIPS/sim/asm/exception.s delete mode 100644 lib/CPUs/MIPS/sim/asm/faculty.c delete mode 100644 lib/CPUs/MIPS/sim/asm/faculty.s delete mode 100644 lib/CPUs/MIPS/sim/asm/fibonacci.c delete mode 100644 lib/CPUs/MIPS/sim/asm/fibonacci.s delete mode 100644 lib/CPUs/MIPS/sim/asm/idata.ld delete mode 100644 lib/CPUs/MIPS/sim/asm/init.s delete mode 100644 lib/CPUs/MIPS/sim/asm/jtag.sh delete mode 100644 lib/CPUs/MIPS/sim/asm/kernel.s delete mode 100644 lib/CPUs/MIPS/sim/asm/link.ld delete mode 100644 lib/CPUs/MIPS/sim/asm/load_store.c delete mode 100644 lib/CPUs/MIPS/sim/asm/load_store.s delete mode 100644 lib/CPUs/MIPS/sim/asm/make.sh delete mode 100644 lib/CPUs/MIPS/sim/asm/mips_exception.s delete mode 100644 lib/CPUs/MIPS/sim/asm/mips_load_store_.txt delete mode 100644 lib/CPUs/MIPS/sim/asm/muldiv.c delete mode 100644 lib/CPUs/MIPS/sim/asm/muldiv.s delete mode 100644 lib/CPUs/MIPS/sim/asm/mult.txt delete mode 100644 lib/CPUs/MIPS/sim/asm/rmd160.s delete mode 100644 lib/CPUs/MIPS/sim/asm/rmd160_test.s delete mode 100644 lib/CPUs/MIPS/sim/asm/spim_load_store.s delete mode 100644 lib/CPUs/MIPS/sim/asm/startup.s delete mode 100644 lib/CPUs/MIPS/sim/asm/test1.s delete mode 100644 lib/CPUs/MIPS/sim/asm/test2.s delete mode 100644 lib/CPUs/MIPS/sim/asm/test3.s delete mode 100644 lib/CPUs/MIPS/sim/asm/test4.s delete mode 100644 lib/CPUs/MIPS/sim/asm/test5.s delete mode 100644 lib/CPUs/MIPS/sim/asm/test6.s delete mode 100644 lib/CPUs/MIPS/sim/asm/test7.s delete mode 100644 lib/CPUs/MIPS/sim/asm/test_addsub.s delete mode 100644 lib/CPUs/MIPS/sim/asm/test_muldiv.s delete mode 100644 lib/CPUs/MIPS/sim/asm/test_slt.s delete mode 100644 lib/CPUs/MIPS/sim/asm/test_slti.s delete mode 100644 lib/CPUs/MIPS/sim/asm/test_sub.s delete mode 100644 lib/CPUs/MIPS/sim/asm/testbench.c delete mode 100644 lib/CPUs/MIPS/sim/asm/testbench.s delete mode 100644 lib/CPUs/MIPS/sim/asm/utils.c delete mode 100644 lib/CPUs/MIPS/sim/asm/utils.h delete mode 100644 lib/CPUs/MIPS/sim/asm/utils.s delete mode 100644 lib/CPUs/MIPS/sim/hello.flash.bin delete mode 100644 lib/CPUs/MIPS/sim/tb_mips_muldiv.fdo delete mode 100644 lib/CPUs/MIPS/sim/tb_mips_muldiv.wdo delete mode 100644 lib/CPUs/MIPS/sim/tb_mips_sys.fdo delete mode 100644 lib/CPUs/MIPS/sim/tb_mips_sys.wdo delete mode 100644 lib/CPUs/MIPS/sim/tb_mips_top.fdo delete mode 100644 lib/CPUs/MIPS/sim/tb_mips_top.wdo delete mode 100644 lib/CPUs/MIPS/sim/tb_mips_top_syn.fdo delete mode 100644 lib/CPUs/MIPS/sim/tb_mips_top_syn.wdo delete mode 100644 lib/CPUs/MIPS/src/async_defs.vhd delete mode 100644 lib/CPUs/MIPS/src/bootloader.ROM.vhd delete mode 100644 lib/CPUs/MIPS/src/bootloader.dis delete mode 100644 lib/CPUs/MIPS/src/core/.directory_history delete mode 100644 lib/CPUs/MIPS/src/core/dcache.vhd delete mode 100644 lib/CPUs/MIPS/src/core/icache.vhd delete mode 100644 lib/CPUs/MIPS/src/core/mips_alu.vhd delete mode 100644 lib/CPUs/MIPS/src/core/mips_bcu.vhd delete mode 100644 lib/CPUs/MIPS/src/core/mips_bui.vhd delete mode 100644 lib/CPUs/MIPS/src/core/mips_cop.vhd delete mode 100644 lib/CPUs/MIPS/src/core/mips_instr.vhd delete mode 100644 lib/CPUs/MIPS/src/core/mips_muldiv.vhd delete mode 100644 lib/CPUs/MIPS/src/core/mips_pipeline.vhd delete mode 100644 lib/CPUs/MIPS/src/core/mips_reg.vhd delete mode 100644 lib/CPUs/MIPS/src/core/mips_shifter.vhd delete mode 100644 lib/CPUs/MIPS/src/core/mips_top.vhd delete mode 100644 lib/CPUs/MIPS/src/core/mips_types.vhd delete mode 100644 lib/CPUs/MIPS/src/mips_sys.vhd delete mode 100644 lib/CPUs/MIPS/src/mips_top_syn.vhd delete mode 100644 lib/CPUs/MIPS/src/tb_mips_muldiv.vhd delete mode 100644 lib/CPUs/MIPS/src/tb_mips_sys.vhd delete mode 100644 lib/CPUs/MIPS/src/tb_mips_top.vhd delete mode 100644 lib/CPUs/MIPS/syn/ise101/constraints/mips_top.xcf delete mode 100644 lib/CPUs/MIPS/syn/ise101/mips_top.prj delete mode 100644 lib/CPUs/MIPS/syn/ise101/mips_top_vhdl.prj delete mode 100644 lib/CPUs/MIPS/todo.txt delete mode 100644 lib/CPUs/MIPS/tools/Makefile delete mode 100644 lib/CPUs/MIPS/tools/flashgen.exe delete mode 100644 lib/CPUs/MIPS/tools/flashgen_big.exe delete mode 100644 lib/CPUs/MIPS/tools/flashgen_little.exe delete mode 100644 lib/CPUs/MIPS/tools/ramgen.exe delete mode 100644 lib/CPUs/MIPS/tools/romgen.exe delete mode 100644 lib/CPUs/MIPS/tools/src/flashgen.c delete mode 100644 lib/CPUs/MIPS/tools/src/ramgen.c delete mode 100644 lib/CPUs/MIPS/tools/src/romgen.c delete mode 100644 lib/FIFO/sim/tb_fifo_async.fdo delete mode 100644 lib/FIFO/sim/tb_fifo_async.wdo delete mode 100644 lib/FIFO/sim/tb_fifo_sync.fdo delete mode 100644 lib/FIFO/sim/tb_fifo_sync.wdo delete mode 100644 lib/FIFO/sim/tb_gray_counter.fdo delete mode 100644 lib/FIFO/sim/tb_gray_counter.wdo delete mode 100644 lib/FIFO/src/.directory_history delete mode 100644 lib/FIFO/src/async_fifo_ctrl.vhd delete mode 100644 lib/FIFO/src/fifo_async.vhd delete mode 100644 lib/FIFO/src/fifo_ctrl_pkg.vhd delete mode 100644 lib/FIFO/src/fifo_sync.vhd delete mode 100644 lib/FIFO/src/fifo_sync_dist.vhd delete mode 100644 lib/FIFO/src/gray_counter.vhd delete mode 100644 lib/FIFO/src/sync_fifo_ctrl.vhd delete mode 100644 lib/FIFO/src/tb_fifo_async.vhd delete mode 100644 lib/FIFO/src/tb_fifo_sync.vhd delete mode 100644 lib/FIFO/src/tb_gray_counter.vhd delete mode 100644 lib/JBUS/sim/tb_busmaster_async.fdo delete mode 100644 lib/JBUS/sim/tb_busmaster_async.wdo delete mode 100644 lib/JBUS/sim/tb_busmaster_sync.fdo delete mode 100644 lib/JBUS/sim/tb_busmaster_sync.wdo delete mode 100644 lib/JBUS/sim/tb_dmac.fdo delete mode 100644 lib/JBUS/sim/tb_dmac.wdo delete mode 100644 lib/JBUS/src/busmaster_async.vhd delete mode 100644 lib/JBUS/src/busmaster_sync.vhd delete mode 100644 lib/JBUS/src/busmaster_types.vhd delete mode 100644 lib/JBUS/src/dmac.vhd delete mode 100644 lib/JBUS/src/tb_busmaster_async.vhd delete mode 100644 lib/JBUS/src/tb_busmaster_sync.vhd delete mode 100644 lib/JBUS/src/tb_dmac.vhd delete mode 100644 lib/PCK_FIO-1.16/PCK_FIO.html delete mode 100644 lib/PCK_FIO-1.16/PCK_FIO.out.gold delete mode 100644 lib/PCK_FIO-1.16/PCK_FIO.vhd delete mode 100644 lib/PCK_FIO-1.16/README delete mode 100644 lib/PCK_FIO-1.16/TB_PCK_FIO.vhd delete mode 100644 lib/PCK_FIO-2002.7/CHANGES delete mode 100644 lib/PCK_FIO-2002.7/PCK_FIO.html delete mode 100644 lib/PCK_FIO-2002.7/PCK_FIO.out.gold delete mode 100644 lib/PCK_FIO-2002.7/PCK_FIO_1987.vhd delete mode 100644 lib/PCK_FIO-2002.7/PCK_FIO_1987_BODY.vhd delete mode 100644 lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd delete mode 100644 lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd delete mode 100644 lib/PCK_FIO-2002.7/README delete mode 100644 lib/PCK_FIO-2002.7/TB_PCK_FIO_1987.vhd delete mode 100644 lib/PCK_FIO-2002.7/TB_PCK_FIO_1993.vhd delete mode 100644 lib/PCK_FIO-2002.7/msMakefile.TBE_PCK_FIO_TB.1987 delete mode 100644 lib/PCK_FIO-2002.7/msMakefile.TBE_PCK_FIO_TB.1993 delete mode 100644 lib/SDRAM/ddr_sdr_v1_4/doc/SDRAM_CTRL.vsd delete mode 100644 lib/SDRAM/ddr_sdr_v1_4/ise9/sdram_ctrl_top_vhdl.prj delete mode 100644 lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl.fdo delete mode 100644 lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl.wdo delete mode 100644 lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_fifo.fdo delete mode 100644 lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_fifo.wdo delete mode 100644 lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_r_rand_w.fdo delete mode 100644 lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_r_rand_w.wdo delete mode 100644 lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_w_rand_r.fdo delete mode 100644 lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_w_rand_r.wdo delete mode 100644 lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_addr.fdo delete mode 100644 lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_addr.wdo delete mode 100644 lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_rw.fdo delete mode 100644 lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_rw.wdo delete mode 100644 lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdram_ctrl_frontend.fdo delete mode 100644 lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdram_ctrl_frontend.wdo delete mode 100644 lib/SDRAM/ddr_sdr_v1_4/src/clockgen_virtex4.vhd delete mode 100644 lib/SDRAM/ddr_sdr_v1_4/src/ddr_phy_virtex4.vhd delete mode 100644 lib/SDRAM/ddr_sdr_v1_4/src/fifo_sync.vhd delete mode 100644 lib/SDRAM/ddr_sdr_v1_4/src/mt46v16m16.vhd delete mode 100644 lib/SDRAM/ddr_sdr_v1_4/src/reset_virtex4.vhd delete mode 100644 lib/SDRAM/ddr_sdr_v1_4/src/sdram_cmd.vhd delete mode 100644 lib/SDRAM/ddr_sdr_v1_4/src/sdram_config.vhd delete mode 100644 lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl.vhd delete mode 100644 lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl_frontend.vhd delete mode 100644 lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl_top.vhd delete mode 100644 lib/SDRAM/ddr_sdr_v1_4/src/sdram_types.vhd delete mode 100644 lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl.vhd delete mode 100644 lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_fifo.vhd delete mode 100644 lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_lin_r_rand_w.vhd delete mode 100644 lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_lin_w_rand_r.vhd delete mode 100644 lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_rand_addr.vhd delete mode 100644 lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_rand_rw.vhd delete mode 100644 lib/SDRAM/ddr_sdr_v1_4/src/tb_sdram_ctrl_frontend.vhd delete mode 100644 lib/SDRAM/ddr_sdr_v1_5/doc/SDRAM_CTRL.vsd delete mode 100644 lib/SDRAM/ddr_sdr_v1_5/sim/ModelSim SE .lnk delete mode 100644 lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend64_wb.fdo delete mode 100644 lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend64_wb.wdo delete mode 100644 lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend_wb.fdo delete mode 100644 lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend_wb.wdo delete mode 100644 lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd delete mode 100644 lib/SDRAM/ddr_sdr_v1_5/src/mt46v16m16.vhd delete mode 100644 lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd delete mode 100644 lib/SDRAM/ddr_sdr_v1_5/src/sdram_config.vhd delete mode 100644 lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd delete mode 100644 lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd delete mode 100644 lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb.vhd delete mode 100644 lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd delete mode 100644 lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd delete mode 100644 lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend64_wb.vhd delete mode 100644 lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend_wb.vhd delete mode 100644 lib/SDRAM/ddr_sdr_v1_5/todo.txt delete mode 100644 lib/SSRAM/sim/ModelSim SE .lnk delete mode 100644 lib/SSRAM/sim/tb_ssram_frontend_wb.fdo delete mode 100644 lib/SSRAM/sim/tb_ssram_frontend_wb.wdo delete mode 100644 lib/SSRAM/src/CY7C1354B.vhd delete mode 100644 lib/SSRAM/src/package_utility.vhd delete mode 100644 lib/SSRAM/src/ssram_frontend_wb.vhd delete mode 100644 lib/SSRAM/src/tb_ssram_frontend_wb.vhd delete mode 100644 lib/VGA_ctrl/sim/ModelSim SE .lnk delete mode 100644 lib/VGA_ctrl/sim/tb_vga_frontend.fdo delete mode 100644 lib/VGA_ctrl/sim/tb_vga_frontend.wdo delete mode 100644 lib/VGA_ctrl/sim/tb_vga_frontend64.fdo delete mode 100644 lib/VGA_ctrl/sim/tb_vga_frontend64.wdo delete mode 100644 lib/VGA_ctrl/src/char_gen.vhd delete mode 100644 lib/VGA_ctrl/src/clkgen_virtex4.vhd delete mode 100644 lib/VGA_ctrl/src/fonts/Fixedsys_8x15.bff delete mode 100644 lib/VGA_ctrl/src/fonts/Fixedsys_8x16.bff delete mode 100644 lib/VGA_ctrl/src/fonts/Fixedsys_9x16.bff delete mode 100644 lib/VGA_ctrl/src/fonts/System_16x16.bff delete mode 100644 lib/VGA_ctrl/src/fonts/char_rom_c64.vhd delete mode 100644 lib/VGA_ctrl/src/fonts/char_rom_data.vhd delete mode 100644 lib/VGA_ctrl/src/fonts/char_rom_datasoft.vhd delete mode 100644 lib/VGA_ctrl/src/fonts/char_rom_demo_maker_m.vhd delete mode 100644 lib/VGA_ctrl/src/fonts/char_rom_fixedsys_8x15.vhd delete mode 100644 lib/VGA_ctrl/src/fonts/char_rom_fixedsys_8x16.vhd delete mode 100644 lib/VGA_ctrl/src/fonts/char_rom_fixedsys_9x16.vhd delete mode 100644 lib/VGA_ctrl/src/fonts/char_rom_system_16x16.vhd delete mode 100644 lib/VGA_ctrl/src/fonts/char_rom_the_goonies.vhd delete mode 100644 lib/VGA_ctrl/src/fonts/make_rom.bat delete mode 100644 lib/VGA_ctrl/src/tb_vga_frontend.vhd delete mode 100644 lib/VGA_ctrl/src/tb_vga_frontend64.vhd delete mode 100644 lib/VGA_ctrl/src/vga_backend.vhd delete mode 100644 lib/VGA_ctrl/src/vga_frontend.vhd delete mode 100644 lib/VGA_ctrl/src/vga_frontend64.vhd delete mode 100644 lib/VGA_ctrl/src/vga_sync.vhd delete mode 100644 lib/VGA_ctrl/src/vga_timing.vhd delete mode 100644 lib/VGA_ctrl/src/vga_types.vhd delete mode 100644 lib/VGA_ctrl/todo.txt delete mode 100644 lib/ac97_ctrl/sim/tb_ac97_wb.fdo delete mode 100644 lib/ac97_ctrl/sim/tb_ac97_wb.wdo delete mode 100644 lib/ac97_ctrl/sim/tb_ac_in.fdo delete mode 100644 lib/ac97_ctrl/sim/tb_ac_in.wdo delete mode 100644 lib/ac97_ctrl/sim/tb_ac_io.fdo delete mode 100644 lib/ac97_ctrl/sim/tb_ac_io.wdo delete mode 100644 lib/ac97_ctrl/sim/tb_ac_out.fdo delete mode 100644 lib/ac97_ctrl/sim/tb_ac_out.wdo delete mode 100644 lib/ac97_ctrl/src/core/ac97_wb.vhd delete mode 100644 lib/ac97_ctrl/src/core/ac_in.vhd delete mode 100644 lib/ac97_ctrl/src/core/ac_io.vhd delete mode 100644 lib/ac97_ctrl/src/core/ac_out.vhd delete mode 100644 lib/ac97_ctrl/src/tb_ac97_wb.vhd delete mode 100644 lib/ac97_ctrl/src/tb_ac_in.vhd delete mode 100644 lib/ac97_ctrl/src/tb_ac_io.vhd delete mode 100644 lib/ac97_ctrl/src/tb_ac_out.vhd delete mode 100644 lib/ac97_ctrl/todo.txt delete mode 100644 lib/filter/sim/eval_lowpass.m delete mode 100644 lib/filter/sim/lowpass.m delete mode 100644 lib/filter/sim/tb_fir_iterative.fdo delete mode 100644 lib/filter/sim/tb_fir_iterative.wdo delete mode 100644 lib/filter/sim/tb_fir_parallel delete mode 100644 lib/filter/sim/tb_fir_parallel.fdo delete mode 100644 lib/filter/sim/tb_fir_parallel.wdo delete mode 100644 lib/filter/sim/tb_fir_results.m delete mode 100644 lib/filter/sim/tb_fir_semi_parallel.fdo delete mode 100644 lib/filter/sim/tb_fir_semi_parallel.wdo delete mode 100644 lib/filter/sim/tb_fir_stage.fdo delete mode 100644 lib/filter/sim/tb_fir_stage.wdo delete mode 100644 lib/filter/sim/tb_fir_stage_sys.fdo delete mode 100644 lib/filter/sim/tb_fir_stage_sys.wdo delete mode 100644 lib/filter/src/delay_line.vhd delete mode 100644 lib/filter/src/filter_pkg.vhd delete mode 100644 lib/filter/src/fir_iterative.vhd delete mode 100644 lib/filter/src/fir_iterative_pkg.vhd delete mode 100644 lib/filter/src/fir_parallel.vhd delete mode 100644 lib/filter/src/fir_parallel_pkg.vhd delete mode 100644 lib/filter/src/fir_pkg.vhd delete mode 100644 lib/filter/src/fir_semi_parallel.vhd delete mode 100644 lib/filter/src/fir_stage.vhd delete mode 100644 lib/filter/src/fir_stage_pkg.vhd delete mode 100644 lib/filter/src/fir_stage_sys.vhd delete mode 100644 lib/filter/src/tb_fir_iterative.vhd delete mode 100644 lib/filter/src/tb_fir_parallel.vhd delete mode 100644 lib/filter/src/tb_fir_semi_parallel.vhd delete mode 100644 lib/filter/src/tb_fir_stage.vhd delete mode 100644 lib/filter/src/tb_fir_stage_sys.vhd delete mode 100644 lib/fix_std/fix_std.vhd delete mode 100644 lib/fix_std/fix_stdb.vhd delete mode 100644 lib/fixed/fixed_util_pkg.vhd delete mode 100644 lib/fixed_ja/fixed_ja.vhd delete mode 100644 lib/fixed_ja/fixed_ja_body.vhd delete mode 100644 lib/jasm/cg.inc.jsm delete mode 100644 lib/jasm/cregs.inc.jsm delete mode 100644 lib/jasm/delays.inc.jsm delete mode 100644 lib/jasm/lcd.inc.jsm delete mode 100644 lib/jasm/mul8x8.inc.jsm delete mode 100644 lib/jasm/uart.inc.jsm delete mode 100644 lib/jasm/utils.inc.jsm delete mode 100644 lib/misc/async_port_wb.vhd delete mode 100644 lib/misc/async_types.vhd delete mode 100644 lib/misc/bbfifo.vhd delete mode 100644 lib/misc/clockgen_virtex4.vhd delete mode 100644 lib/misc/debounce.vhd delete mode 100644 lib/misc/debounce2.vhd delete mode 100644 lib/misc/dpram_1w1r.vhd delete mode 100644 lib/misc/dpram_1w1r1c_sim.vhd delete mode 100644 lib/misc/dpram_1w1r1c_xil.vhd delete mode 100644 lib/misc/dpram_1w1r2c_sim.vhd delete mode 100644 lib/misc/dpram_1w1r2c_xil.vhd delete mode 100644 lib/misc/dpram_1w1r_dist.vhd delete mode 100644 lib/misc/dpram_1w2r1c_sim.vhd delete mode 100644 lib/misc/dpram_1w2r1c_xil.vhd delete mode 100644 lib/misc/dpram_2w2r.vhd delete mode 100644 lib/misc/dpram_2w2r1c_sim.vhd delete mode 100644 lib/misc/dpram_2w2r1c_xil.vhd delete mode 100644 lib/misc/dpram_2w2r2c_sim.vhd delete mode 100644 lib/misc/dpram_2w2r2c_xil.vhd delete mode 100644 lib/misc/flash_port_wb.vhd delete mode 100644 lib/misc/gpio_wb.vhd delete mode 100644 lib/misc/lcd_port.vhd delete mode 100644 lib/misc/mult_signed.vhd delete mode 100644 lib/misc/oneshot.vhd delete mode 100644 lib/misc/pkg_template.vhd delete mode 100644 lib/misc/ram_sim.vhd delete mode 100644 lib/misc/ram_wb.vhd delete mode 100644 lib/misc/rom_sim.vhd delete mode 100644 lib/misc/rom_wb.vhd delete mode 100644 lib/misc/sim/ModelSim SE .lnk delete mode 100644 lib/misc/sim/tb_bbfifo.fdo delete mode 100644 lib/misc/sim/tb_bbfifo.wdo delete mode 100644 lib/misc/sim/tb_ram_wb.fdo delete mode 100644 lib/misc/sim/tb_ram_wb.wdo delete mode 100644 lib/misc/sim/tb_rom_wb.fdo delete mode 100644 lib/misc/sim/tb_rom_wb.wdo delete mode 100644 lib/misc/singleshot.vhd delete mode 100644 lib/misc/tb_bbfifo.vhd delete mode 100644 lib/misc/tb_ram_wb.vhd delete mode 100644 lib/misc/tb_rom_wb.vhd delete mode 100644 lib/misc/tb_template.vhd delete mode 100644 lib/misc/utils_pkg.vhd delete mode 100644 lib/misc/wire_delay.vhd delete mode 100644 lib/ps2_port/sim/tb_ps2_core.fdo delete mode 100644 lib/ps2_port/sim/tb_ps2_core.wdo delete mode 100644 lib/ps2_port/src/debounce.vhd delete mode 100644 lib/ps2_port/src/ps2_core.vhd delete mode 100644 lib/ps2_port/src/ps2_phy_virtex.vhd delete mode 100644 lib/ps2_port/src/ps2_wb.vhd delete mode 100644 lib/ps2_port/src/tb_ps2_core.vhd delete mode 100644 lib/radio/cordic/eval_cordic.m delete mode 100644 lib/radio/cordic/sim/eval_cordic.m delete mode 100644 lib/radio/cordic/sim/tb_cordic_pipe_top.fdo delete mode 100644 lib/radio/cordic/sim/tb_cordic_pipe_top.wdo delete mode 100644 lib/radio/cordic/sim/tb_cordic_top.fdo delete mode 100644 lib/radio/cordic/sim/tb_cordic_top.wdo delete mode 100644 lib/radio/cordic/sim/tb_results.m delete mode 100644 lib/radio/cordic/src/cordic_pipe_post.vhd delete mode 100644 lib/radio/cordic/src/cordic_pipe_pre.vhd delete mode 100644 lib/radio/cordic/src/cordic_pipe_stage.vhd delete mode 100644 lib/radio/cordic/src/cordic_pipe_top.vhd delete mode 100644 lib/radio/cordic/src/cordic_pkg.vhd delete mode 100644 lib/radio/cordic/src/cordic_rom.vhd delete mode 100644 lib/radio/cordic/src/cordic_stage.vhd delete mode 100644 lib/radio/cordic/src/cordic_stage_post.vhd delete mode 100644 lib/radio/cordic/src/cordic_stage_pre.vhd delete mode 100644 lib/radio/cordic/src/cordic_top.vhd delete mode 100644 lib/radio/cordic/src/tb_cordic_pipe_top.vhd delete mode 100644 lib/radio/cordic/src/tb_cordic_top.vhd delete mode 100644 lib/radio/ddc/sim/tb_ddc.fdo delete mode 100644 lib/radio/ddc/sim/tb_ddc.wdo delete mode 100644 lib/radio/ddc/sim/tb_results.m delete mode 100644 lib/radio/ddc/src/ddc.vhd delete mode 100644 lib/radio/ddc/src/syn_ddc.vhd delete mode 100644 lib/radio/ddc/src/tb_ddc.vhd delete mode 100644 lib/radio/decimator/CIC/sim/tb_cic_c_pipe.fdo delete mode 100644 lib/radio/decimator/CIC/sim/tb_cic_c_pipe.wdo delete mode 100644 lib/radio/decimator/CIC/sim/tb_cic_decim_pipe.fdo delete mode 100644 lib/radio/decimator/CIC/sim/tb_cic_decim_pipe.wdo delete mode 100644 lib/radio/decimator/CIC/sim/tb_cic_i_pipe.fdo delete mode 100644 lib/radio/decimator/CIC/sim/tb_cic_i_pipe.wdo delete mode 100644 lib/radio/decimator/CIC/src/cic_c_pipe.vhd delete mode 100644 lib/radio/decimator/CIC/src/cic_decim_pipe.vhd delete mode 100644 lib/radio/decimator/CIC/src/cic_i_pipe.vhd delete mode 100644 lib/radio/decimator/CIC/src/syn_cic_c_pipe.vhd delete mode 100644 lib/radio/decimator/CIC/src/syn_cic_i_pipe.vhd delete mode 100644 lib/radio/decimator/CIC/src/tb_cic_c_pipe.vhd delete mode 100644 lib/radio/decimator/CIC/src/tb_cic_decim_pipe.vhd delete mode 100644 lib/radio/decimator/CIC/src/tb_cic_i_pipe.vhd delete mode 100644 lib/radio/mix/sim/tb_mix_cpx.fdo delete mode 100644 lib/radio/mix/sim/tb_mix_cpx.wdo delete mode 100644 lib/radio/mix/sim/tb_mix_real.fdo delete mode 100644 lib/radio/mix/sim/tb_mix_real.wdo delete mode 100644 lib/radio/mix/sim/tb_undc_real.fdo delete mode 100644 lib/radio/mix/sim/tb_undc_real.wdo delete mode 100644 lib/radio/mix/src/mix_cpx.vhd delete mode 100644 lib/radio/mix/src/mix_real.vhd delete mode 100644 lib/radio/mix/src/tb_mix_cpx.vhd delete mode 100644 lib/radio/mix/src/tb_mix_real.vhd delete mode 100644 lib/radio/mix/src/tb_undc_real.vhd delete mode 100644 lib/radio/mix/src/undc_real.vhd delete mode 100644 lib/radio/nco/sim/tb_mix_cordic.fdo delete mode 100644 lib/radio/nco/sim/tb_mix_cordic.wdo delete mode 100644 lib/radio/nco/sim/tb_mix_results.m delete mode 100644 lib/radio/nco/sim/tb_nco_cordic.fdo delete mode 100644 lib/radio/nco/sim/tb_nco_cordic.wdo delete mode 100644 lib/radio/nco/sim/tb_nco_lut.fdo delete mode 100644 lib/radio/nco/sim/tb_nco_lut.wdo delete mode 100644 lib/radio/nco/sim/tb_nco_results.m delete mode 100644 lib/radio/nco/src/mix_cordic.vhd delete mode 100644 lib/radio/nco/src/nco.vhd.bak delete mode 100644 lib/radio/nco/src/nco_lut.vhd delete mode 100644 lib/radio/nco/src/nco_lut_dbg.vhd delete mode 100644 lib/radio/nco/src/nco_pkg.vhd delete mode 100644 lib/radio/nco/src/tb_mix_cordic.vhd delete mode 100644 lib/radio/nco/src/tb_nco_cordic.vhd delete mode 100644 lib/radio/nco/src/tb_nco_lut.vhd delete mode 100644 lib/radio/nco/src/wavelut.vhd delete mode 100644 lib/radio/nco/src/waverom_dual.vhd delete mode 100644 lib/rams/dpram_1w1r2c_ra_sim.vhd delete mode 100644 lib/rams/dpram_1w1r2c_ra_xil.vhd delete mode 100644 lib/rams/dpram_1w1r2c_ro_sim.vhd delete mode 100644 lib/rams/dpram_1w1r2c_ro_xil.vhd delete mode 100644 lib/rams/dpram_2w2r2c_ra_sim.vhd delete mode 100644 lib/rams/dpram_2w2r2c_ra_xil.vhd delete mode 100644 lib/rams/dpram_2w2r2c_ro_sim.vhd delete mode 100644 lib/rams/dpram_2w2r2c_ro_xil.vhd delete mode 100644 lib/uart/bbfifo_16x8.vhd delete mode 100644 lib/uart/kcuart_rx.vhd delete mode 100644 lib/uart/kcuart_tx.vhd delete mode 100644 lib/uart/uart_rx.vhd delete mode 100644 lib/uart/uart_tx.vhd delete mode 100644 lib/uart/uart_wb.vhd delete mode 100644 projects/mips_sys/ise101/mips_sys/mips_sys.par delete mode 100644 projects/mips_sys/ise101/mips_sys/mips_sys.prj delete mode 100644 projects/mips_sys/ise101/mips_sys/mips_sys.syr delete mode 100644 projects/mips_sys/ise101/mips_sys/mips_sys.twr delete mode 100644 projects/mips_sys/ise101/mips_sys/mips_sys.ut delete mode 100644 projects/mips_sys/ise101/mips_sys/mips_sys.xst delete mode 100644 projects/mips_sys/ise101/mips_sys/mips_sys_map.mrp delete mode 100644 projects/mips_sys/ise101/mips_sys/mips_sys_vhdl.prj delete mode 100644 projects/mips_sys/ise101/mips_sys/ucf/systest.ssram.ucf delete mode 100644 projects/mips_sys/ise101/mips_sys/ucf/systest.ucf delete mode 100644 projects/mips_sys/ise92/mips_sys/mips_sys.prj delete mode 100644 projects/mips_sys/ise92/mips_sys/mips_sys_vhdl.prj delete mode 100644 projects/mips_sys/ise92/mips_sys/ucf/systest.ucf delete mode 100644 projects/mips_sys/sim/tb_mips_sys.fdo delete mode 100644 projects/mips_sys/sim/tb_mips_sys.wdo delete mode 100644 projects/mips_sys/sim/tb_mips_sys_emac.fdo delete mode 100644 projects/mips_sys/sim/tb_mips_sys_emac.wdo delete mode 100644 projects/mips_sys/src/.directory_history delete mode 100644 projects/mips_sys/src/async_defs_sim.vhd delete mode 100644 projects/mips_sys/src/bootloader.ROM.vhd delete mode 100644 projects/mips_sys/src/bootloader.ROM_ld.vhd delete mode 100644 projects/mips_sys/src/bootloader.dis delete mode 100644 projects/mips_sys/src/clockgen_virtex4.vhd delete mode 100644 projects/mips_sys/src/mips_sys.vhd delete mode 100644 projects/mips_sys/src/mips_sys_sim.vhd delete mode 100644 projects/mips_sys/src/ram_ld.vhd delete mode 100644 projects/mips_sys/src/ram_sim.vhd delete mode 100644 projects/mips_sys/src/sdram_config.vhd delete mode 100644 projects/mips_sys/src/sdram_config_sim.vhd delete mode 100644 projects/mips_sys/src/sys_types.vhd delete mode 100644 projects/mips_sys/src/tb_mips_sys.vhd delete mode 100644 projects/mips_sys/tools/insrom.rb delete mode 100644 projects/mips_sys/tools/irom.vhd.tpl delete mode 100644 projects/mips_sys/tools/irom_ld.vhd.tpl delete mode 100644 projects/mips_sys/tools/make delete mode 100644 projects/mips_sys/tools/rom.tcl.tpl delete mode 100644 projects/mips_sys/tools/src/flashgen.c delete mode 100644 projects/mips_sys/tools/src/ramgen.c delete mode 100644 projects/mips_sys/tools/src/romgen.c diff --git a/Common/sim/ModelSim SE .lnk b/Common/sim/ModelSim SE .lnk deleted file mode 100644 index ecadd026618ef9dc683b411377dc4b08753d4bac..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 1441 zcmds1YeLW4jesvk-rQE8%Gq#se#^M0FO7rOlES7)5}ocCOwbKdj4@5%sZ z^f6q4ab-pEd2S8V1WLPnP_2OAk%^^D$bIM6NV1~WHJxXqfAH+Bsn{IzXATB z$J-S0`Ayz-wrEzfKQa5%4bg>P?IJ`RKkIwZuAC=@UJqGFFi)>{w<|N-tR9#SL%uS)2~vs1s~4IHuCrVjM6TWrqw5bv0g^8FI3{j(DW&{seZ@jNdb}{w~N#q<% zDF`1T8fVd89Yt+C((G&Xwx~4@S9HH=+`74RU^Yho=;+l;ZMBc@B&N?KoP2=wL!R#U QfAfo1y^8qTD1%YdufjzO<^TWy diff --git a/Common/sim/compile_fixed.do b/Common/sim/compile_fixed.do deleted file mode 100644 index 0c17180..0000000 --- a/Common/sim/compile_fixed.do +++ /dev/null @@ -1,13 +0,0 @@ -# -# Compile script for Modeltech -# -vlib ieee_proposed -vmap ieee_proposedx ieee_proposed -vcom -work ieee_proposed -93 "../../lib/fixed/modelsim/standard_additions_c.vhdl" -vcom -work ieee_proposed -93 "../../lib/fixed/modelsim/env_c.vhdl" -vcom -work ieee_proposed -93 "../../lib/fixed/modelsim/standard_textio_additions_c.vhdl" -vcom -work ieee_proposed -93 "../../lib/fixed/modelsim/std_logic_1164_additions.vhdl" -vcom -work ieee_proposed -93 "../../lib/fixed/modelsim/numeric_std_additions.vhdl" -vcom -work ieee_proposed -93 "../../lib/fixed/modelsim/numeric_std_unsigned_c.vhdl" -vcom -work ieee_proposed -93 "../../lib/fixed/modelsim/math_utility_pkg_c.vhdl" -vcom -work ieee_proposed -93 "../../lib/fixed/modelsim/fixed_pkg_c.vhdl" diff --git a/Common/sim/compile_simprim.do b/Common/sim/compile_simprim.do deleted file mode 100644 index 9f7ba37..0000000 --- a/Common/sim/compile_simprim.do +++ /dev/null @@ -1,8 +0,0 @@ -vlib simprim - -set XILINX $env(XILINX) - -vcom -93 -work simprim $XILINX/vhdl/src/simprims/simprim_Vcomponents_mti.vhd -vcom -93 -work simprim $XILINX/vhdl/src/simprims/simprim_Vpackage_mti.vhd -vcom -93 -work simprim $XILINX/vhdl/src/simprims/simprim_SMODEL_mti.vhd -vcom -93 -work simprim $XILINX/vhdl/src/simprims/simprim_VITAL_mti.vhd diff --git a/Common/sim/compile_unisim.do b/Common/sim/compile_unisim.do deleted file mode 100644 index 4aec199..0000000 --- a/Common/sim/compile_unisim.do +++ /dev/null @@ -1,8 +0,0 @@ -vlib unisim - -set XILINX $env(XILINX) - -vcom -93 -work unisim $XILINX/vhdl/src/unisims/unisim_vpkg.vhd -vcom -93 -work unisim $XILINX/vhdl/src/unisims/unisim_vcomp.vhd -vcom -93 -work unisim $XILINX/vhdl/src/unisims/unisim_smodel.vhd -vcom -93 -work unisim $XILINX/vhdl/src/unisims/unisim_vital.vhd diff --git a/Common/ucf/ml402.ucf b/Common/ucf/ml402.ucf deleted file mode 100644 index 318e778..0000000 --- a/Common/ucf/ml402.ucf +++ /dev/null @@ -1,675 +0,0 @@ -# -# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -# SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -# XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -# AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -# OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -# IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -# AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -# FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -# WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -# IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -# REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -# INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE. -# -# (c) Copyright 2005 Xilinx, Inc. -# All rights reserved. -# - -# Bus clock nets -NET "sys_clk" TNM_NET = "sys_clk"; -NET "tft_clk" TNM_NET = "tft_clk"; -NET sys_clk_in TNM_NET = "sys_clk_in"; -TIMESPEC "TSSYSCLK" = PERIOD "sys_clk_in" 9.9 ns HIGH 50 %; - -NET sys_clk_in LOC = AE14; -NET sys_clk_in IOSTANDARD = LVCMOS33; -NET sys_rst_in LOC = D6; -NET sys_rst_in PULLUP; -NET sys_rst_in TIG; - -NET uart_RX LOC = W2; -NET uart_RX IOSTANDARD = LVCMOS33; -NET uart_RX TIG; -NET uart_TX LOC = W1; -NET uart_TX IOSTANDARD = LVCMOS33; -NET uart_TX TIG; - -NET ext_irq TIG; - -# Reset timing ignore - treat as async paths -NET sys_rst TIG; -NET opb_v20_0_OPB_Rst TIG; -NET lmb_v10_1_OPB_Rst TIG; -NET lmb_v10_0_OPB_Rst TIG; -NET opb_v20_0_Debug_SYS_Rst TIG; -NET Debug_Rst TIG; -NET plb_v34_0_PLB_Rst TIG; -NET dcm_locked TIG; - -# Locate DCM/BUFG - Tools can probably figure them out automatically -# but just LOC them down to be safe -INST dcm_0/dcm_0/DCM_ADV_INST LOC = DCM_ADV_X0Y2; -INST dcm_1/dcm_1/DCM_ADV_INST LOC = DCM_ADV_X0Y4; -INST dcm_2/dcm_2/DCM_ADV_INST LOC = DCM_ADV_X0Y1; - -INST dcm_0/dcm_0/CLK0_BUFG_INST LOC = BUFGCTRL_X0Y0; -INST dcm_0/dcm_0/CLK90_BUFG_INST LOC = BUFGCTRL_X0Y1; -INST dcm_0/dcm_0/CLKDV_BUFG_INST LOC = BUFGCTRL_X0Y2; - -INST dcm_1/dcm_1/CLK0_BUFG_INST LOC = BUFGCTRL_X0Y31; -INST dcm_1/dcm_1/CLK90_BUFG_INST LOC = BUFGCTRL_X0Y30; - -//////////////////////////////////////////////////////////////////////////// -// Buttons, LEDs, and DIP Switches -//////////////////////////////////////////////////////////////////////////// - -# GPLED 0-3 -NET gpio<0> LOC = G5; #GPLED0 -NET gpio<1> LOC = G6; #GPLED1 -NET gpio<2> LOC = A11; #GPLED2 -NET gpio<3> LOC = A12; #GPLED3 -# North-East-South-West-Center LEDs -NET gpio<4> LOC = C6; # C LED -NET gpio<5> LOC = F9; # W LED -NET gpio<6> LOC = A5; # S LED -NET gpio<7> LOC = E10; # E LED -NET gpio<8> LOC = E2; # N LED -# North-East-South-West-Center Buttons -NET gpio<9> LOC = B6; # C Button -NET gpio<10> LOC = E9; # W Button -NET gpio<11> LOC = A6; # S Button -NET gpio<12> LOC = F10; # E Button -NET gpio<13> LOC = E7; # N Button -# Dip Switches 1-8 -NET gpio<14> LOC = U24; # DIP SW 8 -NET gpio<15> LOC = U25; # DIP SW 7 -NET gpio<16> LOC = V23; # DIP SW 6 -NET gpio<17> LOC = U23; # DIP SW 5 -NET gpio<18> LOC = U26; # DIP SW 4 -NET gpio<19> LOC = T26; # DIP SW 3 -NET gpio<20> LOC = R19; # DIP SW 2 -NET gpio<21> LOC = R20; # DIP SW 1 -NET gpio<14> IOSTANDARD = LVCMOS33; -NET gpio<15> IOSTANDARD = LVCMOS33; -NET gpio<16> IOSTANDARD = LVCMOS33; -NET gpio<17> IOSTANDARD = LVCMOS33; -NET gpio<18> IOSTANDARD = LVCMOS33; -NET gpio<19> IOSTANDARD = LVCMOS33; -NET gpio<20> IOSTANDARD = LVCMOS33; -NET gpio<21> IOSTANDARD = LVCMOS33; -#SMA Connectors -NET gpio<22> LOC = C12; # SMA_IN_N -NET gpio<23> LOC = C13; # SMA_IN_P -NET gpio<24> LOC = D7; # SMA_OUT_N -NET gpio<25> LOC = D8; # SMA_OUT_P -NET gpio<26> LOC = AD12;# USERCLK -NET gpio<26> IOSTANDARD = LVCMOS33; - -NET "gpio<*>" PULLDOWN; -NET "gpio<*>" TIG; -NET "gpio<*>" SLEW = SLOW; -NET "gpio<*>" DRIVE = 2; - -NET "gpio<22>" SLEW = FAST; -NET "gpio<22>" DRIVE = 12; -NET "gpio<23>" SLEW = FAST; -NET "gpio<23>" DRIVE = 12; -NET "gpio<24>" SLEW = FAST; -NET "gpio<24>" DRIVE = 12; -NET "gpio<25>" SLEW = FAST; -NET "gpio<25>" DRIVE = 12; - -NET "gpio2_d_out<*>" TIG; -NET "gpio2_t_out<*>" TIG; -NET "gpio2_in<*>" TIG; - -#------------------------------------------------------------------------------ -# IO Pad Location Constraints / Properties for PS/2 Ports -#------------------------------------------------------------------------------ - -#Keyboard -NET ps2_keyb_clk LOC = D2; -NET ps2_keyb_clk SLEW = SLOW; -NET ps2_keyb_clk DRIVE = 2; -NET ps2_keyb_clk TIG; -NET ps2_keyb_data LOC = G9; -NET ps2_keyb_data SLEW = SLOW; -NET ps2_keyb_data DRIVE = 2; -NET ps2_keyb_data TIG; - -#Mouse -NET ps2_mouse_clk LOC = B14; -NET ps2_mouse_clk SLEW = SLOW; -NET ps2_mouse_clk DRIVE = 2; -NET ps2_mouse_clk TIG; -NET ps2_mouse_data LOC = C14; -NET ps2_mouse_data SLEW = SLOW; -NET ps2_mouse_data DRIVE = 2; -NET ps2_mouse_data TIG; - -#------------------------------------------------------------------------------ -# IO Pad Location Constraints / Properties for IIC Controller -#------------------------------------------------------------------------------ - -NET iic_scl LOC = A17; -NET iic_sda LOC = B17; -NET iic_scl SLEW = SLOW; -NET iic_scl DRIVE = 6; -NET iic_scl TIG; -NET iic_sda SLEW = SLOW; -NET iic_sda DRIVE = 6; -NET iic_sda TIG; - -#------------------------------------------------------------------------------ -# IO Pad Location Constraints / Properties for AC97 Sound Controller -#------------------------------------------------------------------------------ - -NET ac97_bit_clk LOC = AE10; -NET ac97_bit_clk IOSTANDARD = LVCMOS33; -NET ac97_bit_clk PERIOD = 80; -NET ac97_sdata_in LOC = AD16; -NET ac97_sdata_in IOSTANDARD = LVCMOS33; -NET ac97_reset_n LOC = AD10; -NET ac97_reset_n IOSTANDARD = LVCMOS33; -NET ac97_reset_n TIG; -NET ac97_sdata_out LOC = C8; -NET ac97_sync LOC = D9; - -#------------------------------------------------------------------------------ -# IO Pad Location Constraints / Properties for System ACE MPU / USB -#------------------------------------------------------------------------------ - -NET sysace_clk_in LOC = AF11; -NET sysace_clk_in IOSTANDARD = LVCMOS33; -NET sysace_clk_in TNM_NET = "sysace_clk_in"; -# Leave 1 ns margin -TIMESPEC "TSSYSACE" = PERIOD "sysace_clk_in" 29 ns; - -NET sace_usb_a<0> LOC = U22; -NET sace_usb_a<1> LOC = Y10; -NET sace_usb_a<2> LOC = AA10; -NET sace_usb_a<3> LOC = AC7; -NET sace_usb_a<4> LOC = Y7; -NET sace_usb_a<5> LOC = AA9; -NET sace_usb_a<6> LOC = Y9; -NET sace_usb_a<*> IOSTANDARD = LVCMOS33; -NET sace_usb_a<*> SLEW = FAST; -NET sace_usb_a<*> DRIVE = 8; -NET sace_mpce LOC = AD5; -NET sace_mpce IOSTANDARD = LVCMOS33; -NET sace_mpce SLEW = FAST; -NET sace_mpce DRIVE = 8; -NET sace_usb_d<0> LOC = AB7; -NET sace_usb_d<1> LOC = AC9; -NET sace_usb_d<2> LOC = AB9; -NET sace_usb_d<3> LOC = AE6; -NET sace_usb_d<4> LOC = AD6; -NET sace_usb_d<5> LOC = AF9; -NET sace_usb_d<6> LOC = AE9; -NET sace_usb_d<7> LOC = AD8; -NET sace_usb_d<8> LOC = AC8; -NET sace_usb_d<9> LOC = AF4; -NET sace_usb_d<10> LOC = AE4; -NET sace_usb_d<11> LOC = AD3; -NET sace_usb_d<12> LOC = AC3; -NET sace_usb_d<13> LOC = AF6; -NET sace_usb_d<14> LOC = AF5; -NET sace_usb_d<15> LOC = AA7; -NET sace_usb_d<*> IOSTANDARD = LVCMOS33; -NET sace_usb_d<*> SLEW = FAST; -NET sace_usb_d<*> DRIVE = 8; -NET sace_usb_d<*> PULLDOWN; -NET sace_usb_oen LOC = AA8; -NET sace_usb_oen IOSTANDARD = LVCMOS33; -NET sace_usb_oen SLEW = FAST; -NET sace_usb_oen DRIVE = 8; -NET sace_usb_wen LOC = Y8; -NET sace_usb_wen IOSTANDARD = LVCMOS33; -NET sace_usb_wen SLEW = FAST; -NET sace_usb_wen DRIVE = 8; -NET sysace_mpirq LOC = AD4; -NET sysace_mpirq IOSTANDARD = LVCMOS33; -NET sysace_mpirq TIG; -NET sysace_mpirq PULLDOWN; - -NET usb_csn LOC = AF10; -NET usb_csn IOSTANDARD = LVCMOS33; -NET usb_csn SLEW = FAST; -NET usb_csn DRIVE = 8; -NET usb_hpi_reset_n LOC = A7; -NET usb_hpi_reset_n IOSTANDARD = LVCMOS25; -NET usb_hpi_reset_n TIG; -NET usb_hpi_int LOC = V5; -NET usb_hpi_int IOSTANDARD = LVCMOS33; -NET usb_hpi_int TIG; -NET usb_hpi_int PULLDOWN; - -#------------------------------------------------------------------------------ -# IO Pad Location Constraints / Properties for DDR Controllers -#------------------------------------------------------------------------------ - -NET ddr_ad<0> LOC = C26; # DDR_A0 -NET ddr_ad<1> LOC = E17; # DDR_A1 -NET ddr_ad<2> LOC = D18; # DDR_A2 -NET ddr_ad<3> LOC = C19; # DDR_A3 -NET ddr_ad<4> LOC = F17; # DDR_A4 -NET ddr_ad<5> LOC = B18; # DDR_A5 -NET ddr_ad<6> LOC = B20; # DDR_A6 -NET ddr_ad<7> LOC = C20; # DDR_A7 -NET ddr_ad<8> LOC = D20; # DDR_A8 -NET ddr_ad<9> LOC = C21; # DDR_A9 -NET ddr_ad<10> LOC = A18; # DDR_A10 -NET ddr_ad<11> LOC = B21; # DDR_A11 -NET ddr_ad<12> LOC = A24; # DDR_A12 -NET ddr_ba<0> LOC = B12; # DDR_BA0 -NET ddr_ba<1> LOC = A16; # DDR_BA1 -NET ddr_casb LOC = F23; # DDR_CAS_N -NET ddr_cke LOC = G22; # DDR_CKE -NET ddr_csb LOC = G21; # DDR_CS_N -NET ddr_rasb LOC = F24; # DDR_RAS_N -NET ddr_web LOC = A23; # DDR_WE_N - -NET ddr_clk LOC = A10; # DDR_CK1_P -NET ddr_clk_fb LOC = B13; # DDR_CK1_P (FEEDBACK) -NET ddr_clkb LOC = B10; # DDR_CK1_N - -NET ddr_dm<0> LOC = G19; # DDR_DM0 -NET ddr_dm<1> LOC = G24; # DDR_DM1 -NET ddr_dm<2> LOC = G20; # DDR_DM2 -NET ddr_dm<3> LOC = C22; # DDR_DM3 - -NET ddr_dqs<0> LOC = D25; # DDR_DQS0 -NET ddr_dqs<1> LOC = G18; # DDR_DQS1 -NET ddr_dqs<2> LOC = G17; # DDR_DQS2 -NET ddr_dqs<3> LOC = D26; # DDR_DQS3 - -NET ddr_dq<0> LOC = H20; # DDR_D0 -NET ddr_dq<1> LOC = E23; # DDR_D1 -NET ddr_dq<2> LOC = H26; # DDR_D2 -NET ddr_dq<3> LOC = H22; # DDR_D3 -NET ddr_dq<4> LOC = E25; # DDR_D4 -NET ddr_dq<5> LOC = E26; # DDR_D5 -NET ddr_dq<6> LOC = F26; # DDR_D6 -NET ddr_dq<7> LOC = E24; # DDR_D7 -NET ddr_dq<8> LOC = E20; # DDR_D8 -NET ddr_dq<9> LOC = A22; # DDR_D9 -NET ddr_dq<10> LOC = C23; # DDR_D10 -NET ddr_dq<11> LOC = C24; # DDR_D11 -NET ddr_dq<12> LOC = A20; # DDR_D12 -NET ddr_dq<13> LOC = A21; # DDR_D13 -NET ddr_dq<14> LOC = D24; # DDR_D14 -NET ddr_dq<15> LOC = E18; # DDR_D15 -NET ddr_dq<16> LOC = F18; # DDR_D16 -NET ddr_dq<17> LOC = A19; # DDR_D17 -NET ddr_dq<18> LOC = F19; # DDR_D18 -NET ddr_dq<19> LOC = B23; # DDR_D19 -NET ddr_dq<20> LOC = E21; # DDR_D20 -NET ddr_dq<21> LOC = D22; # DDR_D21 -NET ddr_dq<22> LOC = D23; # DDR_D22 -NET ddr_dq<23> LOC = B24; # DDR_D23 -NET ddr_dq<24> LOC = E22; # DDR_D24 -NET ddr_dq<25> LOC = F20; # DDR_D25 -NET ddr_dq<26> LOC = H23; # DDR_D26 -NET ddr_dq<27> LOC = G25; # DDR_D27 -NET ddr_dq<28> LOC = G26; # DDR_D28 -NET ddr_dq<29> LOC = H25; # DDR_D29 -NET ddr_dq<30> LOC = H24; # DDR_D30 -NET ddr_dq<31> LOC = H21; # DDR_D31 - -NET ddr_ad<*> IOSTANDARD = SSTL2_I; -NET ddr_ba<*> IOSTANDARD = SSTL2_I; -NET ddr_casb IOSTANDARD = SSTL2_I; -NET ddr_cke IOSTANDARD = SSTL2_I; -NET ddr_clk IOSTANDARD = SSTL2_I; -NET ddr_clk_fb IOSTANDARD = LVCMOS25; -NET ddr_clkb IOSTANDARD = SSTL2_I; -NET ddr_casb IOSTANDARD = SSTL2_I; -NET ddr_csb IOSTANDARD = SSTL2_I; -NET ddr_rasb IOSTANDARD = SSTL2_I; -NET ddr_web IOSTANDARD = SSTL2_I; - -NET ddr_dqs<*> IOSTANDARD = SSTL2_II; -NET ddr_dm<*> IOSTANDARD = SSTL2_II; -NET ddr_dq<*> IOSTANDARD = SSTL2_II; - -// Timing Constraint for DDR Feedback Clock -NET "ddr_clk_fb" TNM_NET = "ddr_clk_fb"; -TIMESPEC "TSDDR_FB" = PERIOD "ddr_clk_fb" 9.9 ns; - -#------------------------------------------------------------------------------ -# IO Pad Location Constraints / Properties for TFT VGA LCD Controller -#------------------------------------------------------------------------------ - -NET tft_lcd_b<0> LOC = L26; # VGA_B2 -NET tft_lcd_b<0> IOSTANDARD = LVCMOS33; -NET tft_lcd_b<1> LOC = C5; # VGA_B3 -NET tft_lcd_b<2> LOC = C7; # VGA_B4 -NET tft_lcd_b<3> LOC = B7; # VGA_B5 -NET tft_lcd_b<4> LOC = G8; # VGA_B6 -NET tft_lcd_b<5> LOC = F8; # VGA_B7 -NET tft_lcd_b<*> SLEW = FAST; -NET tft_lcd_b<*> DRIVE = 8; - -NET tft_lcd_clk LOC = AF8; -NET tft_lcd_clk IOSTANDARD = LVDCI_33; -NET tft_lcd_clk SLEW = FAST; -NET tft_lcd_clk DRIVE = 8; - -NET tft_lcd_g<0> LOC = M20; # VGA_G2 -NET tft_lcd_g<0> IOSTANDARD = LVCMOS33; -NET tft_lcd_g<1> LOC = E4; # VGA_G3 -NET tft_lcd_g<2> LOC = D3; # VGA_G4 -NET tft_lcd_g<3> LOC = H7; # VGA_G5 -NET tft_lcd_g<4> LOC = H8; # VGA_G6 -NET tft_lcd_g<5> LOC = C1; # VGA_G7 -NET tft_lcd_g<*> SLEW = FAST; -NET tft_lcd_g<*> DRIVE = 8; - -NET tft_lcd_hsync LOC = C10; -NET tft_lcd_hsync SLEW = FAST; -NET tft_lcd_hsync DRIVE = 8; - -NET tft_lcd_r<0> LOC = N25; #VGA_R2 -NET tft_lcd_r<0> IOSTANDARD = LVCMOS33; -NET tft_lcd_r<1> LOC = C2; #VGA_R3 -NET tft_lcd_r<2> LOC = G7; #VGA_R4 -NET tft_lcd_r<3> LOC = F7; #VGA_R5 -NET tft_lcd_r<4> LOC = E5; #VGA_R6 -NET tft_lcd_r<5> LOC = E6; #VGA_R7 -NET tft_lcd_r<*> SLEW = FAST; -NET tft_lcd_r<*> DRIVE = 8; - -NET tft_lcd_vsync LOC = A8; -NET tft_lcd_vsync SLEW = FAST; -NET tft_lcd_vsync DRIVE = 8; - -TIMESPEC "TSPLB_TFT" = FROM "sys_clk" TO "tft_clk" TIG; -TIMESPEC "TSTFT_PLB" = FROM "tft_clk" TO "sys_clk" TIG; - -//////////////////////////////////////////////////////////////////////////// -// Misc Board Signals -//////////////////////////////////////////////////////////////////////////// - -NET plb_error LOC = L24; -NET plb_error IOSTANDARD = LVCMOS33; -NET plb_error TIG; -NET opb_error LOC = V6; -NET opb_error IOSTANDARD = LVCMOS33; -NET opb_error TIG; - -#------------------------------------------------------------------------------ -# IO Pad Location Constraints / Properties for Ethernet -#------------------------------------------------------------------------------ - -NET phy_col LOC = E3; -NET phy_crs LOC = D5; -NET phy_dv LOC = A9; -NET phy_rx_clk LOC = B15; -NET phy_rx_data<3> LOC = C4; -NET phy_rx_data<2> LOC = D4; -NET phy_rx_data<1> LOC = E1; -NET phy_rx_data<0> LOC = F1; - -NET phy_rx_er LOC = B9; -NET phy_tx_clk LOC = C15; -NET phy_mii_clk LOC = D1; -NET phy_mii_int_n LOC = H4; -NET phy_rst_n LOC = D10; -NET phy_tx_data<3> LOC = G1; -NET phy_tx_data<2> LOC = H3; -NET phy_tx_data<1> LOC = H2; -NET phy_tx_data<0> LOC = H1; -NET phy_tx_en LOC = F4; -NET phy_tx_er LOC = F3; -NET phy_mii_data LOC = G4; - -NET phy_mii_int_n PULLUP; - -NET phy_mii_int_n TIG; -NET phy_rst_n TIG; - -# Timing Constraints (these are recommended in documentation and -# are unaltered except for the TIG) -NET "phy_rx_clk" TNM_NET = "RXCLK_GRP"; -NET "phy_tx_clk" TNM_NET = "TXCLK_GRP"; -TIMESPEC "TSTXOUT" = FROM "TXCLK_GRP" TO "PADS" 10 ns; -TIMESPEC "TSRXIN" = FROM "PADS" TO "RXCLK_GRP" 6 ns; - -NET "phy_tx_clk" MAXSKEW= 1.0 ns; -NET "phy_rx_clk" MAXSKEW= 1.0 ns; -NET "phy_rx_clk" PERIOD = 40 ns HIGH 14 ns; -NET "phy_tx_clk" PERIOD = 40 ns HIGH 14 ns; - -NET "phy_rx_data<3>" IOBDELAY=NONE; -NET "phy_rx_data<2>" IOBDELAY=NONE; -NET "phy_rx_data<1>" IOBDELAY=NONE; -NET "phy_rx_data<0>" IOBDELAY=NONE; -NET "phy_dv" IOBDELAY=NONE; -NET "phy_rx_er" IOBDELAY=NONE; -NET "phy_crs" IOBDELAY=NONE; -NET "phy_col" IOBDELAY=NONE; - -# Workaround to help meet "phy_rx_clk MAXSKEW= 1.0 ns" constraint -INST "opb_ethernet_0/opb_ethernet_0/RX_FF_I0" IOB=FALSE; -INST "opb_ethernet_0/opb_ethernet_0/RX_FF_I1" IOB=FALSE; -INST "opb_ethernet_0/opb_ethernet_0/RX_FF_I2" IOB=FALSE; -INST "opb_ethernet_0/opb_ethernet_0/RX_FF_I3" IOB=FALSE; -INST "opb_ethernet_0/opb_ethernet_0/DVD_FF" IOB=FALSE; -INST "opb_ethernet_0/opb_ethernet_0/RER_FF" IOB=FALSE; - -# Timing ignores (to specify unconstrained paths) -TIMESPEC "TS_PHYTX_OPB" = FROM "TXCLK_GRP" TO "sys_clk" TIG; -TIMESPEC "TS_OPB_PHYTX" = FROM "sys_clk" TO "TXCLK_GRP" TIG; -TIMESPEC "TS_PHYRX_OPB" = FROM "RXCLK_GRP" TO "sys_clk" TIG; -TIMESPEC "TS_OPB_PHYRX" = FROM "sys_clk" TO "RXCLK_GRP" TIG; - -#------------------------------------------------------------------------------ -# IO Pad Location Constraints / Properties for SRAM/FLASH -#------------------------------------------------------------------------------ - -NET sram_clk LOC = AF7; -NET sram_clk_fb LOC = AD17; -NET flash_a23 LOC = T21; -NET sram_flash_addr<22> LOC = U20; -NET sram_flash_addr<21> LOC = T19; -NET sram_flash_addr<20> LOC = AC5; -NET sram_flash_addr<19> LOC = AB5; -NET sram_flash_addr<18> LOC = AC4; -NET sram_flash_addr<17> LOC = AB4; - -NET sram_flash_addr<16> LOC = AB3; -NET sram_flash_addr<15> LOC = AA4; -NET sram_flash_addr<14> LOC = AA3; -NET sram_flash_addr<13> LOC = W5; -NET sram_flash_addr<12> LOC = W6; -NET sram_flash_addr<11> LOC = W3; -NET sram_flash_addr<10> LOC = AF3; -NET sram_flash_addr<9> LOC = AE3; -NET sram_flash_addr<8> LOC = AD2; -NET sram_flash_addr<7> LOC = AD1; -NET sram_flash_addr<6> LOC = AC2; -NET sram_flash_addr<5> LOC = AC1; -NET sram_flash_addr<4> LOC = AB2; -NET sram_flash_addr<3> LOC = AB1; -NET sram_flash_addr<2> LOC = AA1; -NET sram_flash_addr<1> LOC = Y2; -NET sram_flash_addr<0> LOC = Y1; -NET sram_flash_data<31> LOC = F14; -NET sram_flash_data<30> LOC = F13; -NET sram_flash_data<29> LOC = F12; -NET sram_flash_data<28> LOC = F11; -NET sram_flash_data<27> LOC = F16; -NET sram_flash_data<26> LOC = F15; -NET sram_flash_data<25> LOC = D14; -NET sram_flash_data<24> LOC = D13; -NET sram_flash_data<23> LOC = D15; -NET sram_flash_data<22> LOC = E14; -NET sram_flash_data<21> LOC = C11; -NET sram_flash_data<20> LOC = D11; -NET sram_flash_data<19> LOC = D16; -NET sram_flash_data<18> LOC = C16; -NET sram_flash_data<17> LOC = E13; -NET sram_flash_data<16> LOC = D12; -NET sram_flash_data<15> LOC = AA14; -NET sram_flash_data<14> LOC = AB14; -NET sram_flash_data<13> LOC = AC12; -NET sram_flash_data<12> LOC = AC11; -NET sram_flash_data<11> LOC = AA16; -NET sram_flash_data<10> LOC = AA15; -NET sram_flash_data<9> LOC = AB13; -NET sram_flash_data<8> LOC = AA13; -NET sram_flash_data<7> LOC = AC14; -NET sram_flash_data<6> LOC = AD14; -NET sram_flash_data<5> LOC = AA12; -NET sram_flash_data<4> LOC = AA11; -NET sram_flash_data<3> LOC = AC16; -NET sram_flash_data<2> LOC = AC15; -NET sram_flash_data<1> LOC = AC13; -NET sram_flash_data<0> LOC = AD13; -NET sram_cen LOC = V7; -NET sram_flash_oe_n LOC = AC6; -NET sram_flash_we_n LOC = AB6; -NET sram_bw<3> LOC = Y3; #Y4; -NET sram_bw<2> LOC = Y4; #Y3; -NET sram_bw<1> LOC = Y5; #Y6; -NET sram_bw<0> LOC = Y6; #Y5; -NET flash_ce LOC = W7; -NET sram_adv_ld_n LOC = W4; -NET sram_mode LOC = V26; - -NET sram_clk IOSTANDARD = LVCMOS33; -NET sram_clk DRIVE = 16; -NET sram_clk SLEW = FAST; -NET sram_clk_fb IOSTANDARD = LVCMOS33; - -NET flash_a23 IOSTANDARD = LVDCI_33; -NET flash_a23 SLEW = FAST; -NET flash_a23 DRIVE = 8; - -NET sram_mode IOSTANDARD = LVDCI_33; -NET sram_mode SLEW = FAST; -NET sram_mode DRIVE = 8; - -NET sram_flash_addr<*> IOSTANDARD = LVDCI_33; -NET sram_flash_addr<*> SLEW = FAST; -NET sram_flash_addr<*> DRIVE = 8; - -NET sram_flash_data<*> IOSTANDARD = LVCMOS33; -NET sram_flash_data<*> DRIVE = 12; -NET sram_flash_data<*> SLEW = FAST; -NET sram_flash_data<*> PULLDOWN; - -NET sram_flash_oe_n IOSTANDARD = LVDCI_33; -NET sram_flash_oe_n SLEW = FAST; -NET sram_flash_oe_n DRIVE = 8; - -NET sram_flash_we_n IOSTANDARD = LVDCI_33; -NET sram_flash_we_n SLEW = FAST; -NET sram_flash_we_n DRIVE = 8; - -NET sram_bw<*> IOSTANDARD = LVDCI_33; -NET sram_bw<*> SLEW = FAST; -NET sram_bw<*> DRIVE = 8; - -NET flash_ce IOSTANDARD = LVDCI_33; -NET flash_ce SLEW = FAST; -NET flash_ce DRIVE = 8; - -NET sram_cen IOSTANDARD = LVDCI_33; -NET sram_cen SLEW = FAST; -NET sram_cen DRIVE = 8; - -NET sram_adv_ld_n IOSTANDARD = LVDCI_33; -NET sram_adv_ld_n SLEW = FAST; -NET sram_adv_ld_n DRIVE = 8; - -#------------------------------------------------------------------------------ -# IO Pad Location Constraints / Properties for Expansion Header GPIO -#------------------------------------------------------------------------------ - -NET gpio_exp_hdr1<31> LOC = AF24; # HDR1_64 -NET gpio_exp_hdr1<30> LOC = AE24; # HDR1_62 -NET gpio_exp_hdr1<29> LOC = AD22; # HDR1_8 -NET gpio_exp_hdr1<28> LOC = AB21; # HDR1_58 -NET gpio_exp_hdr1<27> LOC = W20; # HDR1_44 -NET gpio_exp_hdr1<26> LOC = W21; # HDR1_48 -NET gpio_exp_hdr1<25> LOC = AB22; # HDR1_14 -NET gpio_exp_hdr1<24> LOC = AD25; # HDR1_20 -NET gpio_exp_hdr1<23> LOC = W22; # HDR1_46 -NET gpio_exp_hdr1<22> LOC = V21; # HDR1_56 -NET gpio_exp_hdr1<21> LOC = V22; # HDR1_54 -NET gpio_exp_hdr1<20> LOC = AC22; # HDR1_16 -NET gpio_exp_hdr1<19> LOC = AD26; # HDR1_18 -NET gpio_exp_hdr1<18> LOC = AC26; # HDR1_34 -NET gpio_exp_hdr1<17> LOC = AD23; # HDR1_6 -NET gpio_exp_hdr1<16> LOC = AB25; # HDR1_30 -NET gpio_exp_hdr1<15> LOC = AC23; # HDR1_4 -NET gpio_exp_hdr1<14> LOC = AB26; # HDR1_24 -NET gpio_exp_hdr1<13> LOC = AC21; # HDR1_60 -NET gpio_exp_hdr1<12> LOC = AA23; # HDR1_10 -NET gpio_exp_hdr1<11> LOC = AA26; # HDR1_22 -NET gpio_exp_hdr1<10> LOC = Y25; # HDR1_40 -NET gpio_exp_hdr1<9> LOC = Y26; # HDR1_38 -NET gpio_exp_hdr1<8> LOC = W26; # HDR1_50 -NET gpio_exp_hdr1<7> LOC = AB23; # HDR1_12 -NET gpio_exp_hdr1<6> LOC = Y24; # HDR1_26 -NET gpio_exp_hdr1<5> LOC = AB24; # HDR1_32 -NET gpio_exp_hdr1<4> LOC = W25; # HDR1_52 -NET gpio_exp_hdr1<3> LOC = AC24; # HDR1_2 -NET gpio_exp_hdr1<2> LOC = AC25; # HDR1_36 -NET gpio_exp_hdr1<1> LOC = V20; # HDR1_42 -NET gpio_exp_hdr1<0> LOC = AA24; # HDR1_28 -NET gpio_exp_hdr1<*> TIG; -NET gpio_exp_hdr1<*> PULLDOWN; - -NET gpio_exp_hdr2<31> LOC = AF18; # HDR2_40 -NET gpio_exp_hdr2<30> LOC = AE18; # HDR2_38 -NET gpio_exp_hdr2<29> LOC = AF19; # HDR2_32 -NET gpio_exp_hdr2<28> LOC = AF20; # HDR2_30 -NET gpio_exp_hdr2<27> LOC = AF21; # HDR2_44 -NET gpio_exp_hdr2<26> LOC = AF22; # HDR2_42 -NET gpio_exp_hdr2<25> LOC = AF23; # HDR2_24 -NET gpio_exp_hdr2<24> LOC = AE23; # HDR2_22 -NET gpio_exp_hdr2<23> LOC = AC18; # HDR2_48 -NET gpio_exp_hdr2<22> LOC = AB18; # HDR2_46 -NET gpio_exp_hdr2<21> LOC = AD19; # HDR2_64 -NET gpio_exp_hdr2<20> LOC = AC19; # HDR2_62 -NET gpio_exp_hdr2<19> LOC = AE20; # HDR2_16 -NET gpio_exp_hdr2<18> LOC = AD20; # HDR2_14 -NET gpio_exp_hdr2<17> LOC = AE21; # HDR2_36 -NET gpio_exp_hdr2<16> LOC = AD21; # HDR2_34 -NET gpio_exp_hdr2<15> LOC = AB20; # HDR2_52 -NET gpio_exp_hdr2<14> LOC = AC20; # HDR2_50 -NET gpio_exp_hdr2<13> LOC = Y17; # HDR2_56 -NET gpio_exp_hdr2<12> LOC = AA17; # HDR2_54 -NET gpio_exp_hdr2<11> LOC = AA19; # HDR2_60 -NET gpio_exp_hdr2<10> LOC = AA20; # HDR2_58 -NET gpio_exp_hdr2<9> LOC = Y22; # HDR2_8 -NET gpio_exp_hdr2<8> LOC = Y23; # HDR2_6 -NET gpio_exp_hdr2<7> LOC = W23; # HDR2_12 -NET gpio_exp_hdr2<6> LOC = W24; # HDR2_10 -NET gpio_exp_hdr2<5> LOC = Y20; # HDR2_20 -NET gpio_exp_hdr2<4> LOC = Y21; # HDR2_18 -NET gpio_exp_hdr2<3> LOC = Y19; # HDR2_28 -NET gpio_exp_hdr2<2> LOC = W19; # HDR2_26 -NET gpio_exp_hdr2<1> LOC = AA18; # HDR2_4 -NET gpio_exp_hdr2<0> LOC = Y18; # HDR2_2 -NET gpio_exp_hdr2<*> TIG; -NET gpio_exp_hdr2<*> PULLDOWN; - -#------------------------------------------------------------------------------ -# IO Pad Location Constraints / Properties for Character LCD GPIO -#------------------------------------------------------------------------------ - -NET gpio_char_lcd<6> LOC = AE13; # LCD_E -NET gpio_char_lcd<5> LOC = AC17; # LCD_RS -NET gpio_char_lcd<4> LOC = AB17; # LCD_RW -NET gpio_char_lcd<3> LOC = AF12; # LCD_DB7 -NET gpio_char_lcd<2> LOC = AE12; # LCD_DB6 -NET gpio_char_lcd<1> LOC = AC10; # LCD_DB5 -NET gpio_char_lcd<0> LOC = AB10; # LCD_DB4 -NET gpio_char_lcd<*> IOSTANDARD = LVCMOS33; -NET gpio_char_lcd<*> TIG; -NET gpio_char_lcd<*> PULLDOWN; diff --git a/lib/CPUs/J1/doc/j1.pdf b/lib/CPUs/J1/doc/j1.pdf deleted file mode 100644 index 188ac022e6340132f21f28571b04ba9fea626793..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 124188 zcma&sL#!|ij4t3~+qP}nwr$(CZQHhO+cv&qTk}scySuqblQ!?Z-Si<<5D}wgq+@|1 z9lwq*f?_3LAh0*Gg5u$!moc?7cd;N~`!7+V7qhf+F?AxK7qc;RF%>a2wl^{5GBpM>1{j`WL>2|Nywb|egs_EmtPajsd=aW`FnVK^ZPk?O`0(xY^1Hix6Ztfjt(E8V0f6s7Hbkpe_k28<k=P+!VihM#krniSP={Y0Q+ZPH&>#~W-nha{X*YR*jR;h|9q68$wrmR=No3Xjdr_zX5TQ-4&8gc z$S(*?seUQf9|tqC#a{3W)yvU8y#Qrvjc&Ysp3Gc{W-9Xa|9v@L^7euMcK@8joUzrd zQ$E~poXqTl1dhv=yqolee0iiTt1hcDU96!ox&O;Qv-R;4Jw zRhq1wI$(Ix{ijDsuyPUpE?56kMFXSB@ehFFQ5h$aU1=O{hKktT30!>vFhL}Xfv>S9 zyZzUMe5J?$!coAVZ`lnIDB|HJQ?Ep`7COTS4}b3I^Zn}`p<(@s zf-|z`?J5RI{xnj%r*(=@-kpF04s1L2g&PF~lGo;a&*#Ipx2GbVe`Q+y<&ppDRQ~00 z+skuOPY*s`GhrB}p9=^JxN=*f4b9RMr*&{6L^PAsd|o4S^{Vg>{I2ta{n`)}3jP0q};! zD(jos^N0BNfuoF;VP@c(1)`1Ox%p6Puorj6g;CDFv3S*6p}6ELeIr>5CIQ`rUI9q` z(DkAM?!xo}V#370*TV4lGk~?xwqw9RQ1x@-{7h5^R=3O3MaeycoSxZPIn+zYl$<);`Ijr{I?W zsT^5*;i44PG`w{5@+*jWFc2d+GW$pBi&6S{pQD&i&@meT;Q#HK-`!xpfAXkCc37#Z zqzO_XM)!ib&XA&1k&RUCZh&_PuL+5(2Yc)MbW0V0Q(~DsRI7eEd+7^#D#aCi-Z&@b!fEV`2oY7WM zMY}-K5{=+Act9lyQoa=6SD|Bn5Say;htQe6V8IP*RkN!&v~VuVO#uzRF8n{fd$bX0^P3JjvPy6B6IjOH?!P zdW>Dy#b#Xzu9=vcIfk||Qz@`Ll-P%HIbsk+69M=ly9ZbGMo~P$Al`2Vy%;Ab!>eLz z8gl4<6^6+?>YMWk2&$qUxgIK^aLd(q5W$CGSBhIbnQiDZlNB}yo#-}-G}?>Qx2^g$ zDjVTS9oV^KYNQAlq~4+YVytd!;%w4HG=?CT$MyS)Y3d}^Vyiz948%F>XRZ^RY6;>2 zh@!SI4Jtg>QANn>splfXlPjVk-o=W#FMhuG`_KCFRsfIM=npFSiL0YIP~h{=TV{A+ z-4F{=s^hqUagbD}+05Nns!uzEKLZT3m%coU0RqWD>6Doum&xxxk|H1{Ohxo+G;W(( zt>T;}(4bZu8X6@H7Wk-D;}nXbBYkzjuNtYx{04CBooZ@1Mg*}x7qSIK3k%iOZ|AjJ z*953TapAu$qJz($Dz(Z%q|76Dg%Pw2`e_9 zY>p(9xawr@p!x^sh8x%_EDw@^i9yqdCFFBa^(9#1Fce|YfEvcBY!+EmCO8}t9~?Xj zR>`(;RW2|}=yY7W=p9R5ankD|Ht7^)u_*%w-Ok9IBs|=QWqt#7rGjrCEuSZU5{*LD za&909ZDAaSKB@d)QqhP|C1lv?=z)32!y3y;#F(9K8(|Vq(iUSA4>Ixk86fMmkbkKR z3`PuKj968~qy038XDH^)wj54?XszvEvigk)CWerX38d*n^;;zHx~3>|&6Sa$G)ahX1b zX(NXJl$Ti_HCvTOQjh`daE}st1*D{^6&2X9kGHu2vDOXDAS%Bw$G*{M0Uv2C{;}{0 z-2Ea3bKdXG7PJCLl(RQ{5{zyeg`|}0uk8D4)A!e<0|>SN)e!LB1oRNT9kfYs3{1_9 zc@PyKnhH7K{X11d9RCLRAnuKfSRbI@6SpRz&0xh{(lziCECQ|a2q?sB-Gp*x7K51^w=W_QmW6 zbJbk?kb@Z76L0hti4Qd=oVo~N{9rVz`%Z&6O_r{$g>oFE5mf>&2z_2hL^k`3g%JbO zT?N~~j-ZOduvFL-+xV=JdETZXpuZZRw^|-o&CpwGtCs?g)d*2&p_LSTcEEN@nKs90 z6~#DP-W^Ca_pP58h~^6T2Gb~vms(~~XP{L?vw?9JE3aA!_em&|-mx(sC435iq`lxi0521o=vUli1H zluqg?U`m15H+G{LUTMaug6&wTd;jFvfb9K;(K0zt5H`vY!JM12&}pCov7lB>*$V*W zPz}84qKx?{Ec4AB7)TgR3Noa$NrdB{OMc&>UJ`h?Ui%MZ*Lko_23K-h;)4|x7A5M- z?+ZZ?l&lv_t{}um;Vg+Dkh_t={ZwWoPV*0FkMi?P{{R#6w!#S~ z2A~E#i>zmIyS-Y9o#{@{*K*{^c@TVO|5t;zF?pR z@V`ZD3@gy&=E!uK6N}udPeuUHMFqA!;B{1iBoz^=Cq0?!!ou@|M zYh9BriJ@`N2A7$iV83YHN-O*`FsrVrJobmKaY#k&u2RN(0m6>RQ*YU>m?K>#cE7sk zzR5bECETBIFG^8oWefwCP}TGeumCt^>)#D@3J&?esK}!~70`0}sN!=IelY|7CVeg> zht8M6ChtV=<-FEsNIlh%!#pMhz=pMA%|fu0VKiG(STq%_DC$QMkh8Ali~7fL5a@GL%nx*50G667I;Xpy>KW@zAJNL5^5)$Hoc#Ubz&T zMy895!v+MhA`TLq+;uE{xugOqXSe01SJE6o(2g#Qhye0#H+6=c=)j{pG(Df3TuZvY zF2efm!BJ1w^)@8)$`RjDM|DJg&N&^I&B_y>pzJA=*JXzd8#H_OnR806IKE_hu(*B6 zT#Q~)3I`|x;rDGu#^+w1?^t`t1xnQm=e}dR0YaYD?>0O%t)LN)jAvl`Hl#+YqWA5CbH%Pd3x{IOXt*3b-4h8 z@<0W0rA+%RJeBKuE@p=5$0R+uIDdKk#dIlMZ1+*HPb%ZIKW#mEZe@xl1*sM&%W0?YttW)Zm5{ih~dME`3S;#_oYNq-}w>%G|E{ThcFr>z38njyNrg=9A3}e z(Q%l5wd!4?g}89WRWb(mZQV(TcmjpytaG5i0L~k$FHjFnJ*jV0ubIsVC6|_fY~IQi zijzxC8Ih?~*tBO$TQ{`1hD5#@po#(Br(+APbbAl3YEZwnI`k&^Y;dxbpGjQzUgbdA z^w_FSDnXZ)$b5;!d);bL4-{ENFb#c`>IQw5v@cm`(_{?%87EpoaF0yz&IoD1g=Wt%>TjTMR%78!BTk|$v~7OC~F^zhmTq*%~~G%uC18mFR)Tw>L!!C@6ccO zEor2y)ilvJ9)SdyU_ULZp#4Le&g{K0!r+cAedS`{0n2k~D)V1nEv1Z_~6$7czNr@qRH&^R-Kg=?z_?g`vC$Ac}4Q!53f)MHh{|k8h_HDIOVGG-5Ua3v$S%aPST;qH7}|<6~4dIsi4UV_PpZMq@j)AV+70Y)p=$JN82= zp8>h~>17V-B|FIfB)mOK6jCBHGwPPIkuAB9+=*$Hng!l6T(T9bR?Ek4-B>I>JI;>R zWEKHp_hBpRI|Tl>Cf$Ks5!by(6N>5ED5!y!VflKHX36R}7a7Ne;@LNnzBP(Hd^{KS zC&K3(iZ~nXzQ$fdAkP39MMcy{8#7RIfTR_r=^-;5t`7m*#bYv%l7Z_IU>#cINSVZK zD@|aKsKZLrH^)0LVQ?6T_Y<^mTOB0UFu?Wzs7}eT z?FRi%JD9q%lv6d8yGieMN;$PamK1~so@!jq$gkM~>f8#)>E7a>i3X}}AEs*UaV*_0*I5Z9*VZCfuhK59<4X)3q z3@QZcVNc~|`9Gmb)ozF%p+Mt`(-E2=s7?l&uN4CDAk<>4!MPtJfY@hkMSEA|{;1Sg zC+9=ZN%>RgLW$CKeUC7BuG(R6&W83SRpE@8;}u07?vEQ5A!tTZQzbe>hRINfE`lW^ zP}^rn$oplg2$>Cx=VM+2B`47i<15{w@G8i|D{HM`+{@7x61oPFgmQLF-UE-j9}OMC z9CFymt`F_`out`e1__mIP9JWW0}0wx=ufGb6bT*EH~TrELe4a^KGgiR4AP2IQt^3q zt$_6?XKd>Wqpuz!?gF1zkqJE|Vw|W+_GJ&&V&%-4o)qjbTlle2EqSMq77Xc-({qvh z#l(W~-ks#dM5wgbq+DvGvjqdWBclAb8Ql*VvwwKaHf^wfdz}iUt9XoMwA(r48O9z2 z-e_-)HJUX^^q;VnK}xuJk{xp{i=IT$a6n+t?u=W?@4_@R_#vYU%xFLOsvyg9FfbK^ zP^T;!G4-_s)iwtBJv}>hvoRrp((1d_^HrB#;|knUxp^rGNfZ5)ho8hc*SHIwi$#LH z#4t66i3^$=_hkpL%|Yu=EFg{^E$qWg!gFl5L>BM1tg$l3&@2Z74hN!o+9Y!&OLy6~ zG4>LkEeG-bH_aQsUVn>`%FRugT^;GoXrcZZDg2K1ks&8c3$sdB;y_#{w+gx$)gwlN z2NTV4zRa%0IG3jD+Cni$5^rGEP;?rj5n+&T%$P=aoX?+bQ~}nP!hL}qiZn7C6?7s5 z4WT2Ho!O3>6Zm3+gjGTHRf7lYJjBuJ+B)5+iR$WId6m(@KzB&ULOw5h(JO`)&+6GvQzo z@Uh)$sFU&_f&5pgUJ9fmH9XP{a*lI0Bf>2V)PTBu12ru7JpP+pv)9<6&kMRGQP=31 z>f*-@ZDcV!MlTsqwip_MOw-SVu$s&YrD!0nH&v9=V1O4^j8$C(w3BzGK;~(_d#vxU zqlOgwcQ&I3L*~}PNT5rZpzaoHJ;a6d`4Ap)=adJPmRVj)uBvlL=^r2d(7zLD4&Z(I z5`1@);|bQ~!Vd#0*9nq@P0a^97>+7Q7<&pgMhDLr=2%QAndbKNGb3PbTbX_ zGrNy%c2SXMBVfKD;M9;qa|=uBS*-DS;SNslv~y>`kRonYCPJ%)lUQ3HWpTRU2?3zF zYB)c9g_3VqrLFGk4kr(BeL(zWl6~rdr^uwp6KVBW&KPYklD<06jN`c-TfK8~=Vd)s zL~3!f7y73Phj{RfUJl{amJ$B@bOfzHjz9EpPz8sYgYr9DH61_^#4-EGNcR~a3%Tqd zE}Cm@yF0980aHp{?8wLx1M*&>f=(;_}{UORasixEAfR;;0+%o_n=@QK6 zekF-#iN6Zf+mc#^KI)&S62&I5@GaOfne4K|q})7zX)A6CFc9LjHR=M8deeJG7y-|7 zPm18H%hXp5IU6zF+4~YBhp(028eA;yhppn3Hf{?sq0p@{VN$;5;W_0o68dZiPR35e zM>2lm7*S_Kor0Xmx$6%&xM=pmR;CioMX%Ve_#~+qXI*STOtIJoQx4j;Y?KS>Iiu%} z*+I6i7BX+t;KIgI3`TAH4Cdx-WC#Pr-g~?mH?vWhI0HI&xq-7fp!cPfJgOQf)_Wg& zbwu?lkYFWH6+g{2PxI6feyq#vs*Ow42Dl#iPhZlOB^KeFX2sc#4D_c{1tIj<1f(TCxIXB-65VuTUf0*Tp*;I(XVq;wmgb^7*?>5TH9us%NnMFx zjpaXpRiWRYlF?gkwsgfHlR8>aGG(NWh^qENVNZPuFi8W~B~d(ffU6{{Dd~^#IZUR? zg0cPBw4J0!>#{^PKRC_}fkuf%b0Neo_ab7eW_r!o#M#QAT_*+`-xH~Qs{WFYoR|4| z=01x1eHuoG_7kq#kqwBNRmFr&XMah&7^VAO9s7xfNIyy8Mv``X z9m~Fr9yV67B<|!PE`4(uEnCTzfOqY!o72PGubp+k3@y*l2Ah2*ecT9V$HcQPfjnon zq?!7mG~*QS8+$aKyce>#xR(T#p|s)}qL>rB4+`C^2A4f1ak3UEWK1w7vkmvEGvsMj z4CTg_>b4c)x^WqA)32xP=9D^{O5O8wSm&-9o=y>F$XUGfq+dG^V6b%-TV;;b5>uP} z1>{z}=Z2dj3H`(sR-gYRg&0S^Q$@3lmhjM+Sa;8;{&yh1Sq z&(SG!>6x_BxOW|kN~BuGqEtnR#81p6tO5uXUrZyEB>cSH85$SvnwSvXe#yte=d?)> z)9A)9sk!FM$0#K?3d(mh{Au{6@i4!Rpx=}FBHf)er0WmBe*6Vuf1`~AZ=*JQJ^i6; zlKczmM3oilTI-8!W)Z?snGL{)B*uZk?YA&g<+UfTNaI{PL$zZnw$|#G}8cD?=LIpEn+VR@CN5vs?dQzp&eq;cRub%fu#L~BNWKH7S0R;WXZSp5M}DbBrz z+SxP%Tdzc#nd1#0f;dO6q~Uwli|41U!YbI-N8TmtJ*s?2cH;U~08M(Zl!hG&RP~~P zaBh~+rE6};%?abVx%_9vZBnzTDx5VpC1nCo{Tvd85OlW8*S!2-)YYi13T9Sz>SoTm z``kL!!0uIZ1QDyv7pj})+CCG}_K@u-$BOu5=q!$JONLl1rNRd1mG`ePlP@QtelF4%YDZB;kdf9y;A^Um=cp~Iw6ZFo>&&hoDIL6gY(>>i zlWEVTZX~BCzv56uxpX8)H1-z- z`AdtnV-5{F)2o}D2*_NTGbA*q5o<^xdB=Jlkk8CJ?|PSQyXYb7v#+*(?}NT#dKpo37A+}vjVXs^ybMZfY1Bs+ zK4Dn5cU*GxGhKD@ZoT9Y2WLJ0n&{($22X%c_esOmC323$Ohx6#N*R7A)yT^rBy#k* zTH@8*M&Igi-w021%Z$Q&(ij#+rlV#x3#v zp46;aR!nq@uiAwOnY4}fuzmeu_ws&F!#@FPw8yiV`^`xg^4US;PzBGBuWHEt zj=*b0e0!l{Xrj-Uc(5Jwu4b-M$Lt7#F<$M2X#A_P1>#v6?i-2q=>;X}x+Fl{C4Kj^ zM+nJ}8>S!R12a~S8QDu#bpiD%qdPRXAq6?D(Vfpe`;uo7orY#pkv9?TZ9Y6_yzski z-I5c*=xfDB`(<%H){8K z6Za*CTn|PZp~p5geHxq6A?wB!!gjYWNjN7cF$KOS$zx;+b}g7nV|^H|$KzV0Uy~s3 z!a)R-q+ex{AV01dfaxAEq&LnuNGyiCGo`+tJ-kJ<-|3jpPMMhr@SBiPD*Kk$Lp@jG zB-{tEYC9g`m4UgGVN@GhvQ6{MTI$4uW8IC~i7Sn;B+!t4)dBr$7E9!Yx>(Zrxc0{4 znQMgoRvrJz{fGV3PxD9fyJ@8m3XN}NA{=8w>DO~mlVw@~TzU(!HMl8f+zt=kqe3$ba&fff3b*dS%Mzl*i zUiHcupUj``xK5Q#^giu#FwVGY^tca;(QzhRp8KUv=i@VC1HW1ZgLP&}h6?m=kqd$H zc;l0AlbDF$>}`YAqUdm@Aa!eZJSEFR^P;pZ=N;{KkM3L!=YsBn74|Y5 z=<#AR@uGREIR~Y_96VP6J$AheP`x2TX&g#)I2`L~7LFQKIFUhWOon+DvZm@UbXsf%|#%{M|8;*y; z7~{r*et-^#XWLklQE`grGP%dE(fT%p^t61G`&K8^bQ-i{`0u++RA*MpO+p8%{c6s$ zt}C8w92EVtqD0{=b{byEkTT9QuCYTJqyo2nViJTs1mH6`*oaW(&lhB#lXs%?y}wl$ zTVw=94*cZxq@4NuxRsOd&;K!lD=$w^0+a#HA1yhzO^VF6HX|?5x+*+=9O-a4icId@ zmRXxxz-gy9d!-nw8j+$iacmMs9u3_!G2x?4r$LnwV3o?BgR2Y4PAha_$--qh58)Xj zwY=HzZ#wE3Y11jQVoMZ0BvrlwUi8&P!s?_&U**PFz%9xYx_njs4)X)UG<(#+hp+v38J^M;X2P`Ev`rKY9>GR5b+h;%cr2<`$i!}sukWl*hj25%9YJM znwtGwMm9SDMxzA>$~+5m>`2364qH#Jg0<)Bq0HGVzZrv#-c1Z$yY}LJw9T8x z-RBdIPs4P3jvjmcBu-KUNZ4(oP{Vn~41gxbYW#$j9lnp1cYcKZ=>!^mY*L16XP}*! zw4$#^FX(YQjlpB

3dsjOIP}A;k$z=5U=igCKm&tF`purH>w)dYTa0`TX8b!2cERljnEE|_?je7Cu3^IC{o#OxW*iL(H_^=b33z^0La+~>Gg~E0xJ$s!94KZ_KBuLzm=D3F%6H>Coi8R9xP@kRDb;0kmXkn?rKz)`P-A8%2{ zB-F|ET~-v@Z1b*r7CD8k_KB$+YA%hshmck7-AoNad)7^mN2XlVvM>NGgIUB2%%lj* zo@0zuD11*z>d&TD!yj}5Kg(S>YC7KcBEyg3r+|{R+8pVPYgsRI)~71KJi;u9g&tm7 z7E{B>jEADZtFX#3pFSV|(#En=zUM8x+CHDx-{CIyuhZyl?;ZDd zUmL#%_Rs6CU7f${ZO&WWKhFfqo>|sS=EJJv- zI&UyyfQ~;D(LKtW*nMa=QG@J>`p6p?l0&;(cOfflM_zk*usj6xRBinZmd8LUMEcZg zJ8LA-a@Eljv};@QSjL;l0oW6a-n;DBL=PCMLv1I5EZxK0;PT;&zeplgMUH({2*wKC z&PtV91U^FtqUc^pr$edCT0GWX7Af}S|NMc1ebh1b(x3hu=Zu* z{r()@P@~f8RwKG!AQ)vXZ*(6%K)yh;0@xnkWIfm{f~@@IloQwNVhaUe9HX${q$L69 zw~E>)^o?r_rEvibQU};m6D5+k=>*~%Do((>P)F|K9Fx$aJhH>TL+Y-avQ}l*5-496 zyysOSSpLHtO#jj=H30!34}rn0^j}@SgnX+A=-maRuzw6Yv!zKiRfjsF`*iF!}uT5e&77O*O(1FD#> z5}b}^+cgGZ(72%w&&gBBu9Zo~N@ErI$`oNfQce1^920pGEg_|rdk;NKc*VVR58$35YNP|Ra#JYG za(j-lb{DKXw;b&W9q)5RSO645HX<0K82teTIEh3J5V`~l;YHyTQu)?XLa2xRo2hi@ zQE!t0*&y)<^29gDXg4@GTxOcd`o5t-0VvNy0jM^+3ePYDL7zLki~w4B6aq27N|U$% z7lh-=@>*^z<`reJr_VtZFkMBGS)rmUpcRPTZtMMhTOkl`6Yh~FVV!??l>O(Pm6+)} ziS%pp_tm{v1ZtFbBs1xoAD+k+g)Thws)WVoZ|~RNucL6I!ga}+0I5fcnm~lb(zC8d ztbc^Z?o<|xMq>-CH56xk3z)-ziWJv(RJ#ugd!NSy|_66-&FLUw!Z zb^C`kJf_gAeR3sDujF+Qywn51qiOx#BInWy$0UpkPqepSlCJ25J(-9%cJ7;?%)yRC?JHEnyyCIhQu{QXcFQR!v zTp1C-0i%y|lBGTz+)e}bU^C(bBE*do?%GcSfn1GZG02LT6+s?~1{gU)<=rPaebXmN zj(=D@MCr^+!|1`qUw0^Ey}3j3iFYTAE)0Tm7FcW1n+}JgFoV?>(J0i|iWikc|6+6O zX^`0zX?MSP;t_b|?JZ|gW_Oc=mq~ZSA9xy%EEd*tYLG}Sj63;SP%|wF_{RgxFv;wgan0y zpAjT71r>NP)8xRhAoiycE5Zqm@>I9MA+GzW^PY&x0AK|xI!q`vEWR^q;p`I93vmUV z$_FtA_C%i{RWLz}lTeY%y<)!m88fhXti)_OI6^F+i}e<`?K0TfA-4BSI)PJBl1-sN z2cSDaLCBTmS*;m0MdY&&x`mz*0Rb;`reqvd$UlORCs%OX5Gg&%qYi!Z^jQJXi>&^B1EyUyWBSz2MD`*(5z!b^n&zX7#rv-|;A?2Vjq1DkIY~wFX zLoNba>>^G~1ch=p8qkt6(I%zjMm3MkO^sP>Utt%1o(f79NHKrQ<#si?%48%7r$HkOtEkm~sF1M{; zjjN{iJ^iLKdDPPULgZJO`62A?$cMBT7hqIXu&QC=8^H{Mg=PG4rxmF3NpqiH(a4t* zVXzEv(><}*gtuF>wDP#S3jcTnt|Z~H%DlQz8f_+QZtBfjA4?g9)KSZv<_NtMnU7)s zsn+N{uCA&V;br2-8)a#l3+7BqGr!D9tfCiJ&=l*{031-|z917QnwlE!HSHXJvWPf8 z_Le8_P0E%#GhsYy@93$i3`*0xrZ3*;qyO*Riys>5Wkn)X=3W$NgTWp;Y1&L1;l-5-JZl}3fQzOncuUe(kn87{=EDLraZ(mxsqoO&^UnYmcm^>8B`|Jr?Ka&~JjU!p|Sd-E8TvwfP=UEsYR2X3Tn<`UbltCY3AOHe`MZkdi)c5z-6=w| zp#k;pw;nv9cUbA*O7sK#A?A|+2s_?cL|qSkh}+1%+%`WHa7AUMjZ0JqhP>?Ur7d~j!Ikuj3aktjv<8XmbRF2Y zL3ahZtO_D>C7lmXh$jj1J^NCpytq&q)asTA)0 zk?Lf*Q{-LnQtc?qiB}EK|E_{;51nCwjwF_# z9MJ0+#vp|h@f(EH4jtxEnBw2%$*lPa@5m5B z13UM9gLBTvQ1U}uQLonOmyGy!KpWVw>A5=cKtvN8^dV+S*^#i-pCjSrh}1a+ASG$3 zsZGHVve1@E%CVKKDYNWz3|aBZBtlUyhq@+~7b-+n6)RPbx=ib547O$!lSbo!LJuqw z;c_<{UlO2GBxy@H>QxAu6Q|;cvuyRrxw<7(=9y$=Wi+{4giz#S)@KtLxx-D3#aGBn%Ujim&O#%gg8A zbY)$;8;}xQ-ng2ba+BmZKaEmpM_x)^Bnq@i*3vz4n$s*UzUUv~e6-6@QpfkNPpOndxV`T(p>n=S(qs2=?IA(7r&eKUD%)wn1IqyOz_k^`}8Xt;8SK(s69Kz`Yn+mW7X!G zfW+9$5k@UTx^$eaZPhK)v$j7D%`=K#C=aCf;M%G0f;fZ0Sk+jI>M6iogdDWhoCV=8 zAU|dTli=FQ4dUJP+~!&e7;sj&At-fv&V(kXR(CN*g|KEfcsCC50BkbC7QvUb8O6Zl z>*KOhz$m$#i5N=9FVDbe-(;7yzI?;O;_oMg&QT{=$|8ioSYAIdN&M@$n!X$Mq~~UO zfYYFn_{B#*?P{{^+uqZ%-K54%zm6fPUL=XqLcV`=1BeUnCEu)^{2haWc3LWtlRNo% zRNYo5MuTG08E~>ImrWF44_OUf5*~>(37ZwH{ZbP4lx(0GY^~IZWzI5mfx%E8?5%2( zY6chh*sK-r;|u{x308BocZWk;G-9cS7tU0Ztq7_rjAGP@Le+BYTV`hLIuOMK-IfPR zs=qdB>c(Q`A1?aAccviJRG(Nr;XLWkS++j*l}fV;B{1+?d44evFK+v5vbYJ>?S)>{E^tNoriGWjHwiSW77O-rv9+hqMGpPil4VPC>@D3oDEE1?T zRk&Uh8sRczZc&ET%LmV5mLn#o+x8;=qD#7QLB?dEZA?>(CxSx@Zc$h8#w1-E_s;|x zHD?7=9LuXMhTVYH;26+RoQKF_Lz```KdH$rMHIc*y<{0 z%27rd&!R+Jv1eV{Q3i^ZRsq38_x1k$m9OOj`uov?Qb#*#T(IV>L5OuKkXBMHT?}Rq z7i^AA(ak>`-O^v-I9$_8NdF{AJ-H)GnSf^c2;Wlhgu3k+s z!cextU}A+eu#AxGCS=41@kvpuofR*0N;0!pf|u@>iuPHNNeVJd* zLL`5g4;3m)2Rv8`0J^kFmJ=jsWF^t{Q49q6a=(3mneZK>ccQ%T{IHm)c5#0_>BP$DHEOFS3yYTTkE)x0H}*tAjNMQrkP6k0PPoVW3Qn%vb@+1+MPqRTN- zr)`hD2LR;g_Eqwx-~tI(MmD)=C0)BQDIW3O{9bg2c5W@v;blSVUY3wk>p!|LhRt%G zg#iwBt?DX#&tC&uT7p}tRErxT{4Du_6dcrkFPNew(kOZoH%_tTF%1b!PKmR-!u#yY zDA=am(w#q9e;xZyFMKJN!z2qqL0^)uHvt*2SWU3i$8m9aOdwwk^B`Jv%(m-Y9Yfdd z&_6 zTP`>5oqmu+9Wl;9xU!TBlW(7E>E zEYid{WWx39Vj2gjkKhnrac9yP;5+*Y6o0>hZigu+s3$Pb`h(#Lc(K?GlD{N>OeXb4 zGVx52LtM~?Lx|{=r6;xM)NPnqFn==l&4Y|Soz*M!XfMbn4Ka~5Kc#BGf}tbMDs zp1RS%oMx8xce<^pYU(yS@?@GJz-ih13iaC_JH?7UHyTQ+ckcw$o&KXJ?SB@eZn`$M{qU zkStWo#jEUY3O~|n;o+*B-9RF)Az9i?X`TMQs?R8g03s34CZRS8X3sp60L643? zUg5D@IXYL}z4M~)CZy`Pfxyq)3h)Rak9dx&L8z|kal0dLKgO!ci*Z*B4}}J8c{~fj z7nbhXLY=iFIuAG|zO|}uP+lCDqbAAq_RO9B3(vmaq+(-pusuCpzswSqLvCnZR%880 zH=oMRv!d{p>$?#~tH1ttkg4cZk;9IjVJeI_L!tuvG0!89g-f*ZDUBW&{y7HL@T+0< z79+kLt}$&am^E!2=N8sgxwr40r z-BUtfN#;V{$2EA=O;%z)sREPu7&fawXDuWzel!m9?*6XZ<&Qu@=TInRAWc7B`C{@r z4x20NdC~jg#@NkpkXh zv+?<~AVN}fDhb}H+`l#o(dSi@@k^caOP%#go%c(f`AePqOI>}o{o4j=Q@Aa~mKD6* zKF6G_(=o69WXuyS8C%+JeQguCC+O?oH^X;6?w)7y@*a?O4Lu2*)r4C4MrzQh@SfR9y_6PALx5D;TXrN*CL7pD*F$>ZeSC^j%1mgJG3$|{qZLd zJ)`TNrTOC97~GtYDCnI!2ebside+a1!p~>n*4&Uk#$yl$e8BB)h#372zSPK)GQ8Av{dAQfx+qVdWNn zDK8Yj5OQ#O1kRZpa-Bh1>AZ=9cgbC1KeFP0T~Jm$5Qj;#mnaGV1~FK|x3tSIX9V?D zd1UU)r*tqm%LZt*@cya!7o>TgKnKQvY7nA+$9wBq6%D^G%AT zb)T~E#fva&FXsY@;{dd`v+V%Nsg->n`1p~+6{lMqdpWYM5-J3pM||X1AzQWBJzKh3 z?7?j7;Mr+(_fs>+4&H^giNkj89eJgud)-f6HR~-;Zb%yRfV*TwOAJmu7N`GbPKm*5$S6D78&WUH;#PeH*IgVAck;uBM;b=r-APD|2JwA5M@Zqb(K5;O) zQSdGaD?ax7ur1pd7<*+;J{sVX)f|8C%YU_>+&*T%dYwE?9iDHqKdgOxuDDjqmUmkF zAOYUHr+YWh$gqNm!#%BApJU{H?wrx9;f7Z;^T+IDhwe~sn)>&1xpZ#vzmN`GGx67bQk?CX7#I8Hnh~R>5 z`3Pl@Q(Z99HOZz#));`m2O$7c#0-3Ni=W{GG7l0j>d%itqrp7^HIZNaUxeHS&4mS+ zrsphybN}GHHE1g%3R=d`ywTMF>Ifj0kuyrBl(T5P6Z6okpCF+es)OWhYp`BxHf>|5 z-|ifH&z$K7^XQN$%iJ3JKOan)9kK{J93b%dJAt~t7qb+8<|i4wjNC?XFoqmylWK)& z*{MB^A{TW%x{Lr0jy$zAm{Dr`eV*7srw=Xu&+b-ALD&J{wWLS*URdcQ1 zjQlcz)P&~Qlwv!-BV>$!l`rn)`~>ViohHSK2p-YNH6VG59cqSGC>&i`J(#iAW;Of- zbC^{Ln&N#}*Xfhu?ZT8Yc?TzKlXm@TnDLkD>KN0^DiW4=S3`EdAc$2Jaa;Tt6lf{y zg-m#j#F{%yOE&B}pOJ?arSz;2q3K2P-wWI?INv4vkH09_>1=(wGdujCO8w;CyC1P- z&-Ov74RhMx#M!b}u&=jJ2STZETJLq5-NB82g)&t;S?KBew$JrXy>&^Fu;{t1?$GGviBn7L&=UkFPYkW{@jcJ?{;~I83H%Q2SL!>o>9GD6 zJGyH=7jh5PDOm(`Pz9u3&(mN^?w0Xk)_9#s)m6)pvU|gW#(8)2t7Er z=&elzuTr)3@erJe@w(mBE{)Z#f3lZ2-=#69^mgu%TB<=i_c2T}X-m|c0>7@ZfRDr) z(y-iv%{E{}ZvP9mAMw`5R`pcfp>$CK2D-Xm=OdU~qbC%vx&QF^_0FN&JDt8KM`avE zRY6Xr-GHijVe9}%t__2e=0Z-OB`e^9V9`@?*Q+A|Z)U8`94F;0EcZI$IP=-Sy@{3R zqaVcAT9|otsoVbk1+SU;_mTfC5hv@Tk)By&MYV8__Q5mt%v&+8)5R#cJM;CV2p~)4 z?c;Deg%77pT&Z?Lj}r$F7B(IP7T*W)dS?-3%QVbZ7@RQNknUnGG(mh_MU!i`=i59) zgz=Gs;1)6j_L$SBlbCflNC{=#*+(BV%&U~u*ufD6<^`Z{}~;<&>u znV(x)neBK;b7kssRk{+vL)&92K}6(M-*ji0L*+`cUx;`>xUmWs0vf`d9fB(rxsfq` z6%!FYS! zl$l_Bq%s-)PU>naX4|LL6MBeo8f*nIabRy8XQGB`{$0!QFDBYok zY;kz~Wo|~+MPv%Ysa(sYVkR!kUabvlBynj~joIxZww(Gnw~kdt=M~{;N?wO^DVyt@ z2Fg24MyLJ@%^+)!q=_!!Z*I(eQpS?2l0_%U?OI1Vf7aSwx?f;cp_y67<*B*Q{e2v% zgAY8}gM#a}V7mu*@=cT$E+&zSCUsve%C7iz-tl4fD zbxRVuh}c07OTr7b2I8t^U}-U#@fKxRuq4i~BuC+kZqyVC$1i)g5HlQcxlNOc7dkz@ zk+f-ak}=yRd7{X^`xC0$`&qV-I$cA{Ku3IH%jxB4V1&5t{*09vU2%c_9z5@ciaRfzj3)Rrr5Kmao<33o)Q`ILpEn z?ixvBKSmXGE%ME#L4HQKDO(iuv{{^O*Shew`28h+oov< zgy5G$K)>hO+EI^7w)xl3OCI&)bx&mS@4kB8_prnOKA>WvCjE*q6JPCcDKhz;p8Afi zt>7na-C+ml(=?xbiznY)h1UKo`+}Ruu5USnUV;iYScX#ENBN^?nPJWtia%zK!;HYD zm4acEP3%I$lvp!Hi&m{r2Zy6+4UekNUc30tfvUo)8q6m!_V5`gI`dPT1^p5_+)Lkq zog=q5+UFP@b2C!G@k4E4|D&2SkQa>8S-z&7EJ&$^XRMtq0uPCv3xnri74R8}IvrbfjAA_ zxTQj(ujog5Jac<}?kuRrK&ix)sX;TgO)8yu$dGWUa^_x#+ys<$)p@o!AwP>l(fphP ziRnqHezg!5X@9R`;y>c3{}Bi3f5c(<6BlLj#(B|bqX3bt;i6SkfFb+ZkrhL5%b{rc zV^edr=Z`QdeuPo&$?ua+n}L{HTbrSsIi$Z8JT!RpFK>)Zm}d|i9&t`C#2t!pY9_w? z(hXL=ZA1E3brO2=4|5w>f`abGV^P3G61V$#JG*vK?Ix_{Ll9p$lGl~ok@XjF(CW!hLaDZ0}9sN0cd4mEl-@?mpn;M z?(6)czPJU$qv$*D`jcQX9YgB>kW&ARK>ar=#lpn&zo--|%l|>8SpVa3_5V6rZTxGG zt>K&?PkmNVzR0igY5#TX%3<$(;fJdX(GuXd)7hFUDy@R2eL9nHdLmO=0@^cL%QxaWIf zj$fD(0!7#=594Fn&k*;Kxm1gA@BvE|t-f@6i{H@p)ycW{)~Pg(|9c>D?l`?~;ZZc^ zHVLfHY?R=8oBunD`{DazS)~Ow`LzCdy5+4ATAoOu!`r(+;yc^HVD3zUytIZ1Mo~3k z5yT%4O!LF~a$h{h@9Q=0`!p{?uC!jPo-!T+JooKbpqy#mETVGl`!Wyf-b{SjiuSKV z3iKs&ngfF#eQ6P^{@XEeECY$pgy`P}OH!Woz~kdHk{#f&&sT`_0 z#m;s}^yh2Zy{Hf@B4}pS94q989TgAK4NK%M%a{Io&__$(mOEhePupE)(moqhfQn7> zbgwQASA)o_Oz}{l6-l&WQ}AQ{9WTu6>$LBMNczVoL{#%0R%gyOJh>>9$+IpCnK z;>DAE2g7jwn}2D7_KekAWzB3PdptQA9qH?1PTrP{S~UQ4&Wb%Dk5c5{GghZ~9I`5#>f;X27GM#(7mM zGl~Bo{#14f>+vbo%#x;Kl$F7h=yi4$gkT?CBm`?c1W@lQtvuT712UUaa*i z8BSJZNob6otqlKQjDGBRheM6t=+IcqHa8QLalh30|x4iJ7YJ)3Ea>m}Mke!Jc# zM4G0}fIr*P82+ph%AX}u?R}CQ!0Gv#?PR4{G>FwC`xSH=$Gf8<=)bpmr`e$`^L)H# z$D<}&&?B+N)|~}Tc8wl-Vl^f1gTDprlQH3H$WlD^K<5kA(2b_0KiQD}3h#-sm`7nn zoXrc?AaO^t5<$bG>Ef88oFCr-t;)KVvVlFl!5dudCBv4=m<`!0mW`;bHc0Yk?j?E8 zordMx!73^oO}27vsVX+-8(d9;0*B4a%*r$}o`o+)yz`3>GkqgN@w6%4uj?QSy!n@A zhN!YzhR>K;HNBoQ#?t+wW|rX^Oh{`9wK>Bt9HG3A3XtP|bw9%=+vdslTVEH3sPX}c ziL)23DemA1*2W^*tqymBT&AB#f3@c>~Rj(6WTlg^M5QbIR z(N{8NRwR`8(}~lgMTh9bHD-ED1s^Sxd9=%2gKRk5X9&&!q<1}I){kXa+P7F0h>Ojv z9VSiMVqA?zL{r*I!N5p1`5CKd9RGfj*enLl}ycK56O)sLiT5m9`35 zzYx}BaNm)I%}7i4b|7Q|%9KZF>AT8Z7`*;^;e7<>l`!2hc5C1m3G9H7iy8^+gWY>m zgC#;5$gTZi#^@Umf*1wZV#7Ref!2~Sr@CX^p-wpAV?KdEC>aCO@!Z6VUS<44WIqNk zjV6K(<#Xr|2b3UQX;;9=rRe$Fxfm=tVmehL$Qk6G?H4+>F?6d(3erI^3nRjaz(ui6 zAr4Z`jQ7qHk>VZp3Isz}ZZleBbI{UdPrA~V#sjLcJxLF#L9u(2!=)5&|I)U$VZt9S z7G*Z*Tj#Y;{kARZGdWXq0zso&p#RfxL^&~_EnuLJXO&d@+1U1Szy-gPx596QcT}a) z?7D?1-BhdVQmKZZO-9I@-fY9C0Qlo~C8S3?B*unZ7t*ZjzT|`@H>Deiu&?ga@ASeH z%Q`puiUIB{Wxx!t*sXR8CqH?%v1P-tojQix9$JtODYF?09kv1F=P9WdH;ffxlo?wQH#ZVS5+AXc@V~KbOCj5j0zYE zL(_9f<`EQ43jI zjA*=0V%KPatk5D3oA^1P1#0c45Wf?pQpsPq=ImgN!KiAL{;_V7zX!AYq3Hy#17R-; z0GO=;j!gR;LY13fhou0oTiV-`RjD(@{-D>Gzi_%|H*c_7eB{MHsZiR>+<-g2R< z-|2qcRaf%!?B+ZQ0<=&0%E6$)C@q{}x)J}qypvc*Vcvf$8ZHw_(FAanI9LHp?m15S zrP=0{4fN>JiShNrQy{j?0E4*DVXOm*Uy-Zg`=4j@=~M})Q{#FJ@0A2r{^y2pLqalT zP|#;f8-2a;rnnPcnJi|vofU^rtiooF%^h)g2Iw1qyWDb7VPYrO_y% z$G)wOTS=$>NH&2+%^kh}F}Cd9*b4|MyVIw!nNap&_z=?Gqv@FJF=9Z?lyHm>)v+GZ z_%UsG6|lhWG+u|?i{M&x(x51(XgQq+89TL}e*N{{=2ri-EIzVNHj^q<#o^=f9+6IW1O!*Va-vFyA&G%}_eQ&ACkXT@H`{$^vF zBPIQQQ9Cj3d!@A|P5PN!X!J07vqF9*hMgCV2q}WV1r>dlYY;!;o{T|x>a(xW%m;$Z z5F=1qsNokivow((^(?wDBkc+Ebb3 zIJsvClsbzg`n0C+u55J>r!X(fF8k1LgX&ZlPj$dZe8iHYh9!)R$&feF{(NU53Z061 zyppPvpHnbxp0h^IPwgApIWh#rLZvxfE8CH_Wwg3KSnBGt;R={F16h^^s1{e0Xe77? zh#t+D4PQV^{Y&m3dE^_0?(h1UE(gY#J0Q!G{p@e^AX5t&pZu%Xli9YaOBWgpdAxmcPYZB8+NgU(n+z08EGW}v;L>OS-GDr%N#t2|hh1mibA zm6)>?Qr^Im*!ln;cfDDZRA(=jUYHv@CFd2xV&B}6Slt@vQyq(IGmr_k- zs;?6QsgdcFa0KWeXf(Wri-FCyq%51U*Mo2REi<5lPV^~-suuHWFebK&_cUab*iJlT zk*uyTveIjl{bD3gvI-!Q&@i&%&vi4-J0vVRm&PdWRIdM;dko=gx%EE58bynlY5f2% zm3h)T(&NASrdj*&23p!^MP3&ezhD|^ZTT%%!@Ybz-}NWzRHVOg_D*kFH5Yc3`Q8^b z6`8NLu0kUXMwuLN7J-hY^}!OkJq?yPEdaJQNnk(Xrb%8g9DX;Q3c!N~1k?@E_)$gWd~%YWOBn1NE* zOW65GvHa(C2$9Ydrw*f3GCc*@3-H=!zvh(-TpQR^SiWhN=b_+qJwIj{!r=urIrNr&phbrtbFBtrgRk`~ z8ESd@ROM1k;AL`{cZL>SnTBa(^0BvY{@7@foUHOZ7z7lOR%fQgN-l&HX|0A+$?A9<6t z+uZ&j2ZteQdhQ`I37+9>q25(HG#oTTWOdS+s z(l;Qw5GOh3xCadn+>0$&wKNX6AgoKYqZ6cjB?tCKHbqvTtA7`CO&+L}ko#Q&gOOtn zevl2+!U|2AnouQm`b)IHpPuQ~Fbg##p-TEt`@!gzZWiufAUU9Uh|IcjpmJIJOO-V6aaRNtrN{@cM;Qmr4<*0?LcJ7W1go?C=0r`=>epy5Q z!-{c<-h5JT=`)VH4JC7e6*7VKgHI(9uQ!-{1j(dT<7yH1Ao3(J)+&k>G4zS?1fXRS zTYw4#+<|&P@y48ErW&D_O0gPtYDqZ8c^T+u3+0qEwvtF#x;B2AWzHdpIt?%UOfNFM zuxIZtHsfgoVq#cyQK#*Er5i49IG31a!M>|i<{&FEn?Xv9tdU9Tl-bZhIIB_N5q`2R zDja9LzsUS8m#jSr)*HihD-HlC;dNpPJ3s_;e<#;MuQcUF)(G`dU1h7r4g=1x%dTP4 z_8{r2PBu0r#3kE`l}A_sN={kWCJpgM2Bc6D7?CDlT^G$xj=eMswz0C{L1Ab?n(PS3 zuXP{_S}wuo1i~T=E{!pmYf*1TxE2Iug`*N-d@fh`0)6k9L^3ipjOHWRlWXSN;Zm~` zBe>KjL1{8u6cF;JKf?Y7O!rS0+~7yIY=^W@gCUWVxBBQLXTX>?@F^DmeELyyDLNl( z^*$3ktgB_|gcd*PFRgbtXjFFNLF}L$3VhThuoymh`y#E@?5x`jOq3 zmI*?P`r6j)>aL3ii38;5t81wdM-J+PDB&rIRoMzqiMt{k4w}7ItP{7Ak;16}h@3D) zgQ`CqKtrDT-U>Y8ed$YBpOFjPJ?7GLz8;L#-tW*)Wmr81)IJh&>oBo{WOZe9+13}G zm>y`Xoc*lXn;NXj4Zo2f*(zBl0&;1~Rjg_#bcu32H0%l7a(CPAY;rMvp>J?c+e1oz z`ZAn22_Zs^22y0iEG5V!x1sOx>)+x5 zREk=9d>=zilMp^2rcZPoVjgFA7+TI=pADfw*Ge{;Qi<4U75^!Q1;t(b5n_jxzi57) z?WIfjjT)&GAlO_h~ELa&(!OEZ$b!Lj`I;zbZPrAgXJwSye4zfg@(B*0|O^go{!wbn^ zrv1??c&42&QwQtLDx<>eD9SLExR-PbJ*khYg^}0&nl zu>|xI!kESuMW0aE!)Uewfl>fjUNo1$ zpiE(yn_1kTI1pGSeSpdfj8K~eC+!T(-Hhm$e7lr7Jj+KJy~Vzb=6Xgnac`LPON$1E zr15TE(Y=|TCTyxW(%`l@(v%2Yb;DR@tYr16@elmbgW-!cn&H6BJRMU1mQ)~zJ4Hav z!dQgNuOajS|CVofn%2bHW!jl%SjZwBWjhmb z^s_fr#AEu%W1893W+orvX+D@&=v4QF7>GY?bcHsCOoMm`FDg}aWsBwLHy`}7_EIJz z(ZErSWI9V%LE*o;EEBP7Rvmj<4!dSf>x|W!zt{`k42gl36_lP!4cr5`?O-f5yPeiLH|8z=cfv1I)y^5aE&>@=$#~YE8tmAberk9MMikt~RimBVTv-c5Gf67chMQCCW zX5-q;fI%(T20rphX+7KESNGNT*GMyn|%mT>2AluTRJnD zCaow(ZTCi#tvMzCvmKcweIzVh#cGY3fXK#>h-_(?4UD~_Itx1@p(!nX`K`%=T}}0& zKf@k09(Ritph$EcbyJQQhltPyVtzGk1v%q-`>0Hbx?mPXH1Hsg+`0?n3_Bzpi%A520OZ_;Vsn+CP)D^lNyuEqO~AE0dg(#3PdJ^ z!SZitw@wSJ*CT$go#M$V6Fkz+;uKs*gt9ZQ!{2bN;uX3SzX=dH{jQ?E1U)Jb4Ti#0 zLf8pp(QPacX4n|na4~6w@Ta6pj-eafObF&w(7jmL`MZF&;tm_}7-F&qw-gThID}}e z2Rj1&w7!{Hi$Ocs5z7Y(A^XYDLkE%jbt=VE&k$_%-g{$KGYjONCytQQ2FDY&VxkXd zTGv6RmI{=ge7Bq(FS3Bz%>pfwb5nlkLmx+UV^2P%F6Qkk8R#OY2f1&MxW{hcO%en% z-(liX{tD93ISM&JVS&`3*- z31U;6g&uj8zPuC!{KUc#ow7~u&;fjAlKz$D%QZ4$V~GZOe)QDZWJce9+C@(JS1;k6 zk6$1VEZPY26t473pAifgLTPi{wmsvZNF0BUdb}rt1d?_<1vA-LN&b0q zHOm>x6Sn1S|C4gVM#x~Y$Px1=!(3=5p*bX;Y*IwyO`qbgKEa*RJZ>^YGjWABTxgtC z>(4%R0^ZB2*Bg6P7u8SXp@LHzi^z zSnC@mt#@OnxUK@5lJ$O@h}obH0){BO8M@RfjJd-d%~pj*3r)i%Hid!?GI>IFi7xI6o(ev1GWbKVR&n?^DpvAs_^|LV?Wg41dBru*BW( zp6meF(5@*D)M7RCB1b0l!H$z^vzyilE!m!%Sm@M6o*YDi&wld@F^R|?J3*NSdg4j< z{@#N1hZ{Ad6d@vGh?1_Xk`Zq?OAsUPU8g{tjQxnZ4_<*s6krF4m{GB@Mj8y>6Ao1r zNuAbTlbcge;S?eU@{qOHYu;tnIRtHFykt9X(=MEekI)?T=BR@-*tX}Spx!nW^kQvw zcpdcM{6$YDaYRzu-?e|)Y0z3) zACeUgfGUG8l4#fRVW##ONQ;ZIL_Kgjo)A=2#V+?1daFI!k^2H@Zt1vnuy zNjdx`iByuh1*?cJR|`Z!1LP;+=X6=Hk$M0I=gT-smsgEe{%+guYd|qk&sj@+&Sp~- z^vZ%%?{Vhb&@GD~cQ;f-Wv;3MX80jO4H2#)lRI*tCM;B$)p96nAc=ra^=a= zkQ{Ay2b{%$7x-gjH!FkwwChP!vhO*q~$m2d!M1e6A$)_s6Uqsb-|lp~B6 zYxg0D71+Q3mTu_OHLB=Rk1nX=+?+F~&u-~;VbEYS7CnRCnXQ3FY|Y5ygUFsF8&;Pb zpBpbCjiR@V8=-&DN33O$^Z-u-O8QrcLF5pmQ`{Rkr7vnUf_v=o(tmDf`P+?)`*7+y zT)kVCVyeTj5+K^nk$Gi{zw-MOV4ftnpx=1&CmZ&%AZC;#p=RRTdm|mz!`E9c3fZX4 zI+cpqC~%45aev@I4#}5?L9U>etJ?u=-aLdH{2902WfL6Y?p~rj;wB%A)D%(zCf1oH z)`RJGMr-()4*#YsVbc<$2*vI#pi{*W7md1Ab>QhHLOt0k?!eu4Xp#hZrd;f92MctOR~+2|tNSviZfWRvN_Z#)0Tj$ml$uVxkYvCXlawLh zPaqM5kqOql3!{g_Ld$*{=aF8x?92Cy*)g0Jj3Cnma8v^ySeyroWV#>-mKITOU#zyo zgaiaDxp^t^>q}s{mQev$y+ZOuNV_sAvpmlf$g~MHD52x_R!FI=5_W^ow;FOItXCxb zEZxO}#DbTEY{X!bQ9!1kP@+|Or@Zh3m{=KI25dOa7;i{aVY0K1pb5%?8hnBCQ6Llg z^H@f8U(qAFxyeZrE6{fR1viM*;@ay?(dx?-&i| zSgD@kYR=0AE5fhm()W99+b{W(i^WIVTFPaiq_bcOn z+eym~J?B(Vn`!EPj4s)z2-W>pv7`9)%aSck`?<_Pxa*})_As~EMP;I(jc}?BlCVAq zCD|2NP6I(?Js?7Jb!gx*lTspR#;y{*X5fMns}pFSd}xJU{k7_SD2H*^g4>Nffnz|d z7L{UG$)<)b967z7tBZwf8tXx#J$#fALNkB;3l-aP;}x}U!kqT%DGp$_WARtrL|D1t z^+0rt;m><6)=JtGi0iHw#u$h%HT8WSDt^s<<8nECu(ex zudm>p4`t+nk{SaWHTdK{xtRXP`fo919@6uSNt6jxXV<(`7+!Wo&`B#z)IGl8(-YL_ zjox1t;yd`^8v5Uojeml=GG@SZPsOm-HYg0Nt?h#wu-A|= zIq`F@fB3@u*;&uyw;fh<2Y5}Cirv9s2d>Xvl31vCXK{flOATxc zsLC-&_zT~Wl9QhBl$_t|vTVB(442nJ7~70J2|$h7h**roc6RejjwaLC{LB|h6wx1G z=1p~}rM<*FAG&X%A4$`8xyLt`OWjh5_NH#V_q|Ro@{v|xM+=)0osSFtg^ssL)Mv17 za?X}L1{5(z>PE9I!-%)f%F(~Hk$hV0hc5hn^WB!*{uH-B7FFGl2)p*9CkGu`rzr{7 zDVV=Y#4!q!Y{E_V)rJ+|C9^a>StvK?w*~1o94Z$1eN$6#EO9<;Yt(-Z^Sqb5@^6Fn z19KPwWA58P{Ix%-XEKJ)6opJ38^O>{yZM(0Wc5Y+*3A;hde%@?P7zG z<$a=dOu-AUWoSAB#{BWvcXzapF+>Q4A3LT#U?%ym|{2?9H2C$i*K=8&9#PD$(Js++Il6G!oCUSCSo|r?| z2M6U4Fysvt1hj-{{zN{(kTtsgt1p*DKCxy{5?{m-L=4l#p9|^?wSpc-j%y#i)SHRL zTA@s@jskxxoX}ksniVygzM{}vK0?flk`Aq97I&Q$3lK%``CwSF=L#eIEjnen$1d#B z%a8nNJ4S$rzIk90xnova11hEL$w1FxKG?7CDiB-Qo<>Lb45SJ~q1c9A@)td5W3cha zTnverf>z|j>b`G<@riyrol<;HW}O@hSZL)G7LsGNK3&dO_;dz_k5XzK$pO_RCSY|L zENP(&rIQRBL9Kd`n&Mro&Hb=>Xv^`~33#W90>XHY8yUYq<-|DJ%dt+CHUlGU|Sr&THm zK1@v9D5NNAOBZ?H|AGT#!xs2&;w+kd)1h2w7#bbUU59{du1Z%n9h>q+pm* zSn=Ye8UJVe5=;A=j4KJ*>r{i1Gw3RRg5xQEz4`>w#%2D&u7FKRYOYCXi2IWEbW^t#2c2UAZs3;r!}@7v zSt=n0lzDHl;3KeI6B6==esgkRcH4*oUTHDmF~xGEBF2&+PJ)w}(Xqk)`49prI~h{D z;bR%^fN~Ne?8wwEZ*bb?uxY}28^5-Z3(di>Y5U|>pzvNZEJR6I`!hAuKV$_-e$UDx zCY7t%*Td*DEhG0Pwkzl|j-O2(%HolnCu|~&nlG$1GExs`&!ogU?HD}MuEjSkyZVje zfcS_sghhS)yakcmYoeJHg(qB;6Jz&SBv_+Zw=b_FF>bIO(7CGzx0s`hubKlGO<+ny zR9x=%J9u2-gz^tU;=re=<1k3u9U>*q^7KgvnS<+j|2dO9#C0`LBU7v!XzwDP-mo-l zY;DtdX8EKtP$$6+Y{!=_*}AAiqQbjFnl`5-|IOr&zA#83|7}7pYc)i3+f6wC;zV9I zgh0brIRpe|&U^P2*;}3te*`mCpay2~f~=cA5j@f*~b#*h*fqnVU2WaD&}*MGf8B8`Z!&8J2aACNnJkK z(1bo=-dRAqW^2siC6=(&@DH=%=zN$<6;OpdLFU)j%pT>i@i`im0HRKXx?7OWo0^$l#IumIV+ogismEE0ieWM@7QFTs7X((?xK#ZZ#$REPt}1KDtTuAU5YJ?en2KaiQ>_fwqjghZN-NN+3n z^$7-Bf_*2W% z)TL^_LS8Lv-&ma$-4^J3KP~kTC=abjs=VN~z_d55ZW5B!p8JTiPtSA-mEA=^;~P@q z#6|Me1bw9hTCCMx`}kH2W0L7*)a=w=_e?uGmJygfJc=YxLWk-qbDP_hvN!0W-!SdZ zIWRkad2iO*SNDYt`Yzpz?&DA2_MS+NwO6{*%y~1~V@eP)>!)wc)z>2gpqr#-wh?fc zL@rS3$4dh1i5_L3P3VJnv)wnUaxsW>fzF}EAd-=x>i%Mq;2eW<%aI)sh(eU!AljwO zl!-DOSdKaw3#soe7)`(orzE*~AcoB_1LZRoQ19~HsfILUD6gZtvx^QXE0X$+$AJ{x zDe$eKqe5w2){0{gTEx&8)GaXPU_eOuOEt|Rgp3E18pl}`&N3$Wk^69D2=aou4GzG3 zg>Zs1B{D?GhzeZo#ncCTi{}fe&zSkw-PE8PA2x?xR08FjeQ04gA-GE~Rs)kO5x&&Q zj4r+3Za$09io-{`q<1E&N9p%Lw;?D5omixP$M&=7{;h;cWxJanpi)yda@F{bG@Z88 z6#3RA1k8<&e@0nc9ldFKz{0WNvt0c%fn{(+)a2~VJF2v{*su;69;?vuF~ZzEQ@XME zWSTy*@SK$Z=IB1?I-1e)mP#P)x2nd#)yV~aHh&as0*)IfbeXURO>^D-@KGzNqiP=X zv4>H2@Ge)PN_LE@N`QCr&fn<3Q>A*1_ju7F!@5<{34AjYkVy1V|9jO3|g=pm%w8+{OiX)q4k&q(+ z(&j=DwH=dDJs1qNZ0ql=9>dA68$xQI#aGUZi5# zIt*^Af6^DU5$VOZw@&kpGh2p^f$wTgN(g~U{nW3{DW#z>wkosJ8+BRL?#s@zaP(}x zK|%P1otVe=ysQi4qeiWYmmL+l7x5UEzZ(+AMoeN0i$S!o*BF@qOM2)}Wien$&fPdlf1CNR*D4k<;SaEhY(s{IZ}%KWVuvK#ZIi zxgo3Gr>Y$m^STYrrlygyV?YA2;)b+JZ_?kN&_4TCQw^;ZLLu%CVHUC2@F!4vgb0;4 zKUZZoOx6}Ud>FQeN zrguMZUrE|t`0mhd9pk+5x}HY}MynoiUmbzF#lIx38sof0%)2P~;A4ND?G|?G8yhtQF$bcON81aokCP#m;t}!JkrakNf8B z={DXf>0&Gy!trq0rFE4c_q_dv|3-+qkLwm8t4Z*d9`SX#VAj3mDeoh5)fUE=M~ZV@ z5Jx>=;e1jws(zgyCpG*$bL`ZAO1n#{!S}GcCrzELL{N-(nfs=c`NsJ~-!=UibPJds z&3N81>(%y#|0*w*Jl-iYTI8Fr_Z;#%VZQ#UcKG~9|6K6xbKKx-*W`2(q<~!tPck7} z@my!fw0nndmX7l@3xV%MJMDF*=brZlv9I*Ku%qpB1|CN;lurih0A$eUaLOhbwTiw{fZE_opS!C1 zVn0*n(Z?=7W!7 zY3ea@)q1Yf!*q9%dRz1PifQ-Z`{_q<9fVZxZ9Dz-bUdua^S3@Xy#Hu7hp!zUk!2gj zm`_4C#c@78n80vVH* zO(W+U?&-6qUV|63@EAa6m?kblpqc&Ax&>UVSRkE7#QIR|7$LZKUafLrQU?0@&@gwU ze)eqWtLT@E9k7Nnq#meOkj5Pe!@Cqo1~FoP9oeEdrb4H9at4hqEARf^PC!W}!- zw%{#FPIXXClFC~`N}QhRi0r7>kly8))n?ED%3jC4k$e%6a&qRMj!m&oaUe`1hUjnN zuKjRhgKLgG?r;eZy5Fc-$2mYa)~~n;_e3tm%rF#b!|MTAg>VGXR5%{Pn}mn1_deuI z@bA>)5FmPgC)X&0q-D~~ylMaB$JuP|KpIIF83X2x4I3^Lo^Df(-*?}0s}ciLg0l=t zh2Z7fheykYBvf~C{=ga5m+tj3U(*Mlj@3Wun+Fn26mP}{ZCc(gMVhsmGUB>0|F~02 zf_IQ@)^P@M_)Bw$16xV#QB91&l(uBRw<8BG(LjmV9NV@n^s{__7#8VSGJ9=`ZN)jF zJp~!`IH7HnF4aF7J^kh-6g7@GOQHL7Td?xfr{nvCz?ihHWr(LM!5f)9kqv87UZFx> z1n)4exWccJuAlJp*PO%sG>6eHzx|6MoPKuMv@5IYhd4)WM{%CHg|DgZpF~DKI~DM* z{c%8&6qX6<5MYdrV;x!11{n%3g)>TCjdP-NgLbLO)?>qGI>xNAU6$mC;lxUM8^W3` zI_w`#$YUD;>;FCdJt`y{ii^?5#ZkDVj5|6wQI$Q86z0c>aX?kIyfNZenpB@i*(-)i1+x!@iUUjZWZ8pbO5(R6welnFwH2I{Umx0ps)6V^^1d9u71H3 zZYg10Jn(r%39^7a^V**tdbM$qUFkNB)aDw!M97-B1U z2D>ZHl^G_NCR6#M&kHJT4~U*7B=f;PKT9Al>sBZxaX0Gp*95#=InAREW=|7_?y1*Q z%)QptrtGiwiy~`Hn>E%s}D4k1LOFcB?vu)aGnSh{P(sq!MS~LHv>{0GNrBU*Ww~oRnUpnp(|<$02_Yj zXsZe_**OdkBmoC??F;~x6QvRysjWT2;4*-7`%n0@y(Vmc&xD%lGNJA&?`=TVM>3>R zVw>@E@J!Kb_!Vi=QGDThVCA9V6f2a~>yR^((ERFALTqmB3%`(w%4-TOV&kXVxHt4HUDwYTq<|PfA<;LG$gSfFx^j z;e_8?q~tZGFfcCQ;tmih8HLhIuZ3U^#3zsQW?kvy5Kg{{L z&?sGn=(v{B!PIrz%WXMjV_j7K2-C(!nlphCMRjZ*RW&cy^z!~}wWGJhKRT3dVCv2M zkzW=xt(`?ao&nA}_f6%q&osNO5OAdgysg|^)$=%s48k>BL7l|&40ll$U=4Qs^Z8b} zxffyPAU~z^SbpR5i@JlB1wY31pp$`zZR&B+%6K`7tY-F?$h@4xn{p#XHk);J!vo~M zB?xjKYOIR*E+uWu)Wg9>r|Oi^#O)V~u9wBUDNf=@SF*Q}C+Rk2E&F%iqQqufWLUfA zGRZbBvo@X2?(6?u*%R@gPL;?Eq>&+ojhnDz$yz{T7p)aNW6n9t4w1L#h4$};UVf2K zC)!^;YhZ%w=I}yj$A^ab=$PVrCzK#P81Y(~96r7f3pIcu@Nn=09pI zpjf@$#{4kgc>@PabMEgw+)pVEtb0p(|K(vP#T)hJw5}O5Ls#T|TT33A^m`)J8^fBl z{Wl_nOE5Fzh2eRw)H`ZxsdPTbF^R054C+1?>xpdgycpiQYP(zYo8>vECsdsz8kSdFut|K-N20JXnNZhH zvVD>ru#9c%xednNLBhTUnG)STiW`+e7J5?g1OGhqVaB?USIG)DI3_-kw-Sw=ztiu8 zOe3z=v9On@jBjJ1F3yEj8fGIKbA`xKxBwT2?u?_?@(qD+aQNapW>fTRQrGT==5p!I z8h$&Z8n*%K8!nK-YV{;{M&P^wqjp@GYz+@*DZ}QA5gssw!MB*GxhRQku!Hh%^Zx~Q zK#9MHY*nV}3<f*e=$yOU z9^+!ZglQ7~ce$|+F?g)E}XKKmD!kv7xsobCCz*Uyp`^{wd1SUJZu-?4z8WpCSQ4Pk^ zgkm+99s=AZDep!pMy#zA%?o*I1k0F{2hxWB{2KcgZ6+z}COna z6;F7~jnNiij)jEm-_ay0`8zyik2n~5ShI$`4Ov6Fn{J5XB})^hL=&@#U2Ha0|K2{; z#P^}d5v@^v?x{pQ{j@b#Beo;NhL`Tjgpp4PJRZNA!AoOH4oFoGgKl`W+ngt5muOfo zw}f=pOr^Uc<2@h$N(@ELDwUub3iZzFrJ7`tCceHL!H@@RMqX7B;F@7I>P&A zl&_O_KJdj7jR8Dq-wq{u19zl_FXz@0TPeL4aY--*D7+rdfj6ru*dH7Ix^T1$ zH)c=3e@HK{>R6D4p;9l}7~RuU502IY3ipKDu^t2uKil3=lF7v{c#A>UH}Xix=Lv`^ zAnF7uRHcdDSQesZF?IIkQDG*)jz{FE(-nGXa%8jZFQPG=0l)zDUM92iqE8TfRX#HI zP>3%fxYEY-{SzH9IZEm#Oj#~E`5-7w>5*oY`s0vfP0=xl+!?IiM*DYKnD{x@NS$7| z#ldS+`T@I8eT~#jH+l_hc=RpyA54)Z(HQvDktMzP7B7%2L6#|A`*AY+ls?@QgPG*I zysxf0GN4;iX!IlKNKl^m1+yY`X0ZPTr+e8&M4MK_lG%ysvyZPgnzCUec?LxhcmL z(}qo8%q7cCruxEZOQr`?=-FF!(BS!jnbZX5YA3>ECu-D!n6}Gtau65&jDjG`Gwl+e zixA`5-B+c*PFt~5~y@1*xcX1eoTiOGu?zl1?;Ti z+wEbNR>t1E-DiMIq{SS4v(1;UN_}lo^O0g&v8PCb2sy}@FPSXZurNGoIkwQO=rbil zM-62IBGw^e$RM`i9qxTGiU~js+>gBQq38{5DW$x9v-Ok*k9P{q-Ag-F zvBIt>YQv^yItbfUCoxIMv$@bxzX%JVzS{BkpIX~1UXC|8Q@FhE!{uY_H3PdzaV-xbCyoLNHV zG1|AP`1uFZ6gYgpVt$qfbb_Vbu!30BvHrqEIqbh-$o~HVL;5p${`^|A_9Wo~rE!Cc zcG4EGqF8tLkqSsyO(c^L65*b-zY%_raI*ZhGSJctCSdD5cDn? zEGF&YuB2uuhP`!qm9VJ@32r_LhI|-R{e*QAuuovVcz;I!8-|m0Jn)~Ni*~A1Y9mgl`L|M- zi(gl1NayGUdKNrIu~nF@Hfo{`aOS+Z6KDmE(Fw802cUCRud-`q^q1fow?V3l}#i^Ft3w zxPWiC737k^9lLJ0<$B6eNjKaK`pa~Swb_8_`HQae`HV1u-r zTn$lU;o-L~GX}pFRaBH3MRFqe+#`Z9^?Toea4g>xaov+7 z4`LKb$t+t7?g}gJMUy_el2!C-uM?!(7I|d%rAhvY#{7yh`BKloY^6 zzgAB7^b+KiA}iq9ZnPG0c6Jg5O>a|NqhJrBr>8`8zKrHBMkfG)6lYqC30IjC60(v9 z2jr#pz`B{`7aPOJY&AO!@gs>jpL!;E*j)_7*F(azgRz%Pq9Bnlv;AUukaQrS{qxzH z$XwMve(YTix}E$8kq1$5bT1K{7gpH#$R&3L=e{Kc+HzioQ%MZXi^x{#67axX?gtM> z*8EdLWn{%|qefX|)C*XN?+L-Mn6?!pVT8@YIKc<2nrZ{AIxP@X7C@X2x#(Zh0 ze9LK4WB&3&24ef9acoI1j*@(lSu_AnGm*Y?Cuw9=t0eGk5w2RUN^DY0Pzs8C7mP2G zr%V{MnanTGH;VtMijsfeEjGTG6jg$!ZU|cH$$2$G*sbbW@m3ZS2^u;?PrS4Pwvn~J zvcNL5h535cf)BTZb7J9(2qFcf2f!tJ4)cNc9FBuAxm)qWvKqSXO}`;>`}U3G&2Jdx z$~i4NlAAs2FPs&E@nDM9U*bLCg6V=pIE_Oce!=uY1)NlE4uvqEIgwOyrfg~x-DyUS zq3_e28IpLv$vy-FqyHCNEa%0|n6rXms!{GPQ-*?iNc9;6fmbkeJy_<+Anz`z%5EKTCXkMff(^4JhjoZ-j!p@TaV2X%b z#02C|pD4h`1LK3@3>c?GlW%G$VjH^uU=u#`zYPRq`!63jHaa}>{O|w%5kCHpe<0sO zaUSp>TthZo>5Qkly8U_v-%IV2X=Pzl#*28!bb}WO8Ef=kTqlx*-~q4y_TT&DdCdVS z-D9@a$lwO%?5DvcDzOmK%+D^{1diR3`Ixb+oom#M`Q4_>q1dw3HQJ#XCU`1h!NxjZ zCKXxf$hh82Gy(<1#^N5ST0bXYnb%x4fvznMF~%BwPz{+0d>Oo=4>B_$PNh~UdN`iO zkD?}AVbFG9c6}O9hN9St9*SRZH_vd5!@*|2Oqw=^Bt2YjFtNOHd^A2$+yn>p>R_ln zeUaFW*-;M$NwlKBq9O_Pzp5YMg%v3K=bs1D^c>N_fS{2t9(hVb^22j{g_q_fx)~wU z|D<&=@D8sr_14fN^YvZ50JGusMbPVx8}oHBcPy|9<@PrWF4>u)u%*dYPag~(0fCEv zF`!82os5!I;>8C%d(=~QR!huP;2ldg-{^eCuk&@s_Q1Lm*4!Dx>kHH{dG#14`3#b9 z@%}9ON~QU6WLYvNw*_yOEPVXfM}IhxO%@?~-u(Mw6h4dWPrT?$%p=kGgc>a`Q?@bI zN;_26v5r@x>9v3$aL!|(Q7I?6TW}tEZJzl8TEjo1h%$T$4Y$FjRMF~*e5g&d3O|PIUTh> zXbTw)>G!u$FT=Efha&Lw@W!le;8Jva+imbZZ{JpE*Q>nGdK`K#`eKl`fAS%W^A$K1 zUrf1}Z`}bR@L6hE?YSQ0s?516Y8y7)a*F)^2uDiCYt}UV4yWNn>hJ!oKS-%wqZbaZ z2oC0!iFz0AFPJ;hBoF6{zzN6ujWHC+-CN|7c~2SKJmv8>%x$V6Sx@~N=63nVKr#46 zeT^17yd(}P9?VW%)nK}5Z~Dpx4xMfpk(DJJzYSBdwP3Moh-T4Ag5)K(jsqt?%MVzy z_`}5%3O2Wb+!esKo5)dii`$9B^wqbM8rmI(;6J|xj};ADKD4DA6#CX+=%Q^ym@h6f zzV2rX)-#`;t9gg}>4DXno9rWP`svSFXfbJ!_oUY~#j|d>%C>qDO&J$X1+9N?V!sE- zPPCow4M9=S-NtifA9oa8K?!%DMEoB4w+F}24L;Ji&M+$Lcm@|nVLDVziA}gxT2e8^ zrT=d6M`YrI8XU}&s*ZO%_;_ZWS(k%r$&eZ|={*RD;2`*PnsvO|!8hINm`dTEUF8@` z*p8fygqxHMK0raWc<7!TmUr3^^%z2RM%N@KK_HS-Z7OeaJvr!tzE0t$O#9=lZ`0{? zjmlzI^ixdQE!Q_2h$GM3VPf2HwLDBBJc_=B%+PzQe_N-6xdGsb07#3gyGKZ15xRcn6KK zP>|2NU^DBihlg8i3N}f*&aN1ts3%haQ@&_4jSXSsv9EU;o8xT}-yFt)pE+;)iNt3W zbiToTKH7**(|6toz86&dJH6|xdES0tlf-D85&OO$;$>y+|4v@!6vq_;g7j*jE8M@r z;GnI_L0Eak9tE#j$h9Gb)EydH8Ryo3q30QH2(U5$ zd)0H?ycWVGZH@N6R6f5c44POBCM1FE6g)AC;Hf4W=ebugM>4l!c(EYb=IMGXczpqD z{z$h3B0JJhooiiGKEmEkr||`xY3Cj25EmqA`U?j6nH)?}oblI-;Ug7*smuai%M~!C zxialHiBljzb}QOdfRSlL4#Jc0OzFV*qDvh)CA##kqGu=oS9n*6vn@vq5z936@M#6Xso86>) z2nDv(RAOL;f;4}cRIw`b^tIaPTor?_7poJQtAgf=-AUX8#{Le&F_@k*oXPMj zhm^UOg5S93?HYHivdNPO!C!C;lkejaCKFY@O@D#yHN;SA=-L@LObnOgxr@b^?!D8m zJN!3z>@SRw-SZ+MAAbXkx3jsKz!T61df0>S>|UC$P_$x7R}xM!K}=;j>w(1-Xudin zs+7&D>o%p8?P{ZTPygX|p^{V0;$9|ku5sDtpI;31OO1B#S2EafH*9CG*#|5Ti~>>O zqnbxVFY{4^7~`cSCCCSkzi3ON^Ove1sY20Sf(c;=CKJ(X#e{j>bMG{-!V*c$$~c3- zFn%RWb`7zaxHJpVrdq_43t@(4@g835+!5rw%O{%;^j4vFfYuemu|V9eg_+FCaQR7| z4DTEkh+%5zrN3~HdGTOCysr5(%b-gNYcE5KH1<+gy$rbB)A z0VgatzMdL82k?~qbx&vvI$sQkM9UDxh9&sWqG`c{s?Wu6a=w1f*4i07MK_axsi@M7 zJPwAvYChE=2f#H=!iil7FpjQZAI6tfCdA3&hH1R;nT>;?5%#Hpj+dv6qFY$cU$brflEv)V2W>?MOb~;d#D%mD$9kdEh87hSL2@= zDBzqnNGobTyBDP9V!_*3cBuV*KDfmY6$2IHY_W~F8wz1xG5sCmErz?#IPVrq7G%B0 z(h(lK#~Qq^TReM=k4Beqwh&}_T3pX2YkcIXKPBk$w)Ys67E2f2V^C{a8)uU>CTNLg zlRdCE*@GFPxNGn(J8hg@wmacX#y*B;6Tzr0(b?OK7W#*DXsS2Wza+GRy$-R!Z=Dky9}@nYwfZJKGSh9y6U(!aF?An z&MspoB=~BNpp*64Lm0*w&n^S8e1ND#;+5v9An^^dXOHbwxcAs0o%h&<_a3_#?Xg>f z_L!TvTg+YX4pR@~L+I~Q!5xOTEkf2elQ(~v`iBsWmklMjQX1VIxVY0<>H1+>bb_y< zCCC_c>m+jnd)bR`CysWMc{wqIgHp{3NtnyFUh|3Y+ zmRi!^Fj(1D_f3iBp1)$EaznRlO$G#{UuLm<9hoCA`?`o5E}Ax)u}CK+5Hp6WX@b^1 zarPDj_1pInEpKgB*I=HnsvGT}GbsD`Vr&X8&C1%|8~|s;7jLrqHzMH$nea_|fwvCV z%ihb#jZUg{swMF?VH5&qc6H{@or>%60G-8x5Jg3mTg-`u$7KcGJ6nrv9#NQ4C5qDGjs!v!MKg1B5tMS< zYC69|i8~ESfl{D-*meO39rF$n8ac!D`;Z29;I<7O8`G*heZOHKhw`=NE;v~0=croI zzK2~PFz;RC-ALt2t6eZ_C{!ahEUQUkdfHv0Qh`zp1lw++G=E@BQZCiHuTv)N9mSK| zqO@D2W@`r)Wi;Kp1pd+ITLI?8v}83Alb)5rorG^p)1gP+^{~iP2g#afZDvCA#z(-Z z5;CPmOHw+zY^`jdTDdC4C1{7J6sAuPp*k@u=oteRAd|rD5`n@tYk=;H6(8M8S>+HE z#GIw3Gj2YZ^j9%658U^zIT(1V0Hm!OK{s=-Nm8*#MG;|>@ZtdRXhoL6$)w6%VsN){ zeJTqVzNj>@5tC)0$;?;{MNY;JCh(MNnKl8`@@vzH3zZmG3S}fjEG7Go6P07BxyU^&p zM+a@Pm$vPB@W76&qe+3>ghCp<7nFnJL&&JiCafX(@r0(?OIi$kwV8&jRa zwzWG_v*1W=L5~JgeZa27VHd%uSvug0Ss?J8_P}I9OYeqFa!-wI9L%w@XX@Kj%4U(N zwlPOalhI;h5TLo8b4c6Yi0UgTMt+&`(u4q2#P3+dL7PO6W|K`SY2Q6%;!!BE?J{26 z3-KQKGO;Pi;+8-zj=S2&KV{DRd`*m($4k}4V~Tl?fjRpX2?JQCi7rMT_)Nsc@YwjcHRvg?+eY*2?(Bsy@b+aV z_o}2ds9wQ9*1*}#{CA0=`>$QW-ds$pGSB9sQZBBbhjQX0GRSR@ z&kV)0xuDql3r=FADshDx>BkZ%cL|vpy}MvquuS3Ig^Rg_^4cT>&|gVCjJ{UYW)3ML@d4g(xxKRfJ!&tzqF@8Qz2VL=jAZJ=`EA+KmG>q5qq;EEz@z*^m~u4}ZqvNPev5G*9YsN&arcsv=>se6%0(QmFf5DwLJVdw zkTYc{`L7r|&~DX5>9sKq3DiRlwD32aTW_7FjV8?sW0oV}-ebA>wAp(Q)X(33@4;Fs z2zI6mFw1|RKUpf~m8qg^0UOhtx_P?U*8B?Z=RPd>1{w?ulC!1Hv|6^<#OI5U{&*Y# z=MN1XrRRsZ2XPod{l*qf4Z^?-lFH7u$Y3y^aAVjk3Wrh>(t&qd_}s5)$`8FcpRLB= z)4nOz2WeueUSCf?x#o^|&f9p^ z_1a~j8T?wiNR47P%UH!jy`X5yZ{+>+G|{S3@^kcc91I$*7GM;;yv4okM2on>=<`eO zEc4=ru->w~=Up70Q~kNgxbHZRi&46Jv{1~F z^{At~V`+WZqmYo*i-K$OwpjQr<}(*X@5DVbxGl;DBhr2SBCkBV2PxQVQbhMb*gpn7 z(Nzu*f5Rv>b}zoXq&o^sv~UIUC$RD+`B^&%@y|cN(CvZ_F8DCWy@akn>tA}?rvtAq z;L|+IQ=-yGk9Fc60+#$%j)McfNL<3a6~RRlPRikXMx?g7a1{|B3|}NXHQ@39ZSOW< zlIL-7dQp9^lzmwTi@C>9#sNKWIykrhVmx@28Tq6vNSpTMvfN}3hBNf_bIO2N3oY8e zq!oJS+X2ZKc57cQp)J3TLk1>dSCq~v zid&(3b%g}wi%hx}c#Bnqt#+I&-Oi4Tgaii8{<=`bFO`~_mKxe_nzCrwru#_6+FbwZ zyL6R*#Mt+HRYp@_80Z5GZ;j^mywK8a!S(O8Pm}O?3KY9@$(^!8Kgj8H7+DGpVCXc`6xCIg%7UY!^FwGdLiakiLyGbPf)3GNZ~?^44!a^KNz3i)h=q*w2T3p| zGuxvjbVp;feNZU-IycXDgTgQ_yn`QJjG~(kCNk<3bq?RQgCR79h-i1!y<@vC^}$M- z{Nc%ihIV)u2R2U#^Ok@d-^{f*zwL6*(Y*o=r(@k!F2Lwx71z?8bg-fOCpZ0KtGHUj z(gkxx3J$s8Xpz?KddDH8Em=%u!^5!U-xZW@^3siIX&*TKqHI<8E9+=JSrQvzG;GD< zZ^?&m@DpX+IKzIBon&P2G2J4?Na>PX^~}7;I)dFI$?t~UAmkPaGUvU<6>b2TbDz(= z5Vt=!U>_RdGpGVwM;@q9G2tZ$w z&g&!1(>sSeG+~R`q7`#OJ(%P$n%=f2?N1C{oyJcLCLYe$b^F41!gk*t77BQsvjvYu z5!hl%c0YNyKXyMmE{Ag4zj>N?a;yq=hc8RLn5x8+_-6Z$U>ifZO6@X4^kvSMWp){> zZVCH^Y*89UvD9B-o8G8C39v|Uk+&VhSi^yRv3D>JUBk1He_)F8Lp@*p!ldwRx_*GS z{P#JhhJpaI5ntg6j>lnM;c2ALS9XHK!R)W>1noR+uC#s``MX#FX94;QAK7UXS1HkH z)GgLabb{iX`YSt)c4Ql*Sh%thI0}Qf$}2mKvE7m+J0Y}nJHug0@Z?~+vef#5FXY5q z;`)b5c;b_8^>i6uH0uc-ASA3d%``npYP1L#D2r^4}^hsQ* z^?t=Cc*2hPiceE_wnu(KX4owkCQitVYrk^SOvg)6ViWdiC|7L4lLNh9sc1}v^IW+J z#@rnu(!?=NPzmR?ZD-jnH-QChE=MLfeo}SIOvs%Y>XDiFM$NFygvXyleq|sU~TWJR_M2OnAmCGa-U)uWiXpc+W2ND>GqlZ9hirLXb4ZS7sU~w1hGf zgVE-dnJ&C#rWX@*@|ZBlDK;Tc&9!R(~QpkevbJwpeES-zYgl zN!zEl%?uDOV%o0RsllM4!Ne9-zbzitk)a@Rnr+NxgFwGOzZ8p5Q*d=*SH5n_ruXF3RRW>`lcJ1t3x1ULpvGTy-a~n79Mj~PRQ~(Eq zep_gD&%`i7JS$H-5b3Q_3_*7ad7CPeJ?D0bvYjBZOqKQeIL1vSufHZ!rKr~Q_Q$4a z*k($@4)oaHV*K@~z1MA|-0ho$=pR?7N&I6HWTaI3$*I)1{|d1QpQRBpL53&v4YB5sr zh3mFaZcHoNMtLxbp@%V0PBvMlI%lQu8!Iv(hT%0CWMVA7ceVv`?rUjD*3$-+#0*%2J;-Q&vk?UsM7RqxM zr&L!>Cop>@&{u7nWj4LA-4wmt4g-xcP$mj$YM|NjVwYzoxu)r*_1i_5_T;Ow2T{8n z=68v@PZB;KTZ^xmx4RRzjlH@>Xk<3+_HUv}ci?(W`^HE|c?XsLoGZKZ2RJ)y-f0u1Y%;`<5q4hj$O*?r&AHE`;Te5+>6aQU_T2wh%TQi+ z?C`Kd3HzV7FKXHL$wI|)d+l8s;klpq!u=Or!?sTrN2-Kv>K9Rhm`C=BiygiVzpj%H zy5X_cc<;Een&kW0oOPF`V7rx3{hJmm#3N|k+e_RA%1)7z7-~&$HS?@1gw}JA(P|@%is|UlY?u8^0PIrkpnaE}P$G+gwG`%y(^O8r3k1p9K zFQ#uB*=8QUF}jTTfuVh}Ul&Z;C;N@_uzj*W(nh4&(H>oyz*GoFw!u;76@D9glJv;N z>F;5u7ZczMA&Xp*Lz5oW=!Yg^hwx-;-x#K|AKVhvUX7NVnK<7Z)AmWf*4d)Wlf}%d zrETCeoVR&$V=h_avx$FT<~A;#uYO@h{WcRnz*GLml*>Gsw{ypqn?}}?r52k;wnS~Q zX($)KBR0W{YCHWksf~`9l0*T$vssL4NBPg&7hC25hZ9I{f^NJ0U2UK25@8`WjdA6q zC@u0xNs^n!+zzpln~+1QUO9;djqL$jUTeTDQR(M!tg$94yj*hJff7r3pH+bhgs)12EKR);li4bnU?zBv1yn88PH{Kew& zfK#!gMZxL8Y{3bSzBF$u_e&z9w+K}GbhnI%liH(R!sM7OO3^ymXkmUtCm24vg(+32!=X%# z8TP@x#U=zK)E!)wX_vC2xx}V<{ByV5MDwF#KccLQQ|v(84Ed#{P;9vgPi9ohNkLQP z&@RbM7v6Hyi?N0BU?exqEtXntn%UuwM{dG~Z8i-Y1D}19n~c+TM&E)Hm_m3;z`$0` zwrrf1uig=yY^yqglhc|W!D+PX=4K=1cW(N{R=241FV~>=Yi5@%%u95d+sXKdPE*;T zj_7pAWYOuu{TFGs=!80U=$4Jg8k1zFxq}Oj>@?G^l(N%|n;l4Y!c&6Vf6$gnWsN<; z6Zmm8OiSf(_}~$qM&GBhgs0K=87tvww5d}-7clcf7BX^Q#dok7|t)7~MB1ce#!VsMN00qdff#gYsb7&o)a$^;E# zV|!w22QuVMD|#t?z-U-@oGM>z8#{gCF$rFbEmH#-FlFf4h+PX2v}bNp)*{Mqh6B1y zGojTuaR!6C4&9XhzY=(}+d4LF${Gk=$ad$A7ZwL#NchFQUamu)E3dQecyUn7i#Q{jT{QJ_ZgWcC zy>xVSW9mDA7SIMnp>J><{=gW%n8+4(2rxIY(q8D0*C@IzU7go)Toc`En;ZGeg;Uc$ zGf2!kry||gFY+>}#Hb#9VzQopA54gjl19`7HPydhXaWD)+1nO^%bJ-2I5B}wlQUd= z*ST{8$gqNdTgF+tyd#+RfCVc!T(b2pk!&doOx?nKg5+euQ6LEYm!gMUDGb}^BM~!j zo-Q2CqaO@Y5}xmQk@U0>pZIh2A%&gLQ~WlaQHVXHGm0(myTph-789LSnbVH!BH9c2 zVl+WtzozVq@!;eb*l`MDuNIAjVaK@QqHIp$FXxk3-Vqq`2lW---H6RTjD8)822#ovlv_!8PRxBwA)1f+( z$XSDYHsVrF*%%+%24_#b7!7h)AeWZg0v?R??9Fdv98PYs$^2~|n0eNYGz(XCAzFuX zu*9lHrnz@i5|_D8-)&pxoRswJGS)1x5r@*2X%H3~`t4<8?iq$o;N-=%5sLgkknxY6ywy z9CNBsgjApZFeto*JI;obj64Y=-)4Pax_aP?jR{4E);A2Z!4;oUx`YQT?v6`%SD`xs zrEf$gJ>9hhMgAbOUQ7qZ7yCABm)MpDz?HD9x2SP{Va$$Z1c%}jhNu*O#cEwJv9{8- z*&&FdGh~<80goZ>6m`iJC~y#e(1;I*2*r)dCIDxGLO9p?@XzLZd6iJ&1M^d*hnd3` zQ&jz-&~^=+U8vK6OlH_~M>QXoK6gToT_W1}5%@A17k+jZmG)%plT)-t?)X6w0&W`p zh1*V9b1+C7#OoT9R#AMk3}rHv^>HT!ol0vzmGxIC7i7_t4=K7Wp5TnTbDJt+kc7un5{#n_ zd>V~RIU61%x2|yMJY(|ufaVL^fHh@7Nnzo*RxJ?KovBnjIq=QoIz8+X_utLgoTm?V z=C(ZNtV9P`B&a=yoz~nAaOSdg>e6&i(Es1vyY5<+9A{z%=3hO<@ejjQf~vUko=b)S zle)}sbSEim0FE$do^D=-r@C8BQdH|T#xVT2Uh#cjWaip??W%5$sDX_JSv%w8%6mjc zM8@T`gYbQ~{qMS<3L?4<2>5%1FL2^<5804k;{>6%t6lSuL^s5&vohHv8yACNCP~N} zgfE2G5A!rtpjcc+TWJnED~w%A3`^((A7phx%#1^k7^vvqnCvuYeMs4Z>j?(!M?j0^ zcCa|?PV5t7W1g7piiG5%XuxAl)zjj+hH%waG?VnXjzQMj=WAv|MDPkRoCeg|lld2C2=QjWUSZ zB+C{(CK1>uD^k(a~INlm$~L-4UG8 z6?Anck4>>JJW}!p;=x6wBDvc+`&an$cPD1U|~AAD2rIRO`+1tq{;)6 zl3PA_jVOB`aZwglqMq0&i(WxgAsc0JD7X@2qb#ZW9#?#~OqS4-kc~oKIWXsBqbzmU z?z|ljs+*~35Ya6@G)QDQ59>5cvqj!6j995vUla!YmFz4=3ei$qp37}&k|;j8x3%o~ z$tDDhl(j&k5HeB-ibC{q+-VCd1=N7vg{%}N{giwcPv*L7bJE5VBHf(<1^|sbdh- zTRJOc5UM)JO4+cfQzfGW91r^_iz>vWLKdSwx4}pyH)awiHC9TT)GRwEHP_NPspOVJ;-sRp zYYO~)41%%MoRhM1p*FxtS$QLO#$=wBYOL$;%woxuh|WlnDvK}bDDqL)87W(DD(1;Z z0o|fFFGEx_O74;|h+d`ych<_nh?tU`yc(FPr7VVOfq<#9@?fHN_Q{}K&Q#f`T#6TTp1(P--u!ZnIJOfoEaPeU+i#% zb2<7KgoMs08ER7hZyZzL;LX^hP1ob_;TM2T@&l4yNY%p%ua#Ke_|vJ#KXkY#}E0K2fw zg}Q4u%Dx=3nCW6;M~J#vOAD3|bcPpu#0#}Wcc%3q%NDRC>LDQN4SPZYLXR;fG`|`U z3vSctvAI( za&&+v3s-y>G08-RtUq_|So6z0jSx;m(uxGpgLp9Jd@0iI4Z>~c)TLXEL@%*#9Z|q$ zd8cxHLc+#9bfZ$mZ?`dKUGE-N`^#?9$S%=I(BYgqT$PgaN%C=7WYMA z;o(>pvNBWWV;9W^C?xnHBEK^-cP7LtUCL2R-hf0HJXwNhINXQW5P>QOB~Aui7Fjem zm=F(L8hggqDQtH z5Kh!`%_3)Xf@J_$0P}F*N|9+p9;lEJPXL^Yy}1W-SK(!fsQv*Nv+)JPG#wBS+L)MJ zEM)izEoD7`Oh{p>?3k6_k=YI+U&W8Ihi{CXF3iC~Cy_xz9FkxbmvvcMmMKcW*K*X@ z8F9l~$bn%bW*>I2%t{EOD98}LCyuet(wM^l;3dh5a0s+DKsIm^K(10z`&wxD&e{mz z0E~4`Pd7)Fl8h#0j5fjrMmlN<0^T?GW#Qyx6-rQmvS=*6W?{k5OfuQg31cQ}3J?Zo8e@L##()GT#9EuB9b=)b z=O)}kd=rkXk_wZA3<+@uBrEXU#_$v&(_1VB&Bx-U*`6}lBz)*bLEg&FCRb18_{gb%VWP=f7fDnf{YOo8UpIe3KbZlax;rxlB@=^}&N zHY3nsiD6L;zM~O>QS83)j7^X?aZ|;uXtR=5*(MCiaH5vmZ zfY*WNw@yf=^k(s^wy3)d34bC~hdkkoXN7B0G zSrt2Djqe&}8r%vUqIs$FMzx6{_13syZE<2;Y9ty%qJ_le*9IxPD%^5o=2_gir2!nY zovOw%=zHGe_h7sSNe}&OO_f1@C;O;+pJmR2w~g26lR;*5049bD*h#FnA{`hB%=E^S zFk(81wJf=3fxu?iTHqmw@Vd4>?BNfR0ff>9wD7x(9=wT{a^xY1S_zjv?D!*5mDd;; z8j%p}7KiDRES%er5!5yaVRHzu{i$TrkbxOa(BP@a&TzHKWu@jJH@S8RnOc^z-UJp1 zBV&vfB0Q*PAF(qId-If2#(yCE%EmAPVoz)qJXOxX;3SgDsfKbFqXjEBwjTyARE+?! zr#j>6*$9oroaJ$j2c*zfx@+0A3R&?4=Q`!WU$-M^BnFp5ns?LL3x0!Jg<|*Cc_!`b%;r>4j#iD^_hG)KQNd1ghB{~RzhD}$pTjdC=cv49-*ZITWhhusBGyb9WJ zkCfG+zZR{)i!Nwb7VF1+4t=2}6H>dZ7VO!tl@&7DA;dHtc;&FNDQ``XGUc|FnMK4N z)hpU)pkBsuZi!{)d%z=muhk#i3d1rOq;Rs(M)yjih%tGlt)r$3&(j_5^GsWiRkmGC z%1+bGtvyK9fk^nhrXjCm7Lm#nF9umOIH2s5wkzNBY}cjNg#Oj`JT^@N&)FT(Iq(Hf zcz)MiJ%A(7rAI+Jz)sm`Zoe_^;pz5(&=f(7Vwoy%WCnyvOHY$wWu@H2>zz$Gds0rQ zyKR{^st}FiLK&+NX*PsqzOApze z3bEd@>l6f57QE03J9SLRo|D)ZI-HUWpA76!Rk?7-@c3p(&x|+8No$5y$4-@QB<7Vd zUY>n+A7{}?%AJ&=&_cmZPCgfR)hD3HHl)xMvm+!hS7H+-4n7M64Co*$JZoKVF>@az zDJ**j$hwZk8FKU;w-vb+#w_@95ODSulc%jAHhFftXK@Ym-3v2Bd8=tQEx6EHHD5 z6*&}5OMv~3rE<4Sw*Vw4uyASiScWHzjEI@DoHDhg6B1$3G8zbt8XfN;L|R15G4M@( zj*&B)v+#Irw{wSji#J#d;6IPmP(pKuP<;i}DgkX%I074pi4PmK0!O(@yn{*!MjcW@ zF;??Y#v{!vr>uYm17gokPqTsC&RrB)H8omH9sn30V2GG{Y4pJGNfi0w&WRFoKXo`4 z9Zd8wjNiVB*{H)4oRfAtQpdrAE0ja*OhwZ^o5;VJ1A9ZQ9eEw$;kVfWd!1uM4bj-5 zT@duNv;Y84EZZv~BdFdsdN2`xa15sq<@bHlcyb~GDag@qj#Uw9I%jx5;MM_1+5xfG z4EZ`96FtguQHLwIl_Rct^R9$xu5tAW*by{y|J#~|M|r1x01Iq#h8 z*k&VhX?{S(FLN%T3{{+;B5R>Qw4&!PY80hm&NjBCtZRCKY@F9p-fYYWug%jQ)JGMh zQCz;oBg1*1dXf`W?T+hws8`4t$8~Ef!|qkMPQxy+P%pDiXXYtKb{Rn(%Y$;05zoQ3 z+_oxYPn9T_kb(L=Q5#M_gb3Mb%DdC+o+q-OAa?oI0l}%J1Jkj2EEX9c?U9F?#&>2l zQAsb%p2YxY=_p!u-(z|3ym}Dp9RuwM0)iIIOw+hCOUNjSgGYfI2v&(-0fG!=3n0$o zQGo9n27!|@%8^>=1(JB$Vk6>hiKiJhcw=7ABoRPg+lT5H0I}2pICBu0V$cF9%=&JI zL`mmK7Kc>N9c2-Bvo(Ce(E{pm2drZY9&*~qtWb$3NIGw1Q7T*CNV7C4?6vG`x$+5m zfgslx%PjJPNPOl*o;lel*VD`eIiEssZo87aK&NWFQ`|aI{yHRvosSDD|I@3O8o13- zBNp2Gne>DuOSsd$Y-6#Ta6-n_tMb>&)q9{?;QQyedaV|o)Mg#X6zkm!*}BcU*W?j9 z-#4ui9XF^NjVTFy2tSzS#wii7>VKAEL+HR_Uw>^3l-&^Wqtt)>$9^jI?`|*D_|-m^tvNW+RWGDZ`ucA5f2y!Y8z z-8+R9e1yk}4UbtU<8=|5yQ5r#PJ;|i4@i24clHgIGe@})bA8(?^Xn|ffk8Rft**Op zQ{OajUPRnkkd%IcL{{KtfLlOocp)`Q#o}YMg$J%A_Go#2iRgA_s|#8iuCst7Gc0eK zCZ$kAtBNmRYBCVk>@?1#!4{Xh@gS@a3%S#lt}C3EIJCNy zJKuH|0Q~g10i-2C-`WNk1}C$22lKr)f`j7CH) zg_{RzSD;q!+WaJT%7*VK=@3TaS`c}Mr`-aHTf8L^=BA%-Atj97U+%_ZWBlQ8{vcyQF?TBJi8Me^M0ptuB3h;MEwdog5RlZMMa8X3wDlo z#7|+_4$zLYE=z+!#0c^9P4@(u5k;8SnM8vIDjPIuTwPS6TgT&aw7^z)yQKyp(sIb+ z_Gk(yMw(e*g<(>(K$s`RKG|(f2(-cx#Ilrk=l&<8F-hlu*g_uD<<3^FyP+O30-;=J z`4Ss*-eTvBF>FjcioG?xh(%`J_ffVlXp8BPmkC+sqO0&85_1&3AX#2JK^lC09fB1x z@^88^jIAStSBnW!jW*4wa7=|?AZ(nKkzZq$qw7p21U@-v!EoI)c380vr=8=hcRFI= zwA(&M_zM#mY@cF)vgHE|lOuNDsD&{3$Q?_XUgye}9DAlg_ z2-_!aBeo#X3xm5D3FvnAEEv(wbxDQ0nzT-oS1o4umbG%&X9&?p8S%%WMci(qxNbWk z%eF_RD#DiXqX}rxfjI=@G&agKrkf^$9k!@!)n{Hod3cM?m5ao(^V-@=<3T&27zVk3 zjYRC`+b{qx20)0j^+4{K?8$&2e?(soWM?NUBv-Oc^Q(ldTmh%ipc%yb1CDJt4;By& z^f19f9-Z4|=vD4N!j;!M?TXZyH6(Fk>0UuS?W}O09J16YP(NQlmYFgR^a|;byu!XQ zCRH@WL^;(#grOo&}<=*bdNsVdt;6w;)Q*V zl5?B$VEOrO_BhiJhmTf+VrL-LaosfafxhpaHgfuuj*;hNzvoguNS-73b#Sz>gU7^bt2p)8~$J&5k zSO7acD|cG^L^CkKTy|KWg9KoGcEkrhuz>D)EIyMm!RwZgmjyDXVyc>Q1u<`}od+M; zu}_c;JAa2@K@2r2T`+O{niUnPn5W4gq3iVUvEPiI_O_Jmoi+Q;5dy~y?6s*b5!;IA z)toOYqdDM%01Z5>zlagoqa8f+Ee<_%7c*MydW#qkzEYxWbfz-hIrhv}Cg_bfx*ZXM zv{ZIt<}enfB;y00w!%Yl6B8k%^np!wUKREtrFE*~YUrx5gBrp#!;FjqNFVJ%R9<#n zkagGh&X_Xes}-^nF$lppE0zm+=Wrac!z5ff(x%q0Ojy4xCu~}7mltf4J)?VyUq0dj zqSSFxlT6H*cK&@G}UZlbO5H7%q)90%tDquM73$$9OC0Bw1=P8IKa%=h~E0v}ZA1gQITJ&BE z6w{g5WW}svYb@_^l<@()c$ONBs*T*7f#u@m?q3w;dZVVqT5Zbp#$gruE$mvT{LXWR zCtsRUmcN77VG2x@lRDTnNInZFw=BvzatDXb7J!NSM^6qY6w%xvd)_l_CeU*l;2ON!XnbW z;KQcemmGRvUaGCSJ|e^c>6NI_mAf)!P9?Eexr65C?#V18Pr52-ZK6_Pl3Zf(Jk=$R z;if#}o%;uibSnuHkL?JmziYdeY}>OOHk#?2AdMp9fCQ>x7)uH0VaygeoBoniexj(yk=qIF+PzP9>l3=;jOiY&y9e zETIj{QIuqhsthD=Ogy1;}FpY(-_F)g%rD-_KU42^j>2R1b&-mFp7okb`EY!8%)ymdeG zNqIKo&KjOYv(~j7oNNuqMuiV!6meYxyWB)u9Zk|ZCKZN?lNZWqr%rpxn=;cdtwhMD z?g>yQ};4kzAA;?KETcEl7=mQC|c~CV9rK9E` zmm4`%61s6CC+al(@8;6w`LC^m9E6}Q>kLRtLp62UFoPs$07)01Ix!EVtq%x?rOdmy z`57?+6QkT}6KP5&ZZ<4UjzP!{+}3h+9r1uj|LQGlqIcd00*8(r>|zeESmm8gD{w5; z!5i>BrcwViE0A8|dz~<)+7;Q*87!N0i@tb_6}6PBtCISrDp5u|fBcfnrSBFj1_MWgRG12FoA}qp!roFeH+kC{*M+ zHc+gb*_`4`i%_g=VkriS<<1P3j$*lKIfY`QJWy;vgks);qnP?wP)ws3C??NWN1;-L zGGh{WYV<#QzCy<^CbnG=On`|^=iM?$VSdyFzvx{%cfBMX6X6&Abyxf+0TF(A3yxpj$HcFa#ODgX3X%^@{3(b$u_9RM;|gJoeX{RdJTg`T!*m1(hH3R2 z!Mr%|%K<_!|J>2bJDBLD5e)PyT}+Ly^l2}MUk!FzfCatrH71!f2sG&JX~0wszQN;$gE7$P3@E+IfN6PFL;;>7DIN zeBL83;Q{H43b%fRBx+~KX*_ynAqKX0)G_RvNY&0Ljd+rayH~mUh7;YI(q#G*3Lr`f zw?W$KG#_rAs4SA4wh{&lu z`T+>aWYhJ`%mA34afiZ&tk7LTmCJ%zd1SGpQDw2C>?8R@oW+7IYYjNTpvyw8AMwFB zXbB2TU8s3R43{fY*RrasSR2EKED&9hkpTs*99e`}e{rn0Gb2caWSEqvrSL61B2&I@qSg->IGs7$QSn6mEbGv?8CFTQ@V{xIh>dU56i+Va%srFo;p&} zQ&tapfeE|3OK7NV<*G8saDY`kMk(54!m271%2!#bv4Z3)&pFtV3$G)ACl5nfClS)S zaGpef$LpwIqNxU5I+4KB$VfciWHIbZ%?upa%Y7{lvELzWBhiOGfjR3cdyMi9*|H;z zL#kAOyK+C_jtp;e1~*0Wnt$bZ@V;|orv1pB)lnT^G+jDDriK0DyK>R z62+vZil?nLl<$}3ZWMM!(u6m5uL=Sp7#N!xo&ZwV_I;4e=Q~3BqFz1CQm68w415Lt zj#N%n6M?#%XQul>XD;lflkT1womb^3@2)u;%bEP{ur?A;R(Fk6eDcIf)Mu$&qHDa^ zhWHO^jZuzLNOZL*TaJ)*n59*5dfdcW+uMTDJGuTj&_ATn5-NC(=pda3pY{wp#GF~Q zTLP$}+>}j|7VNX!os`}P3!=1+D#$KIvQ|gPTJ4We;CxqEh z-99H?L#iI5Al7+;u0XL47W|g#5ArYly3vLN!K%?FUb#sb1e{)_OjMr)EroaeM7MXI z;EFo~>IUX@A4E1Xkg}~`#r4MEVMrDi)^c*y>VQ-#vb=@Xsi*Qjx|^T*AbKQPr69!A z6`c4ux?Iw!k`Rv?UEX0d?zF{a>OI&04S@0m-|iaLKaYz%Md~opU}2K<3p|cHnE}Ll z;mlGTQ^DLD7Z>*npGKE*a_M+LHoiRQ>nft>?bqhJk%TW5aui3{v|ou!)kje)mHJwt z=~ndyx-RaabRWl%uWn=MnhV%oPOgX^5Y5wDXpLmk`)J)2ojwZZk>DJ^F7#sWK{K^129nPv}Z5WT3|6Jj+Mx}&9|O$$0m*yd6rHbll=#AEbs3;J0s5CC=VPP z5aO7B?KtM`PaG>j5TS@dTMiT|d>&qqtW@12UZV|;K5OMtJ|WpShC(u5I!Cfm9!NGI zny9znNalS^B=b=?l9l?-lZ|twPkSLfMwMr;qKZK1P69xX&O8KW*^Y90r(zuzuR$MV zsT9ae>Or7|cb@xFHlt=eDe^$s903HG-8it^c+%a7aZ|$b!lyDbfq9zjsuz=-H5{;z zg+{*Q9?~PjL%Id$6~tz;J486<#=T9hrNyWIG*h5rZK5tZS8;?D!&=dOGjNbO*H1N? zW2v-CQ8>Bli_;EDkI@I0MVqPtsdP++u0b~q_F!kC0`NiHrCpLTWu0j0m&;hfh+b@@_MBZNRp!i#_Bo9nLIuDiPl%uMwKbOyV4Qu9@?v#=MQt=?rN zWf0!`G)l3VCb@-!y!*_1b*XW0!kbFEXYb+iWrse{bl*>KFqW2Wcgck2PFB_~1Gi@} zj{2gbIPZHE#&mM5yDpg4T=dzCXaP7Ye6gzx9NXJFPf#lphh1*vO$PhpL`ZXTJ|SA! zG|%e$6_Pa0EZ^%4X?j;CoSqpG6c8TPLSthZ?4b;CV2|SBDr3X}k_5r?!f_yYqg39D zeG6Aj2Sa^IhAxAHL*1?dV0T`J;rlYC7irF5_a@7h>$W9Y!Zy`_{>wTDhoHv4x0!n_2qUxPw%prF# z`keFpdxs4>jnT}ej=ns64`2rl;r6`TZJ0r*n!#5+(Pp1UNrG@#dai-tZS#leAR`!? z$fkD_m_Cwoz^e#MBS*Q4qnHpGw0aA&q!@i{VQfeh1hNuFsdqA%B-=D*8I#{+IH4Ny z@;(~S0n@v)jDK|mF@m_P=0>?@mMb&!ED&CmqlK{1G~N3M%3m{w;49g;cXeIp(^k-T z#4?!{HHrrcK>Xd`zS`+x>aSdVhvt)=(2NvGd)01b4VY?$Ok+&DRvOD1=$_Q3@vcWP zGk$Dg{bD?W``Era`5B-@EKGc)0B~b6*a>CHx&ed6!)fRk2)S z40aSkn8bRgPtzpkdl@zlmB+W}a@ckrZ?|HiKEY5VwYkcD--P`eEw4v84wP|-J^Y{n zw>*Ob&8|1zqVelBFjOK3tVcGgA~2iC@~+`@nYi$2u+wZB<-p}3rR#cu#{#`!FF&pLT-m>ZR*d--rN`4ho^Nk1~n6*~D!g zN%v82Lg_HdP6NVPqYh(Atz=hm8#^EL!VeO=GjxNEv9Vb5AePT}mW6>0 z973-#x5f=esPfg$-GX$w^TfHfnT(MGI~kxwD5|hLP%U)1Nmj?IvSe zTAACBlT00(h-Z8j2(kGB>|9_ z$b&Q4C!{NklYQFbkQD5rKApx^$2JgF>ygsb6XorZDqV4YHuDV|s-X1tlK6Jq3^usa12K(S7Iz?!TRLiw(| zlWn&9v0xOj4WE$8lT%LUAG6pw{hgPSGf#G~w|!-v_868WHmj2|Ij32U15+FV&dD&z zZ!Qq02pz`4JlP0pn*7sFAK<}1?TksV@J}}7Fxe*@_cGb1xQqW9>=SasF6>hp293go zP)^*F#b92Tr{uDtn5Q&7F4FkGB|R}u3uIR(*-aCRhT!5z9ysb(RN^#tm%AenLU9PVr&R(2T3iEpR zg^K&aI*p|z>okhaIt{>Jol<<47S1V&HzVVews&W~$b4Gho5ltyBlC4sE6SM^Zs4Q0ubH=Z%oM zQpO0a40WZdLO?s33Lau4glzY$!X*di13xSZc^}Z~**Yjt6sw}-+hsx5;B+5`(PKaw9i)?_YylXPR%|m6``2bwWuWhnXsaXx| zqwq|zEr!#dWrdujuXN*(JoJ?g2}57mWeQEsW9us=#EAEW5-PF%{Cjz)KT}^>G=Mnt zmHr|ZHRViu^qQn>LHd@3bee+3D>N#$vchs#sV}pLyLfJ-A)14LI;KrxZDA2sTE16V zOX$yeTriu|ChcVZWH?jfTxBb}!8-MoUT%wuf77$0Ds(<6QeCNs<`#y=vIr8TwDbq? zD5a%B9k)0XF}t3`6S?kfQ;kHWrDAorG?bQlY;8$O%Ov~Q_clAMNPW2mSLDnbyrrmQ5Gra6GBy+=wxNl z$>uippCqnHYgy@q(JHl;JkhNTrR9l;zNkx`S#jQW1p9zs*v_L+X&H5271vrOhFq^w zDfmj6;m%s@PK|se!_ZnfKM;h zv_(40%GY=cNY;H!tq&s0+hw17b+en&SqkBL7&=Qw!9FyUq9gZ^T87SYLa4K>!#tBZ z%Q~DwTxVG)+d&OvTFzByy!U*p(6H6Dg0`$?X)HDDNnQse42>niWRW0tc2Wn;$B6co z8Qu{yVg5PGm_JBknPmzXhsH9==sZeenKXjrDo-DxYb?{m8q37&8-tD7DQgWj3R36FUPR>&8Eh2P zl5Wo^MT|4+F8aEkmb8|2usAMM`sAp#Y=dcXwPlylY>?V=mkE@ZBx*fYHi{~PSp)fW zpC%iXiV|Kp8Norh~fkvJ>BualtH!5*bcA_`A z1-WWw@nVqH%5BpFi@O-3IJ96vqFa&za#sV`N9Jc-IH{B*sfm+H&IO5+8s))Br78Wn z26IAoJrXoGqAVJOODB0?s`w(zoZ7$1NyS}kO&=P}J`6Rx=tUM0(@HiKU58mk<(ib3 zg}gmEDd;?1rft6e3n6`Bp9|yko+r?8HAttJb!Mo=jN`ud)h%)%;Tg|^8&7M|IjOOd zgOg%-%gITlIMfYNo9-%ZQ#mZYr@Nk2oK+JUb(=!hV|E^6aZ-a6i<5%>&mAO^uWgn^ zJ@uGH*X%AmrtB66CuNXrVWofxGM?P)x$JsOhg9h?WyvUB3RzJ^XB}B4|B^NCv~JdU zJIPB`;Y)?L>H8G|{t?>8tUWb5a?8-<#FtT|O&jS_BVuiq`c52$seeqfnDLWcto#tCl$i~HSKuHrztX0j6v zdnNTSKZqyV5SL}@-NR2JU6m3(p^LgPX-~&1Cd%@AVb&@G>~bD6li}SHnVIRS3hwO9 zVxzIS4MoD4nfTh=vg9I>l;ZM$;T}4QGQ!4fQiEt~VperPn#-}M;iQuR$8U~?7PLLN zS@HV?Kqnn5GQ$>Ztx=AeKHXvsvdP;H(=T;cuVV#Dm3AsCOrvdc6=cuc_Dy>d@^ZR* z@te3vdSje;l*u<0GC4&~A}l{s6Fvbi6TtAPQp%Sbh}5C`lmh<91FFn+v2+^2(9T1ee9Kds5P@ooBtnW(HY(!+s>_kT1SsS*?`-nlf z@UkH9A#RA%jHXd`sau?47x`zKd$5qog~-^><<|U*E~D)rv~<_s=wp<6WYa9F1Pnao z@J#5ACL;S@ctG2+fdDK!%9VS$TV1-YMEQP31pIlwK(^#A)-mwJUOBJSJW7<5Doo3APGhMyIsfN52HidxM^uDkSPm#^DV^ul? zZNk=#J2lF|>GXs!yU%DLG!K!;KEmq6&g^VKkqzab73Vydvun;n+`rd|a(s#m`HRqa zk$otVheNnaFL(R)LU(ekXTW9up6=q{RDxW^g1GOafB0HQYE~K7!KVTUABhk#M49p! zOwh|Chr@tuawt~|io)n!Y?ay4IflxUQ|06iWZM`D+GYW2xOsqX#34A<=w$NwD2tQT zwZ{rdGR~qL-o|=vGZpCem^&tcTv9J;&a#ht8SVCsb^EQ^~Q(l=7%s26nuphb%g0*_~e2-f30 z0=NOAqKhjA={k$_XJ*297=8qL4*Thr$8=V*!iZ=psgSby*-nfEznp%TO1(zjsMm#2 z6~nWIG2&->lGm_IQt8yO_HivYW!4;!4Ms#SD}=rjR>oDOcY7-{6JZ$%BNEiEn^IC_ zB~;A%KJ%f3Wz<(z%TYs$hYea2l(Wixd_lW~`MfD*+!_2I}P<3nhK_ryv5^)piiHPzA-yl!ey(pRsKdaQpb8XT65?zh3MMfG) za(VJ0COJaSNhAdZ88tTDE|Cs;QU2~*@(3zX_opv*Y=Z`X42|+g%rPK4_cQ8J4?!OB z8+oh{rN}f?aY%piSclbgcpxgKSYpxRL`q*mi%FjRon;(=)I?m}LI-gL6R8gU_;=Cg ztaaG=))j{1R@O}s@`x1>{kDqdvS{Iecrwfhk^67janM5-N!UpeLiYeni5U>~pi47} z4>uYVI8mo{WzdAWuQixD5-nt|rBl!5C%_3^P$)`pKS55TNm`c~PV7uf6<(t1;PT<0 z;YA%VgCcCo=8_}}ZNoj%lOS(xSxbf-UdsJ$ZKFrhO}hwsBr>I4`{mTMYlnl!b4^Wc z(A2cKdQz#Yk~A10h|NO;ik%SnqB=o7F1K9~DTf@y;IN)5}n;i zSqh}c+s@brP}*)?L0$vbL}8(m=qv+e>Kfg|KP360ZzFFHZ0DTJVz6c1q0<)f)+}YP zSBnf%n?yYv1|^dGos z8KF5Q#<@_jxKF(Rb7^y($b5!yi(ckO_kb!(tg#&zknz!Z>nX34&g*G1QKjp^i-{`A zdF@OT6LPOiR2frJpobHC;W14H4^=m6U7UxiifZIcl&PklRvxO#Qp$O#Iwb<|P&Eyf zNg+4otSla?O5S%4sq%emvQSmQ0!Iazhlz!vVsK@ln&_*~v5Cub7HX6S3+0f>LJf#m zsHWWO&O$Zm93~6ZlJ0F!>!lZBzqOn6^OK2clK^;)?q#$fZNOxr24sej$kf0%6V=ig zLm299#i1tah*3j<5uJ%@8=pWY6J=^r=Yle82=PJo+jhe8D&rt9P_>aGcLu6f>LVrt zRm*^YfvVDq`tYi5(>Z}ENA^);8!Q+YsG>W4GEk-Si1|X7M%B18P@_B;r~wfJRXPPw zXQ0ZiD|#?cOlCS5s2asKh=HmKB{4auTEu#YgR0W?I0sc_0W~=&s*)!MRr^To?uZd3 z*NKC&q_C=iYoNMlCk|>U>y{so!9mq24uXTKJD0{;sM;wUOcttko-k*jYNJ-w86?wQ zO_s_@!pdaT#4U9es_MaauuwG&G8Yu5H;c{lsK_|flZ85y(ie3)?yvVciYp6Mo!b`+ zRb>b_S*R*oC&mii2OGZUwcPI(cd$@Z@7>NqRdH#~Le(Zde6Uca$rDEe7OLtMNGwz> z(%=jhs%DxVISW;FlRFDl6Q6e{3sq^S>Ks&+lqC+T2FXN&gQ^NF<{VVrgtB6yMtSg2 z10q(cZlW1trK-XT!Ltgi4-AwXQyQ2%#1n(Ef))}*U7dyInfRG~6S3KO4 zIeSl9g4hw&84Sdypxx@`noJ}H-3R1lflS?1R}85MQ8NS}R0qy#>@#xB&axtd?vn7M zkkA8!#2K4IMTH{V^`0FS;Av+bBRzD@smJ2k8urQ+HVC`ufPQHUejjv!%I9F8I(wJ8XYOsYb4!a|QoYO2&G2~ANLl&Xt8kN7+?pj1YY zaU`Nv;dDf_uv`}~^Y2$kR1ly3h9U}sP9U(EBLY2MwA{O{ za)i{}U1v`xGekW?p`FB%}!0wZ;1^uUksUx}{vWm%GJ%@woEl=@~LSI}w50c<=+j zC>@>(IwXZR9p&WQ-GFSIf5($>3$b(8`^J2svFbt8IyEPm5HtH|2z+&v(}-)yM}-R5}8uB1Tqg^o|705Jt1}Y4`LON z^f~Cy#VM|3v9DT4iQB864XOmc_7Z;CURw##HOGLg8}z_f1PN7K@L~ z975pY;E3c#@;A!+5cdQr8_7?Djl`ULYfP;?SEu1>nd`^U-eY;!)kpQlOv4N?{GJWq zgS7J^Z<#eR9rVUBY|j2S$WF6DWpIqqKyCbc8gZEUz771%5}wS9Fr>l=bfcUWIg^ke z?%Z2Yf&uR%?k>>#C}JCtAkF*H%29c{TN!0-XYXqbEksnLZC@(uLyHHGLyQ7^ToVS{ zDA(c|2aym>bTpuaIPZoS;mmy62~l0&FOcXdt?jx%4(EG_B`_hAs*mmfIe3=ifU9d( z>84^i0qpgfCz^_uuAmRIgCL`JOWG9&BE|DC27!!iGfSvC10{=Yvn$KvS#bBts}4SkrReJO%hB=|V*?0zSs-)kef{qtzW%mLRj8A8F}4Ge zJ^tNBDi2>s=20}9=<=^*&>c|qoi+THjr3kkJ4t#T0s6Xcd6)MpcLN*V#EKNpU11PV zJ6k2Xc#5&ea zbD#u0rsuQ!1P@jPQ4jNJzdHTAXAPK|k(q&0C;Vk>%&5LIKQ2yGVHhi3eDR$k$K^WE z@0sBN;~7PJ)frM8#Ey)9)`I+Z*N6dW(Pj>c3~#$a1~f4KCL`yf9HYFQquTIg-ZXK=*My{y zD(5xIuGXIr2E>>RFn;&w0k_pN-KjxNqx`fQG_8a2ut{Ji25W+&m)9DMx`P(rzpPbZ zRCJvE#u31|9m(x6z}%LiA6zd(|H6Y3<^ptv4x9_b;Kp+WJEQ206+Z8Q?1>n$+!BK~ zneH*xvLG-Mqx)hX6dZl%(q`L zqQ?4FqMW|eNia1&eRZ0t9s-#Q#cs`wOm+sx=n$DYm=Ybgv&Va?i!oS z6j`|cWdndIUrC zba?SQRU6OI*x=$+~4ZK>IJSu1hk(@uyXmuC%cQ|aW6 zqnj)Hbki}a4lybi7BubkPK|<>%LvIlAY$Dae~G761~I0n?{#xYEYs7WR~dc<9aE@< zGHigojOqv-J}b~1qw|3l>tu?{UPr#1LPHblvH63$4QL-pAhFxLv$Z+cK4Sy06@Dz~ zOLKEfb;ht+WYF+}O>;v*UIbAqc+#M#%2scRIwKBIx{BhRC{Q)e4hF8E{TZ4eObsEo zGrTak*1Hxnj55B++^ta~YPWVyJu`b;r@gfAR^ccd-+~4ybX-ciCzO4^Kr*w( zGamy^S)hKP3Y`?Oyup$IhhH*jnzVyi1}3%hcd&Aze-5d;n<7*i5iAgIrz#U?!+=pP z(lqg`?H;GQ(J!mpb1($egtI007>rwg4pVr>f;VLSYRtH0#n6_iGq0VLS*GFamHZBJ z6=aq{CmNI0bbESr#RhhyW=2sb6MK}Clqa(s#s`gOAS=se62`jfa@V=jGfM*v!lrj^ z7!P})zKj|H90FzIQe>1a!Dk+c$YnU45PXodFo=ureuYRisiYY;PtVKQ3(IwA(2ABW zYWpIKRVEdnkG8T(^%;aO$i_rnNM_lM26#TIQC?|J3ITdL?W&JQluC1Wm8Fpd-6!N_ zft2oq!oOM|G(i)D8aHtOn#dlBw0T%RbP?H2X;7nxV#rUotNXlkk?YWJ(PC4O=qX36 z%tRbQhCK2XHzZ-@Wg%n;jpe3Zb0^l1P3|HCpf)Y*e%h7)HS<~>`RiKNG1}g_u}NUj z(T(LW%vBuXW*;g$O*UX-q;#IcTZDxRl~r*EWjlh61qeCztKzZfT9v2~YOl zS3i3d>rQj=t;5GT+TO#%<)HD$l)n1R2)4c7$6iDRHG4k+bh?r9#;D%{k$amUP_dxMM4`5*w%@UM(hXcyfZ$y_b|vJAnQ3Q6 zImyv-02mE(HV~MiX><{iEFOFee085gu@q1iM8N3nUhp~8DHMrohOD;#A$#f)+)9xluwnQ3cA3mI++ql@C)oQ=Ua z;aF&1fHB&ri-MH+EXoLD;xi@We(rWQjk+H4($jBW#jxStYug@06d)Sy19Dsb+76;g zwkAL?UquMRZDW#<7i)()2Gx04>R4VHxhcB?h(q(sUea%G&%ErXk2 z`H&|!%PNtdZd-k}1vthNq3zvT)qtXLs}piG95b>8x2TV9 ziqtV|wA4AukROjm?Wl!FWz$hiCK(@Pq&7LqP!NV#nIl_e`=T=LsUX%PqZ};X@WI8( zIj-fzTsSAl!OFADV(2U;l%scA_$;vHP7g>xOhvGnw#YguO=}JVkO16akzE#Kf&yTR zTnAGqY#A0eAyV_}JzY1sfhH~A zAQJUP{{1L2eS*#rnm}v;Y$7}5JLty2%yMlMofk;uyq5A7Shg^io5$TaaE31=TTQ;W zXDl+Z$D1)c{rULy%UA#SDyYDJp5H%x??jc=Of-?=801KYL^R|3SoFzdL}&iN^do4B#IfKvNLr{q>LDyfySq z_4UvB=N4aocKq37pFO_*ch-E^wvu0e@y2wETgb0}Yk#-sXzc*{M?W>7g`lagKhgKC zy#Cc2lP+W2qK23EvcLX(e8qwGt-pTJ==XyDyWRcQ-z;tZdj9>ZH*bylq?BL(W>kHC zV~;F*Kh^xj?CFcq{pYq$2NgX!x3K2rnA<)wyU@}p0W19CScYiBH`eel-5cx#Vlmb(!jemRbd`a1YAAJhTlN^E6WoX;He>9SYH zd<-AbdOU5hO#^d`>B~`d&STli34EFJI31Ps?=Xgsc0RXv2csHBulQ`)r=QOO{M#Ne zOWYZYA&a;4+12-KwC6HLdZ6lDi#gCwb!QNk4@UiJ4j1q%b)l;`f6RKV;wB6<$imRY)Ov_ zKN%7Nal}R)(W4@9=>{Wa8R3FB|kfT<$t$rGhfghYi6u; zIXYV!&}h@~+0ySXW@n$@kLEy;>&BKbE~}t+d-H)E_b|wrc_bdq{@EK7%GyD*zZf;Y z!ojMc_{yY%vmGd0$0Am{IFCiNNP1zN%**_0w#s95;Ea#trsmggjIGY80gYj&k#G7x z&*bJSXfn$B7IH$o1C5q8%5|&1x8h`OJFV!Qh;L zeoU6l`DC`bY{@U)Ai~i>B>(A+dAS?c^k{QA!J3xC^NacSWi`JX`@DR=v}$Azz5?L- z>>cPhfjS*~2xYB1`f__ie{H0l!?+-wx>6>Pkg^I`-p>l~_9POt8@B@%@j--*?-NV_(wie;6=ZH#1K=Dr()1$=uMp zY%z-t{^*0J@VrUOCf*-@J4Jr@o6qk|i$1>s`tol5!O1)AF|oI{rL9k9TgzJUyrz~f z&#N5_I}+EE|8#EYLIwWtU^C2DA?*v5xLC3+u3!Cno~d6<%$-R7*-C{D=E6J!svn=5 zOJ*MNJBmjxV$A+0m*0PC9q?Fua_-hl*>Ydz^_$tiPi`-Z^GRK5o|b>?-`%d;PQHC~ z@7&)@%U8<*`Sg+q9MI71)h0Vjz4dw;%^97dJw$KydblqVPT(3nWRsf<`(^}^PVmXY zOX}fKPBl06{_S`^{oM$iC4BGue+N%?d4!)QU0lf0mmi=YAe`qj zJP#EF$sYT|O*u;$Cz%P!L-wI__|lHNNf?j}{pa)i`OES1N@hWD)_qWkhnyc*@M=7! zxLI2GYWDoa{P}YA^Kv}d8~Q`jO!aqp3#X$wcXK&nXBj1#&aT&$75L2shi{UP<*JOA ze}!VqV$`j)d;a-~X}e&z2ZM-{@%1?LIDaskGwSs1>FiG~FZypLSh|pqET{u?2ag0x zNS^Up*1nbyf9cAez7mdKQK8UET2Iv%EA|W_^uFDjE^gThNk?dAyx#}0_7nf9!LZ+zz&-a<}eSc|?qy0IO8}c+H z;JV&prZLX;h*9ph`*gPABfk1Xo=|l#hGUP-W_myIaQC8WZ8wbFd9>rcH)uLh+ixXq zBm~>tonNrs3}X+s!C3#p{PTIOZ#7jGdaiCmBKwnti7=VPJctk0?Yop&O4`@E;mf(q zFSpmktt#Y`+bacJ_hYt5)BGQ)-k1}{mObZKk)tm_QhW9bN*QSXU@5py~cLK0>3S= z!Kr7qfOQWh|L+#z?N659e`6mW8?>;%%bjt$K`ol)R!-`Jg`4%hqM?A3u}jU?Jcws) z(w|OzeR%a>XeF0@zSa^L0ksT92O2*l2@p1p)A~1W%$+uD`SlM5HHwn*YQL7(muqE; z1TL0s>qm=Z|M}g|fnlJm6ZkV1UXqQ;0;V3a$6qf*;D=dWLvefO(kHj_Oc&!(j%e+*bcx5t} z8H(@cD<|;&giK(8ntH#XAz1qyKKQWnNK8VjW&xERDI1o)W&^hP7Jnz*jm1V-^9Lk$ z6H;q>fHY@X&*@&1U;Nz$9`2Ro4R)rB)vz>i-&u37Yj zYW(`dry$2IRX~=nv|ek5?@oRR*IJBU8tZ6wh%G=kE@(2aCA(kb2DDJ`HhNMjJv-5mmg zG=hMnfOL1=nZe-bIp=%t``zFD4KsV~z1CjqSx^4gvoklLgT?_v)MLu?Mj-7DD1l(<(MN{ zj5cZJUUu)EmG16p0dc-q5I0@QCoI@m6g=8I z`YO~I6BhgYwYJ-S|7a^P2^I9+xT_l+6eMUWs(cFVJnEit^+mUx$?C@1ze?BUcyd$} zZ?DCq&>7AqRj}Vrv9#Pe9jMqp=y?EP`g{YM;9lB=B#Em2wS{^u$q-QycW0v%Bes{YFzujB$GEESCGqEG>3XvDRDh{E7KJ z{star6KzWD?6A8l(KEiIk%{lTXDgQSdFzchh$X8Fna;jYXgRcfXy6WxSE^YY$nd{n z3^qQsRKiIe^={O0ImMaU%}U(BpXe=nPkG>fv4XqWUQvZMv{e{f(wsXd+ex)*`(?xF zi-l&Un9V6$N#%jXS;om)&oeR~Du=09S(~bvubHiAw9`2O{8S_9z;Ch+F-xD`zZ1Ub zrqoI0)KneNrG37oupR`pmt2r=^^~J>Ksa|+PPzGG^QL1*Sn(p4Ez>YO?r?`R$<%&p z#>L?H06gHysLfFNY{eQH0Tuh|a{p5Q;^5{U)Z!j*Q8jbfCH*8VPRCB9;g!8$6SvRh z&iRS%QonA0`jw};fShOQe6|pOB0qmB|D9!Yvdo4{eoqcpTW-12$^|2w<)hZ_G;cR< zlk@ZC$piHXs!2Q2%brC>{zRqI1H@XCMvcB5pD%G!_5Qo3K72BJR{%_uhzG81wn3bE zReX_h4=p(Xx_wIJGT*Me&CfU5i3U4ndMh8qn;ln~?lEN~ppq^%pRy5`qU@V|IzEyi zmd*?4a5{#97K2jmRTZz3hBG%1~45 z(b4jGb^rVlMuk3sfI2EqfrJW2)`XMH@zj60LsPvypxxqraZ$t4$rEonLMa^&I&{zW zS8aaFnZx&Yd>#_j^4$+RG%&lOb5G39bekWZ!$4r7ys*IDWDVsf$mB1s34-4}g7&IW zJ6m&kqpO~WL-;U#<~a@1M*D$b3jL0}{-kQbCn76u1pjc|UMM#2$ZB$ZDHO=+He=A4M2 z8Mi6tBpJ@^4Q^Yuagll{5z_s|mt%O(Vw@-&j8cruc z>tQUkw`kL4HuSDCf><+`BlZTCEk{L-M;EFyCzrZ>7pHkMo`hW}jXO;)$KzoNhSZM;=udY^L&{2KTkWHZw!-&v z#XLHn*;zeJ&D0k_P(J>=;+h+5Q|i|(c4wfMe&0p+Qq%W{NS4!<_=VAcB=?LN%C zQbK`YW6jbLf2ymolh36|%LHu7$UC2PmeuEc+zb>*BQTM7Q&!YCsuOI6Oe+~N$(lA% z?|Bh47j}MLWeu*1tm|LuTYH)K@W`HcRx)fKbqMLrFuug``*V`dg?y8hdmtxxk~YtZi-KI zLk7m!V{O3Mu)3=-lb+0& zSipbCuNy}HkbS@jc630n2xlyfd&0#hLR2W{yt$R75GM=0Wl_cBtDFkMk|3P}8S|$- z{fsCnulfxZY3ib@Vb*1P3-1r9x>URTax2ay537y03)3l^*qzth4X%vRQukn8&)RXh z6pPi-20jXs8L<24d0EqM4Sj6)RCFF-ozKu(F1p-PwV_isFFa5bD_y{+nK^zmC2f~@ zT#@6of#L8`lxN?2r*@hBq-w4?@8$9wW68@#OUPtKB8K z)-Jt4UsP4C=h9bqS1$ZAqd?9C#w4JoWUj7W^3rJYQr%uM3ukIC_k;tT3lHzTy$oOf zYN+7}^4aC1-s*ChY@R}4q-Fq9-D3>%n6Nxa_*x1GFwv! zEA8s_T8}F*4HMJ)vYxr9+4gi@EN!awlASuC=+>Rcb`FcCjbmusvD!OfY&dB0KAx}t z?8YUoP4Ga=yom4XYn#~lc0f(q1`Is>LY?sgYe(Zl9Ks&<(wA~LKC5cI>5pztPc|Of zdL`@h2%3mIrT#VqPeQWu#2dh&Gmc}o80I076%%kUO7Fs)^5ktAZ)zI>ul$z}G`T$d zwT0P@TkWs5yHECgPpzth-As6%)OnuuSLR|cJSlGv53@yAVtn;_g!f$M02O_rSrI+z z0%mB>$k9(Mz6n>gzCmrHW2onfV8X-4MXKA`-<|0R1maD6^M(8iw5L9}^w=BOmR zYbem*tC}1?vdjiW(bexW$stWp%s5O?8ijRIuEj6F!aYULfX%O2Sg}pI+M32Wj|WnN z6(XN7nN(&Gyzh%sCwzNeIJzw}%|!pAoYzK|IkBm}@|DumORs{{n8^jtGcIEn8xEvw zULG^^8I8y_-m0-NfuJQ;py&Y3te;$%-?3#=#`Bh9<%)M0day}`tt1LNxLC!JE> zw%Da9l%OBR^O4r5{WN&-qIdoXZuAt5cA?d#RBQJ{u)@VBs~&1t(=y9Oqk)crB)+dM zppbYoT9s-gc?bAFXDe^pmE`WaPSjUk9(S~A^SM)^xunGtWoXNK<`0Z69lK=Iov}n` zt*}F%8iVS&`gPFu_x9L$js(58ZHn@IgN|2@ypG5KcMQ2Z?y^YeX2_fSkJ3=TacmDq`K;yyEo_WozgihbGvgV z26*($-$Qe~yC%i+VLYZ=DOsn7`@3w;^oFodO0kWD^Kazr`xiJHz~tJy%frlw0)fSw z%O)g3+YzgoRvhoSQx-z#+T2`YYic*3qH36Z-Oml(^?6T=n%~hg6eCQHw>}f7d~_#% z(3^XQV)+aQ;N+DFcX-#N1!?l$^ZmOqjH8QK$>~vxR8%JKCa=z$TJhVTG?~fU%`^>) z_%-8A1}@n)6t1ZhQZ6lKZd;^VG$=G1uo#rG-{U% zXXAwRjF7y02S|+e!S+u&BW`@=ayrul)TMM_Y20t*bjTHrUY|Ra-WKuipMvZ1{D|CH z75>T3PfbS_BhIfpV`E~-M5L^rL2lslgRGaIooUx#y=C5P&D8h3v>av)KJbtA4%jPQ zP%CX93m|~5ipJ*1sDgK?1gKe{vK`n-ms=p$O3W7FZVb|X5()QT%N_>(I52w&UjmZL zR%TWGVnyB9Ga*;ayERYbNGd-OsXmk)A$kJX>Y17PpeWsvXiX3tb%feQ8@?JdC9oGH zsijM$i;yq@dZZ2@!^V$CkOuWNupgBo#^XLlYQkRIa{m~BG$%`QO$3#1SA4sQERMMF zjtkbLA^#RP%s{|yk(;ELX|y|8^b9)at2%06yI>Pe)DZR=VfOKB$9rSuy5I}!6HfR% z5&a!)ab&kD0PMzsm3{G7i#c^vZI>|xmoLUGBJOU%HgU-H7ATAq2yA{9<+n0+!oDo% zMyDtn=%4E0gdT`nH+>bq>kdp&J2fSiD&c#yVsYoCN6db?7WtTTdurO*v~@2@u8%4v z>&$Zt=Y_qVbdvJ_RH#2_qK z>u_n)u!-ZsG*RaeHk{3*d~CtlOcZ=jwA9aE88lr{oUBQhI`@R2&%Wd? zZf$rZW4uXOdvay(PX4k*Q%!^BhkMAf1L0k%yKdv4$7|QPJl7ZegCY*&l+Lwd?i?S@ z^da2J*L)FiSYh~Hy{U$OK$VX+`FX(G_`aiC)xGpO1JwlB9kb#KYGIzv0awKg^BQrU z^r^b@ZAKx}Wp{|%OF#9IU%>M5qI{fVT56hqzBAr<`|13tK~`#%$^yHFAyU%@6l`62 zxVn)*;2u3{VY-Eii<@0F4o?5uC9cyB{1O{P1J+85j;e6Xh~-clqf0(V6no5Tph zIbiRntOWW7Kk_^I+Tu7L%2!yo2OnUD>E5u`lrq2{&HkRVaH7I(qT==T;bpq;PT$h8 z$uQ2QK?K~GirttTUK5Y@>QU@G*Xt?#m@?kLV8^BU$ifE!!S44x9Z_cURR(Tdv7dQ} z`bOC}S$%a(iMbHv{1{obu|)f|n3L!#xTkhgzf?N;fUH%w`w7nTu_rI9isw(n0-t7X zezE2IM#C)Iuf?d@ZyJwD^5T|j%giy}!z*_(YELSj*^MC`K9tMwyKa-yBy0E`GBm5- zS_sY$sOu*gyQ+zMA4{LYp2=RuMp)miMv0$E#bocCs-8g;7?a@>HJ3h*s@PZ{4aE&u z^M+d2-!LBW@p?VcAn;oS!q1e%N*B9^4VzTXtdaxjZ!BpZS=s3;OF#Z>r5d>sU15KO4u3 zucm6M576d@Xi^o&1U z_hR(?WbDoAOj+*Y$tf~sVR#80&g1t!m)+;9GyUm4Zpw^#uZ8GzR~dNEO$B|vy(a&( zU!73t`0)N@c&oE`{}J8t!tHxYVy2e~@A!(pade1?<(2AU3sahpC-8ZY^%tNj{#dhfuu0rY0zTCkf70Nzr7PR>swpjb% zefuet4KR4RK6r@zoRlTrdB|=Do@A&@ouzA`emW>U^iE=5Cbwn=|4W)GSoeY$O&Z2W zqXOxaA*^A0L+DXRgGB=;5i{dXS0Q6JR_CWO&i6v}a#|m1 zxxawe#qYz3@V=2*_TJSYvj2Wo?^7JXe0XTNQE$#9#ybOj9G6!zKIc6Pg|paV{(HaLr#e zmXtWl+G3+oTIndgJJ&x=s0>ic4Rlhgq{<{;&33;$saf7T;S}bdJ&!K#VS69`q~YVn zQo?hS&0=lW!`lP2MW!A>>+u;$JMew*_jQQEx1KK^7$~5<;v#AbE=(iXV{N4O*iHqw zLbH^ZPp)dsB%?pw(tO}K<#*7#ANS@l>V22Jy`Gc3h^785t;_R`4Y}K^n%<4c{8wv6 zfpW|Jy1L$nJU-q)pT>0lCT4HH6g(MrxA&NVSNz%h9;Bg4aR3tosp^&@P)lu<<8yNq zB*$mz`j`0$4reEeUlVE?Qs8{V;KkAol40;a+C7+j8V)Za!w%1Mp-Cv-u4W@%uuAdm z;lkuI38!=SwKh%D6oxzmZV|R!CeyhvvEz?R!na=WE=UAAek}v$WVYxIzRr!~cs5dm zr`o%oCP9%`6Xb)OtNNm2dY(PgeNhj7;VPj^$NQ1tY~D^)(WP!%*>gW5YeNS|dn0`- zBv8rbi8&H0D=8x>q`(9Ovj4ow`TZ&n4?x<;+QiY6l#LN|Nf97wX6a~TPYMvV)OR!z zHZrg=G~(k!`rfB&N{5D~19lC%_fZi?1T!_stFu6M@o@^|(B+i+yyc|o8zLMro&#cSns+u2^ zhVyM)lx8pabh#a_p1|QW^ZSbn&{RyMY`$}A^taJjeT*Or`XBWtTN~TX%H*yEBYI-@ zV=Erq<&UtidAn`y3Uy!qExSJ2!UP=XD`GEM3g0(J%y=NvvSxoUCai-ees^|J}jJtxsIVofp8IQK4ZHM5wqRf$i@cuAUR^5jro z1cf|+@m#~%P2qMU@t9;+PWU}(^*74}b4RQw4KT2CVc05T!?thV_^Z3R8m(_zpDsn; zZOij(xcvk;sQq-jSf|LrhnT&jQS%TP{Jzc%?gFSPUx9V zyjM{r?68hlhv377{^YHraySF?Tb)aI&9=;i6~(sC%<*gS5=|$pefA~rVBk(wRbT@P zShcb%%qw1y`+WdPUC7Hv+H|-EmZcM#YClyDeJ$RomCb_ZUE-|X+enmvu6|Zbc*uN9 zngG4R$h5}t_WZYUIzDQ&8e%83>7M4sK_u(W3T72o0-C|S3p2QiUby8uZ7T{NmT&(|IUXC6agxneJr-%6?8&7*00zq?VzWWOk1s}6cb5R)}!pg7%#xwYe!C#JfY z&BIje9707Z$(V!(ur6+9s1zd;s53EE9taP(D$d`AwY#wgh;qck^O@a3sTq=KVLxii z5b;|Gm;=zMX}v&FCTMgNKa;~s4TyiIAy8exz41~EgiMw6Y?lV8DbQE>*_2T`5~gvs zl2Vh)pK({wyI{X9u4p+0y3Tk)`^1^!v+C0x_jEC8`t0?=_hPTK zLT5yi0V3pXHGB5Z6p^TmGtA9f{rN~JP6>qDi4LLYV%GGP=3ylt%|koevt~kN5ZD`| zpHDpKuaq^y>Uq+6v^H24>L9E*5h{KP4`(58ITx|M=Y(#{B&byxy|?X^d0C%C2``d$ zFO5~RMg5KzhRADpdse(x=U4$>;^Go-@inh?v}Bm*!JnQXv?I{CSEd*$HCuP9iy1n< z*ER9BrkYJDiG<$sJvKK9FC#Y#ui2BYYaV*l-(xnu+UC|ou*tv2Fr=c7#0ULQF~78y z+8H1A*`Z**wKu!P%Xe9%!y&o08&J5S;>}@My4|1FyW-Z;c3F{$?}QjswK8{YaB_yF z#G7*>l7*!79hd?G1Hw~S&aI^p^A|a1)N^b$*LzT8iEK>% z$^~R~{C4UdFbOw-_reNCu}77+o)Abml%(k^`t@`>%s88SnD)e*y`{o2eYP!xNGG#(FD%peY3a3YjWgr% z!D9NV`|t6hN%IKNhZmNLDi1wkxeR^a_n2{y_RX5$A%NMA1i?*GkWY)8IEiI$HN~N~ z&Veml$-+U8F0#+3Z=&Z#gC+Jqm8SP!hQ{}J@y$mktYx!w_?f zZ!In^_9TGF{faPtN{@YD`s^pCml!H;!@@e>bJ9-%s#KwK70%0 zk#Gy0vU;tFo8SbOq_n`5naW(DBY0j=Ek@_0;!A0u78y@MZrq&8E1}cq`Zba@m?irs^J0Vbe3OOVRJ)eWNbAJAeSJlxT`jI z#L$^+)rHG6K-m85_3o-~dy=Sk?ptHhv^la07XfHLU&`CChP*XKqu@X#S3E%L9tegON|F3Vk~r3|=14{z%xQvXVI3k|t!@)w$4R4K zr1bdRY2e5mpf8OSqb%ut8|EVO^0dR_8=1DP8>N5G(%C>$$v|k5KxrI7*CwA}cNh zpB$z?GE+T5C(lEobK>Vt4|l6tWq?Xxau344%!8Gg{j|;T00~BgZ}w5*Kn#x|p8QMh zFt3fW7lbrV-2ohKxRzMOR?csUlp-cp*hrGeI?AGQC#xLy6J*B)vWGk9&av2|^_rEp z_uQtrX@Y$7N~>jCR|H~0U9<}*IEKRX4#=0tjABwO%MZT@Aqb26#<*2foqU-rAePkr zaNw>R@U<`bz9{JF9)ZW4D_)v%>$$P-yxNk@ZW*F)u(OW{X5?HY9T<>lA9QOv8zXfg zZ$V$3VCgS3C)!kDFUy8X;fQAj@#6|9v~&?~>3tgjp0M->w4vQiGS{Py!Vx}nFDyUC z@=D)F`AUdz%oT=BiG>aSRu&m6*7dW3$r*h;1N>M_WqsSp0UAvcaLUwrnK3| z9liWuKy?^V-r&MEu2&*q6|#|OOOc*wn-5i^jBPBzWXV6ktH!2AOW{0sHDd&mhb>#% z@zu%&I;MFw^sJEUf?my9uGzfz>WQ+{W^aX8PNj1Tsl$Dc}l!Jvy8wpftZ)ELA$_z%TNB~76 z2OB4Q10x3zh?TduF;Fsc)C9;2i;@DAja(f;%|%=t#grUDIF^)&;(UYK33oj`dFEM5c7*Z=IaI^ znt$MWFcbbi63BLwK=wZgWCaWICI?x;EdPH_;2)A@yU97Wzu_F~Pig-U?N7Quf&i%; zDMaTSNC8r2h7P2fNY@jAD1ago>$R>yCZmX?O$w5T6G(+vz}oY@KQI9|<_T(|@2GES zWAdZl@7gM3@Jnrx0CMs&q(DBt?;}C9_mRjDj7Ut^3pzz0BNFgOkpl?`u>^o32h#TfkPQh45iUTHi4A0$AYv3jMHVC`2qOTB zKo%t6_aYM$5)*{QpsP$sKuGZy0T3nrLBJp6LA3fu?f*y~3nvl_L~sB_7Iq{S$W%c^ zRwNdPrGkpgNGuRW0u-5EFADDDyvd57F))wKt^t?|nkl;QL*I`VK~57YGn~tRST! zLMtRABLQRtfG-IfIT+ZR**ei&7S5k94)CZ*Y%E|sWQW)}D+gFp!7mOb4sZmp z1|=}etW7|tplgZ%C8sBj;3xy08_2GHm@uUFJC7jK{&61w%(0&*s%F*#)(&Pr&xOs5 zjg3GN2^4}fL52aaa?<|QC&cD{=evmLV>vZpT4ggUBL{j#8!LV5-bzu(7d2-jFhA#$f8fW$+s^E(hmzJ5U|R_cEvsl+3zr2fiO%W&_p#xQ~;C zF91n8Ob`!RO#IJLvtr?&n;8PzJ95aUXc}A7yagKV|SA zavgln^?jgT{-Utg9_^nL7F_$kRak(r8Nk>QKE9vnLG1`2Mk^_rh=**;9n$tzav{uQEUp*sP^EPEp>!x@fmQ5i2KqaR z>c=+AWT$gXk^NdzO1=+`H+en>NU33xlGyFG-|Hv{K2KdmEPE!suZpR=72-*oF}a+a zsKC>g?LNGYayv|l#kYGPAU{UYrOzzL@G5QOZuq7tm-d^tib+lzaPd^1b3;iwO5aft z!4ZCnjkG@~)amHNyllh~qQjbL<=ckzotncVexlsRTofF5YYg6NhNjmKkW26 zpeWlswl)JNNkIq|Bof7Iu=u;z1hW3JT$W#6la+(@KU9;SYV}LOu1iSFOq_pFo9i(4 zPih0M{a>mLXf98jEG>;3kw7!CwFh~!n>zEW|DUl&N=`vlQsleO6ST23{GFBGISKa5 zzcY@7@fYKOtiYcx4`PZCR|PWH|G_nZc?UMpAD`fRfAaH&L;B%JAkGQwSiZXfW{?BA zzMqlwhm!$C9Z-vFX9jUZAcyqh{_CqhM*xon8U^AcKrRd7fW9ApIv~*bwUY$*1ulWz zFt`l53*z*y9T%7q$UWCJkP#vMes^p?$Naz4Dj?%ud=H4re~okhpiK~f_Pfm}NXm(- zNI`6d<99(rg84s~$PGa=Gyjk?5(fm2{+QQa&#tesG6VmZ?H}zxEr5({%zrVIYoPlN zQ{%XS^Zr{vzzDE1vvzVoVguM(IyqdIe;E%G3&6q5%FI&V9t2(i`u6rVF26fq2OCVUl9>$WodD+&{=<76@1eef}5X-~j8`ck=!X6oA0>FHj&?ch{d0Woi%m(tleG4-HuxPvcc3KN=yt zQS&oFywf8}C@x11spYzu{!$Wam`MbCl)JiEEoz^hs#L*Jyfm$(`+!v5;abXLr=Zhy zS$KZ7fana9=+8eQxciyKO^F!aF-fH;(r-RdSQAUzLi%CILAoQ{0|&0PFNyNlPH`6r z(XZdNIbql$Kjm0@T_aATm+0N(x~zoc90J%=S3LU@3_uo^zso>KR{62IJjAiF{ULtPY;TsYef1kLVnz*2ZD6P1W zrL&QvnSuWAlV|=H;KO!fuAIMs4>(l*<~pv=Ar9mpYr$>6ZVDX!SZ{LcKXoRM+`u36 z(-0FDRs;!FM&eJGdcAD?TkB%G5wbW~emaw%F7>-JWM>8Yi$7l+U@b#pV+V7O0|HOj zfH$Gse>x|K2mgIes){1&0xDpK@i)u+e{ql?o%p%D{}m=6E1*ATaD4>~lR%|^aQ#2; z`iJ^!*aP~!q5J>o%pp0Q-)Al*Bq}Z>3^CI`eI=Nhf50DXzb5_*e}GT}#|^OfLyG?} zmz#41GP411Oo^29dgy-$DUjOlGx=}L`6kTxCqw~Bef`cc5mhAtNo9!s|G_clfAM2% z?7vucL;pEBe?p2M{DK^TjO?HaBo1~k7639r@~a%o;H>`7e9C`_J2}C~`}-{ZB?hsx z{v`%+-fbgATX%!ypACuaiWXU5VZacP;Pcflp+Z4eAa6nqP9^WiXQ|_UgU=K`HuyQ9 z`@Z{uU%+!GuGZD6oLh2?n!$LT6S?JOT%+VLVfSlGjM845_P*{ z5sCELkvStxagg9X8pnkT7i){*3ps{+IgKIG{jZ zu|UBf-t|*Uk=gdE99y_k=udd+mVZVhNG|qw!70c~D#%`=pue&5>xJO2^(lmF|DgOg zl6p6k|GQ;_nEk7Ct>fSY16Zj4i6Q)TZ9&TUuZcKF?f=pczAVXx4%N~ze28m zMBR{F_wTHh5*1ce61=g7l>nvq%?y4Ig^)buKk%6CMh*Z7WcwK}z{|~RuKw-kf576u zT>}2KPe?D2mTux`Crf}%MEl2D*piE z9RF2hhX9J-r6w&YD=sJZU21vDl&@dcIocm*kRwRGH?;s<1}7T8(e=mm>qz_K zDi~vZulXL`Z)gXk2Hf&mH$kQU!b?MThklocx`c|X7$~C#+P5_`vj4+;{zVudzw{HC z09l!Sstemsw%laM^;Pia_czjy@{d;6Ex>0#YHl7u!0h|I*Y!W{`gQz%|Nmf~pjMz3 zKl=JFju1Nj=N^91_4kVSZ}lLm{tNL!Hi>R}YH-Hk*CrA~w6gkEMt`%_BnaBs2W{-r zGlACj92}rT8<0&KoLV+0NVJ0colHc4Ac>5{|fYo02M$0AOw&F$OAxT z4^RUI3u*|lAS7YLOv(mP!C$*Lkn``;{1a<{M!dP9B=j>W&dSby1AG`Mdsz}J;`4Vt zJF9$F3dJN-yV=JW@PTANSm~WcNhw2Q=D;nh6QspAWX^j6iVt55b6C$ulo8E*ad5fh znLH`RWH(EhFdKRc3yo23YFfZ0lP~g!vfP|h8QW^ek86e3A*yyP?>)&R$-{<+4gF{5 zd}+(sZ$9);rOH;ldR615>!rPNTzrb0T3aD~kx5*>NkSVcMw20l`gk$B>KFzY7&l->qWsZ*uPxXk1|V&Lf3M8$AF)?CnmpGajE5gV<#%#*R<@UU#e>$$meZQZSb_W9^^(B7kC0sE@@jfMBKT!zxfPMfcz z+1ZZAN3Q-Q1>KYivjE9IrCr5@Ha{aB?*6}=%0q+8EwLYSyF27t3#Rfe! znIi82?RV*mYxd&6OLWT52CJL^d(>rLj)STT*U2rF>#a5WW_xfA9tm^_4tY$Xi%@7z z2;;M8>)C0(RsmWof8)<^RI?9KvBkARUE$|Zrr%-bi#&G|U<#3F|ngG0&K{Ivq--YhU0N(tTYri8o>BrUu@P z6dXUpFpuXj2gv}xixY7trbr2EjuFB}W7{ZwJP zb9fzirt}>C9_ofmBXrK?Q{?K+VYBmN{vFY!-HI*#)4KzxK2vXAvAsZOcSWqj5?^7I zAv_uNA)>ZlO%Pqw;<~B`ZdVw)c5?L@harQo;D=C$2N?pLa_ZCZDa<}Z` zttkciwC`Ip4@Y8m!K-^Gxyoixs@W1&2y&4Jb|Cmy<>b9TeofH?|7|OX0M~=yqd#}= zhICJI|JgM3TV6fV!g;TeNAaZfFFSB|k8<~P(`zbD8ucp_F9z`vqvFB|aghV4YJ(1n z3-*NHeD2*pXgHVUeFtFI3+t(l?}$^?zvHEJ_0WpBfc}aiCl<;(T4K)*O6#iMFr=X_ z?J8080sL4sVTRhS59c|4HtnWnM_f?yiV#s-k)d0zkO2qah`JnDQHN?qStMQ)^JfSND;g{_a>BBq4~L> zJ*jhFhvKD$45ZI)WDmI#WMB*3^=rI^$Xv*x>UK!A3>2{P@Kt;1+odJz$0_Kk(;Fqy zkLbXNn(apJr-;!4@5P2I?$rzY{IKnI2-@A}33&An6g7@mrqdr+#dPsJwIOI5{=gJ4 z_*T=-Uged4W<~I)ruiv~`^OV=0Uq{TiSd+NSaRBG?<26?RsEH0u~k$|?04AvHD-cE zINa=CGuFh`qF^Yh&DIOr2E0k_M`_q*%h1^zQD!^Qw~TrQpqAR9bkkD5`#e}KIvzci z_!(-%Az~`u#OVC-hHY70$FSrFG1RdQxRIfz?QTyN+>gLfn9uVu>Q)R<;`rsC+Jnxs z`e|2W7P+%?+4@9tbE#Hmsyh`n{#^D!_L%;YAo~x`6+j{_Jv$`Ua)2H@0`IW1|A@8B zEWZLR6Z_3T%f=20tv3QKC?fxTpalYd3$!3ei3Cvl9~Whp8-X^u0mdNI2`~Ye z0!-a(O^vJpW&m@51;7$u1+WHKn^_wHYydW(Pg{U3_%TDskdV^#fVM`UM-4%b&VY_) zHinQr9e~~S&bi?e(0(Y0K*%;a=;Zo_Uz_Rxdw>JL!N>}ubHV~h#aw^AA!YDzs(k^ha=y-f23M*_F;`@OZkvo8bf5n(Nx{3{C$)dW41~{^t7dri4Fh{t-iNb-NZbuD6iIJpyCc9TvzgBM99i551 z!%uq@C_*F?;*b>b*(}|#A|@=xLtb3aP;cEwhYX?BNvV9y_}LN83g}BiOC}eb+qb00 zr_3Ch&=nS5_c;QOB zr*BjhI}XlMN+rpa0OiLiYTjQ}tB2;o^`!2K37V{|P)^41X55Y=Z+?O5cYFC~RBNic>H5O?nFZ~;?` zAG)@q_{r4^RL@OgI18iMMNp=)7$`Qsom~I2p65Kd(P!&ycdy3AcCyRq?elr1m60x5 znqI2TVw3Y6-yF1hHfCzgw>+&A{un048uQIju|8%8eK({ODp zMMuKP8VP&?u4ZgpxonA$h$2a~XHpK9nv>-X zF+l$`8PbS$5pjISF8Vknrup5_%AjVN<5GEvo}Rx>!@eflrvHtE6IlDj7y2g((?kxNbnlf4anh&LMZY`0{L2Ni89@K=$wUq zl%C?PaN@7v`dGLy)xISztEKZk)l4t$`Brrj=tjwz>1$4IN{Ifg zYGW$`7uC3E8jpgJCG5z%q%Q3zSi;b_aZ|}PE7gJf)Z(muN?6hlnhyAzx&exfCc)px z-t`!ru+oe}|~iIQI`duo>5 zYmUkZ&^rxdjdYw1OjzJ>!@)nH_>u#coMWeoVX62og_&BX8pT_d?-n~P_av8w<-=wP z#>gqm&v=gkteXr3Y>(qdloji{CTOHgwxms~EU~OG3Pg3c)BRia@4|YY3u;{e6B1|j z=64Ks(7VMd>TWH*p|eJB)8W=?loTovVQF3z5!@}^Dm_TMMDD28PJ(k+hsoQKGQEtx zv-j;5pSwXfG=<=cncl#|fy=WiKk{$I$J{JJ`O(|yT3Wu-!YTK;*@#gKS0u2cf|U4R z+23si6;5FRpBKLybZ<%9E3pkbyRP6qQZ2Prb*$g`xtp+|@ulc?d@j zZHl2bQob90mia{&{^AxX{5hlR33{AXiP>5ql?kaM6uc#rHgPt2)9px^7VVj4)!7u} zwr8F0!u04k&z#r;^MYP~Sj6sTlpGe6t26XDLX>u0YL)_I&3wgO#(Mg^O;}Aco?!)bSG9($ZdAdT}9Po{e8(~Lxk2{I?ac3SL z)WBm3Jtnp%^R&6&wBp%0o2o>B7C6pFP(|pxW$LcJ#$SBUgPeq{ez!hFmoyBu@@+2L zTZ7mxy@!a@+ZJnad#V6uZ>ThXz#C%Mlu0|760U({U%^qWX*&E9dDWC4fvzym!4EbJ z^s8RZtd#3-zqPbX$K67|)!^a0TQ#n}z^-U$hzQVqX zxjpkKGD*8p4$H)CbystWklRDi6q>>Y^N(%sj4iFFW~(N(xrAm7Mt0*J9<|Ohr0k;t z2wivft8967TMtBq9}&94%PSUwVDSL{&|aye04FSzmM|Y2PF#0lZcwOe;ihSjV1aTs zPIC)4hW>9@BhAHX>#E0*AkH9Zz} zi5{M1?zLO9%J+~PhjV{0lcJhpa9i2RF0=`6F{)WJdom`pM#_ZD~U^7G94SFD3LICw-&qhjZ*iD_$zXs_+#5VHqOo?`1a2u^5V`Jbf+o{Dyc;s6Hbn0$14SYDe0HQZ9Z zIS=CEY0zmnQs)^-gtt3ap_5NA9y*EC2ds(=o$=u*M%P!=mg=l9wnnHIN5m?~Ux#Et z|F}NAz2&JK+q==vVtlV6zP!~H?a?dLt`M&wdec#!uE4WKt7G%oSku{&xYM;+9uCU2 zyJpd`5*9}aqgwPRa}>4*rG`f21HQ5KhHdC!x`XIi-EA*pmtOh0tg)xLVEdF_oRM-M z^1#@-d&qIaUP#yun%<+&$Z9eE$jF=7F@1Y@PzU8WyBHzn&enS^aXYEfy?t`+BtDsJ z#9f4KneGf%xlyhL2CoNQz1<&rUc0jQy++^6&GHS)t~C$R6v-WGSF3pdh2W2UK=MqV zz1!my)8)zAxpz?GW=0nmusm0Ocl=4`4H{vpB&D_p7zNmRy3T49S;v_M#~vq*97yXX z7kqs$7>78_$b;1XM##rG(D|aQic~Hd-B-bdpdm}k4E)2p)}1wR!*a%yX*mCuHx_8Imbzd2 z<+HYmE?{+QnIncL;XHr1^2HFdF&Q(@Cm=U1ax{lfw0{2c+>ytLfH+4dolyL#G=!td z&-)Z4!5$i-d|uSC94eX5bxaHffz^lN`LmUV8Z3|CSk#kHK6)Br^*-%zcgVuWGBBfN zEnil^`I<>uSBjF<^4S(?75(e#o}=4D>sLW5GOF8fF`1ZszAm?)k0IZYaqFd{s{3}; zQexFn!aAINGV5%%@w{h_?^kQyqv@a7AVDX41j!$qLr96tkOS zVIi8 zq=0`fDXp}QpC|0zE6z6*dADN`1Tsr<=t*WOlmt{vu+4JoGwz?t>V?xN;`l+!8!~;; zhaE(06f}3RZEQqCxRa4loexiYgz6XCSPxBbdE2@oZ^`eBiaw`={|cAmDhg)ncEi>^ z-9l*@)mt<=Cd6n$C~0&1q9QVaV!or;^2qEb)$NnfxfV25k54|seulGCv2#Xels}+< z%$vRX1~v3B%5+ethK-bpOadRSl{zh<$MGX%W9`dvmc>$3pMFs>fni`NnzkCNA z70b$|%z95vY4*$)DX#n=Y;Py>z`6My%!m|xi{8QkuBH3ROPHCL+R(cKO7RNF(T@Z@ zV}o%gf>e<7NKg9v96xlyyT3uQyzpQD1RSubieAH?aZUC+>#qH9<$gB(KB|CJ79mzL zm4cfnrzOCRpdvchK9*7{?LK8M<|CJH?ic3jg9p&Buz|2Wx7pll0%4P9e7$k3Da2{Q z2p=(LB+LSALn|8JY z;XY5803X}E82%?;T%ltwKLjCne%c#$fWcPW(2rx(=#d~pcG!IiCC}So_H=%SiD}pD z*hGFCTGnr?d5q1I+a_HzL@v5(xX>fV;J9Vw!1UgevrTocZ{kiH`~elomn)f{#8>3z zj2n5x@rxpZiI2pc;YMUPjUVgRy?jC5B2#vv55?eq))aQXXcpDYF>Y|9vMe2_W+G!qUT#RpPcb=x)Jvgqqm9dpJl}l zMJMr)`5$PqWJf*rNSA54ld$bo71&+_W8R(CPkORflN`Y%y*i6wr!N@wmb?Z7VJ$a* zbh+wI!S0SE5+}{!VZ!>YHLCshZ6c9gue0-Ogp_st&%C0N4kt%^NMl(asp=)4L0wS$ zOc5+F98hi+cUdzulb=P~+ayW5;Dw(?QyKH%W)9R4e!aiIC(EA6B)vd1w|Gxg^F`f^&NcAJNB|)YFrLS^yPvOMk`se^bVz4;!zn>gz`=t zSrHlH95rN?FdV#b+jieEmC_EU=u4DQhY2<7AbCl=*fYb2w~Dkod#XO^@bcb_)NcJ{ zzFwJl+Oz3ksrQZ-aN*WZ4dKJQNx1gB*l!DOL2Z&|08a(&6AD?^m|y`86{@VyOXwAd zyyJp>**Q`Ov7C={9BI{_OSxN6QZ&_hpksKE@84?d2Y3y9a>LhxW5pOo3QCJ5+V^oO zo+y5Jf@c4D`v_>l$K`9RU$$0NY}6f+>^ia-w&2sjyB$=Pfw_N1cKWW9vZUwvV?Ne^ za`i6P!Pk9-bGf3q8SYbm^>fvi@7(VsM<`f0sAj5TYLn4~0nI-^J+>;y+1xIgY#LKq z#l8PxXDrCDC{sm@M>O5G#n@>T$2gBoy?7{Bszn>g8#+4*KxFb5mFHtVCV!(ZbuSk> zVnj2Px3-F#Gm+~pQOQ#ah6+b5xUom+rBV~FmU<#>g5ja|3`K-7Pb-D@g6Rj%*}mz> zwu1ii_RUhgIM-m|v|di|3)Q>*-u(O0a&g}?{WN@^en8305pAUhRaYE@zix_ zj()^a4qg`inM5gY&sRo2;2^EMH`N?(zKTFp~=95NZS5K=Z(V3#qWx5`b=;5)Mo zU@J#u8|!}aK^Xg$D8FqA7aGxO7610?QMe0H@(v(2yyn%SXZuG@?&77fwX7GrEot0i zwT(&R^cMqk90V}mC`ZV^N6@VKQrt4lmI&xy5j-?zwji{R=L_c%A>|6%PLMu!9-6+2h$&6aNro&siaaLL>l zN;1h|d-H8T_8d&GbNqW=kEMyHIs=2}= zA2-%VBe+TdzeeYaS>8ape(bZej@yE1l-XKSSbE`P_T3iv(zrskVe?XkFIR%st8Kp3 zxIA2=Ox&W|iJ@$*c)d{;{ba8@4)ocq_bdqKBHtECPgumL6Un{`m5zK;%gJ)%HtYlbz7CGtHSqE5&;4;Cyvq@-~*!JH@kQqKow@ z69LhVPsxrcQE=M!>P%qd)~FQ6qpx6nhF7@;W#P$N#{}w-PP?vm&V7jji+ox=^8zJ; zBx+68cn8&ZU0JO!JK3N<-eJLi%->Ji)Jt2~+SuAyJGWdkIuC4LQ9Y4ciBO@<6l#`- zW&*YD-zWRYD;X z=8(ZE-&oB=! z(ZC2&uF^qCI`WiaTqvz$d4C_&Jdv4|g@y`LvMfiUl+3u2p(K`(asrIW#Tk_v{e@%$ zQN2ArC+kX2j5$IxYAL$TV1;cOzr7fcVLSezt=aiJBD96deGd)gtuPDc+;9u8&8FAH zhYk8V!4%kIZbS?;TvR!tLrTW2E#zS6`d3@Jny3dg2vKXk?fUs~Pdq2a%)6iq){)cK zFheg)_;E})! z)ZtLKaS*?bn~~ciJ=o#lXa+&Em^k-X{DS+4O3ke>rCarhVlXjekz_~7BFkn~ZyfA> zSZ}?i3S*h(qE~Z=11z{6GTL3JS7-fze};jLJuyFK(u}Ux^U7BaS-Z|noG%b_GSQE? zBVTX452rS%;&$+75>q6cG_t(3C^tO3KTSh?<}hx#u?5>|BfBYkqTE;pyXln9DA1Ab zuez&+oA&z%Gu;!_)mLf&j_$KeX~Ou9TN$uRZ-sL!?ZZBZ$TNwkso$#e_fam=JoK@CsHTr zF(?kOj0c*hWDU9A73uB~6rSy2W}cm9X6~I53PPxSh-h604?KPJq3RZ3ZcZK95@3Ei z1Fx&5#P5N;!{4w+XtqwLH<4|C_X>*|>KMX0Mv=@KCrg&2p0?MX^h8D6du2@<@AgIoc5QUL;+Q!Uu9Ke0siCqN1y7OlH^4>$HFwSd^{!(mBF% zuI3p?&`HAgLNxp2mhtR69txVMxi#J%i5|W?``Cap)vRIoY0bID@3yh`1e~2RoE4R- z*8?J`+pnxrAd{yW^3Q9xpkTC7518A=4y|~qSpJ>e$4jHe^-dle$SIG2i zcoQaqS-+lXr*HG6vuUX3tTG}PjSGp`P`uVo_}cNSuI9>bCoyY6ThrEju$PZs?vV)c zzc@bjng&Yn6ALfKu3SSUTN+%+jDc&0hV_n|y?bc$94O-26Lgbu)R1Um5-b}WnF(=F zdu0eDUPMD_ZncNLkKD<6__Aq@wLNEvdAP;E%o)T})z3msJZEzlJm&hU`3-#8<#OxD z{#A(tdN}PDh#5~pv$&P82SE?GM{rLjuF}>C+nj>U8PcnWINnv0BkJlfuU$h0t=+ZZ z(M1wVie!XG_q&iR5`#k6n(SO~Zu@Rhsrw%ON&?UsN5Va^=e6Ue`|5Ln4UfsEA#xBVpBhLKTrf=T-+S zqtd2x=J14T`^hEtr2~v+?L~TaaO!M_^-@~7`AJ45okIH973%5r3ur?Rh{(5!0md-t zXq1#IxN#~)jCMSb)_~GId&FB(d009-Ebkj1cPR+;+`V1H52ef+DW40`1}0+m&G4{I zFOWfyPi+eb8)!$)Y0pBUu_7SHutrs-t+qRCR(VT1mvqQw;1u81Oh6*g$m=uZC~;u$ zdRp_fx7Hw*w)R?gmW2A_8=%RF9x+tbNaBz`dw{$xP!tM23mdz9r_3^B?A(di0yXsf ziEZtpXPzqU=t$rQr_hFe0bO=b# z972DNM*8IIBOBQ|IS~8o71*n{2hrzA>}jSwnrO2@6S&^~R(Ay2iF%z>%z)3#)6?2N zgA+Gten4NyFP=>da<(Tgn`|N`!8=sXygKsGPF}oCEca-r=wy7_S@o>Q#8Umu>Q)h? z&$5!4$VYgydRy$J`)-!yn>L{J2#b@}&G)41s^z2vk_h;#>Iu|)cN!vtFuYv#Yc1x@ ztC>oJU8Wp%o7oc#3AN-Ldu7z~of>ey)@*0iZT@F8k0I&oMa0MA{Iwi&(j|7Q&0>j$ z`4Ff=N_{Xx{Ym@@=nH9Q`%i(6%>o-4D-CjI5UkPk$jix!L=5*DWGj=H0yQb`7;ul- zTIUvZa1aQBqsa9UuQlj_n`>pNJ%RI!NFKHLk?|`kHu6b>^hK8Z25Z}0aVHP0uFtxB z;Z8T1{KNgo9@(msc+foPPkQEo7RS`1ZYDkIu0ha_ALAn&H1mB|W$Hdj-**V0Vm-vb zIFF~DXQ0(WZ&HkoUHRh;r;AQylWdTKyhngCtE{3eF@l)9WC&6J;83WIK;Ig$n1PAXaH&rr;Z5o8}~8Kns%6WNp>#L zyr~T4xAON%+8*rn1*QWrc_<3Gh+Qvl_L)LT{|%Gl&j(w7N0FXLA8romOgfoIwD0+%AJV)x?;}0$^KV_Zv>djc=>{#P`sb8H1_ozjE zwC;IX7X9e$|9O0vgM5XpHNBFQfh$XpuTxE-eQaVvvz?BmhLnMgPNtoug76&^O9gOW zza038%!nja!IXmS5a97ifl|m(m-2V zTbE5+n{3BiciT{3pJC+iO zZbdgKn;bVqEURqWx6ce80PgB)XIZw~nH&d%a9W#-A8^)?+-o@^~qLOjQD4ALi|Tk z5X-Mr+`p27z7vAJlXHI~1F8NX0{xlq^E=VU>VJqnzYu$VqxJmX7(L&aJU_@e|2-M! z$7RD$vGM)=Uz2f|n0~oZ@>g}$RG9tBjnL1AA`$CSDrm)TrBpnVG4fTJLfu3tXQNB< zqaS`etsi_8yfF)K2eN3)D~L=c*C6|AZjgobRrqzp(Q+eQo9(li#lzqM&- zzdA9k#>C*N^o+V8qdB>%7`sH=>yfp7hv?Lc#+CcWKAq zA<^CUO(YS~B*f$j?(R>y4^3<)BTFoOX&_14=j;9EX;uTb<-lpf14P`I9?bm&+x_P+ zZr+*sM5n|@ng!n^G;7qaQa?ydENnTF9V&D(uA3nwRew%0l6xMfTijX%(qD~OL};}= zmtWmySdC|L8__&Wx+FEHuklysZx+8(D3jADAe&M&=U@thOm{E1DcGNaJ#ZwCOyoPx zR+euh;x|XC`LrMzme(~UcmQIK zd_}M=)+`v7(Ic;|_?igdZzmxpm;YH2%TXtisl%Y_D?;27bHi0wGE1e)R=Qgv2P!p+ z)5PW;l>TD89sQV#-St}vT3plI!P~>TZixz-l($H%xz@#o zmg93(+AG>XnMRp|nJ?(I#+v7Khnp=1%kyHzU!FcTUk8GCnQmTifn`NPDLeQqyk5li zX`iNMmO&4iuyAfCE#5h3j^!`LIEWpl-@A_QA_spz{@g7VoBvuVw%(kl-0_1zWw~Pl z69!QhvWKxGAN9oPD5{idnSaL+xX$9Mx zA?L`%?S38xCBZfusm|PlMxMNJPS&U-65YooTKBbw4#(Fk!O$GiuM$^nX@yR>aYj*< z5)G3NC39mjG$QUU)YlH2ZN3WkK{OPqnW@YY+7i%n#NX`TDcsAtQ%aC(FUP!bG2m&U z;TA7hjTMmBa~e;gDnRM;KfoHU^*UhPd}7cxosKE`EEig>t{};WLw_=RN>cA~l)3HS zP{_q{{(<%2>1~|{P!^`SbzCqPn8~}i!i0z8PXpUm$UB`_sy;;J`c0yGBr2%$ir;FQ z5*@0e-%gB~=8crohaiwC+6D#~(O$sT-I#}WGm066_gNKLg_6R?&zu-IlRVNNzVVc( ze7kBA0WK7*Bi$My(uC7uVfN{oHzI}t%XLb5nhc>^%LdlNpprjGXCUr_-Q8QMrAlIN zsN8nV_#M!0P0kRZmgsZB$Ag=)b{E|=P9p!ygmdJoi4N9leW_R4p(Z(?)>krIKni-( z?a!~t#Oijo)}W|-6v`K@Y$1mXpIEvJoh=ZdgRzLz1DU@PeIrR8t_$+i$J>Am{W$Ki zY*uM4=4{xUX~nkr#v_yVU61J$9?}E~iOMafI7r$~y96bRLM#xe6V|+DtB^a3M zK5YpbW(({+a-gy?k{jkdH+Z0TJZ_LJcv|ONPL~nV3m7CQQk0PTa%T0*>f8B6wKMp+ ztMwoey#_JQi^vdH*zEhX5sFqzlgjdaxP6lpy4x;t>u_*t$eH5H>b&MzJ{F8!?H0g~ z2=L(^x|Gs!8zKDTgeV?FdBTA{w{NJ6O%AbVMv_dBPiw?skMp&IP%{z=p!9vW`P`yr z-Vv+nOjCG(CK1D`2kKSXHjxIn@t)B;Xpk1(+eAVP(Y8qVgvq_v8PkH_FGcPtkx~*S z0Tu$urV$wel~SrjwljlIH~6ePL<@6fnYU2DqJg$Ho{w?y@9fjg@wE_w7Xk$)GTOW##Xtn8 zKRCTlL`gBg^L@79b5mrhZ-v4s^fOaMM`D0EpGCW?RZ&WIbr8dxBrH%+B38CBOeTbU zFHBKeCuF-v63O}AxA%+;N+D_=OG~=+^>+GD<~KwkBl-9A`a8vo)uzi8>1hHvX6>QhCs z+32xIosQuQ@-BW))88tJ>5*0)#rItEfLf1is?u6Sc}ay!`7$J4oe&b+dUa%KnZ2c` z?3eOMMHjXY+VvQ7B(vjR@;NWHsK;YgqKWOZXC^RFeEW5 zec5@~yc!UBl=ud!^3&&%%qb;BzX8ZW$hRcSMf>;e5-r_|igPT(IIvmgWT&9`L%Z(g z9|i^zhxF~PL%+1^#3ERDpg_};`?i^%o`ZWY`uorLwej`v`bs`3x`Yl zOHe7wFq7m^=9OnuCBGI-IS5$4AIWfB<6so3MwE-BaADss;(6ijG$pAwEj|>T_N)AWQtVD)IB&EPtRWGEEb9cD{oYc+UO(@RYUZlV^`N+FVziqAv#BIay!>H4e|S8r3T5XI~9|@xu3&`$Y5I^RaVij4M38 zDpJi^l?8%FT{cB#8|2qXa!=2dSlI#%k|p%aBqDj^Ia@J1Y8N2}5vPa5^X1AK>Yine z0;xo^2ymNc)Te&=g8pO%4~+#2`ELjk29q5e_X|Sv@sIXps`@$#B~+NJjNkyKat5SGJF2p=9C*qy$3(Q`PrnM$^D~5vsXQi6d^i^25}^#uEzN~Gb3((h^=L{+U{_IathQ-L7q6|r}X?*g^li1 zQv3bp&c}~okc)8$;qiB`bvm)mQ|XJ)dFdI3dl?TI z>(=u_&3tQB=sQ*78Dz{9R9r;Nf*D>=bP)WaySeo&(BlrwsYfe#4j!wzU};aPJX?n) z8-krg+-aJlVeB%&lBVkt!IIyk!6LpL1(B=t^X~J$9dE>|Y6(WyIUx>LnpCkLtO|-~ z!`vG~I={x7fDooUZ&%39MCIHsJq4H~ALTs|-r-h~k|R4r9Ndzk744%;cS|rldr53*7I-K1#+p3T=$%trRS8=W(J2NHQAaY*;k`ZwatdGgE5xojp%xeN)cbB|^vk<~onBmt3Yafd#^@g9 zhsfrFO#4Rfi4qBn#-)WtqGyCD2L`#y^Tcd@9cnR`-k`4L$>op3$4JyoZe^>Wy)E7| z04?=gX29j#xBuGk)i-uNpy}}_Su#j0&O|UlQq#AgW_jDZb<4|ge1X?dG?S2xm;;MS z_p3j68e41z^M;})!Lkk6>8!I4%t#e&MfvoS{n=%1YQz{9XncYfAve}4LhuK%#lZq; zk)j0rH$_tSQ_XC5q*ZNwGU7Uod$kmj+k2?*7W$1si+Oad?kb6Z6)<5cJ;V?l3klp% zHX5N|ZHNb0?+*pwooA-Drf-KA&*)t`yYgjvLz+mb{gZ}LyS>tdRu!({bBOc_u2rk8 zbDPBF%3@{;EWUXZ*pLYK$>Krs#5)lMAw20WnabyPkXSaq1EW#BmwJh~VNQuBP@{3D zsHr{|HPDKycJ{)xQ&Y#*A9pOQ&3K-hhsYna6`b#DVyN~-S*G_KOIHF0Il4?iQ(RTh zP@h+&K^abO*_O1_3A3D`l=`;9WhR2_r82of;=%oVZs&Ncw(I08ilgwlNi)_s!`3+e z+e`BE!9o9CV7wR8gHX~Hv*$GhR_c?JV2(8m;9pPYXgorpg;#^UAtx{ab#si_wT8;; zczb6pikpSz4%pm=r~J*(V=Zy#0lU);DH4 zLL7n2wmjv1@|Fx5lqlDTX!`@PE*yhJ1r&ZbZZ8%&-dK6mQKN?dFXQSO+jH1#|CDi51tA!Y;_^+(w2#MxE^ z&aYx+J)THAOM!2?Pmf_eO%ADN$r1=FxUz)YQpDQ!%EvayDQdIm6%%ygJk%Fcm!*z; zPGxkwXH(KSFcWiJ7D{ro`l%h{Ic=LZqgOT)^RuF6(A|6txEMH-p+B$!>#kG9fN1NE zHwtgQ(bfXf`sN-|@n+eGl>~-n`w9%Z4QEJC?=^5e+!NkVFW*U^KUiDV3veizaey2{ zA1lZ#gk~Kiw^}fvo)KTS=cT8KrxEkSI|bv!@lU<$?^lv>S2A-oE{keJnL~3#wGs(l z)QE4s?5NA)0`WJj+;OGa@+z70s_D0+kl#dOe;~0EtT&EEIsK@9n&xT6>XM*pNI#g0 zfm{ddkxo3(vnL1p} zEft^^FOJPf%~_L4tqLD+Y?1xL*A6OmVAg-NL=Ks_gjtZK?9g#B zu)~$INky6O%3o2Qms9j9gtU4L3A0i9wtsX%sq!iYj_aJ85E$mhWS7@biRVRr zi6!;@Rl+1U2*POIezJI{eG^6+jN3e?b{MC&YmfR7lM+hkp1s?#_XH3Uhn1K{02`+D zl*l%Zgo`9y#!b~Q(c?}7kRgdayQTTddWoK}Z|JJI-Na`hVT#kewC06*Vu=NK(x6tX z&81JwndyS_sM?rUforR7ui1dZXakp=b20PKHM{jIj1?{}csVbyy*Lr|=zLc_{Fd9n zdN>~uh}%ObUi|zk`d#l`#5g1$F6`q!__Zh0MK`PCe%xJ`3%FetGecoYkhhZ9q56gn zqe>m~B}T0$S^|51 z=m}d)2!`EZQw2m7R)gJp!o&U=2fQakq|oMO38vxg0@D*>RyK`by<$zf2(!{CzYAhV zRA|8fRRMmXhXz3(+YXip#?YnDd|D`)zjm92nr><8^Sg#oO{mkwN{Ng)B7|vB?4V=n zigf-EL1cAPYJMRkib2T_37nQfc(@3ZV8UZSuGVAS5mT=5-kkVsYBJQU*E&W4XVRPK z?$MNKn3|mry^3EX!?@XVo|*P!KmEFruD7RK~Wq&Mp|A zygm5c9pR5Wu#I(#LzS*m3v$>mfJPn)V-j>c?sekNZm~QuH!yCi5d<(*jLq(M(;w$sCheme5^LjE2Wa+O1 z`yaZe|KyDKFXE}cNo4?pg#eR!fII~o!*7%NU!^htAN)G32Rwft*3$u&J^ywK1W*zG zX$|y;2gOGi)@9Li z9*G4DoIMNN;1ceQUkezdr}O5EHBDRFK;PaDc5KvfvW~1;OhT$$X8L+@fv%~US?OAQ zl6p)+a(v!el4{iF#3a=>TU(^SyCf#LUlb3>Sa$#qZwF)w;2hLE)YzQdk0nkcqg13+ zVpQ^H!!lx20}_kEh$23}{X?>WT|m6fe8<8dhe`V*MQ_2^a8= zOdPE?OLtG-+UpH8(_oy&(0v^C`?w3I1s+(u8Ak8Gb-onKaN z-B>!B(jNQn=KzZ*2o73HjWb_+?#&8Z&>^16)|((tlUc9lq+^z(mS>ym)uYj?)+!GZ zx93NWMyypY)EdwLD5#dflSgWnwDUO1v1$M9*y(Nm?s_AL=@+eWzM z(bYR?FEqAc7t1S|^XVZT5)Uu3hGJK7dn*+&$2iSKtMn|_S{>)Eok)+@fdbBT4)%{b z-yVjuK65oUdkF(Hy6+%Xg>bD{=R7jqbS^SJ8MK3KQajqa?{c1}?51$)oNuIEL(O?Y zNg1#9U-`N1QsUr%g1*X91HSxg?EMhM{U@>aXJOsnLhrk}6ALpycb2r*-_+*7BAgYoe(Xm&t4Cp^i0p8FRXBdp)syvu4L7fE zGRtQVHybQ$fqm6-N1_m9_Uf&*4>%MpY||nVa2*`mUMCGB8?S^4KI__!@<&igc9V>< zk#{5Gd)|sRkxq@g;sdJ)EsA&n<9LqU5ard1r*+w^g!nCr4r0AT?XMwq-YD0Em;3L< zcaOssiO+N)a969|))78dXK9zDwScqG1z5UD^^7OQl?@1l?YWD3uiM380NCwdw0kRkLy9})BtF_Bn|6n z-7ouO(!|x3?5Z3d|CuR6f;*Z<>m?0aFQ*da^Q6V2_0>mryIq#~l3O=3e0kR^J_u{Z z6b-5CTfnd6?pJLP)I^g9e+{7@ipu{ag#IGS{Cf-m zl%CiCG88{4J^evn_0bf%d1LC+x5a=?+}pWZ4(stXURwr2>K5KKUXxYt zxLXZRM5-Ok5w=dYKtv&en2DI&*-{A#l~32E)igq2b|0@ZaaK#h6fyGc(#dhp>Y>z8 zslTpU29m~TYcDTZNavlZ!%0P;RKIhQCr44MC(;Z_vdT@;R;ZSwfnY9TTSC-+iI25P zdRrtM_coJaNo4%iYc^TA_r`C~ArF6vxmME}swMFT9N!^ijD$drJRw0x=$Y6w@SHPS zNAD47AcVbXOE(ycm3tFi3YoPXf)LUGoezjr@^Wx-+YHuC^)(PEt)ICM99Mq2HxQOS zQ#;SlZPl&&myV;u5AmrsJCow)TFc<8im{PAbQ7NTf5p-dx$1v{r9Vqv{|+TUI%WVU zqyKNGW2QfAhB2}L{_=m##y?{X0C0eo;2&7~@&2#VFFiBsPgwiC6mq6`l6-r(K`V^m!X*W|7Xjn{fRBp3n+b%u?O39 zJ9WV-gR};3cs606KwDlyqr({h0F&P7AajX2eM) zv3GHKi~foT%=FX0!O~CqC%-E+fB)tEmygj;5_Er-?*1Pz0gwdHfBawLR51c{a()NQ z4`+;D(DB3A=O=XhM-|(@Q*QLrWUef)6H{Y<+z-(tQA#LgqbUuKx-tQhV`S|lbG`ikv3Qzz4CE;LH<$h z-Gbw%&b4xcS^EWq6&KG z9yW_70o21?;P#BQ}3B;uC=E9blBA z@1o6L^5G_oc~cQ!8ALq?=Y=tf&605}BIt!PVn5=#mJBBFhz;IZ9B|3qvv8YQlwx)``qDk)R6(4D6yM+A{mmCSmG{ z=0p(*rqRR3j?wjnoEPQtYA&R7!A!(eBineRrc|)W47H5SAyZgNOV?EJ zr)!_?=vGvq=QS`kx>*;KDTEj<-6kNJ06|UIDe<=!&VkDb<>SO!yFzN%Ob9M4T&P#% z%qKipSeL<3^ZX_r#q7W+@1oYkm4J6<86cc#t-n|&`3v?AAWAn)4FOXQ(nr2XDwYNW zZ%|2>vfFUvsI=9=+p(rGURT5nuE`%t#0ur9;A2m$mRXZV>0GuK(Lx6hRiHnHf3Y@3 z)JXRxBKx)mjG16fruc1^F7A}sZP<->tv4*HxqFbyPDhkV?{kEAj&mpGwJwgpGTuyOLfOSZ>#Z4Cn z!aWdKB7NCkBmRf`+dqoc?L`u+KPgU1Yb z{QF=BSPlNEzxzdn^bZYEOC$SV+BlX!X^{SS|JPwoN6YrJ0J=w%hb59DdhhANvD1)o zpQzeky2?9J1_57Q-636J|Gh5=SiYY^-rFDQo@N~$G{jlVUN2areVtugxB}I<;a6o* z-oXs&qLM>G${k5Zl$U_nRa?}(_O&`60pgtM@r>k zc6v~)G}PTK1^K=TQT%!C3#ANLETW>BLej*XrGqZ^LNltB7qY^}ZAO#|3{{D;!g9ZY z@e{K^s;3BFJC283^thsm)^ssV34Izpvr@u#j+|F@PQ!@lSMCxTbIYl?67q#_Mm@|~ z{rbhOx0M+=1vSf-jQbKA=ApU9(4F9&>+g)VNA>1VkKS5>eMMRfv+AKYRHXzu1n@qh z^tH|8M#|Q5ddrJZx@|y*qC~k9+Ia5865Kh|(y#4b%wZKzcbD zStO8IPYP|J3KKn3LW@C@$21>mLWcovvm@XvIDQsWRIHr=-diKQl;&`C`O(kBIL3I$ zSin332nHBD-qhJ&9vU83UXKlkgkutHAN2$n=`wQp?-=cDq{Z%$tIKBTzp>(zdGeu; zgDev_7jL*>33z3K6g{?mey4hmADlIF=<>SSn8U%vrSzv-r&p&$k-N)P_5UV}EU{R)5C0@migKlUyZG_>d zge>y2CAk%~i=Vt?J|{KCo%FIY^Dn9e_U2jeD4LmpR?Z;F5Z>O@19wZkhC`^6XRvp7 zxI#L3S5$KM#HHyjLm zOCawIj^xsA#72o?)?_^c0lj}@a1Zt-17G_FVu9(c&>e4!gyfxv^vq@MsDN1FRD5UO z0xp=90FA@#N1Vi4dT^vEM1;VyIo8N0yAaUhv4tJKHnT$fy>(vd`ZOqEL-p+z^6li80{z@@gn&N3BX}j zdK3!SkR?VdLy6OHV@E_lLBR{?qv%pxFA=ni7g7cMb|1w|uv-sidHDTW7QsDPc3w&;+5i^{fI;{6|NofV>Q7^C16^I+ zim-4dUEN57a=mf`ctc$f_Gs^v_CWl&jEK*NJXtoRK&xKHBb(5xL@Zvji$gBAdDNFO zyQj56Cc}rRJgu3H%Fm+~Ul)Q;E-qY`tG2wF?y-s40eVC4UUrEzU<8eGIaj@e$2Xx{ zADCYz=7(-mEEq0t`dc3aSuCC=Tmg5cN39r6iXcn8AU!-uf?k8ft#^4@v5#6`!cIj* z_B+xLq297AKXBjSTt@hvst7jP)Gm+IVLU9@IqBDW)hg&kX@Av7vZ{5g6=+>YeXvqi z8Mtx4J!)yueJGknBVIac=|1Opxu*Vy}}_ne8TZ zGe6*pq2Swi-00DO-LQ<=WZ~drx7omU`;mF^mu|IeqoM7$Zgm|QCl%__^?SF93pQx* z*GOUfJ{|Zcb;@5HY<`OrfEGC&J-|_cg@x{KCebY41y}zlRK7p|C{+HoD*?Dr{?T^) zv;_Lyw(gf6*9ogh4J4FIexUUAV0^!@w-mD?Oli8j)HjN{aZL7J!{ur ztnu60I({sCHvazu;cxamL*LJWa{Jn711mxRBbCo&@8JN;lS6pWw9Zvroac7-wDaET z&LN%=k5;1lC!obpqvgRkG>6&#m*=x5?8TuIl)JlSkSn`Zo~P$NZI!W`Hys zs54sajwsrdjGtQMYId_*?AlqWOUNC3(^6F{ZLx2CuwzrY z;ocnr7_b;VP;sX`(awUMbTYWOprgNnzR1A%D?opE{rnSv{>3opH-G{>B>-6$&^OaE z{S82AzeDX0fPR1e4p4yG#otuY%mC>A2R;AaE9qZw`ltJx@8(0lh2KBV*8tO^pXV*H zQC5};O6a{dv)9+K2Oq;KrA=(IqIf^OgND#=3zA|ELeA#T-1H5VGjz~sEInSZw%1yn zaZ6it(weOdudy&QqFLr2(+v{W=g)kD7$k>;*ez-(&e-JO zw_M)J;!5dEEb_8>N{fcg*L|7Cc{PJ0S~aQucHN;kJO zL@$f;#sH0nhvG^AN?SKiKSK`J1!CSv5e;KWpKN`meHqDPRQED@#J5$<#BHL+<)F=G z4?aA%SEocl-gX&8$>xiSKyZ9Q!jQ{{CPSM2$bZ=CiaJ;vitFy6^F~+!UL2-~T$ylj z^<8?~3#lrF4m+_nd*7;JsAM-awO_tz6bCMB=oN?MYuho{@+zmj*BrAzu;u<(ysjy_ z4&ef!E&TyjYrr&{CLZyso^nAv8>7(Dv|}(#E)?^VBvWC0%-^V?w@o#hlP?mN?%8vD zHVvgt@=X{MVELk?`GO_d3A5+KMEThxfz2toqf+;P(4N>$(6~Q-)+Iz2ICN1C@>FZV zv=_vKWr}Wtfy*lhMybe9)8#Wj8;|wLcR>s4el&Ja@@5xP4AgFjn0fxTMb-3KTlr~w z4|+@AeobPM_LXEC(XBWI7k2TkYx+>L?zhmo&3#L7dI#7_O<2F^;dZt@5PDuAd0M7% zIHz1pAL#`wL$*)+@ID#n{>YD^1nf}l68r~Aecc+l0VB^`4V%>`x2YM*dV+zX_)hya zevTtbyqET-EwXA$VTSgi>RLwYjkn!i(}Y2UI!R8rhullqg)AVx5rYG6L-E;FrXWRW4rc*4vA#@xwVQ*SC99BjEoxrwn|M=R)Op@k^rerB) zF!MBIHTZ7v@yY8WE@V@XQwiG9N*3ec7g%A=&4M*k`uu^6TwTd>#L|R4ki3H%0YkL% zwTk1;hgizZQ?M@={#r;T^|DTij&Dm+pI=QwzD6`eMuayYO@roXNWMXT<151(7F+## z@ILVI86V9>qN9r84t^-#Sno@cKj%;dfOq4r3!48~p3q}0yM$i^$pOZV6_>8jM?z)&V^HYN1H0ykLNxsqBs zXq*G+3y@Se7Iq)JhsRjCVLo9E8syU~(U@6*sB^^v$l-oqvD0_A>Z0L36TgIDa{w@M z(=JnYA3(t#?lRN>%Fyj>D`=r3pQ_sPr8*w{2>rTDGvja}1Mkjr2|6M|5ac{brEvq? za^~;+^GPqc&D3LdeJUxtpVgu8)xbme8OVYoJ?QN3N%?8U7@GVb>=xkCQISP-Y-zL) z?vM9eB7!l$lm)C8qu8s)>CVG=f};nNM*H;2hLBN3%PD;UwUp$;GumNIwi{=TC>gASJuAOm!LX&y?%iC-dcyBqFv!~ zlHLpaH2~A?tk1*o;`!D1!Zg2AN%5|V!`Ft!%l+LXJ8duVnT6SjL5ZWVk_r{)R-@qh zX=F36Vk4yz?lae@2PJ(}B&Pv;`E5%L3}(z#smBq^CMN8M6=Nlo512lTQuaT0K zwE|zUxx7(;_k(n!{a`yU_09pkhxav%ur4y;r#4#bEXe6SaO@n!*_!hCy2}2slWFFv z%R_{(RW+?U2ed`hX#8HUUYrT-{u+)yOxylR-SeMJ;C=)q6~NYu3g92d#P*%3^>@1i zz$ZT!LCmbbP__PUoXGm;ZuU=B3qLO_`Tpl(`uk(2kWc&DRfV*aUm zH?MSIwf~u|?<3pvZo*l(#HrH>}4-ysC6$$+2 zvUZ6EUo=i4iXYtHjsj1gqtnz%&k(&DPPt^{Ox~oa`7vbBcb_#Jt|gi6(qorn)fqNe zPz0Yem^da1!yo^tPMV5_QG9yKzjqCv7{n+wTt9Ukc`iO>S)cmT=Eu6d_Eu|Re)iX2 zdj&>4{d_ZxZAeu_)V^g`E{JA-NqJtgRbL2s!B3cdD&(J&zhT-G#{Nr>J$Ju;nlFOSap4~r81_0(?;!3+)FU# z(&T>khA~T+GYVa|Ruch#n%z5qb4vuzpc}!tyL$@KH?!!&?U}*7tYgOEmp&ARdE0L)LHx z*4KAKCbzkEPXs}rx_!HzX^2U_sOlZKufeq0U>Sjn;*Bu-1{z!OHLetG_D<_v>7wG{ zYow%3n2Uw``-Ucf_9U}glCYKv7h{`eQ|^Iy!dWebF{1N9+_S{^ zd2s$L4O3r%M@?H`8tC)j^fVi59T&)*3wnzknn?zY-=-|adoq7kJ@Srqt+^CKurvZVKxe3hOiX7}S5Cy^|R zA7PMOXu>V>;^Is^wUM9*j~>p#ZR@&CUL%v@tCbR@6^_Xwx0w&U%NXr!9ro~zScMGq zp;9Fb<{Ikq3|k=JqwWA6d0Hm%r+Bi?TGrN%_RgzXWm5`|;EfioEm03F>y*4@9$GEc zq>3Sh0YN;6b+_&C97&nR^FcXcT8|%9RpW2YrtIj~uWx|VMRiLnb31z|g=lg%-YPx) zplhYi2~AK+bnOPs6Uy99cso;uRR;nGNdY<4^C?@L!SSJ}ZDfiaM->Mb8%$LvqOpB) zVs5W1F!QP+gvs)EvN0(y$O12xbcAL zE&ec6Pe&bz5BB@_;1?{ET3et0ns0x2LjIF{`)|!9f3JYpm>9pWZ15O=H?;Y6Ys2`9 zrOo%(ADt%PyMNbfes4*C={0{a_o{xF33C9nR8WdztA|35UFOte2QY3&%+9YpuQZK4+c1)>jwEcanD7{Pt}M z0UbhYfyB)_?idx*Q-;Y%m=?$12SzwVl{wD0w!c+;t444|zN71!3E&#+Grv7ydYkBF zxKC)$caK{L>hUgwC@I>TG&p)7raz|tr8McD`3Egaf#>Dvj*J_Ojx2Wj7N&=0Zw?IZ z*9xU^rE#XIbG>eWR~8hNSCv<#*Jh{Xr>B)=R#m50m*u7x=D%`MM^LCNKke&)q*zMW z-d!n>9*MEl_gL#YsD|EB(j6;H^+2_-Y@KIc9QXfFjc~DzE5?i^;+Zgh(NyanaIL)07B|{c zSL@=j?fht^Y;kQHeYRhC#>(7Vk4Xxw-4uIq=p9mOs& zPER(YHlsG4C~+G-_kJ_|=y35Riq_$5M!5Y&{J-E% z|9Ccm0Eec4v@Hk#iW&|A9y{r(-=_uce&M%o>%mFYbiywGRn7?6~Z2uQ@roVEzIQ|Ku zBX>d0lDsLA)$$HlQTn74qK((-`uzL z{iI6#n&fgUxZINp!Tp$hU2rj;B((6964}MVJoL-~4MzJ8Ucq^FqcxBXYVq#r_Z1FC8J^!zpJe(?3bQgVT->WW$`@FZ;GCtoj*5F0{t^pJm$2c2;L{Di1~-1Jh*&44!rthFG%BZxw5{%e7Chp;i#wA z@q7bez09<=+E)?J;BXYrKC2L6+ht~=usGNtFr zPuX|!_)a>H7JD)^xyiLO*nj-^cH>gE@cGp;{fZG%u^|E&#WtB;fnW|*ZpRq5D@*yq z3wvt!L!^q5>d!L^;jBjo_6Z9^q zDQfL`>2omoF_YV|UrkfmCAGaA-DVKhujS>U1%7JF@Exa-%uF?bkz3q>1+M3A(SCU2 z%kg*zdTu=BPDggeC0IlRTmN9kSw($Txz24`@*48$v3*GCd3(|<-A+N<)jRdx$zY55 zCad07i$np#%yE4&e1QaYO+zio%TVtn6FnSF;H6VVo@`G~$4uq(T|uci+`8%hR!?JC z7GGCM+ELZ{g?^4hY-~l&h@In65R*oBM8eCHVw0)axu2`FLiWgCEE6(}r6cTnlmyt` zNphU0krJu$EW)hPIPIzrO4NY)G4(FVe8m)} z_*w=S>oCanHNxLtlRcM^#GkfY<&TCX_ko~ai_H>im zP_=ntPVv|31CAVRJ(E1bOYu~54e56Eqp^wIn?moS?`wp<`f!6lH;?)3IF^<`oBH&3 z=v3ht!d*nsWCL5foTnO;5nhd;Nu#v&&)HZcGa$XLk>Dju<50ARV|#lh2%N z!Tj;$gOPbBCm-?dTq@u=UT(WvPM6dr#<} zVdlO~r+UsiSSYpSwR=^Cev;|qx(^1-DgB|#$}GiQjsE!U0@}E^B6{x#ta3fSm<no=^QP#6GlE%7?VkfQ180%LLy8w zV+T66%R!rkg>K?PKtiqr-ys~*HSYNsuTv%}BpDtqzZ4pLBC=(UYh6V=ysca!8&Y_44ZTQACuB!h{IXQ+ z>4|%uv}Gi0)UNfYjjsFlozJb4(Pwh8X872F;7vXwUo4kd5K8q6D|@$6mL}jtg6N*z1T7AUw~D)3NC# z_LG*^+jwoNrWNOgluy5zA%)&!`dxA&Hb3Xif~~?{rQC#>eZ~$4)8nq*S?kbUF>)%b z8{K|}kfKSXs&Nt28Kb-Cokog+;8Jkmo70~xs=a5swja)ZUD{Eh)NapLnBdr?!E zaM`eotp5uC5UqQpbS}#!Dcs(5<;e8@c^_8Ydqa0F1n6E<^V2hf#0hwY$~_}0HCK63 zbKq*-xXnVMptB)UWk|QfT3g-pFtbzT#)Dhr!nZ?-#!hrOH&Th3eFzN>yBF^yqrH4_ zb38ZjfNgX1-Kc$Nxwc6T z!rGWqlm?_f@9ZwB+%9pYQ7Mu1t4@ZQW7H$NM}#q1yi9U!(+_LP7cx~EWX+jwU!oTtY^D!*Su)lfS9!c%;pM&}?qv=WI5OwU-}#{Z zIO}fxytjMG`Nr6TU8$3qjRErmUByH~cDiS=(xe4V5rGjEi;C1Nt5`~SK6#6}@rZZ7 z+M=zs;3jQ+m$eiEdj=j!y*iqll~vb&hsTjoaDs8?6YewxZ-g?c{{rNZ(tP(GBT-U= z9)Tu+?@dpdasmLqV&}^HfE_%mWRWj^uRKNkJ!})Y2@|nAa4Q?ie;OigtUwZz(#QGCxn1Ip^RKg>iN~8c5}j+*;@%)j(7vR}Y(`{zOunXt}i&O2aLIu1x@%Az~*V!Il847JtbrHFNPy8bI{(Udn{gf{4_hEUm zcOI?x%^vtwTE0_ZXeDHgR7f%#h;w50(`%8`kabPQoLdlv zB;I#z4ts% zCT*-qY($ep2scmV+Z7Q#mWggQC6P%ky0lQia+?f36IL#&G^(PZ6_QbCQcru?b1%M{ z=Q;-$>*G_|vIU~pZx$2R`#g4jr(#p`LYdm!llYCgaOa3Ky->GH06j%R< z`?Rw3x@FSX*7xqYcNJYG9+nMx-o6KZqTSypY#QPdWm_aKBk+;>7m3Y%1~d!@h`7od zAe!G@w6?!Z@cQ{x7$xMjbZWgh__)aLW0+j}c|FY(%y6eVy^aLyKPE=4cKYd=VJ46H z_MYfl1vkHNmk^mp#`lKcF*ujQPtU#+sW9r36xu&~J0|>CDRpQi8NIIFycuxNOWoEn zNJ1OR_Jo!XDk^iB@}Os*V%Er_VI1UF&9B7W5*sLYM|7#oZInk-k|SPkb05C*bet#W z8%=GnM7ODcL)(15OW`?M$q2&i zp_bagvm)fDs=NC(9kOtW2+lmB>4552_nJ=B+P$fg?R%|r%WLtHPjlbG1!KSQSl73v#!q;SOcLBmcXC_Qt{xR<63q91Ew3%#;ovaSyVzGAk~VJm z?b=6IT|442ntL?SC7cAO@?=i;+Os_iR}T}nERIzsYtMq158z$v3=4-z#AkyaU}S-j{Q*m7SWKxW4LnXCpgpfszZB4(Lp+*PG3H;=xm3;4v}>y` z*EL~d5qGaX!^uK(@tQ)@J<|uC{Fbt1R^Ujg;24E_r@2RS+V|%d);4YMn=?0FHM}Ob zJa6>D&Cxj@l!1ItUh}*nqoB`%n7R5jj<>{>pv~=II-qcQPszJB=?mK4ThgVQp@7Lc z>78i>W1Q!Mxo?77Q!^JDr$l$Hbmp3gJMp*DlS^x=`)};=$E&E$I%__3NzXF<3IK1` zHpFX+U7i)#@I<&C(r*@OoF!(jvwYR@oS}$Uwm>brh}YVYT{V0~!cDY)$86>#Qp_3M z$CY=&DBwUqhk&blgyxYQ+SexdQDK&u*}Bh?Y~1=ini5Hofl0^U=BUCh@km+Woy7st zxoGyqz0||8C+oPKMeQ7Q)*{W;Y#g`onS2H!Ceac@DK$C+j_nxUOg?L zMT+g~dvg-d6%{vYJr70ei3 z17=kc*|MnUB-9rVukCveCtz@kp|PWX$v}`-yEM_M}|vrKIQcuCnj_#Kn2Ne4lZ&F{f+I!Uy{M z1OzMw(IL*#!!lu|kMswUTUIw^#p9(NsS+BN8d@r`+TI0k9{ZK);kuk7qSF}b0sV#>K*3NSQ9bd*0R)Gb}x3$w```9d#;&6YcNvmW0M zz%&#oud*%(w4gWlEIcJ{i@K8#^Pm7_e7bHR(5-RR*)@GH{{If#Agl<)PgF! z$-cAC3P@*YW~pBz5M`Mzzr1hGtyS7VSC0W_4UL<%Y+?L9wiNKZ&*n^$?xIcq+Mh!d zM`dP-VD1E?Q+a8GWVa}-(>tG9M$hv{Rfq0gF4MCfSUqVeMQ<1EL{zY3v)0^)E0CM5 zz~;4DlNcozY<=)kvrzwb#>gcWd_raNPTx+NLU4zM9Ax*bVKc8sP@}5el6F8pnPpGK zp_%9_6`SJE%B)o1?VmHR=n&BCPvhkk?;1?0#*oD7u1W3JCJ`Rmlk?WJoHO>9O%+S$ z0iW6CnrnYCfT8WYAe++VMi6YCQr4|a7{9-jx7Q~eq{6{0mAN!p#TuGjyTnHF#N5Cc z_hnYg)nb;i^R-kYF8AtSrCfc?VDW;26P44}zIjthG0QWmD79&;m((?EhNONX&~e#c<$U8uhE^+63g^2;Y3o@}zCS{ZTnx z0zJ}@kRc%8`N1ch{g82zG!?VRc&Fi;d5t341@F`?Qh6?#0a(|Xif539+U~FOAApIAAT9a) znSeak<&xm*E??q}?|XF@R4pmb8(?AP5@*cGwj?gs(M$?^9#HGVKDnY)`0fri`$l(P zycSm~Qs9wClA{Wm7eY5^-SULuPO0_&Q_83O8co`bXkhbGIr} zW5f}qeV>w{_T3De-hzE6T)yeSrdI0Ir{cgqpaT}(Xf)#YF9DFFK!^Xtv#BSqts<*` zO%ecb$Dr{)0{i}SYVrdgT#-x;{_<%aIWhn7X~KSiwg-y->eB>* z_5bi_qJXmy;?9;j7;{G}5c~+$UfIO;=U*5H2aL_n|No785B>QVg*bqDuMD^~O#t}% zzcK5NJez++@uOYMuqL=4Zca-)+QbnU+;8yoN8uqqFzWwKX8jWa{V`bEf+2YavK+7KkmPZ~7P5klu|Lh!v3cw*heHQlDq1M$Hj23}RPix+cI^AsQ zP+4&`Ij~S&+KN>CH8~?ryr-SQmvx4dl|(a9o&pP+ZkCikS%2Zej-dX{9{qfG>jeFA z{ahEB7X1KBQCZ2O@r?1ebQF{>g3xjDxegJ_m9p)N?56#ev6v5US_wBQ*{sD}g=_OTAAduD!cFQM$26v-==) zOa^FG|ca=p1TzSuM2 z+k@%FjZlNpDF%i}`uq;l$;e1}bwGRM%=|niZaJ~uc)7&lZ7eEO*z@Ad70QSC%cn5e zm}SM$7%tq+OD&c(Zt`k)WM z{w}~rBXf8E{l*#Sl`n;TvYL#raD5psB`*nS4M-o=9nP|Q57T|KwKOSa07P<$Z1B~1 zeJP%d=$ne!6jviyWogqsW>NMDMTNAd>3-phVt_^9Gl;U)`mEahzg}Kdr_(GDbvW2li$gB;gnNEo*Ai5>5g4!uwD`o>Otn|a43{}!1~KC+!Hy$ zexVz$9xqEwnvgo`c-X00>DWnXh_sq~Bfsn;x^j)SbjYevb@FrGLAbxaJv`VxIn4m2 z(Z76ErnjhY_uhQg2*g|sW@Fo)*Cuv_Mh0KB#7zW5e0-kwFp05{#KKcy5)X(I!?7yisoAS~qwO*P>8LOU2jSn-I+V{G%id z^3~3%b9!x(cJW&@VNcILV`shS*UguHW7{`lXNTO~jqIb_+Iv4C(GucPPKM!u@b3kZ zXNFEd9aY5Dj0>`}9@Y9KDV2pz2pU=PYYsA=#_OIVGq7q4XFokqSJ;?O*guD`d4H`# zaWgO*&YBx~RZ@kgI$hjEN%~q(jzALXErDoL^%C2QfR06wT0_99`urO|`|6mBZ>;OT zG`G!0&0@<@nR;&3pB4Kp+rL+zZhPP5Jb=b}2wA92E^bSPIks<@w$(npV3w%#wU3Hj zC?=$2)4$Bz(2TTP!PC@BrxQU!*^@@?GEy=ev0eOZyP)u4Ul%;5ovAEj+StO$do-~^ z)!3@mYuoUSVS1itfU&&myn(k7mZNlWN$hNq(QPk9vlIJLQPNXaR;4y*aq~%0&6C;X^5E-wAgElqoRdsj3? z8~alUJtdHKGln*JyC6_$WD<1CALk~}_a4#Extn(@{@G^G^;f#-Qlv_CMctYOJlEd0 zFC*X!bQfo}2Q##=fyg_m_!-uSm^81nF*8of*}JuqyDl-?w`wjd*iqbKt%cox!8qu= zyzq?c?%{rE&g$xI=gN5huvNp!T4%Kb>jGQNVU+P< z(sPRzfjH<^x1Yp8tluF>q9({C;_|siBm+ZCgW~@G} z%Yj5(+9lo*Qve?tnSa(I8FKrKPKtSWd8F0vjYuVV*M0WzOq{nyp@fKI*}Sq0=^7O= zZOPh7YD$yWyLxMhk7w#O&IdN`ZseTppd+PEI+v-N8|ScXZdc<_^}Sjn&wMVA1uh?y zVJ}z{we@lPZVX9fz@ac-7=ijn3NPCzEFrmuoY&MK#jc<(k8}cSM}g#7_T8ieg^;kd z)%uI89{}H~P1oyrO%Em?O(Vlp?cxPE-%Tly635{}wJ{{#Z@1;yEvGaaN1;1iG!`J` z+x(QF=X`HpOree*3a?(I8tw1#&i@oEvmUotN|l1Q4h3sI)7-0}axUT3Ou8Q%r)bLj zBD@6WyG0_pRxG(Hr0z~e^PuE!0R8+N+G(= z*9_E~W+SifMS{;A2br13QHrKsmse) zf*I`TCm^e}E#s8~rjmWVD?dl5n(vplKJoiXw@_X!wwW$9`OTpcoj+Q#WO(*b(!}=S zo4X%W#Ksie6?RtA)mDsC$u+(Wj*}3?T$O9zrKj__(QJ~d%@gqn;tYSjQIb0@Y`KfB z99>TKzX`wH#!SsXdFj+i-X&qOPf}C8Rvs-8h-r=&6$O)c_p&cva9a>M|t zlumWZoq<;nTaN1T2qW857gn!Ve;@l&wtrskgHs_QtTA9flwNT{Y?X$!_Z6LmV?r4% zTZk+wTOtC=5>^f`t1e^v7~49zP|@tHeCLMOMsBo>df@O08wJy~cO2(O<`t6?^`c)~ zfx^`?khN~(`ix=fB{RACZe@{vymZq|xs)vvjP_WLtn~Eg-qF^;f`RY(yX#OF_V|~< z*IV--*|c|X7*5k1nm1QF9^9~I;p^08Xe8qq{TvK#oS2Yxy+pH8_su2Qxbv>?#Y^r9 zw|tdYcyRkQ?KK{%3!kPu!a%dt!NEkHF?>{1219Geg#OcNad&Qwqr838_5}$0#uyr) z2gRjt?>T10V_LH{upMn`j2E5a)GgkeXfJm3hgo^@^qy(|66d(cqdb%$r#O;nWn%p~ z`ptvc*?ih71ARl3Qxn8?Ok$T^sXhsSdz+$4Hx~@l!-_8N=_;=GT)grw2um2xwW5Jr zIdKjZfd}>6A$X*()1s$idr!XCzcRHH$in@wWhJX^RKu)WPl-R4#G;4DYHwWW<9+y* zm0%a`J69F2cDu6mVy-#PFcr)&q4hO=9GhP@DA1f-pqe(x>(jo_=&GrvuO@L|6zp_0 zpDLVIv5)nd#EbZEPZ;87`X$CBE?GSuALBM4SW|PIOuEZKw!`}9qwo&+fF=8(u2!~s z1a%aOn}rDzxn)y6jj2eZiPC%gH1S#PRVnG`ZC7%7=dWEYD<&oned(?ln)7hMAnal_1h4q^?h+t*)wAsv_6U)uCf_(J7WMHZ^Vp;aWKm1@t^b8Gv& z64*YAFCaH+uLjSo-z56LD9K0KTQ{&4?fU4nf9yrNLS)U?_57Gq4&Q7R#MR5!pQNXg z?qV&RCC2m_gW*r#how7C8%o8TaaE-$&`A>gwxzTvF_bwej}{NNqGR}~wc!<+omXS* z+`yq)k}Gf?(lJoxVpQk))%%utA6+0pp906nf=Jo`*v5oEbz%J{XCmfDQ&tO14a01@ zJ-%0aPp&3W?b2rzPhr2F?380X6g`F28t5_dtr?_~NIVgB@ag2Y;rgox&)J1j>iIq- zPop8HeB}~G)1yAE9O~-lUDt{P^MVi*8tLWQd<&6;2LkpAP2%L@Zshxy{fE|lE+kXU znNf8`y9KW0RmT!>P^?6p-MxP1AcjTVv40<@Xenv%Y=%V8XSkSkn#cOBi4`SOF(leN zAU#j5bw+PZ3OCIxZJ=PeRq^@GT^^R#97N-|#F)uIv{2t2rgpBmE8ys}?eeO$1zb|K zu-K(nyRmr_qowb0(d<>ViQD<)F?)ONd((EEYtJJY<^+6G56CqWbBT&j35%MT+nSZe790Xl&aQ!GE2;3i$`M5woSRAcyaOo=F1UcH;Vy!Wb zAbwsHFN6mIy$-U#o8Ztcws>n0gcr^QREamY5LB0v`Ljac*9|T!M@KtBK0X&07hV@A zuPxq^4}wCW_`v*p{QNus2akiBjiZSxkB!4cpuHa*!RY>7%*KKDN1u4jY;k-TT|Nje znD4KKjt)p2B^<)o+JKH4HZiqza=gLC4>gCQ5aw_m3#18@2LeHx@PL7f#}tKzqTnWG z2rvr#S4(z3_3)RbfIon?pnwQ~JHeZHTXQEfH2wyc>`f(*td*^U;~!0fki2jKF1|lU z{$J=2ppkz)c0i4P4qh1G5mdG{$5^;Y0e%Y+elP^g14aSI-!=L91;J23r~nTbAqWNw z^Bv;^R1OrC{Ne8SPm2D;`BPC_ye2RaM9iHrb`FNz)`nL=FkTd#7Xp&BwR6K`EUkbU z0tQaIshgN%%uKK#X*V=T!`8yl#RQN3qf0;P{j(Zjz9ZHBB)R{hEKTf`mH&5X;&4Zk z{D@Cb%GS&YhqiH)m--K<(0@_u=4O9))6NNx{b42MW_)NY`lv?^fZ`!QKh4bqEo|{P z6JU;;*x6wL;T}zWK45}!i3kIKI$|8LXptW_D2{df;|7a4vME8ViH+qAE>|9Nw1tTi z){#r(4uls_;2*-rVnqJ9`B94RpPK%KYJQLa3kS5s_xJiCLIwISUH`p`{#i89Ho!{h za$5GLNhV5ciSYa7zgu866k}5#Z+sLx0#C z7Z}V1umN`YZ#e#({M`Rv_5-w_d8B3TKlFD+MC8wrxZ=?kRA3-7jp}Hv`{M$>`NIHw zA`8$TG=u;G2@Lq?0@?gQgYZL8Fu(=*GYt&zfsgS4H1JUv?=O77kD~ydUuh^f^!Ktz z-~jBed1|nj9DT{(ak8)c4LPNli{J@FsUuZ~yqe$mtGzj7-SLV-r5C|LwKi&os zj64dA`-KnK4uJ6KUuZz=F+Xs?{TCVp41qw7w~K%SDFJ@v1Ecs6(BJrA0x;kK;OBP1 zNI>|7se07FaA;%&@U2s zTviC+%VGwhICCBY&$87zXTkpMeZ;$Hxms0-MaS zaX`Ru1pn{t0$MuWE*$)uJ`gA<__*xBP$cwNSzvA;kI!*n9Q>$bWdS|`f!}llK>$1B zG1()I;z@s@0c#6C@>p3g0s%uElOGs`f})Pg9!Tf%yS>4H;=i^5=p6c+&H=q0mlYTR zJdFM(QyBkIT9%{hueAh>fI*Mj4A2Hl;5S=|nSs+v2aT=0e z;P*Ks0Ehl2D}K~b0L(A#qM(T5x&&kj=RejzKp#M7ek}{E2S+(9f2j|k{R>_43m}h; z4FZOOf!t@u$_jviJR`?wfcTE-7ntKfqSE7h0A%cMG$im{=s4fe;&hA#R48yvR=`36 zJHD;~>nZBDJpcg%H2iCQz(yf(lne6c`e$yyVZYN5zy@-h4}pXnU+WM^=usN~U+Y7{ zft>uuX(-fh?E=dDZN7l{kB<#lOAx=wiXRO7d0%kEn_#eLJe9C8h))CKjt2Hx5TClO zts@8+1V|mkCvRh63j&k{QU|_lN`VZ7Vd5wOAf>lBFcslQaTr(}EFr*;0@i5>DKHX_ jkQDj%97a??&PfMH6TIV(4IaYJ4}n3cI60+NWvKoKb3s*% diff --git a/lib/CPUs/J1/sim/tb_j1.do b/lib/CPUs/J1/sim/tb_j1.do deleted file mode 100644 index 4fa1a55..0000000 --- a/lib/CPUs/J1/sim/tb_j1.do +++ /dev/null @@ -1,15 +0,0 @@ -## NOTE: Do not edit this file. -## -vlib work -vcom -explicit -93 "../src/core/ram_2c_2r_2w.vhd" -vcom -explicit -93 "../src/core/j1.vhd" -vcom -explicit -93 "../src/tb_j1.vhd" - -vmap work - -vsim -t 1ps -lib work tb_j1 -do {tb_j1.wave.do} -view wave -view structure -view signals -run 1us diff --git a/lib/CPUs/J1/sim/tb_j1.wave.do b/lib/CPUs/J1/sim/tb_j1.wave.do deleted file mode 100644 index 58c0f66..0000000 --- a/lib/CPUs/J1/sim/tb_j1.wave.do +++ /dev/null @@ -1,58 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_j1/sys_clk_i -add wave -noupdate -format Logic /tb_j1/sys_rst_i -add wave -noupdate -format Literal -radix hexadecimal /tb_j1/io_din -add wave -noupdate -format Logic /tb_j1/io_rd -add wave -noupdate -format Logic /tb_j1/io_wr -add wave -noupdate -format Literal -radix hexadecimal /tb_j1/io_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_j1/io_dout -add wave -noupdate -format Literal -radix hexadecimal /tb_j1/inst_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_j1/inst_din -add wave -noupdate -format Literal -radix hexadecimal /tb_j1/data_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_j1/data_din -add wave -noupdate -format Literal -radix hexadecimal /tb_j1/data_dout -add wave -noupdate -format Logic /tb_j1/data_we -add wave -noupdate -format Logic /tb_j1/data_en -add wave -noupdate -divider {J1 internals} -add wave -noupdate -format Literal -radix hexadecimal /tb_j1/uut/insn -add wave -noupdate -format Literal -radix hexadecimal /tb_j1/uut/immediate -add wave -noupdate -format Literal -radix hexadecimal /tb_j1/uut/ramrd -add wave -noupdate -format Literal /tb_j1/uut/dsp -add wave -noupdate -format Literal /tb_j1/uut/dsp2 -add wave -noupdate -format Literal -radix hexadecimal /tb_j1/uut/st0 -add wave -noupdate -format Literal -radix hexadecimal /tb_j1/uut/st02 -add wave -noupdate -format Logic /tb_j1/uut/dstkw2 -add wave -noupdate -format Literal -radix hexadecimal /tb_j1/uut/pc -add wave -noupdate -format Literal -radix hexadecimal /tb_j1/uut/pc2 -add wave -noupdate -format Literal /tb_j1/uut/rsp -add wave -noupdate -format Literal /tb_j1/uut/rsp2 -add wave -noupdate -format Logic /tb_j1/uut/rstkw2 -add wave -noupdate -format Literal -radix hexadecimal /tb_j1/uut/rstkd2 -add wave -noupdate -format Logic /tb_j1/uut/ramwe2 -add wave -noupdate -format Literal -radix hexadecimal /tb_j1/uut/pc_plus_1 -add wave -noupdate -format Literal -radix hexadecimal /tb_j1/uut/dstack -add wave -noupdate -format Literal -radix hexadecimal /tb_j1/uut/rstack -add wave -noupdate -format Literal -radix hexadecimal /tb_j1/uut/st1 -add wave -noupdate -format Literal -radix hexadecimal /tb_j1/uut/rst0 -add wave -noupdate -format Literal /tb_j1/uut/st0sel -add wave -noupdate -format Logic /tb_j1/uut/is_alu -add wave -noupdate -format Logic /tb_j1/uut/is_lit -add wave -noupdate -format Literal /tb_j1/uut/dd -add wave -noupdate -format Literal /tb_j1/uut/rd -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {1600185 ps} 0} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -update -WaveRestoreZoom {0 ps} {1050 ns} diff --git a/lib/CPUs/J1/src/core/j1.v b/lib/CPUs/J1/src/core/j1.v deleted file mode 100644 index 861cb3c..0000000 --- a/lib/CPUs/J1/src/core/j1.v +++ /dev/null @@ -1,187 +0,0 @@ -module j1( - input sys_clk_i, input sys_rst_i, input [15:0] io_din, - output io_rd, output io_wr, output [15:0] io_addr, output [15:0] io_dout); - - wire [15:0] insn; - wire [15:0] immediate = { 1'b0, insn[14:0] }; - - wire [15:0] ramrd; - - reg [4:0] dsp; // Data stack pointer - reg [4:0] _dsp; - reg [15:0] st0; // Return stack pointer - reg [15:0] _st0; - wire _dstkW; // D stack write - - reg [12:0] pc; - reg [12:0] _pc; - reg [4:0] rsp; - reg [4:0] _rsp; - reg _rstkW; // R stack write - reg [15:0] _rstkD; - wire _ramWE; // RAM write enable - - wire [15:0] pc_plus_1; - assign pc_plus_1 = pc + 1; - - // The D and R stacks - reg [15:0] dstack[0:31]; - reg [15:0] rstack[0:31]; - always @(posedge sys_clk_i) - begin - if (_dstkW) - dstack[_dsp] = st0; - if (_rstkW) - rstack[_rsp] = _rstkD; - end - wire [15:0] st1 = dstack[dsp]; - wire [15:0] rst0 = rstack[rsp]; - - // st0sel is the ALU operation. For branch and call the operation - // is T, for 0branch it is N. For ALU ops it is loaded from the instruction - // field. - reg [3:0] st0sel; - always @* - begin - case (insn[14:13]) - 2'b00: st0sel = 0; // ubranch - 2'b10: st0sel = 0; // call - 2'b01: st0sel = 1; // 0branch - 2'b11: st0sel = insn[11:8]; // ALU - default: st0sel = 4'bxxxx; - endcase - end - -`define RAMS 3 - - genvar i; - -`define w (16 >> `RAMS) -`define w1 (`w - 1) - - generate - for (i = 0; i < (1 << `RAMS); i=i+1) begin : ram - // RAMB16_S18_S18 - RAMB16_S2_S2 - ram( - .DIA(0), - // .DIPA(0), - .DOA(insn[`w*i+`w1:`w*i]), - .WEA(0), - .ENA(1), - .CLKA(sys_clk_i), - .ADDRA({_pc}), - - .DIB(st1[`w*i+`w1:`w*i]), - // .DIPB(2'b0), - .WEB(_ramWE & (_st0[15:14] == 0)), - .ENB(|_st0[15:14] == 0), - .CLKB(sys_clk_i), - .ADDRB(_st0[15:1]), - .DOB(ramrd[`w*i+`w1:`w*i])); - end - endgenerate - - // Compute the new value of T. - always @* - begin - if (insn[15]) - _st0 = immediate; - else - case (st0sel) - 4'b0000: _st0 = st0; - 4'b0001: _st0 = st1; - 4'b0010: _st0 = st0 + st1; - 4'b0011: _st0 = st0 & st1; - 4'b0100: _st0 = st0 | st1; - 4'b0101: _st0 = st0 ^ st1; - 4'b0110: _st0 = ~st0; - 4'b0111: _st0 = {16{(st1 == st0)}}; - 4'b1000: _st0 = {16{($signed(st1) < $signed(st0))}}; - 4'b1001: _st0 = st1 >> st0[3:0]; - 4'b1010: _st0 = st0 - 1; - 4'b1011: _st0 = rst0; - 4'b1100: _st0 = |st0[15:14] ? io_din : ramrd; - 4'b1101: _st0 = st1 << st0[3:0]; - 4'b1110: _st0 = {rsp, 3'b000, dsp}; - 4'b1111: _st0 = {16{(st1 < st0)}}; - default: _st0 = 16'hxxxx; - endcase - end - - wire is_alu = (insn[15:13] == 3'b011); - wire is_lit = (insn[15]); - - assign io_rd = (is_alu & (insn[11:8] == 4'hc)); - assign io_wr = _ramWE; - assign io_addr = st0; - assign io_dout = st1; - - assign _ramWE = is_alu & insn[5]; - assign _dstkW = is_lit | (is_alu & insn[7]); - - wire [1:0] dd = insn[1:0]; // D stack delta - wire [1:0] rd = insn[3:2]; // R stack delta - - always @* - begin - if (is_lit) begin // literal - _dsp = dsp + 1; - _rsp = rsp; - _rstkW = 0; - _rstkD = _pc; - end else if (is_alu) begin - _dsp = dsp + {dd[1], dd[1], dd[1], dd}; - _rsp = rsp + {rd[1], rd[1], rd[1], rd}; - _rstkW = insn[6]; - _rstkD = st0; - end else begin // jump/call - // predicated jump is like DROP - if (insn[15:13] == 3'b001) begin - _dsp = dsp - 1; - end else begin - _dsp = dsp; - end - if (insn[15:13] == 3'b010) begin // call - _rsp = rsp + 1; - _rstkW = 1; - _rstkD = {pc_plus_1[14:0], 1'b0}; - end else begin - _rsp = rsp; - _rstkW = 0; - _rstkD = _pc; - end - end - end - - always @* - begin - if (sys_rst_i) - _pc = pc; - else - if ((insn[15:13] == 3'b000) | - ((insn[15:13] == 3'b001) & (|st0 == 0)) | - (insn[15:13] == 3'b010)) - _pc = insn[12:0]; - else if (is_alu & insn[12]) - _pc = rst0[15:1]; - else - _pc = pc_plus_1; - end - - always @(posedge sys_clk_i) - begin - if (sys_rst_i) begin - pc <= 0; - dsp <= 0; - st0 <= 0; - rsp <= 0; - end else begin - dsp <= _dsp; - pc <= _pc; - st0 <= _st0; - rsp <= _rsp; - end - end - -endmodule // j1 diff --git a/lib/CPUs/J1/src/core/j1.vhd b/lib/CPUs/J1/src/core/j1.vhd deleted file mode 100644 index d5c9f14..0000000 --- a/lib/CPUs/J1/src/core/j1.vhd +++ /dev/null @@ -1,282 +0,0 @@ -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -entity j1 is - Generic - ( - R_STACK_SIZE : natural := 32; - D_STACK_SIZE : natural := 32 - - ); - Port - ( - sys_clk_i : in std_logic; - sys_rst_i : in std_logic; - io_din : in unsigned(15 downto 0); - io_rd : out std_logic; - io_wr : out std_logic; - io_addr : out unsigned(15 downto 0); - io_dout : out unsigned(15 downto 0); - inst_din : in unsigned(15 downto 0); - inst_addr : out unsigned(12 downto 0); - data_addr : out unsigned(12 downto 0); - data_we : out std_logic; - data_en : out std_logic; - data_din : in unsigned(15 downto 0); - data_dout : out unsigned(15 downto 0) - - ); -end j1; - -architecture behave of j1 is - -signal insn : unsigned(15 downto 0); -signal immediate : unsigned(15 downto 0); -signal ramrd : unsigned(15 downto 0); - -signal dsp : unsigned(4 downto 0); -- Data stack pointer (register) -signal dsp2 : unsigned(4 downto 0); -- register -signal st0 : unsigned(15 downto 0); -- Return stack pointer (register) -signal st02 : unsigned(15 downto 0); -- register - -signal dstkW2 : std_logic; -- D stack write - -signal pc : unsigned(12 downto 0); -- register -signal pc2 : unsigned(12 downto 0); -- register -signal rsp : unsigned(4 downto 0); -- register -signal rsp2 : unsigned(4 downto 0); -- register - -signal rstkW2 : std_logic; -- register -signal rstkD2 : unsigned(15 downto 0); -- register -signal ramWE2 : std_logic; -- RAM write enable - -signal pc_plus_1 : unsigned(15 downto 0); - -type stack_t is array (integer range <>) of unsigned(15 downto 0); - -signal dstack : stack_t(0 to D_STACK_SIZE-1); -- register -signal rstack : stack_t(0 to R_STACK_SIZE-1); -- register - -signal st1 : unsigned(15 downto 0); -signal rst0 : unsigned(15 downto 0); - -signal st0sel : unsigned(3 downto 0); - -signal is_alu : BOOLEAN; -signal is_lit : BOOLEAN; - -signal dd : unsigned(1 downto 0); -- D stack delta -signal rd : unsigned(1 downto 0); -- R stack delta - -signal stack_ram_en : std_logic; -- helper for RAM R/W -signal stack_ram_we : std_logic; -- helper for RAM R/W - -begin - --- LINE 25: -pc_plus_1 <= ("000" & pc) + 1; - --- LINE 37: -st1 <= dstack(to_integer(dsp)); -rst0 <= rstack(to_integer(rsp)); -immediate <= '1' & insn(14 downto 0); - --- LINE 112: -is_alu <= (insn(15 downto 13) = "011"); -is_lit <= (insn(15) = '1'); - - --- LINE 115: -io_rd <= '1' when (is_alu and (insn(11 downto 8) = X"C")) else '0'; -io_wr <= ramWE2; -io_addr <= st0; -io_dout <= st1; -ramWE2 <= '1' when (is_alu and (insn(5) = '1')) else '0'; -dstkW2 <= '1' when (is_lit or (is_alu and insn(7) = '1')) else '0'; -dd <= insn(1 downto 0); -rd <= insn(3 downto 2); - - --- LINE 27: --- The D and R stacks -proc_d_and_r_stack: -process(sys_clk_i) -begin - if rising_edge(sys_clk_i) then - if dstkW2 = '1' then - dstack(to_integer(dsp2)) <= st0; - end if; - if rstkW2 = '1' then - rstack(to_integer(rsp2)) <= rstkD2; - end if; - - end if; -end process; - - --- LINE 40: --- st0sel is the ALU operation. For branch and call the operation --- is T, for 0branch it is N. For ALU ops it is loaded from the instruction --- field. - -proc_aluop_sel: -process(insn) -begin - - - case insn(14 downto 13) is - - when "00" => st0sel <= "0000"; - when "10" => st0sel <= "0000"; - when "01" => st0sel <= "0001"; - when "11" => st0sel <= insn(11 downto 8); - when others => st0sel <= "XXXX"; - - end case; -end process; - - --- LINE 55: --- define RAMS outside this module -insn <= inst_din; -inst_addr <= pc2(12 downto 0); -data_en <= not (st02(15) or st02(14)); -data_we <= ramWE2 and not (st02(15) or st02(14)); -ramrd <= data_din; -data_dout <= st1; -data_addr <= st02(13 downto 1); - - --- LINE 85: --- Compute the new value of T. -proc_alu: -process(insn, immediate, st0sel, st0, st1, rst0, rsp, dsp) -begin - - if insn(15) = '1' then - st02 <= immediate; - else - case st0sel is - - when "0000" => st02 <= st0; - when "0001" => st02 <= st1; - when "0010" => st02 <= st0 + st1; - when "0011" => st02 <= st0 and st1; - when "0100" => st02 <= st0 or st1; - when "0101" => st02 <= st0 xor st1; - when "0110" => st02 <= not st0; - when "0111" => - if st1 = st0 then - st02 <= X"FFFF"; - else - st02 <= X"0000"; - end if; - - when "1000" => - if signed(st1) < signed(st0) then - st02 <= X"FFFF"; - else - st02 <= X"0000"; - end if; - - when "1001" => st02 <= st1 srl to_integer(st0(3 downto 0)); - when "1010" => st02 <= st0 - 1; - when "1011" => st02 <= rst0; - when "1100" => - if st0(15) = '1' or st0(14) = '1' then -- LINE 104: ???? - st02 <= io_din; - else - st02 <= ramrd; - end if; - - when "1101" => st02 <= st1 sll to_integer(st0(3 downto 0)); - when "1110" => st02 <= "000" & rsp & "000" & dsp; -- LINE 106: ???? - when "1111" => - if st1 < st0 then - st02 <= X"FFFF"; - else - st02 <= X"0000"; - end if; - when others => st02 <= "XXXXXXXXXXXXXXXX"; - - end case; - end if; -end process; - --- LINE 126: -proc_stack_ctrl: -process(is_lit, is_alu, pc2, dd, rd, insn, st0, pc_plus_1, rsp, dsp) -begin - if is_lit then -- literal - dsp2 <= dsp + 1; - rsp2 <= rsp; - rstkW2 <= '0'; - rstkD2 <= "000" & pc2; - elsif is_alu then - dsp2 <= dsp + (dd(1) & dd(1) & dd(1) & dd); - rsp2 <= rsp + (rd(1) & rd(1) & rd(1) & rd); - rstkW2 <= insn(6); - rstkD2 <= st0; - else -- jump/call - -- predicated jump is like DROP - if insn(15 downto 13) = "001" then - dsp2 <= dsp - 1; - else - dsp2 <= dsp; -- *default - end if; - if insn(15 downto 13) = "010" then -- call - rsp2 <= rsp + 1; - rstkW2 <= '1'; - rstkD2 <= pc_plus_1(14 downto 0) & '0'; - else - rsp2 <= rsp; -- *default - rstkW2 <= '0'; -- *default - rstkD2 <= "000" & pc2; -- *default - end if; - - end if; -end process; - --- LINE 157: -proc_pc: -process(sys_rst_i, is_alu, insn, pc, st0, rst0, pc_plus_1) -begin - - if sys_rst_i = '1' then - pc2 <= pc; - else - if ((insn(15 downto 13) = "000") - or ((insn(15 downto 13) = "001") - and (st0 = X"0000")) - or (insn(15 downto 13) = "010")) then - pc2 <= insn(12 downto 0); - elsif is_alu and (insn(12) = '1') then -- return - pc2 <= rst0(13 downto 1); -- LINE 167: ???? - else - pc2 <= pc_plus_1(12 downto 0); -- LINE 169: truncation ???? - end if; - end if; -end process; - --- LINE 172: -proc_next: -process(sys_clk_i) -begin - - if rising_edge(sys_clk_i) then - if sys_rst_i = '1' then - pc <= (others => '0'); - dsp <= (others => '0'); - st0 <= (others => '0'); - rsp <= (others => '0'); - else - dsp <= dsp2; - pc <= pc2; - st0 <= st02; - rsp <= rsp2; - end if; - end if; -end process; - -end behave; diff --git a/lib/CPUs/J1/src/core/ram_2c_2r_2w.vhd b/lib/CPUs/J1/src/core/ram_2c_2r_2w.vhd deleted file mode 100644 index 23d8118..0000000 --- a/lib/CPUs/J1/src/core/ram_2c_2r_2w.vhd +++ /dev/null @@ -1,84 +0,0 @@ --------------------------------------------------------------------------- --- Project: Generic RAM. Infers BlockRAM for Xilinx --- This file: On-chip RAM --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -entity ram_2c_2r_2w is - Generic - ( - addr_width : integer := 3; - data_width : integer := 8 - ); - Port ( - clka : in STD_LOGIC; - clkb : in STD_LOGIC; - en_a : in STD_LOGIC; - en_b : in STD_LOGIC; - we_a : in STD_LOGIC; - we_b : in STD_LOGIC; - addr_a : in unsigned (addr_width-1 downto 0); - addr_b : in unsigned (addr_width-1 downto 0); - din_a : in unsigned (data_width-1 downto 0); - din_b : in unsigned (data_width-1 downto 0); - dout_a : out unsigned (data_width-1 downto 0); - dout_b : out unsigned (data_width-1 downto 0) - ); -end ram_2c_2r_2w; - -architecture Behavioral of ram_2c_2r_2w is - - constant depth : integer := 2**addr_width; - type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0); - shared variable RAM : RAMtype; - -begin - -process (clka) -begin -if clka'event and clka = '1' then - if en_a = '1' then - if we_a = '1' then - RAM(to_integer(addr_a)) := din_a; - end if; - dout_a <= RAM(to_integer(addr_a)); - end if; -end if; -end process; - -process (clkb) -begin -if clkb'event and clkb = '1' then - if en_b = '1' then - if we_b = '1' then - RAM(to_integer(addr_b)) := din_b; - end if; - dout_b <= RAM(to_integer(addr_b)); - end if; -end if; -end process; - - -end Behavioral; - diff --git a/lib/CPUs/J1/src/tb_j1.vhd b/lib/CPUs/J1/src/tb_j1.vhd deleted file mode 100644 index 8aa4c3c..0000000 --- a/lib/CPUs/J1/src/tb_j1.vhd +++ /dev/null @@ -1,150 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: testbench for embedded cpu with rom --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; -use std.textio.all; -- Imports the standard textio package. - -library work; - -ENTITY tb_j1 IS -END tb_j1; - -ARCHITECTURE behavior OF tb_j1 IS - - constant CLK_PERIOD : time := 10 ns; - - -- Inputs - signal sys_clk_i : std_logic := '0'; - signal sys_rst_i : std_logic := '1'; - signal io_din : unsigned(15 downto 0) := (others => '0'); - signal inst_din : unsigned(15 downto 0) := (others => '0'); - signal data_din : unsigned(15 downto 0) := (others => '0'); - - -- Outputs - signal io_rd : std_logic; - signal io_wr : std_logic; - signal io_addr : unsigned(15 downto 0); - signal io_dout : unsigned(15 downto 0); - signal data_dout : unsigned(15 downto 0); - signal inst_addr : unsigned(12 downto 0); - signal data_addr : unsigned(12 downto 0); - signal data_we : std_logic; - signal data_en : std_logic; - - type rom_t is array (integer range <>) of unsigned(15 downto 0); - - signal rom : rom_t(0 to 15) := - ( - X"8123", -- 0000 - X"0002", -- 0001 - X"0005", -- 0002 - X"8456", -- 0003 - X"4008", -- 0004 - X"0003", -- 0005 - X"0000", -- 0006 - X"0000", -- 0007 - X"8456", -- 0008 - X"8451", -- 0009 - X"7000", -- 000A - X"0000", -- 000B - X"0000", -- 000C - X"0000", -- 000D - X"0000", -- 000E - X"0000" -- 000F - ); - -BEGIN - - -- Instruction rom -process(sys_clk_i) -begin - if rising_edge(sys_clk_i) then - inst_din <= rom(to_integer(inst_addr(3 downto 0))); - end if; -end process; - -uut: entity work.j1 - PORT MAP - ( - sys_clk_i => sys_clk_i, - sys_rst_i => sys_rst_i, - io_din => io_din, - io_rd => io_rd, - io_wr => io_wr, - io_addr => io_addr, - inst_din => inst_din, - inst_addr => inst_addr, - data_addr => data_addr, - data_we => data_we, - data_en => data_en, - data_din => data_din, - data_dout => data_dout - ); - -inst_ram: entity work.ram_2c_2r_2w - GENERIC MAP - ( - addr_width => 13, - data_width => 16 - ) - PORT MAP( - clka => sys_clk_i, - clkb => sys_clk_i, - en_a => '1', - en_b => data_en, - we_a => '0', - we_b => data_we, - addr_a => (others => '0'), --inst_addr - addr_b => data_addr, - din_a => (others => '0'), - din_b => data_dout, - dout_a => open, -- inst_din - dout_b => data_din - ); - - -CLK_GEN: process - begin - wait for CLK_PERIOD/2; - sys_clk_i <= not sys_clk_i; - end process; - -STIMULUS: process - - begin - - wait for 3*CLK_PERIOD; - sys_rst_i <= '0'; - wait for 2*CLK_PERIOD; - - - wait for 1000*CLK_PERIOD; - - assert false report "Test finished" severity error; - wait; - - end process; - -end behavior; diff --git a/lib/CPUs/JCpu/asm/dctest.jsm b/lib/CPUs/JCpu/asm/dctest.jsm deleted file mode 100644 index 38d5947..0000000 --- a/lib/CPUs/JCpu/asm/dctest.jsm +++ /dev/null @@ -1,56 +0,0 @@ -; ------------------------------------------------- -; PROJECT "dctest" -; ------------------------------------------------- - -include "../../../jasm/cregs.inc.jsm" - -; ------------------------------------------------- - xmem - org 4 -konst: dc 0x01, 0x12,"A" -gap1: db 16 -mesg: dc "Hallo", 13,0x0A, 0 -name: dc "Jens",0 -msg1: dc "Welcome to JASM CPU",0 -msg2: dc "Ready",0 -msg3: dc "Testing",0 -msg4: dc "Passed",0 -msg5: dc "Error",0 -crlf: dc 0x0D, 0x0A - - org 0x00 -shit: db 4 - - cmem 0 - org 8 -cram1: db 16 -cram2: db 6 -cram3: db 4 - - cmem 1 -cram4: db 8 -cram5: db 8 - org 0x20 -cram6: db 8 -cram7: db 4 - -reg_revision: equ 0x00 -reg_testid: equ 0x01 - -; ------------------------------------------------- - code - org 0x000 -reset: jmp start - -; ------------------------------------------------- - org 0x001 -int_vec: jmp isr - -; ------------------------------------------------- - org 0x010 - -start: jmp start - -; ------------------------------------------------- -isr: reti - diff --git a/lib/CPUs/JCpu/asm/dctest.tcl b/lib/CPUs/JCpu/asm/dctest.tcl deleted file mode 100644 index ca88834..0000000 --- a/lib/CPUs/JCpu/asm/dctest.tcl +++ /dev/null @@ -1,212 +0,0 @@ -# ---------------------------------------------------------------------- -# Project: JCPU, a portable 8-bit RISC CPU written in VHDL -# This file: The ROM file for upload to target over JTAG -# -# Copyright (C) 2007 J. Ahrensfeld -# -# This program is free software: you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation, either version 3 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see . -# -# For questions and ideas, please contact the author at jens@jayfield.org -# -# --------------------------------------------------------------------- - -# --------------------------------------------------------------------- -# For Chipscope 9.1 -# --------------------------------------------------------------------- -# Source JTAG/TCL frame work -cd $env(CHIPSCOPE)\\bin\\nt -source csejtag.tcl - -namespace import ::chipscope::* - -# Platform USB Cable -set PLATFORM_USB_CABLE_ARGS [list "port=USB2" "frequency=6000000"] -# frequency="24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000" - -# Create session -set handle [::chipscope::csejtag_session create 0] - -# Open JTAG and lock -set open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS] -set lock_result [::chipscope::csejtag_target lock $handle 1000] - -set devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT] - -# Get Device ID -set devtype "Virtex-4SX" -set devid 2 -set irlength [::chipscope::csejtag_tap get_irlength $handle $devid] -set idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid] - -set CSE_OP $CSEJTAG_SHIFT_READWRITE -set CSE_ES $CSEJTAG_RUN_TEST_IDLE - -# Write Program -# JASM_ROM_INSERT_HERE -# Assembled from dctest.jsm -# --------------------------------------------------------------- -# Shift the USER2 Instruction (b1111000010) into the Instruction Register of FPGA -# User 1 -set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength "3C2"] - -# 0x000: JMP 0x010 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00030010" - -# 0x001: JMP 0x011 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00130011" - -# 0x002: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00200000" - -# 0x003: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00300000" - -# 0x004: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00400000" - -# 0x005: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00500000" - -# 0x006: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00600000" - -# 0x007: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00700000" - -# 0x008: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00800000" - -# 0x009: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00900000" - -# 0x00A: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00A00000" - -# 0x00B: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00B00000" - -# 0x00C: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00C00000" - -# 0x00D: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00D00000" - -# 0x00E: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00E00000" - -# 0x00F: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00F00000" - -# 0x010: JMP 0x010 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01030010" - -# 0x011: RETI -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0113F000" - -# Assembled from dctest.jsm -# --------------------------------------------------------------- -# Shift the USER2 Instruction (b1111000011) into the Instruction Register of FPGA -# User 2 -set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength "3C3"] - -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0000" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0100" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0200" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0300" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0401" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0512" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0641" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0700" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0800" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0900" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0A00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0B00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0C00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0D00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0E00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0F00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1000" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1100" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1200" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1300" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1400" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1500" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1600" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1748" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1861" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "196C" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1A6C" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1B6F" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1C0D" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1D0A" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1E00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1F4A" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2065" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "216E" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2273" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2300" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2457" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2565" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "266C" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2763" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "286F" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "296D" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2A65" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2B20" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2C74" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2D6F" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2E20" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2F4A" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3041" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3153" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "324D" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3320" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3443" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3550" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3655" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3700" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3852" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3965" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3A61" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3B64" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3C79" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3D00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3E54" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3F65" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4073" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4174" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4269" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "436E" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4467" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4500" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4650" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4761" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4873" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4973" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4A65" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4B64" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4C00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4D45" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4E72" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4F72" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "506F" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5172" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5200" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "530D" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "540A" - -::chipscope::csejtag_target unlock $handle -::chipscope::csejtag_target close $handle -::chipscope::csejtag_session destroy $handle -exit diff --git a/lib/CPUs/JCpu/asm/itest.jsm b/lib/CPUs/JCpu/asm/itest.jsm deleted file mode 100644 index 9666253..0000000 --- a/lib/CPUs/JCpu/asm/itest.jsm +++ /dev/null @@ -1,858 +0,0 @@ -; ------------------------------------------------- -; PROJECT "itest" -; ------------------------------------------------- - -include "../../../jasm/cregs.inc.jsm" - -; ------------------------------------------------- - xmem -msg: dc "Hallo", 0 -xram: db 256 - - cmem 0 -cram: db 256 - -reg_revision: equ 0x00 -reg_testid: equ 0x01 - -; ------------------------------------------------- - code - org 0x000 -reset: jmp start - -; ------------------------------------------------- - org 0x001 -int_vec: jmp isr - -; ------------------------------------------------- - org 0x010 - -start: call init - cin R0, (cpu_revision) - xout (reg_revision), R0 - - ; Test 0 - call test0 - - ; Test 1 - mov R0, 1 - xout (reg_testid), R0 - call test1 - - ; Test 2 - mov R0, 2 - xout (reg_testid), R0 - call test2 - - ; Test 3 - mov R0, 3 - xout (reg_testid), R0 - call test3 - - ; Test 4 - mov R0, 4 - xout (reg_testid), R0 - call test4 - - ; Test 5 - mov R0, 5 - xout (reg_testid), R0 - call test5 - - ; Test 6 - mov R0, 6 - xout (reg_testid), R0 - call test6 - - ; Test 7 - mov R0, 7 - xout (reg_testid), R0 - call test7 - - ; Test 8 - mov R0, 8 - xout (reg_testid), R0 - call test8 - - ; Test 9 - mov R0, 9 - xout (reg_testid), R0 - call test9 - - ; Test 10 - mov R0, 10 - xout (reg_testid), R0 - call test10 - - ; Test 11 - mov R0, 11 - xout (reg_testid), R0 - call test11 - - ; Test 12 - mov R0, 12 - xout (reg_testid), R0 - call test12 - - ; End of test - mov R0, 0xFF - xout (reg_testid), R0 - - jmp ok - -; ------------------------------------------------- -init: mov R0, 0 - mov R1, 0 - mov R2, 0 - mov R3, 0 - mov R4, 0 - mov R5, 0 - mov R6, 0 - mov R7, 0 - mov R8, 0 - mov R9, 0 - mov R10, 0 - mov R11, 0 - mov R12, 0 - mov R13, 0 - mov R14, 0 - mov R15, 0 - ret - -; ------------------------------------------------- -; MOV|R|K -; MOV|R|R -test0: mov R0, 0x10 - cmp R0, 0x10 - jne error - add R0, 1 - - mov R1, R0 - cmp R1, 0x11 - jne error - add R1, 1 - - mov R2, R1 - cmp R2, 0x12 - jne error - add R2, 1 - - mov R3, R2 - cmp R3, 0x13 - jne error - add R3, 1 - - mov R4, R3 - cmp R4, 0x14 - jne error - add R4, 1 - - mov R5, R4 - cmp R5, 0x15 - jne error - add R5, 1 - - mov R6, R5 - cmp R6, 0x16 - jne error - add R6, 1 - - mov R7, R6 - cmp R7, 0x17 - jne error - add R7, 1 - - mov R8, R7 - cmp R8, 0x18 - jne error - add R8, 1 - - mov R9, R8 - cmp R9, 0x19 - jne error - add R9, 1 - - mov R10, R9 - cmp R10, 0x1A - jne error - add R10, 1 - - mov R11, R10 - cmp R11, 0x1B - jne error - add R11, 1 - - mov R12, R11 - cmp R12, 0x1C - jne error - add R12, 1 - - mov R13, R12 - cmp R13, 0x1D - jne error - add R13, 1 - - mov R14, R13 - cmp R14, 0x1E - jne error - add R14, 1 - - mov R15, R14 - cmp R15, 0x1F - jne error - add R15, 1 - - ret - -; ------------------------------------------------- -; Instruction test -; TST|R -; CMP|R|K -; JNZ|K -; JC|K -; JNE|K -; JLT|K -; JGT|K -; JLE|K -; JGE|K -; JMP|K -test1: mov R0, 0 ; R0 <= 0 - tst R0 - jnz error - jc error - cmp R0, 0 - jne error - jlt error - jgt error - jle t1_ok10 - jmp error - -t1_ok10: jeq t1_ok20 - jmp error - -t1_ok20: jge t1_ok30 - jmp error - -t1_ok30: cmp R0, 0x55 - jeq error - jlt t1_ok40 - jmp error - -t1_ok40: jle t1_ok50 - jmp error - -t1_ok50: jge error - jgt error - - mov R0, 0x55 ; R0 <= 0xAA - tst R0 - jz error - jc error - - cmp R0, 0xAA - jeq error - jne t1_ok60 - jmp error - -t1_ok60: jlt t1_ok70 - jmp error - -t1_ok70: jle t1_ok80 - jmp error - -t1_ok80: jgt error - - cmp R0, 0x55 - jeq t1_ok90 - jmp error - -t1_ok90: jne error - jlt error - - jle t1_ok100 - jmp error - -t1_ok100: jgt error - jge t1_ok110 - jmp error - -t1_ok110: mov R0, 0xAA ; R0 <= 0x55 - tst R0 - jz error - jc error - - cmp R0, 0x55 - jeq error - jne t1_ok120 - jmp error - -t1_ok120: jgt t1_ok130 - jmp error - -t1_ok130: jge t1_ok140 - jmp error - -t1_ok140: jlt error - jle error - - ret - -; ------------------------------------------------- -; ADD|R|K -; ADDC|R|K -; ToDo: ADD|R|R -; ToDo: ADDC|R|R -; CMP|R|R -test2: mov R0, 0 - mov R1, 0 - mov R2, R0 - mov R3, R1 - -t2_loop: add R0, 0x01 - addc R1, 0x00 - add R2, 1 - cmp R2, 0 - jne t2_L1 - add R3, 1 - cmp R3, 0x02 -t2_L1: jne t2_loop - cmp R0, R2 - jne error - cmp R1, R3 - jne error - mov R0, 0 - - ret - -; ------------------------------------------------- -; SUB|R|K -; SUBC|R|K -; ToDo: SUB|R|R -; ToDo: SUBC|R|R -; CMP|R|R -test3: mov R0, 0x00 - mov R1, 0x03 - mov R2, R0 - mov R3, R1 - -t3_loop: sub R0, 0x01 - subc R1, 0x00 - sub R2, 1 - cmp R2, 0xFF - jne t3_L1 - sub R3, 1 - cmp R3, 0x00 -t3_L1: jne t3_loop - cmp R0, R2 - jne error - cmp R1, R3 - jne error - mov R0, 0 - - ret -; ------------------------------------------------- -; SUB|K|R -; SUB|R|R -; SUBC|R|R -; SUBC|K|R -; CMP|R|R -test4: mov R0, 0x03 - mov R1, 0x05 - sub 0x05, R0 - sub R1, 0x03 - cmp R0, R1 - jne error - mov R0, 0x03 - mov R1, 0x05 - sub R0, R1 - subc 0, R0 - cmp R0, 0x01 - jne error - add R0, 0 - subc R1, R0 - cmp R1, 0x04 - jne error - mov R0, 0 - - ret - -; ------------------------------------------------- -; MOVC|R|Ri -; MOVC|R|Ki -; MOVC|Ri|R -; MOVC|Ri|K -; MOVC|Ki|R -test5: mov R0, 1 - movc (cram+0x5A), R0 - dec R0 - movc (cram+0), R0 - movc R1, (cram+0x5A) - movc (R1), 0xA5 - movc R0, (R1) - movc R1, (R1) - add R1, 0xFF-0xA5 - movc R0, (R1) -t5_loop1: movc (R0), R0 - movc R2, (R0) - cmp R2, R0 - jne error - movc (R2), R1 - movc R2, (R2) - cmp R2, R1 - jne error - dec R1 - inc R0 - jnz t5_loop1 - - ret - -; ------------------------------------------------- -; MOVX|R|Ri -; MOVX|R|Ki -; MOVX|Ri|R -; MOVX|Ri|K -; MOVX|Ki|R -test6: mov R0, 1 - movx (xram+0x5A), R0 - dec R0 - movx (xram+0), R0 - movx R1, (xram+0x5A) - movx (R1), 0xA5 - movx R0, (R1) - movx R1, (R1) - add R1, 0xFF-0xA5 - movx R0, (R1) -t6_loop1: movx (R0), R0 - movx R2, (R0) - cmp R2, R0 - jne error - movx (R2), R1 - movx R2, (R2) - cmp R2, R1 - jne error - dec R1 - inc R0 - jnz t6_loop1 - - ret - -; ------------------------------------------------- -; PUSH|R -; POP|R -test7: mov R0, 0xAA - mov R1, 0 -t7_loop1: push R0 - inc R0 - dec R1 - jnz t7_loop1 -t7_loop2: pop R0 - dec R1 - jnz t7_loop2 - cmp R0, 0xAA - jne error - - ret - -; ------------------------------------------------- -; JMP|K -; CALL|K -; RET -test8: mov R0, 0x55 - push R0 - mov R0, 0 - mov R1, 0xFF - call t8_rec - pop R0 - cmp R0, 0x55 - jne error - - ; Stack manipulations 1 - mov R0, return1'high - mov R1, return1'low - cout (cpu_stack_high), R0 - push R1 - - mov R0, init'high - mov R1, init'low - cout (cpu_stack_high), R0 - push R1 - ret - - ; Stack manipulations 2 -return1: mov R0, return2'high - mov R1, return2'low - cout (cpu_stack_high), R0 - push R1 - - mov R0, init'high - mov R1, init'low - cout (cpu_stack_high), R0 - push R1 -return2: ret - -t8_rec: cmp R0, R1 - jeq ex_t8_rec - inc R0 - jmp t8_rstub -ex_t8_rec: dec R0 - dec R1 - ret - -t8_rstub: call t8_rec - jmp ex_t8_rec - -; ------------------------------------------------- -; SWAP|R -; SHL|R -; SHR|R -; ROL|R -; ROR|R -; ROLC|R -; RORC|R -test9: mov R0, 0xA5 ; SWAP test - mov R1, 0x5A - swap R0 - cmp R0, 0x5A - jne error - swap R0 - cmp R0, 0xA5 - jne error - mov R0, 0xD2 - swap R0 - cmp R0, 0x2D - jne error - swap R1 - cmp R0, 0x2D - jne error - cmp R1, 0xA5 - jne error - - mov R0, 0x2D - shl R0 ; SHL test - cmp R0, 0x5A - jne error - shl R0 - cmp R0, 0xB4 - jne error - shl R0 - cmp R0, 0x68 - jne error - shl R0 - cmp R0, 0xD0 - jne error - shl R0 - cmp R0, 0xA0 - jne error - shl R0 - cmp R0, 0x40 - jne error - shl R0 - cmp R0, 0x80 - jne error - shl R0 - cmp R0, 0x00 - jne error - - mov R1, 0x84 - shr R1 ; SHR test - cmp R1, 0x42 - jne error - shr R1 - cmp R1, 0x21 - jne error - shr R1 - cmp R1, 0x10 - jne error - shr R1 - cmp R1, 0x08 - jne error - shr R1 - cmp R1, 0x04 - jne error - shr R1 - cmp R1, 0x02 - jne error - shr R1 - cmp R1, 0x01 - jne error - shr R1 - cmp R1, 0x00 - jne error - - mov R0, 0xC5 ; ROL test - rol R0 - cmp R0, 0x8B - jne error - rol R0 - cmp R0, 0x17 - jne error - rol R0 - cmp R0, 0x2E - jne error - rol R0 - cmp R0, 0x5C - jne error - rol R0 - cmp R0, 0xB8 - jne error - rol R0 - cmp R0, 0x71 - jne error - rol R0 - cmp R0, 0xE2 - jne error - rol R0 - cmp R0, 0xC5 - jne error - - mov R1, 0x63 ; ROR test - ror R1 - cmp R1, 0xB1 - jne error - ror R1 - cmp R1, 0xD8 - jne error - ror R1 - cmp R1, 0x6C - jne error - ror R1 - cmp R1, 0x36 - jne error - ror R1 - cmp R1, 0x1B - jne error - ror R1 - cmp R1, 0x8D - jne error - ror R1 - cmp R1, 0xC6 - jne error - ror R1 - cmp R1, 0x63 - jne error - - - xor R0, R0 ; ROLC generate - mov R0, 0xC5 - rolc R0 - push R0 - rolc R0 - push R0 - rolc R0 - push R0 - rolc R0 - push R0 - rolc R0 - push R0 - rolc R0 - push R0 - rolc R0 - push R0 - rolc R0 - push R0 - rolc R0 - - cmp R0, 0xC5 ; ROLC verify - jne error - pop R0 - cmp R0, 0x62 - jne error - pop R0 - cmp R0, 0xB1 - jne error - pop R0 - cmp R0, 0x58 - jne error - pop R0 - cmp R0, 0xAC - jne error - pop R0 - cmp R0, 0x56 - jne error - pop R0 - cmp R0, 0x2B - jne error - pop R0 - cmp R0, 0x15 - jne error - pop R0 - cmp R0, 0x8A - jne error - - xor R1, R1 ; RORC generate - mov R1, 0x63 - rorc R1 - push R1 - rorc R1 - push R1 - rorc R1 - push R1 - rorc R1 - push R1 - rorc R1 - push R1 - rorc R1 - push R1 - rorc R1 - push R1 - rorc R1 - push R1 - rorc R1 - - cmp R1, 0x63 ; RORC verify - jne error - pop R1 - cmp R1, 0xC6 - jne error - pop R1 - cmp R1, 0x8C - jne error - pop R1 - cmp R1, 0x19 - jne error - pop R1 - cmp R1, 0x33 - jne error - pop R1 - cmp R1, 0x66 - jne error - pop R1 - cmp R1, 0xCC - jne error - pop R1 - cmp R1, 0x98 - jne error - pop R1 - cmp R1, 0x31 - jne error - - ret - -; ------------------------------------------------- -; AND|R|R -; AND|R|K -; OR|R|R -; OR|R|K -; XOR|R|R -; XOR|R|K -test10: mov R0, 0xA5 ; AND - swap R0 - push R0 - and R0, 0x0F - cmp R0, 0x0A - jne error - pop R0 - push R0 - and R0, 0x0F - cmp R0, 0x0A - pop R1 - jne error - swap R1 - mov R2, 0x0F - and R1, R2 - cmp R1, 0x05 - jne error - - mov R0, 0x05 ; OR - mov R2, 0xA0 - swap R0 - or R2, R0 - cmp R2, 0xF0 - jne error - swap R0 - or R0, 0x50 - cmp R0, 0x55 - jne error - - mov R1, 0x01 - mov R0, 0x01 - xor R0, 0x01 - jnz error - xor R0, R1 - cmp R0, 0x01 - jne error - - ret - -; ------------------------------------------------- -test11: - mov R0, 0x03 - cout (cpu_int_ctrl), R0 - - xin R0, (2) - or R0, 1 - xout (2), R0 - nop - nop - nop - nop - nop - nop - xin R0, (2) - and R0, 0xFE - xout (2), R0 - nop - nop - nop - nop - - cin R0, (cpu_int_ctrl) - or R0, 0x80 - cout (cpu_int_ctrl), R0 - nop - cin R0, (cpu_int_ctrl) - or R0, 0x80 - cout (cpu_int_ctrl), R0 - nop - cin R0, (cpu_int_ctrl) - or R0, 0x80 - cout (cpu_int_ctrl), R0 - nop - cin R0, (cpu_int_ctrl) - or R0, 0x80 - cout (cpu_int_ctrl), R0 - nop - nop - nop - nop - nop - nop - nop - nop - nop - ret - -; ------------------------------------------------- -; Tests clrc, setc -test12: sub R0, 0 - jc error - setc - jnc error - nop - sub R0, 0 - jc error - - mov R0, 0 - clrc - jc error - setc - jnc error - nop - clrc - jc error - ret - -; ------------------------------------------------- -isr: inc R14 - reti - -; ------------------------------------------------- - org 0x3FF -error: jmp error - -; ------------------------------------------------- - org 0x2FF -ok: jmp ok - -; ------------------------------------------------- - \ No newline at end of file diff --git a/lib/CPUs/JCpu/asm/itest.tcl b/lib/CPUs/JCpu/asm/itest.tcl deleted file mode 100644 index 3724ca6..0000000 --- a/lib/CPUs/JCpu/asm/itest.tcl +++ /dev/null @@ -1,3407 +0,0 @@ -# ---------------------------------------------------------------------- -# Project: JCPU, a portable 8-bit RISC CPU written in VHDL -# This file: The ROM file for upload to target over JTAG -# -# Copyright (C) 2007 J. Ahrensfeld -# -# This program is free software: you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation, either version 3 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see . -# -# For questions and ideas, please contact the author at jens@jayfield.org -# -# --------------------------------------------------------------------- - -# --------------------------------------------------------------------- -# For Chipscope 9.1 -# --------------------------------------------------------------------- -# Source JTAG/TCL frame work -cd $env(CHIPSCOPE)\\bin\\nt -source csejtag.tcl - -namespace import ::chipscope::* - -# Platform USB Cable -set PLATFORM_USB_CABLE_ARGS [list "port=USB2" "frequency=6000000"] -# frequency="24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000" - -# Create session -set handle [::chipscope::csejtag_session create 0] - -# Open JTAG and lock -set open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS] -set lock_result [::chipscope::csejtag_target lock $handle 1000] - -set devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT] - -# Get Device ID -set devtype "Virtex-4SX" -set devid 2 -set irlength [::chipscope::csejtag_tap get_irlength $handle $devid] -set idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid] - -set CSE_OP $CSEJTAG_SHIFT_READWRITE -set CSE_ES $CSEJTAG_RUN_TEST_IDLE - -# Write Program -# JASM_ROM_INSERT_HERE -# Assembled from itest.jsm -# --------------------------------------------------------------- -# Shift the USER2 Instruction (b1111000010) into the Instruction Register of FPGA -# User 1 -set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength "3C2"] - -# 0x000: JMP 0x010 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00030010" - -# 0x001: JMP 0x288 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00130288" - -# 0x002: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00200000" - -# 0x003: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00300000" - -# 0x004: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00400000" - -# 0x005: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00500000" - -# 0x006: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00600000" - -# 0x007: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00700000" - -# 0x008: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00800000" - -# 0x009: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00900000" - -# 0x00A: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00A00000" - -# 0x00B: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00B00000" - -# 0x00C: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00C00000" - -# 0x00D: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00D00000" - -# 0x00E: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00E00000" - -# 0x00F: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00F00000" - -# 0x010: CALL 0x03B -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0103B03B" - -# 0x011: CIN R00, (0x00) -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01129000" - -# 0x012: XOUT (0x00), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01224000" - -# 0x013: CALL 0x04C -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0133B04C" - -# 0x014: MOV R00, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01403010" - -# 0x015: XOUT (0x01), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01524010" - -# 0x016: CALL 0x08D -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0163B08D" - -# 0x017: MOV R00, 0x02 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01703020" - -# 0x018: XOUT (0x01), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01824010" - -# 0x019: CALL 0x0C9 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0193B0C9" - -# 0x01A: MOV R00, 0x03 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01A03030" - -# 0x01B: XOUT (0x01), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01B24010" - -# 0x01C: CALL 0x0DB -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01C3B0DB" - -# 0x01D: MOV R00, 0x04 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01D03040" - -# 0x01E: XOUT (0x01), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01E24010" - -# 0x01F: CALL 0x0ED -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01F3B0ED" - -# 0x020: MOV R00, 0x05 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02003050" - -# 0x021: XOUT (0x01), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02124010" - -# 0x022: CALL 0x0FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0223B0FF" - -# 0x023: MOV R00, 0x06 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02303060" - -# 0x024: XOUT (0x01), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02424010" - -# 0x025: CALL 0x115 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0253B115" - -# 0x026: MOV R00, 0x07 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02603070" - -# 0x027: XOUT (0x01), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02724010" - -# 0x028: CALL 0x12B -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0283B12B" - -# 0x029: MOV R00, 0x08 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02903080" - -# 0x02A: XOUT (0x01), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02A24010" - -# 0x02B: CALL 0x137 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02B3B137" - -# 0x02C: MOV R00, 0x09 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02C03090" - -# 0x02D: XOUT (0x01), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02D24010" - -# 0x02E: CALL 0x15A -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02E3B15A" - -# 0x02F: MOV R00, 0x0A -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02F030A0" - -# 0x030: XOUT (0x01), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03024010" - -# 0x031: CALL 0x22A -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0313B22A" - -# 0x032: MOV R00, 0x0B -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "032030B0" - -# 0x033: XOUT (0x01), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03324010" - -# 0x034: CALL 0x24D -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0343B24D" - -# 0x035: MOV R00, 0x0C -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "035030C0" - -# 0x036: XOUT (0x01), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03624010" - -# 0x037: CALL 0x278 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0373B278" - -# 0x038: MOV R00, 0xFF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03803FF0" - -# 0x039: XOUT (0x01), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03924010" - -# 0x03A: JMP 0x2FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03A302FF" - -# 0x03B: MOV R00, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03B03000" - -# 0x03C: MOV R01, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03C03001" - -# 0x03D: MOV R02, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03D03002" - -# 0x03E: MOV R03, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03E03003" - -# 0x03F: MOV R04, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03F03004" - -# 0x040: MOV R05, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04003005" - -# 0x041: MOV R06, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04103006" - -# 0x042: MOV R07, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04203007" - -# 0x043: MOV R08, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04303008" - -# 0x044: MOV R09, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04403009" - -# 0x045: MOV R10, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0450300A" - -# 0x046: MOV R11, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0460300B" - -# 0x047: MOV R12, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0470300C" - -# 0x048: MOV R13, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0480300D" - -# 0x049: MOV R14, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0490300E" - -# 0x04A: MOV R15, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04A0300F" - -# 0x04B: RET -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04B3E000" - -# 0x04C: MOV R00, 0x10 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04C03100" - -# 0x04D: CMP R00, 0x10 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04D0F100" - -# 0x04E: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04E3A3FF" - -# 0x04F: ADD R00, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04F11010" - -# 0x050: MOV R01, R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05002001" - -# 0x051: CMP R01, 0x11 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0510F111" - -# 0x052: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0523A3FF" - -# 0x053: ADD R01, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05311011" - -# 0x054: MOV R02, R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05402012" - -# 0x055: CMP R02, 0x12 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0550F122" - -# 0x056: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0563A3FF" - -# 0x057: ADD R02, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05711012" - -# 0x058: MOV R03, R02 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05802023" - -# 0x059: CMP R03, 0x13 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0590F133" - -# 0x05A: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05A3A3FF" - -# 0x05B: ADD R03, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05B11013" - -# 0x05C: MOV R04, R03 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05C02034" - -# 0x05D: CMP R04, 0x14 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05D0F144" - -# 0x05E: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05E3A3FF" - -# 0x05F: ADD R04, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05F11014" - -# 0x060: MOV R05, R04 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06002045" - -# 0x061: CMP R05, 0x15 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0610F155" - -# 0x062: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0623A3FF" - -# 0x063: ADD R05, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06311015" - -# 0x064: MOV R06, R05 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06402056" - -# 0x065: CMP R06, 0x16 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0650F166" - -# 0x066: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0663A3FF" - -# 0x067: ADD R06, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06711016" - -# 0x068: MOV R07, R06 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06802067" - -# 0x069: CMP R07, 0x17 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0690F177" - -# 0x06A: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06A3A3FF" - -# 0x06B: ADD R07, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06B11017" - -# 0x06C: MOV R08, R07 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06C02078" - -# 0x06D: CMP R08, 0x18 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06D0F188" - -# 0x06E: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06E3A3FF" - -# 0x06F: ADD R08, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06F11018" - -# 0x070: MOV R09, R08 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "07002089" - -# 0x071: CMP R09, 0x19 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0710F199" - -# 0x072: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0723A3FF" - -# 0x073: ADD R09, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "07311019" - -# 0x074: MOV R10, R09 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0740209A" - -# 0x075: CMP R10, 0x1A -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0750F1AA" - -# 0x076: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0763A3FF" - -# 0x077: ADD R10, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0771101A" - -# 0x078: MOV R11, R10 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "078020AB" - -# 0x079: CMP R11, 0x1B -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0790F1BB" - -# 0x07A: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "07A3A3FF" - -# 0x07B: ADD R11, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "07B1101B" - -# 0x07C: MOV R12, R11 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "07C020BC" - -# 0x07D: CMP R12, 0x1C -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "07D0F1CC" - -# 0x07E: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "07E3A3FF" - -# 0x07F: ADD R12, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "07F1101C" - -# 0x080: MOV R13, R12 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "080020CD" - -# 0x081: CMP R13, 0x1D -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0810F1DD" - -# 0x082: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0823A3FF" - -# 0x083: ADD R13, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0831101D" - -# 0x084: MOV R14, R13 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "084020DE" - -# 0x085: CMP R14, 0x1E -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0850F1EE" - -# 0x086: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0863A3FF" - -# 0x087: ADD R14, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0871101E" - -# 0x088: MOV R15, R14 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "088020EF" - -# 0x089: CMP R15, 0x1F -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0890F1FF" - -# 0x08A: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "08A3A3FF" - -# 0x08B: ADD R15, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "08B1101F" - -# 0x08C: RET -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "08C3E000" - -# 0x08D: MOV R00, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "08D03000" - -# 0x08E: TST R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "08E0F000" - -# 0x08F: JNZ 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "08F323FF" - -# 0x090: JC 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "090333FF" - -# 0x091: CMP R00, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0910F000" - -# 0x092: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0923A3FF" - -# 0x093: JLT 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "093353FF" - -# 0x094: JGT 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "094363FF" - -# 0x095: JLE 0x097 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "09537097" - -# 0x096: JMP 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "096303FF" - -# 0x097: JEQ 0x099 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "09739099" - -# 0x098: JMP 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "098303FF" - -# 0x099: JGE 0x09B -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0993809B" - -# 0x09A: JMP 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "09A303FF" - -# 0x09B: CMP R00, 0x55 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "09B0F550" - -# 0x09C: JEQ 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "09C393FF" - -# 0x09D: JLT 0x09F -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "09D3509F" - -# 0x09E: JMP 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "09E303FF" - -# 0x09F: JLE 0x0A1 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "09F370A1" - -# 0x0A0: JMP 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0A0303FF" - -# 0x0A1: JGE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0A1383FF" - -# 0x0A2: JGT 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0A2363FF" - -# 0x0A3: MOV R00, 0x55 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0A303550" - -# 0x0A4: TST R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0A40F000" - -# 0x0A5: JZ 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0A5313FF" - -# 0x0A6: JC 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0A6333FF" - -# 0x0A7: CMP R00, 0xAA -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0A70FAA0" - -# 0x0A8: JEQ 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0A8393FF" - -# 0x0A9: JNE 0x0AB -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0A93A0AB" - -# 0x0AA: JMP 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0AA303FF" - -# 0x0AB: JLT 0x0AD -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0AB350AD" - -# 0x0AC: JMP 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0AC303FF" - -# 0x0AD: JLE 0x0AF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0AD370AF" - -# 0x0AE: JMP 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0AE303FF" - -# 0x0AF: JGT 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0AF363FF" - -# 0x0B0: CMP R00, 0x55 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0B00F550" - -# 0x0B1: JEQ 0x0B3 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0B1390B3" - -# 0x0B2: JMP 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0B2303FF" - -# 0x0B3: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0B33A3FF" - -# 0x0B4: JLT 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0B4353FF" - -# 0x0B5: JLE 0x0B7 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0B5370B7" - -# 0x0B6: JMP 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0B6303FF" - -# 0x0B7: JGT 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0B7363FF" - -# 0x0B8: JGE 0x0BA -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0B8380BA" - -# 0x0B9: JMP 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0B9303FF" - -# 0x0BA: MOV R00, 0xAA -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0BA03AA0" - -# 0x0BB: TST R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0BB0F000" - -# 0x0BC: JZ 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0BC313FF" - -# 0x0BD: JC 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0BD333FF" - -# 0x0BE: CMP R00, 0x55 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0BE0F550" - -# 0x0BF: JEQ 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0BF393FF" - -# 0x0C0: JNE 0x0C2 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0C03A0C2" - -# 0x0C1: JMP 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0C1303FF" - -# 0x0C2: JGT 0x0C4 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0C2360C4" - -# 0x0C3: JMP 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0C3303FF" - -# 0x0C4: JGE 0x0C6 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0C4380C6" - -# 0x0C5: JMP 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0C5303FF" - -# 0x0C6: JLT 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0C6353FF" - -# 0x0C7: JLE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0C7373FF" - -# 0x0C8: RET -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0C83E000" - -# 0x0C9: MOV R00, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0C903000" - -# 0x0CA: MOV R01, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0CA03001" - -# 0x0CB: MOV R02, R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0CB02002" - -# 0x0CC: MOV R03, R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0CC02013" - -# 0x0CD: ADD R00, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0CD11010" - -# 0x0CE: ADDC R01, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0CE13001" - -# 0x0CF: ADD R02, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0CF11012" - -# 0x0D0: CMP R02, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0D00F002" - -# 0x0D1: JNE 0x0D4 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0D13A0D4" - -# 0x0D2: ADD R03, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0D211013" - -# 0x0D3: CMP R03, 0x02 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0D30F023" - -# 0x0D4: JNE 0x0CD -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0D43A0CD" - -# 0x0D5: CMP R00, R02 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0D50E020" - -# 0x0D6: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0D63A3FF" - -# 0x0D7: CMP R01, R03 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0D70E031" - -# 0x0D8: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0D83A3FF" - -# 0x0D9: MOV R00, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0D903000" - -# 0x0DA: RET -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0DA3E000" - -# 0x0DB: MOV R00, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0DB03000" - -# 0x0DC: MOV R01, 0x03 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0DC03031" - -# 0x0DD: MOV R02, R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0DD02002" - -# 0x0DE: MOV R03, R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0DE02013" - -# 0x0DF: SUB R00, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0DF15010" - -# 0x0E0: SUBC R01, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0E017001" - -# 0x0E1: SUB R02, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0E115012" - -# 0x0E2: CMP R02, 0xFF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0E20FFF2" - -# 0x0E3: JNE 0x0E6 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0E33A0E6" - -# 0x0E4: SUB R03, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0E415013" - -# 0x0E5: CMP R03, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0E50F003" - -# 0x0E6: JNE 0x0DF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0E63A0DF" - -# 0x0E7: CMP R00, R02 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0E70E020" - -# 0x0E8: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0E83A3FF" - -# 0x0E9: CMP R01, R03 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0E90E031" - -# 0x0EA: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0EA3A3FF" - -# 0x0EB: MOV R00, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0EB03000" - -# 0x0EC: RET -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0EC3E000" - -# 0x0ED: MOV R00, 0x03 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0ED03030" - -# 0x0EE: MOV R01, 0x05 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0EE03051" - -# 0x0EF: SUB 0x05, R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0EF2E050" - -# 0x0F0: SUB R01, 0x03 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0F015031" - -# 0x0F1: CMP R00, R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0F10E010" - -# 0x0F2: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0F23A3FF" - -# 0x0F3: MOV R00, 0x03 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0F303030" - -# 0x0F4: MOV R01, 0x05 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0F403051" - -# 0x0F5: SUB R00, R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0F514010" - -# 0x0F6: SUBC 0x00, R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0F62F000" - -# 0x0F7: CMP R00, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0F70F010" - -# 0x0F8: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0F83A3FF" - -# 0x0F9: ADD R00, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0F911000" - -# 0x0FA: SUBC R01, R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0FA16001" - -# 0x0FB: CMP R01, 0x04 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0FB0F041" - -# 0x0FC: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0FC3A3FF" - -# 0x0FD: MOV R00, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0FD03000" - -# 0x0FE: RET -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0FE3E000" - -# 0x0FF: MOV R00, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0FF03010" - -# 0x100: MOVC (0x5A), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1000D5A0" - -# 0x101: DEC R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "10115010" - -# 0x102: MOVC (0x00), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1020D000" - -# 0x103: MOVC R01, (0x5A) -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1030A5A1" - -# 0x104: MOVC (R01), 0xA5 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1040CA51" - -# 0x105: MOVC R00, (R01) -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "10509010" - -# 0x106: MOVC R01, (R01) -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "10609011" - -# 0x107: ADD R01, 0x5A -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "107115A1" - -# 0x108: MOVC R00, (R01) -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "10809010" - -# 0x109: MOVC (R00), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1090B000" - -# 0x10A: MOVC R02, (R00) -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "10A09002" - -# 0x10B: CMP R02, R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "10B0E002" - -# 0x10C: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "10C3A3FF" - -# 0x10D: MOVC (R01), R02 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "10D0B021" - -# 0x10E: MOVC R02, (R02) -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "10E09022" - -# 0x10F: CMP R02, R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "10F0E012" - -# 0x110: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1103A3FF" - -# 0x111: DEC R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "11115011" - -# 0x112: INC R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "11211010" - -# 0x113: JNZ 0x109 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "11332109" - -# 0x114: RET -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1143E000" - -# 0x115: MOV R00, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "11503010" - -# 0x116: MOVX (0x60), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "11608600" - -# 0x117: DEC R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "11715010" - -# 0x118: MOVX (0x06), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "11808060" - -# 0x119: MOVX R01, (0x60) -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "11905601" - -# 0x11A: MOVX (R01), 0xA5 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "11A07A51" - -# 0x11B: MOVX R00, (R01) -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "11B04010" - -# 0x11C: MOVX R01, (R01) -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "11C04011" - -# 0x11D: ADD R01, 0x5A -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "11D115A1" - -# 0x11E: MOVX R00, (R01) -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "11E04010" - -# 0x11F: MOVX (R00), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "11F06000" - -# 0x120: MOVX R02, (R00) -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "12004002" - -# 0x121: CMP R02, R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1210E002" - -# 0x122: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1223A3FF" - -# 0x123: MOVX (R01), R02 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "12306021" - -# 0x124: MOVX R02, (R02) -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "12404022" - -# 0x125: CMP R02, R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1250E012" - -# 0x126: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1263A3FF" - -# 0x127: DEC R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "12715011" - -# 0x128: INC R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "12811010" - -# 0x129: JNZ 0x11F -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1293211F" - -# 0x12A: RET -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "12A3E000" - -# 0x12B: MOV R00, 0xAA -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "12B03AA0" - -# 0x12C: MOV R01, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "12C03001" - -# 0x12D: PUSH R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "12D3C000" - -# 0x12E: INC R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "12E11010" - -# 0x12F: DEC R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "12F15011" - -# 0x130: JNZ 0x12D -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1303212D" - -# 0x131: POP R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1313D000" - -# 0x132: DEC R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "13215011" - -# 0x133: JNZ 0x131 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "13332131" - -# 0x134: CMP R00, 0xAA -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1340FAA0" - -# 0x135: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1353A3FF" - -# 0x136: RET -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1363E000" - -# 0x137: MOV R00, 0x55 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "13703550" - -# 0x138: PUSH R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1383C000" - -# 0x139: MOV R00, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "13903000" - -# 0x13A: MOV R01, 0xFF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "13A03FF1" - -# 0x13B: CALL 0x151 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "13B3B151" - -# 0x13C: POP R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "13C3D000" - -# 0x13D: CMP R00, 0x55 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "13D0F550" - -# 0x13E: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "13E3A3FF" - -# 0x13F: MOV R00, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "13F03010" - -# 0x140: MOV R01, 0x48 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "14003481" - -# 0x141: COUT (0x05), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "14126050" - -# 0x142: PUSH R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1423C001" - -# 0x143: MOV R00, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "14303000" - -# 0x144: MOV R01, 0x3B -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "144033B1" - -# 0x145: COUT (0x05), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "14526050" - -# 0x146: PUSH R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1463C001" - -# 0x147: RET -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1473E000" - -# 0x148: MOV R00, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "14803010" - -# 0x149: MOV R01, 0x50 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "14903501" - -# 0x14A: COUT (0x05), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "14A26050" - -# 0x14B: PUSH R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "14B3C001" - -# 0x14C: MOV R00, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "14C03000" - -# 0x14D: MOV R01, 0x3B -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "14D033B1" - -# 0x14E: COUT (0x05), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "14E26050" - -# 0x14F: PUSH R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "14F3C001" - -# 0x150: RET -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1503E000" - -# 0x151: CMP R00, R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1510E010" - -# 0x152: JEQ 0x155 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "15239155" - -# 0x153: INC R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "15311010" - -# 0x154: JMP 0x158 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "15430158" - -# 0x155: DEC R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "15515010" - -# 0x156: DEC R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "15615011" - -# 0x157: RET -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1573E000" - -# 0x158: CALL 0x151 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1583B151" - -# 0x159: JMP 0x155 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "15930155" - -# 0x15A: MOV R00, 0xA5 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "15A03A50" - -# 0x15B: MOV R01, 0x5A -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "15B035A1" - -# 0x15C: SWAP R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "15C2A000" - -# 0x15D: CMP R00, 0x5A -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "15D0F5A0" - -# 0x15E: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "15E3A3FF" - -# 0x15F: SWAP R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "15F2A000" - -# 0x160: CMP R00, 0xA5 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1600FA50" - -# 0x161: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1613A3FF" - -# 0x162: MOV R00, 0xD2 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "16203D20" - -# 0x163: SWAP R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1632A000" - -# 0x164: CMP R00, 0x2D -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1640F2D0" - -# 0x165: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1653A3FF" - -# 0x166: SWAP R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1662A001" - -# 0x167: CMP R00, 0x2D -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1670F2D0" - -# 0x168: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1683A3FF" - -# 0x169: CMP R01, 0xA5 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1690FA51" - -# 0x16A: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "16A3A3FF" - -# 0x16B: MOV R00, 0x2D -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "16B032D0" - -# 0x16C: SHL R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "16C1E000" - -# 0x16D: CMP R00, 0x5A -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "16D0F5A0" - -# 0x16E: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "16E3A3FF" - -# 0x16F: SHL R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "16F1E000" - -# 0x170: CMP R00, 0xB4 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1700FB40" - -# 0x171: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1713A3FF" - -# 0x172: SHL R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1721E000" - -# 0x173: CMP R00, 0x68 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1730F680" - -# 0x174: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1743A3FF" - -# 0x175: SHL R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1751E000" - -# 0x176: CMP R00, 0xD0 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1760FD00" - -# 0x177: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1773A3FF" - -# 0x178: SHL R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1781E000" - -# 0x179: CMP R00, 0xA0 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1790FA00" - -# 0x17A: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "17A3A3FF" - -# 0x17B: SHL R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "17B1E000" - -# 0x17C: CMP R00, 0x40 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "17C0F400" - -# 0x17D: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "17D3A3FF" - -# 0x17E: SHL R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "17E1E000" - -# 0x17F: CMP R00, 0x80 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "17F0F800" - -# 0x180: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1803A3FF" - -# 0x181: SHL R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1811E000" - -# 0x182: CMP R00, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1820F000" - -# 0x183: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1833A3FF" - -# 0x184: MOV R01, 0x84 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "18403841" - -# 0x185: SHR R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1851F001" - -# 0x186: CMP R01, 0x42 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1860F421" - -# 0x187: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1873A3FF" - -# 0x188: SHR R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1881F001" - -# 0x189: CMP R01, 0x21 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1890F211" - -# 0x18A: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "18A3A3FF" - -# 0x18B: SHR R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "18B1F001" - -# 0x18C: CMP R01, 0x10 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "18C0F101" - -# 0x18D: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "18D3A3FF" - -# 0x18E: SHR R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "18E1F001" - -# 0x18F: CMP R01, 0x08 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "18F0F081" - -# 0x190: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1903A3FF" - -# 0x191: SHR R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1911F001" - -# 0x192: CMP R01, 0x04 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1920F041" - -# 0x193: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1933A3FF" - -# 0x194: SHR R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1941F001" - -# 0x195: CMP R01, 0x02 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1950F021" - -# 0x196: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1963A3FF" - -# 0x197: SHR R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1971F001" - -# 0x198: CMP R01, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1980F011" - -# 0x199: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1993A3FF" - -# 0x19A: SHR R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "19A1F001" - -# 0x19B: CMP R01, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "19B0F001" - -# 0x19C: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "19C3A3FF" - -# 0x19D: MOV R00, 0xC5 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "19D03C50" - -# 0x19E: ROL R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "19E20000" - -# 0x19F: CMP R00, 0x8B -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "19F0F8B0" - -# 0x1A0: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1A03A3FF" - -# 0x1A1: ROL R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1A120000" - -# 0x1A2: CMP R00, 0x17 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1A20F170" - -# 0x1A3: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1A33A3FF" - -# 0x1A4: ROL R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1A420000" - -# 0x1A5: CMP R00, 0x2E -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1A50F2E0" - -# 0x1A6: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1A63A3FF" - -# 0x1A7: ROL R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1A720000" - -# 0x1A8: CMP R00, 0x5C -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1A80F5C0" - -# 0x1A9: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1A93A3FF" - -# 0x1AA: ROL R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1AA20000" - -# 0x1AB: CMP R00, 0xB8 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1AB0FB80" - -# 0x1AC: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1AC3A3FF" - -# 0x1AD: ROL R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1AD20000" - -# 0x1AE: CMP R00, 0x71 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1AE0F710" - -# 0x1AF: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1AF3A3FF" - -# 0x1B0: ROL R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1B020000" - -# 0x1B1: CMP R00, 0xE2 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1B10FE20" - -# 0x1B2: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1B23A3FF" - -# 0x1B3: ROL R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1B320000" - -# 0x1B4: CMP R00, 0xC5 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1B40FC50" - -# 0x1B5: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1B53A3FF" - -# 0x1B6: MOV R01, 0x63 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1B603631" - -# 0x1B7: ROR R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1B721001" - -# 0x1B8: CMP R01, 0xB1 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1B80FB11" - -# 0x1B9: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1B93A3FF" - -# 0x1BA: ROR R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1BA21001" - -# 0x1BB: CMP R01, 0xD8 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1BB0FD81" - -# 0x1BC: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1BC3A3FF" - -# 0x1BD: ROR R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1BD21001" - -# 0x1BE: CMP R01, 0x6C -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1BE0F6C1" - -# 0x1BF: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1BF3A3FF" - -# 0x1C0: ROR R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1C021001" - -# 0x1C1: CMP R01, 0x36 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1C10F361" - -# 0x1C2: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1C23A3FF" - -# 0x1C3: ROR R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1C321001" - -# 0x1C4: CMP R01, 0x1B -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1C40F1B1" - -# 0x1C5: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1C53A3FF" - -# 0x1C6: ROR R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1C621001" - -# 0x1C7: CMP R01, 0x8D -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1C70F8D1" - -# 0x1C8: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1C83A3FF" - -# 0x1C9: ROR R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1C921001" - -# 0x1CA: CMP R01, 0xC6 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1CA0FC61" - -# 0x1CB: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1CB3A3FF" - -# 0x1CC: ROR R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1CC21001" - -# 0x1CD: CMP R01, 0x63 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1CD0F631" - -# 0x1CE: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1CE3A3FF" - -# 0x1CF: XOR R00, R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1CF1C000" - -# 0x1D0: MOV R00, 0xC5 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1D003C50" - -# 0x1D1: ROLC R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1D122000" - -# 0x1D2: PUSH R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1D23C000" - -# 0x1D3: ROLC R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1D322000" - -# 0x1D4: PUSH R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1D43C000" - -# 0x1D5: ROLC R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1D522000" - -# 0x1D6: PUSH R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1D63C000" - -# 0x1D7: ROLC R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1D722000" - -# 0x1D8: PUSH R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1D83C000" - -# 0x1D9: ROLC R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1D922000" - -# 0x1DA: PUSH R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1DA3C000" - -# 0x1DB: ROLC R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1DB22000" - -# 0x1DC: PUSH R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1DC3C000" - -# 0x1DD: ROLC R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1DD22000" - -# 0x1DE: PUSH R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1DE3C000" - -# 0x1DF: ROLC R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1DF22000" - -# 0x1E0: PUSH R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1E03C000" - -# 0x1E1: ROLC R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1E122000" - -# 0x1E2: CMP R00, 0xC5 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1E20FC50" - -# 0x1E3: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1E33A3FF" - -# 0x1E4: POP R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1E43D000" - -# 0x1E5: CMP R00, 0x62 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1E50F620" - -# 0x1E6: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1E63A3FF" - -# 0x1E7: POP R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1E73D000" - -# 0x1E8: CMP R00, 0xB1 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1E80FB10" - -# 0x1E9: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1E93A3FF" - -# 0x1EA: POP R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1EA3D000" - -# 0x1EB: CMP R00, 0x58 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1EB0F580" - -# 0x1EC: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1EC3A3FF" - -# 0x1ED: POP R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1ED3D000" - -# 0x1EE: CMP R00, 0xAC -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1EE0FAC0" - -# 0x1EF: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1EF3A3FF" - -# 0x1F0: POP R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1F03D000" - -# 0x1F1: CMP R00, 0x56 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1F10F560" - -# 0x1F2: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1F23A3FF" - -# 0x1F3: POP R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1F33D000" - -# 0x1F4: CMP R00, 0x2B -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1F40F2B0" - -# 0x1F5: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1F53A3FF" - -# 0x1F6: POP R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1F63D000" - -# 0x1F7: CMP R00, 0x15 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1F70F150" - -# 0x1F8: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1F83A3FF" - -# 0x1F9: POP R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1F93D000" - -# 0x1FA: CMP R00, 0x8A -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1FA0F8A0" - -# 0x1FB: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1FB3A3FF" - -# 0x1FC: XOR R01, R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1FC1C011" - -# 0x1FD: MOV R01, 0x63 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1FD03631" - -# 0x1FE: RORC R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1FE23001" - -# 0x1FF: PUSH R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1FF3C001" - -# 0x200: RORC R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "20023001" - -# 0x201: PUSH R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2013C001" - -# 0x202: RORC R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "20223001" - -# 0x203: PUSH R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2033C001" - -# 0x204: RORC R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "20423001" - -# 0x205: PUSH R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2053C001" - -# 0x206: RORC R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "20623001" - -# 0x207: PUSH R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2073C001" - -# 0x208: RORC R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "20823001" - -# 0x209: PUSH R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2093C001" - -# 0x20A: RORC R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "20A23001" - -# 0x20B: PUSH R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "20B3C001" - -# 0x20C: RORC R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "20C23001" - -# 0x20D: PUSH R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "20D3C001" - -# 0x20E: RORC R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "20E23001" - -# 0x20F: CMP R01, 0x63 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "20F0F631" - -# 0x210: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2103A3FF" - -# 0x211: POP R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2113D001" - -# 0x212: CMP R01, 0xC6 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2120FC61" - -# 0x213: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2133A3FF" - -# 0x214: POP R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2143D001" - -# 0x215: CMP R01, 0x8C -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2150F8C1" - -# 0x216: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2163A3FF" - -# 0x217: POP R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2173D001" - -# 0x218: CMP R01, 0x19 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2180F191" - -# 0x219: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2193A3FF" - -# 0x21A: POP R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "21A3D001" - -# 0x21B: CMP R01, 0x33 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "21B0F331" - -# 0x21C: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "21C3A3FF" - -# 0x21D: POP R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "21D3D001" - -# 0x21E: CMP R01, 0x66 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "21E0F661" - -# 0x21F: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "21F3A3FF" - -# 0x220: POP R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2203D001" - -# 0x221: CMP R01, 0xCC -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2210FCC1" - -# 0x222: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2223A3FF" - -# 0x223: POP R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2233D001" - -# 0x224: CMP R01, 0x98 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2240F981" - -# 0x225: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2253A3FF" - -# 0x226: POP R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2263D001" - -# 0x227: CMP R01, 0x31 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2270F311" - -# 0x228: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2283A3FF" - -# 0x229: RET -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2293E000" - -# 0x22A: MOV R00, 0xA5 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "22A03A50" - -# 0x22B: SWAP R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "22B2A000" - -# 0x22C: PUSH R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "22C3C000" - -# 0x22D: AND R00, 0x0F -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "22D190F0" - -# 0x22E: CMP R00, 0x0A -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "22E0F0A0" - -# 0x22F: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "22F3A3FF" - -# 0x230: POP R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2303D000" - -# 0x231: PUSH R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2313C000" - -# 0x232: AND R00, 0x0F -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "232190F0" - -# 0x233: CMP R00, 0x0A -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2330F0A0" - -# 0x234: POP R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2343D001" - -# 0x235: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2353A3FF" - -# 0x236: SWAP R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2362A001" - -# 0x237: MOV R02, 0x0F -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "237030F2" - -# 0x238: AND R01, R02 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "23818021" - -# 0x239: CMP R01, 0x05 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2390F051" - -# 0x23A: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "23A3A3FF" - -# 0x23B: MOV R00, 0x05 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "23B03050" - -# 0x23C: MOV R02, 0xA0 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "23C03A02" - -# 0x23D: SWAP R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "23D2A000" - -# 0x23E: OR R02, R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "23E1A002" - -# 0x23F: CMP R02, 0xF0 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "23F0FF02" - -# 0x240: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2403A3FF" - -# 0x241: SWAP R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2412A000" - -# 0x242: OR R00, 0x50 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2421B500" - -# 0x243: CMP R00, 0x55 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2430F550" - -# 0x244: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2443A3FF" - -# 0x245: MOV R01, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "24503011" - -# 0x246: MOV R00, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "24603010" - -# 0x247: XOR R00, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2471D010" - -# 0x248: JNZ 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "248323FF" - -# 0x249: XOR R00, R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2491C010" - -# 0x24A: CMP R00, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "24A0F010" - -# 0x24B: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "24B3A3FF" - -# 0x24C: RET -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "24C3E000" - -# 0x24D: MOV R00, 0x03 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "24D03030" - -# 0x24E: COUT (0x03), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "24E26030" - -# 0x24F: XIN R00, (0x02) -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "24F28020" - -# 0x250: OR R00, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2501B010" - -# 0x251: XOUT (0x02), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "25124020" - -# 0x252: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "25200000" - -# 0x253: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "25300000" - -# 0x254: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "25400000" - -# 0x255: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "25500000" - -# 0x256: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "25600000" - -# 0x257: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "25700000" - -# 0x258: XIN R00, (0x02) -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "25828020" - -# 0x259: AND R00, 0xFE -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "25919FE0" - -# 0x25A: XOUT (0x02), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "25A24020" - -# 0x25B: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "25B00000" - -# 0x25C: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "25C00000" - -# 0x25D: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "25D00000" - -# 0x25E: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "25E00000" - -# 0x25F: CIN R00, (0x03) -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "25F29030" - -# 0x260: OR R00, 0x80 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2601B800" - -# 0x261: COUT (0x03), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "26126030" - -# 0x262: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "26200000" - -# 0x263: CIN R00, (0x03) -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "26329030" - -# 0x264: OR R00, 0x80 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2641B800" - -# 0x265: COUT (0x03), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "26526030" - -# 0x266: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "26600000" - -# 0x267: CIN R00, (0x03) -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "26729030" - -# 0x268: OR R00, 0x80 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2681B800" - -# 0x269: COUT (0x03), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "26926030" - -# 0x26A: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "26A00000" - -# 0x26B: CIN R00, (0x03) -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "26B29030" - -# 0x26C: OR R00, 0x80 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "26C1B800" - -# 0x26D: COUT (0x03), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "26D26030" - -# 0x26E: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "26E00000" - -# 0x26F: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "26F00000" - -# 0x270: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "27000000" - -# 0x271: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "27100000" - -# 0x272: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "27200000" - -# 0x273: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "27300000" - -# 0x274: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "27400000" - -# 0x275: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "27500000" - -# 0x276: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "27600000" - -# 0x277: RET -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2773E000" - -# 0x278: SUB R00, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "27815000" - -# 0x279: JC 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "279333FF" - -# 0x27A: SETC -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "27A2B000" - -# 0x27B: JNC 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "27B343FF" - -# 0x27C: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "27C00000" - -# 0x27D: SUB R00, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "27D15000" - -# 0x27E: JC 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "27E333FF" - -# 0x27F: MOV R00, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "27F03000" - -# 0x280: CLRC -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "28015000" - -# 0x281: JC 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "281333FF" - -# 0x282: SETC -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2822B000" - -# 0x283: JNC 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "283343FF" - -# 0x284: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "28400000" - -# 0x285: CLRC -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "28515000" - -# 0x286: JC 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "286333FF" - -# 0x287: RET -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2873E000" - -# 0x288: INC R14 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2881101E" - -# 0x289: RETI -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2893F000" - -# 0x28A: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "28A00000" - -# 0x28B: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "28B00000" - -# 0x28C: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "28C00000" - -# 0x28D: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "28D00000" - -# 0x28E: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "28E00000" - -# 0x28F: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "28F00000" - -# 0x290: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "29000000" - -# 0x291: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "29100000" - -# 0x292: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "29200000" - -# 0x293: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "29300000" - -# 0x294: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "29400000" - -# 0x295: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "29500000" - -# 0x296: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "29600000" - -# 0x297: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "29700000" - -# 0x298: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "29800000" - -# 0x299: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "29900000" - -# 0x29A: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "29A00000" - -# 0x29B: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "29B00000" - -# 0x29C: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "29C00000" - -# 0x29D: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "29D00000" - -# 0x29E: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "29E00000" - -# 0x29F: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "29F00000" - -# 0x2A0: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2A000000" - -# 0x2A1: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2A100000" - -# 0x2A2: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2A200000" - -# 0x2A3: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2A300000" - -# 0x2A4: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2A400000" - -# 0x2A5: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2A500000" - -# 0x2A6: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2A600000" - -# 0x2A7: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2A700000" - -# 0x2A8: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2A800000" - -# 0x2A9: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2A900000" - -# 0x2AA: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2AA00000" - -# 0x2AB: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2AB00000" - -# 0x2AC: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2AC00000" - -# 0x2AD: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2AD00000" - -# 0x2AE: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2AE00000" - -# 0x2AF: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2AF00000" - -# 0x2B0: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2B000000" - -# 0x2B1: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2B100000" - -# 0x2B2: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2B200000" - -# 0x2B3: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2B300000" - -# 0x2B4: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2B400000" - -# 0x2B5: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2B500000" - -# 0x2B6: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2B600000" - -# 0x2B7: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2B700000" - -# 0x2B8: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2B800000" - -# 0x2B9: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2B900000" - -# 0x2BA: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2BA00000" - -# 0x2BB: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2BB00000" - -# 0x2BC: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2BC00000" - -# 0x2BD: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2BD00000" - -# 0x2BE: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2BE00000" - -# 0x2BF: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2BF00000" - -# 0x2C0: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2C000000" - -# 0x2C1: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2C100000" - -# 0x2C2: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2C200000" - -# 0x2C3: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2C300000" - -# 0x2C4: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2C400000" - -# 0x2C5: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2C500000" - -# 0x2C6: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2C600000" - -# 0x2C7: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2C700000" - -# 0x2C8: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2C800000" - -# 0x2C9: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2C900000" - -# 0x2CA: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2CA00000" - -# 0x2CB: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2CB00000" - -# 0x2CC: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2CC00000" - -# 0x2CD: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2CD00000" - -# 0x2CE: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2CE00000" - -# 0x2CF: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2CF00000" - -# 0x2D0: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2D000000" - -# 0x2D1: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2D100000" - -# 0x2D2: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2D200000" - -# 0x2D3: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2D300000" - -# 0x2D4: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2D400000" - -# 0x2D5: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2D500000" - -# 0x2D6: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2D600000" - -# 0x2D7: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2D700000" - -# 0x2D8: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2D800000" - -# 0x2D9: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2D900000" - -# 0x2DA: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2DA00000" - -# 0x2DB: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2DB00000" - -# 0x2DC: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2DC00000" - -# 0x2DD: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2DD00000" - -# 0x2DE: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2DE00000" - -# 0x2DF: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2DF00000" - -# 0x2E0: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2E000000" - -# 0x2E1: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2E100000" - -# 0x2E2: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2E200000" - -# 0x2E3: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2E300000" - -# 0x2E4: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2E400000" - -# 0x2E5: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2E500000" - -# 0x2E6: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2E600000" - -# 0x2E7: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2E700000" - -# 0x2E8: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2E800000" - -# 0x2E9: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2E900000" - -# 0x2EA: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2EA00000" - -# 0x2EB: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2EB00000" - -# 0x2EC: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2EC00000" - -# 0x2ED: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2ED00000" - -# 0x2EE: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2EE00000" - -# 0x2EF: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2EF00000" - -# 0x2F0: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2F000000" - -# 0x2F1: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2F100000" - -# 0x2F2: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2F200000" - -# 0x2F3: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2F300000" - -# 0x2F4: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2F400000" - -# 0x2F5: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2F500000" - -# 0x2F6: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2F600000" - -# 0x2F7: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2F700000" - -# 0x2F8: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2F800000" - -# 0x2F9: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2F900000" - -# 0x2FA: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2FA00000" - -# 0x2FB: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2FB00000" - -# 0x2FC: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2FC00000" - -# 0x2FD: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2FD00000" - -# 0x2FE: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2FE00000" - -# 0x2FF: JMP 0x2FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2FF302FF" - -# 0x300: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "30000000" - -# 0x301: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "30100000" - -# 0x302: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "30200000" - -# 0x303: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "30300000" - -# 0x304: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "30400000" - -# 0x305: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "30500000" - -# 0x306: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "30600000" - -# 0x307: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "30700000" - -# 0x308: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "30800000" - -# 0x309: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "30900000" - -# 0x30A: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "30A00000" - -# 0x30B: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "30B00000" - -# 0x30C: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "30C00000" - -# 0x30D: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "30D00000" - -# 0x30E: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "30E00000" - -# 0x30F: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "30F00000" - -# 0x310: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "31000000" - -# 0x311: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "31100000" - -# 0x312: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "31200000" - -# 0x313: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "31300000" - -# 0x314: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "31400000" - -# 0x315: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "31500000" - -# 0x316: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "31600000" - -# 0x317: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "31700000" - -# 0x318: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "31800000" - -# 0x319: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "31900000" - -# 0x31A: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "31A00000" - -# 0x31B: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "31B00000" - -# 0x31C: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "31C00000" - -# 0x31D: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "31D00000" - -# 0x31E: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "31E00000" - -# 0x31F: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "31F00000" - -# 0x320: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "32000000" - -# 0x321: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "32100000" - -# 0x322: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "32200000" - -# 0x323: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "32300000" - -# 0x324: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "32400000" - -# 0x325: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "32500000" - -# 0x326: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "32600000" - -# 0x327: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "32700000" - -# 0x328: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "32800000" - -# 0x329: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "32900000" - -# 0x32A: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "32A00000" - -# 0x32B: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "32B00000" - -# 0x32C: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "32C00000" - -# 0x32D: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "32D00000" - -# 0x32E: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "32E00000" - -# 0x32F: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "32F00000" - -# 0x330: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "33000000" - -# 0x331: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "33100000" - -# 0x332: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "33200000" - -# 0x333: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "33300000" - -# 0x334: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "33400000" - -# 0x335: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "33500000" - -# 0x336: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "33600000" - -# 0x337: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "33700000" - -# 0x338: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "33800000" - -# 0x339: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "33900000" - -# 0x33A: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "33A00000" - -# 0x33B: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "33B00000" - -# 0x33C: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "33C00000" - -# 0x33D: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "33D00000" - -# 0x33E: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "33E00000" - -# 0x33F: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "33F00000" - -# 0x340: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "34000000" - -# 0x341: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "34100000" - -# 0x342: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "34200000" - -# 0x343: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "34300000" - -# 0x344: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "34400000" - -# 0x345: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "34500000" - -# 0x346: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "34600000" - -# 0x347: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "34700000" - -# 0x348: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "34800000" - -# 0x349: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "34900000" - -# 0x34A: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "34A00000" - -# 0x34B: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "34B00000" - -# 0x34C: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "34C00000" - -# 0x34D: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "34D00000" - -# 0x34E: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "34E00000" - -# 0x34F: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "34F00000" - -# 0x350: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "35000000" - -# 0x351: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "35100000" - -# 0x352: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "35200000" - -# 0x353: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "35300000" - -# 0x354: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "35400000" - -# 0x355: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "35500000" - -# 0x356: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "35600000" - -# 0x357: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "35700000" - -# 0x358: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "35800000" - -# 0x359: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "35900000" - -# 0x35A: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "35A00000" - -# 0x35B: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "35B00000" - -# 0x35C: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "35C00000" - -# 0x35D: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "35D00000" - -# 0x35E: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "35E00000" - -# 0x35F: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "35F00000" - -# 0x360: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "36000000" - -# 0x361: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "36100000" - -# 0x362: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "36200000" - -# 0x363: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "36300000" - -# 0x364: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "36400000" - -# 0x365: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "36500000" - -# 0x366: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "36600000" - -# 0x367: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "36700000" - -# 0x368: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "36800000" - -# 0x369: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "36900000" - -# 0x36A: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "36A00000" - -# 0x36B: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "36B00000" - -# 0x36C: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "36C00000" - -# 0x36D: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "36D00000" - -# 0x36E: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "36E00000" - -# 0x36F: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "36F00000" - -# 0x370: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "37000000" - -# 0x371: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "37100000" - -# 0x372: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "37200000" - -# 0x373: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "37300000" - -# 0x374: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "37400000" - -# 0x375: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "37500000" - -# 0x376: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "37600000" - -# 0x377: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "37700000" - -# 0x378: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "37800000" - -# 0x379: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "37900000" - -# 0x37A: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "37A00000" - -# 0x37B: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "37B00000" - -# 0x37C: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "37C00000" - -# 0x37D: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "37D00000" - -# 0x37E: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "37E00000" - -# 0x37F: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "37F00000" - -# 0x380: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "38000000" - -# 0x381: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "38100000" - -# 0x382: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "38200000" - -# 0x383: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "38300000" - -# 0x384: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "38400000" - -# 0x385: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "38500000" - -# 0x386: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "38600000" - -# 0x387: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "38700000" - -# 0x388: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "38800000" - -# 0x389: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "38900000" - -# 0x38A: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "38A00000" - -# 0x38B: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "38B00000" - -# 0x38C: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "38C00000" - -# 0x38D: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "38D00000" - -# 0x38E: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "38E00000" - -# 0x38F: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "38F00000" - -# 0x390: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "39000000" - -# 0x391: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "39100000" - -# 0x392: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "39200000" - -# 0x393: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "39300000" - -# 0x394: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "39400000" - -# 0x395: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "39500000" - -# 0x396: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "39600000" - -# 0x397: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "39700000" - -# 0x398: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "39800000" - -# 0x399: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "39900000" - -# 0x39A: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "39A00000" - -# 0x39B: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "39B00000" - -# 0x39C: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "39C00000" - -# 0x39D: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "39D00000" - -# 0x39E: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "39E00000" - -# 0x39F: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "39F00000" - -# 0x3A0: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3A000000" - -# 0x3A1: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3A100000" - -# 0x3A2: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3A200000" - -# 0x3A3: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3A300000" - -# 0x3A4: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3A400000" - -# 0x3A5: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3A500000" - -# 0x3A6: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3A600000" - -# 0x3A7: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3A700000" - -# 0x3A8: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3A800000" - -# 0x3A9: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3A900000" - -# 0x3AA: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3AA00000" - -# 0x3AB: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3AB00000" - -# 0x3AC: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3AC00000" - -# 0x3AD: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3AD00000" - -# 0x3AE: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3AE00000" - -# 0x3AF: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3AF00000" - -# 0x3B0: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3B000000" - -# 0x3B1: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3B100000" - -# 0x3B2: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3B200000" - -# 0x3B3: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3B300000" - -# 0x3B4: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3B400000" - -# 0x3B5: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3B500000" - -# 0x3B6: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3B600000" - -# 0x3B7: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3B700000" - -# 0x3B8: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3B800000" - -# 0x3B9: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3B900000" - -# 0x3BA: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3BA00000" - -# 0x3BB: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3BB00000" - -# 0x3BC: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3BC00000" - -# 0x3BD: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3BD00000" - -# 0x3BE: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3BE00000" - -# 0x3BF: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3BF00000" - -# 0x3C0: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3C000000" - -# 0x3C1: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3C100000" - -# 0x3C2: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3C200000" - -# 0x3C3: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3C300000" - -# 0x3C4: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3C400000" - -# 0x3C5: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3C500000" - -# 0x3C6: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3C600000" - -# 0x3C7: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3C700000" - -# 0x3C8: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3C800000" - -# 0x3C9: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3C900000" - -# 0x3CA: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3CA00000" - -# 0x3CB: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3CB00000" - -# 0x3CC: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3CC00000" - -# 0x3CD: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3CD00000" - -# 0x3CE: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3CE00000" - -# 0x3CF: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3CF00000" - -# 0x3D0: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3D000000" - -# 0x3D1: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3D100000" - -# 0x3D2: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3D200000" - -# 0x3D3: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3D300000" - -# 0x3D4: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3D400000" - -# 0x3D5: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3D500000" - -# 0x3D6: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3D600000" - -# 0x3D7: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3D700000" - -# 0x3D8: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3D800000" - -# 0x3D9: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3D900000" - -# 0x3DA: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3DA00000" - -# 0x3DB: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3DB00000" - -# 0x3DC: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3DC00000" - -# 0x3DD: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3DD00000" - -# 0x3DE: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3DE00000" - -# 0x3DF: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3DF00000" - -# 0x3E0: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3E000000" - -# 0x3E1: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3E100000" - -# 0x3E2: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3E200000" - -# 0x3E3: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3E300000" - -# 0x3E4: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3E400000" - -# 0x3E5: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3E500000" - -# 0x3E6: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3E600000" - -# 0x3E7: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3E700000" - -# 0x3E8: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3E800000" - -# 0x3E9: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3E900000" - -# 0x3EA: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3EA00000" - -# 0x3EB: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3EB00000" - -# 0x3EC: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3EC00000" - -# 0x3ED: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3ED00000" - -# 0x3EE: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3EE00000" - -# 0x3EF: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3EF00000" - -# 0x3F0: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3F000000" - -# 0x3F1: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3F100000" - -# 0x3F2: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3F200000" - -# 0x3F3: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3F300000" - -# 0x3F4: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3F400000" - -# 0x3F5: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3F500000" - -# 0x3F6: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3F600000" - -# 0x3F7: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3F700000" - -# 0x3F8: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3F800000" - -# 0x3F9: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3F900000" - -# 0x3FA: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3FA00000" - -# 0x3FB: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3FB00000" - -# 0x3FC: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3FC00000" - -# 0x3FD: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3FD00000" - -# 0x3FE: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3FE00000" - -# 0x3FF: JMP 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3FF303FF" - -# Assembled from itest.jsm -# --------------------------------------------------------------- -# Shift the USER2 Instruction (b1111000011) into the Instruction Register of FPGA -# User 2 -set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength "3C3"] - -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0048" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0161" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "026C" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "036C" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "046F" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0500" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0600" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0700" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0800" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0900" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0A00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0B00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0C00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0D00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0E00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0F00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1000" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1100" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1200" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1300" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1400" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1500" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1600" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1700" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1800" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1900" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1A00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1B00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1C00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1D00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1E00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1F00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2000" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2100" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2200" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2300" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2400" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2500" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2600" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2700" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2800" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2900" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2A00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2B00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2C00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2D00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2E00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2F00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3000" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3100" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3200" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3300" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3400" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3500" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3600" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3700" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3800" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3900" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3A00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3B00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3C00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3D00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3E00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3F00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4000" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4100" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4200" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4300" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4400" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4500" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4600" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4700" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4800" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4900" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4A00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4B00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4C00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4D00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4E00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4F00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5000" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5100" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5200" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5300" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5400" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5500" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5600" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5700" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5800" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5900" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5A00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5B00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5C00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5D00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5E00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5F00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "6000" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "6100" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "6200" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "6300" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "6400" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "6500" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "6600" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "6700" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "6800" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "6900" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "6A00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "6B00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "6C00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "6D00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "6E00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "6F00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "7000" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "7100" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "7200" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "7300" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "7400" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "7500" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "7600" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "7700" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "7800" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "7900" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "7A00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "7B00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "7C00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "7D00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "7E00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "7F00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "8000" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "8100" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "8200" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "8300" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "8400" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "8500" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "8600" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "8700" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "8800" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "8900" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "8A00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "8B00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "8C00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "8D00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "8E00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "8F00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "9000" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "9100" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "9200" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "9300" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "9400" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "9500" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "9600" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "9700" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "9800" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "9900" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "9A00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "9B00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "9C00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "9D00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "9E00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "9F00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "A000" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "A100" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "A200" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "A300" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "A400" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "A500" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "A600" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "A700" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "A800" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "A900" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "AA00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "AB00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "AC00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "AD00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "AE00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "AF00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "B000" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "B100" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "B200" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "B300" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "B400" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "B500" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "B600" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "B700" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "B800" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "B900" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "BA00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "BB00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "BC00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "BD00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "BE00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "BF00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "C000" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "C100" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "C200" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "C300" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "C400" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "C500" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "C600" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "C700" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "C800" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "C900" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "CA00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "CB00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "CC00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "CD00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "CE00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "CF00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "D000" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "D100" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "D200" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "D300" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "D400" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "D500" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "D600" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "D700" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "D800" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "D900" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "DA00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "DB00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "DC00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "DD00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "DE00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "DF00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "E000" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "E100" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "E200" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "E300" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "E400" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "E500" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "E600" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "E700" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "E800" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "E900" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "EA00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "EB00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "EC00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "ED00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "EE00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "EF00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "F000" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "F100" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "F200" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "F300" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "F400" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "F500" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "F600" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "F700" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "F800" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "F900" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "FA00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "FB00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "FC00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "FD00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "FE00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "FF00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "10000" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "10100" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "10200" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "10300" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "10400" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "10500" - -::chipscope::csejtag_target unlock $handle -::chipscope::csejtag_target close $handle -::chipscope::csejtag_session destroy $handle -exit diff --git a/lib/CPUs/JCpu/asm/make b/lib/CPUs/JCpu/asm/make deleted file mode 100644 index e7f598f..0000000 --- a/lib/CPUs/JCpu/asm/make +++ /dev/null @@ -1,50 +0,0 @@ -#!/bin/sh - -# ---------------------------------------------------------------------- -# Project: JCPU, a portable 8-bit RISC CPU written in VHDL -# This file: rom-file generation for cpu_core -# -# Copyright (C) 2007 J. Ahrensfeld -# -# This program is free software: you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation, either version 3 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see . -# -# For questions and ideas, please contact the author at jens@jayfield.org -# -# --------------------------------------------------------------------- - -TARGET=$2 -DSTDIR=$1 - -JASM_HOME=/cygdrive/w/vhdl/lib/CPUs/JCpu/tools - -$JASM_HOME/jasm.rb $TARGET.jsm - -irom_tcl_snippet="$TARGET.irom.tcl.snip" -irom_vhdl_snippet="$TARGET.irom.vhdl.snip" -irom_ld_vhdl_snippet="$TARGET.irom_ld.vhdl.snip" -xrom_tcl_snippet="$TARGET.xrom.tcl.snip" -xrom_vhdl_snippet="$TARGET.xrom.vhdl.snip" -xrom_ld_vhdl_snippet="$TARGET.xrom_ld.vhdl.snip" - -$JASM_HOME/insrom.rb $irom_vhdl_snippet $JASM_HOME/irom.vhd.tpl >$DSTDIR/$TARGET\_irom.vhdl -$JASM_HOME/insrom.rb $irom_ld_vhdl_snippet $JASM_HOME/irom_ld.vhd.tpl >$DSTDIR/$TARGET\_irom_ld.vhdl - -$JASM_HOME/insrom.rb $xrom_vhdl_snippet $JASM_HOME/xrom.vhd.tpl >$DSTDIR/$TARGET\_xrom.vhdl -$JASM_HOME/insrom.rb $xrom_ld_vhdl_snippet $JASM_HOME/xrom_ld.vhd.tpl >$DSTDIR/$TARGET\_xrom_ld.vhdl - -cat $irom_tcl_snippet > $TARGET.tcl.snip.snip -cat $xrom_tcl_snippet >> $TARGET.tcl.snip.snip -$JASM_HOME/insrom.rb $TARGET.tcl.snip.snip $JASM_HOME/rom.tcl.tpl >$TARGET.tcl - -rm -f *.snip diff --git a/lib/CPUs/JCpu/asm/mul8x8.jsm b/lib/CPUs/JCpu/asm/mul8x8.jsm deleted file mode 100644 index c9b6c3b..0000000 --- a/lib/CPUs/JCpu/asm/mul8x8.jsm +++ /dev/null @@ -1,29 +0,0 @@ -; ------------------------------------------------- -; Constants -; ------------------------------------------------- - -; Chip register -include "../../../jasm/cregs.inc.jsm" - -; ------------------------------------------------- -; Program -; ------------------------------------------------- - code - org 0x000 -reset: jmp init - -; ------------------------------------------------- -; Main -; ------------------------------------------------- -init: mov R0, 0x45 - mov R1, 0xF5 - - call mul8x8 -stop: jmp stop - - -; ------------------------------------------------- -include "../../../jasm/mul8x8.inc.jsm" - - - \ No newline at end of file diff --git a/lib/CPUs/JCpu/asm/mul8x8.tcl b/lib/CPUs/JCpu/asm/mul8x8.tcl deleted file mode 100644 index 6bec87e..0000000 --- a/lib/CPUs/JCpu/asm/mul8x8.tcl +++ /dev/null @@ -1,154 +0,0 @@ -# ---------------------------------------------------------------------- -# Project: JCPU, a portable 8-bit RISC CPU written in VHDL -# This file: The ROM file for upload to target over JTAG -# -# Copyright (C) 2007 J. Ahrensfeld -# -# This program is free software: you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation, either version 3 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see . -# -# For questions and ideas, please contact the author at jens@jayfield.org -# -# --------------------------------------------------------------------- - -# --------------------------------------------------------------------- -# For Chipscope 9.1 -# --------------------------------------------------------------------- -# Source JTAG/TCL frame work -cd $env(CHIPSCOPE)\\bin\\nt -source csejtag.tcl - -namespace import ::chipscope::* - -# Platform USB Cable -set PLATFORM_USB_CABLE_ARGS [list "port=USB2" "frequency=6000000"] -# frequency="24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000" - -# Create session -set handle [::chipscope::csejtag_session create 0] - -# Open JTAG and lock -set open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS] -set lock_result [::chipscope::csejtag_target lock $handle 1000] - -set devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT] - -# Get Device ID -set devtype "Virtex-4SX" -set devid 2 -set irlength [::chipscope::csejtag_tap get_irlength $handle $devid] -set idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid] - -set CSE_OP $CSEJTAG_SHIFT_READWRITE -set CSE_ES $CSEJTAG_RUN_TEST_IDLE - -# Write Program -# JASM_ROM_INSERT_HERE -# Assembled from mul8x8.jsm -# --------------------------------------------------------------- -# Shift the USER2 Instruction (b1111000010) into the Instruction Register of FPGA -# User 1 -set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength "3C2"] - -# 0x000: JMP 0x001 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00030001" - -# 0x001: MOV R00, 0x45 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00103450" - -# 0x002: MOV R01, 0xF5 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00203F51" - -# 0x003: CALL 0x005 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0033B005" - -# 0x004: JMP 0x004 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00430004" - -# 0x005: PUSH R02 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0053C002" - -# 0x006: PUSH R03 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0063C003" - -# 0x007: PUSH R04 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0073C004" - -# 0x008: MOV R04, R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00802014" - -# 0x009: MOV R01, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00903001" - -# 0x00A: MOV R02, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00A03002" - -# 0x00B: MOV R03, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00B03003" - -# 0x00C: CMP R04, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00C0F014" - -# 0x00D: JEQ 0x015 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00D39015" - -# 0x00E: SHR R04 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00E1F004" - -# 0x00F: JNC 0x012 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00F34012" - -# 0x010: ADD R02, R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01010002" - -# 0x011: ADDC R03, R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01112013" - -# 0x012: SHL R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0121E000" - -# 0x013: ROLC R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01322001" - -# 0x014: JMP 0x00C -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0143000C" - -# 0x015: ADD R00, R02 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01510020" - -# 0x016: ADDC R01, R03 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01612031" - -# 0x017: POP R04 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0173D004" - -# 0x018: POP R03 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0183D003" - -# 0x019: POP R02 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0193D002" - -# 0x01A: RET -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01A3E000" - -# Assembled from mul8x8.jsm -# --------------------------------------------------------------- -# Shift the USER2 Instruction (b1111000011) into the Instruction Register of FPGA -# User 2 -set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength "3C3"] - - -::chipscope::csejtag_target unlock $handle -::chipscope::csejtag_target close $handle -::chipscope::csejtag_session destroy $handle -exit diff --git a/lib/CPUs/JCpu/asm/reti_issue.jsm b/lib/CPUs/JCpu/asm/reti_issue.jsm deleted file mode 100644 index 78edc49..0000000 --- a/lib/CPUs/JCpu/asm/reti_issue.jsm +++ /dev/null @@ -1,50 +0,0 @@ -; ------------------------------------------------- -; Constants -; ------------------------------------------------- - -; Chip register -cpu_revision: equ 0x00 ; RO -cpu_control: equ 0x01 ; R/W -cpu_status: equ 0x02 ; RO -cpu_int_ctrl: equ 0x03 ; R/W - -; ------------------------------------------------- -; Program -; ------------------------------------------------- - code -reset: jmp init - - org 0x001 -; nop - reti - -; ------------------------------------------------- -; Main -; ------------------------------------------------- -init: mov R0, 0x05 - cout (cpu_int_ctrl), R0 - mov R0, 0x00 -loop: nop - inc R0 - nop - call subr - nop - push R3 - nop - push R2 - nop - push R1 - nop - push R0 - nop - pop R0 - nop - pop R1 - nop - pop R2 - nop - pop R3 - nop - jmp loop - -subr: ret diff --git a/lib/CPUs/JCpu/asm/reti_issue.tcl b/lib/CPUs/JCpu/asm/reti_issue.tcl deleted file mode 100644 index 5da9c56..0000000 --- a/lib/CPUs/JCpu/asm/reti_issue.tcl +++ /dev/null @@ -1,157 +0,0 @@ -# ---------------------------------------------------------------------- -# Project: JCPU, a portable 8-bit RISC CPU written in VHDL -# This file: The ROM file for upload to target over JTAG -# -# Copyright (C) 2007 J. Ahrensfeld -# -# This program is free software: you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation, either version 3 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see . -# -# For questions and ideas, please contact the author at jens@jayfield.org -# -# --------------------------------------------------------------------- - -# --------------------------------------------------------------------- -# For Chipscope 9.1 -# --------------------------------------------------------------------- -# Source JTAG/TCL frame work -cd $env(CHIPSCOPE)\\bin\\nt -source csejtag.tcl - -namespace import ::chipscope::* - -# Platform USB Cable -set PLATFORM_USB_CABLE_ARGS [list "port=USB2" "frequency=6000000"] -# frequency="24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000" - -# Create session -set handle [::chipscope::csejtag_session create 0] - -# Open JTAG and lock -set open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS] -set lock_result [::chipscope::csejtag_target lock $handle 1000] - -set devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT] - -# Get Device ID -set devtype "Virtex-4SX" -set devid 2 -set irlength [::chipscope::csejtag_tap get_irlength $handle $devid] -set idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid] - -set CSE_OP $CSEJTAG_SHIFT_READWRITE -set CSE_ES $CSEJTAG_RUN_TEST_IDLE - -# Write Program -# JASM_ROM_INSERT_HERE -# Assembled from reti_issue.jsm -# --------------------------------------------------------------- -# Shift the USER2 Instruction (b1111000010) into the Instruction Register of FPGA -# User 1 -set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength "3C2"] - -# 0x000: JMP 0x002 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00030002" - -# 0x001: RETI -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0013F000" - -# 0x002: MOV R00, 0x05 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00203050" - -# 0x003: COUT (0x03), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00326030" - -# 0x004: MOV R00, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00403000" - -# 0x005: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00500000" - -# 0x006: INC R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00611010" - -# 0x007: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00700000" - -# 0x008: CALL 0x01B -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0083B01B" - -# 0x009: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00900000" - -# 0x00A: PUSH R03 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00A3C003" - -# 0x00B: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00B00000" - -# 0x00C: PUSH R02 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00C3C002" - -# 0x00D: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00D00000" - -# 0x00E: PUSH R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00E3C001" - -# 0x00F: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00F00000" - -# 0x010: PUSH R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0103C000" - -# 0x011: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01100000" - -# 0x012: POP R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0123D000" - -# 0x013: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01300000" - -# 0x014: POP R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0143D001" - -# 0x015: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01500000" - -# 0x016: POP R02 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0163D002" - -# 0x017: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01700000" - -# 0x018: POP R03 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0183D003" - -# 0x019: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01900000" - -# 0x01A: JMP 0x005 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01A30005" - -# 0x01B: RET -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01B3E000" - -# Assembled from reti_issue.jsm -# --------------------------------------------------------------- -# Shift the USER2 Instruction (b1111000011) into the Instruction Register of FPGA -# User 2 -set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength "3C3"] - - -::chipscope::csejtag_target unlock $handle -::chipscope::csejtag_target close $handle -::chipscope::csejtag_session destroy $handle -exit diff --git a/lib/CPUs/JCpu/doc/block_diagram.png b/lib/CPUs/JCpu/doc/block_diagram.png deleted file mode 100644 index 14bbb546864ab27695f53a12755b96921ad898a9..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 8026 zcmZ8m2UJtf(g*)4N>ve2M3LST1qCBj2t~S7fk+gjOMpa$NQnwk1%Z%61VKb8(xeH2 z0Mb(^g3_BxE)i*RQ7{nT!}s3z&Ue0ZX7A4K&g{;5yuXkGqgG`+< zTwH=}e+ze4VBsw;uG0%w;Fs+~#}+300#6RV;0jW@)4sPjl>fWChlo0ae{LYka*y+g zyJ~{AH~jTaBJb0R99vyTr>l$G>f`2fOFqzZ<7^LK3q8~_(R`!92dcAI*7MlixFZ>D zr}yMJTm3thfAaFme&{A_%I6mOFBE5MFT(Z4BN4fH}k3+M4*JN4WIaUIvT zUEP5mxuX7ok|VCO``iKXB5?V*?M&8MuDumtuPcDP`HW&%LP@I1lD3}`hXj6Ap632} z9+vn<{A>)ulba_*%wYYi>SF)vlt8gkhW@NOa!1QZm2{$!qGdLv$Z~+6UdBD-{Sw2; zHAqX$N2CoqeH~a(o~&f*u@6x+L&^>ok3rS{0rjr$W07Zk03&Htb?GaK%0cJs-ZQjU z`AgC<`PxGgCkfMAdv3qm?5CGLNt0{-nu0?N0~c0(Dv{f_PL))tr_vkd+68=9j)fjf zMM8?b>Eu^o=!(ir?vp=0AHl?*@hoE=bNbMH5s1B)QH4U^^COdq%@@6&8yDA6ns_z5 zkTtFyvBf|7Cn)`vEf2ZJBIkJP7=w9)#Qce3c{MkwrAV82$1=6SGRktfL@j`V{qoK4 z-J;#JUUHo6eE2R5mxIm?dMo}-G1d?W$O6PG(45(SZD2AO#OSGs>*-+=cX%q$=sZBn zeHRVitWUb>e=*4;i2g_5UqYmR1j{F~kgx}5;+;^C2iiB8vmX%4Evj6DGPlXB+0VE5 z_^>>WPDpF=4BZz3mF)M81oib48F*Z?6U*0LQ`XVsQFGN{%S*f^+?mkPEO4B%Jnb+t zV+uG{vhMyJ47bk4<`XgIOJvw@XkzQv9!}(I^k{l>32Rmyd^%tMFD2r$wj3F6DMI2o zEs6UK$!5e5uq$6f37!A*C=8X%NA5q@YERE^=6w|E zCTuY~(@u2YNp;syaEdiVQ#7B#ds#aOWo31ra*vAkLX*j7fqe%?XuxbM!CI|NBtJ{q zQFj!p@Ye%kRrKT>w@(p1`Q-K+0OxysCCmVOt2l~&Nmd^C4&buIUIgJhbl(yCsQjo` zqymvb=1n^po5-c2O2+xbvp0@ix{rO!3G)moJt1wK9a;05*1QOLD^=7TID4K#qx9)$SbCPVyagXoP2e*GUsxcBFXO> z?J^hkpW4Hs>)#mubu`HePb=ULy+hNKfDg@&qf4hvt0SMwS~sCM3i34k^chFpiWl%} z?hK0l?JUt(zOHgX%J9$G|MhQ^Go*44ner3f00NM5dhEK97~*}{!Ba?@eYopBO;$q) zTevo>=kVqco)fkDv&X?M@}qq7rLGmBK#WvAxIWE{d^b=n)up)em8FtH|FGLP=()tB zsY1rMs9YaaXRfKp#gjN*37haja;YvJvRaSmaCQrZV(gOrGlqXWt!u3J&q|yZx#u57 zRQ@)q^h&4y;bx25xD?X+U7Bd)=0~yE>^`aTb$KVNu7tmFVE1hq+@Ay$M1xYxuW$qW z5KxPBuYKU-VUk^>&`EY5#{bCjCHh@b`HbD{>i9tZe0S^h$Tol0=0_l7A}zgKVCP8i zJaKr3mFk;lBF*Z8t{z}|LvNeQ;({Uk@vBiE0bMW5+Ty%qfVm8surivhcXA-x#C5h{ zGFxcQaE0guTMp)%1@}~dN)@1-Dn^V2jT{FBp4hsb4kc=I+iuZz5;DX$h`3WP5Q|hG ze5b1H!y*hP4UsfpyUJ_wbbd)hC<))t5KZM=m@`M&M6Ovp$S@i~*EFazNf6I%W_I%^ zBA7}{v4gID?Qc!i#pm455-QET5LX^f8AU{cAIPw7Amx9f=zqiM|7F7C5KKgEd8=F5 zJ(;23%E3QL&9c{v^sb~S;I6wMzQ(Jpk~+qhQE9Tvv$Ix1?Hnp-iotjonLF%Ah&l*t zmAKLI3OQ33cAgL%bBb{7_g|%Gix+xm;#Y zvgQ}2?o7Y=8Jkn(soTLGdlTe`)@mat3Q}9bX%XI3<*<5AwyO856jvcic-rCpOh44L z(&}rw$PDkQWHk~?3g5hRO!e(4)rkk;*7)^rh)Yl2#Y{O*3Qu3I%~x3cLUAyhk0||i z|MBEF?!m$(?fU2=SlRw_U%;kbc4 z73dgywvIb6-%ek=&U@k!vopHgL)1Kto+U%ZcvB1Z(q8OtqfE#W|CO`}vbxL_G;1jU zPUCB*7q`~K2tECe=xwHW5&G=4KlZww z*yUTEY1J1s`A+`XDL77BZKwY}dlhyB;4ebIWGos9z-hv-=?>Q+a#zy3t`HdYl+F}| z97zYr577M)9Q(u`))Mir!0I8}CstK^@gchRqWrL=onU-=RMV;mld6^cssKF84A|5* z&$fq|9+6x2ig~N%3!)<5IP=xZ-VztZ-iz*0ktR4bT(#p9Q#ES`4Qli0?R0Kmbnj9s z*iM&pMt|J-=NxE-`)bGj3{*~5yo;ulwk|z68q+)@&NDzjbY z7Q0LVNve@fjje?(HV%BQE8MGQZxtr>7t4Q>1SaTJnx@=(-l z(&snp+;JXY?mK`h-x-m!>UDXedRPvs2kX+yn0C8FZm5S7Io9FNS)bH5(v!YP9=E#sqPC&zQZIx&_G_P6J zr+M(l?+Rvj9cX3m*?Y*FAW`lHen&(aQS!o|(x9%$3z3tDUamFL-=?K3VZL0pu$ z3h}ch=|H{a+y;^A_4*lnXS~J1CDuq*7AMZ`W!k#a`ypL)lb?d=C1y91fhb%KRBqT_ zb66jXoU|;fEEJb1I8*-9*E2-*SdS_!Tf1ywD&92vxOJ~mLq;5PCD`wK!fDlz1L=t_ z0tCA?h3}!)ES1y>suQ$Kiw~R%;H%WCjT3)sjcS*DI{04ulvJ(W=`rQF85(zGlijIe z9lhgHwcbZf!+awW;?rTrHIToS3?E7lApl-A^XOjdbE(1R)0z9z8HUWpi?_rvlkrJ) zY0|WYavGKqR)xFsj%s1mq@FC!pSpe;-jy_t$LpOk5sZbKFPF#n@|oi^V>OHkPS%Q; zXCeL{g=nINEk>Ya3wrtqu;WaY+R@OWySahNKZN))?|9M+L zz}D4hM6M=4(!T7FGKu^Nn5`%O(>;cPVe2OlnogZ10ja_TjGns~UKDsj0_`y=?ueeb zzna5N$()}(`!@H&YBV^9j+jLJBTp`5M0~dKn9O>BN9Y}0?^hC=pIr-1z-%3w$&+_4 z(E4^szd@@ReWt3P!N{XEhT#qkDTD;he|o%%uwkbhCOtpkJ5kw%gs?`g&}VXK~m zB?%2WA@&v^2kC1mV$9%4B$Iez9N<`d(M;g+!x_#EUY)Cv(b)>2;|7l=8g+7FD9fF^ z?+%_cuyz~nD^W-bgk?2NM6|zA+#5?tlZS5`dtx`|7L<$M1eim*x72ZzoiCjGlSqLi zi>6S_`p~i(z?<`)`KAxbY69#|CMu6mCuhP}Ck{vex8u>^$skO6!kECeF!3^Dzc4UdIxp+nO?4)rViUEJQ)(cd8SW@RIKNIvnl=!Cw&Upzn_SGXo}S-&BjrUl}!8# z7c>(4nH>*rzNb{Y=8WqB6{(3R47a83PvG;RZgqOzdfEupAB9XQrSY5wZa{Ju%9z2# zu1UZQrHF>P7+xQWI^Nj4n$QtYSoz~ZY0T7>Bl64FTTPxLaQe-*cAav)5sXsvKl}UQ zq`<9GawYYf9Mstxo*@a+XDpmM%DU%?+Pe0ULWbl?PXWB%wP$7Fuf>$si58(<*liDf z;HC0TMlB^vuia*9up91d*p((9Lv2pT(P=((T|mUc+e5wMI7`y{+qf|8oScT;YD!c~ zG5lw0am6hS$bFi~lP*=_gibGauQcS4N8-UzL%|hNAAhRme&CfWO5vB|xz54kcb{qN zDU_36$OuGCxKn4Qz@}o?b7|hW&-Ml{i;aaC1^0P(v4hjW=vqXpV^g_h_?JWELoX;Z zhP|N-Tw*ClAF2O-#@R4uM|ujR6mUlEZUd@SPuJ7*CR?jxyfz^gCvNuz6UHA;{wmB3 zilNJkvw9vr{V30KP6{~Wfi2!NY%vr(w`eF*0<`%Ra;~n+C!c4}8v&;egvg1k678lL-%~)0tlM zML24Gqg2#FFo>vWi4-=$vd)v6_9a4`z;|PKTxvT4vUX4P6B7%E+?ag-EYP=R4$R|^ zqAD{~&Vdu2)!n5X0wY5<@UpCi1bSZ|UOGq57@)N8v1M-cSHhogt{UqzV;K=>SiHZ$ z;&Qx8M8DL$clht+LffR4ux5mw)Jc3JXcVh>-0DCuoj27ptW)yv z(&`0M z%;zY~IvR$VbT_!QLRHw2hUWl*Ez5fw-zc5`QV>X;x90jv8~i;!{#@IOzH@OMHK3^J zV&vgEW9jstMehB!0GW2HL-L7akCkvQUL&}BwI~}eNw92N9Wm5q|=noQ;jqZr7i6lRwShr~( zaS>=lkEdw<>B@35{DkTss9=q6fr4tnfv~iLp8`dabU&w*kE#0}c|>7<2&9SNcA_3@596eJ>E5YKE$^qP5p)k7c5?#_D)nYA9SLXNWAEJD z%kJkDa-_pnswcmWW>3^HIVNj-o}(>dyhjj$oy_!cleebz3u~sJ<#o4TtEvZxh(X+r zmX_-9maVrP>h5{<(_qO=TtJnY4>y4QZ2@D=kLRnBH)qcfwdb>D=H~3+f+^CE-OwV( z`F`#h`q&}jrlZ30Fg|EH+Jj+ z9kwWeW5%scIrEwK+K0{A6^QE$=mdT|9K~4l5m3nSWzZ5CIIYZ)M>}(J-kFWTxpq@J zds6OE1dQ=rHv`?iJ7xPQKa$h?R@MSVFz=OLJQE^b0XSBjw_QdG$yvWAluv1`FZM?W z9=mpae1K4UUp{?n4N{iQoovlYp7D0Rk1@`juI=?zE{!E~I=>gu)e_*3Pq?)^T%^PGP66<%q)u7C)zbr7KtIZO>Be zk}Y0rGO30!ZDR9Jq+?r{0A2!@Tbsb7&C56c`39elpYT`cM0aK2l!V^IG@U{Jz3cL* zA)<$DOvjInDP00SxZF0qQT$!Ct1*Dq*(?u^Jt0xzR2F;W3<`5Q;AhC+70V?-_iFU8 zm{MmWQ>wChc;iv`9KCe8@|Q9xg64mbF6@Rr;jG~kae4NRf8jHJ8K($ZhYwJ8!QPX? zRH{^PzSVYIx$+_NgPq_Z@{_!YDtUuuj=i8q`_G$P++B?x(hbXV|Ih~$ui!u*ze2KjB8K1;{S{oi;Dfk&EEQ21(-jq5MzoG6eipMZ zlHUOb+Ay3G@0FdFc~X!_W*H(urI$heyg#RsfoP1QLbIgwG9MPz8~~s&W>p*lX0&}v zq}Nyx=Zc>WVz(0BzRk8Zv_`enZUP0}v-yWry~bZPMN?Z8OWl<`=y^rCp4(qLBOlcO z-bo=}!+*oa6U7^jF2*r*xd&{fho<)hJ>0M53Y(Ib`Z~2j3My zUaNPP>OL&0M-um#c=es7P2U)2)sRxfZqg-QoG>pF7q80a>}Jv`In+2JCD>u-fM*l3 zipeKBBS}r&RU;yjm$xz|)xU9EfHuWp8zJ_Z0XqHtV;V0Jk&WN|ARwSUOz#l_`<7O< zF}^(c0{=S7X8f3WcH~_d_GPyl9vdPJPs@waWF9N$XfinYs!;U7=?nH7zjH=w?_wj# zU@nPs&2~_cdNK-}U(pXpR2&{VR(>%jd4e~oXA#yA!^_vz1b{6oSp%>Awx2}#A(9Dc;PFv&6BVl4!bF-hq-@EGjdx<%t-S9Q#WI&==EH!^mHdsHdUCoqhM&I)S!7g8W)O*(1 zuc|yc*fvWDnL66{><<%ISiIhgv0^GtPg^X6c5kg~dS~de?--MBFSZ;2&7>D)%g;Zl z3jHLZTscsXMN5E|!7bxf^QP%%0!7`L#;JTs9d)q?t?FZD0ufoKEwjgd zrWdrPdJjuHwK06$Sy>y--WhLb9)6#6k?V^hWQ$u8!j!$4k1{U2xzJMKc3bWhQAebe z^A7h?_D$qnTAR2_P(oG4WgqolM=pEqD4P2f&O^TF?PXSKPeDwmZoB%rVzo6m!6_`-SIU52*&3wA1}5oSH_;k_tXgxq9PQg3iZjgH1#pSQm-cWI_r)ZJZ{R8d2jr=hV#6Nlg~mM<4)4$lwFXq_0)v4 zb+G+Yy*!x03eJuTmCBLJv6h3XH!LyDzA#aFvY}wBwg|dwmB>))`bG8h0|pXrcpLGs zH7^s)XT17^*i!~OYOSr#$@0aR=S=7$8NEz>2=0wTBsZI5OJ8wFS3cA12UZm;#FiXj zi-Rz#r1HRXSC!`62fVN$dCyBHFFkp5%y0WNQVFnK-?67%JsQ$Xcz%hz_EA}4FFRV* zexT`Uwi$V?E}74O?~SIiTSj;!jLA!lc#7HQqOd!g0jdHotwEYUpGh!VvHY`iop}3& zhHHLla=pXi&O-b~6|%wgkm?y881?dL74ksN?Zo$&3a%}ARNq0049dL_Q(jJS6&Sm7 zPXjz90hp4M%a~i4G8&+hF1=xXx9>OiU-@#S8{x*ypv9t61a8} z%dlo=Zu^C!;>9!@qdp1~Hj7tw^Hv{>w;y-v9_`tOivLmBa@c>kw0tY7CcJusZ<`05 z(x*^9C4OSXkz6*L=U#cso;n-!9fmed#<$eLVbBhL+1?CKc}vYF}*s3&Y<=eJTIhOZI(}= zWou+u)`v%e-|qUeLxkeB{dDzvR41uwcoLPRcPpLa^U>k$dC$M87J!Lc(^%c>=IHUmGL~>8y=ZR)!Z-G z_6K==`(D3`+b7_eL<-)WcKR_DPz1ESKN$$cx+>_FjMskDm>Dqu9v(BZa`p<$b?B8+ zj#;@nA9PXqo8fOMIL){xw#a#f_&)DcEiGZ4x_ux)?>H?%$kdVl1fVa$i%y9WXZ{7< z7e8OnZ%@w|P=0zVGo8NE)O^`DE2l)fUlHeQp6^T8Jfvz0{l*t-i3#md(Tn$2{WanN zBj26YwZ@jqkF6Lcd*h|S^URVb6+Xl&EEHJAteD(pJ@ZUdIHl@nH5!0YBBu?%{UEcO zyTSMvmMob=Yhgl6lNBwY(ayG8GBT>shUH>3rajoY#EW5lsW^&rQ$)vTPtbZ2AHOJZ z$>#x;r0qvTGHM!2KQ;Ds4`|Kac_ zCh*E{vr@eii4JzvCEo4Asmh-4QDK<$XS_^r$EQYbzpV0upJ<5{2Fx$c$?;D21lV4; zFahN?h%tM{FPUD_047PE7B|wPTI8G{jeGYrM!Pz1mS~fk?(lbb^cRYi?r9{Q)2E^d zvirJ@Z1`5V&>JW6=P%iZDZjLu5jju&TDFgRS@6HW{67}?ENdzlQ?2qHH+gG60x42w R_xBh16(cKnnZb=m{{zZ`SOEY4 diff --git a/lib/CPUs/JCpu/doc/memory_map.png b/lib/CPUs/JCpu/doc/memory_map.png deleted file mode 100644 index 30a22a08a2c6fb8ce339c3d68920919a94977aed..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 3545 zcmbtXc{CJm+a61{Y}tvjjK)5iELqDwV~CiEv4$B!Qj%hV<`!re!uUW_mA(7?>+DPoO9pLb3fdyQySeyIAfw5P669ks=|58T|8; zaYzSRztfQ-tPT&ByjTWCJ6egr+|8yAj0g-*U&dX0V+X_XL^rFOWZ* z2koZun&b8Eq-fF#SMpq;J1ROmU2HQA53{Im*^&Z~s^X2%QD1cYD}t3X(Q7zq9Zdos zoE}+0FK1MJDJVCoI){PqSc{AsU1_Lnz;E5^Nq8zcxBE;%4mFiwDgXoG{;fofkl_qm zdsI0k`vxx&h-Pa19fqD4W@ztEgq??UV%+5{wy6R7lHyaMbT~!y?HjypZ z?w#MU`zC_wKvJHk2ki7<{Xb~`4f#Kb(`<3I`Ot~}>LZj3?p@THHFt3R0C^FjX(%4L z<5D8eVNn!@h``Z0CV8QkR-7_uY-KU%Ds}Nt@X7m~IIrBMW`+x`_D6h%eQXG5fyL@G zxnpa=eT`kU0$fwm*B!Cb+XJ3Z(R=EyhY7y-8R@j0n5{B%2DY%&(*jChez(a>_a z4yi=MrL5EB936TVP>9q=KkA?UnF25;9Iwvn8xxHiK4a1}bWoZ+Gd3o=%*_o8+cSF5 zuFeO@c)VXyZp=8}`>!i8XBIB%UQic5#|6>nbe$Aqx7nEkTp;Yvf9$nun0_+*t{}=C z)pb`ze@dLGm}|Z0Tb>@Y;Jz%+U!~AYVq^Y&O=C7W9zWcC?;cxoz#5aBUc>umQPau+ zANY^SWp;&ZS4tmyF>Z^7eW}dQciiLnuC;B?R98pV3BdIpGN!bZ#l(s8=zaw3 z;pyC|*XFq@Goo?@XBdNIihae&ViQ!w5%t}P&5j8qZ^r6=-zAU@tP-ns-G?Zi*B;R| zy4_NY8(_~Z2z%_mw_CJc{5ymrO{HBsQjLOfhcn^%;8R!i+gR`q-((hSMO4>iEQC6& z(;GjizKZcLuDZi9Qzi}wLY*4ud{s^-d~zjoMO&~M!rSE-7iUkD23w!6p8&`Ybk&D4 z5j3{Ez9*+AcsoK)%-gZzRT6e*(^)TEBP^6NgD53yCZ7{N^vWEEzY`e%9p02^z{YqN z3p2!VS@rxVUV(!&j!&;eWtEPBRerwd9;8To*)zOr9ooq0?j)#KS|P z^Ug^6X6Fn>3-Kk+^xRpSV@$m}oE2tOe%gJ@MJ-rgezz1#M;ywiY3J$QPDzqQwzz)^ z0&1$h!Qqip1%ASWB>&T-YGv*3+rzb7sL#D@dQ%j}@J3XGv3m}e#@Xz&dK|rUZhyxV zq#x$fHHr^Z&z!JbM8=-X^&Eoq6k!gr<`p#Je4YnV)t9HdVwA#m_!t>Wdsf%)L#-P) z3S>j@WIsj*{#Kh^Z|d`-BnUoh2{;Jcx?<9oWoUp(S$4ai>*s?Tj&x(`RS1Br2XDyY zC->DX4mFpBlPBly73NH|vn^JV2G_pdK>rj_CWR7A7E+ggEzoyL%XXVSB+jCN{tE2>EBn;{Hgj|^{O)Ca4qj(c`A=Tp|s+60j?L*dK8 z##=>Ph-u=MuYrw^mH>s*#^on3_TtDrkniSxkUZ)Hnyx*_U6@yWuKj%qG05)-nc!UB z#jc#cB7^JmG}bd(rCZ%zh(IGUzb=`IQd%a1un=C8uen7P18af~-j6v8vp+1V`y&iT zH~V#r{5MxXW9zMQsqIpm&hugQdy)ge?jTJf|K+E?J0ojEc12X#)0UsBb?Ue6wH}wc zVC@>bIt=t=%@avY?(naiUZ(c)2AJ9qd5r%f6(`Y_)rX&rBp%=4d~2N84FW2uonaSj zT$#3@0q=lUodPt9!@6a8%(OJMgRHFdJHp(tc2F?{_j~lr%Q}g(TdZ&bKBpwet_B`; z<1`#*laIJ5AF<};TXRaE3ctPYv2e{aNSE+rEloguI7FKoQ2f9958&$(@? za!9X;PxJ5%*x;7Fx#SS7MJjP~WcF;qocWdF?Av;Dl?4n))UDVhN78l4(UPxiPP$dO ze{J_T$PN5|MU(0@qP>@s9uSNx(x-~Oh_Zd4q50z&_99wkpx~+${q`a}77~Vq$aJC09r0krx>> z#p^^N+cA0R!y7n1x#PLv=3JF!gTPO|z7KXz&xH@PVa-j~BQNDzLdfYQ$DUU)(!z;q zFZY&~^WU}G;Fo%8k2_a5Qrd0t&v93!f*c&I!hd`mtMRw8k9}<@Oxdnr76^T|#rz|D z9-%DRvgBc~)3YKV*CHf%D!FG{@T8lAG!^g!1a?DY0mV@LcbBIgh&FAjps6;yr?eX4 z{oss^7b_5Y*>!ZDUvu`o-`?u|mg~_s{1ho8d@M%h43_n-5uu&@m|{&@`k*RLE@lw& z5`l6W$h<*-%=<^qPm+>b zG~`g6;iqwu=W-+Ca~E8wQQm)Z;=Z}%M0FVt@B1nzNC55+DMqWJwEuoAlZ%b$$*=61 z*-5JppKdnxD4NYlqJb;ynkN;GDDj{(z`JIb>aA;pZnexbNbeIXw`NoQHJ`{rb&eK; z#oK1tN`MOtRy8#&tjGQC%{Vk~q>gDSB~3wb+7&CAq*Uz##_yWOmFPTQx&dYR4dW-q z(2c@oKz*4QR%t^k*LmWVo7yq11=*b$@F?xc!G=U3t&#wnFk!Z)ZJ7hthV3o?$6lvw{OQAn(=+b_~*@#EK zjH+P=>kiiMkha3GnZyY;*Bc`R6rb=styjh8frn+TDXp$Ap`(i-{#(U=mFF6`&Rx5a zRI7B2&)uX7&wtsx!-`BT2D0?dK>Zmui9nAbFGpU=VJ=J6b)#)y=tsIEAse5pM^s}U`VrU U+3VN3fBt7MvrDG6##iJ12RA=#&;S4c diff --git a/lib/CPUs/JCpu/gpl-3.0.txt b/lib/CPUs/JCpu/gpl-3.0.txt deleted file mode 100644 index 94a9ed0..0000000 --- a/lib/CPUs/JCpu/gpl-3.0.txt +++ /dev/null @@ -1,674 +0,0 @@ - GNU GENERAL PUBLIC LICENSE - Version 3, 29 June 2007 - - Copyright (C) 2007 Free Software Foundation, Inc. - Everyone is permitted to copy and distribute verbatim copies - of this license document, but changing it is not allowed. - - Preamble - - The GNU General Public License is a free, copyleft license for -software and other kinds of works. - - The licenses for most software and other practical works are designed -to take away your freedom to share and change the works. By contrast, -the GNU General Public License is intended to guarantee your freedom to -share and change all versions of a program--to make sure it remains free -software for all its users. We, the Free Software Foundation, use the -GNU General Public License for most of our software; it applies also to -any other work released this way by its authors. You can apply it to -your programs, too. - - When we speak of free software, we are referring to freedom, not -price. Our General Public Licenses are designed to make sure that you -have the freedom to distribute copies of free software (and charge for -them if you wish), that you receive source code or can get it if you -want it, that you can change the software or use pieces of it in new -free programs, and that you know you can do these things. - - To protect your rights, we need to prevent others from denying you -these rights or asking you to surrender the rights. Therefore, you have -certain responsibilities if you distribute copies of the software, or if -you modify it: responsibilities to respect the freedom of others. - - For example, if you distribute copies of such a program, whether -gratis or for a fee, you must pass on to the recipients the same -freedoms that you received. You must make sure that they, too, receive -or can get the source code. And you must show them these terms so they -know their rights. - - Developers that use the GNU GPL protect your rights with two steps: -(1) assert copyright on the software, and (2) offer you this License -giving you legal permission to copy, distribute and/or modify it. - - For the developers' and authors' protection, the GPL clearly explains -that there is no warranty for this free software. For both users' and -authors' sake, the GPL requires that modified versions be marked as -changed, so that their problems will not be attributed erroneously to -authors of previous versions. - - Some devices are designed to deny users access to install or run -modified versions of the software inside them, although the manufacturer -can do so. This is fundamentally incompatible with the aim of -protecting users' freedom to change the software. The systematic -pattern of such abuse occurs in the area of products for individuals to -use, which is precisely where it is most unacceptable. Therefore, we -have designed this version of the GPL to prohibit the practice for those -products. If such problems arise substantially in other domains, we -stand ready to extend this provision to those domains in future versions -of the GPL, as needed to protect the freedom of users. - - Finally, every program is threatened constantly by software patents. -States should not allow patents to restrict development and use of -software on general-purpose computers, but in those that do, we wish to -avoid the special danger that patents applied to a free program could -make it effectively proprietary. To prevent this, the GPL assures that -patents cannot be used to render the program non-free. - - The precise terms and conditions for copying, distribution and -modification follow. - - TERMS AND CONDITIONS - - 0. Definitions. - - "This License" refers to version 3 of the GNU General Public License. - - "Copyright" also means copyright-like laws that apply to other kinds of -works, such as semiconductor masks. - - "The Program" refers to any copyrightable work licensed under this -License. Each licensee is addressed as "you". "Licensees" and -"recipients" may be individuals or organizations. - - To "modify" a work means to copy from or adapt all or part of the work -in a fashion requiring copyright permission, other than the making of an -exact copy. The resulting work is called a "modified version" of the -earlier work or a work "based on" the earlier work. - - A "covered work" means either the unmodified Program or a work based -on the Program. - - To "propagate" a work means to do anything with it that, without -permission, would make you directly or secondarily liable for -infringement under applicable copyright law, except executing it on a -computer or modifying a private copy. Propagation includes copying, -distribution (with or without modification), making available to the -public, and in some countries other activities as well. - - To "convey" a work means any kind of propagation that enables other -parties to make or receive copies. Mere interaction with a user through -a computer network, with no transfer of a copy, is not conveying. - - An interactive user interface displays "Appropriate Legal Notices" -to the extent that it includes a convenient and prominently visible -feature that (1) displays an appropriate copyright notice, and (2) -tells the user that there is no warranty for the work (except to the -extent that warranties are provided), that licensees may convey the -work under this License, and how to view a copy of this License. If -the interface presents a list of user commands or options, such as a -menu, a prominent item in the list meets this criterion. - - 1. Source Code. - - The "source code" for a work means the preferred form of the work -for making modifications to it. "Object code" means any non-source -form of a work. - - A "Standard Interface" means an interface that either is an official -standard defined by a recognized standards body, or, in the case of -interfaces specified for a particular programming language, one that -is widely used among developers working in that language. - - The "System Libraries" of an executable work include anything, other -than the work as a whole, that (a) is included in the normal form of -packaging a Major Component, but which is not part of that Major -Component, and (b) serves only to enable use of the work with that -Major Component, or to implement a Standard Interface for which an -implementation is available to the public in source code form. A -"Major Component", in this context, means a major essential component -(kernel, window system, and so on) of the specific operating system -(if any) on which the executable work runs, or a compiler used to -produce the work, or an object code interpreter used to run it. - - The "Corresponding Source" for a work in object code form means all -the source code needed to generate, install, and (for an executable -work) run the object code and to modify the work, including scripts to -control those activities. However, it does not include the work's -System Libraries, or general-purpose tools or generally available free -programs which are used unmodified in performing those activities but -which are not part of the work. For example, Corresponding Source -includes interface definition files associated with source files for -the work, and the source code for shared libraries and dynamically -linked subprograms that the work is specifically designed to require, -such as by intimate data communication or control flow between those -subprograms and other parts of the work. - - The Corresponding Source need not include anything that users -can regenerate automatically from other parts of the Corresponding -Source. - - The Corresponding Source for a work in source code form is that -same work. - - 2. Basic Permissions. - - All rights granted under this License are granted for the term of -copyright on the Program, and are irrevocable provided the stated -conditions are met. This License explicitly affirms your unlimited -permission to run the unmodified Program. The output from running a -covered work is covered by this License only if the output, given its -content, constitutes a covered work. This License acknowledges your -rights of fair use or other equivalent, as provided by copyright law. - - You may make, run and propagate covered works that you do not -convey, without conditions so long as your license otherwise remains -in force. You may convey covered works to others for the sole purpose -of having them make modifications exclusively for you, or provide you -with facilities for running those works, provided that you comply with -the terms of this License in conveying all material for which you do -not control copyright. Those thus making or running the covered works -for you must do so exclusively on your behalf, under your direction -and control, on terms that prohibit them from making any copies of -your copyrighted material outside their relationship with you. - - Conveying under any other circumstances is permitted solely under -the conditions stated below. Sublicensing is not allowed; section 10 -makes it unnecessary. - - 3. Protecting Users' Legal Rights From Anti-Circumvention Law. - - No covered work shall be deemed part of an effective technological -measure under any applicable law fulfilling obligations under article -11 of the WIPO copyright treaty adopted on 20 December 1996, or -similar laws prohibiting or restricting circumvention of such -measures. - - When you convey a covered work, you waive any legal power to forbid -circumvention of technological measures to the extent such circumvention -is effected by exercising rights under this License with respect to -the covered work, and you disclaim any intention to limit operation or -modification of the work as a means of enforcing, against the work's -users, your or third parties' legal rights to forbid circumvention of -technological measures. - - 4. Conveying Verbatim Copies. - - You may convey verbatim copies of the Program's source code as you -receive it, in any medium, provided that you conspicuously and -appropriately publish on each copy an appropriate copyright notice; -keep intact all notices stating that this License and any -non-permissive terms added in accord with section 7 apply to the code; -keep intact all notices of the absence of any warranty; and give all -recipients a copy of this License along with the Program. - - You may charge any price or no price for each copy that you convey, -and you may offer support or warranty protection for a fee. - - 5. Conveying Modified Source Versions. - - You may convey a work based on the Program, or the modifications to -produce it from the Program, in the form of source code under the -terms of section 4, provided that you also meet all of these conditions: - - a) The work must carry prominent notices stating that you modified - it, and giving a relevant date. - - b) The work must carry prominent notices stating that it is - released under this License and any conditions added under section - 7. This requirement modifies the requirement in section 4 to - "keep intact all notices". - - c) You must license the entire work, as a whole, under this - License to anyone who comes into possession of a copy. This - License will therefore apply, along with any applicable section 7 - additional terms, to the whole of the work, and all its parts, - regardless of how they are packaged. This License gives no - permission to license the work in any other way, but it does not - invalidate such permission if you have separately received it. - - d) If the work has interactive user interfaces, each must display - Appropriate Legal Notices; however, if the Program has interactive - interfaces that do not display Appropriate Legal Notices, your - work need not make them do so. - - A compilation of a covered work with other separate and independent -works, which are not by their nature extensions of the covered work, -and which are not combined with it such as to form a larger program, -in or on a volume of a storage or distribution medium, is called an -"aggregate" if the compilation and its resulting copyright are not -used to limit the access or legal rights of the compilation's users -beyond what the individual works permit. Inclusion of a covered work -in an aggregate does not cause this License to apply to the other -parts of the aggregate. - - 6. Conveying Non-Source Forms. - - You may convey a covered work in object code form under the terms -of sections 4 and 5, provided that you also convey the -machine-readable Corresponding Source under the terms of this License, -in one of these ways: - - a) Convey the object code in, or embodied in, a physical product - (including a physical distribution medium), accompanied by the - Corresponding Source fixed on a durable physical medium - customarily used for software interchange. - - b) Convey the object code in, or embodied in, a physical product - (including a physical distribution medium), accompanied by a - written offer, valid for at least three years and valid for as - long as you offer spare parts or customer support for that product - model, to give anyone who possesses the object code either (1) a - copy of the Corresponding Source for all the software in the - product that is covered by this License, on a durable physical - medium customarily used for software interchange, for a price no - more than your reasonable cost of physically performing this - conveying of source, or (2) access to copy the - Corresponding Source from a network server at no charge. - - c) Convey individual copies of the object code with a copy of the - written offer to provide the Corresponding Source. This - alternative is allowed only occasionally and noncommercially, and - only if you received the object code with such an offer, in accord - with subsection 6b. - - d) Convey the object code by offering access from a designated - place (gratis or for a charge), and offer equivalent access to the - Corresponding Source in the same way through the same place at no - further charge. You need not require recipients to copy the - Corresponding Source along with the object code. If the place to - copy the object code is a network server, the Corresponding Source - may be on a different server (operated by you or a third party) - that supports equivalent copying facilities, provided you maintain - clear directions next to the object code saying where to find the - Corresponding Source. Regardless of what server hosts the - Corresponding Source, you remain obligated to ensure that it is - available for as long as needed to satisfy these requirements. - - e) Convey the object code using peer-to-peer transmission, provided - you inform other peers where the object code and Corresponding - Source of the work are being offered to the general public at no - charge under subsection 6d. - - A separable portion of the object code, whose source code is excluded -from the Corresponding Source as a System Library, need not be -included in conveying the object code work. - - A "User Product" is either (1) a "consumer product", which means any -tangible personal property which is normally used for personal, family, -or household purposes, or (2) anything designed or sold for incorporation -into a dwelling. In determining whether a product is a consumer product, -doubtful cases shall be resolved in favor of coverage. For a particular -product received by a particular user, "normally used" refers to a -typical or common use of that class of product, regardless of the status -of the particular user or of the way in which the particular user -actually uses, or expects or is expected to use, the product. A product -is a consumer product regardless of whether the product has substantial -commercial, industrial or non-consumer uses, unless such uses represent -the only significant mode of use of the product. - - "Installation Information" for a User Product means any methods, -procedures, authorization keys, or other information required to install -and execute modified versions of a covered work in that User Product from -a modified version of its Corresponding Source. The information must -suffice to ensure that the continued functioning of the modified object -code is in no case prevented or interfered with solely because -modification has been made. - - If you convey an object code work under this section in, or with, or -specifically for use in, a User Product, and the conveying occurs as -part of a transaction in which the right of possession and use of the -User Product is transferred to the recipient in perpetuity or for a -fixed term (regardless of how the transaction is characterized), the -Corresponding Source conveyed under this section must be accompanied -by the Installation Information. But this requirement does not apply -if neither you nor any third party retains the ability to install -modified object code on the User Product (for example, the work has -been installed in ROM). - - The requirement to provide Installation Information does not include a -requirement to continue to provide support service, warranty, or updates -for a work that has been modified or installed by the recipient, or for -the User Product in which it has been modified or installed. Access to a -network may be denied when the modification itself materially and -adversely affects the operation of the network or violates the rules and -protocols for communication across the network. - - Corresponding Source conveyed, and Installation Information provided, -in accord with this section must be in a format that is publicly -documented (and with an implementation available to the public in -source code form), and must require no special password or key for -unpacking, reading or copying. - - 7. Additional Terms. - - "Additional permissions" are terms that supplement the terms of this -License by making exceptions from one or more of its conditions. -Additional permissions that are applicable to the entire Program shall -be treated as though they were included in this License, to the extent -that they are valid under applicable law. If additional permissions -apply only to part of the Program, that part may be used separately -under those permissions, but the entire Program remains governed by -this License without regard to the additional permissions. - - When you convey a copy of a covered work, you may at your option -remove any additional permissions from that copy, or from any part of -it. (Additional permissions may be written to require their own -removal in certain cases when you modify the work.) You may place -additional permissions on material, added by you to a covered work, -for which you have or can give appropriate copyright permission. - - Notwithstanding any other provision of this License, for material you -add to a covered work, you may (if authorized by the copyright holders of -that material) supplement the terms of this License with terms: - - a) Disclaiming warranty or limiting liability differently from the - terms of sections 15 and 16 of this License; or - - b) Requiring preservation of specified reasonable legal notices or - author attributions in that material or in the Appropriate Legal - Notices displayed by works containing it; or - - c) Prohibiting misrepresentation of the origin of that material, or - requiring that modified versions of such material be marked in - reasonable ways as different from the original version; or - - d) Limiting the use for publicity purposes of names of licensors or - authors of the material; or - - e) Declining to grant rights under trademark law for use of some - trade names, trademarks, or service marks; or - - f) Requiring indemnification of licensors and authors of that - material by anyone who conveys the material (or modified versions of - it) with contractual assumptions of liability to the recipient, for - any liability that these contractual assumptions directly impose on - those licensors and authors. - - All other non-permissive additional terms are considered "further -restrictions" within the meaning of section 10. If the Program as you -received it, or any part of it, contains a notice stating that it is -governed by this License along with a term that is a further -restriction, you may remove that term. If a license document contains -a further restriction but permits relicensing or conveying under this -License, you may add to a covered work material governed by the terms -of that license document, provided that the further restriction does -not survive such relicensing or conveying. - - If you add terms to a covered work in accord with this section, you -must place, in the relevant source files, a statement of the -additional terms that apply to those files, or a notice indicating -where to find the applicable terms. - - Additional terms, permissive or non-permissive, may be stated in the -form of a separately written license, or stated as exceptions; -the above requirements apply either way. - - 8. Termination. - - You may not propagate or modify a covered work except as expressly -provided under this License. Any attempt otherwise to propagate or -modify it is void, and will automatically terminate your rights under -this License (including any patent licenses granted under the third -paragraph of section 11). - - However, if you cease all violation of this License, then your -license from a particular copyright holder is reinstated (a) -provisionally, unless and until the copyright holder explicitly and -finally terminates your license, and (b) permanently, if the copyright -holder fails to notify you of the violation by some reasonable means -prior to 60 days after the cessation. - - Moreover, your license from a particular copyright holder is -reinstated permanently if the copyright holder notifies you of the -violation by some reasonable means, this is the first time you have -received notice of violation of this License (for any work) from that -copyright holder, and you cure the violation prior to 30 days after -your receipt of the notice. - - Termination of your rights under this section does not terminate the -licenses of parties who have received copies or rights from you under -this License. If your rights have been terminated and not permanently -reinstated, you do not qualify to receive new licenses for the same -material under section 10. - - 9. Acceptance Not Required for Having Copies. - - You are not required to accept this License in order to receive or -run a copy of the Program. Ancillary propagation of a covered work -occurring solely as a consequence of using peer-to-peer transmission -to receive a copy likewise does not require acceptance. However, -nothing other than this License grants you permission to propagate or -modify any covered work. These actions infringe copyright if you do -not accept this License. Therefore, by modifying or propagating a -covered work, you indicate your acceptance of this License to do so. - - 10. Automatic Licensing of Downstream Recipients. - - Each time you convey a covered work, the recipient automatically -receives a license from the original licensors, to run, modify and -propagate that work, subject to this License. You are not responsible -for enforcing compliance by third parties with this License. - - An "entity transaction" is a transaction transferring control of an -organization, or substantially all assets of one, or subdividing an -organization, or merging organizations. If propagation of a covered -work results from an entity transaction, each party to that -transaction who receives a copy of the work also receives whatever -licenses to the work the party's predecessor in interest had or could -give under the previous paragraph, plus a right to possession of the -Corresponding Source of the work from the predecessor in interest, if -the predecessor has it or can get it with reasonable efforts. - - You may not impose any further restrictions on the exercise of the -rights granted or affirmed under this License. For example, you may -not impose a license fee, royalty, or other charge for exercise of -rights granted under this License, and you may not initiate litigation -(including a cross-claim or counterclaim in a lawsuit) alleging that -any patent claim is infringed by making, using, selling, offering for -sale, or importing the Program or any portion of it. - - 11. Patents. - - A "contributor" is a copyright holder who authorizes use under this -License of the Program or a work on which the Program is based. The -work thus licensed is called the contributor's "contributor version". - - A contributor's "essential patent claims" are all patent claims -owned or controlled by the contributor, whether already acquired or -hereafter acquired, that would be infringed by some manner, permitted -by this License, of making, using, or selling its contributor version, -but do not include claims that would be infringed only as a -consequence of further modification of the contributor version. For -purposes of this definition, "control" includes the right to grant -patent sublicenses in a manner consistent with the requirements of -this License. - - Each contributor grants you a non-exclusive, worldwide, royalty-free -patent license under the contributor's essential patent claims, to -make, use, sell, offer for sale, import and otherwise run, modify and -propagate the contents of its contributor version. - - In the following three paragraphs, a "patent license" is any express -agreement or commitment, however denominated, not to enforce a patent -(such as an express permission to practice a patent or covenant not to -sue for patent infringement). To "grant" such a patent license to a -party means to make such an agreement or commitment not to enforce a -patent against the party. - - If you convey a covered work, knowingly relying on a patent license, -and the Corresponding Source of the work is not available for anyone -to copy, free of charge and under the terms of this License, through a -publicly available network server or other readily accessible means, -then you must either (1) cause the Corresponding Source to be so -available, or (2) arrange to deprive yourself of the benefit of the -patent license for this particular work, or (3) arrange, in a manner -consistent with the requirements of this License, to extend the patent -license to downstream recipients. "Knowingly relying" means you have -actual knowledge that, but for the patent license, your conveying the -covered work in a country, or your recipient's use of the covered work -in a country, would infringe one or more identifiable patents in that -country that you have reason to believe are valid. - - If, pursuant to or in connection with a single transaction or -arrangement, you convey, or propagate by procuring conveyance of, a -covered work, and grant a patent license to some of the parties -receiving the covered work authorizing them to use, propagate, modify -or convey a specific copy of the covered work, then the patent license -you grant is automatically extended to all recipients of the covered -work and works based on it. - - A patent license is "discriminatory" if it does not include within -the scope of its coverage, prohibits the exercise of, or is -conditioned on the non-exercise of one or more of the rights that are -specifically granted under this License. You may not convey a covered -work if you are a party to an arrangement with a third party that is -in the business of distributing software, under which you make payment -to the third party based on the extent of your activity of conveying -the work, and under which the third party grants, to any of the -parties who would receive the covered work from you, a discriminatory -patent license (a) in connection with copies of the covered work -conveyed by you (or copies made from those copies), or (b) primarily -for and in connection with specific products or compilations that -contain the covered work, unless you entered into that arrangement, -or that patent license was granted, prior to 28 March 2007. - - Nothing in this License shall be construed as excluding or limiting -any implied license or other defenses to infringement that may -otherwise be available to you under applicable patent law. - - 12. No Surrender of Others' Freedom. - - If conditions are imposed on you (whether by court order, agreement or -otherwise) that contradict the conditions of this License, they do not -excuse you from the conditions of this License. If you cannot convey a -covered work so as to satisfy simultaneously your obligations under this -License and any other pertinent obligations, then as a consequence you may -not convey it at all. For example, if you agree to terms that obligate you -to collect a royalty for further conveying from those to whom you convey -the Program, the only way you could satisfy both those terms and this -License would be to refrain entirely from conveying the Program. - - 13. Use with the GNU Affero General Public License. - - Notwithstanding any other provision of this License, you have -permission to link or combine any covered work with a work licensed -under version 3 of the GNU Affero General Public License into a single -combined work, and to convey the resulting work. The terms of this -License will continue to apply to the part which is the covered work, -but the special requirements of the GNU Affero General Public License, -section 13, concerning interaction through a network will apply to the -combination as such. - - 14. Revised Versions of this License. - - The Free Software Foundation may publish revised and/or new versions of -the GNU General Public License from time to time. Such new versions will -be similar in spirit to the present version, but may differ in detail to -address new problems or concerns. - - Each version is given a distinguishing version number. If the -Program specifies that a certain numbered version of the GNU General -Public License "or any later version" applies to it, you have the -option of following the terms and conditions either of that numbered -version or of any later version published by the Free Software -Foundation. If the Program does not specify a version number of the -GNU General Public License, you may choose any version ever published -by the Free Software Foundation. - - If the Program specifies that a proxy can decide which future -versions of the GNU General Public License can be used, that proxy's -public statement of acceptance of a version permanently authorizes you -to choose that version for the Program. - - Later license versions may give you additional or different -permissions. However, no additional obligations are imposed on any -author or copyright holder as a result of your choosing to follow a -later version. - - 15. Disclaimer of Warranty. - - THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY -APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT -HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY -OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, -THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM -IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF -ALL NECESSARY SERVICING, REPAIR OR CORRECTION. - - 16. Limitation of Liability. - - IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING -WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES AND/OR CONVEYS -THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY -GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE -USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF -DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD -PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS), -EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF -SUCH DAMAGES. - - 17. Interpretation of Sections 15 and 16. - - If the disclaimer of warranty and limitation of liability provided -above cannot be given local legal effect according to their terms, -reviewing courts shall apply local law that most closely approximates -an absolute waiver of all civil liability in connection with the -Program, unless a warranty or assumption of liability accompanies a -copy of the Program in return for a fee. - - END OF TERMS AND CONDITIONS - - How to Apply These Terms to Your New Programs - - If you develop a new program, and you want it to be of the greatest -possible use to the public, the best way to achieve this is to make it -free software which everyone can redistribute and change under these terms. - - To do so, attach the following notices to the program. It is safest -to attach them to the start of each source file to most effectively -state the exclusion of warranty; and each file should have at least -the "copyright" line and a pointer to where the full notice is found. - - - Copyright (C) - - This program is free software: you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation, either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - -Also add information on how to contact you by electronic and paper mail. - - If the program does terminal interaction, make it output a short -notice like this when it starts in an interactive mode: - - Copyright (C) - This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'. - This is free software, and you are welcome to redistribute it - under certain conditions; type `show c' for details. - -The hypothetical commands `show w' and `show c' should show the appropriate -parts of the General Public License. Of course, your program's commands -might be different; for a GUI interface, you would use an "about box". - - You should also get your employer (if you work as a programmer) or school, -if any, to sign a "copyright disclaimer" for the program, if necessary. -For more information on this, and how to apply and follow the GNU GPL, see -. - - The GNU General Public License does not permit incorporating your program -into proprietary programs. If your program is a subroutine library, you -may consider it more useful to permit linking proprietary applications with -the library. If this is what you want to do, use the GNU Lesser General -Public License instead of this License. But first, please read -. diff --git a/lib/CPUs/JCpu/sim/ModelSim SE .lnk b/lib/CPUs/JCpu/sim/ModelSim SE .lnk deleted file mode 100644 index 1fe4002cf53e2956f215c58e00f2edd07e60eaba..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 1455 zcmds1T}YE*6n^F`6bcjh(d!vBB~3ekf=1#ex!>i>UqD-uOIrk>8dl%d(L})o^#&wz3-|3 zXml}Lfk|aW`9*FG)Duq41Pr&QH09UskJRN&Yj7`CemiwngYz4dNKGVOU5hn3Y_UJH z%@`I7q=ca-aoC-ebtMIvB?V43=$o=1*~-RYc~O`MdyVZtO>s9(yP!oZR&L!ipB->m zs)u!qvZDh&G;?i)hd(!M$*7JZOqf4P39#Bq%c|qZKljEJ$>iOxBW5?;IUT zpma!HmoMlCr)%%!l zC7knN_^BPF-i}UckuG&C%$^3*l_A$wS{o{C*0S`Ukjs$HjNhM-P5%d!&YNUIDa!cm zYf;Hv11e~-((>o?_sOB8c zjMFZXXICi~B0gbQqFvV?mK7)W^$U9Kjq$LWoAoY|7t4!cSdQodN04ED3`LB$4DRXf zT5^U>+F0d2i$4-O?fXPfl*}+=l5-KhHC=wK*M?562E*k3MZI>EIZrniD*8)Gkt%9z zjA8)s7-5Xx)F+=K$E}Y?1}>@I=kyh4_Q;jwX=9I^F*ByTHxaXjA!@YDjo~5dO%C+P zcE)}oiJT*8MZu#)<17a2qo}Q&?NY$qq1HHF+xw<<`_{^#`54`!6T_Fg8Xw0#57=DgXcg diff --git a/lib/CPUs/JCpu/sim/tb_cpu.fdo b/lib/CPUs/JCpu/sim/tb_cpu.fdo deleted file mode 100644 index 86feedf..0000000 --- a/lib/CPUs/JCpu/sim/tb_cpu.fdo +++ /dev/null @@ -1,22 +0,0 @@ -## NOTE: Do not edit this file. -## -vlib work -vcom -explicit -93 "../../../PCK_FIO-1.16/PCK_FIO.vhd" -vcom -explicit -93 "../src/core/cpu_pkg.vhd" -vcom -explicit -93 "../src/core/stack_ctrl.vhd" -vcom -explicit -93 "../src/core/reg_dual.vhd" -vcom -explicit -93 "../src/core/chipram.vhd" -vcom -explicit -93 "../src/core/chipreg.vhd" -vcom -explicit -93 "../src/core/pc.vhd" -vcom -explicit -93 "../src/core/dpath_ctrl.vhd" -vcom -explicit -93 "../src/core/int_ctrl.vhd" -vcom -explicit -93 "../src/core/alu.vhd" -vcom -explicit -93 "../src/core/cpu.vhd" -vcom -explicit -93 "../src/itest_irom.vhdl" -vcom -explicit -93 "../src/tb_cpu_itest.vhd" -vsim -t 1ps -lib work tb_cpu -do {tb_cpu.wdo} -view wave -view structure -view signals -run 50us diff --git a/lib/CPUs/JCpu/sim/tb_cpu.wdo b/lib/CPUs/JCpu/sim/tb_cpu.wdo deleted file mode 100644 index 2ef036e..0000000 --- a/lib/CPUs/JCpu/sim/tb_cpu.wdo +++ /dev/null @@ -1,107 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_cpu/rst -add wave -noupdate -format Logic /tb_cpu/clk -add wave -noupdate -format Logic /tb_cpu/ce -add wave -noupdate -format Logic /tb_cpu/uut/cpu_active -add wave -noupdate -format Logic /tb_cpu/int_in -add wave -noupdate -format Logic /tb_cpu/int_ack -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/irom_data -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/irom_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/xmem_din -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/xmem_dout -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/xmem_addr -add wave -noupdate -format Logic /tb_cpu/xmem_we -add wave -noupdate -format Logic /tb_cpu/xmem_re -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/sram -add wave -noupdate -format Logic /tb_cpu/uut/io_sel -add wave -noupdate -format Literal /tb_cpu/uut/iphase -add wave -noupdate -divider CPU -add wave -noupdate -format Literal /tb_cpu/reg -add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname -add wave -noupdate -format Literal /tb_cpu/uut/cpu_status -add wave -noupdate -format Literal /tb_cpu/uut/status_reg -add wave -noupdate -format Literal /tb_cpu/uut/ctrl -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/stk_out -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/stk_in -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/stk_reg -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/pc_in -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/pc_next -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/idata -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/int_pc_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/iphase -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/const_data -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/reg_a_dout -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/reg_b_dout -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/reg_din -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/alu_op1 -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/alu_op2 -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/alu_result -add wave -noupdate -format Literal /tb_cpu/uut/alu_status -add wave -noupdate -format Logic /tb_cpu/uut/pc_inc -add wave -noupdate -format Logic /tb_cpu/uut/pc_load -add wave -noupdate -format Logic /tb_cpu/uut/stk_we -add wave -noupdate -format Logic /tb_cpu/uut/cmem_we -add wave -noupdate -format Literal /tb_cpu/uut/ctrl_iphase -add wave -noupdate -format Logic /tb_cpu/uut/was_pcld -add wave -noupdate -format Logic /tb_cpu/uut/was_pop2pc -add wave -noupdate -format Logic /tb_cpu/uut/int_pc_load -add wave -noupdate -format Logic /tb_cpu/uut/int_stk_push -add wave -noupdate -format Logic /tb_cpu/uut/stk_push -add wave -noupdate -format Logic /tb_cpu/uut/stk_pop -add wave -noupdate -format Logic /tb_cpu/uut/status_save -add wave -noupdate -format Logic /tb_cpu/uut/status_restore -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/stk_ptr -add wave -noupdate -divider Stack -add wave -noupdate -format Logic /tb_cpu/clk -add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname -add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/push -add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/pop -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_stack_ctrl/din -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_stack_ctrl/dout -add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/mem_we -add wave -noupdate -divider Chipram -add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/we_a -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/din_a -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/addr_a -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/dout_a -add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/we_b -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/din_b -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/addr_b -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/dout_b -add wave -noupdate -divider Sequencer -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_dpath_ctrl/inst_in -add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/iphase_in -add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/status_in -add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/ctrl_out -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_dpath_ctrl/idout -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_dpath_ctrl/ddout -add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/opcode -add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/ctrl_lines -add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_cpu/uut/inst_reg_ab/mem -add wave -noupdate -divider {Chip register} -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/creg_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/creg_din -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/creg_dout -add wave -noupdate -format Literal /tb_cpu/uut/creg_ctrl_out -add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname -add wave -noupdate -format Logic /tb_cpu/clk -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_exit -add wave -noupdate -format Literal /tb_cpu/uut/inst_int_ctrl/int_state -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {136355 ps} 0} -configure wave -namecolwidth 166 -configure wave -valuecolwidth 101 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -update -WaveRestoreZoom {93532 ps} {206468 ps} diff --git a/lib/CPUs/JCpu/sim/tb_cpu_embedded.fdo b/lib/CPUs/JCpu/sim/tb_cpu_embedded.fdo deleted file mode 100644 index bf718fb..0000000 --- a/lib/CPUs/JCpu/sim/tb_cpu_embedded.fdo +++ /dev/null @@ -1,22 +0,0 @@ -## NOTE: Do not edit this file. -## -vlib work -vcom -explicit -93 "../src/core/cpu_pkg.vhd" -vcom -explicit -93 "../src/core/stack_ctrl.vhd" -vcom -explicit -93 "../src/core/reg_dual.vhd" -vcom -explicit -93 "../src/core/chipram.vhd" -vcom -explicit -93 "../src/core/chipreg.vhd" -vcom -explicit -93 "../src/core/pc.vhd" -vcom -explicit -93 "../src/core/dpath_ctrl.vhd" -vcom -explicit -93 "../src/core/int_ctrl.vhd" -vcom -explicit -93 "../src/core/alu.vhd" -vcom -explicit -93 "../src/core/cpu.vhd" -vcom -explicit -93 "../src/cpu_embedded.vhd" -vcom -explicit -93 "../src/tb_cpu_embedded.vhd" -vcom -explicit -93 "../src/itest_irom.vhdl" -vsim -t 1ps -lib work tb_cpu_embedded -do {tb_cpu_embedded.wdo} -view wave -view structure -view signals -run 10us diff --git a/lib/CPUs/JCpu/sim/tb_cpu_embedded.wdo b/lib/CPUs/JCpu/sim/tb_cpu_embedded.wdo deleted file mode 100644 index caec2d7..0000000 --- a/lib/CPUs/JCpu/sim/tb_cpu_embedded.wdo +++ /dev/null @@ -1,26 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_cpu_embedded/rst -add wave -noupdate -format Logic /tb_cpu_embedded/clk -add wave -noupdate -format Logic /tb_cpu_embedded/ce -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu_embedded/sram -add wave -noupdate -format Logic /tb_cpu_embedded/int_in -add wave -noupdate -format Logic /tb_cpu_embedded/int_ack -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu_embedded/uut/rom_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu_embedded/uut/rom_data -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {2168142 ps} 0} -configure wave -namecolwidth 143 -configure wave -valuecolwidth 101 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -update -WaveRestoreZoom {0 ps} {10500 ns} diff --git a/lib/CPUs/JCpu/sim/tb_cpu_itest.fdo b/lib/CPUs/JCpu/sim/tb_cpu_itest.fdo deleted file mode 100644 index 77ca67d..0000000 --- a/lib/CPUs/JCpu/sim/tb_cpu_itest.fdo +++ /dev/null @@ -1,22 +0,0 @@ -## NOTE: Do not edit this file. -## -vlib work -vcom -explicit -93 "../../../PCK_FIO-1.16/PCK_FIO.vhd" -vcom -explicit -93 "../src/core/cpu_pkg.vhd" -vcom -explicit -93 "../src/core/stack_ctrl.vhd" -vcom -explicit -93 "../src/core/reg_dual.vhd" -vcom -explicit -93 "../src/core/chipram.vhd" -vcom -explicit -93 "../src/core/chipreg.vhd" -vcom -explicit -93 "../src/core/pc.vhd" -vcom -explicit -93 "../src/core/dpath_ctrl.vhd" -vcom -explicit -93 "../src/core/int_ctrl.vhd" -vcom -explicit -93 "../src/core/alu.vhd" -vcom -explicit -93 "../src/core/cpu.vhd" -vcom -explicit -93 "../src/itest_irom.vhdl" -vcom -explicit -93 "../src/tb_cpu_itest.vhd" -vsim -t 1ps -lib work tb_cpu -do {tb_cpu_itest.wdo} -view wave -view structure -view signals -run 400us diff --git a/lib/CPUs/JCpu/sim/tb_cpu_itest.wdo b/lib/CPUs/JCpu/sim/tb_cpu_itest.wdo deleted file mode 100644 index c3e2205..0000000 --- a/lib/CPUs/JCpu/sim/tb_cpu_itest.wdo +++ /dev/null @@ -1,122 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_cpu/rst -add wave -noupdate -format Logic /tb_cpu/clk -add wave -noupdate -format Logic /tb_cpu/ce -add wave -noupdate -format Logic /tb_cpu/int_in -add wave -noupdate -format Logic /tb_cpu/int_ack -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/irom_data -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/irom_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/xmem_din -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/xmem_dout -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/xmem_addr -add wave -noupdate -format Logic /tb_cpu/xmem_we -add wave -noupdate -format Logic /tb_cpu/xmem_re -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/sram -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_cpu/reg -add wave -noupdate -format Logic /tb_cpu/uut/io_sel -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/mem_data -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/mem_addr -add wave -noupdate -divider CPU -add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname -add wave -noupdate -format Literal /tb_cpu/uut/cpu_status -add wave -noupdate -format Literal /tb_cpu/uut/status_reg -add wave -noupdate -format Literal /tb_cpu/uut/ctrl -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/stk_out -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/stk_in -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/stk_reg -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/pc_in -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/pc_next -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/idata -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/int_pc_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/iphase -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/const_data -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/reg_a_dout -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/reg_b_dout -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/reg_din -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/alu_op1 -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/alu_op2 -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/alu_result -add wave -noupdate -format Literal /tb_cpu/uut/alu_status -add wave -noupdate -format Logic /tb_cpu/uut/pc_inc -add wave -noupdate -format Logic /tb_cpu/uut/pc_load -add wave -noupdate -format Logic /tb_cpu/uut/cpu_active -add wave -noupdate -format Logic /tb_cpu/uut/stk_we -add wave -noupdate -format Logic /tb_cpu/uut/cmem_we -add wave -noupdate -format Literal /tb_cpu/uut/ctrl_iphase -add wave -noupdate -format Logic /tb_cpu/uut/was_pcld -add wave -noupdate -format Logic /tb_cpu/uut/was_pop2pc -add wave -noupdate -format Logic /tb_cpu/uut/int_pc_load -add wave -noupdate -format Logic /tb_cpu/uut/int_stk_push -add wave -noupdate -format Logic /tb_cpu/uut/stk_push -add wave -noupdate -format Logic /tb_cpu/uut/stk_pop -add wave -noupdate -format Logic /tb_cpu/uut/status_save -add wave -noupdate -format Logic /tb_cpu/uut/status_restore -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/stk_ptr -add wave -noupdate -divider Stack -add wave -noupdate -format Logic /tb_cpu/clk -add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname -add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/push -add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/pop -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_stack_ctrl/din -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_stack_ctrl/dout -add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/mem_we -add wave -noupdate -divider Chipram -add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/we_a -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/din_a -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/addr_a -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/dout_a -add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/we_b -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/din_b -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/addr_b -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/dout_b -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/ram -add wave -noupdate -divider Sequencer -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/reg -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_dpath_ctrl/inst_in -add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/iphase_in -add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/status_in -add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/ctrl_out -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_dpath_ctrl/idout -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_dpath_ctrl/ddout -add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/opcode -add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/ctrl_lines -add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_cpu/uut/inst_reg_ab/mem -add wave -noupdate -divider {Chip register} -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/creg_dout -add wave -noupdate -format Literal /tb_cpu/uut/creg_ctrl_out -add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname -add wave -noupdate -format Logic /tb_cpu/clk -add wave -noupdate -divider {Interrup Ctrl.} -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_in -add wave -noupdate -format Literal -expand /tb_cpu/uut/inst_int_ctrl/ctrl_in -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_request -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_ack -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_exit -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_ack_out -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stat_save_out -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stat_rest_out -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/pc_load_out -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stk_push_out -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stk_pop_out -add wave -noupdate -format Literal /tb_cpu/uut/inst_int_ctrl/int_state -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/pc_load -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stk_push -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stk_pop -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {107309645 ps} 0} -configure wave -namecolwidth 166 -configure wave -valuecolwidth 101 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -update -WaveRestoreZoom {0 ps} {420 us} diff --git a/lib/CPUs/JCpu/sim/tb_cpu_reti_issue.fdo b/lib/CPUs/JCpu/sim/tb_cpu_reti_issue.fdo deleted file mode 100644 index aba9eda..0000000 --- a/lib/CPUs/JCpu/sim/tb_cpu_reti_issue.fdo +++ /dev/null @@ -1,22 +0,0 @@ -## NOTE: Do not edit this file. -## -vlib work -vcom -explicit -93 "../../../PCK_FIO-1.16/PCK_FIO.vhd" -vcom -explicit -93 "../src/core/cpu_pkg.vhd" -vcom -explicit -93 "../src/core/stack_ctrl.vhd" -vcom -explicit -93 "../src/core/reg_dual.vhd" -vcom -explicit -93 "../src/core/chipram.vhd" -vcom -explicit -93 "../src/core/chipreg.vhd" -vcom -explicit -93 "../src/core/pc.vhd" -vcom -explicit -93 "../src/core/dpath_ctrl.vhd" -vcom -explicit -93 "../src/core/int_ctrl.vhd" -vcom -explicit -93 "../src/core/alu.vhd" -vcom -explicit -93 "../src/core/cpu.vhd" -vcom -explicit -93 "../src/reti_issue_irom.vhdl" -vcom -explicit -93 "../src/tb_cpu_irq.vhd" -vsim -t 1ps -lib work tb_cpu -do {tb_cpu_reti_issue.wdo} -view wave -view structure -view signals -run 50us diff --git a/lib/CPUs/JCpu/sim/tb_cpu_reti_issue.wdo b/lib/CPUs/JCpu/sim/tb_cpu_reti_issue.wdo deleted file mode 100644 index d6d7e7e..0000000 --- a/lib/CPUs/JCpu/sim/tb_cpu_reti_issue.wdo +++ /dev/null @@ -1,90 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Literal /tb_cpu/uut/iphase -add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/ctrl_lines -add wave -noupdate -format Literal /tb_cpu/reg -add wave -noupdate -format Logic /tb_cpu/int_in -add wave -noupdate -format Logic /tb_cpu/int_ack -add wave -noupdate -format Literal /tb_cpu/xmem_din -add wave -noupdate -format Literal /tb_cpu/xmem_dout -add wave -noupdate -format Literal /tb_cpu/xmem_addr -add wave -noupdate -format Logic /tb_cpu/xmem_we -add wave -noupdate -format Logic /tb_cpu/xmem_re -add wave -noupdate -format Logic /tb_cpu/io_sel -add wave -noupdate -format Literal /tb_cpu/sram -add wave -noupdate -divider {Chip RAM} -add wave -noupdate -format Literal /tb_cpu/uut/iphase -add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname -add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/clka -add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/clkb -add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/en_a -add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/en_b -add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/we_a -add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/we_b -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/addr_a -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/addr_b -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/din_a -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/din_b -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/dout_a -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/dout_b -add wave -noupdate -divider {Interrupt controller} -add wave -noupdate -format Literal /tb_cpu/uut/iphase -add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/rst -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/clk -add wave -noupdate -format Literal /tb_cpu/uut/inst_int_ctrl/ctrl_in -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_in -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_request -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_exit -add wave -noupdate -format Literal /tb_cpu/uut/inst_int_ctrl/iphase_in -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_int_ctrl/pc_addr_out -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_ack -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stat_save_out -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stat_rest_out -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/pc_load_out -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stk_push_out -add wave -noupdate -format Literal /tb_cpu/uut/inst_int_ctrl/int_state -add wave -noupdate -format Literal /tb_cpu/uut/inst_int_ctrl/int_state_next -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/pc_load -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stk_push -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stk_pop -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stk_pop_out -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stk_push_out -add wave -noupdate -divider PC -add wave -noupdate -format Literal /tb_cpu/uut/iphase -add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname -add wave -noupdate -format Logic /tb_cpu/uut/inst_pc/rst -add wave -noupdate -format Logic /tb_cpu/uut/inst_pc/clk -add wave -noupdate -format Logic /tb_cpu/uut/inst_pc/inc -add wave -noupdate -format Logic /tb_cpu/uut/inst_pc/load -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_pc/pc_in -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_pc/pc_out -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_pc/pc_next -add wave -noupdate -divider {Stack controller} -add wave -noupdate -format Literal /tb_cpu/uut/iphase -add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname -add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/rst -add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/clk -add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/push -add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/pop -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_stack_ctrl/ptr_out -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_stack_ctrl/din -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_stack_ctrl/dout -add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/mem_we -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_stack_ctrl/ptr -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {0 ps} 0} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -update -WaveRestoreZoom {0 ps} {47421482 ps} diff --git a/lib/CPUs/JCpu/sim/tb_mul8x8.fdo b/lib/CPUs/JCpu/sim/tb_mul8x8.fdo deleted file mode 100644 index 5a852a4..0000000 --- a/lib/CPUs/JCpu/sim/tb_mul8x8.fdo +++ /dev/null @@ -1,22 +0,0 @@ -## NOTE: Do not edit this file. -## -vlib work -vcom -explicit -93 "../src/core/cpu_pkg.vhd" -vcom -explicit -93 "../src/core/stack_ctrl.vhd" -vcom -explicit -93 "../src/core/reg_dual.vhd" -vcom -explicit -93 "../src/core/chipram.vhd" -vcom -explicit -93 "../src/core/chipreg.vhd" -vcom -explicit -93 "../src/core/pc.vhd" -vcom -explicit -93 "../src/core/dpath_ctrl.vhd" -vcom -explicit -93 "../src/core/int_ctrl.vhd" -vcom -explicit -93 "../src/core/alu.vhd" -vcom -explicit -93 "../src/core/cpu.vhd" -vcom -explicit -93 "../src/cpu_embedded.vhd" -vcom -explicit -93 "../src/tb_cpu_embedded.vhd" -vcom -explicit -93 "../src/mul8x8_irom.vhdl" -vsim -t 1ps -lib work tb_cpu_embedded -do {tb_mul8x8.wdo} -view wave -view structure -view signals -run 10us diff --git a/lib/CPUs/JCpu/sim/tb_mul8x8.wdo b/lib/CPUs/JCpu/sim/tb_mul8x8.wdo deleted file mode 100644 index 355e0a4..0000000 --- a/lib/CPUs/JCpu/sim/tb_mul8x8.wdo +++ /dev/null @@ -1,31 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_cpu_embedded/uut/inst_cpu/rst -add wave -noupdate -format Logic /tb_cpu_embedded/uut/inst_cpu/clk -add wave -noupdate -format Logic /tb_cpu_embedded/uut/inst_cpu/ce -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu_embedded/uut/inst_cpu/instr_din -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu_embedded/uut/inst_cpu/instr_addr -add wave -noupdate -format Literal /tb_cpu_embedded/uut/inst_cpu/cpu_status -add wave -noupdate -format Literal /tb_cpu_embedded/uut/inst_cpu/status_reg -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu_embedded/uut/inst_cpu/alu_op1 -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu_embedded/uut/inst_cpu/alu_op2 -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu_embedded/uut/inst_cpu/alu_result -add wave -noupdate -format Literal /tb_cpu_embedded/uut/inst_cpu/alu_status -add wave -noupdate -format Literal /tb_cpu_embedded/uut/inst_cpu/inst_dpath_ctrl/dbg_iname -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_cpu_embedded/uut/inst_cpu/inst_reg_ab/mem -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {529679 ps} 0} -configure wave -namecolwidth 143 -configure wave -valuecolwidth 101 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -update -WaveRestoreZoom {9002500 ps} {10052500 ps} diff --git a/lib/CPUs/JCpu/src/core/alu.vhd b/lib/CPUs/JCpu/src/core/alu.vhd deleted file mode 100644 index 19b3478..0000000 --- a/lib/CPUs/JCpu/src/core/alu.vhd +++ /dev/null @@ -1,236 +0,0 @@ --------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: The arithmetic logic unit --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.cpu_pkg.all; - -entity alu is - Generic ( - data_width : integer := 8 - ); - Port ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - op_en : in STD_LOGIC; - cy_in : in STD_LOGIC; - op1_in : in unsigned (data_width-1 downto 0); - op2_in : in unsigned (data_width-1 downto 0); - opsel : in alu_op_t; - res_out : out unsigned (data_width-1 downto 0); - stat_load : in STD_LOGIC; - stat_in : in alu_status_t; - stat_out : out alu_status_t - ); -end alu; - -architecture Behavioral of alu is - - signal sum_cy, sh_cy, sum_cy_in, sh_cy_in, left_shift, add_subn : STD_LOGIC; - signal result, sum_res, lf_res, sh_res, res_reg : unsigned (data_width-1 downto 0); - signal status, stat_reg : alu_status_t; - - -------------------------------------------------------------------------- - function test_zero(arg : unsigned) return STD_LOGIC is - variable result : STD_LOGIC; - begin - result := '0'; - for i in arg'range loop - result := result or To_X01(arg(i)); - end loop; - - return not result; - end test_zero; - --------------------------------------------------------------------------- -begin - --------------------------------------------------------------------------- -proc_logic_func: - process (op1_in, op2_in, opsel) - begin - - case opsel is - when op1_and_op2 => - lf_res <= op1_in and op2_in; - when op1_or_op2 => - lf_res <= op1_in or op2_in; - when op1_xor_op2 => - lf_res <= op1_in xor op2_in; - when others => - lf_res <= (others => '-'); - end case; - - end process; - --------------------------------------------------------------------------- -proc_shift_func: - process (op1_in, left_shift, sh_cy_in) - begin - if left_shift = '1' then - sh_res <= op1_in(op1_in'left-1 downto op1_in'right) & sh_cy_in; - sh_cy <= op1_in(op1_in'left); - else - sh_res <= sh_cy_in & op1_in(op1_in'left downto op1_in'right+1); - sh_cy <= op1_in(op1_in'right); - end if; - - end process; - --------------------------------------------------------------------------- -proc_alu_out: - process(opsel, op1_in, op2_in, res_reg, stat_reg, lf_res, sum_res, sh_res, sum_cy, sh_cy, cy_in) - - begin - - case opsel is - - when op1_add_op2 | op1_sub_op2 | op1_addc_op2 | op1_subc_op2 => - status.zero <= test_zero(res_reg); - status.carry <= sum_cy; - result <= sum_res; - when op1_and_op2 | op1_or_op2 | op1_xor_op2 => - status.zero <= test_zero(res_reg); - status.carry <= stat_reg.carry; - result <= lf_res; - when shl_op | shr_op | rol_op | ror_op | rolc_op | rorc_op => - status.zero <= test_zero(res_reg); - status.carry <= sh_cy; - result <= sh_res; - when swap_op => - result <= op1_in(op1_in'left-op1_in'length/2 downto op1_in'right) & op1_in(op1_in'left downto op1_in'right+op1_in'length/2); - status <= stat_reg; - when others => - result <= op2_in; - status.zero <= stat_reg.zero; - status.carry <= stat_reg.carry or cy_in; - end case; - - end process; - --------------------------------------------------------------------------- -proc_alu_in: - process(opsel, op1_in, stat_reg) - - begin - - add_subn <= '-'; - sum_cy_in <= '-'; - sh_cy_in <= '-'; - left_shift <= '-'; - - case opsel is - - when op1_add_op2 => - sum_cy_in <= '0'; - add_subn <= '1'; - - when op1_sub_op2 => - sum_cy_in <= '0'; - add_subn <= '0'; - - when op1_addc_op2 => - sum_cy_in <= stat_reg.carry; - add_subn <= '1'; - - when op1_subc_op2 => - sum_cy_in <= stat_reg.carry; - add_subn <= '0'; - - when shl_op => - sh_cy_in <= '0'; - left_shift <= '1'; - - when shr_op => - sh_cy_in <= '0'; - left_shift <= '0'; - - when rol_op => - sh_cy_in <= op1_in(op1_in'left); - left_shift <= '1'; - - when ror_op => - sh_cy_in <= op1_in(op1_in'right); - left_shift <= '0'; - - when rolc_op => - sh_cy_in <= stat_reg.carry; - left_shift <= '1'; - - when rorc_op => - sh_cy_in <= stat_reg.carry; - left_shift <= '0'; - - when others => null; - - end case; - - end process; - --------------------------------------------------------------------------- -proc_res_reg: - process(clk, rst, op_en, stat_load, res_reg, stat_reg) - begin - if rst = '1' then - res_reg <= (others => '0'); - stat_reg <= (others => '0'); - elsif rising_edge(clk) then - if op_en = '1' then - res_reg <= result; - stat_reg <= status; - elsif stat_load = '1' then - stat_reg <= stat_in; - end if; - end if; - res_out <= res_reg; - stat_out <= stat_reg; - - end process; - --------------------------------------------------------------------------- -alu_addsub: - process(op1_in, op2_in, sum_cy_in, add_subn) - variable sum : unsigned(data_width+1 downto 0); - variable op1, op2 : unsigned(data_width+1 downto 0); - begin - if add_subn = '1' then - op1 := '0' & op1_in & '1'; - op2 := '0' & op2_in & sum_cy_in; - sum := op1 + op2; - else - op1 := '0' & op1_in & not sum_cy_in; - op2 := '0' & op2_in & '1'; - sum := op1 - op2; - end if; - - -- Form sum + carry - sum_res <= sum(data_width downto 1); - sum_cy <= sum(sum'left); - - end process; - --------------------------------------------------------------------------- -end Behavioral; - diff --git a/lib/CPUs/JCpu/src/core/chipram.vhd b/lib/CPUs/JCpu/src/core/chipram.vhd deleted file mode 100644 index a954a77..0000000 --- a/lib/CPUs/JCpu/src/core/chipram.vhd +++ /dev/null @@ -1,85 +0,0 @@ --------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: On-chip RAM --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.cpu_pkg.all; - -entity chipram is - Generic ( - addr_width : integer := 3; - data_width : integer := 8 - ); - Port ( - clka : in STD_LOGIC; - clkb : in STD_LOGIC; - en_a : in STD_LOGIC; - en_b : in STD_LOGIC; - we_a : in STD_LOGIC; - we_b : in STD_LOGIC; - addr_a : in unsigned (addr_width-1 downto 0); - addr_b : in unsigned (addr_width-1 downto 0); - din_a : in unsigned (data_width-1 downto 0); - din_b : in unsigned (data_width-1 downto 0); - dout_a : out unsigned (data_width-1 downto 0); - dout_b : out unsigned (data_width-1 downto 0) - ); -end chipram; - -architecture Behavioral of chipram is - - constant depth : integer := 2**addr_width; - type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0); - shared variable RAM : RAMtype; - -begin - -process (clka) -begin -if clka'event and clka = '1' then - if en_a = '1' then - if we_a = '1' then - RAM(to_integer(addr_a)) := din_a; - end if; - dout_a <= RAM(to_integer(addr_a)); - end if; -end if; -end process; - -process (clkb) -begin -if clkb'event and clkb = '1' then - if en_b = '1' then - if we_b = '1' then - RAM(to_integer(addr_b)) := din_b; - end if; - dout_b <= RAM(to_integer(addr_b)); - end if; -end if; -end process; - - -end Behavioral; - diff --git a/lib/CPUs/JCpu/src/core/chipreg.vhd b/lib/CPUs/JCpu/src/core/chipreg.vhd deleted file mode 100644 index 6c5b9f1..0000000 --- a/lib/CPUs/JCpu/src/core/chipreg.vhd +++ /dev/null @@ -1,117 +0,0 @@ --------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: On-Chip registers --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.cpu_pkg.all; - -entity chipreg is - Port ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - we : in STD_LOGIC; - addr : in dmem_addr_t; - din : in dmem_data_t; - dout : out dmem_data_t; - ctrl_in : in creg_ctrl_in_t; - ctrl_out : out creg_ctrl_out_t - ); -end chipreg; - -architecture Behavioral of chipreg is - - signal reg_bank_sel : bank_sel_t; - signal reg_int_ctrl : int_ctrl_in_t; - signal reg_stk_high : unsigned(IMEM_ADDR_WIDTH-DMEM_ADDR_WIDTH-1 downto 0); - signal reg_cmem_high : unsigned(IMEM_ADDR_WIDTH-DMEM_ADDR_WIDTH-1 downto 0); - -begin - -proc_assign_ctrl_lines: - process (clk) - begin - if rising_edge(clk) then - ctrl_out.bank_sel <= reg_bank_sel; - ctrl_out.int_ctrl <= reg_int_ctrl; - ctrl_out.stk_high <= reg_stk_high; - ctrl_out.cmem_high <= reg_cmem_high; - end if; - end process; - -proc_reg_write: - process (rst, clk) - begin - if rst = '1' then - reg_stk_high <= (others => '0'); - reg_cmem_high <= (others => '0'); - reg_bank_sel <= (others => '0'); - reg_int_ctrl.enable <= '0'; - elsif rising_edge(clk) then - if we = '1' then - case addr is - when X"01" => - reg_bank_sel(bank_sel_t'range) <= din(bank_sel_t'range); - when X"03" => - reg_int_ctrl.enable <= din(0); - when X"04" => - reg_cmem_high <= din(IMEM_ADDR_WIDTH-DMEM_ADDR_WIDTH-1 downto 0); - when X"05" => - reg_stk_high <= din(IMEM_ADDR_WIDTH-DMEM_ADDR_WIDTH-1 downto 0); - when others => null; - end case; - end if; - end if; - end process; - -proc_reg_read: - process (clk) - begin - if rising_edge(clk) then - case addr is - when X"00" => -- Revison - dout <= to_unsigned(REVISION, dmem_data_t'length); - when X"01" => -- Control 0 - dout <= (7 downto bank_sel_t'length => '0') & reg_bank_sel; - when X"02" => -- CPU status - dout <= "000000" & ctrl_in.alu.carry & ctrl_in.alu.zero; - when X"03" => -- Interrupt control - dout <= "0000000" & reg_int_ctrl.enable; - when X"04" => -- Upper stack bits out - dout <= "0000" & reg_cmem_high; - when X"05" => -- Upper cmem bits out - dout <= "0000" & reg_stk_high; - when others => - if addr(0) = '0' then - dout <= X"DE"; - else - dout <= X"AD"; - end if; - end case; - - end if; - end process; - -end Behavioral; - diff --git a/lib/CPUs/JCpu/src/core/cpu.vhd b/lib/CPUs/JCpu/src/core/cpu.vhd deleted file mode 100644 index 38e8686..0000000 --- a/lib/CPUs/JCpu/src/core/cpu.vhd +++ /dev/null @@ -1,563 +0,0 @@ --------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: JCPU top file --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.cpu_pkg.all; - -entity cpu is - Generic ( - use_instr_register : boolean := false; - use_ctrl_rom : boolean := true - - ); - Port ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - ce : in STD_LOGIC; - int_in : in STD_LOGIC; - int_ack : out STD_LOGIC; - xmem_we : out STD_LOGIC; - xmem_re : out STD_LOGIC; - instr_din : in unsigned (IMEM_DATA_WIDTH-1 downto 0); - instr_addr : out unsigned (IMEM_ADDR_WIDTH-1 downto 0); - xmem_din : in unsigned (DMEM_DATA_WIDTH-1 downto 0); - xmem_dout : out unsigned (DMEM_DATA_WIDTH-1 downto 0); - xmem_addr : out unsigned (DMEM_ADDR_WIDTH-1 downto 0); - io_sel : out std_logic - ); -end cpu; - -architecture rtl of cpu is - - COMPONENT stack_ctrl - GENERIC ( - addr_width : integer - ); - Port ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - push : in STD_LOGIC; - pop : in STD_LOGIC; - din : in inst_addr_t; - dout : out inst_addr_t; - mem_we : out STD_LOGIC; - ptr_out : out unsigned (addr_width-1 downto 0) - ); - END COMPONENT; - - COMPONENT pc - Port ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - inc : in STD_LOGIC; - load : in STD_LOGIC; - pc_in : in inst_addr_t; - pc_out : out inst_addr_t; - pc_next : out inst_addr_t - ); - END COMPONENT; - - COMPONENT dpath_ctrl - GENERIC ( - use_rom : boolean - ); - Port ( - inst_in : in inst_t; - iphase_in : in iphase_t; - status_in : in cpu_status_t; - ctrl_out : out dpath_ctrl_out_t; - idout : out inst_addr_t; - ddout : out dmem_data_t - ); - END COMPONENT; - - COMPONENT int_ctrl - Port ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - ctrl_in : in int_ctrl_in_t; - int_in : in STD_LOGIC; - int_exit : in STD_LOGIC; - iphase_in : in iphase_t; - int_ack_out : out STD_LOGIC; - stat_save_out : out STD_LOGIC; - stat_rest_out : out STD_LOGIC; - pc_addr_out : out inst_addr_t; - pc_load_out : out STD_LOGIC; - stk_push_out : out STD_LOGIC; - stk_pop_out : out STD_LOGIC - ); - END COMPONENT; - - COMPONENT reg_dual - GENERIC ( - addr_width : integer; - data_width : integer - ); - Port ( - clk : in STD_LOGIC; - we_a : in STD_LOGIC; - ptr_a : in reg_ptr_t; - ptr_b : in reg_ptr_t; - din_a : in unsigned (data_width-1 downto 0); - dout_a : out unsigned (data_width-1 downto 0); - dout_b : out unsigned (data_width-1 downto 0) - ); - END COMPONENT; - - COMPONENT chipram - GENERIC ( - addr_width : integer; - data_width : integer - ); - Port ( - clka : in STD_LOGIC; - clkb : in STD_LOGIC; - en_a : in STD_LOGIC; - en_b : in STD_LOGIC; - we_a : in STD_LOGIC; - we_b : in STD_LOGIC; - addr_a : in unsigned (addr_width-1 downto 0); - addr_b : in unsigned (addr_width-1 downto 0); - din_a : in unsigned (data_width-1 downto 0); - din_b : in unsigned (data_width-1 downto 0); - dout_a : out unsigned (data_width-1 downto 0); - dout_b : out unsigned (data_width-1 downto 0) - ); - END COMPONENT; - - COMPONENT chipreg - Port ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - we : in STD_LOGIC; - addr : in dmem_addr_t; - din : in dmem_data_t; - dout : out dmem_data_t; - ctrl_in : in creg_ctrl_in_t; - ctrl_out : out creg_ctrl_out_t - ); - END COMPONENT; - - COMPONENT alu - GENERIC ( - data_width : integer := 8 - ); - Port ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - op_en : in STD_LOGIC; - cy_in : in STD_LOGIC; - op1_in : in unsigned (data_width-1 downto 0); - op2_in : in unsigned (data_width-1 downto 0); - opsel : in alu_op_t; - res_out : out unsigned (data_width-1 downto 0); - stat_load : in STD_LOGIC; - stat_in : in alu_status_t; - stat_out : out alu_status_t - ); - END COMPONENT; - - signal cpu_status, status_reg : cpu_status_t; -- := cpu_status_t(others => '0'); - signal ctrl : dpath_ctrl_out_t; - signal stk_out : inst_addr_t; - signal stk_in : inst_addr_t; - signal stk_reg : inst_addr_t; - signal pc_in, pc_out, pc_next, idata, int_pc_addr : inst_addr_t; - signal iphase : iphase_t; - signal const_data, reg_a_dout, reg_b_dout : dmem_data_t; - signal reg_din : dmem_data_t; - signal alu_op1, alu_op2, alu_result : dmem_data_t; - signal alu_status : alu_status_t; - signal pc_inc, pc_load, cpu_active, stk_we, cmem_we, creg_we : STD_LOGIC; - signal ctrl_inst : inst_t; - signal ctrl_iphase : iphase_t; - signal was_pcld, was_pop2pc, int_pc_load, int_stk_push, int_stk_pop, stk_push, stk_pop : STD_LOGIC; - signal status_save, status_restore : STD_LOGIC; - signal creg_dout : dmem_data_t; - signal cmem_din, cmem_dout : inst_addr_t; - signal stk_addr, cmem_addr : unsigned(CHIPRAM_SIZE_BITS-1 downto 0); - signal stk_ptr : unsigned(STACK_SIZE_BITS-1 downto 0); - signal creg_ctrl_out : creg_ctrl_out_t; - signal creg_ctrl_in : creg_ctrl_in_t; - signal xio_sel, cio_sel : std_logic; - signal mem_data : dmem_data_t; - signal mem_addr : dmem_data_t; - -begin - io_sel <= xio_sel; - instr_addr <= pc_out; - pc_inc <= cpu_active and ctrl.lines.pc_inc; - stk_addr <= '0' & stk_ptr; - cpu_status.alu <= alu_status; - creg_ctrl_in.alu <= alu_status; - - xmem_dout <= mem_data; - xmem_addr <= mem_addr; - cmem_din <= creg_ctrl_out.cmem_high & mem_data; - cmem_addr <= '1' & creg_ctrl_out.bank_sel & mem_addr(MIN(cmem_addr'length-creg_ctrl_out.bank_sel'length-1, mem_addr'length)-1 downto 0); - --------------------------------------------------------------------- -mem_ctrl_lines: - process(ctrl.lines) - begin - xio_sel <= '0'; - xmem_re <= '0'; - xmem_we <= '0'; - cio_sel <= '0'; - cmem_we <= '0'; - creg_we <= '0'; - - case ctrl.lines.mem_access is - when xmem_access => - xmem_re <= ctrl.lines.mem_read; - xmem_we <= ctrl.lines.mem_write; - when xio_access => - xio_sel <= '1'; - xmem_re <= ctrl.lines.mem_read; - xmem_we <= ctrl.lines.mem_write; - when cmem_access => - cmem_we <= ctrl.lines.mem_write; - when cio_access => - cio_sel <= '1'; - creg_we <= ctrl.lines.mem_write; - when others => null; - end case; - end process; - -iphase_counter: - process(rst, clk, ce) - variable pos : integer; - begin - if rst = '1' then - iphase <= iphase_t'low; - cpu_active <= '0'; - elsif rising_edge(clk) then - cpu_active <= '0'; - if ce = '1' then - cpu_active <= '1'; - if iphase = iphase_t'high then - iphase <= iphase_t'low; - else - iphase <= iphase + 1; - end if; - end if; - end if; - end process; - -gen_instr_reg: -if use_instr_register = true generate - -instr_reg: - process (rst, clk, ce) - begin - if rst = '1' then - ctrl_inst <= (others => '0'); - ctrl_iphase <= 0; - elsif rising_edge(clk) and ce = '1' then - ctrl_inst <= instr_din; - ctrl_iphase <= iphase; - end if; - end process; - -end generate; - -gen_instr_direct: -if use_instr_register = false generate - - ctrl_inst <= instr_din; - ctrl_iphase <= iphase; - -end generate; - -status_register: - process(clk, status_save) - begin - if rising_edge(clk) and status_save = '1' then - status_reg.alu <= alu_status; - end if; - end process; - -pc_pushpop: - process(ctrl.lines, int_pc_load, int_stk_push, int_stk_pop, was_pop2pc) - begin - pc_load <= ctrl.lines.pc_load or int_pc_load; - stk_push <= ctrl.lines.stk_push or (int_stk_push and not was_pop2pc); - stk_pop <= (ctrl.lines.stk_pop and not ctrl.lines.pc_load) or int_stk_pop or ((ctrl.lines.stk_pop and ctrl.lines.pc_load) and not int_pc_load); - end process; - -lines_delay: - process(clk) - begin - if rising_edge(clk) then - was_pcld <= ctrl.lines.pc_load; - was_pop2pc <= ctrl.lines.stk_pop and ctrl.lines.pc_load; - end if; - end process; - -stk_mux: - process(ctrl.lines, was_pcld, int_stk_push, pc_next, idata, reg_a_dout, creg_ctrl_out) - begin - if was_pcld = '1' and int_stk_push = '1' then - stk_in <= idata; - elsif ctrl.lines.stk_push = '1' and ctrl.lines.pc_load = '0' then - stk_in <= creg_ctrl_out.stk_high & reg_a_dout; - else - stk_in <= pc_next; - end if; - - end process; - -pc_mux: - process(ctrl.lines, int_pc_load, int_stk_pop, idata, int_pc_addr, stk_out) - begin - - pc_in <= stk_out; - if int_pc_load = '1' then - if int_stk_pop = '0' then - pc_in <= int_pc_addr; - end if; - elsif ctrl.lines.pc_load = '1' then - if ctrl.lines.stk_pop = '0' then - pc_in <= idata; - end if; - end if; - - end process; - -mem_data_mux: - process(ctrl.lines.ddata_src_sel, reg_a_dout, reg_b_dout, const_data, creg_ctrl_out) - begin - case ctrl.lines.ddata_src_sel is - when reg_a => - mem_data <= reg_a_dout; - when reg_b => - mem_data <= reg_b_dout; - when const => - mem_data <= const_data; - when others => - mem_data <= const_data; - end case; - - end process; - -mem_addr_mux: - process(ctrl.lines.daddr_src_sel, reg_a_dout, reg_b_dout, const_data, creg_ctrl_out.bank_sel) - begin - case ctrl.lines.daddr_src_sel is - when reg_a => - mem_addr <= reg_a_dout; - when reg_b => - mem_addr <= reg_b_dout; - when const => - mem_addr <= const_data; - when others => - mem_addr <= const_data; - end case; - - end process; - -reg_in_mux: - process(ctrl.lines.reg_src_sel, cio_sel, xmem_din, alu_result, stk_out, cmem_dout, creg_dout) - variable data : dmem_data_t; - begin - case ctrl.lines.reg_src_sel is - when xmem_src => - data := xmem_din; - when cmem_src => - if cio_sel = '0' then - data := cmem_dout(dmem_data_t'range); - else - data := creg_dout(dmem_data_t'range); - end if; - when stk_src => - data := stk_out(dmem_data_t'range); - when others => - data := alu_result; - end case; - - reg_din <= data; - - end process; - -alu_op1_mux: - process(ctrl.lines.alu_op1_src_sel, reg_a_dout, reg_b_dout, const_data) - variable data : dmem_data_t; - begin - case ctrl.lines.alu_op1_src_sel is - when reg_a => - data := reg_a_dout; - when reg_b => - data := reg_b_dout; - when others => - data := const_data; - end case; - - alu_op1 <= data; - - end process; - -alu_op2_mux: - process(ctrl.lines.alu_op2_src_sel, reg_a_dout, reg_b_dout, const_data) - variable data : dmem_data_t; - begin - case ctrl.lines.alu_op2_src_sel is - when reg_a => - data := reg_a_dout; - when reg_b => - data := reg_b_dout; - when others => - data := const_data; - end case; - - alu_op2 <= data; - - end process; - --------------------------------------------------------------------- - inst_stack_ctrl: stack_ctrl - GENERIC MAP ( - addr_width => STACK_SIZE_BITS - ) - PORT MAP( - rst => rst, - clk => clk, - push => stk_push, - pop => stk_pop, - dout => stk_reg, - din => stk_in, - ptr_out => stk_ptr, - mem_we => stk_we - ); - - inst_pc: pc - PORT MAP( - rst => rst, - clk => clk, - inc => pc_inc, - load => pc_load, - pc_in => pc_in, - pc_out => pc_out, - pc_next => pc_next - ); - - inst_dpath_ctrl: dpath_ctrl - GENERIC MAP ( - use_rom => use_ctrl_rom - ) - PORT MAP( - inst_in => ctrl_inst, - iphase_in => ctrl_iphase, - status_in => cpu_status, - ctrl_out => ctrl, - ddout => const_data, - idout => idata - ); - - inst_int_ctrl: int_ctrl - PORT MAP( - rst => rst, - clk => clk, - ctrl_in => creg_ctrl_out.int_ctrl, - int_in => int_in, - int_ack_out => int_ack, - int_exit => ctrl.lines.int_exit, - iphase_in => ctrl_iphase, - stat_save_out => status_save, - stat_rest_out => status_restore, - pc_addr_out => int_pc_addr, - pc_load_out => int_pc_load, - stk_push_out => int_stk_push, - stk_pop_out => int_stk_pop - - ); - - inst_reg_ab: reg_dual - GENERIC MAP ( - addr_width => REG_SIZE_BITS, - data_width => DMEM_DATA_WIDTH - ) - PORT MAP( - clk => clk, - we_a => ctrl.lines.reg_we, - ptr_a => ctrl.reg_a_ptr, - ptr_b => ctrl.reg_b_ptr, - din_a => reg_din, - dout_a => reg_a_dout, - dout_b => reg_b_dout - ); - - inst_chipram: chipram - GENERIC MAP ( - addr_width => CHIPRAM_SIZE_BITS, - data_width => IMEM_ADDR_WIDTH - ) - PORT MAP( - clka => clk, - clkb => clk, - en_a => cpu_active, - en_b => cpu_active, - we_a => stk_we, - we_b => cmem_we, - addr_a => stk_addr, - addr_b => cmem_addr, - din_a => stk_reg, - din_b => cmem_din, - dout_a => stk_out, - dout_b => cmem_dout - ); - - inst_chipreg: chipreg - PORT MAP( - rst => rst, - clk => clk, - we => creg_we, - addr => mem_addr, - din => mem_data, - dout => creg_dout, - ctrl_in => creg_ctrl_in, - ctrl_out => creg_ctrl_out - ); - - inst_alu: alu - GENERIC MAP ( - data_width => DMEM_DATA_WIDTH - ) - PORT MAP( - rst => rst, - clk => clk, - op_en => ctrl.lines.alu_load, - cy_in => ctrl.lines.alu_cy_in, - op1_in => alu_op1, - op2_in => alu_op2, - opsel => ctrl.lines.alu_opsel, - res_out => alu_result, - stat_load => status_restore, - stat_in => status_reg.alu, - stat_out => alu_status - ); - -end rtl; diff --git a/lib/CPUs/JCpu/src/core/cpu_pkg.vhd b/lib/CPUs/JCpu/src/core/cpu_pkg.vhd deleted file mode 100644 index 91bdae2..0000000 --- a/lib/CPUs/JCpu/src/core/cpu_pkg.vhd +++ /dev/null @@ -1,852 +0,0 @@ --------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: Types, constants and functions for JCPU --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - - -package cpu_pkg is - - -- Revision of the CPU - constant REVISION : integer := 4; - - -- Chipram depth (valid values 9..floor(log2(BlockRamBytes))) - constant CHIPRAM_SIZE_BITS : integer := 10; - - -- Number of registers (16 registers fixed) - constant REG_SIZE_BITS : integer := 4; - - -- Instruction memory - constant IMEM_ADDR_WIDTH : integer := 12; - - -- Data memory - constant DMEM_DATA_WIDTH : integer := 8; - constant DMEM_ADDR_WIDTH : integer := 8; - - -- Instruction format - constant INST_OPCODE_WIDTH : integer := 6; - constant IMEM_DATA_WIDTH : integer := INST_OPCODE_WIDTH + DMEM_DATA_WIDTH + REG_SIZE_BITS; - - -- Microcode ROM - constant MUCODE_ADDR_WIDTH : integer := 9; - - -- Stack depth (uses lower half of CHIPRAM) - constant STACK_SIZE_BITS : integer := CHIPRAM_SIZE_BITS-1; - - --Types - subtype iphase_t is integer range 0 to 1; - type mem_access_t is (cmem_access, xmem_access, cio_access, xio_access); - type reg_src_t is (alu_src, stk_src, cmem_src, xmem_src); - type alu_src_t is (reg_a, reg_b, const); - type ddata_src_t is (reg_a, reg_b, const); - type daddr_src_t is (reg_a, reg_b, const); - subtype instr_name_t is string(1 to 12); - type instr_name_array_t is array (0 to 63) of instr_name_t; - subtype opcode_t is unsigned (INST_OPCODE_WIDTH-1 downto 0); - subtype inst_data_t is unsigned (IMEM_ADDR_WIDTH-1 downto 0); - subtype inst_addr_t is unsigned (IMEM_ADDR_WIDTH-1 downto 0); - subtype inst_t is unsigned (IMEM_DATA_WIDTH-1 downto 0); - subtype dmem_data_t is unsigned (DMEM_DATA_WIDTH-1 downto 0); - subtype dmem_addr_t is unsigned (DMEM_DATA_WIDTH-1 downto 0); - subtype reg_ptr_t is unsigned (3 downto 0); - type dmem_array_t is array (natural range <>) of dmem_data_t; - type instr_addr_array is array (integer range <>) of inst_addr_t; - subtype bank_sel_t is unsigned (CHIPRAM_SIZE_BITS-DMEM_DATA_WIDTH-2 downto 0); - - type alu_op_t is - ( - pass_op2, - op1_add_op2, - op1_sub_op2, - op1_addc_op2, - op1_subc_op2, - op1_and_op2, - op1_or_op2, - op1_xor_op2, - swap_op, - shl_op, - shr_op, - rol_op, - ror_op, - rolc_op, - rorc_op - ); - - type alu_status_t is record - zero : STD_LOGIC; - carry : STD_LOGIC; - end record; - - type cpu_status_t is record - alu : alu_status_t; - end record; - - type ctrl_lines_t is record - reg_we : STD_LOGIC; - reg_src_sel : reg_src_t; - alu_op1_src_sel : alu_src_t; - alu_op2_src_sel : alu_src_t; - alu_opsel : alu_op_t; - alu_load : STD_LOGIC; - alu_cy_in : STD_LOGIC; - ddata_src_sel : ddata_src_t; - daddr_src_sel : daddr_src_t; - pc_load : STD_LOGIC; - pc_inc : STD_LOGIC; - stk_push : STD_LOGIC; - stk_pop : STD_LOGIC; - mem_access : mem_access_t; - mem_read : STD_LOGIC; - mem_write : STD_LOGIC; - int_exit : STD_LOGIC; - end record; - - type dpath_ctrl_out_t is record - lines : ctrl_lines_t; - reg_a_ptr : reg_ptr_t; - reg_b_ptr : reg_ptr_t; - end record; - - type int_ctrl_in_t is record - enable : std_logic; - end record; - - type creg_ctrl_out_t is record - bank_sel : bank_sel_t; - int_ctrl : int_ctrl_in_t; - stk_high : unsigned(IMEM_ADDR_WIDTH-DMEM_ADDR_WIDTH-1 downto 0); - cmem_high : unsigned(IMEM_ADDR_WIDTH-DMEM_ADDR_WIDTH-1 downto 0); - end record; - - type creg_ctrl_in_t is record - alu : alu_status_t; - end record; - - - type murom_t is array (0 to integer(2**MUCODE_ADDR_WIDTH)-1) of ctrl_lines_t; - - constant instr_name_array : instr_name_array_t := - ( - "NOP ", -- 00 - "HALT ", -- 01 - "MOV|R|R ", -- 02 - "MOV|R|K ", -- 03 - "MOVX|R|Ri ", -- 04 - "MOVX|R|Ki ", -- 05 - "MOVX|Ri|R ", -- 06 - "MOVX|Ri|K ", -- 07 - "MOVX|Ki|R ", -- 08 - "MOVC|R|Ri ", -- 09 - "MOVC|R|Ki ", -- 0A - "MOVC|Ri|R ", -- 0B - "MOVC|Ri|K ", -- 0C - "MOVC|Ki|R ", -- 0D - "CMP|R|R ", -- 0E - "CMP|R|K ", -- 0F - "ADD|R|R ", -- 10 - "ADD|R|K ", -- 11 - "ADDC|R|R ", -- 12 - "ADDC|R|K ", -- 13 - "SUB|R|R ", -- 14 - "SUB|R|K ", -- 15 - "SUBC|R|R ", -- 16 - "SUBC|R|K ", -- 17 - "AND|R|R ", -- 18 - "AND|R|K ", -- 19 - "OR|R|R ", -- 1A - "OR|R|K ", -- 1B - "XOR|R|R ", -- 1C - "XOR|R|K ", -- 1D - "SHL|R ", -- 1E - "SHR|R ", -- 1F - "ROL|R ", -- 20 - "ROR|R ", -- 21 - "ROLC|R ", -- 22 - "RORC|R ", -- 23 - "XOUT|Ki|R ", -- 24 - "XOUT|Ri|K ", -- 25 - "COUT|Ki|R ", -- 26 - "COUT|Ri|K ", -- 27 - "XIN|R|Ki ", -- 28 - "CIN|R|Ki ", -- 29 - "SWAP|R ", -- 2A - "SETC ", -- 2B - "UNDEF ", -- 2C - "UNDEF ", -- 2D - "SUB|K|R ", -- 2E - "SUBC|K|R ", -- 2F - "JMP|K ", -- 30 - "JZ|K ", -- 31 - "JNZ|K ", -- 32 - "JC|K ", -- 33 - "JNC|K ", -- 34 - "JLT|K ", -- 35 - "JGT|K ", -- 36 - "JLE|K ", -- 37 - "JGE|K ", -- 38 - "JEQ|K ", -- 39 - "JNE|K ", -- 3A - "CALL|K ", -- 3B - "PUSH|R ", -- 3C - "POP|R ", -- 3D - "RET ", -- 3E - "RETI " -- 3F - ); - -- Functions - function Instr(opcode : opcode_t) return inst_t; - function Instr(opcode : opcode_t; data : inst_data_t) return inst_t; - function Instr(opcode : opcode_t; data : inst_data_t; reg : integer) return inst_t; - function Instr(opcode : opcode_t; reg_a : integer) return inst_t; - function Instr(opcode : opcode_t; reg_a, reg_b : integer) return inst_t; - function Instr(opcode : opcode_t; reg_a, reg_b, reg_c : integer) return inst_t; - function ctrl_lines_default return ctrl_lines_t; - function idecoder(instr_name : instr_name_t; iphase : iphase_t; status : cpu_status_t) return ctrl_lines_t; - function idecoder(opcode : opcode_t; iphase : iphase_t; status : cpu_status_t) return ctrl_lines_t; - function gen_murom return murom_t; - function get_muromaddr (opcode : opcode_t; iphase : iphase_t; status : cpu_status_t) return unsigned; - function MIN (X, Y: INTEGER) return INTEGER; - function MAX (X, Y: INTEGER) return INTEGER; - -end cpu_pkg; - -package body cpu_pkg is - - function Instr(opcode : opcode_t) return inst_t is - variable inst : inst_t := (others => '0'); - begin - inst(inst_t'length-1 downto inst_t'length-opcode_t'length) := opcode; - return inst; - - end Instr; - - function Instr(opcode : opcode_t; data : inst_data_t) return inst_t is - variable inst : inst_t := (others => '0'); - begin - inst(inst_t'length-1 downto inst_t'length-opcode_t'length) := opcode; - inst(inst_t'length-opcode_t'length-1 downto inst_t'length-opcode_t'length-inst_addr_t'length) := data; - return inst; - - end Instr; - - function Instr(opcode : opcode_t; data : inst_data_t; reg : integer) return inst_t is - variable inst : inst_t := (others => '0'); - begin - inst(inst_t'length-1 downto inst_t'length-opcode_t'length) := opcode; - inst(inst_t'length-opcode_t'length-1 downto inst_t'length-opcode_t'length-inst_data_t'length) := data; - inst(reg_ptr_t'length-1 downto 0) := reg_ptr_t(to_unsigned(reg, reg_ptr_t'length)); - - return inst; - - end Instr; - - function Instr(opcode : opcode_t; reg_a : integer) return inst_t is - variable inst : inst_t := (others => '0'); - begin - inst(inst_t'length-1 downto inst_t'length-opcode_t'length) := opcode; - inst(reg_ptr_t'length-1 downto 0) := reg_ptr_t(to_unsigned(reg_a, reg_ptr_t'length)); - - return inst; - - end Instr; - - function Instr(opcode : opcode_t; reg_a, reg_b : integer) return inst_t is - variable inst : inst_t := (others => '0'); - begin - inst(inst_t'length-1 downto inst_t'length-opcode_t'length) := opcode; - inst(2*(reg_ptr_t'length)-1 downto reg_ptr_t'length) := reg_ptr_t(to_unsigned(reg_b, reg_ptr_t'length)); - inst(reg_ptr_t'length-1 downto 0) := reg_ptr_t(to_unsigned(reg_a, reg_ptr_t'length)); - - return inst; - - end Instr; - - function Instr(opcode : opcode_t; reg_a, reg_b, reg_c : integer) return inst_t is - variable inst : inst_t := (others => '0'); - begin - inst(inst_t'length-1 downto inst_t'length-opcode_t'length) := opcode; - inst(3*(reg_ptr_t'length)-1 downto 2*reg_ptr_t'length) := reg_ptr_t(to_unsigned(reg_c, reg_ptr_t'length)); - inst(2*(reg_ptr_t'length)-1 downto reg_ptr_t'length) := reg_ptr_t(to_unsigned(reg_b, reg_ptr_t'length)); - inst(reg_ptr_t'length-1 downto 0) := reg_ptr_t(to_unsigned(reg_a, reg_ptr_t'length)); - - return inst; - - end Instr; - - function ctrl_lines_default return ctrl_lines_t is - variable result : ctrl_lines_t; - begin - result.pc_load := '0'; - result.pc_inc := '0'; - result.stk_push := '0'; - result.stk_pop := '0'; - result.reg_we := '0'; - result.reg_src_sel := alu_src; - result.ddata_src_sel := reg_a; - result.daddr_src_sel := reg_b; - result.alu_opsel := pass_op2; - result.alu_op1_src_sel := reg_a; - result.alu_op2_src_sel := reg_b; - result.alu_load := '0'; - result.alu_cy_in := '0'; - result.mem_access := cmem_access; - result.mem_read := '0'; - result.mem_write := '0'; - result.int_exit := '0'; - return result; - - end ctrl_lines_default; - - function idecoder(opcode : opcode_t; iphase : iphase_t; status : cpu_status_t) return ctrl_lines_t is - variable instr_name : instr_name_t; - begin - instr_name := instr_name_array(to_integer(opcode)); - return idecoder(instr_name, iphase, status); - end idecoder; - - function idecoder(instr_name : instr_name_t; iphase : iphase_t; status : cpu_status_t) return ctrl_lines_t is - variable result : ctrl_lines_t; - variable ze, cy : STD_LOGIC; - - begin - ze := status.alu.zero; - cy := status.alu.carry; - - result := ctrl_lines_default; - if iphase = 0 then - result.pc_inc := '1'; - end if; - - case instr_name is - - when "HALT " => - result.pc_inc := '0'; - when "SETC " => -- carry <= 1 - result.reg_src_sel := alu_src; - result.alu_opsel := pass_op2; - result.alu_op2_src_sel := reg_b; - result.alu_load := '1'; - result.alu_cy_in := '1'; - when "MOV|R|R " => -- R(a) <= R(b) - result.reg_src_sel := alu_src; - result.alu_opsel := pass_op2; - result.alu_op2_src_sel := reg_b; - result.alu_load := '1'; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "MOV|R|K " => -- R(a) <= #kk - result.reg_src_sel := alu_src; - result.alu_opsel := pass_op2; - result.alu_op2_src_sel := const; - result.alu_load := '1'; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "MOVC|Ri|R " => -- [R(b)] <= R(a) - result.mem_access := cmem_access; - result.daddr_src_sel := reg_b; - result.ddata_src_sel := reg_a; - if iphase = 0 then - result.mem_write := '1'; - end if; - when "MOVC|Ri|K " => -- [R(a)] <= kk - result.mem_access := cmem_access; - result.daddr_src_sel := reg_a; - result.ddata_src_sel := const; - if iphase = 0 then - result.mem_write := '1'; - end if; - when "COUT|Ri|K " => -- [R(a)] <= kk - result.mem_access := cio_access; - result.daddr_src_sel := reg_a; - result.ddata_src_sel := const; - if iphase = 0 then - result.mem_write := '1'; - end if; - when "MOVC|R|Ri " => -- R(a) <= [R(b)] - result.mem_access := cmem_access; - result.reg_src_sel := cmem_src; - result.daddr_src_sel := reg_b; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "MOVC|R|Ki " => -- R(a) <= [#addr] - result.mem_access := cmem_access; - result.reg_src_sel := cmem_src; - result.daddr_src_sel := const; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "CIN|R|Ki " => -- R(a) <= [#addr] - result.mem_access := cio_access; - result.reg_src_sel := cmem_src; - result.daddr_src_sel := const; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "MOVC|Ki|R " => -- [#addr] <= R(a) - result.mem_access := cmem_access; - result.daddr_src_sel := const; - result.ddata_src_sel := reg_a; - if iphase = 0 then - result.mem_write := '1'; - end if; - when "COUT|Ki|R " => -- [#addr] <= R(a) - result.mem_access := cio_access; - result.daddr_src_sel := const; - result.ddata_src_sel := reg_a; - if iphase = 0 then - result.mem_write := '1'; - end if; - when "MOVX|Ri|R " => -- [R(b)] <= R(a) - result.mem_access := xmem_access; - result.daddr_src_sel := reg_b; - result.ddata_src_sel := reg_a; - if iphase = 0 then - result.mem_write := '1'; - end if; - when "MOVX|Ri|K " => -- [R(a)] <= kk - result.mem_access := xmem_access; - result.daddr_src_sel := reg_a; - result.ddata_src_sel := const; - if iphase = 0 then - result.mem_write := '1'; - end if; - when "XOUT|Ri|K " => -- [R(a)] <= kk - result.mem_access := xio_access; - result.daddr_src_sel := reg_a; - result.ddata_src_sel := const; - if iphase = 0 then - result.mem_write := '1'; - end if; - when "MOVX|R|Ri " => -- R(a) <= [R(b)] - result.mem_access := xmem_access; - result.reg_src_sel := xmem_src; - result.daddr_src_sel := reg_b; - if iphase = 0 then - result.mem_read := '1'; - elsif iphase = 1 then - result.reg_we := '1'; - end if; - when "MOVX|R|Ki " => -- R(a) <= [#addr] - result.mem_access := xmem_access; - result.reg_src_sel := xmem_src; - result.daddr_src_sel := const; - if iphase = 0 then - result.mem_read := '1'; - elsif iphase = 1 then - result.reg_we := '1'; - end if; - when "XIN|R|Ki " => -- R(a) <= [#addr] - result.mem_access := xio_access; - result.reg_src_sel := xmem_src; - result.daddr_src_sel := const; - if iphase = 0 then - result.mem_read := '1'; - elsif iphase = 1 then - result.reg_we := '1'; - end if; - when "MOVX|Ki|R " => -- [#addr] <= R(a) - result.mem_access := xmem_access; - result.daddr_src_sel := const; - result.ddata_src_sel := reg_a; - if iphase = 0 then - result.mem_write := '1'; - end if; - when "XOUT|Ki|R " => -- [#addr] <= R(a) - result.mem_access := xio_access; - result.daddr_src_sel := const; - result.ddata_src_sel := reg_a; - if iphase = 0 then - result.mem_write := '1'; - end if; - when "ADD|R|R " => -- R(a) <= R(a) + R(b) - result.alu_opsel := op1_add_op2; - result.alu_op1_src_sel := reg_a; - result.alu_op2_src_sel := reg_b; - result.reg_src_sel := alu_src; - result.alu_load := '1'; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "ADD|R|K " => -- R(a) <= R(a) + k - result.alu_opsel := op1_add_op2; - result.alu_op1_src_sel := reg_a; - result.alu_op2_src_sel := const; - result.reg_src_sel := alu_src; - result.alu_load := '1'; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "ADDC|R|R " => -- R(a) <= R(a) + R(b) - result.alu_opsel := op1_addc_op2; - result.alu_op1_src_sel := reg_a; - result.alu_op2_src_sel := reg_b; - result.reg_src_sel := alu_src; - result.alu_load := '1'; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "ADDC|R|K " => -- R(a) <= R(a) + k - result.alu_opsel := op1_addc_op2; - result.alu_op1_src_sel := reg_a; - result.alu_op2_src_sel := const; - result.reg_src_sel := alu_src; - result.alu_load := '1'; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "SUB|R|R " => -- R(a) <= R(a) + R(b) - result.alu_opsel := op1_sub_op2; - result.alu_op1_src_sel := reg_a; - result.alu_op2_src_sel := reg_b; - result.reg_src_sel := alu_src; - result.alu_load := '1'; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "SUB|R|K " => -- R(a) <= R(a) + k - result.alu_opsel := op1_sub_op2; - result.alu_op1_src_sel := reg_a; - result.alu_op2_src_sel := const; - result.reg_src_sel := alu_src; - result.alu_load := '1'; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "SUB|K|R " => -- R(a) <= k - R(a) - result.alu_opsel := op1_sub_op2; - result.alu_op1_src_sel := const; - result.alu_op2_src_sel := reg_a; - result.reg_src_sel := alu_src; - result.alu_load := '1'; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "SUBC|R|R " => -- R(a) <= R(a) + R(b) - result.alu_opsel := op1_subc_op2; - result.alu_op1_src_sel := reg_a; - result.alu_op2_src_sel := reg_b; - result.reg_src_sel := alu_src; - result.alu_load := '1'; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "SUBC|R|K " => -- R(a) <= R(a) + k - result.alu_opsel := op1_subc_op2; - result.alu_op1_src_sel := reg_a; - result.alu_op2_src_sel := const; - result.reg_src_sel := alu_src; - result.alu_load := '1'; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "SUBC|K|R " => -- R(a) <= K - R(a) - result.alu_opsel := op1_subc_op2; - result.alu_op1_src_sel := const; - result.alu_op2_src_sel := reg_a; - result.reg_src_sel := alu_src; - result.alu_load := '1'; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "AND|R|R " => -- R(a) <= R(a) and R(b) - result.alu_opsel := op1_and_op2; - result.alu_op1_src_sel := reg_a; - result.alu_op2_src_sel := reg_b; - result.reg_src_sel := alu_src; - result.alu_load := '1'; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "AND|R|K " => -- R(a) <= R(a) and k - result.alu_opsel := op1_and_op2; - result.alu_op1_src_sel := reg_a; - result.alu_op2_src_sel := const; - result.reg_src_sel := alu_src; - result.alu_load := '1'; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "OR|R|R " => -- R(a) <= R(a) or R(b) - result.alu_opsel := op1_or_op2; - result.alu_op1_src_sel := reg_a; - result.alu_op2_src_sel := reg_b; - result.reg_src_sel := alu_src; - result.alu_load := '1'; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "OR|R|K " => -- R(a) <= R(a) or R(b) - result.alu_opsel := op1_or_op2; - result.alu_op1_src_sel := reg_a; - result.alu_op2_src_sel := const; - result.reg_src_sel := alu_src; - result.alu_load := '1'; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "XOR|R|R " => -- R(a) <= R(a) xor R(b) - result.alu_opsel := op1_xor_op2; - result.alu_op1_src_sel := reg_a; - result.alu_op2_src_sel := reg_b; - result.reg_src_sel := alu_src; - result.alu_load := '1'; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "XOR|R|K " => -- R(a) <= R(a) xor R(b) - result.alu_opsel := op1_xor_op2; - result.alu_op1_src_sel := reg_a; - result.alu_op2_src_sel := const; - result.reg_src_sel := alu_src; - result.alu_load := '1'; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "SWAP|R " => -- R(a) <= R(b) - result.reg_src_sel := alu_src; - result.alu_opsel := swap_op; - result.alu_op1_src_sel := reg_a; - result.alu_load := '1'; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "SHL|R " => -- R(a) <= R(a) xor R(b) - result.reg_src_sel := alu_src; - result.alu_opsel := shl_op; - result.alu_op1_src_sel := reg_a; - result.alu_load := '1'; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "SHR|R " => -- R(a) <= R(a) xor R(b) - result.reg_src_sel := alu_src; - result.alu_opsel := shr_op; - result.alu_op1_src_sel := reg_a; - result.alu_load := '1'; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "ROL|R " => -- R(a) <= R(a) xor R(b) - result.reg_src_sel := alu_src; - result.alu_opsel := rol_op; - result.alu_op1_src_sel := reg_a; - result.alu_load := '1'; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "ROR|R " => -- R(a) <= R(a) xor R(b) - result.reg_src_sel := alu_src; - result.alu_opsel := ror_op; - result.alu_op1_src_sel := reg_a; - result.alu_load := '1'; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "ROLC|R " => -- R(a) <= R(a) xor R(b) - result.reg_src_sel := alu_src; - result.alu_opsel := rolc_op; - result.alu_op1_src_sel := reg_a; - result.alu_load := '1'; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "RORC|R " => -- R(a) <= R(a) xor R(b) - result.reg_src_sel := alu_src; - result.alu_opsel := rorc_op; - result.alu_op1_src_sel := reg_a; - result.alu_load := '1'; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "CMP|R|R " => -- - result.alu_opsel := op1_sub_op2; - result.alu_op1_src_sel := reg_a; - result.alu_op2_src_sel := reg_b; - result.alu_load := '1'; - when "CMP|R|K " => -- - result.alu_opsel := op1_sub_op2; - result.alu_op1_src_sel := reg_a; - result.alu_op2_src_sel := const; - result.alu_load := '1'; - when "JMP|K " => -- PC <= #addr - if iphase = 0 then - result.pc_load := '1'; - end if; - when "JZ|K " => -- PC <= #addr, zero - if iphase = 0 then - if ze = '1' then - result.pc_load := '1'; - end if; - end if; - when "JNZ|K " => -- PC <= #addr, !zero - if iphase = 0 then - if ze = '0' then - result.pc_load := '1'; - end if; - end if; - when "JC|K " => -- PC <= #addr, carry - if iphase = 0 then - if cy = '1' then - result.pc_load := '1'; - end if; - end if; - when "JNC|K " => -- PC <= #addr, !carry - if iphase = 0 then - if cy = '0' then - result.pc_load := '1'; - end if; - end if; - when "JLT|K " => -- PC <= #addr, !carry - if iphase = 0 then - if cy = '1' then - result.pc_load := '1'; - end if; - end if; - when "JGT|K " => -- - if iphase = 0 then - if (cy or ze) = '0' then - result.pc_load := '1'; - end if; - end if; - when "JLE|K " => -- - if iphase = 0 then - if (cy xor ze) = '1' then - result.pc_load := '1'; - end if; - end if; - when "JGE|K " => -- - if iphase = 0 then - if (not cy or ze) = '1' then - result.pc_load := '1'; - end if; - end if; - when "JEQ|K " => -- - if iphase = 0 then - if ze = '1' then - result.pc_load := '1'; - end if; - end if; - when "JNE|K " => -- - if iphase = 0 then - if ze = '0' then - result.pc_load := '1'; - end if; - end if; - when "PUSH|R " => -- push - if iphase = 0 then - result.stk_push := '1'; - end if; - when "POP|R " => -- pop - result.reg_src_sel := stk_src; - if iphase = 0 then - result.stk_pop := '1'; - elsif iphase = 1 then - result.reg_we := '1'; - end if; - when "CALL|K " => -- call - if iphase = 0 then - result.pc_load := '1'; - result.stk_push := '1'; - end if; - when "RET " => -- return - if iphase = 0 then - result.pc_load := '1'; - result.stk_pop := '1'; - end if; - when "RETI " => -- return - result.pc_inc := '0'; - result.int_exit := '1'; - - when others => null; -- nop - end case; - - return result; - - end idecoder; - - function gen_murom return murom_t is - variable result : murom_t; - variable opcode : opcode_t; - variable iphase : iphase_t; - variable addr : unsigned(MUCODE_ADDR_WIDTH-1 downto 0); - variable status : cpu_status_t; - variable pos : integer := 0; - - begin - for i in 0 to 2**addr'length-1 loop - addr := to_unsigned(i, addr'length); - opcode := addr(opcode'length-1 downto 0); - pos := opcode'length; - iphase := 0; - if addr(pos) = '1' then - iphase := 1; - end if; - pos := pos + 1; - status.alu.zero := addr(pos); - pos := pos + 1; - status.alu.carry := addr(pos); - - result(i) := idecoder(opcode, iphase, status); - end loop; - - return result; - end gen_murom; - - function get_muromaddr (opcode : opcode_t; iphase : iphase_t; status : cpu_status_t) return unsigned is - variable addr : unsigned(MUCODE_ADDR_WIDTH-1 downto 0); - begin - addr := status.alu.carry & status.alu.zero & to_unsigned(iphase, 1) & opcode; - return addr; - - end get_muromaddr; - - ------------------------------------------------------------- - function MIN (X, Y: INTEGER) return INTEGER is - variable res : integer := X; - begin - if Y < X then - res := Y; - end if; - - return res; - - end MIN; - - ------------------------------------------------------------- - function MAX (X, Y: INTEGER) return INTEGER is - variable res : integer := X; - begin - if Y > X then - res := Y; - end if; - - return res; - - end MAX; - - -end cpu_pkg; - diff --git a/lib/CPUs/JCpu/src/core/dpath_ctrl.vhd b/lib/CPUs/JCpu/src/core/dpath_ctrl.vhd deleted file mode 100644 index 1610d00..0000000 --- a/lib/CPUs/JCpu/src/core/dpath_ctrl.vhd +++ /dev/null @@ -1,87 +0,0 @@ --------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: The datapath controller --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.cpu_pkg.all; - -entity dpath_ctrl is - Generic ( - use_rom : boolean := true - ); - Port ( - inst_in : in inst_t; - iphase_in : in iphase_t; - status_in : in cpu_status_t; - ctrl_out : out dpath_ctrl_out_t; - idout : out inst_addr_t; - ddout : out dmem_data_t - ); -end dpath_ctrl; - -architecture Behavioral of dpath_ctrl is - - signal opcode : opcode_t; - signal ctrl_lines : ctrl_lines_t; - signal dbg_iname : instr_name_t; - -begin - - idout <= inst_in(IMEM_ADDR_WIDTH-1 downto 0); - ddout <= inst_in(REG_SIZE_BITS+DMEM_DATA_WIDTH-1 downto REG_SIZE_BITS); - opcode <= inst_in(IMEM_DATA_WIDTH-1 downto IMEM_DATA_WIDTH-INST_OPCODE_WIDTH); - - ctrl_out.reg_a_ptr <= inst_in(reg_ptr_t'length-1 downto 0); - ctrl_out.reg_b_ptr <= inst_in(2*(reg_ptr_t'length)-1 downto reg_ptr_t'length); - ctrl_out.lines <= ctrl_lines; - - -- pragma translate_off - dbg_iname <= instr_name_array(to_integer(opcode)); - -- pragma translate_on - -gen_ctrl_rom: -if use_rom = true generate - - i_dec: - process(opcode, iphase_in, status_in) - constant rom_data : murom_t := gen_murom; - variable addr : unsigned(MUCODE_ADDR_WIDTH-1 downto 0); - begin - addr := get_muromaddr(opcode, iphase_in, status_in); - ctrl_lines <= rom_data(to_integer(addr)); - end process; -end generate; - -gen_ctrl: -if use_rom = false generate - i_dec: - process (opcode, iphase_in, status_in) - begin - ctrl_lines <= idecoder(opcode, iphase_in, status_in); - end process; -end generate; - -end Behavioral; - diff --git a/lib/CPUs/JCpu/src/core/int_ctrl.vhd b/lib/CPUs/JCpu/src/core/int_ctrl.vhd deleted file mode 100644 index ebff3db..0000000 --- a/lib/CPUs/JCpu/src/core/int_ctrl.vhd +++ /dev/null @@ -1,138 +0,0 @@ --------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: Interrupt controller --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.cpu_pkg.all; - -entity int_ctrl is - Port ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - ctrl_in : in int_ctrl_in_t; - int_in : in STD_LOGIC; - int_exit : in STD_LOGIC; - iphase_in : in iphase_t; - pc_addr_out : out inst_addr_t; - int_ack_out : out STD_LOGIC; - stat_save_out : out STD_LOGIC; - stat_rest_out : out STD_LOGIC; - pc_load_out : out STD_LOGIC; - stk_push_out : out STD_LOGIC; - stk_pop_out : out STD_LOGIC - ); -end int_ctrl; - -architecture Behavioral of int_ctrl is - - type int_state_t is (int_idle, int_inject, int_active, int_release); - - signal int_state, int_state_next : int_state_t; - signal pc_load, int_ack, stk_push, stk_pop : STD_LOGIC; - signal int_request : std_logic; - - -begin - - int_ack_out <= int_ack; - pc_load_out <= pc_load; - stk_push_out <= stk_push; - stk_pop_out <= stk_pop; - ------------------------------------------------------------------------ -irg_ctrl_fsm: - process (int_state, iphase_in, int_request, int_exit) - begin - - pc_addr_out <= to_unsigned(1, inst_addr_t'length); - int_state_next <= int_state; - int_ack <= '0'; - pc_load <= '0'; - stk_push <= '0'; - stk_pop <= '0'; - case int_state is - - when int_idle => - if int_request = '1' and iphase_in = 1 then - int_state_next <= int_inject; - end if; - when int_inject => - if iphase_in = 0 then - int_ack <= '1'; - pc_load <= '1'; - elsif iphase_in = 1 then - stk_push <= '1'; - int_state_next <= int_active; - end if; - when int_active => - if int_exit = '1' and iphase_in = 1 then - int_state_next <= int_release; - end if; - when int_release => - if iphase_in = 0 then - stk_pop <= '1'; - pc_load <= '1'; - elsif iphase_in = 1 then - int_state_next <= int_idle; - end if; - when others => - int_state_next <= int_idle; - end case; - - end process; - -irq_ctrl_states: - process (rst, clk, int_state_next) - begin - if rst = '1' then - int_state <= int_idle; - elsif rising_edge(clk) then - int_state <= int_state_next; - end if; - end process; - ------------------------------------------------------------------------ -pin_sample: - process (clk) - begin - if rising_edge(clk) then - int_request <= '0'; - if ctrl_in.enable = '1' then - int_request <= int_in; - end if; - end if; - end process; - ------------------------------------------------------------------------ -stat_save_restore: - process (clk, stk_push, stk_pop) - begin - if rising_edge(clk) then - stat_save_out <= stk_push; - stat_rest_out <= stk_pop; - end if; - end process; - -end Behavioral; diff --git a/lib/CPUs/JCpu/src/core/pc.vhd b/lib/CPUs/JCpu/src/core/pc.vhd deleted file mode 100644 index 6b1d575..0000000 --- a/lib/CPUs/JCpu/src/core/pc.vhd +++ /dev/null @@ -1,70 +0,0 @@ --------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: Programm counter --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.cpu_pkg.all; - -entity pc is - Port ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - inc : in STD_LOGIC; - load : in STD_LOGIC; - pc_in : in inst_addr_t; - pc_out : out inst_addr_t; - pc_next : out inst_addr_t - ); -end pc; - -architecture Behavioral of pc is - -begin - -proc_pc: - process(rst, clk, inc, load, pc_in) - variable vpc, vpc_reg: inst_addr_t; - begin - if rst = '1' then - vpc_reg := (others => '0'); - elsif rising_edge(clk) then - if inc = '1' or load = '1' then - vpc_reg := vpc; - elsif inc = '0' then - pc_next <= vpc; - end if; - end if; - - if load = '1' then - vpc := pc_in; - else - vpc := vpc_reg + 1; - end if; - pc_out <= vpc_reg; - - end process; - -end Behavioral; - diff --git a/lib/CPUs/JCpu/src/core/reg_dual.vhd b/lib/CPUs/JCpu/src/core/reg_dual.vhd deleted file mode 100644 index 6b7e4d8..0000000 --- a/lib/CPUs/JCpu/src/core/reg_dual.vhd +++ /dev/null @@ -1,81 +0,0 @@ --------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: On-Chip work registers --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.cpu_pkg.all; - -entity reg_dual is - Generic ( - addr_width : integer := 3; - data_width : integer := 8 - ); - Port ( - clk : in STD_LOGIC; - we_a : in STD_LOGIC; - ptr_a : in reg_ptr_t; - ptr_b : in reg_ptr_t; - din_a : in unsigned (data_width-1 downto 0); - dout_a : out unsigned (data_width-1 downto 0); - dout_b : out unsigned (data_width-1 downto 0) - ); -end reg_dual; - -architecture Behavioral of reg_dual is - - constant depth : integer := 2**addr_width; - type mem_t is array (0 to depth-1) of unsigned (data_width-1 downto 0); - signal addr_a, addr_b : unsigned (addr_width-1 downto 0) := (others => '0'); - - signal mem : mem_t; -begin - - addr_a <= TO_01(ptr_a(addr_width-1 downto 0)); - addr_b <= TO_01(ptr_b(addr_width-1 downto 0)); - -reg_in_ab: - process(clk) - begin - if rising_edge(clk) then - if we_a = '1' then - mem(to_integer(addr_a)) <= din_a; - end if; - end if; - end process; - -reg_out_a: - process(mem, addr_a) - begin - dout_a <= TO_01(mem(to_integer(addr_a))); - end process; - -reg_out_b: - process(mem, addr_b) - begin - dout_b <= TO_01(mem(to_integer(addr_b))); - end process; - -end Behavioral; - diff --git a/lib/CPUs/JCpu/src/core/stack_ctrl.vhd b/lib/CPUs/JCpu/src/core/stack_ctrl.vhd deleted file mode 100644 index 7eccae3..0000000 --- a/lib/CPUs/JCpu/src/core/stack_ctrl.vhd +++ /dev/null @@ -1,73 +0,0 @@ --------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: The call/return/data stack --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.cpu_pkg.all; - -entity stack_ctrl is -Generic ( - addr_width : integer := 3 -); -Port ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - push : in STD_LOGIC; - pop : in STD_LOGIC; - ptr_out : out unsigned (addr_width-1 downto 0); - din : in inst_addr_t; - dout : out inst_addr_t; - mem_we : out STD_LOGIC - ); -end stack_ctrl; - -architecture Behavioral of stack_ctrl is - - signal ptr : unsigned (addr_width-1 downto 0); - -begin - - ptr_out <= ptr; - -stk_ptr: - process(rst, clk, ptr, push, pop) - begin - if rst = '1' then - ptr <= (others => '0'); - dout <= (others => '0'); - mem_we <= '0'; - elsif rising_edge(clk) then - mem_we <= push; - if push = '1' then - ptr <= ptr + 1; - dout <= din; - elsif pop = '1' then - ptr <= ptr - 1; - end if; - end if; - end process; - -end Behavioral; - diff --git a/lib/CPUs/JCpu/src/cpu_embedded.vhd b/lib/CPUs/JCpu/src/cpu_embedded.vhd deleted file mode 100644 index 56c6dec..0000000 --- a/lib/CPUs/JCpu/src/cpu_embedded.vhd +++ /dev/null @@ -1,106 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: cpu_embedded using cpu_core and rom --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.cpu_pkg.all; - -entity cpu_embedded is - Port ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - ce : in STD_LOGIC; - int_in : in STD_LOGIC; - int_ack : out STD_LOGIC; - xmem_we : out STD_LOGIC; - xmem_re : out STD_LOGIC; - xmem_din : in unsigned (DMEM_DATA_WIDTH-1 downto 0); - xmem_dout : out unsigned (DMEM_DATA_WIDTH-1 downto 0); - xmem_addr : out unsigned (DMEM_ADDR_WIDTH-1 downto 0); - io_sel : out STD_LOGIC - ); -end cpu_embedded; - -architecture rtl of cpu_embedded is - - signal irom_data : unsigned (IMEM_DATA_WIDTH-1 downto 0); - signal irom_addr : unsigned (IMEM_ADDR_WIDTH-1 downto 0); - - COMPONENT cpu - Port ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - ce : in STD_LOGIC; - int_in : in STD_LOGIC; - int_ack : out STD_LOGIC; - xmem_we : out STD_LOGIC; - xmem_re : out STD_LOGIC; - instr_din : in unsigned (IMEM_DATA_WIDTH-1 downto 0); - instr_addr : out unsigned (IMEM_ADDR_WIDTH-1 downto 0); - xmem_din : in unsigned (DMEM_DATA_WIDTH-1 downto 0); - xmem_dout : out unsigned (DMEM_DATA_WIDTH-1 downto 0); - xmem_addr : out unsigned (DMEM_DATA_WIDTH-1 downto 0); - io_sel : out STD_LOGIC - ); - END COMPONENT; - - - COMPONENT irom - Port ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - addr : in inst_addr_t; - dout : out inst_t - ); - END COMPONENT; - -begin - -inst_cpu: cpu - PORT MAP( - rst => rst, - clk => clk, - ce => ce, - int_in => int_in, - int_ack => int_ack, - xmem_we => xmem_we, - xmem_re => xmem_re, - instr_din => irom_data, - instr_addr => irom_addr, - xmem_din => xmem_din, - xmem_dout => xmem_dout, - xmem_addr => xmem_addr, - io_sel => io_sel - ); - -inst_irom: irom - PORT MAP( - clk => clk, - ce => ce, - addr => irom_addr, - dout => irom_data - ); - -end rtl; diff --git a/lib/CPUs/JCpu/src/dctest_irom.vhdl b/lib/CPUs/JCpu/src/dctest_irom.vhdl deleted file mode 100644 index 7987a15..0000000 --- a/lib/CPUs/JCpu/src/dctest_irom.vhdl +++ /dev/null @@ -1,79 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: The ROM file for use in your VHDL design --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library work; -use work.cpu_pkg.all; - --- JASM_ROM_INSERT_HERE -ENTITY irom IS - Port ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - addr : in inst_addr_t; - dout : out inst_t - ); -END irom; - -ARCHITECTURE dctest OF irom IS - - type imem_rom_t is array (0 to 17) of inst_t; - - -- Assembled from dctest.jsm - constant imem_rom : imem_rom_t := - ( - "110000" & X"010", -- 0x000: JMP 0x010 - "110000" & X"011", -- 0x001: JMP 0x011 - "000000" & X"000", -- 0x002: - "000000" & X"000", -- 0x003: - "000000" & X"000", -- 0x004: - "000000" & X"000", -- 0x005: - "000000" & X"000", -- 0x006: - "000000" & X"000", -- 0x007: - "000000" & X"000", -- 0x008: - "000000" & X"000", -- 0x009: - "000000" & X"000", -- 0x00A: - "000000" & X"000", -- 0x00B: - "000000" & X"000", -- 0x00C: - "000000" & X"000", -- 0x00D: - "000000" & X"000", -- 0x00E: - "000000" & X"000", -- 0x00F: - "110000" & X"010", -- 0x010: JMP 0x010 - "111111" & X"000" -- 0x011: RETI - ); - -begin - -PROM_READ: - process(clk, ce) - begin - if rising_edge(clk) and ce = '1' then - dout <= imem_rom(to_integer(addr)); - end if; - end process; - -end dctest; - diff --git a/lib/CPUs/JCpu/src/dctest_irom_ld.vhdl b/lib/CPUs/JCpu/src/dctest_irom_ld.vhdl deleted file mode 100644 index 223dd46..0000000 --- a/lib/CPUs/JCpu/src/dctest_irom_ld.vhdl +++ /dev/null @@ -1,1181 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: loadable ROM --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library UNISIM; -use UNISIM.VComponents.all; - -library work; -use work.cpu_pkg.all; - -ENTITY irom IS - Port ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - addr : in inst_addr_t; - dout : out inst_t - ); - -END irom; - -ARCHITECTURE loadable OF irom IS - - -- JASM_ROM_INSERT_HERE - - -- Assembled from dctest.jsm - type imem_rom_t is array (0 to 1023) of inst_t; - signal imem_rom : imem_rom_t := - ( - "110000" & X"010", -- 0x000: JMP 0x010 - "110000" & X"011", -- 0x001: JMP 0x011 - "000000" & X"000", -- 0x002: - "000000" & X"000", -- 0x003: - "000000" & X"000", -- 0x004: - "000000" & X"000", -- 0x005: - "000000" & X"000", -- 0x006: - "000000" & X"000", -- 0x007: - "000000" & X"000", -- 0x008: - "000000" & X"000", -- 0x009: - "000000" & X"000", -- 0x00A: - "000000" & X"000", -- 0x00B: - "000000" & X"000", -- 0x00C: - "000000" & X"000", -- 0x00D: - "000000" & X"000", -- 0x00E: - "000000" & X"000", -- 0x00F: - "110000" & X"010", -- 0x010: JMP 0x010 - "111111" & X"000", -- 0x011: RETI - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000" - ); - - signal jtag_ld_clk : STD_LOGIC; - signal jtag_ld_we : STD_LOGIC; - signal jtag_ld_addr : inst_addr_t; - signal jtag_ld_dout : inst_t; - signal jtag_ld_din : inst_t; - signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic; - signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic; - signal user_regi, user_rego : unsigned (31 downto 0); - constant id : unsigned (31 downto 0) := X"BABE" & X"BEEF"; - -begin - --------------------------------------------------------------------------- --- Virtex-4: JTAG Loader --------------------------------------------------------------------------- - i00_BUFG : BUFG - port map - ( - O => bs_clk1, - I => bs_clk0 - ); - - i01_BUFG : BUFG - port map - ( - O => bs_update1, - I => bs_update0 - ); - - BSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 - generic map - ( - JTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4) - ) - port map - ( - CAPTURE => bs_capture, -- CAPTURE output from TAP controller - DRCK => bs_clk0, -- Data register output for USER functions - RESET => bs_rst, -- Reset output from TAP controller - SEL => bs_sel, -- USER active output - SHIFT => bs_shift, -- SHIFT output from TAP controller - TDI => bs_tdi, -- TDI output from TAP controller - UPDATE => bs_update0, -- UPDATE output from TAP controller - TDO => bs_tdo -- Data input for USER function - ); - - jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-inst_addr_t'length+1); - jtag_ld_din <= user_regi(inst_t'length-1 downto 0); - jtag_ld_clk <= bs_update1; - jtag_ld_we <= bs_sel; - -sipo: - process (bs_rst, bs_clk1, bs_tdi, bs_shift) - begin - if bs_rst = '1' then - user_regi <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_regi <= bs_tdi & user_regi(user_regi'left downto 1); - end if; - end if; - end process; - -piso: - process (bs_rst, bs_clk1, bs_shift, user_rego) - begin - bs_tdo <= user_rego(0); - if bs_rst = '1' then - user_rego <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_rego <= user_rego(0) & user_rego(user_rego'left downto 1); - else - user_rego <= (user_rego'left downto inst_t'length => '0') & jtag_ld_dout; --- user_rego <= id; - end if; - end if; - end process; - --------------------------------------------------------------------------- --- ROM Read/Write --------------------------------------------------------------------------- -PROM_READ: - process(clk, ce) - begin - if rising_edge(clk) and ce = '1' then - dout <= imem_rom(to_integer(addr)); - end if; - end process; - -PROM_WRITE: - process(jtag_ld_clk, jtag_ld_we) - begin - if rising_edge(jtag_ld_clk) then - if jtag_ld_we = '1' then - imem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din; - else - jtag_ld_dout <= imem_rom(to_integer(jtag_ld_addr)); - end if; - end if; - end process; - --------------------------------------------------------------------------- -end loadable; diff --git a/lib/CPUs/JCpu/src/dctest_xrom.vhdl b/lib/CPUs/JCpu/src/dctest_xrom.vhdl deleted file mode 100644 index 24fe36c..0000000 --- a/lib/CPUs/JCpu/src/dctest_xrom.vhdl +++ /dev/null @@ -1,317 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: The ROM file for use in your VHDL design --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library work; -use work.cpu_pkg.all; - --- JASM_ROM_INSERT_HERE -ENTITY xrom IS - Port ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - addr : in dmem_addr_t; - dout : out dmem_data_t - ); -END xrom; - -ARCHITECTURE dctest OF xrom IS - - type xmem_rom_t is array (0 to 255) of dmem_data_t; - - -- Assembled from dctest.jsm - constant xmem_rom : xmem_rom_t := - ( - X"00", -- 0x00 - X"00", -- 0x01 - X"00", -- 0x02 - X"00", -- 0x03 - X"01", -- 0x04 - X"12", -- 0x05 - X"41", -- 0x06 - X"00", -- 0x07 - X"00", -- 0x08 - X"00", -- 0x09 - X"00", -- 0x0A - X"00", -- 0x0B - X"00", -- 0x0C - X"00", -- 0x0D - X"00", -- 0x0E - X"00", -- 0x0F - X"00", -- 0x10 - X"00", -- 0x11 - X"00", -- 0x12 - X"00", -- 0x13 - X"00", -- 0x14 - X"00", -- 0x15 - X"00", -- 0x16 - X"48", -- 0x17 - X"61", -- 0x18 - X"6C", -- 0x19 - X"6C", -- 0x1A - X"6F", -- 0x1B - X"0D", -- 0x1C - X"0A", -- 0x1D - X"00", -- 0x1E - X"4A", -- 0x1F - X"65", -- 0x20 - X"6E", -- 0x21 - X"73", -- 0x22 - X"00", -- 0x23 - X"57", -- 0x24 - X"65", -- 0x25 - X"6C", -- 0x26 - X"63", -- 0x27 - X"6F", -- 0x28 - X"6D", -- 0x29 - X"65", -- 0x2A - X"20", -- 0x2B - X"74", -- 0x2C - X"6F", -- 0x2D - X"20", -- 0x2E - X"4A", -- 0x2F - X"41", -- 0x30 - X"53", -- 0x31 - X"4D", -- 0x32 - X"20", -- 0x33 - X"43", -- 0x34 - X"50", -- 0x35 - X"55", -- 0x36 - X"00", -- 0x37 - X"52", -- 0x38 - X"65", -- 0x39 - X"61", -- 0x3A - X"64", -- 0x3B - X"79", -- 0x3C - X"00", -- 0x3D - X"54", -- 0x3E - X"65", -- 0x3F - X"73", -- 0x40 - X"74", -- 0x41 - X"69", -- 0x42 - X"6E", -- 0x43 - X"67", -- 0x44 - X"00", -- 0x45 - X"50", -- 0x46 - X"61", -- 0x47 - X"73", -- 0x48 - X"73", -- 0x49 - X"65", -- 0x4A - X"64", -- 0x4B - X"00", -- 0x4C - X"45", -- 0x4D - X"72", -- 0x4E - X"72", -- 0x4F - X"6F", -- 0x50 - X"72", -- 0x51 - X"00", -- 0x52 - X"0D", -- 0x53 - X"0A", -- 0x54 - X"00", -- 0x55 - X"00", -- 0x56 - X"00", -- 0x57 - X"00", -- 0x58 - X"00", -- 0x59 - X"00", -- 0x5A - X"00", -- 0x5B - X"00", -- 0x5C - X"00", -- 0x5D - X"00", -- 0x5E - X"00", -- 0x5F - X"00", -- 0x60 - X"00", -- 0x61 - X"00", -- 0x62 - X"00", -- 0x63 - X"00", -- 0x64 - X"00", -- 0x65 - X"00", -- 0x66 - X"00", -- 0x67 - X"00", -- 0x68 - X"00", -- 0x69 - X"00", -- 0x6A - X"00", -- 0x6B - X"00", -- 0x6C - X"00", -- 0x6D - X"00", -- 0x6E - X"00", -- 0x6F - X"00", -- 0x70 - X"00", -- 0x71 - X"00", -- 0x72 - X"00", -- 0x73 - X"00", -- 0x74 - X"00", -- 0x75 - X"00", -- 0x76 - X"00", -- 0x77 - X"00", -- 0x78 - X"00", -- 0x79 - X"00", -- 0x7A - X"00", -- 0x7B - X"00", -- 0x7C - X"00", -- 0x7D - X"00", -- 0x7E - X"00", -- 0x7F - X"00", -- 0x80 - X"00", -- 0x81 - X"00", -- 0x82 - X"00", -- 0x83 - X"00", -- 0x84 - X"00", -- 0x85 - X"00", -- 0x86 - X"00", -- 0x87 - X"00", -- 0x88 - X"00", -- 0x89 - X"00", -- 0x8A - X"00", -- 0x8B - X"00", -- 0x8C - X"00", -- 0x8D - X"00", -- 0x8E - X"00", -- 0x8F - X"00", -- 0x90 - X"00", -- 0x91 - X"00", -- 0x92 - X"00", -- 0x93 - X"00", -- 0x94 - X"00", -- 0x95 - X"00", -- 0x96 - X"00", -- 0x97 - X"00", -- 0x98 - X"00", -- 0x99 - X"00", -- 0x9A - X"00", -- 0x9B - X"00", -- 0x9C - X"00", -- 0x9D - X"00", -- 0x9E - X"00", -- 0x9F - X"00", -- 0xA0 - X"00", -- 0xA1 - X"00", -- 0xA2 - X"00", -- 0xA3 - X"00", -- 0xA4 - X"00", -- 0xA5 - X"00", -- 0xA6 - X"00", -- 0xA7 - X"00", -- 0xA8 - X"00", -- 0xA9 - X"00", -- 0xAA - X"00", -- 0xAB - X"00", -- 0xAC - X"00", -- 0xAD - X"00", -- 0xAE - X"00", -- 0xAF - X"00", -- 0xB0 - X"00", -- 0xB1 - X"00", -- 0xB2 - X"00", -- 0xB3 - X"00", -- 0xB4 - X"00", -- 0xB5 - X"00", -- 0xB6 - X"00", -- 0xB7 - X"00", -- 0xB8 - X"00", -- 0xB9 - X"00", -- 0xBA - X"00", -- 0xBB - X"00", -- 0xBC - X"00", -- 0xBD - X"00", -- 0xBE - X"00", -- 0xBF - X"00", -- 0xC0 - X"00", -- 0xC1 - X"00", -- 0xC2 - X"00", -- 0xC3 - X"00", -- 0xC4 - X"00", -- 0xC5 - X"00", -- 0xC6 - X"00", -- 0xC7 - X"00", -- 0xC8 - X"00", -- 0xC9 - X"00", -- 0xCA - X"00", -- 0xCB - X"00", -- 0xCC - X"00", -- 0xCD - X"00", -- 0xCE - X"00", -- 0xCF - X"00", -- 0xD0 - X"00", -- 0xD1 - X"00", -- 0xD2 - X"00", -- 0xD3 - X"00", -- 0xD4 - X"00", -- 0xD5 - X"00", -- 0xD6 - X"00", -- 0xD7 - X"00", -- 0xD8 - X"00", -- 0xD9 - X"00", -- 0xDA - X"00", -- 0xDB - X"00", -- 0xDC - X"00", -- 0xDD - X"00", -- 0xDE - X"00", -- 0xDF - X"00", -- 0xE0 - X"00", -- 0xE1 - X"00", -- 0xE2 - X"00", -- 0xE3 - X"00", -- 0xE4 - X"00", -- 0xE5 - X"00", -- 0xE6 - X"00", -- 0xE7 - X"00", -- 0xE8 - X"00", -- 0xE9 - X"00", -- 0xEA - X"00", -- 0xEB - X"00", -- 0xEC - X"00", -- 0xED - X"00", -- 0xEE - X"00", -- 0xEF - X"00", -- 0xF0 - X"00", -- 0xF1 - X"00", -- 0xF2 - X"00", -- 0xF3 - X"00", -- 0xF4 - X"00", -- 0xF5 - X"00", -- 0xF6 - X"00", -- 0xF7 - X"00", -- 0xF8 - X"00", -- 0xF9 - X"00", -- 0xFA - X"00", -- 0xFB - X"00", -- 0xFC - X"00", -- 0xFD - X"00", -- 0xFE - X"00" -- 0xFF - ); - -begin - -PROM_READ: - process(clk, ce) - begin - if rising_edge(clk) and ce = '1' then - dout <= xmem_rom(to_integer(addr)); - end if; - end process; - -end dctest; - diff --git a/lib/CPUs/JCpu/src/dctest_xrom_ld.vhdl b/lib/CPUs/JCpu/src/dctest_xrom_ld.vhdl deleted file mode 100644 index 802ba50..0000000 --- a/lib/CPUs/JCpu/src/dctest_xrom_ld.vhdl +++ /dev/null @@ -1,413 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: loadable ROM --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library UNISIM; -use UNISIM.VComponents.all; - -library work; -use work.cpu_pkg.all; - -ENTITY xrom IS - Port ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - addr : in dmem_addr_t; - dout : out dmem_data_t - ); - -END xrom; - -ARCHITECTURE loadable OF xrom IS - - -- JASM_ROM_INSERT_HERE - - -- Assembled from dctest.jsm - type xmem_rom_t is array (0 to 255) of dmem_data_t; - signal xmem_rom : xmem_rom_t := - ( - X"00", -- 0x00 - X"00", -- 0x01 - X"00", -- 0x02 - X"00", -- 0x03 - X"01", -- 0x04 - X"12", -- 0x05 - X"41", -- 0x06 - X"00", -- 0x07 - X"00", -- 0x08 - X"00", -- 0x09 - X"00", -- 0x0A - X"00", -- 0x0B - X"00", -- 0x0C - X"00", -- 0x0D - X"00", -- 0x0E - X"00", -- 0x0F - X"00", -- 0x10 - X"00", -- 0x11 - X"00", -- 0x12 - X"00", -- 0x13 - X"00", -- 0x14 - X"00", -- 0x15 - X"00", -- 0x16 - X"48", -- 0x17 - X"61", -- 0x18 - X"6C", -- 0x19 - X"6C", -- 0x1A - X"6F", -- 0x1B - X"0D", -- 0x1C - X"0A", -- 0x1D - X"00", -- 0x1E - X"4A", -- 0x1F - X"65", -- 0x20 - X"6E", -- 0x21 - X"73", -- 0x22 - X"00", -- 0x23 - X"57", -- 0x24 - X"65", -- 0x25 - X"6C", -- 0x26 - X"63", -- 0x27 - X"6F", -- 0x28 - X"6D", -- 0x29 - X"65", -- 0x2A - X"20", -- 0x2B - X"74", -- 0x2C - X"6F", -- 0x2D - X"20", -- 0x2E - X"4A", -- 0x2F - X"41", -- 0x30 - X"53", -- 0x31 - X"4D", -- 0x32 - X"20", -- 0x33 - X"43", -- 0x34 - X"50", -- 0x35 - X"55", -- 0x36 - X"00", -- 0x37 - X"52", -- 0x38 - X"65", -- 0x39 - X"61", -- 0x3A - X"64", -- 0x3B - X"79", -- 0x3C - X"00", -- 0x3D - X"54", -- 0x3E - X"65", -- 0x3F - X"73", -- 0x40 - X"74", -- 0x41 - X"69", -- 0x42 - X"6E", -- 0x43 - X"67", -- 0x44 - X"00", -- 0x45 - X"50", -- 0x46 - X"61", -- 0x47 - X"73", -- 0x48 - X"73", -- 0x49 - X"65", -- 0x4A - X"64", -- 0x4B - X"00", -- 0x4C - X"45", -- 0x4D - X"72", -- 0x4E - X"72", -- 0x4F - X"6F", -- 0x50 - X"72", -- 0x51 - X"00", -- 0x52 - X"0D", -- 0x53 - X"0A", -- 0x54 - X"00", -- 0x55 - X"00", -- 0x56 - X"00", -- 0x57 - X"00", -- 0x58 - X"00", -- 0x59 - X"00", -- 0x5A - X"00", -- 0x5B - X"00", -- 0x5C - X"00", -- 0x5D - X"00", -- 0x5E - X"00", -- 0x5F - X"00", -- 0x60 - X"00", -- 0x61 - X"00", -- 0x62 - X"00", -- 0x63 - X"00", -- 0x64 - X"00", -- 0x65 - X"00", -- 0x66 - X"00", -- 0x67 - X"00", -- 0x68 - X"00", -- 0x69 - X"00", -- 0x6A - X"00", -- 0x6B - X"00", -- 0x6C - X"00", -- 0x6D - X"00", -- 0x6E - X"00", -- 0x6F - X"00", -- 0x70 - X"00", -- 0x71 - X"00", -- 0x72 - X"00", -- 0x73 - X"00", -- 0x74 - X"00", -- 0x75 - X"00", -- 0x76 - X"00", -- 0x77 - X"00", -- 0x78 - X"00", -- 0x79 - X"00", -- 0x7A - X"00", -- 0x7B - X"00", -- 0x7C - X"00", -- 0x7D - X"00", -- 0x7E - X"00", -- 0x7F - X"00", -- 0x80 - X"00", -- 0x81 - X"00", -- 0x82 - X"00", -- 0x83 - X"00", -- 0x84 - X"00", -- 0x85 - X"00", -- 0x86 - X"00", -- 0x87 - X"00", -- 0x88 - X"00", -- 0x89 - X"00", -- 0x8A - X"00", -- 0x8B - X"00", -- 0x8C - X"00", -- 0x8D - X"00", -- 0x8E - X"00", -- 0x8F - X"00", -- 0x90 - X"00", -- 0x91 - X"00", -- 0x92 - X"00", -- 0x93 - X"00", -- 0x94 - X"00", -- 0x95 - X"00", -- 0x96 - X"00", -- 0x97 - X"00", -- 0x98 - X"00", -- 0x99 - X"00", -- 0x9A - X"00", -- 0x9B - X"00", -- 0x9C - X"00", -- 0x9D - X"00", -- 0x9E - X"00", -- 0x9F - X"00", -- 0xA0 - X"00", -- 0xA1 - X"00", -- 0xA2 - X"00", -- 0xA3 - X"00", -- 0xA4 - X"00", -- 0xA5 - X"00", -- 0xA6 - X"00", -- 0xA7 - X"00", -- 0xA8 - X"00", -- 0xA9 - X"00", -- 0xAA - X"00", -- 0xAB - X"00", -- 0xAC - X"00", -- 0xAD - X"00", -- 0xAE - X"00", -- 0xAF - X"00", -- 0xB0 - X"00", -- 0xB1 - X"00", -- 0xB2 - X"00", -- 0xB3 - X"00", -- 0xB4 - X"00", -- 0xB5 - X"00", -- 0xB6 - X"00", -- 0xB7 - X"00", -- 0xB8 - X"00", -- 0xB9 - X"00", -- 0xBA - X"00", -- 0xBB - X"00", -- 0xBC - X"00", -- 0xBD - X"00", -- 0xBE - X"00", -- 0xBF - X"00", -- 0xC0 - X"00", -- 0xC1 - X"00", -- 0xC2 - X"00", -- 0xC3 - X"00", -- 0xC4 - X"00", -- 0xC5 - X"00", -- 0xC6 - X"00", -- 0xC7 - X"00", -- 0xC8 - X"00", -- 0xC9 - X"00", -- 0xCA - X"00", -- 0xCB - X"00", -- 0xCC - X"00", -- 0xCD - X"00", -- 0xCE - X"00", -- 0xCF - X"00", -- 0xD0 - X"00", -- 0xD1 - X"00", -- 0xD2 - X"00", -- 0xD3 - X"00", -- 0xD4 - X"00", -- 0xD5 - X"00", -- 0xD6 - X"00", -- 0xD7 - X"00", -- 0xD8 - X"00", -- 0xD9 - X"00", -- 0xDA - X"00", -- 0xDB - X"00", -- 0xDC - X"00", -- 0xDD - X"00", -- 0xDE - X"00", -- 0xDF - X"00", -- 0xE0 - X"00", -- 0xE1 - X"00", -- 0xE2 - X"00", -- 0xE3 - X"00", -- 0xE4 - X"00", -- 0xE5 - X"00", -- 0xE6 - X"00", -- 0xE7 - X"00", -- 0xE8 - X"00", -- 0xE9 - X"00", -- 0xEA - X"00", -- 0xEB - X"00", -- 0xEC - X"00", -- 0xED - X"00", -- 0xEE - X"00", -- 0xEF - X"00", -- 0xF0 - X"00", -- 0xF1 - X"00", -- 0xF2 - X"00", -- 0xF3 - X"00", -- 0xF4 - X"00", -- 0xF5 - X"00", -- 0xF6 - X"00", -- 0xF7 - X"00", -- 0xF8 - X"00", -- 0xF9 - X"00", -- 0xFA - X"00", -- 0xFB - X"00", -- 0xFC - X"00", -- 0xFD - X"00", -- 0xFE - X"00" -- 0xFF - ); - - signal jtag_ld_clk : STD_LOGIC; - signal jtag_ld_we : STD_LOGIC; - signal jtag_ld_addr : dmem_addr_t; - signal jtag_ld_dout : dmem_data_t; - signal jtag_ld_din : dmem_data_t; - signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic; - signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic; - signal user_regi, user_rego : unsigned (15 downto 0); - constant id : unsigned (15 downto 0) := X"BEEF"; - -begin - --------------------------------------------------------------------------- --- Virtex-4: JTAG Loader --------------------------------------------------------------------------- - i00_BUFG : BUFG - port map - ( - O => bs_clk1, - I => bs_clk0 - ); - - i01_BUFG : BUFG - port map - ( - O => bs_update1, - I => bs_update0 - ); - - BSCAN_VIRTEX4_inst2 : BSCAN_VIRTEX4 - generic map - ( - JTAG_CHAIN => 2 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4) - ) - port map - ( - CAPTURE => bs_capture, -- CAPTURE output from TAP controller - DRCK => bs_clk0, -- Data register output for USER functions - RESET => bs_rst, -- Reset output from TAP controller - SEL => bs_sel, -- USER active output - SHIFT => bs_shift, -- SHIFT output from TAP controller - TDI => bs_tdi, -- TDI output from TAP controller - UPDATE => bs_update0, -- UPDATE output from TAP controller - TDO => bs_tdo -- Data input for USER function - ); - - jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-dmem_data_t'length+1); - jtag_ld_din <= user_regi(dmem_data_t'left downto 0); - jtag_ld_clk <= bs_update1; - jtag_ld_we <= bs_sel; - -sipo: - process (bs_rst, bs_clk1, bs_tdi, bs_shift) - begin - if bs_rst = '1' then - user_regi <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_regi <= bs_tdi & user_regi(user_regi'left downto 1); - end if; - end if; - end process; - -piso: - process (bs_rst, bs_clk1, bs_shift, user_rego) - begin - bs_tdo <= user_rego(0); - if bs_rst = '1' then - user_rego <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_rego <= user_rego(0) & user_rego(user_rego'left downto 1); - else - user_rego <= (user_rego'left downto dmem_data_t'length => '0') & jtag_ld_dout; --- user_rego <= id; - end if; - end if; - end process; - --------------------------------------------------------------------------- --- ROM Read/Write --------------------------------------------------------------------------- -PROM_READ: - process(clk, ce) - begin - if rising_edge(clk) and ce = '1' then - dout <= xmem_rom(to_integer(addr)); - end if; - end process; - -PROM_WRITE: - process(jtag_ld_clk, jtag_ld_we) - begin - if rising_edge(jtag_ld_clk) then - if jtag_ld_we = '1' then - xmem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din; - else - jtag_ld_dout <= xmem_rom(to_integer(jtag_ld_addr)); - end if; - end if; - end process; - --------------------------------------------------------------------------- -end loadable; diff --git a/lib/CPUs/JCpu/src/itest_irom.vhdl b/lib/CPUs/JCpu/src/itest_irom.vhdl deleted file mode 100644 index 0ed28f2..0000000 --- a/lib/CPUs/JCpu/src/itest_irom.vhdl +++ /dev/null @@ -1,1086 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: The ROM file for use in your VHDL design --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library work; -use work.cpu_pkg.all; - --- JASM_ROM_INSERT_HERE -ENTITY irom IS - Port - ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - addr : in inst_addr_t; - dout : out inst_t - ); -END irom; - -ARCHITECTURE itest OF irom IS - - type imem_rom_t is array (0 to 1023) of inst_t; - - -- Assembled from itest.jsm - constant imem_rom : imem_rom_t := - ( - "110000" & X"010", -- 0x000: JMP 0x010 - "110000" & X"288", -- 0x001: JMP 0x288 - "000000" & X"000", -- 0x002: - "000000" & X"000", -- 0x003: - "000000" & X"000", -- 0x004: - "000000" & X"000", -- 0x005: - "000000" & X"000", -- 0x006: - "000000" & X"000", -- 0x007: - "000000" & X"000", -- 0x008: - "000000" & X"000", -- 0x009: - "000000" & X"000", -- 0x00A: - "000000" & X"000", -- 0x00B: - "000000" & X"000", -- 0x00C: - "000000" & X"000", -- 0x00D: - "000000" & X"000", -- 0x00E: - "000000" & X"000", -- 0x00F: - "111011" & X"03B", -- 0x010: CALL 0x03B - "101001" & X"000", -- 0x011: CIN R00, (0x00) - "100100" & X"000", -- 0x012: XOUT (0x00), R00 - "111011" & X"04C", -- 0x013: CALL 0x04C - "000011" & X"010", -- 0x014: MOV R00, 0x01 - "100100" & X"010", -- 0x015: XOUT (0x01), R00 - "111011" & X"08D", -- 0x016: CALL 0x08D - "000011" & X"020", -- 0x017: MOV R00, 0x02 - "100100" & X"010", -- 0x018: XOUT (0x01), R00 - "111011" & X"0C9", -- 0x019: CALL 0x0C9 - "000011" & X"030", -- 0x01A: MOV R00, 0x03 - "100100" & X"010", -- 0x01B: XOUT (0x01), R00 - "111011" & X"0DB", -- 0x01C: CALL 0x0DB - "000011" & X"040", -- 0x01D: MOV R00, 0x04 - "100100" & X"010", -- 0x01E: XOUT (0x01), R00 - "111011" & X"0ED", -- 0x01F: CALL 0x0ED - "000011" & X"050", -- 0x020: MOV R00, 0x05 - "100100" & X"010", -- 0x021: XOUT (0x01), R00 - "111011" & X"0FF", -- 0x022: CALL 0x0FF - "000011" & X"060", -- 0x023: MOV R00, 0x06 - "100100" & X"010", -- 0x024: XOUT (0x01), R00 - "111011" & X"115", -- 0x025: CALL 0x115 - "000011" & X"070", -- 0x026: MOV R00, 0x07 - "100100" & X"010", -- 0x027: XOUT (0x01), R00 - "111011" & X"12B", -- 0x028: CALL 0x12B - "000011" & X"080", -- 0x029: MOV R00, 0x08 - "100100" & X"010", -- 0x02A: XOUT (0x01), R00 - "111011" & X"137", -- 0x02B: CALL 0x137 - "000011" & X"090", -- 0x02C: MOV R00, 0x09 - "100100" & X"010", -- 0x02D: XOUT (0x01), R00 - "111011" & X"15A", -- 0x02E: CALL 0x15A - "000011" & X"0A0", -- 0x02F: MOV R00, 0x0A - "100100" & X"010", -- 0x030: XOUT (0x01), R00 - "111011" & X"22A", -- 0x031: CALL 0x22A - "000011" & X"0B0", -- 0x032: MOV R00, 0x0B - "100100" & X"010", -- 0x033: XOUT (0x01), R00 - "111011" & X"24D", -- 0x034: CALL 0x24D - "000011" & X"0C0", -- 0x035: MOV R00, 0x0C - "100100" & X"010", -- 0x036: XOUT (0x01), R00 - "111011" & X"278", -- 0x037: CALL 0x278 - "000011" & X"FF0", -- 0x038: MOV R00, 0xFF - "100100" & X"010", -- 0x039: XOUT (0x01), R00 - "110000" & X"2FF", -- 0x03A: JMP 0x2FF - "000011" & X"000", -- 0x03B: MOV R00, 0x00 - "000011" & X"001", -- 0x03C: MOV R01, 0x00 - "000011" & X"002", -- 0x03D: MOV R02, 0x00 - "000011" & X"003", -- 0x03E: MOV R03, 0x00 - "000011" & X"004", -- 0x03F: MOV R04, 0x00 - "000011" & X"005", -- 0x040: MOV R05, 0x00 - "000011" & X"006", -- 0x041: MOV R06, 0x00 - "000011" & X"007", -- 0x042: MOV R07, 0x00 - "000011" & X"008", -- 0x043: MOV R08, 0x00 - "000011" & X"009", -- 0x044: MOV R09, 0x00 - "000011" & X"00A", -- 0x045: MOV R10, 0x00 - "000011" & X"00B", -- 0x046: MOV R11, 0x00 - "000011" & X"00C", -- 0x047: MOV R12, 0x00 - "000011" & X"00D", -- 0x048: MOV R13, 0x00 - "000011" & X"00E", -- 0x049: MOV R14, 0x00 - "000011" & X"00F", -- 0x04A: MOV R15, 0x00 - "111110" & X"000", -- 0x04B: RET - "000011" & X"100", -- 0x04C: MOV R00, 0x10 - "001111" & X"100", -- 0x04D: CMP R00, 0x10 - "111010" & X"3FF", -- 0x04E: JNE 0x3FF - "010001" & X"010", -- 0x04F: ADD R00, 0x01 - "000010" & X"001", -- 0x050: MOV R01, R00 - "001111" & X"111", -- 0x051: CMP R01, 0x11 - "111010" & X"3FF", -- 0x052: JNE 0x3FF - "010001" & X"011", -- 0x053: ADD R01, 0x01 - "000010" & X"012", -- 0x054: MOV R02, R01 - "001111" & X"122", -- 0x055: CMP R02, 0x12 - "111010" & X"3FF", -- 0x056: JNE 0x3FF - "010001" & X"012", -- 0x057: ADD R02, 0x01 - "000010" & X"023", -- 0x058: MOV R03, R02 - "001111" & X"133", -- 0x059: CMP R03, 0x13 - "111010" & X"3FF", -- 0x05A: JNE 0x3FF - "010001" & X"013", -- 0x05B: ADD R03, 0x01 - "000010" & X"034", -- 0x05C: MOV R04, R03 - "001111" & X"144", -- 0x05D: CMP R04, 0x14 - "111010" & X"3FF", -- 0x05E: JNE 0x3FF - "010001" & X"014", -- 0x05F: ADD R04, 0x01 - "000010" & X"045", -- 0x060: MOV R05, R04 - "001111" & X"155", -- 0x061: CMP R05, 0x15 - "111010" & X"3FF", -- 0x062: JNE 0x3FF - "010001" & X"015", -- 0x063: ADD R05, 0x01 - "000010" & X"056", -- 0x064: MOV R06, R05 - "001111" & X"166", -- 0x065: CMP R06, 0x16 - "111010" & X"3FF", -- 0x066: JNE 0x3FF - "010001" & X"016", -- 0x067: ADD R06, 0x01 - "000010" & X"067", -- 0x068: MOV R07, R06 - "001111" & X"177", -- 0x069: CMP R07, 0x17 - "111010" & X"3FF", -- 0x06A: JNE 0x3FF - "010001" & X"017", -- 0x06B: ADD R07, 0x01 - "000010" & X"078", -- 0x06C: MOV R08, R07 - "001111" & X"188", -- 0x06D: CMP R08, 0x18 - "111010" & X"3FF", -- 0x06E: JNE 0x3FF - "010001" & X"018", -- 0x06F: ADD R08, 0x01 - "000010" & X"089", -- 0x070: MOV R09, R08 - "001111" & X"199", -- 0x071: CMP R09, 0x19 - "111010" & X"3FF", -- 0x072: JNE 0x3FF - "010001" & X"019", -- 0x073: ADD R09, 0x01 - "000010" & X"09A", -- 0x074: MOV R10, R09 - "001111" & X"1AA", -- 0x075: CMP R10, 0x1A - "111010" & X"3FF", -- 0x076: JNE 0x3FF - "010001" & X"01A", -- 0x077: ADD R10, 0x01 - "000010" & X"0AB", -- 0x078: MOV R11, R10 - "001111" & X"1BB", -- 0x079: CMP R11, 0x1B - "111010" & X"3FF", -- 0x07A: JNE 0x3FF - "010001" & X"01B", -- 0x07B: ADD R11, 0x01 - "000010" & X"0BC", -- 0x07C: MOV R12, R11 - "001111" & X"1CC", -- 0x07D: CMP R12, 0x1C - "111010" & X"3FF", -- 0x07E: JNE 0x3FF - "010001" & X"01C", -- 0x07F: ADD R12, 0x01 - "000010" & X"0CD", -- 0x080: MOV R13, R12 - "001111" & X"1DD", -- 0x081: CMP R13, 0x1D - "111010" & X"3FF", -- 0x082: JNE 0x3FF - "010001" & X"01D", -- 0x083: ADD R13, 0x01 - "000010" & X"0DE", -- 0x084: MOV R14, R13 - "001111" & X"1EE", -- 0x085: CMP R14, 0x1E - "111010" & X"3FF", -- 0x086: JNE 0x3FF - "010001" & X"01E", -- 0x087: ADD R14, 0x01 - "000010" & X"0EF", -- 0x088: MOV R15, R14 - "001111" & X"1FF", -- 0x089: CMP R15, 0x1F - "111010" & X"3FF", -- 0x08A: JNE 0x3FF - "010001" & X"01F", -- 0x08B: ADD R15, 0x01 - "111110" & X"000", -- 0x08C: RET - "000011" & X"000", -- 0x08D: MOV R00, 0x00 - "001111" & X"000", -- 0x08E: TST R00 - "110010" & X"3FF", -- 0x08F: JNZ 0x3FF - "110011" & X"3FF", -- 0x090: JC 0x3FF - "001111" & X"000", -- 0x091: CMP R00, 0x00 - "111010" & X"3FF", -- 0x092: JNE 0x3FF - "110101" & X"3FF", -- 0x093: JLT 0x3FF - "110110" & X"3FF", -- 0x094: JGT 0x3FF - "110111" & X"097", -- 0x095: JLE 0x097 - "110000" & X"3FF", -- 0x096: JMP 0x3FF - "111001" & X"099", -- 0x097: JEQ 0x099 - "110000" & X"3FF", -- 0x098: JMP 0x3FF - "111000" & X"09B", -- 0x099: JGE 0x09B - "110000" & X"3FF", -- 0x09A: JMP 0x3FF - "001111" & X"550", -- 0x09B: CMP R00, 0x55 - "111001" & X"3FF", -- 0x09C: JEQ 0x3FF - "110101" & X"09F", -- 0x09D: JLT 0x09F - "110000" & X"3FF", -- 0x09E: JMP 0x3FF - "110111" & X"0A1", -- 0x09F: JLE 0x0A1 - "110000" & X"3FF", -- 0x0A0: JMP 0x3FF - "111000" & X"3FF", -- 0x0A1: JGE 0x3FF - "110110" & X"3FF", -- 0x0A2: JGT 0x3FF - "000011" & X"550", -- 0x0A3: MOV R00, 0x55 - "001111" & X"000", -- 0x0A4: TST R00 - "110001" & X"3FF", -- 0x0A5: JZ 0x3FF - "110011" & X"3FF", -- 0x0A6: JC 0x3FF - "001111" & X"AA0", -- 0x0A7: CMP R00, 0xAA - "111001" & X"3FF", -- 0x0A8: JEQ 0x3FF - "111010" & X"0AB", -- 0x0A9: JNE 0x0AB - "110000" & X"3FF", -- 0x0AA: JMP 0x3FF - "110101" & X"0AD", -- 0x0AB: JLT 0x0AD - "110000" & X"3FF", -- 0x0AC: JMP 0x3FF - "110111" & X"0AF", -- 0x0AD: JLE 0x0AF - "110000" & X"3FF", -- 0x0AE: JMP 0x3FF - "110110" & X"3FF", -- 0x0AF: JGT 0x3FF - "001111" & X"550", -- 0x0B0: CMP R00, 0x55 - "111001" & X"0B3", -- 0x0B1: JEQ 0x0B3 - "110000" & X"3FF", -- 0x0B2: JMP 0x3FF - "111010" & X"3FF", -- 0x0B3: JNE 0x3FF - "110101" & X"3FF", -- 0x0B4: JLT 0x3FF - "110111" & X"0B7", -- 0x0B5: JLE 0x0B7 - "110000" & X"3FF", -- 0x0B6: JMP 0x3FF - "110110" & X"3FF", -- 0x0B7: JGT 0x3FF - "111000" & X"0BA", -- 0x0B8: JGE 0x0BA - "110000" & X"3FF", -- 0x0B9: JMP 0x3FF - "000011" & X"AA0", -- 0x0BA: MOV R00, 0xAA - "001111" & X"000", -- 0x0BB: TST R00 - "110001" & X"3FF", -- 0x0BC: JZ 0x3FF - "110011" & X"3FF", -- 0x0BD: JC 0x3FF - "001111" & X"550", -- 0x0BE: CMP R00, 0x55 - "111001" & X"3FF", -- 0x0BF: JEQ 0x3FF - "111010" & X"0C2", -- 0x0C0: JNE 0x0C2 - "110000" & X"3FF", -- 0x0C1: JMP 0x3FF - "110110" & X"0C4", -- 0x0C2: JGT 0x0C4 - "110000" & X"3FF", -- 0x0C3: JMP 0x3FF - "111000" & X"0C6", -- 0x0C4: JGE 0x0C6 - "110000" & X"3FF", -- 0x0C5: JMP 0x3FF - "110101" & X"3FF", -- 0x0C6: JLT 0x3FF - "110111" & X"3FF", -- 0x0C7: JLE 0x3FF - "111110" & X"000", -- 0x0C8: RET - "000011" & X"000", -- 0x0C9: MOV R00, 0x00 - "000011" & X"001", -- 0x0CA: MOV R01, 0x00 - "000010" & X"002", -- 0x0CB: MOV R02, R00 - "000010" & X"013", -- 0x0CC: MOV R03, R01 - "010001" & X"010", -- 0x0CD: ADD R00, 0x01 - "010011" & X"001", -- 0x0CE: ADDC R01, 0x00 - "010001" & X"012", -- 0x0CF: ADD R02, 0x01 - "001111" & X"002", -- 0x0D0: CMP R02, 0x00 - "111010" & X"0D4", -- 0x0D1: JNE 0x0D4 - "010001" & X"013", -- 0x0D2: ADD R03, 0x01 - "001111" & X"023", -- 0x0D3: CMP R03, 0x02 - "111010" & X"0CD", -- 0x0D4: JNE 0x0CD - "001110" & X"020", -- 0x0D5: CMP R00, R02 - "111010" & X"3FF", -- 0x0D6: JNE 0x3FF - "001110" & X"031", -- 0x0D7: CMP R01, R03 - "111010" & X"3FF", -- 0x0D8: JNE 0x3FF - "000011" & X"000", -- 0x0D9: MOV R00, 0x00 - "111110" & X"000", -- 0x0DA: RET - "000011" & X"000", -- 0x0DB: MOV R00, 0x00 - "000011" & X"031", -- 0x0DC: MOV R01, 0x03 - "000010" & X"002", -- 0x0DD: MOV R02, R00 - "000010" & X"013", -- 0x0DE: MOV R03, R01 - "010101" & X"010", -- 0x0DF: SUB R00, 0x01 - "010111" & X"001", -- 0x0E0: SUBC R01, 0x00 - "010101" & X"012", -- 0x0E1: SUB R02, 0x01 - "001111" & X"FF2", -- 0x0E2: CMP R02, 0xFF - "111010" & X"0E6", -- 0x0E3: JNE 0x0E6 - "010101" & X"013", -- 0x0E4: SUB R03, 0x01 - "001111" & X"003", -- 0x0E5: CMP R03, 0x00 - "111010" & X"0DF", -- 0x0E6: JNE 0x0DF - "001110" & X"020", -- 0x0E7: CMP R00, R02 - "111010" & X"3FF", -- 0x0E8: JNE 0x3FF - "001110" & X"031", -- 0x0E9: CMP R01, R03 - "111010" & X"3FF", -- 0x0EA: JNE 0x3FF - "000011" & X"000", -- 0x0EB: MOV R00, 0x00 - "111110" & X"000", -- 0x0EC: RET - "000011" & X"030", -- 0x0ED: MOV R00, 0x03 - "000011" & X"051", -- 0x0EE: MOV R01, 0x05 - "101110" & X"050", -- 0x0EF: SUB 0x05, R00 - "010101" & X"031", -- 0x0F0: SUB R01, 0x03 - "001110" & X"010", -- 0x0F1: CMP R00, R01 - "111010" & X"3FF", -- 0x0F2: JNE 0x3FF - "000011" & X"030", -- 0x0F3: MOV R00, 0x03 - "000011" & X"051", -- 0x0F4: MOV R01, 0x05 - "010100" & X"010", -- 0x0F5: SUB R00, R01 - "101111" & X"000", -- 0x0F6: SUBC 0x00, R00 - "001111" & X"010", -- 0x0F7: CMP R00, 0x01 - "111010" & X"3FF", -- 0x0F8: JNE 0x3FF - "010001" & X"000", -- 0x0F9: ADD R00, 0x00 - "010110" & X"001", -- 0x0FA: SUBC R01, R00 - "001111" & X"041", -- 0x0FB: CMP R01, 0x04 - "111010" & X"3FF", -- 0x0FC: JNE 0x3FF - "000011" & X"000", -- 0x0FD: MOV R00, 0x00 - "111110" & X"000", -- 0x0FE: RET - "000011" & X"010", -- 0x0FF: MOV R00, 0x01 - "001101" & X"5A0", -- 0x100: MOVC (0x5A), R00 - "010101" & X"010", -- 0x101: DEC R00 - "001101" & X"000", -- 0x102: MOVC (0x00), R00 - "001010" & X"5A1", -- 0x103: MOVC R01, (0x5A) - "001100" & X"A51", -- 0x104: MOVC (R01), 0xA5 - "001001" & X"010", -- 0x105: MOVC R00, (R01) - "001001" & X"011", -- 0x106: MOVC R01, (R01) - "010001" & X"5A1", -- 0x107: ADD R01, 0x5A - "001001" & X"010", -- 0x108: MOVC R00, (R01) - "001011" & X"000", -- 0x109: MOVC (R00), R00 - "001001" & X"002", -- 0x10A: MOVC R02, (R00) - "001110" & X"002", -- 0x10B: CMP R02, R00 - "111010" & X"3FF", -- 0x10C: JNE 0x3FF - "001011" & X"021", -- 0x10D: MOVC (R01), R02 - "001001" & X"022", -- 0x10E: MOVC R02, (R02) - "001110" & X"012", -- 0x10F: CMP R02, R01 - "111010" & X"3FF", -- 0x110: JNE 0x3FF - "010101" & X"011", -- 0x111: DEC R01 - "010001" & X"010", -- 0x112: INC R00 - "110010" & X"109", -- 0x113: JNZ 0x109 - "111110" & X"000", -- 0x114: RET - "000011" & X"010", -- 0x115: MOV R00, 0x01 - "001000" & X"600", -- 0x116: MOVX (0x60), R00 - "010101" & X"010", -- 0x117: DEC R00 - "001000" & X"060", -- 0x118: MOVX (0x06), R00 - "000101" & X"601", -- 0x119: MOVX R01, (0x60) - "000111" & X"A51", -- 0x11A: MOVX (R01), 0xA5 - "000100" & X"010", -- 0x11B: MOVX R00, (R01) - "000100" & X"011", -- 0x11C: MOVX R01, (R01) - "010001" & X"5A1", -- 0x11D: ADD R01, 0x5A - "000100" & X"010", -- 0x11E: MOVX R00, (R01) - "000110" & X"000", -- 0x11F: MOVX (R00), R00 - "000100" & X"002", -- 0x120: MOVX R02, (R00) - "001110" & X"002", -- 0x121: CMP R02, R00 - "111010" & X"3FF", -- 0x122: JNE 0x3FF - "000110" & X"021", -- 0x123: MOVX (R01), R02 - "000100" & X"022", -- 0x124: MOVX R02, (R02) - "001110" & X"012", -- 0x125: CMP R02, R01 - "111010" & X"3FF", -- 0x126: JNE 0x3FF - "010101" & X"011", -- 0x127: DEC R01 - "010001" & X"010", -- 0x128: INC R00 - "110010" & X"11F", -- 0x129: JNZ 0x11F - "111110" & X"000", -- 0x12A: RET - "000011" & X"AA0", -- 0x12B: MOV R00, 0xAA - "000011" & X"001", -- 0x12C: MOV R01, 0x00 - "111100" & X"000", -- 0x12D: PUSH R00 - "010001" & X"010", -- 0x12E: INC R00 - "010101" & X"011", -- 0x12F: DEC R01 - "110010" & X"12D", -- 0x130: JNZ 0x12D - "111101" & X"000", -- 0x131: POP R00 - "010101" & X"011", -- 0x132: DEC R01 - "110010" & X"131", -- 0x133: JNZ 0x131 - "001111" & X"AA0", -- 0x134: CMP R00, 0xAA - "111010" & X"3FF", -- 0x135: JNE 0x3FF - "111110" & X"000", -- 0x136: RET - "000011" & X"550", -- 0x137: MOV R00, 0x55 - "111100" & X"000", -- 0x138: PUSH R00 - "000011" & X"000", -- 0x139: MOV R00, 0x00 - "000011" & X"FF1", -- 0x13A: MOV R01, 0xFF - "111011" & X"151", -- 0x13B: CALL 0x151 - "111101" & X"000", -- 0x13C: POP R00 - "001111" & X"550", -- 0x13D: CMP R00, 0x55 - "111010" & X"3FF", -- 0x13E: JNE 0x3FF - "000011" & X"010", -- 0x13F: MOV R00, 0x01 - "000011" & X"481", -- 0x140: MOV R01, 0x48 - "100110" & X"050", -- 0x141: COUT (0x05), R00 - "111100" & X"001", -- 0x142: PUSH R01 - "000011" & X"000", -- 0x143: MOV R00, 0x00 - "000011" & X"3B1", -- 0x144: MOV R01, 0x3B - "100110" & X"050", -- 0x145: COUT (0x05), R00 - "111100" & X"001", -- 0x146: PUSH R01 - "111110" & X"000", -- 0x147: RET - "000011" & X"010", -- 0x148: MOV R00, 0x01 - "000011" & X"501", -- 0x149: MOV R01, 0x50 - "100110" & X"050", -- 0x14A: COUT (0x05), R00 - "111100" & X"001", -- 0x14B: PUSH R01 - "000011" & X"000", -- 0x14C: MOV R00, 0x00 - "000011" & X"3B1", -- 0x14D: MOV R01, 0x3B - "100110" & X"050", -- 0x14E: COUT (0x05), R00 - "111100" & X"001", -- 0x14F: PUSH R01 - "111110" & X"000", -- 0x150: RET - "001110" & X"010", -- 0x151: CMP R00, R01 - "111001" & X"155", -- 0x152: JEQ 0x155 - "010001" & X"010", -- 0x153: INC R00 - "110000" & X"158", -- 0x154: JMP 0x158 - "010101" & X"010", -- 0x155: DEC R00 - "010101" & X"011", -- 0x156: DEC R01 - "111110" & X"000", -- 0x157: RET - "111011" & X"151", -- 0x158: CALL 0x151 - "110000" & X"155", -- 0x159: JMP 0x155 - "000011" & X"A50", -- 0x15A: MOV R00, 0xA5 - "000011" & X"5A1", -- 0x15B: MOV R01, 0x5A - "101010" & X"000", -- 0x15C: SWAP R00 - "001111" & X"5A0", -- 0x15D: CMP R00, 0x5A - "111010" & X"3FF", -- 0x15E: JNE 0x3FF - "101010" & X"000", -- 0x15F: SWAP R00 - "001111" & X"A50", -- 0x160: CMP R00, 0xA5 - "111010" & X"3FF", -- 0x161: JNE 0x3FF - "000011" & X"D20", -- 0x162: MOV R00, 0xD2 - "101010" & X"000", -- 0x163: SWAP R00 - "001111" & X"2D0", -- 0x164: CMP R00, 0x2D - "111010" & X"3FF", -- 0x165: JNE 0x3FF - "101010" & X"001", -- 0x166: SWAP R01 - "001111" & X"2D0", -- 0x167: CMP R00, 0x2D - "111010" & X"3FF", -- 0x168: JNE 0x3FF - "001111" & X"A51", -- 0x169: CMP R01, 0xA5 - "111010" & X"3FF", -- 0x16A: JNE 0x3FF - "000011" & X"2D0", -- 0x16B: MOV R00, 0x2D - "011110" & X"000", -- 0x16C: SHL R00 - "001111" & X"5A0", -- 0x16D: CMP R00, 0x5A - "111010" & X"3FF", -- 0x16E: JNE 0x3FF - "011110" & X"000", -- 0x16F: SHL R00 - "001111" & X"B40", -- 0x170: CMP R00, 0xB4 - "111010" & X"3FF", -- 0x171: JNE 0x3FF - "011110" & X"000", -- 0x172: SHL R00 - "001111" & X"680", -- 0x173: CMP R00, 0x68 - "111010" & X"3FF", -- 0x174: JNE 0x3FF - "011110" & X"000", -- 0x175: SHL R00 - "001111" & X"D00", -- 0x176: CMP R00, 0xD0 - "111010" & X"3FF", -- 0x177: JNE 0x3FF - "011110" & X"000", -- 0x178: SHL R00 - "001111" & X"A00", -- 0x179: CMP R00, 0xA0 - "111010" & X"3FF", -- 0x17A: JNE 0x3FF - "011110" & X"000", -- 0x17B: SHL R00 - "001111" & X"400", -- 0x17C: CMP R00, 0x40 - "111010" & X"3FF", -- 0x17D: JNE 0x3FF - "011110" & X"000", -- 0x17E: SHL R00 - "001111" & X"800", -- 0x17F: CMP R00, 0x80 - "111010" & X"3FF", -- 0x180: JNE 0x3FF - "011110" & X"000", -- 0x181: SHL R00 - "001111" & X"000", -- 0x182: CMP R00, 0x00 - "111010" & X"3FF", -- 0x183: JNE 0x3FF - "000011" & X"841", -- 0x184: MOV R01, 0x84 - "011111" & X"001", -- 0x185: SHR R01 - "001111" & X"421", -- 0x186: CMP R01, 0x42 - "111010" & X"3FF", -- 0x187: JNE 0x3FF - "011111" & X"001", -- 0x188: SHR R01 - "001111" & X"211", -- 0x189: CMP R01, 0x21 - "111010" & X"3FF", -- 0x18A: JNE 0x3FF - "011111" & X"001", -- 0x18B: SHR R01 - "001111" & X"101", -- 0x18C: CMP R01, 0x10 - "111010" & X"3FF", -- 0x18D: JNE 0x3FF - "011111" & X"001", -- 0x18E: SHR R01 - "001111" & X"081", -- 0x18F: CMP R01, 0x08 - "111010" & X"3FF", -- 0x190: JNE 0x3FF - "011111" & X"001", -- 0x191: SHR R01 - "001111" & X"041", -- 0x192: CMP R01, 0x04 - "111010" & X"3FF", -- 0x193: JNE 0x3FF - "011111" & X"001", -- 0x194: SHR R01 - "001111" & X"021", -- 0x195: CMP R01, 0x02 - "111010" & X"3FF", -- 0x196: JNE 0x3FF - "011111" & X"001", -- 0x197: SHR R01 - "001111" & X"011", -- 0x198: CMP R01, 0x01 - "111010" & X"3FF", -- 0x199: JNE 0x3FF - "011111" & X"001", -- 0x19A: SHR R01 - "001111" & X"001", -- 0x19B: CMP R01, 0x00 - "111010" & X"3FF", -- 0x19C: JNE 0x3FF - "000011" & X"C50", -- 0x19D: MOV R00, 0xC5 - "100000" & X"000", -- 0x19E: ROL R00 - "001111" & X"8B0", -- 0x19F: CMP R00, 0x8B - "111010" & X"3FF", -- 0x1A0: JNE 0x3FF - "100000" & X"000", -- 0x1A1: ROL R00 - "001111" & X"170", -- 0x1A2: CMP R00, 0x17 - "111010" & X"3FF", -- 0x1A3: JNE 0x3FF - "100000" & X"000", -- 0x1A4: ROL R00 - "001111" & X"2E0", -- 0x1A5: CMP R00, 0x2E - "111010" & X"3FF", -- 0x1A6: JNE 0x3FF - "100000" & X"000", -- 0x1A7: ROL R00 - "001111" & X"5C0", -- 0x1A8: CMP R00, 0x5C - "111010" & X"3FF", -- 0x1A9: JNE 0x3FF - "100000" & X"000", -- 0x1AA: ROL R00 - "001111" & X"B80", -- 0x1AB: CMP R00, 0xB8 - "111010" & X"3FF", -- 0x1AC: JNE 0x3FF - "100000" & X"000", -- 0x1AD: ROL R00 - "001111" & X"710", -- 0x1AE: CMP R00, 0x71 - "111010" & X"3FF", -- 0x1AF: JNE 0x3FF - "100000" & X"000", -- 0x1B0: ROL R00 - "001111" & X"E20", -- 0x1B1: CMP R00, 0xE2 - "111010" & X"3FF", -- 0x1B2: JNE 0x3FF - "100000" & X"000", -- 0x1B3: ROL R00 - "001111" & X"C50", -- 0x1B4: CMP R00, 0xC5 - "111010" & X"3FF", -- 0x1B5: JNE 0x3FF - "000011" & X"631", -- 0x1B6: MOV R01, 0x63 - "100001" & X"001", -- 0x1B7: ROR R01 - "001111" & X"B11", -- 0x1B8: CMP R01, 0xB1 - "111010" & X"3FF", -- 0x1B9: JNE 0x3FF - "100001" & X"001", -- 0x1BA: ROR R01 - "001111" & X"D81", -- 0x1BB: CMP R01, 0xD8 - "111010" & X"3FF", -- 0x1BC: JNE 0x3FF - "100001" & X"001", -- 0x1BD: ROR R01 - "001111" & X"6C1", -- 0x1BE: CMP R01, 0x6C - "111010" & X"3FF", -- 0x1BF: JNE 0x3FF - "100001" & X"001", -- 0x1C0: ROR R01 - "001111" & X"361", -- 0x1C1: CMP R01, 0x36 - "111010" & X"3FF", -- 0x1C2: JNE 0x3FF - "100001" & X"001", -- 0x1C3: ROR R01 - "001111" & X"1B1", -- 0x1C4: CMP R01, 0x1B - "111010" & X"3FF", -- 0x1C5: JNE 0x3FF - "100001" & X"001", -- 0x1C6: ROR R01 - "001111" & X"8D1", -- 0x1C7: CMP R01, 0x8D - "111010" & X"3FF", -- 0x1C8: JNE 0x3FF - "100001" & X"001", -- 0x1C9: ROR R01 - "001111" & X"C61", -- 0x1CA: CMP R01, 0xC6 - "111010" & X"3FF", -- 0x1CB: JNE 0x3FF - "100001" & X"001", -- 0x1CC: ROR R01 - "001111" & X"631", -- 0x1CD: CMP R01, 0x63 - "111010" & X"3FF", -- 0x1CE: JNE 0x3FF - "011100" & X"000", -- 0x1CF: XOR R00, R00 - "000011" & X"C50", -- 0x1D0: MOV R00, 0xC5 - "100010" & X"000", -- 0x1D1: ROLC R00 - "111100" & X"000", -- 0x1D2: PUSH R00 - "100010" & X"000", -- 0x1D3: ROLC R00 - "111100" & X"000", -- 0x1D4: PUSH R00 - "100010" & X"000", -- 0x1D5: ROLC R00 - "111100" & X"000", -- 0x1D6: PUSH R00 - "100010" & X"000", -- 0x1D7: ROLC R00 - "111100" & X"000", -- 0x1D8: PUSH R00 - "100010" & X"000", -- 0x1D9: ROLC R00 - "111100" & X"000", -- 0x1DA: PUSH R00 - "100010" & X"000", -- 0x1DB: ROLC R00 - "111100" & X"000", -- 0x1DC: PUSH R00 - "100010" & X"000", -- 0x1DD: ROLC R00 - "111100" & X"000", -- 0x1DE: PUSH R00 - "100010" & X"000", -- 0x1DF: ROLC R00 - "111100" & X"000", -- 0x1E0: PUSH R00 - "100010" & X"000", -- 0x1E1: ROLC R00 - "001111" & X"C50", -- 0x1E2: CMP R00, 0xC5 - "111010" & X"3FF", -- 0x1E3: JNE 0x3FF - "111101" & X"000", -- 0x1E4: POP R00 - "001111" & X"620", -- 0x1E5: CMP R00, 0x62 - "111010" & X"3FF", -- 0x1E6: JNE 0x3FF - "111101" & X"000", -- 0x1E7: POP R00 - "001111" & X"B10", -- 0x1E8: CMP R00, 0xB1 - "111010" & X"3FF", -- 0x1E9: JNE 0x3FF - "111101" & X"000", -- 0x1EA: POP R00 - "001111" & X"580", -- 0x1EB: CMP R00, 0x58 - "111010" & X"3FF", -- 0x1EC: JNE 0x3FF - "111101" & X"000", -- 0x1ED: POP R00 - "001111" & X"AC0", -- 0x1EE: CMP R00, 0xAC - "111010" & X"3FF", -- 0x1EF: JNE 0x3FF - "111101" & X"000", -- 0x1F0: POP R00 - "001111" & X"560", -- 0x1F1: CMP R00, 0x56 - "111010" & X"3FF", -- 0x1F2: JNE 0x3FF - "111101" & X"000", -- 0x1F3: POP R00 - "001111" & X"2B0", -- 0x1F4: CMP R00, 0x2B - "111010" & X"3FF", -- 0x1F5: JNE 0x3FF - "111101" & X"000", -- 0x1F6: POP R00 - "001111" & X"150", -- 0x1F7: CMP R00, 0x15 - "111010" & X"3FF", -- 0x1F8: JNE 0x3FF - "111101" & X"000", -- 0x1F9: POP R00 - "001111" & X"8A0", -- 0x1FA: CMP R00, 0x8A - "111010" & X"3FF", -- 0x1FB: JNE 0x3FF - "011100" & X"011", -- 0x1FC: XOR R01, R01 - "000011" & X"631", -- 0x1FD: MOV R01, 0x63 - "100011" & X"001", -- 0x1FE: RORC R01 - "111100" & X"001", -- 0x1FF: PUSH R01 - "100011" & X"001", -- 0x200: RORC R01 - "111100" & X"001", -- 0x201: PUSH R01 - "100011" & X"001", -- 0x202: RORC R01 - "111100" & X"001", -- 0x203: PUSH R01 - "100011" & X"001", -- 0x204: RORC R01 - "111100" & X"001", -- 0x205: PUSH R01 - "100011" & X"001", -- 0x206: RORC R01 - "111100" & X"001", -- 0x207: PUSH R01 - "100011" & X"001", -- 0x208: RORC R01 - "111100" & X"001", -- 0x209: PUSH R01 - "100011" & X"001", -- 0x20A: RORC R01 - "111100" & X"001", -- 0x20B: PUSH R01 - "100011" & X"001", -- 0x20C: RORC R01 - "111100" & X"001", -- 0x20D: PUSH R01 - "100011" & X"001", -- 0x20E: RORC R01 - "001111" & X"631", -- 0x20F: CMP R01, 0x63 - "111010" & X"3FF", -- 0x210: JNE 0x3FF - "111101" & X"001", -- 0x211: POP R01 - "001111" & X"C61", -- 0x212: CMP R01, 0xC6 - "111010" & X"3FF", -- 0x213: JNE 0x3FF - "111101" & X"001", -- 0x214: POP R01 - "001111" & X"8C1", -- 0x215: CMP R01, 0x8C - "111010" & X"3FF", -- 0x216: JNE 0x3FF - "111101" & X"001", -- 0x217: POP R01 - "001111" & X"191", -- 0x218: CMP R01, 0x19 - "111010" & X"3FF", -- 0x219: JNE 0x3FF - "111101" & X"001", -- 0x21A: POP R01 - "001111" & X"331", -- 0x21B: CMP R01, 0x33 - "111010" & X"3FF", -- 0x21C: JNE 0x3FF - "111101" & X"001", -- 0x21D: POP R01 - "001111" & X"661", -- 0x21E: CMP R01, 0x66 - "111010" & X"3FF", -- 0x21F: JNE 0x3FF - "111101" & X"001", -- 0x220: POP R01 - "001111" & X"CC1", -- 0x221: CMP R01, 0xCC - "111010" & X"3FF", -- 0x222: JNE 0x3FF - "111101" & X"001", -- 0x223: POP R01 - "001111" & X"981", -- 0x224: CMP R01, 0x98 - "111010" & X"3FF", -- 0x225: JNE 0x3FF - "111101" & X"001", -- 0x226: POP R01 - "001111" & X"311", -- 0x227: CMP R01, 0x31 - "111010" & X"3FF", -- 0x228: JNE 0x3FF - "111110" & X"000", -- 0x229: RET - "000011" & X"A50", -- 0x22A: MOV R00, 0xA5 - "101010" & X"000", -- 0x22B: SWAP R00 - "111100" & X"000", -- 0x22C: PUSH R00 - "011001" & X"0F0", -- 0x22D: AND R00, 0x0F - "001111" & X"0A0", -- 0x22E: CMP R00, 0x0A - "111010" & X"3FF", -- 0x22F: JNE 0x3FF - "111101" & X"000", -- 0x230: POP R00 - "111100" & X"000", -- 0x231: PUSH R00 - "011001" & X"0F0", -- 0x232: AND R00, 0x0F - "001111" & X"0A0", -- 0x233: CMP R00, 0x0A - "111101" & X"001", -- 0x234: POP R01 - "111010" & X"3FF", -- 0x235: JNE 0x3FF - "101010" & X"001", -- 0x236: SWAP R01 - "000011" & X"0F2", -- 0x237: MOV R02, 0x0F - "011000" & X"021", -- 0x238: AND R01, R02 - "001111" & X"051", -- 0x239: CMP R01, 0x05 - "111010" & X"3FF", -- 0x23A: JNE 0x3FF - "000011" & X"050", -- 0x23B: MOV R00, 0x05 - "000011" & X"A02", -- 0x23C: MOV R02, 0xA0 - "101010" & X"000", -- 0x23D: SWAP R00 - "011010" & X"002", -- 0x23E: OR R02, R00 - "001111" & X"F02", -- 0x23F: CMP R02, 0xF0 - "111010" & X"3FF", -- 0x240: JNE 0x3FF - "101010" & X"000", -- 0x241: SWAP R00 - "011011" & X"500", -- 0x242: OR R00, 0x50 - "001111" & X"550", -- 0x243: CMP R00, 0x55 - "111010" & X"3FF", -- 0x244: JNE 0x3FF - "000011" & X"011", -- 0x245: MOV R01, 0x01 - "000011" & X"010", -- 0x246: MOV R00, 0x01 - "011101" & X"010", -- 0x247: XOR R00, 0x01 - "110010" & X"3FF", -- 0x248: JNZ 0x3FF - "011100" & X"010", -- 0x249: XOR R00, R01 - "001111" & X"010", -- 0x24A: CMP R00, 0x01 - "111010" & X"3FF", -- 0x24B: JNE 0x3FF - "111110" & X"000", -- 0x24C: RET - "000011" & X"030", -- 0x24D: MOV R00, 0x03 - "100110" & X"030", -- 0x24E: COUT (0x03), R00 - "101000" & X"020", -- 0x24F: XIN R00, (0x02) - "011011" & X"010", -- 0x250: OR R00, 0x01 - "100100" & X"020", -- 0x251: XOUT (0x02), R00 - "000000" & X"000", -- 0x252: NOP - "000000" & X"000", -- 0x253: NOP - "000000" & X"000", -- 0x254: NOP - "000000" & X"000", -- 0x255: NOP - "000000" & X"000", -- 0x256: NOP - "000000" & X"000", -- 0x257: NOP - "101000" & X"020", -- 0x258: XIN R00, (0x02) - "011001" & X"FE0", -- 0x259: AND R00, 0xFE - "100100" & X"020", -- 0x25A: XOUT (0x02), R00 - "000000" & X"000", -- 0x25B: NOP - "000000" & X"000", -- 0x25C: NOP - "000000" & X"000", -- 0x25D: NOP - "000000" & X"000", -- 0x25E: NOP - "101001" & X"030", -- 0x25F: CIN R00, (0x03) - "011011" & X"800", -- 0x260: OR R00, 0x80 - "100110" & X"030", -- 0x261: COUT (0x03), R00 - "000000" & X"000", -- 0x262: NOP - "101001" & X"030", -- 0x263: CIN R00, (0x03) - "011011" & X"800", -- 0x264: OR R00, 0x80 - "100110" & X"030", -- 0x265: COUT (0x03), R00 - "000000" & X"000", -- 0x266: NOP - "101001" & X"030", -- 0x267: CIN R00, (0x03) - "011011" & X"800", -- 0x268: OR R00, 0x80 - "100110" & X"030", -- 0x269: COUT (0x03), R00 - "000000" & X"000", -- 0x26A: NOP - "101001" & X"030", -- 0x26B: CIN R00, (0x03) - "011011" & X"800", -- 0x26C: OR R00, 0x80 - "100110" & X"030", -- 0x26D: COUT (0x03), R00 - "000000" & X"000", -- 0x26E: NOP - "000000" & X"000", -- 0x26F: NOP - "000000" & X"000", -- 0x270: NOP - "000000" & X"000", -- 0x271: NOP - "000000" & X"000", -- 0x272: NOP - "000000" & X"000", -- 0x273: NOP - "000000" & X"000", -- 0x274: NOP - "000000" & X"000", -- 0x275: NOP - "000000" & X"000", -- 0x276: NOP - "111110" & X"000", -- 0x277: RET - "010101" & X"000", -- 0x278: SUB R00, 0x00 - "110011" & X"3FF", -- 0x279: JC 0x3FF - "101011" & X"000", -- 0x27A: SETC - "110100" & X"3FF", -- 0x27B: JNC 0x3FF - "000000" & X"000", -- 0x27C: NOP - "010101" & X"000", -- 0x27D: SUB R00, 0x00 - "110011" & X"3FF", -- 0x27E: JC 0x3FF - "000011" & X"000", -- 0x27F: MOV R00, 0x00 - "010101" & X"000", -- 0x280: CLRC - "110011" & X"3FF", -- 0x281: JC 0x3FF - "101011" & X"000", -- 0x282: SETC - "110100" & X"3FF", -- 0x283: JNC 0x3FF - "000000" & X"000", -- 0x284: NOP - "010101" & X"000", -- 0x285: CLRC - "110011" & X"3FF", -- 0x286: JC 0x3FF - "111110" & X"000", -- 0x287: RET - "010001" & X"01E", -- 0x288: INC R14 - "111111" & X"000", -- 0x289: RETI - "000000" & X"000", -- 0x28A: - "000000" & X"000", -- 0x28B: - "000000" & X"000", -- 0x28C: - "000000" & X"000", -- 0x28D: - "000000" & X"000", -- 0x28E: - "000000" & X"000", -- 0x28F: - "000000" & X"000", -- 0x290: - "000000" & X"000", -- 0x291: - "000000" & X"000", -- 0x292: - "000000" & X"000", -- 0x293: - "000000" & X"000", -- 0x294: - "000000" & X"000", -- 0x295: - "000000" & X"000", -- 0x296: - "000000" & X"000", -- 0x297: - "000000" & X"000", -- 0x298: - "000000" & X"000", -- 0x299: - "000000" & X"000", -- 0x29A: - "000000" & X"000", -- 0x29B: - "000000" & X"000", -- 0x29C: - "000000" & X"000", -- 0x29D: - "000000" & X"000", -- 0x29E: - "000000" & X"000", -- 0x29F: - "000000" & X"000", -- 0x2A0: - "000000" & X"000", -- 0x2A1: - "000000" & X"000", -- 0x2A2: - "000000" & X"000", -- 0x2A3: - "000000" & X"000", -- 0x2A4: - "000000" & X"000", -- 0x2A5: - "000000" & X"000", -- 0x2A6: - "000000" & X"000", -- 0x2A7: - "000000" & X"000", -- 0x2A8: - "000000" & X"000", -- 0x2A9: - "000000" & X"000", -- 0x2AA: - "000000" & X"000", -- 0x2AB: - "000000" & X"000", -- 0x2AC: - "000000" & X"000", -- 0x2AD: - "000000" & X"000", -- 0x2AE: - "000000" & X"000", -- 0x2AF: - "000000" & X"000", -- 0x2B0: - "000000" & X"000", -- 0x2B1: - "000000" & X"000", -- 0x2B2: - "000000" & X"000", -- 0x2B3: - "000000" & X"000", -- 0x2B4: - "000000" & X"000", -- 0x2B5: - "000000" & X"000", -- 0x2B6: - "000000" & X"000", -- 0x2B7: - "000000" & X"000", -- 0x2B8: - "000000" & X"000", -- 0x2B9: - "000000" & X"000", -- 0x2BA: - "000000" & X"000", -- 0x2BB: - "000000" & X"000", -- 0x2BC: - "000000" & X"000", -- 0x2BD: - "000000" & X"000", -- 0x2BE: - "000000" & X"000", -- 0x2BF: - "000000" & X"000", -- 0x2C0: - "000000" & X"000", -- 0x2C1: - "000000" & X"000", -- 0x2C2: - "000000" & X"000", -- 0x2C3: - "000000" & X"000", -- 0x2C4: - "000000" & X"000", -- 0x2C5: - "000000" & X"000", -- 0x2C6: - "000000" & X"000", -- 0x2C7: - "000000" & X"000", -- 0x2C8: - "000000" & X"000", -- 0x2C9: - "000000" & X"000", -- 0x2CA: - "000000" & X"000", -- 0x2CB: - "000000" & X"000", -- 0x2CC: - "000000" & X"000", -- 0x2CD: - "000000" & X"000", -- 0x2CE: - "000000" & X"000", -- 0x2CF: - "000000" & X"000", -- 0x2D0: - "000000" & X"000", -- 0x2D1: - "000000" & X"000", -- 0x2D2: - "000000" & X"000", -- 0x2D3: - "000000" & X"000", -- 0x2D4: - "000000" & X"000", -- 0x2D5: - "000000" & X"000", -- 0x2D6: - "000000" & X"000", -- 0x2D7: - "000000" & X"000", -- 0x2D8: - "000000" & X"000", -- 0x2D9: - "000000" & X"000", -- 0x2DA: - "000000" & X"000", -- 0x2DB: - "000000" & X"000", -- 0x2DC: - "000000" & X"000", -- 0x2DD: - "000000" & X"000", -- 0x2DE: - "000000" & X"000", -- 0x2DF: - "000000" & X"000", -- 0x2E0: - "000000" & X"000", -- 0x2E1: - "000000" & X"000", -- 0x2E2: - "000000" & X"000", -- 0x2E3: - "000000" & X"000", -- 0x2E4: - "000000" & X"000", -- 0x2E5: - "000000" & X"000", -- 0x2E6: - "000000" & X"000", -- 0x2E7: - "000000" & X"000", -- 0x2E8: - "000000" & X"000", -- 0x2E9: - "000000" & X"000", -- 0x2EA: - "000000" & X"000", -- 0x2EB: - "000000" & X"000", -- 0x2EC: - "000000" & X"000", -- 0x2ED: - "000000" & X"000", -- 0x2EE: - "000000" & X"000", -- 0x2EF: - "000000" & X"000", -- 0x2F0: - "000000" & X"000", -- 0x2F1: - "000000" & X"000", -- 0x2F2: - "000000" & X"000", -- 0x2F3: - "000000" & X"000", -- 0x2F4: - "000000" & X"000", -- 0x2F5: - "000000" & X"000", -- 0x2F6: - "000000" & X"000", -- 0x2F7: - "000000" & X"000", -- 0x2F8: - "000000" & X"000", -- 0x2F9: - "000000" & X"000", -- 0x2FA: - "000000" & X"000", -- 0x2FB: - "000000" & X"000", -- 0x2FC: - "000000" & X"000", -- 0x2FD: - "000000" & X"000", -- 0x2FE: - "110000" & X"2FF", -- 0x2FF: JMP 0x2FF - "000000" & X"000", -- 0x300: - "000000" & X"000", -- 0x301: - "000000" & X"000", -- 0x302: - "000000" & X"000", -- 0x303: - "000000" & X"000", -- 0x304: - "000000" & X"000", -- 0x305: - "000000" & X"000", -- 0x306: - "000000" & X"000", -- 0x307: - "000000" & X"000", -- 0x308: - "000000" & X"000", -- 0x309: - "000000" & X"000", -- 0x30A: - "000000" & X"000", -- 0x30B: - "000000" & X"000", -- 0x30C: - "000000" & X"000", -- 0x30D: - "000000" & X"000", -- 0x30E: - "000000" & X"000", -- 0x30F: - "000000" & X"000", -- 0x310: - "000000" & X"000", -- 0x311: - "000000" & X"000", -- 0x312: - "000000" & X"000", -- 0x313: - "000000" & X"000", -- 0x314: - "000000" & X"000", -- 0x315: - "000000" & X"000", -- 0x316: - "000000" & X"000", -- 0x317: - "000000" & X"000", -- 0x318: - "000000" & X"000", -- 0x319: - "000000" & X"000", -- 0x31A: - "000000" & X"000", -- 0x31B: - "000000" & X"000", -- 0x31C: - "000000" & X"000", -- 0x31D: - "000000" & X"000", -- 0x31E: - "000000" & X"000", -- 0x31F: - "000000" & X"000", -- 0x320: - "000000" & X"000", -- 0x321: - "000000" & X"000", -- 0x322: - "000000" & X"000", -- 0x323: - "000000" & X"000", -- 0x324: - "000000" & X"000", -- 0x325: - "000000" & X"000", -- 0x326: - "000000" & X"000", -- 0x327: - "000000" & X"000", -- 0x328: - "000000" & X"000", -- 0x329: - "000000" & X"000", -- 0x32A: - "000000" & X"000", -- 0x32B: - "000000" & X"000", -- 0x32C: - "000000" & X"000", -- 0x32D: - "000000" & X"000", -- 0x32E: - "000000" & X"000", -- 0x32F: - "000000" & X"000", -- 0x330: - "000000" & X"000", -- 0x331: - "000000" & X"000", -- 0x332: - "000000" & X"000", -- 0x333: - "000000" & X"000", -- 0x334: - "000000" & X"000", -- 0x335: - "000000" & X"000", -- 0x336: - "000000" & X"000", -- 0x337: - "000000" & X"000", -- 0x338: - "000000" & X"000", -- 0x339: - "000000" & X"000", -- 0x33A: - "000000" & X"000", -- 0x33B: - "000000" & X"000", -- 0x33C: - "000000" & X"000", -- 0x33D: - "000000" & X"000", -- 0x33E: - "000000" & X"000", -- 0x33F: - "000000" & X"000", -- 0x340: - "000000" & X"000", -- 0x341: - "000000" & X"000", -- 0x342: - "000000" & X"000", -- 0x343: - "000000" & X"000", -- 0x344: - "000000" & X"000", -- 0x345: - "000000" & X"000", -- 0x346: - "000000" & X"000", -- 0x347: - "000000" & X"000", -- 0x348: - "000000" & X"000", -- 0x349: - "000000" & X"000", -- 0x34A: - "000000" & X"000", -- 0x34B: - "000000" & X"000", -- 0x34C: - "000000" & X"000", -- 0x34D: - "000000" & X"000", -- 0x34E: - "000000" & X"000", -- 0x34F: - "000000" & X"000", -- 0x350: - "000000" & X"000", -- 0x351: - "000000" & X"000", -- 0x352: - "000000" & X"000", -- 0x353: - "000000" & X"000", -- 0x354: - "000000" & X"000", -- 0x355: - "000000" & X"000", -- 0x356: - "000000" & X"000", -- 0x357: - "000000" & X"000", -- 0x358: - "000000" & X"000", -- 0x359: - "000000" & X"000", -- 0x35A: - "000000" & X"000", -- 0x35B: - "000000" & X"000", -- 0x35C: - "000000" & X"000", -- 0x35D: - "000000" & X"000", -- 0x35E: - "000000" & X"000", -- 0x35F: - "000000" & X"000", -- 0x360: - "000000" & X"000", -- 0x361: - "000000" & X"000", -- 0x362: - "000000" & X"000", -- 0x363: - "000000" & X"000", -- 0x364: - "000000" & X"000", -- 0x365: - "000000" & X"000", -- 0x366: - "000000" & X"000", -- 0x367: - "000000" & X"000", -- 0x368: - "000000" & X"000", -- 0x369: - "000000" & X"000", -- 0x36A: - "000000" & X"000", -- 0x36B: - "000000" & X"000", -- 0x36C: - "000000" & X"000", -- 0x36D: - "000000" & X"000", -- 0x36E: - "000000" & X"000", -- 0x36F: - "000000" & X"000", -- 0x370: - "000000" & X"000", -- 0x371: - "000000" & X"000", -- 0x372: - "000000" & X"000", -- 0x373: - "000000" & X"000", -- 0x374: - "000000" & X"000", -- 0x375: - "000000" & X"000", -- 0x376: - "000000" & X"000", -- 0x377: - "000000" & X"000", -- 0x378: - "000000" & X"000", -- 0x379: - "000000" & X"000", -- 0x37A: - "000000" & X"000", -- 0x37B: - "000000" & X"000", -- 0x37C: - "000000" & X"000", -- 0x37D: - "000000" & X"000", -- 0x37E: - "000000" & X"000", -- 0x37F: - "000000" & X"000", -- 0x380: - "000000" & X"000", -- 0x381: - "000000" & X"000", -- 0x382: - "000000" & X"000", -- 0x383: - "000000" & X"000", -- 0x384: - "000000" & X"000", -- 0x385: - "000000" & X"000", -- 0x386: - "000000" & X"000", -- 0x387: - "000000" & X"000", -- 0x388: - "000000" & X"000", -- 0x389: - "000000" & X"000", -- 0x38A: - "000000" & X"000", -- 0x38B: - "000000" & X"000", -- 0x38C: - "000000" & X"000", -- 0x38D: - "000000" & X"000", -- 0x38E: - "000000" & X"000", -- 0x38F: - "000000" & X"000", -- 0x390: - "000000" & X"000", -- 0x391: - "000000" & X"000", -- 0x392: - "000000" & X"000", -- 0x393: - "000000" & X"000", -- 0x394: - "000000" & X"000", -- 0x395: - "000000" & X"000", -- 0x396: - "000000" & X"000", -- 0x397: - "000000" & X"000", -- 0x398: - "000000" & X"000", -- 0x399: - "000000" & X"000", -- 0x39A: - "000000" & X"000", -- 0x39B: - "000000" & X"000", -- 0x39C: - "000000" & X"000", -- 0x39D: - "000000" & X"000", -- 0x39E: - "000000" & X"000", -- 0x39F: - "000000" & X"000", -- 0x3A0: - "000000" & X"000", -- 0x3A1: - "000000" & X"000", -- 0x3A2: - "000000" & X"000", -- 0x3A3: - "000000" & X"000", -- 0x3A4: - "000000" & X"000", -- 0x3A5: - "000000" & X"000", -- 0x3A6: - "000000" & X"000", -- 0x3A7: - "000000" & X"000", -- 0x3A8: - "000000" & X"000", -- 0x3A9: - "000000" & X"000", -- 0x3AA: - "000000" & X"000", -- 0x3AB: - "000000" & X"000", -- 0x3AC: - "000000" & X"000", -- 0x3AD: - "000000" & X"000", -- 0x3AE: - "000000" & X"000", -- 0x3AF: - "000000" & X"000", -- 0x3B0: - "000000" & X"000", -- 0x3B1: - "000000" & X"000", -- 0x3B2: - "000000" & X"000", -- 0x3B3: - "000000" & X"000", -- 0x3B4: - "000000" & X"000", -- 0x3B5: - "000000" & X"000", -- 0x3B6: - "000000" & X"000", -- 0x3B7: - "000000" & X"000", -- 0x3B8: - "000000" & X"000", -- 0x3B9: - "000000" & X"000", -- 0x3BA: - "000000" & X"000", -- 0x3BB: - "000000" & X"000", -- 0x3BC: - "000000" & X"000", -- 0x3BD: - "000000" & X"000", -- 0x3BE: - "000000" & X"000", -- 0x3BF: - "000000" & X"000", -- 0x3C0: - "000000" & X"000", -- 0x3C1: - "000000" & X"000", -- 0x3C2: - "000000" & X"000", -- 0x3C3: - "000000" & X"000", -- 0x3C4: - "000000" & X"000", -- 0x3C5: - "000000" & X"000", -- 0x3C6: - "000000" & X"000", -- 0x3C7: - "000000" & X"000", -- 0x3C8: - "000000" & X"000", -- 0x3C9: - "000000" & X"000", -- 0x3CA: - "000000" & X"000", -- 0x3CB: - "000000" & X"000", -- 0x3CC: - "000000" & X"000", -- 0x3CD: - "000000" & X"000", -- 0x3CE: - "000000" & X"000", -- 0x3CF: - "000000" & X"000", -- 0x3D0: - "000000" & X"000", -- 0x3D1: - "000000" & X"000", -- 0x3D2: - "000000" & X"000", -- 0x3D3: - "000000" & X"000", -- 0x3D4: - "000000" & X"000", -- 0x3D5: - "000000" & X"000", -- 0x3D6: - "000000" & X"000", -- 0x3D7: - "000000" & X"000", -- 0x3D8: - "000000" & X"000", -- 0x3D9: - "000000" & X"000", -- 0x3DA: - "000000" & X"000", -- 0x3DB: - "000000" & X"000", -- 0x3DC: - "000000" & X"000", -- 0x3DD: - "000000" & X"000", -- 0x3DE: - "000000" & X"000", -- 0x3DF: - "000000" & X"000", -- 0x3E0: - "000000" & X"000", -- 0x3E1: - "000000" & X"000", -- 0x3E2: - "000000" & X"000", -- 0x3E3: - "000000" & X"000", -- 0x3E4: - "000000" & X"000", -- 0x3E5: - "000000" & X"000", -- 0x3E6: - "000000" & X"000", -- 0x3E7: - "000000" & X"000", -- 0x3E8: - "000000" & X"000", -- 0x3E9: - "000000" & X"000", -- 0x3EA: - "000000" & X"000", -- 0x3EB: - "000000" & X"000", -- 0x3EC: - "000000" & X"000", -- 0x3ED: - "000000" & X"000", -- 0x3EE: - "000000" & X"000", -- 0x3EF: - "000000" & X"000", -- 0x3F0: - "000000" & X"000", -- 0x3F1: - "000000" & X"000", -- 0x3F2: - "000000" & X"000", -- 0x3F3: - "000000" & X"000", -- 0x3F4: - "000000" & X"000", -- 0x3F5: - "000000" & X"000", -- 0x3F6: - "000000" & X"000", -- 0x3F7: - "000000" & X"000", -- 0x3F8: - "000000" & X"000", -- 0x3F9: - "000000" & X"000", -- 0x3FA: - "000000" & X"000", -- 0x3FB: - "000000" & X"000", -- 0x3FC: - "000000" & X"000", -- 0x3FD: - "000000" & X"000", -- 0x3FE: - "110000" & X"3FF" -- 0x3FF: JMP 0x3FF - ); - -begin - -PROM_READ: - process(clk, ce) - begin - if rising_edge(clk) and ce = '1' then - dout <= imem_rom(to_integer(addr)); - end if; - end process; - -end itest; - diff --git a/lib/CPUs/JCpu/src/itest_irom_ld.vhdl b/lib/CPUs/JCpu/src/itest_irom_ld.vhdl deleted file mode 100644 index d4371a1..0000000 --- a/lib/CPUs/JCpu/src/itest_irom_ld.vhdl +++ /dev/null @@ -1,1181 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: loadable ROM --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library UNISIM; -use UNISIM.VComponents.all; - -library work; -use work.cpu_pkg.all; - -ENTITY irom IS - Port ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - addr : in inst_addr_t; - dout : out inst_t - ); - -END irom; - -ARCHITECTURE loadable OF irom IS - - -- JASM_ROM_INSERT_HERE - - -- Assembled from itest.jsm - type imem_rom_t is array (0 to 1023) of inst_t; - signal imem_rom : imem_rom_t := - ( - "110000" & X"010", -- 0x000: JMP 0x010 - "110000" & X"288", -- 0x001: JMP 0x288 - "000000" & X"000", -- 0x002: - "000000" & X"000", -- 0x003: - "000000" & X"000", -- 0x004: - "000000" & X"000", -- 0x005: - "000000" & X"000", -- 0x006: - "000000" & X"000", -- 0x007: - "000000" & X"000", -- 0x008: - "000000" & X"000", -- 0x009: - "000000" & X"000", -- 0x00A: - "000000" & X"000", -- 0x00B: - "000000" & X"000", -- 0x00C: - "000000" & X"000", -- 0x00D: - "000000" & X"000", -- 0x00E: - "000000" & X"000", -- 0x00F: - "111011" & X"03B", -- 0x010: CALL 0x03B - "101001" & X"000", -- 0x011: CIN R00, (0x00) - "100100" & X"000", -- 0x012: XOUT (0x00), R00 - "111011" & X"04C", -- 0x013: CALL 0x04C - "000011" & X"010", -- 0x014: MOV R00, 0x01 - "100100" & X"010", -- 0x015: XOUT (0x01), R00 - "111011" & X"08D", -- 0x016: CALL 0x08D - "000011" & X"020", -- 0x017: MOV R00, 0x02 - "100100" & X"010", -- 0x018: XOUT (0x01), R00 - "111011" & X"0C9", -- 0x019: CALL 0x0C9 - "000011" & X"030", -- 0x01A: MOV R00, 0x03 - "100100" & X"010", -- 0x01B: XOUT (0x01), R00 - "111011" & X"0DB", -- 0x01C: CALL 0x0DB - "000011" & X"040", -- 0x01D: MOV R00, 0x04 - "100100" & X"010", -- 0x01E: XOUT (0x01), R00 - "111011" & X"0ED", -- 0x01F: CALL 0x0ED - "000011" & X"050", -- 0x020: MOV R00, 0x05 - "100100" & X"010", -- 0x021: XOUT (0x01), R00 - "111011" & X"0FF", -- 0x022: CALL 0x0FF - "000011" & X"060", -- 0x023: MOV R00, 0x06 - "100100" & X"010", -- 0x024: XOUT (0x01), R00 - "111011" & X"115", -- 0x025: CALL 0x115 - "000011" & X"070", -- 0x026: MOV R00, 0x07 - "100100" & X"010", -- 0x027: XOUT (0x01), R00 - "111011" & X"12B", -- 0x028: CALL 0x12B - "000011" & X"080", -- 0x029: MOV R00, 0x08 - "100100" & X"010", -- 0x02A: XOUT (0x01), R00 - "111011" & X"137", -- 0x02B: CALL 0x137 - "000011" & X"090", -- 0x02C: MOV R00, 0x09 - "100100" & X"010", -- 0x02D: XOUT (0x01), R00 - "111011" & X"15A", -- 0x02E: CALL 0x15A - "000011" & X"0A0", -- 0x02F: MOV R00, 0x0A - "100100" & X"010", -- 0x030: XOUT (0x01), R00 - "111011" & X"22A", -- 0x031: CALL 0x22A - "000011" & X"0B0", -- 0x032: MOV R00, 0x0B - "100100" & X"010", -- 0x033: XOUT (0x01), R00 - "111011" & X"24D", -- 0x034: CALL 0x24D - "000011" & X"0C0", -- 0x035: MOV R00, 0x0C - "100100" & X"010", -- 0x036: XOUT (0x01), R00 - "111011" & X"278", -- 0x037: CALL 0x278 - "000011" & X"FF0", -- 0x038: MOV R00, 0xFF - "100100" & X"010", -- 0x039: XOUT (0x01), R00 - "110000" & X"2FF", -- 0x03A: JMP 0x2FF - "000011" & X"000", -- 0x03B: MOV R00, 0x00 - "000011" & X"001", -- 0x03C: MOV R01, 0x00 - "000011" & X"002", -- 0x03D: MOV R02, 0x00 - "000011" & X"003", -- 0x03E: MOV R03, 0x00 - "000011" & X"004", -- 0x03F: MOV R04, 0x00 - "000011" & X"005", -- 0x040: MOV R05, 0x00 - "000011" & X"006", -- 0x041: MOV R06, 0x00 - "000011" & X"007", -- 0x042: MOV R07, 0x00 - "000011" & X"008", -- 0x043: MOV R08, 0x00 - "000011" & X"009", -- 0x044: MOV R09, 0x00 - "000011" & X"00A", -- 0x045: MOV R10, 0x00 - "000011" & X"00B", -- 0x046: MOV R11, 0x00 - "000011" & X"00C", -- 0x047: MOV R12, 0x00 - "000011" & X"00D", -- 0x048: MOV R13, 0x00 - "000011" & X"00E", -- 0x049: MOV R14, 0x00 - "000011" & X"00F", -- 0x04A: MOV R15, 0x00 - "111110" & X"000", -- 0x04B: RET - "000011" & X"100", -- 0x04C: MOV R00, 0x10 - "001111" & X"100", -- 0x04D: CMP R00, 0x10 - "111010" & X"3FF", -- 0x04E: JNE 0x3FF - "010001" & X"010", -- 0x04F: ADD R00, 0x01 - "000010" & X"001", -- 0x050: MOV R01, R00 - "001111" & X"111", -- 0x051: CMP R01, 0x11 - "111010" & X"3FF", -- 0x052: JNE 0x3FF - "010001" & X"011", -- 0x053: ADD R01, 0x01 - "000010" & X"012", -- 0x054: MOV R02, R01 - "001111" & X"122", -- 0x055: CMP R02, 0x12 - "111010" & X"3FF", -- 0x056: JNE 0x3FF - "010001" & X"012", -- 0x057: ADD R02, 0x01 - "000010" & X"023", -- 0x058: MOV R03, R02 - "001111" & X"133", -- 0x059: CMP R03, 0x13 - "111010" & X"3FF", -- 0x05A: JNE 0x3FF - "010001" & X"013", -- 0x05B: ADD R03, 0x01 - "000010" & X"034", -- 0x05C: MOV R04, R03 - "001111" & X"144", -- 0x05D: CMP R04, 0x14 - "111010" & X"3FF", -- 0x05E: JNE 0x3FF - "010001" & X"014", -- 0x05F: ADD R04, 0x01 - "000010" & X"045", -- 0x060: MOV R05, R04 - "001111" & X"155", -- 0x061: CMP R05, 0x15 - "111010" & X"3FF", -- 0x062: JNE 0x3FF - "010001" & X"015", -- 0x063: ADD R05, 0x01 - "000010" & X"056", -- 0x064: MOV R06, R05 - "001111" & X"166", -- 0x065: CMP R06, 0x16 - "111010" & X"3FF", -- 0x066: JNE 0x3FF - "010001" & X"016", -- 0x067: ADD R06, 0x01 - "000010" & X"067", -- 0x068: MOV R07, R06 - "001111" & X"177", -- 0x069: CMP R07, 0x17 - "111010" & X"3FF", -- 0x06A: JNE 0x3FF - "010001" & X"017", -- 0x06B: ADD R07, 0x01 - "000010" & X"078", -- 0x06C: MOV R08, R07 - "001111" & X"188", -- 0x06D: CMP R08, 0x18 - "111010" & X"3FF", -- 0x06E: JNE 0x3FF - "010001" & X"018", -- 0x06F: ADD R08, 0x01 - "000010" & X"089", -- 0x070: MOV R09, R08 - "001111" & X"199", -- 0x071: CMP R09, 0x19 - "111010" & X"3FF", -- 0x072: JNE 0x3FF - "010001" & X"019", -- 0x073: ADD R09, 0x01 - "000010" & X"09A", -- 0x074: MOV R10, R09 - "001111" & X"1AA", -- 0x075: CMP R10, 0x1A - "111010" & X"3FF", -- 0x076: JNE 0x3FF - "010001" & X"01A", -- 0x077: ADD R10, 0x01 - "000010" & X"0AB", -- 0x078: MOV R11, R10 - "001111" & X"1BB", -- 0x079: CMP R11, 0x1B - "111010" & X"3FF", -- 0x07A: JNE 0x3FF - "010001" & X"01B", -- 0x07B: ADD R11, 0x01 - "000010" & X"0BC", -- 0x07C: MOV R12, R11 - "001111" & X"1CC", -- 0x07D: CMP R12, 0x1C - "111010" & X"3FF", -- 0x07E: JNE 0x3FF - "010001" & X"01C", -- 0x07F: ADD R12, 0x01 - "000010" & X"0CD", -- 0x080: MOV R13, R12 - "001111" & X"1DD", -- 0x081: CMP R13, 0x1D - "111010" & X"3FF", -- 0x082: JNE 0x3FF - "010001" & X"01D", -- 0x083: ADD R13, 0x01 - "000010" & X"0DE", -- 0x084: MOV R14, R13 - "001111" & X"1EE", -- 0x085: CMP R14, 0x1E - "111010" & X"3FF", -- 0x086: JNE 0x3FF - "010001" & X"01E", -- 0x087: ADD R14, 0x01 - "000010" & X"0EF", -- 0x088: MOV R15, R14 - "001111" & X"1FF", -- 0x089: CMP R15, 0x1F - "111010" & X"3FF", -- 0x08A: JNE 0x3FF - "010001" & X"01F", -- 0x08B: ADD R15, 0x01 - "111110" & X"000", -- 0x08C: RET - "000011" & X"000", -- 0x08D: MOV R00, 0x00 - "001111" & X"000", -- 0x08E: TST R00 - "110010" & X"3FF", -- 0x08F: JNZ 0x3FF - "110011" & X"3FF", -- 0x090: JC 0x3FF - "001111" & X"000", -- 0x091: CMP R00, 0x00 - "111010" & X"3FF", -- 0x092: JNE 0x3FF - "110101" & X"3FF", -- 0x093: JLT 0x3FF - "110110" & X"3FF", -- 0x094: JGT 0x3FF - "110111" & X"097", -- 0x095: JLE 0x097 - "110000" & X"3FF", -- 0x096: JMP 0x3FF - "111001" & X"099", -- 0x097: JEQ 0x099 - "110000" & X"3FF", -- 0x098: JMP 0x3FF - "111000" & X"09B", -- 0x099: JGE 0x09B - "110000" & X"3FF", -- 0x09A: JMP 0x3FF - "001111" & X"550", -- 0x09B: CMP R00, 0x55 - "111001" & X"3FF", -- 0x09C: JEQ 0x3FF - "110101" & X"09F", -- 0x09D: JLT 0x09F - "110000" & X"3FF", -- 0x09E: JMP 0x3FF - "110111" & X"0A1", -- 0x09F: JLE 0x0A1 - "110000" & X"3FF", -- 0x0A0: JMP 0x3FF - "111000" & X"3FF", -- 0x0A1: JGE 0x3FF - "110110" & X"3FF", -- 0x0A2: JGT 0x3FF - "000011" & X"550", -- 0x0A3: MOV R00, 0x55 - "001111" & X"000", -- 0x0A4: TST R00 - "110001" & X"3FF", -- 0x0A5: JZ 0x3FF - "110011" & X"3FF", -- 0x0A6: JC 0x3FF - "001111" & X"AA0", -- 0x0A7: CMP R00, 0xAA - "111001" & X"3FF", -- 0x0A8: JEQ 0x3FF - "111010" & X"0AB", -- 0x0A9: JNE 0x0AB - "110000" & X"3FF", -- 0x0AA: JMP 0x3FF - "110101" & X"0AD", -- 0x0AB: JLT 0x0AD - "110000" & X"3FF", -- 0x0AC: JMP 0x3FF - "110111" & X"0AF", -- 0x0AD: JLE 0x0AF - "110000" & X"3FF", -- 0x0AE: JMP 0x3FF - "110110" & X"3FF", -- 0x0AF: JGT 0x3FF - "001111" & X"550", -- 0x0B0: CMP R00, 0x55 - "111001" & X"0B3", -- 0x0B1: JEQ 0x0B3 - "110000" & X"3FF", -- 0x0B2: JMP 0x3FF - "111010" & X"3FF", -- 0x0B3: JNE 0x3FF - "110101" & X"3FF", -- 0x0B4: JLT 0x3FF - "110111" & X"0B7", -- 0x0B5: JLE 0x0B7 - "110000" & X"3FF", -- 0x0B6: JMP 0x3FF - "110110" & X"3FF", -- 0x0B7: JGT 0x3FF - "111000" & X"0BA", -- 0x0B8: JGE 0x0BA - "110000" & X"3FF", -- 0x0B9: JMP 0x3FF - "000011" & X"AA0", -- 0x0BA: MOV R00, 0xAA - "001111" & X"000", -- 0x0BB: TST R00 - "110001" & X"3FF", -- 0x0BC: JZ 0x3FF - "110011" & X"3FF", -- 0x0BD: JC 0x3FF - "001111" & X"550", -- 0x0BE: CMP R00, 0x55 - "111001" & X"3FF", -- 0x0BF: JEQ 0x3FF - "111010" & X"0C2", -- 0x0C0: JNE 0x0C2 - "110000" & X"3FF", -- 0x0C1: JMP 0x3FF - "110110" & X"0C4", -- 0x0C2: JGT 0x0C4 - "110000" & X"3FF", -- 0x0C3: JMP 0x3FF - "111000" & X"0C6", -- 0x0C4: JGE 0x0C6 - "110000" & X"3FF", -- 0x0C5: JMP 0x3FF - "110101" & X"3FF", -- 0x0C6: JLT 0x3FF - "110111" & X"3FF", -- 0x0C7: JLE 0x3FF - "111110" & X"000", -- 0x0C8: RET - "000011" & X"000", -- 0x0C9: MOV R00, 0x00 - "000011" & X"001", -- 0x0CA: MOV R01, 0x00 - "000010" & X"002", -- 0x0CB: MOV R02, R00 - "000010" & X"013", -- 0x0CC: MOV R03, R01 - "010001" & X"010", -- 0x0CD: ADD R00, 0x01 - "010011" & X"001", -- 0x0CE: ADDC R01, 0x00 - "010001" & X"012", -- 0x0CF: ADD R02, 0x01 - "001111" & X"002", -- 0x0D0: CMP R02, 0x00 - "111010" & X"0D4", -- 0x0D1: JNE 0x0D4 - "010001" & X"013", -- 0x0D2: ADD R03, 0x01 - "001111" & X"023", -- 0x0D3: CMP R03, 0x02 - "111010" & X"0CD", -- 0x0D4: JNE 0x0CD - "001110" & X"020", -- 0x0D5: CMP R00, R02 - "111010" & X"3FF", -- 0x0D6: JNE 0x3FF - "001110" & X"031", -- 0x0D7: CMP R01, R03 - "111010" & X"3FF", -- 0x0D8: JNE 0x3FF - "000011" & X"000", -- 0x0D9: MOV R00, 0x00 - "111110" & X"000", -- 0x0DA: RET - "000011" & X"000", -- 0x0DB: MOV R00, 0x00 - "000011" & X"031", -- 0x0DC: MOV R01, 0x03 - "000010" & X"002", -- 0x0DD: MOV R02, R00 - "000010" & X"013", -- 0x0DE: MOV R03, R01 - "010101" & X"010", -- 0x0DF: SUB R00, 0x01 - "010111" & X"001", -- 0x0E0: SUBC R01, 0x00 - "010101" & X"012", -- 0x0E1: SUB R02, 0x01 - "001111" & X"FF2", -- 0x0E2: CMP R02, 0xFF - "111010" & X"0E6", -- 0x0E3: JNE 0x0E6 - "010101" & X"013", -- 0x0E4: SUB R03, 0x01 - "001111" & X"003", -- 0x0E5: CMP R03, 0x00 - "111010" & X"0DF", -- 0x0E6: JNE 0x0DF - "001110" & X"020", -- 0x0E7: CMP R00, R02 - "111010" & X"3FF", -- 0x0E8: JNE 0x3FF - "001110" & X"031", -- 0x0E9: CMP R01, R03 - "111010" & X"3FF", -- 0x0EA: JNE 0x3FF - "000011" & X"000", -- 0x0EB: MOV R00, 0x00 - "111110" & X"000", -- 0x0EC: RET - "000011" & X"030", -- 0x0ED: MOV R00, 0x03 - "000011" & X"051", -- 0x0EE: MOV R01, 0x05 - "101110" & X"050", -- 0x0EF: SUB 0x05, R00 - "010101" & X"031", -- 0x0F0: SUB R01, 0x03 - "001110" & X"010", -- 0x0F1: CMP R00, R01 - "111010" & X"3FF", -- 0x0F2: JNE 0x3FF - "000011" & X"030", -- 0x0F3: MOV R00, 0x03 - "000011" & X"051", -- 0x0F4: MOV R01, 0x05 - "010100" & X"010", -- 0x0F5: SUB R00, R01 - "101111" & X"000", -- 0x0F6: SUBC 0x00, R00 - "001111" & X"010", -- 0x0F7: CMP R00, 0x01 - "111010" & X"3FF", -- 0x0F8: JNE 0x3FF - "010001" & X"000", -- 0x0F9: ADD R00, 0x00 - "010110" & X"001", -- 0x0FA: SUBC R01, R00 - "001111" & X"041", -- 0x0FB: CMP R01, 0x04 - "111010" & X"3FF", -- 0x0FC: JNE 0x3FF - "000011" & X"000", -- 0x0FD: MOV R00, 0x00 - "111110" & X"000", -- 0x0FE: RET - "000011" & X"010", -- 0x0FF: MOV R00, 0x01 - "001101" & X"5A0", -- 0x100: MOVC (0x5A), R00 - "010101" & X"010", -- 0x101: DEC R00 - "001101" & X"000", -- 0x102: MOVC (0x00), R00 - "001010" & X"5A1", -- 0x103: MOVC R01, (0x5A) - "001100" & X"A51", -- 0x104: MOVC (R01), 0xA5 - "001001" & X"010", -- 0x105: MOVC R00, (R01) - "001001" & X"011", -- 0x106: MOVC R01, (R01) - "010001" & X"5A1", -- 0x107: ADD R01, 0x5A - "001001" & X"010", -- 0x108: MOVC R00, (R01) - "001011" & X"000", -- 0x109: MOVC (R00), R00 - "001001" & X"002", -- 0x10A: MOVC R02, (R00) - "001110" & X"002", -- 0x10B: CMP R02, R00 - "111010" & X"3FF", -- 0x10C: JNE 0x3FF - "001011" & X"021", -- 0x10D: MOVC (R01), R02 - "001001" & X"022", -- 0x10E: MOVC R02, (R02) - "001110" & X"012", -- 0x10F: CMP R02, R01 - "111010" & X"3FF", -- 0x110: JNE 0x3FF - "010101" & X"011", -- 0x111: DEC R01 - "010001" & X"010", -- 0x112: INC R00 - "110010" & X"109", -- 0x113: JNZ 0x109 - "111110" & X"000", -- 0x114: RET - "000011" & X"010", -- 0x115: MOV R00, 0x01 - "001000" & X"600", -- 0x116: MOVX (0x60), R00 - "010101" & X"010", -- 0x117: DEC R00 - "001000" & X"060", -- 0x118: MOVX (0x06), R00 - "000101" & X"601", -- 0x119: MOVX R01, (0x60) - "000111" & X"A51", -- 0x11A: MOVX (R01), 0xA5 - "000100" & X"010", -- 0x11B: MOVX R00, (R01) - "000100" & X"011", -- 0x11C: MOVX R01, (R01) - "010001" & X"5A1", -- 0x11D: ADD R01, 0x5A - "000100" & X"010", -- 0x11E: MOVX R00, (R01) - "000110" & X"000", -- 0x11F: MOVX (R00), R00 - "000100" & X"002", -- 0x120: MOVX R02, (R00) - "001110" & X"002", -- 0x121: CMP R02, R00 - "111010" & X"3FF", -- 0x122: JNE 0x3FF - "000110" & X"021", -- 0x123: MOVX (R01), R02 - "000100" & X"022", -- 0x124: MOVX R02, (R02) - "001110" & X"012", -- 0x125: CMP R02, R01 - "111010" & X"3FF", -- 0x126: JNE 0x3FF - "010101" & X"011", -- 0x127: DEC R01 - "010001" & X"010", -- 0x128: INC R00 - "110010" & X"11F", -- 0x129: JNZ 0x11F - "111110" & X"000", -- 0x12A: RET - "000011" & X"AA0", -- 0x12B: MOV R00, 0xAA - "000011" & X"001", -- 0x12C: MOV R01, 0x00 - "111100" & X"000", -- 0x12D: PUSH R00 - "010001" & X"010", -- 0x12E: INC R00 - "010101" & X"011", -- 0x12F: DEC R01 - "110010" & X"12D", -- 0x130: JNZ 0x12D - "111101" & X"000", -- 0x131: POP R00 - "010101" & X"011", -- 0x132: DEC R01 - "110010" & X"131", -- 0x133: JNZ 0x131 - "001111" & X"AA0", -- 0x134: CMP R00, 0xAA - "111010" & X"3FF", -- 0x135: JNE 0x3FF - "111110" & X"000", -- 0x136: RET - "000011" & X"550", -- 0x137: MOV R00, 0x55 - "111100" & X"000", -- 0x138: PUSH R00 - "000011" & X"000", -- 0x139: MOV R00, 0x00 - "000011" & X"FF1", -- 0x13A: MOV R01, 0xFF - "111011" & X"151", -- 0x13B: CALL 0x151 - "111101" & X"000", -- 0x13C: POP R00 - "001111" & X"550", -- 0x13D: CMP R00, 0x55 - "111010" & X"3FF", -- 0x13E: JNE 0x3FF - "000011" & X"010", -- 0x13F: MOV R00, 0x01 - "000011" & X"481", -- 0x140: MOV R01, 0x48 - "100110" & X"050", -- 0x141: COUT (0x05), R00 - "111100" & X"001", -- 0x142: PUSH R01 - "000011" & X"000", -- 0x143: MOV R00, 0x00 - "000011" & X"3B1", -- 0x144: MOV R01, 0x3B - "100110" & X"050", -- 0x145: COUT (0x05), R00 - "111100" & X"001", -- 0x146: PUSH R01 - "111110" & X"000", -- 0x147: RET - "000011" & X"010", -- 0x148: MOV R00, 0x01 - "000011" & X"501", -- 0x149: MOV R01, 0x50 - "100110" & X"050", -- 0x14A: COUT (0x05), R00 - "111100" & X"001", -- 0x14B: PUSH R01 - "000011" & X"000", -- 0x14C: MOV R00, 0x00 - "000011" & X"3B1", -- 0x14D: MOV R01, 0x3B - "100110" & X"050", -- 0x14E: COUT (0x05), R00 - "111100" & X"001", -- 0x14F: PUSH R01 - "111110" & X"000", -- 0x150: RET - "001110" & X"010", -- 0x151: CMP R00, R01 - "111001" & X"155", -- 0x152: JEQ 0x155 - "010001" & X"010", -- 0x153: INC R00 - "110000" & X"158", -- 0x154: JMP 0x158 - "010101" & X"010", -- 0x155: DEC R00 - "010101" & X"011", -- 0x156: DEC R01 - "111110" & X"000", -- 0x157: RET - "111011" & X"151", -- 0x158: CALL 0x151 - "110000" & X"155", -- 0x159: JMP 0x155 - "000011" & X"A50", -- 0x15A: MOV R00, 0xA5 - "000011" & X"5A1", -- 0x15B: MOV R01, 0x5A - "101010" & X"000", -- 0x15C: SWAP R00 - "001111" & X"5A0", -- 0x15D: CMP R00, 0x5A - "111010" & X"3FF", -- 0x15E: JNE 0x3FF - "101010" & X"000", -- 0x15F: SWAP R00 - "001111" & X"A50", -- 0x160: CMP R00, 0xA5 - "111010" & X"3FF", -- 0x161: JNE 0x3FF - "000011" & X"D20", -- 0x162: MOV R00, 0xD2 - "101010" & X"000", -- 0x163: SWAP R00 - "001111" & X"2D0", -- 0x164: CMP R00, 0x2D - "111010" & X"3FF", -- 0x165: JNE 0x3FF - "101010" & X"001", -- 0x166: SWAP R01 - "001111" & X"2D0", -- 0x167: CMP R00, 0x2D - "111010" & X"3FF", -- 0x168: JNE 0x3FF - "001111" & X"A51", -- 0x169: CMP R01, 0xA5 - "111010" & X"3FF", -- 0x16A: JNE 0x3FF - "000011" & X"2D0", -- 0x16B: MOV R00, 0x2D - "011110" & X"000", -- 0x16C: SHL R00 - "001111" & X"5A0", -- 0x16D: CMP R00, 0x5A - "111010" & X"3FF", -- 0x16E: JNE 0x3FF - "011110" & X"000", -- 0x16F: SHL R00 - "001111" & X"B40", -- 0x170: CMP R00, 0xB4 - "111010" & X"3FF", -- 0x171: JNE 0x3FF - "011110" & X"000", -- 0x172: SHL R00 - "001111" & X"680", -- 0x173: CMP R00, 0x68 - "111010" & X"3FF", -- 0x174: JNE 0x3FF - "011110" & X"000", -- 0x175: SHL R00 - "001111" & X"D00", -- 0x176: CMP R00, 0xD0 - "111010" & X"3FF", -- 0x177: JNE 0x3FF - "011110" & X"000", -- 0x178: SHL R00 - "001111" & X"A00", -- 0x179: CMP R00, 0xA0 - "111010" & X"3FF", -- 0x17A: JNE 0x3FF - "011110" & X"000", -- 0x17B: SHL R00 - "001111" & X"400", -- 0x17C: CMP R00, 0x40 - "111010" & X"3FF", -- 0x17D: JNE 0x3FF - "011110" & X"000", -- 0x17E: SHL R00 - "001111" & X"800", -- 0x17F: CMP R00, 0x80 - "111010" & X"3FF", -- 0x180: JNE 0x3FF - "011110" & X"000", -- 0x181: SHL R00 - "001111" & X"000", -- 0x182: CMP R00, 0x00 - "111010" & X"3FF", -- 0x183: JNE 0x3FF - "000011" & X"841", -- 0x184: MOV R01, 0x84 - "011111" & X"001", -- 0x185: SHR R01 - "001111" & X"421", -- 0x186: CMP R01, 0x42 - "111010" & X"3FF", -- 0x187: JNE 0x3FF - "011111" & X"001", -- 0x188: SHR R01 - "001111" & X"211", -- 0x189: CMP R01, 0x21 - "111010" & X"3FF", -- 0x18A: JNE 0x3FF - "011111" & X"001", -- 0x18B: SHR R01 - "001111" & X"101", -- 0x18C: CMP R01, 0x10 - "111010" & X"3FF", -- 0x18D: JNE 0x3FF - "011111" & X"001", -- 0x18E: SHR R01 - "001111" & X"081", -- 0x18F: CMP R01, 0x08 - "111010" & X"3FF", -- 0x190: JNE 0x3FF - "011111" & X"001", -- 0x191: SHR R01 - "001111" & X"041", -- 0x192: CMP R01, 0x04 - "111010" & X"3FF", -- 0x193: JNE 0x3FF - "011111" & X"001", -- 0x194: SHR R01 - "001111" & X"021", -- 0x195: CMP R01, 0x02 - "111010" & X"3FF", -- 0x196: JNE 0x3FF - "011111" & X"001", -- 0x197: SHR R01 - "001111" & X"011", -- 0x198: CMP R01, 0x01 - "111010" & X"3FF", -- 0x199: JNE 0x3FF - "011111" & X"001", -- 0x19A: SHR R01 - "001111" & X"001", -- 0x19B: CMP R01, 0x00 - "111010" & X"3FF", -- 0x19C: JNE 0x3FF - "000011" & X"C50", -- 0x19D: MOV R00, 0xC5 - "100000" & X"000", -- 0x19E: ROL R00 - "001111" & X"8B0", -- 0x19F: CMP R00, 0x8B - "111010" & X"3FF", -- 0x1A0: JNE 0x3FF - "100000" & X"000", -- 0x1A1: ROL R00 - "001111" & X"170", -- 0x1A2: CMP R00, 0x17 - "111010" & X"3FF", -- 0x1A3: JNE 0x3FF - "100000" & X"000", -- 0x1A4: ROL R00 - "001111" & X"2E0", -- 0x1A5: CMP R00, 0x2E - "111010" & X"3FF", -- 0x1A6: JNE 0x3FF - "100000" & X"000", -- 0x1A7: ROL R00 - "001111" & X"5C0", -- 0x1A8: CMP R00, 0x5C - "111010" & X"3FF", -- 0x1A9: JNE 0x3FF - "100000" & X"000", -- 0x1AA: ROL R00 - "001111" & X"B80", -- 0x1AB: CMP R00, 0xB8 - "111010" & X"3FF", -- 0x1AC: JNE 0x3FF - "100000" & X"000", -- 0x1AD: ROL R00 - "001111" & X"710", -- 0x1AE: CMP R00, 0x71 - "111010" & X"3FF", -- 0x1AF: JNE 0x3FF - "100000" & X"000", -- 0x1B0: ROL R00 - "001111" & X"E20", -- 0x1B1: CMP R00, 0xE2 - "111010" & X"3FF", -- 0x1B2: JNE 0x3FF - "100000" & X"000", -- 0x1B3: ROL R00 - "001111" & X"C50", -- 0x1B4: CMP R00, 0xC5 - "111010" & X"3FF", -- 0x1B5: JNE 0x3FF - "000011" & X"631", -- 0x1B6: MOV R01, 0x63 - "100001" & X"001", -- 0x1B7: ROR R01 - "001111" & X"B11", -- 0x1B8: CMP R01, 0xB1 - "111010" & X"3FF", -- 0x1B9: JNE 0x3FF - "100001" & X"001", -- 0x1BA: ROR R01 - "001111" & X"D81", -- 0x1BB: CMP R01, 0xD8 - "111010" & X"3FF", -- 0x1BC: JNE 0x3FF - "100001" & X"001", -- 0x1BD: ROR R01 - "001111" & X"6C1", -- 0x1BE: CMP R01, 0x6C - "111010" & X"3FF", -- 0x1BF: JNE 0x3FF - "100001" & X"001", -- 0x1C0: ROR R01 - "001111" & X"361", -- 0x1C1: CMP R01, 0x36 - "111010" & X"3FF", -- 0x1C2: JNE 0x3FF - "100001" & X"001", -- 0x1C3: ROR R01 - "001111" & X"1B1", -- 0x1C4: CMP R01, 0x1B - "111010" & X"3FF", -- 0x1C5: JNE 0x3FF - "100001" & X"001", -- 0x1C6: ROR R01 - "001111" & X"8D1", -- 0x1C7: CMP R01, 0x8D - "111010" & X"3FF", -- 0x1C8: JNE 0x3FF - "100001" & X"001", -- 0x1C9: ROR R01 - "001111" & X"C61", -- 0x1CA: CMP R01, 0xC6 - "111010" & X"3FF", -- 0x1CB: JNE 0x3FF - "100001" & X"001", -- 0x1CC: ROR R01 - "001111" & X"631", -- 0x1CD: CMP R01, 0x63 - "111010" & X"3FF", -- 0x1CE: JNE 0x3FF - "011100" & X"000", -- 0x1CF: XOR R00, R00 - "000011" & X"C50", -- 0x1D0: MOV R00, 0xC5 - "100010" & X"000", -- 0x1D1: ROLC R00 - "111100" & X"000", -- 0x1D2: PUSH R00 - "100010" & X"000", -- 0x1D3: ROLC R00 - "111100" & X"000", -- 0x1D4: PUSH R00 - "100010" & X"000", -- 0x1D5: ROLC R00 - "111100" & X"000", -- 0x1D6: PUSH R00 - "100010" & X"000", -- 0x1D7: ROLC R00 - "111100" & X"000", -- 0x1D8: PUSH R00 - "100010" & X"000", -- 0x1D9: ROLC R00 - "111100" & X"000", -- 0x1DA: PUSH R00 - "100010" & X"000", -- 0x1DB: ROLC R00 - "111100" & X"000", -- 0x1DC: PUSH R00 - "100010" & X"000", -- 0x1DD: ROLC R00 - "111100" & X"000", -- 0x1DE: PUSH R00 - "100010" & X"000", -- 0x1DF: ROLC R00 - "111100" & X"000", -- 0x1E0: PUSH R00 - "100010" & X"000", -- 0x1E1: ROLC R00 - "001111" & X"C50", -- 0x1E2: CMP R00, 0xC5 - "111010" & X"3FF", -- 0x1E3: JNE 0x3FF - "111101" & X"000", -- 0x1E4: POP R00 - "001111" & X"620", -- 0x1E5: CMP R00, 0x62 - "111010" & X"3FF", -- 0x1E6: JNE 0x3FF - "111101" & X"000", -- 0x1E7: POP R00 - "001111" & X"B10", -- 0x1E8: CMP R00, 0xB1 - "111010" & X"3FF", -- 0x1E9: JNE 0x3FF - "111101" & X"000", -- 0x1EA: POP R00 - "001111" & X"580", -- 0x1EB: CMP R00, 0x58 - "111010" & X"3FF", -- 0x1EC: JNE 0x3FF - "111101" & X"000", -- 0x1ED: POP R00 - "001111" & X"AC0", -- 0x1EE: CMP R00, 0xAC - "111010" & X"3FF", -- 0x1EF: JNE 0x3FF - "111101" & X"000", -- 0x1F0: POP R00 - "001111" & X"560", -- 0x1F1: CMP R00, 0x56 - "111010" & X"3FF", -- 0x1F2: JNE 0x3FF - "111101" & X"000", -- 0x1F3: POP R00 - "001111" & X"2B0", -- 0x1F4: CMP R00, 0x2B - "111010" & X"3FF", -- 0x1F5: JNE 0x3FF - "111101" & X"000", -- 0x1F6: POP R00 - "001111" & X"150", -- 0x1F7: CMP R00, 0x15 - "111010" & X"3FF", -- 0x1F8: JNE 0x3FF - "111101" & X"000", -- 0x1F9: POP R00 - "001111" & X"8A0", -- 0x1FA: CMP R00, 0x8A - "111010" & X"3FF", -- 0x1FB: JNE 0x3FF - "011100" & X"011", -- 0x1FC: XOR R01, R01 - "000011" & X"631", -- 0x1FD: MOV R01, 0x63 - "100011" & X"001", -- 0x1FE: RORC R01 - "111100" & X"001", -- 0x1FF: PUSH R01 - "100011" & X"001", -- 0x200: RORC R01 - "111100" & X"001", -- 0x201: PUSH R01 - "100011" & X"001", -- 0x202: RORC R01 - "111100" & X"001", -- 0x203: PUSH R01 - "100011" & X"001", -- 0x204: RORC R01 - "111100" & X"001", -- 0x205: PUSH R01 - "100011" & X"001", -- 0x206: RORC R01 - "111100" & X"001", -- 0x207: PUSH R01 - "100011" & X"001", -- 0x208: RORC R01 - "111100" & X"001", -- 0x209: PUSH R01 - "100011" & X"001", -- 0x20A: RORC R01 - "111100" & X"001", -- 0x20B: PUSH R01 - "100011" & X"001", -- 0x20C: RORC R01 - "111100" & X"001", -- 0x20D: PUSH R01 - "100011" & X"001", -- 0x20E: RORC R01 - "001111" & X"631", -- 0x20F: CMP R01, 0x63 - "111010" & X"3FF", -- 0x210: JNE 0x3FF - "111101" & X"001", -- 0x211: POP R01 - "001111" & X"C61", -- 0x212: CMP R01, 0xC6 - "111010" & X"3FF", -- 0x213: JNE 0x3FF - "111101" & X"001", -- 0x214: POP R01 - "001111" & X"8C1", -- 0x215: CMP R01, 0x8C - "111010" & X"3FF", -- 0x216: JNE 0x3FF - "111101" & X"001", -- 0x217: POP R01 - "001111" & X"191", -- 0x218: CMP R01, 0x19 - "111010" & X"3FF", -- 0x219: JNE 0x3FF - "111101" & X"001", -- 0x21A: POP R01 - "001111" & X"331", -- 0x21B: CMP R01, 0x33 - "111010" & X"3FF", -- 0x21C: JNE 0x3FF - "111101" & X"001", -- 0x21D: POP R01 - "001111" & X"661", -- 0x21E: CMP R01, 0x66 - "111010" & X"3FF", -- 0x21F: JNE 0x3FF - "111101" & X"001", -- 0x220: POP R01 - "001111" & X"CC1", -- 0x221: CMP R01, 0xCC - "111010" & X"3FF", -- 0x222: JNE 0x3FF - "111101" & X"001", -- 0x223: POP R01 - "001111" & X"981", -- 0x224: CMP R01, 0x98 - "111010" & X"3FF", -- 0x225: JNE 0x3FF - "111101" & X"001", -- 0x226: POP R01 - "001111" & X"311", -- 0x227: CMP R01, 0x31 - "111010" & X"3FF", -- 0x228: JNE 0x3FF - "111110" & X"000", -- 0x229: RET - "000011" & X"A50", -- 0x22A: MOV R00, 0xA5 - "101010" & X"000", -- 0x22B: SWAP R00 - "111100" & X"000", -- 0x22C: PUSH R00 - "011001" & X"0F0", -- 0x22D: AND R00, 0x0F - "001111" & X"0A0", -- 0x22E: CMP R00, 0x0A - "111010" & X"3FF", -- 0x22F: JNE 0x3FF - "111101" & X"000", -- 0x230: POP R00 - "111100" & X"000", -- 0x231: PUSH R00 - "011001" & X"0F0", -- 0x232: AND R00, 0x0F - "001111" & X"0A0", -- 0x233: CMP R00, 0x0A - "111101" & X"001", -- 0x234: POP R01 - "111010" & X"3FF", -- 0x235: JNE 0x3FF - "101010" & X"001", -- 0x236: SWAP R01 - "000011" & X"0F2", -- 0x237: MOV R02, 0x0F - "011000" & X"021", -- 0x238: AND R01, R02 - "001111" & X"051", -- 0x239: CMP R01, 0x05 - "111010" & X"3FF", -- 0x23A: JNE 0x3FF - "000011" & X"050", -- 0x23B: MOV R00, 0x05 - "000011" & X"A02", -- 0x23C: MOV R02, 0xA0 - "101010" & X"000", -- 0x23D: SWAP R00 - "011010" & X"002", -- 0x23E: OR R02, R00 - "001111" & X"F02", -- 0x23F: CMP R02, 0xF0 - "111010" & X"3FF", -- 0x240: JNE 0x3FF - "101010" & X"000", -- 0x241: SWAP R00 - "011011" & X"500", -- 0x242: OR R00, 0x50 - "001111" & X"550", -- 0x243: CMP R00, 0x55 - "111010" & X"3FF", -- 0x244: JNE 0x3FF - "000011" & X"011", -- 0x245: MOV R01, 0x01 - "000011" & X"010", -- 0x246: MOV R00, 0x01 - "011101" & X"010", -- 0x247: XOR R00, 0x01 - "110010" & X"3FF", -- 0x248: JNZ 0x3FF - "011100" & X"010", -- 0x249: XOR R00, R01 - "001111" & X"010", -- 0x24A: CMP R00, 0x01 - "111010" & X"3FF", -- 0x24B: JNE 0x3FF - "111110" & X"000", -- 0x24C: RET - "000011" & X"030", -- 0x24D: MOV R00, 0x03 - "100110" & X"030", -- 0x24E: COUT (0x03), R00 - "101000" & X"020", -- 0x24F: XIN R00, (0x02) - "011011" & X"010", -- 0x250: OR R00, 0x01 - "100100" & X"020", -- 0x251: XOUT (0x02), R00 - "000000" & X"000", -- 0x252: NOP - "000000" & X"000", -- 0x253: NOP - "000000" & X"000", -- 0x254: NOP - "000000" & X"000", -- 0x255: NOP - "000000" & X"000", -- 0x256: NOP - "000000" & X"000", -- 0x257: NOP - "101000" & X"020", -- 0x258: XIN R00, (0x02) - "011001" & X"FE0", -- 0x259: AND R00, 0xFE - "100100" & X"020", -- 0x25A: XOUT (0x02), R00 - "000000" & X"000", -- 0x25B: NOP - "000000" & X"000", -- 0x25C: NOP - "000000" & X"000", -- 0x25D: NOP - "000000" & X"000", -- 0x25E: NOP - "101001" & X"030", -- 0x25F: CIN R00, (0x03) - "011011" & X"800", -- 0x260: OR R00, 0x80 - "100110" & X"030", -- 0x261: COUT (0x03), R00 - "000000" & X"000", -- 0x262: NOP - "101001" & X"030", -- 0x263: CIN R00, (0x03) - "011011" & X"800", -- 0x264: OR R00, 0x80 - "100110" & X"030", -- 0x265: COUT (0x03), R00 - "000000" & X"000", -- 0x266: NOP - "101001" & X"030", -- 0x267: CIN R00, (0x03) - "011011" & X"800", -- 0x268: OR R00, 0x80 - "100110" & X"030", -- 0x269: COUT (0x03), R00 - "000000" & X"000", -- 0x26A: NOP - "101001" & X"030", -- 0x26B: CIN R00, (0x03) - "011011" & X"800", -- 0x26C: OR R00, 0x80 - "100110" & X"030", -- 0x26D: COUT (0x03), R00 - "000000" & X"000", -- 0x26E: NOP - "000000" & X"000", -- 0x26F: NOP - "000000" & X"000", -- 0x270: NOP - "000000" & X"000", -- 0x271: NOP - "000000" & X"000", -- 0x272: NOP - "000000" & X"000", -- 0x273: NOP - "000000" & X"000", -- 0x274: NOP - "000000" & X"000", -- 0x275: NOP - "000000" & X"000", -- 0x276: NOP - "111110" & X"000", -- 0x277: RET - "010101" & X"000", -- 0x278: SUB R00, 0x00 - "110011" & X"3FF", -- 0x279: JC 0x3FF - "101011" & X"000", -- 0x27A: SETC - "110100" & X"3FF", -- 0x27B: JNC 0x3FF - "000000" & X"000", -- 0x27C: NOP - "010101" & X"000", -- 0x27D: SUB R00, 0x00 - "110011" & X"3FF", -- 0x27E: JC 0x3FF - "000011" & X"000", -- 0x27F: MOV R00, 0x00 - "010101" & X"000", -- 0x280: CLRC - "110011" & X"3FF", -- 0x281: JC 0x3FF - "101011" & X"000", -- 0x282: SETC - "110100" & X"3FF", -- 0x283: JNC 0x3FF - "000000" & X"000", -- 0x284: NOP - "010101" & X"000", -- 0x285: CLRC - "110011" & X"3FF", -- 0x286: JC 0x3FF - "111110" & X"000", -- 0x287: RET - "010001" & X"01E", -- 0x288: INC R14 - "111111" & X"000", -- 0x289: RETI - "000000" & X"000", -- 0x28A: - "000000" & X"000", -- 0x28B: - "000000" & X"000", -- 0x28C: - "000000" & X"000", -- 0x28D: - "000000" & X"000", -- 0x28E: - "000000" & X"000", -- 0x28F: - "000000" & X"000", -- 0x290: - "000000" & X"000", -- 0x291: - "000000" & X"000", -- 0x292: - "000000" & X"000", -- 0x293: - "000000" & X"000", -- 0x294: - "000000" & X"000", -- 0x295: - "000000" & X"000", -- 0x296: - "000000" & X"000", -- 0x297: - "000000" & X"000", -- 0x298: - "000000" & X"000", -- 0x299: - "000000" & X"000", -- 0x29A: - "000000" & X"000", -- 0x29B: - "000000" & X"000", -- 0x29C: - "000000" & X"000", -- 0x29D: - "000000" & X"000", -- 0x29E: - "000000" & X"000", -- 0x29F: - "000000" & X"000", -- 0x2A0: - "000000" & X"000", -- 0x2A1: - "000000" & X"000", -- 0x2A2: - "000000" & X"000", -- 0x2A3: - "000000" & X"000", -- 0x2A4: - "000000" & X"000", -- 0x2A5: - "000000" & X"000", -- 0x2A6: - "000000" & X"000", -- 0x2A7: - "000000" & X"000", -- 0x2A8: - "000000" & X"000", -- 0x2A9: - "000000" & X"000", -- 0x2AA: - "000000" & X"000", -- 0x2AB: - "000000" & X"000", -- 0x2AC: - "000000" & X"000", -- 0x2AD: - "000000" & X"000", -- 0x2AE: - "000000" & X"000", -- 0x2AF: - "000000" & X"000", -- 0x2B0: - "000000" & X"000", -- 0x2B1: - "000000" & X"000", -- 0x2B2: - "000000" & X"000", -- 0x2B3: - "000000" & X"000", -- 0x2B4: - "000000" & X"000", -- 0x2B5: - "000000" & X"000", -- 0x2B6: - "000000" & X"000", -- 0x2B7: - "000000" & X"000", -- 0x2B8: - "000000" & X"000", -- 0x2B9: - "000000" & X"000", -- 0x2BA: - "000000" & X"000", -- 0x2BB: - "000000" & X"000", -- 0x2BC: - "000000" & X"000", -- 0x2BD: - "000000" & X"000", -- 0x2BE: - "000000" & X"000", -- 0x2BF: - "000000" & X"000", -- 0x2C0: - "000000" & X"000", -- 0x2C1: - "000000" & X"000", -- 0x2C2: - "000000" & X"000", -- 0x2C3: - "000000" & X"000", -- 0x2C4: - "000000" & X"000", -- 0x2C5: - "000000" & X"000", -- 0x2C6: - "000000" & X"000", -- 0x2C7: - "000000" & X"000", -- 0x2C8: - "000000" & X"000", -- 0x2C9: - "000000" & X"000", -- 0x2CA: - "000000" & X"000", -- 0x2CB: - "000000" & X"000", -- 0x2CC: - "000000" & X"000", -- 0x2CD: - "000000" & X"000", -- 0x2CE: - "000000" & X"000", -- 0x2CF: - "000000" & X"000", -- 0x2D0: - "000000" & X"000", -- 0x2D1: - "000000" & X"000", -- 0x2D2: - "000000" & X"000", -- 0x2D3: - "000000" & X"000", -- 0x2D4: - "000000" & X"000", -- 0x2D5: - "000000" & X"000", -- 0x2D6: - "000000" & X"000", -- 0x2D7: - "000000" & X"000", -- 0x2D8: - "000000" & X"000", -- 0x2D9: - "000000" & X"000", -- 0x2DA: - "000000" & X"000", -- 0x2DB: - "000000" & X"000", -- 0x2DC: - "000000" & X"000", -- 0x2DD: - "000000" & X"000", -- 0x2DE: - "000000" & X"000", -- 0x2DF: - "000000" & X"000", -- 0x2E0: - "000000" & X"000", -- 0x2E1: - "000000" & X"000", -- 0x2E2: - "000000" & X"000", -- 0x2E3: - "000000" & X"000", -- 0x2E4: - "000000" & X"000", -- 0x2E5: - "000000" & X"000", -- 0x2E6: - "000000" & X"000", -- 0x2E7: - "000000" & X"000", -- 0x2E8: - "000000" & X"000", -- 0x2E9: - "000000" & X"000", -- 0x2EA: - "000000" & X"000", -- 0x2EB: - "000000" & X"000", -- 0x2EC: - "000000" & X"000", -- 0x2ED: - "000000" & X"000", -- 0x2EE: - "000000" & X"000", -- 0x2EF: - "000000" & X"000", -- 0x2F0: - "000000" & X"000", -- 0x2F1: - "000000" & X"000", -- 0x2F2: - "000000" & X"000", -- 0x2F3: - "000000" & X"000", -- 0x2F4: - "000000" & X"000", -- 0x2F5: - "000000" & X"000", -- 0x2F6: - "000000" & X"000", -- 0x2F7: - "000000" & X"000", -- 0x2F8: - "000000" & X"000", -- 0x2F9: - "000000" & X"000", -- 0x2FA: - "000000" & X"000", -- 0x2FB: - "000000" & X"000", -- 0x2FC: - "000000" & X"000", -- 0x2FD: - "000000" & X"000", -- 0x2FE: - "110000" & X"2FF", -- 0x2FF: JMP 0x2FF - "000000" & X"000", -- 0x300: - "000000" & X"000", -- 0x301: - "000000" & X"000", -- 0x302: - "000000" & X"000", -- 0x303: - "000000" & X"000", -- 0x304: - "000000" & X"000", -- 0x305: - "000000" & X"000", -- 0x306: - "000000" & X"000", -- 0x307: - "000000" & X"000", -- 0x308: - "000000" & X"000", -- 0x309: - "000000" & X"000", -- 0x30A: - "000000" & X"000", -- 0x30B: - "000000" & X"000", -- 0x30C: - "000000" & X"000", -- 0x30D: - "000000" & X"000", -- 0x30E: - "000000" & X"000", -- 0x30F: - "000000" & X"000", -- 0x310: - "000000" & X"000", -- 0x311: - "000000" & X"000", -- 0x312: - "000000" & X"000", -- 0x313: - "000000" & X"000", -- 0x314: - "000000" & X"000", -- 0x315: - "000000" & X"000", -- 0x316: - "000000" & X"000", -- 0x317: - "000000" & X"000", -- 0x318: - "000000" & X"000", -- 0x319: - "000000" & X"000", -- 0x31A: - "000000" & X"000", -- 0x31B: - "000000" & X"000", -- 0x31C: - "000000" & X"000", -- 0x31D: - "000000" & X"000", -- 0x31E: - "000000" & X"000", -- 0x31F: - "000000" & X"000", -- 0x320: - "000000" & X"000", -- 0x321: - "000000" & X"000", -- 0x322: - "000000" & X"000", -- 0x323: - "000000" & X"000", -- 0x324: - "000000" & X"000", -- 0x325: - "000000" & X"000", -- 0x326: - "000000" & X"000", -- 0x327: - "000000" & X"000", -- 0x328: - "000000" & X"000", -- 0x329: - "000000" & X"000", -- 0x32A: - "000000" & X"000", -- 0x32B: - "000000" & X"000", -- 0x32C: - "000000" & X"000", -- 0x32D: - "000000" & X"000", -- 0x32E: - "000000" & X"000", -- 0x32F: - "000000" & X"000", -- 0x330: - "000000" & X"000", -- 0x331: - "000000" & X"000", -- 0x332: - "000000" & X"000", -- 0x333: - "000000" & X"000", -- 0x334: - "000000" & X"000", -- 0x335: - "000000" & X"000", -- 0x336: - "000000" & X"000", -- 0x337: - "000000" & X"000", -- 0x338: - "000000" & X"000", -- 0x339: - "000000" & X"000", -- 0x33A: - "000000" & X"000", -- 0x33B: - "000000" & X"000", -- 0x33C: - "000000" & X"000", -- 0x33D: - "000000" & X"000", -- 0x33E: - "000000" & X"000", -- 0x33F: - "000000" & X"000", -- 0x340: - "000000" & X"000", -- 0x341: - "000000" & X"000", -- 0x342: - "000000" & X"000", -- 0x343: - "000000" & X"000", -- 0x344: - "000000" & X"000", -- 0x345: - "000000" & X"000", -- 0x346: - "000000" & X"000", -- 0x347: - "000000" & X"000", -- 0x348: - "000000" & X"000", -- 0x349: - "000000" & X"000", -- 0x34A: - "000000" & X"000", -- 0x34B: - "000000" & X"000", -- 0x34C: - "000000" & X"000", -- 0x34D: - "000000" & X"000", -- 0x34E: - "000000" & X"000", -- 0x34F: - "000000" & X"000", -- 0x350: - "000000" & X"000", -- 0x351: - "000000" & X"000", -- 0x352: - "000000" & X"000", -- 0x353: - "000000" & X"000", -- 0x354: - "000000" & X"000", -- 0x355: - "000000" & X"000", -- 0x356: - "000000" & X"000", -- 0x357: - "000000" & X"000", -- 0x358: - "000000" & X"000", -- 0x359: - "000000" & X"000", -- 0x35A: - "000000" & X"000", -- 0x35B: - "000000" & X"000", -- 0x35C: - "000000" & X"000", -- 0x35D: - "000000" & X"000", -- 0x35E: - "000000" & X"000", -- 0x35F: - "000000" & X"000", -- 0x360: - "000000" & X"000", -- 0x361: - "000000" & X"000", -- 0x362: - "000000" & X"000", -- 0x363: - "000000" & X"000", -- 0x364: - "000000" & X"000", -- 0x365: - "000000" & X"000", -- 0x366: - "000000" & X"000", -- 0x367: - "000000" & X"000", -- 0x368: - "000000" & X"000", -- 0x369: - "000000" & X"000", -- 0x36A: - "000000" & X"000", -- 0x36B: - "000000" & X"000", -- 0x36C: - "000000" & X"000", -- 0x36D: - "000000" & X"000", -- 0x36E: - "000000" & X"000", -- 0x36F: - "000000" & X"000", -- 0x370: - "000000" & X"000", -- 0x371: - "000000" & X"000", -- 0x372: - "000000" & X"000", -- 0x373: - "000000" & X"000", -- 0x374: - "000000" & X"000", -- 0x375: - "000000" & X"000", -- 0x376: - "000000" & X"000", -- 0x377: - "000000" & X"000", -- 0x378: - "000000" & X"000", -- 0x379: - "000000" & X"000", -- 0x37A: - "000000" & X"000", -- 0x37B: - "000000" & X"000", -- 0x37C: - "000000" & X"000", -- 0x37D: - "000000" & X"000", -- 0x37E: - "000000" & X"000", -- 0x37F: - "000000" & X"000", -- 0x380: - "000000" & X"000", -- 0x381: - "000000" & X"000", -- 0x382: - "000000" & X"000", -- 0x383: - "000000" & X"000", -- 0x384: - "000000" & X"000", -- 0x385: - "000000" & X"000", -- 0x386: - "000000" & X"000", -- 0x387: - "000000" & X"000", -- 0x388: - "000000" & X"000", -- 0x389: - "000000" & X"000", -- 0x38A: - "000000" & X"000", -- 0x38B: - "000000" & X"000", -- 0x38C: - "000000" & X"000", -- 0x38D: - "000000" & X"000", -- 0x38E: - "000000" & X"000", -- 0x38F: - "000000" & X"000", -- 0x390: - "000000" & X"000", -- 0x391: - "000000" & X"000", -- 0x392: - "000000" & X"000", -- 0x393: - "000000" & X"000", -- 0x394: - "000000" & X"000", -- 0x395: - "000000" & X"000", -- 0x396: - "000000" & X"000", -- 0x397: - "000000" & X"000", -- 0x398: - "000000" & X"000", -- 0x399: - "000000" & X"000", -- 0x39A: - "000000" & X"000", -- 0x39B: - "000000" & X"000", -- 0x39C: - "000000" & X"000", -- 0x39D: - "000000" & X"000", -- 0x39E: - "000000" & X"000", -- 0x39F: - "000000" & X"000", -- 0x3A0: - "000000" & X"000", -- 0x3A1: - "000000" & X"000", -- 0x3A2: - "000000" & X"000", -- 0x3A3: - "000000" & X"000", -- 0x3A4: - "000000" & X"000", -- 0x3A5: - "000000" & X"000", -- 0x3A6: - "000000" & X"000", -- 0x3A7: - "000000" & X"000", -- 0x3A8: - "000000" & X"000", -- 0x3A9: - "000000" & X"000", -- 0x3AA: - "000000" & X"000", -- 0x3AB: - "000000" & X"000", -- 0x3AC: - "000000" & X"000", -- 0x3AD: - "000000" & X"000", -- 0x3AE: - "000000" & X"000", -- 0x3AF: - "000000" & X"000", -- 0x3B0: - "000000" & X"000", -- 0x3B1: - "000000" & X"000", -- 0x3B2: - "000000" & X"000", -- 0x3B3: - "000000" & X"000", -- 0x3B4: - "000000" & X"000", -- 0x3B5: - "000000" & X"000", -- 0x3B6: - "000000" & X"000", -- 0x3B7: - "000000" & X"000", -- 0x3B8: - "000000" & X"000", -- 0x3B9: - "000000" & X"000", -- 0x3BA: - "000000" & X"000", -- 0x3BB: - "000000" & X"000", -- 0x3BC: - "000000" & X"000", -- 0x3BD: - "000000" & X"000", -- 0x3BE: - "000000" & X"000", -- 0x3BF: - "000000" & X"000", -- 0x3C0: - "000000" & X"000", -- 0x3C1: - "000000" & X"000", -- 0x3C2: - "000000" & X"000", -- 0x3C3: - "000000" & X"000", -- 0x3C4: - "000000" & X"000", -- 0x3C5: - "000000" & X"000", -- 0x3C6: - "000000" & X"000", -- 0x3C7: - "000000" & X"000", -- 0x3C8: - "000000" & X"000", -- 0x3C9: - "000000" & X"000", -- 0x3CA: - "000000" & X"000", -- 0x3CB: - "000000" & X"000", -- 0x3CC: - "000000" & X"000", -- 0x3CD: - "000000" & X"000", -- 0x3CE: - "000000" & X"000", -- 0x3CF: - "000000" & X"000", -- 0x3D0: - "000000" & X"000", -- 0x3D1: - "000000" & X"000", -- 0x3D2: - "000000" & X"000", -- 0x3D3: - "000000" & X"000", -- 0x3D4: - "000000" & X"000", -- 0x3D5: - "000000" & X"000", -- 0x3D6: - "000000" & X"000", -- 0x3D7: - "000000" & X"000", -- 0x3D8: - "000000" & X"000", -- 0x3D9: - "000000" & X"000", -- 0x3DA: - "000000" & X"000", -- 0x3DB: - "000000" & X"000", -- 0x3DC: - "000000" & X"000", -- 0x3DD: - "000000" & X"000", -- 0x3DE: - "000000" & X"000", -- 0x3DF: - "000000" & X"000", -- 0x3E0: - "000000" & X"000", -- 0x3E1: - "000000" & X"000", -- 0x3E2: - "000000" & X"000", -- 0x3E3: - "000000" & X"000", -- 0x3E4: - "000000" & X"000", -- 0x3E5: - "000000" & X"000", -- 0x3E6: - "000000" & X"000", -- 0x3E7: - "000000" & X"000", -- 0x3E8: - "000000" & X"000", -- 0x3E9: - "000000" & X"000", -- 0x3EA: - "000000" & X"000", -- 0x3EB: - "000000" & X"000", -- 0x3EC: - "000000" & X"000", -- 0x3ED: - "000000" & X"000", -- 0x3EE: - "000000" & X"000", -- 0x3EF: - "000000" & X"000", -- 0x3F0: - "000000" & X"000", -- 0x3F1: - "000000" & X"000", -- 0x3F2: - "000000" & X"000", -- 0x3F3: - "000000" & X"000", -- 0x3F4: - "000000" & X"000", -- 0x3F5: - "000000" & X"000", -- 0x3F6: - "000000" & X"000", -- 0x3F7: - "000000" & X"000", -- 0x3F8: - "000000" & X"000", -- 0x3F9: - "000000" & X"000", -- 0x3FA: - "000000" & X"000", -- 0x3FB: - "000000" & X"000", -- 0x3FC: - "000000" & X"000", -- 0x3FD: - "000000" & X"000", -- 0x3FE: - "110000" & X"3FF" -- 0x3FF: JMP 0x3FF - ); - - signal jtag_ld_clk : STD_LOGIC; - signal jtag_ld_we : STD_LOGIC; - signal jtag_ld_addr : inst_addr_t; - signal jtag_ld_dout : inst_t; - signal jtag_ld_din : inst_t; - signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic; - signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic; - signal user_regi, user_rego : unsigned (31 downto 0); - constant id : unsigned (31 downto 0) := X"BABE" & X"BEEF"; - -begin - --------------------------------------------------------------------------- --- Virtex-4: JTAG Loader --------------------------------------------------------------------------- - i00_BUFG : BUFG - port map - ( - O => bs_clk1, - I => bs_clk0 - ); - - i01_BUFG : BUFG - port map - ( - O => bs_update1, - I => bs_update0 - ); - - BSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 - generic map - ( - JTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4) - ) - port map - ( - CAPTURE => bs_capture, -- CAPTURE output from TAP controller - DRCK => bs_clk0, -- Data register output for USER functions - RESET => bs_rst, -- Reset output from TAP controller - SEL => bs_sel, -- USER active output - SHIFT => bs_shift, -- SHIFT output from TAP controller - TDI => bs_tdi, -- TDI output from TAP controller - UPDATE => bs_update0, -- UPDATE output from TAP controller - TDO => bs_tdo -- Data input for USER function - ); - - jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-inst_addr_t'length+1); - jtag_ld_din <= user_regi(inst_t'length-1 downto 0); - jtag_ld_clk <= bs_update1; - jtag_ld_we <= bs_sel; - -sipo: - process (bs_rst, bs_clk1, bs_tdi, bs_shift) - begin - if bs_rst = '1' then - user_regi <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_regi <= bs_tdi & user_regi(user_regi'left downto 1); - end if; - end if; - end process; - -piso: - process (bs_rst, bs_clk1, bs_shift, user_rego) - begin - bs_tdo <= user_rego(0); - if bs_rst = '1' then - user_rego <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_rego <= user_rego(0) & user_rego(user_rego'left downto 1); - else - user_rego <= (user_rego'left downto inst_t'length => '0') & jtag_ld_dout; --- user_rego <= id; - end if; - end if; - end process; - --------------------------------------------------------------------------- --- ROM Read/Write --------------------------------------------------------------------------- -PROM_READ: - process(clk, ce) - begin - if rising_edge(clk) and ce = '1' then - dout <= imem_rom(to_integer(addr)); - end if; - end process; - -PROM_WRITE: - process(jtag_ld_clk, jtag_ld_we) - begin - if rising_edge(jtag_ld_clk) then - if jtag_ld_we = '1' then - imem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din; - else - jtag_ld_dout <= imem_rom(to_integer(jtag_ld_addr)); - end if; - end if; - end process; - --------------------------------------------------------------------------- -end loadable; diff --git a/lib/CPUs/JCpu/src/itest_xrom.vhdl b/lib/CPUs/JCpu/src/itest_xrom.vhdl deleted file mode 100644 index 4206abc..0000000 --- a/lib/CPUs/JCpu/src/itest_xrom.vhdl +++ /dev/null @@ -1,317 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: The ROM file for use in your VHDL design --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library work; -use work.cpu_pkg.all; - --- JASM_ROM_INSERT_HERE -ENTITY xrom IS - Port ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - addr : in dmem_addr_t; - dout : out dmem_data_t - ); -END xrom; - -ARCHITECTURE itest OF xrom IS - - type xmem_rom_t is array (0 to 255) of dmem_data_t; - - -- Assembled from itest.jsm - constant xmem_rom : xmem_rom_t := - ( - X"48", -- 0x00 - X"61", -- 0x01 - X"6C", -- 0x02 - X"6C", -- 0x03 - X"6F", -- 0x04 - X"00", -- 0x05 - X"00", -- 0x06 - X"00", -- 0x07 - X"00", -- 0x08 - X"00", -- 0x09 - X"00", -- 0x0A - X"00", -- 0x0B - X"00", -- 0x0C - X"00", -- 0x0D - X"00", -- 0x0E - X"00", -- 0x0F - X"00", -- 0x10 - X"00", -- 0x11 - X"00", -- 0x12 - X"00", -- 0x13 - X"00", -- 0x14 - X"00", -- 0x15 - X"00", -- 0x16 - X"00", -- 0x17 - X"00", -- 0x18 - X"00", -- 0x19 - X"00", -- 0x1A - X"00", -- 0x1B - X"00", -- 0x1C - X"00", -- 0x1D - X"00", -- 0x1E - X"00", -- 0x1F - X"00", -- 0x20 - X"00", -- 0x21 - X"00", -- 0x22 - X"00", -- 0x23 - X"00", -- 0x24 - X"00", -- 0x25 - X"00", -- 0x26 - X"00", -- 0x27 - X"00", -- 0x28 - X"00", -- 0x29 - X"00", -- 0x2A - X"00", -- 0x2B - X"00", -- 0x2C - X"00", -- 0x2D - X"00", -- 0x2E - X"00", -- 0x2F - X"00", -- 0x30 - X"00", -- 0x31 - X"00", -- 0x32 - X"00", -- 0x33 - X"00", -- 0x34 - X"00", -- 0x35 - X"00", -- 0x36 - X"00", -- 0x37 - X"00", -- 0x38 - X"00", -- 0x39 - X"00", -- 0x3A - X"00", -- 0x3B - X"00", -- 0x3C - X"00", -- 0x3D - X"00", -- 0x3E - X"00", -- 0x3F - X"00", -- 0x40 - X"00", -- 0x41 - X"00", -- 0x42 - X"00", -- 0x43 - X"00", -- 0x44 - X"00", -- 0x45 - X"00", -- 0x46 - X"00", -- 0x47 - X"00", -- 0x48 - X"00", -- 0x49 - X"00", -- 0x4A - X"00", -- 0x4B - X"00", -- 0x4C - X"00", -- 0x4D - X"00", -- 0x4E - X"00", -- 0x4F - X"00", -- 0x50 - X"00", -- 0x51 - X"00", -- 0x52 - X"00", -- 0x53 - X"00", -- 0x54 - X"00", -- 0x55 - X"00", -- 0x56 - X"00", -- 0x57 - X"00", -- 0x58 - X"00", -- 0x59 - X"00", -- 0x5A - X"00", -- 0x5B - X"00", -- 0x5C - X"00", -- 0x5D - X"00", -- 0x5E - X"00", -- 0x5F - X"00", -- 0x60 - X"00", -- 0x61 - X"00", -- 0x62 - X"00", -- 0x63 - X"00", -- 0x64 - X"00", -- 0x65 - X"00", -- 0x66 - X"00", -- 0x67 - X"00", -- 0x68 - X"00", -- 0x69 - X"00", -- 0x6A - X"00", -- 0x6B - X"00", -- 0x6C - X"00", -- 0x6D - X"00", -- 0x6E - X"00", -- 0x6F - X"00", -- 0x70 - X"00", -- 0x71 - X"00", -- 0x72 - X"00", -- 0x73 - X"00", -- 0x74 - X"00", -- 0x75 - X"00", -- 0x76 - X"00", -- 0x77 - X"00", -- 0x78 - X"00", -- 0x79 - X"00", -- 0x7A - X"00", -- 0x7B - X"00", -- 0x7C - X"00", -- 0x7D - X"00", -- 0x7E - X"00", -- 0x7F - X"00", -- 0x80 - X"00", -- 0x81 - X"00", -- 0x82 - X"00", -- 0x83 - X"00", -- 0x84 - X"00", -- 0x85 - X"00", -- 0x86 - X"00", -- 0x87 - X"00", -- 0x88 - X"00", -- 0x89 - X"00", -- 0x8A - X"00", -- 0x8B - X"00", -- 0x8C - X"00", -- 0x8D - X"00", -- 0x8E - X"00", -- 0x8F - X"00", -- 0x90 - X"00", -- 0x91 - X"00", -- 0x92 - X"00", -- 0x93 - X"00", -- 0x94 - X"00", -- 0x95 - X"00", -- 0x96 - X"00", -- 0x97 - X"00", -- 0x98 - X"00", -- 0x99 - X"00", -- 0x9A - X"00", -- 0x9B - X"00", -- 0x9C - X"00", -- 0x9D - X"00", -- 0x9E - X"00", -- 0x9F - X"00", -- 0xA0 - X"00", -- 0xA1 - X"00", -- 0xA2 - X"00", -- 0xA3 - X"00", -- 0xA4 - X"00", -- 0xA5 - X"00", -- 0xA6 - X"00", -- 0xA7 - X"00", -- 0xA8 - X"00", -- 0xA9 - X"00", -- 0xAA - X"00", -- 0xAB - X"00", -- 0xAC - X"00", -- 0xAD - X"00", -- 0xAE - X"00", -- 0xAF - X"00", -- 0xB0 - X"00", -- 0xB1 - X"00", -- 0xB2 - X"00", -- 0xB3 - X"00", -- 0xB4 - X"00", -- 0xB5 - X"00", -- 0xB6 - X"00", -- 0xB7 - X"00", -- 0xB8 - X"00", -- 0xB9 - X"00", -- 0xBA - X"00", -- 0xBB - X"00", -- 0xBC - X"00", -- 0xBD - X"00", -- 0xBE - X"00", -- 0xBF - X"00", -- 0xC0 - X"00", -- 0xC1 - X"00", -- 0xC2 - X"00", -- 0xC3 - X"00", -- 0xC4 - X"00", -- 0xC5 - X"00", -- 0xC6 - X"00", -- 0xC7 - X"00", -- 0xC8 - X"00", -- 0xC9 - X"00", -- 0xCA - X"00", -- 0xCB - X"00", -- 0xCC - X"00", -- 0xCD - X"00", -- 0xCE - X"00", -- 0xCF - X"00", -- 0xD0 - X"00", -- 0xD1 - X"00", -- 0xD2 - X"00", -- 0xD3 - X"00", -- 0xD4 - X"00", -- 0xD5 - X"00", -- 0xD6 - X"00", -- 0xD7 - X"00", -- 0xD8 - X"00", -- 0xD9 - X"00", -- 0xDA - X"00", -- 0xDB - X"00", -- 0xDC - X"00", -- 0xDD - X"00", -- 0xDE - X"00", -- 0xDF - X"00", -- 0xE0 - X"00", -- 0xE1 - X"00", -- 0xE2 - X"00", -- 0xE3 - X"00", -- 0xE4 - X"00", -- 0xE5 - X"00", -- 0xE6 - X"00", -- 0xE7 - X"00", -- 0xE8 - X"00", -- 0xE9 - X"00", -- 0xEA - X"00", -- 0xEB - X"00", -- 0xEC - X"00", -- 0xED - X"00", -- 0xEE - X"00", -- 0xEF - X"00", -- 0xF0 - X"00", -- 0xF1 - X"00", -- 0xF2 - X"00", -- 0xF3 - X"00", -- 0xF4 - X"00", -- 0xF5 - X"00", -- 0xF6 - X"00", -- 0xF7 - X"00", -- 0xF8 - X"00", -- 0xF9 - X"00", -- 0xFA - X"00", -- 0xFB - X"00", -- 0xFC - X"00", -- 0xFD - X"00", -- 0xFE - X"00" -- 0xFF - ); - -begin - -PROM_READ: - process(clk, ce) - begin - if rising_edge(clk) and ce = '1' then - dout <= xmem_rom(to_integer(addr)); - end if; - end process; - -end itest; - diff --git a/lib/CPUs/JCpu/src/itest_xrom_ld.vhdl b/lib/CPUs/JCpu/src/itest_xrom_ld.vhdl deleted file mode 100644 index 60a84ac..0000000 --- a/lib/CPUs/JCpu/src/itest_xrom_ld.vhdl +++ /dev/null @@ -1,413 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: loadable ROM --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library UNISIM; -use UNISIM.VComponents.all; - -library work; -use work.cpu_pkg.all; - -ENTITY xrom IS - Port ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - addr : in dmem_addr_t; - dout : out dmem_data_t - ); - -END xrom; - -ARCHITECTURE loadable OF xrom IS - - -- JASM_ROM_INSERT_HERE - - -- Assembled from itest.jsm - type xmem_rom_t is array (0 to 255) of dmem_data_t; - signal xmem_rom : xmem_rom_t := - ( - X"48", -- 0x00 - X"61", -- 0x01 - X"6C", -- 0x02 - X"6C", -- 0x03 - X"6F", -- 0x04 - X"00", -- 0x05 - X"00", -- 0x06 - X"00", -- 0x07 - X"00", -- 0x08 - X"00", -- 0x09 - X"00", -- 0x0A - X"00", -- 0x0B - X"00", -- 0x0C - X"00", -- 0x0D - X"00", -- 0x0E - X"00", -- 0x0F - X"00", -- 0x10 - X"00", -- 0x11 - X"00", -- 0x12 - X"00", -- 0x13 - X"00", -- 0x14 - X"00", -- 0x15 - X"00", -- 0x16 - X"00", -- 0x17 - X"00", -- 0x18 - X"00", -- 0x19 - X"00", -- 0x1A - X"00", -- 0x1B - X"00", -- 0x1C - X"00", -- 0x1D - X"00", -- 0x1E - X"00", -- 0x1F - X"00", -- 0x20 - X"00", -- 0x21 - X"00", -- 0x22 - X"00", -- 0x23 - X"00", -- 0x24 - X"00", -- 0x25 - X"00", -- 0x26 - X"00", -- 0x27 - X"00", -- 0x28 - X"00", -- 0x29 - X"00", -- 0x2A - X"00", -- 0x2B - X"00", -- 0x2C - X"00", -- 0x2D - X"00", -- 0x2E - X"00", -- 0x2F - X"00", -- 0x30 - X"00", -- 0x31 - X"00", -- 0x32 - X"00", -- 0x33 - X"00", -- 0x34 - X"00", -- 0x35 - X"00", -- 0x36 - X"00", -- 0x37 - X"00", -- 0x38 - X"00", -- 0x39 - X"00", -- 0x3A - X"00", -- 0x3B - X"00", -- 0x3C - X"00", -- 0x3D - X"00", -- 0x3E - X"00", -- 0x3F - X"00", -- 0x40 - X"00", -- 0x41 - X"00", -- 0x42 - X"00", -- 0x43 - X"00", -- 0x44 - X"00", -- 0x45 - X"00", -- 0x46 - X"00", -- 0x47 - X"00", -- 0x48 - X"00", -- 0x49 - X"00", -- 0x4A - X"00", -- 0x4B - X"00", -- 0x4C - X"00", -- 0x4D - X"00", -- 0x4E - X"00", -- 0x4F - X"00", -- 0x50 - X"00", -- 0x51 - X"00", -- 0x52 - X"00", -- 0x53 - X"00", -- 0x54 - X"00", -- 0x55 - X"00", -- 0x56 - X"00", -- 0x57 - X"00", -- 0x58 - X"00", -- 0x59 - X"00", -- 0x5A - X"00", -- 0x5B - X"00", -- 0x5C - X"00", -- 0x5D - X"00", -- 0x5E - X"00", -- 0x5F - X"00", -- 0x60 - X"00", -- 0x61 - X"00", -- 0x62 - X"00", -- 0x63 - X"00", -- 0x64 - X"00", -- 0x65 - X"00", -- 0x66 - X"00", -- 0x67 - X"00", -- 0x68 - X"00", -- 0x69 - X"00", -- 0x6A - X"00", -- 0x6B - X"00", -- 0x6C - X"00", -- 0x6D - X"00", -- 0x6E - X"00", -- 0x6F - X"00", -- 0x70 - X"00", -- 0x71 - X"00", -- 0x72 - X"00", -- 0x73 - X"00", -- 0x74 - X"00", -- 0x75 - X"00", -- 0x76 - X"00", -- 0x77 - X"00", -- 0x78 - X"00", -- 0x79 - X"00", -- 0x7A - X"00", -- 0x7B - X"00", -- 0x7C - X"00", -- 0x7D - X"00", -- 0x7E - X"00", -- 0x7F - X"00", -- 0x80 - X"00", -- 0x81 - X"00", -- 0x82 - X"00", -- 0x83 - X"00", -- 0x84 - X"00", -- 0x85 - X"00", -- 0x86 - X"00", -- 0x87 - X"00", -- 0x88 - X"00", -- 0x89 - X"00", -- 0x8A - X"00", -- 0x8B - X"00", -- 0x8C - X"00", -- 0x8D - X"00", -- 0x8E - X"00", -- 0x8F - X"00", -- 0x90 - X"00", -- 0x91 - X"00", -- 0x92 - X"00", -- 0x93 - X"00", -- 0x94 - X"00", -- 0x95 - X"00", -- 0x96 - X"00", -- 0x97 - X"00", -- 0x98 - X"00", -- 0x99 - X"00", -- 0x9A - X"00", -- 0x9B - X"00", -- 0x9C - X"00", -- 0x9D - X"00", -- 0x9E - X"00", -- 0x9F - X"00", -- 0xA0 - X"00", -- 0xA1 - X"00", -- 0xA2 - X"00", -- 0xA3 - X"00", -- 0xA4 - X"00", -- 0xA5 - X"00", -- 0xA6 - X"00", -- 0xA7 - X"00", -- 0xA8 - X"00", -- 0xA9 - X"00", -- 0xAA - X"00", -- 0xAB - X"00", -- 0xAC - X"00", -- 0xAD - X"00", -- 0xAE - X"00", -- 0xAF - X"00", -- 0xB0 - X"00", -- 0xB1 - X"00", -- 0xB2 - X"00", -- 0xB3 - X"00", -- 0xB4 - X"00", -- 0xB5 - X"00", -- 0xB6 - X"00", -- 0xB7 - X"00", -- 0xB8 - X"00", -- 0xB9 - X"00", -- 0xBA - X"00", -- 0xBB - X"00", -- 0xBC - X"00", -- 0xBD - X"00", -- 0xBE - X"00", -- 0xBF - X"00", -- 0xC0 - X"00", -- 0xC1 - X"00", -- 0xC2 - X"00", -- 0xC3 - X"00", -- 0xC4 - X"00", -- 0xC5 - X"00", -- 0xC6 - X"00", -- 0xC7 - X"00", -- 0xC8 - X"00", -- 0xC9 - X"00", -- 0xCA - X"00", -- 0xCB - X"00", -- 0xCC - X"00", -- 0xCD - X"00", -- 0xCE - X"00", -- 0xCF - X"00", -- 0xD0 - X"00", -- 0xD1 - X"00", -- 0xD2 - X"00", -- 0xD3 - X"00", -- 0xD4 - X"00", -- 0xD5 - X"00", -- 0xD6 - X"00", -- 0xD7 - X"00", -- 0xD8 - X"00", -- 0xD9 - X"00", -- 0xDA - X"00", -- 0xDB - X"00", -- 0xDC - X"00", -- 0xDD - X"00", -- 0xDE - X"00", -- 0xDF - X"00", -- 0xE0 - X"00", -- 0xE1 - X"00", -- 0xE2 - X"00", -- 0xE3 - X"00", -- 0xE4 - X"00", -- 0xE5 - X"00", -- 0xE6 - X"00", -- 0xE7 - X"00", -- 0xE8 - X"00", -- 0xE9 - X"00", -- 0xEA - X"00", -- 0xEB - X"00", -- 0xEC - X"00", -- 0xED - X"00", -- 0xEE - X"00", -- 0xEF - X"00", -- 0xF0 - X"00", -- 0xF1 - X"00", -- 0xF2 - X"00", -- 0xF3 - X"00", -- 0xF4 - X"00", -- 0xF5 - X"00", -- 0xF6 - X"00", -- 0xF7 - X"00", -- 0xF8 - X"00", -- 0xF9 - X"00", -- 0xFA - X"00", -- 0xFB - X"00", -- 0xFC - X"00", -- 0xFD - X"00", -- 0xFE - X"00" -- 0xFF - ); - - signal jtag_ld_clk : STD_LOGIC; - signal jtag_ld_we : STD_LOGIC; - signal jtag_ld_addr : dmem_addr_t; - signal jtag_ld_dout : dmem_data_t; - signal jtag_ld_din : dmem_data_t; - signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic; - signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic; - signal user_regi, user_rego : unsigned (15 downto 0); - constant id : unsigned (15 downto 0) := X"BEEF"; - -begin - --------------------------------------------------------------------------- --- Virtex-4: JTAG Loader --------------------------------------------------------------------------- - i00_BUFG : BUFG - port map - ( - O => bs_clk1, - I => bs_clk0 - ); - - i01_BUFG : BUFG - port map - ( - O => bs_update1, - I => bs_update0 - ); - - BSCAN_VIRTEX4_inst2 : BSCAN_VIRTEX4 - generic map - ( - JTAG_CHAIN => 2 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4) - ) - port map - ( - CAPTURE => bs_capture, -- CAPTURE output from TAP controller - DRCK => bs_clk0, -- Data register output for USER functions - RESET => bs_rst, -- Reset output from TAP controller - SEL => bs_sel, -- USER active output - SHIFT => bs_shift, -- SHIFT output from TAP controller - TDI => bs_tdi, -- TDI output from TAP controller - UPDATE => bs_update0, -- UPDATE output from TAP controller - TDO => bs_tdo -- Data input for USER function - ); - - jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-dmem_data_t'length+1); - jtag_ld_din <= user_regi(dmem_data_t'left downto 0); - jtag_ld_clk <= bs_update1; - jtag_ld_we <= bs_sel; - -sipo: - process (bs_rst, bs_clk1, bs_tdi, bs_shift) - begin - if bs_rst = '1' then - user_regi <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_regi <= bs_tdi & user_regi(user_regi'left downto 1); - end if; - end if; - end process; - -piso: - process (bs_rst, bs_clk1, bs_shift, user_rego) - begin - bs_tdo <= user_rego(0); - if bs_rst = '1' then - user_rego <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_rego <= user_rego(0) & user_rego(user_rego'left downto 1); - else - user_rego <= (user_rego'left downto dmem_data_t'length => '0') & jtag_ld_dout; --- user_rego <= id; - end if; - end if; - end process; - --------------------------------------------------------------------------- --- ROM Read/Write --------------------------------------------------------------------------- -PROM_READ: - process(clk, ce) - begin - if rising_edge(clk) and ce = '1' then - dout <= xmem_rom(to_integer(addr)); - end if; - end process; - -PROM_WRITE: - process(jtag_ld_clk, jtag_ld_we) - begin - if rising_edge(jtag_ld_clk) then - if jtag_ld_we = '1' then - xmem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din; - else - jtag_ld_dout <= xmem_rom(to_integer(jtag_ld_addr)); - end if; - end if; - end process; - --------------------------------------------------------------------------- -end loadable; diff --git a/lib/CPUs/JCpu/src/mul8x8_irom.vhdl b/lib/CPUs/JCpu/src/mul8x8_irom.vhdl deleted file mode 100644 index 3b0de3b..0000000 --- a/lib/CPUs/JCpu/src/mul8x8_irom.vhdl +++ /dev/null @@ -1,88 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: The ROM file for use in your VHDL design --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library work; -use work.cpu_pkg.all; - --- JASM_ROM_INSERT_HERE -ENTITY irom IS - Port ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - addr : in inst_addr_t; - dout : out inst_t - ); -END irom; - -ARCHITECTURE mul8x8 OF irom IS - - type imem_rom_t is array (0 to 26) of inst_t; - - -- Assembled from mul8x8.jsm - constant imem_rom : imem_rom_t := - ( - "110000" & X"001", -- 0x000: JMP 0x001 - "000011" & X"450", -- 0x001: MOV R00, 0x45 - "000011" & X"F51", -- 0x002: MOV R01, 0xF5 - "111011" & X"005", -- 0x003: CALL 0x005 - "110000" & X"004", -- 0x004: JMP 0x004 - "111100" & X"002", -- 0x005: PUSH R02 - "111100" & X"003", -- 0x006: PUSH R03 - "111100" & X"004", -- 0x007: PUSH R04 - "000010" & X"014", -- 0x008: MOV R04, R01 - "000011" & X"001", -- 0x009: MOV R01, 0x00 - "000011" & X"002", -- 0x00A: MOV R02, 0x00 - "000011" & X"003", -- 0x00B: MOV R03, 0x00 - "001111" & X"014", -- 0x00C: CMP R04, 0x01 - "111001" & X"015", -- 0x00D: JEQ 0x015 - "011111" & X"004", -- 0x00E: SHR R04 - "110100" & X"012", -- 0x00F: JNC 0x012 - "010000" & X"002", -- 0x010: ADD R02, R00 - "010010" & X"013", -- 0x011: ADDC R03, R01 - "011110" & X"000", -- 0x012: SHL R00 - "100010" & X"001", -- 0x013: ROLC R01 - "110000" & X"00C", -- 0x014: JMP 0x00C - "010000" & X"020", -- 0x015: ADD R00, R02 - "010010" & X"031", -- 0x016: ADDC R01, R03 - "111101" & X"004", -- 0x017: POP R04 - "111101" & X"003", -- 0x018: POP R03 - "111101" & X"002", -- 0x019: POP R02 - "111110" & X"000" -- 0x01A: RET - ); - -begin - -PROM_READ: - process(clk, ce) - begin - if rising_edge(clk) and ce = '1' then - dout <= imem_rom(to_integer(addr)); - end if; - end process; - -end mul8x8; - diff --git a/lib/CPUs/JCpu/src/mul8x8_irom_ld.vhdl b/lib/CPUs/JCpu/src/mul8x8_irom_ld.vhdl deleted file mode 100644 index 4303d08..0000000 --- a/lib/CPUs/JCpu/src/mul8x8_irom_ld.vhdl +++ /dev/null @@ -1,1181 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: loadable ROM --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library UNISIM; -use UNISIM.VComponents.all; - -library work; -use work.cpu_pkg.all; - -ENTITY irom IS - Port ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - addr : in inst_addr_t; - dout : out inst_t - ); - -END irom; - -ARCHITECTURE loadable OF irom IS - - -- JASM_ROM_INSERT_HERE - - -- Assembled from mul8x8.jsm - type imem_rom_t is array (0 to 1023) of inst_t; - signal imem_rom : imem_rom_t := - ( - "110000" & X"001", -- 0x000: JMP 0x001 - "000011" & X"450", -- 0x001: MOV R00, 0x45 - "000011" & X"F51", -- 0x002: MOV R01, 0xF5 - "111011" & X"005", -- 0x003: CALL 0x005 - "110000" & X"004", -- 0x004: JMP 0x004 - "111100" & X"002", -- 0x005: PUSH R02 - "111100" & X"003", -- 0x006: PUSH R03 - "111100" & X"004", -- 0x007: PUSH R04 - "000010" & X"014", -- 0x008: MOV R04, R01 - "000011" & X"001", -- 0x009: MOV R01, 0x00 - "000011" & X"002", -- 0x00A: MOV R02, 0x00 - "000011" & X"003", -- 0x00B: MOV R03, 0x00 - "001111" & X"014", -- 0x00C: CMP R04, 0x01 - "111001" & X"015", -- 0x00D: JEQ 0x015 - "011111" & X"004", -- 0x00E: SHR R04 - "110100" & X"012", -- 0x00F: JNC 0x012 - "010000" & X"002", -- 0x010: ADD R02, R00 - "010010" & X"013", -- 0x011: ADDC R03, R01 - "011110" & X"000", -- 0x012: SHL R00 - "100010" & X"001", -- 0x013: ROLC R01 - "110000" & X"00C", -- 0x014: JMP 0x00C - "010000" & X"020", -- 0x015: ADD R00, R02 - "010010" & X"031", -- 0x016: ADDC R01, R03 - "111101" & X"004", -- 0x017: POP R04 - "111101" & X"003", -- 0x018: POP R03 - "111101" & X"002", -- 0x019: POP R02 - "111110" & X"000", -- 0x01A: RET - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000" - ); - - signal jtag_ld_clk : STD_LOGIC; - signal jtag_ld_we : STD_LOGIC; - signal jtag_ld_addr : inst_addr_t; - signal jtag_ld_dout : inst_t; - signal jtag_ld_din : inst_t; - signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic; - signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic; - signal user_regi, user_rego : unsigned (31 downto 0); - constant id : unsigned (31 downto 0) := X"BABE" & X"BEEF"; - -begin - --------------------------------------------------------------------------- --- Virtex-4: JTAG Loader --------------------------------------------------------------------------- - i00_BUFG : BUFG - port map - ( - O => bs_clk1, - I => bs_clk0 - ); - - i01_BUFG : BUFG - port map - ( - O => bs_update1, - I => bs_update0 - ); - - BSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 - generic map - ( - JTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4) - ) - port map - ( - CAPTURE => bs_capture, -- CAPTURE output from TAP controller - DRCK => bs_clk0, -- Data register output for USER functions - RESET => bs_rst, -- Reset output from TAP controller - SEL => bs_sel, -- USER active output - SHIFT => bs_shift, -- SHIFT output from TAP controller - TDI => bs_tdi, -- TDI output from TAP controller - UPDATE => bs_update0, -- UPDATE output from TAP controller - TDO => bs_tdo -- Data input for USER function - ); - - jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-inst_addr_t'length+1); - jtag_ld_din <= user_regi(inst_t'length-1 downto 0); - jtag_ld_clk <= bs_update1; - jtag_ld_we <= bs_sel; - -sipo: - process (bs_rst, bs_clk1, bs_tdi, bs_shift) - begin - if bs_rst = '1' then - user_regi <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_regi <= bs_tdi & user_regi(user_regi'left downto 1); - end if; - end if; - end process; - -piso: - process (bs_rst, bs_clk1, bs_shift, user_rego) - begin - bs_tdo <= user_rego(0); - if bs_rst = '1' then - user_rego <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_rego <= user_rego(0) & user_rego(user_rego'left downto 1); - else - user_rego <= (user_rego'left downto inst_t'length => '0') & jtag_ld_dout; --- user_rego <= id; - end if; - end if; - end process; - --------------------------------------------------------------------------- --- ROM Read/Write --------------------------------------------------------------------------- -PROM_READ: - process(clk, ce) - begin - if rising_edge(clk) and ce = '1' then - dout <= imem_rom(to_integer(addr)); - end if; - end process; - -PROM_WRITE: - process(jtag_ld_clk, jtag_ld_we) - begin - if rising_edge(jtag_ld_clk) then - if jtag_ld_we = '1' then - imem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din; - else - jtag_ld_dout <= imem_rom(to_integer(jtag_ld_addr)); - end if; - end if; - end process; - --------------------------------------------------------------------------- -end loadable; diff --git a/lib/CPUs/JCpu/src/mul8x8_xrom.vhdl b/lib/CPUs/JCpu/src/mul8x8_xrom.vhdl deleted file mode 100644 index 508e8cf..0000000 --- a/lib/CPUs/JCpu/src/mul8x8_xrom.vhdl +++ /dev/null @@ -1,317 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: The ROM file for use in your VHDL design --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library work; -use work.cpu_pkg.all; - --- JASM_ROM_INSERT_HERE -ENTITY xrom IS - Port ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - addr : in dmem_addr_t; - dout : out dmem_data_t - ); -END xrom; - -ARCHITECTURE mul8x8 OF xrom IS - - type xmem_rom_t is array (0 to 255) of dmem_data_t; - - -- Assembled from mul8x8.jsm - constant xmem_rom : xmem_rom_t := - ( - X"00", -- 0x00 - X"00", -- 0x01 - X"00", -- 0x02 - X"00", -- 0x03 - X"00", -- 0x04 - X"00", -- 0x05 - X"00", -- 0x06 - X"00", -- 0x07 - X"00", -- 0x08 - X"00", -- 0x09 - X"00", -- 0x0A - X"00", -- 0x0B - X"00", -- 0x0C - X"00", -- 0x0D - X"00", -- 0x0E - X"00", -- 0x0F - X"00", -- 0x10 - X"00", -- 0x11 - X"00", -- 0x12 - X"00", -- 0x13 - X"00", -- 0x14 - X"00", -- 0x15 - X"00", -- 0x16 - X"00", -- 0x17 - X"00", -- 0x18 - X"00", -- 0x19 - X"00", -- 0x1A - X"00", -- 0x1B - X"00", -- 0x1C - X"00", -- 0x1D - X"00", -- 0x1E - X"00", -- 0x1F - X"00", -- 0x20 - X"00", -- 0x21 - X"00", -- 0x22 - X"00", -- 0x23 - X"00", -- 0x24 - X"00", -- 0x25 - X"00", -- 0x26 - X"00", -- 0x27 - X"00", -- 0x28 - X"00", -- 0x29 - X"00", -- 0x2A - X"00", -- 0x2B - X"00", -- 0x2C - X"00", -- 0x2D - X"00", -- 0x2E - X"00", -- 0x2F - X"00", -- 0x30 - X"00", -- 0x31 - X"00", -- 0x32 - X"00", -- 0x33 - X"00", -- 0x34 - X"00", -- 0x35 - X"00", -- 0x36 - X"00", -- 0x37 - X"00", -- 0x38 - X"00", -- 0x39 - X"00", -- 0x3A - X"00", -- 0x3B - X"00", -- 0x3C - X"00", -- 0x3D - X"00", -- 0x3E - X"00", -- 0x3F - X"00", -- 0x40 - X"00", -- 0x41 - X"00", -- 0x42 - X"00", -- 0x43 - X"00", -- 0x44 - X"00", -- 0x45 - X"00", -- 0x46 - X"00", -- 0x47 - X"00", -- 0x48 - X"00", -- 0x49 - X"00", -- 0x4A - X"00", -- 0x4B - X"00", -- 0x4C - X"00", -- 0x4D - X"00", -- 0x4E - X"00", -- 0x4F - X"00", -- 0x50 - X"00", -- 0x51 - X"00", -- 0x52 - X"00", -- 0x53 - X"00", -- 0x54 - X"00", -- 0x55 - X"00", -- 0x56 - X"00", -- 0x57 - X"00", -- 0x58 - X"00", -- 0x59 - X"00", -- 0x5A - X"00", -- 0x5B - X"00", -- 0x5C - X"00", -- 0x5D - X"00", -- 0x5E - X"00", -- 0x5F - X"00", -- 0x60 - X"00", -- 0x61 - X"00", -- 0x62 - X"00", -- 0x63 - X"00", -- 0x64 - X"00", -- 0x65 - X"00", -- 0x66 - X"00", -- 0x67 - X"00", -- 0x68 - X"00", -- 0x69 - X"00", -- 0x6A - X"00", -- 0x6B - X"00", -- 0x6C - X"00", -- 0x6D - X"00", -- 0x6E - X"00", -- 0x6F - X"00", -- 0x70 - X"00", -- 0x71 - X"00", -- 0x72 - X"00", -- 0x73 - X"00", -- 0x74 - X"00", -- 0x75 - X"00", -- 0x76 - X"00", -- 0x77 - X"00", -- 0x78 - X"00", -- 0x79 - X"00", -- 0x7A - X"00", -- 0x7B - X"00", -- 0x7C - X"00", -- 0x7D - X"00", -- 0x7E - X"00", -- 0x7F - X"00", -- 0x80 - X"00", -- 0x81 - X"00", -- 0x82 - X"00", -- 0x83 - X"00", -- 0x84 - X"00", -- 0x85 - X"00", -- 0x86 - X"00", -- 0x87 - X"00", -- 0x88 - X"00", -- 0x89 - X"00", -- 0x8A - X"00", -- 0x8B - X"00", -- 0x8C - X"00", -- 0x8D - X"00", -- 0x8E - X"00", -- 0x8F - X"00", -- 0x90 - X"00", -- 0x91 - X"00", -- 0x92 - X"00", -- 0x93 - X"00", -- 0x94 - X"00", -- 0x95 - X"00", -- 0x96 - X"00", -- 0x97 - X"00", -- 0x98 - X"00", -- 0x99 - X"00", -- 0x9A - X"00", -- 0x9B - X"00", -- 0x9C - X"00", -- 0x9D - X"00", -- 0x9E - X"00", -- 0x9F - X"00", -- 0xA0 - X"00", -- 0xA1 - X"00", -- 0xA2 - X"00", -- 0xA3 - X"00", -- 0xA4 - X"00", -- 0xA5 - X"00", -- 0xA6 - X"00", -- 0xA7 - X"00", -- 0xA8 - X"00", -- 0xA9 - X"00", -- 0xAA - X"00", -- 0xAB - X"00", -- 0xAC - X"00", -- 0xAD - X"00", -- 0xAE - X"00", -- 0xAF - X"00", -- 0xB0 - X"00", -- 0xB1 - X"00", -- 0xB2 - X"00", -- 0xB3 - X"00", -- 0xB4 - X"00", -- 0xB5 - X"00", -- 0xB6 - X"00", -- 0xB7 - X"00", -- 0xB8 - X"00", -- 0xB9 - X"00", -- 0xBA - X"00", -- 0xBB - X"00", -- 0xBC - X"00", -- 0xBD - X"00", -- 0xBE - X"00", -- 0xBF - X"00", -- 0xC0 - X"00", -- 0xC1 - X"00", -- 0xC2 - X"00", -- 0xC3 - X"00", -- 0xC4 - X"00", -- 0xC5 - X"00", -- 0xC6 - X"00", -- 0xC7 - X"00", -- 0xC8 - X"00", -- 0xC9 - X"00", -- 0xCA - X"00", -- 0xCB - X"00", -- 0xCC - X"00", -- 0xCD - X"00", -- 0xCE - X"00", -- 0xCF - X"00", -- 0xD0 - X"00", -- 0xD1 - X"00", -- 0xD2 - X"00", -- 0xD3 - X"00", -- 0xD4 - X"00", -- 0xD5 - X"00", -- 0xD6 - X"00", -- 0xD7 - X"00", -- 0xD8 - X"00", -- 0xD9 - X"00", -- 0xDA - X"00", -- 0xDB - X"00", -- 0xDC - X"00", -- 0xDD - X"00", -- 0xDE - X"00", -- 0xDF - X"00", -- 0xE0 - X"00", -- 0xE1 - X"00", -- 0xE2 - X"00", -- 0xE3 - X"00", -- 0xE4 - X"00", -- 0xE5 - X"00", -- 0xE6 - X"00", -- 0xE7 - X"00", -- 0xE8 - X"00", -- 0xE9 - X"00", -- 0xEA - X"00", -- 0xEB - X"00", -- 0xEC - X"00", -- 0xED - X"00", -- 0xEE - X"00", -- 0xEF - X"00", -- 0xF0 - X"00", -- 0xF1 - X"00", -- 0xF2 - X"00", -- 0xF3 - X"00", -- 0xF4 - X"00", -- 0xF5 - X"00", -- 0xF6 - X"00", -- 0xF7 - X"00", -- 0xF8 - X"00", -- 0xF9 - X"00", -- 0xFA - X"00", -- 0xFB - X"00", -- 0xFC - X"00", -- 0xFD - X"00", -- 0xFE - X"00" -- 0xFF - ); - -begin - -PROM_READ: - process(clk, ce) - begin - if rising_edge(clk) and ce = '1' then - dout <= xmem_rom(to_integer(addr)); - end if; - end process; - -end mul8x8; - diff --git a/lib/CPUs/JCpu/src/mul8x8_xrom_ld.vhdl b/lib/CPUs/JCpu/src/mul8x8_xrom_ld.vhdl deleted file mode 100644 index a75d090..0000000 --- a/lib/CPUs/JCpu/src/mul8x8_xrom_ld.vhdl +++ /dev/null @@ -1,413 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: loadable ROM --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library UNISIM; -use UNISIM.VComponents.all; - -library work; -use work.cpu_pkg.all; - -ENTITY xrom IS - Port ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - addr : in dmem_addr_t; - dout : out dmem_data_t - ); - -END xrom; - -ARCHITECTURE loadable OF xrom IS - - -- JASM_ROM_INSERT_HERE - - -- Assembled from mul8x8.jsm - type xmem_rom_t is array (0 to 255) of dmem_data_t; - signal xmem_rom : xmem_rom_t := - ( - X"00", -- 0x00 - X"00", -- 0x01 - X"00", -- 0x02 - X"00", -- 0x03 - X"00", -- 0x04 - X"00", -- 0x05 - X"00", -- 0x06 - X"00", -- 0x07 - X"00", -- 0x08 - X"00", -- 0x09 - X"00", -- 0x0A - X"00", -- 0x0B - X"00", -- 0x0C - X"00", -- 0x0D - X"00", -- 0x0E - X"00", -- 0x0F - X"00", -- 0x10 - X"00", -- 0x11 - X"00", -- 0x12 - X"00", -- 0x13 - X"00", -- 0x14 - X"00", -- 0x15 - X"00", -- 0x16 - X"00", -- 0x17 - X"00", -- 0x18 - X"00", -- 0x19 - X"00", -- 0x1A - X"00", -- 0x1B - X"00", -- 0x1C - X"00", -- 0x1D - X"00", -- 0x1E - X"00", -- 0x1F - X"00", -- 0x20 - X"00", -- 0x21 - X"00", -- 0x22 - X"00", -- 0x23 - X"00", -- 0x24 - X"00", -- 0x25 - X"00", -- 0x26 - X"00", -- 0x27 - X"00", -- 0x28 - X"00", -- 0x29 - X"00", -- 0x2A - X"00", -- 0x2B - X"00", -- 0x2C - X"00", -- 0x2D - X"00", -- 0x2E - X"00", -- 0x2F - X"00", -- 0x30 - X"00", -- 0x31 - X"00", -- 0x32 - X"00", -- 0x33 - X"00", -- 0x34 - X"00", -- 0x35 - X"00", -- 0x36 - X"00", -- 0x37 - X"00", -- 0x38 - X"00", -- 0x39 - X"00", -- 0x3A - X"00", -- 0x3B - X"00", -- 0x3C - X"00", -- 0x3D - X"00", -- 0x3E - X"00", -- 0x3F - X"00", -- 0x40 - X"00", -- 0x41 - X"00", -- 0x42 - X"00", -- 0x43 - X"00", -- 0x44 - X"00", -- 0x45 - X"00", -- 0x46 - X"00", -- 0x47 - X"00", -- 0x48 - X"00", -- 0x49 - X"00", -- 0x4A - X"00", -- 0x4B - X"00", -- 0x4C - X"00", -- 0x4D - X"00", -- 0x4E - X"00", -- 0x4F - X"00", -- 0x50 - X"00", -- 0x51 - X"00", -- 0x52 - X"00", -- 0x53 - X"00", -- 0x54 - X"00", -- 0x55 - X"00", -- 0x56 - X"00", -- 0x57 - X"00", -- 0x58 - X"00", -- 0x59 - X"00", -- 0x5A - X"00", -- 0x5B - X"00", -- 0x5C - X"00", -- 0x5D - X"00", -- 0x5E - X"00", -- 0x5F - X"00", -- 0x60 - X"00", -- 0x61 - X"00", -- 0x62 - X"00", -- 0x63 - X"00", -- 0x64 - X"00", -- 0x65 - X"00", -- 0x66 - X"00", -- 0x67 - X"00", -- 0x68 - X"00", -- 0x69 - X"00", -- 0x6A - X"00", -- 0x6B - X"00", -- 0x6C - X"00", -- 0x6D - X"00", -- 0x6E - X"00", -- 0x6F - X"00", -- 0x70 - X"00", -- 0x71 - X"00", -- 0x72 - X"00", -- 0x73 - X"00", -- 0x74 - X"00", -- 0x75 - X"00", -- 0x76 - X"00", -- 0x77 - X"00", -- 0x78 - X"00", -- 0x79 - X"00", -- 0x7A - X"00", -- 0x7B - X"00", -- 0x7C - X"00", -- 0x7D - X"00", -- 0x7E - X"00", -- 0x7F - X"00", -- 0x80 - X"00", -- 0x81 - X"00", -- 0x82 - X"00", -- 0x83 - X"00", -- 0x84 - X"00", -- 0x85 - X"00", -- 0x86 - X"00", -- 0x87 - X"00", -- 0x88 - X"00", -- 0x89 - X"00", -- 0x8A - X"00", -- 0x8B - X"00", -- 0x8C - X"00", -- 0x8D - X"00", -- 0x8E - X"00", -- 0x8F - X"00", -- 0x90 - X"00", -- 0x91 - X"00", -- 0x92 - X"00", -- 0x93 - X"00", -- 0x94 - X"00", -- 0x95 - X"00", -- 0x96 - X"00", -- 0x97 - X"00", -- 0x98 - X"00", -- 0x99 - X"00", -- 0x9A - X"00", -- 0x9B - X"00", -- 0x9C - X"00", -- 0x9D - X"00", -- 0x9E - X"00", -- 0x9F - X"00", -- 0xA0 - X"00", -- 0xA1 - X"00", -- 0xA2 - X"00", -- 0xA3 - X"00", -- 0xA4 - X"00", -- 0xA5 - X"00", -- 0xA6 - X"00", -- 0xA7 - X"00", -- 0xA8 - X"00", -- 0xA9 - X"00", -- 0xAA - X"00", -- 0xAB - X"00", -- 0xAC - X"00", -- 0xAD - X"00", -- 0xAE - X"00", -- 0xAF - X"00", -- 0xB0 - X"00", -- 0xB1 - X"00", -- 0xB2 - X"00", -- 0xB3 - X"00", -- 0xB4 - X"00", -- 0xB5 - X"00", -- 0xB6 - X"00", -- 0xB7 - X"00", -- 0xB8 - X"00", -- 0xB9 - X"00", -- 0xBA - X"00", -- 0xBB - X"00", -- 0xBC - X"00", -- 0xBD - X"00", -- 0xBE - X"00", -- 0xBF - X"00", -- 0xC0 - X"00", -- 0xC1 - X"00", -- 0xC2 - X"00", -- 0xC3 - X"00", -- 0xC4 - X"00", -- 0xC5 - X"00", -- 0xC6 - X"00", -- 0xC7 - X"00", -- 0xC8 - X"00", -- 0xC9 - X"00", -- 0xCA - X"00", -- 0xCB - X"00", -- 0xCC - X"00", -- 0xCD - X"00", -- 0xCE - X"00", -- 0xCF - X"00", -- 0xD0 - X"00", -- 0xD1 - X"00", -- 0xD2 - X"00", -- 0xD3 - X"00", -- 0xD4 - X"00", -- 0xD5 - X"00", -- 0xD6 - X"00", -- 0xD7 - X"00", -- 0xD8 - X"00", -- 0xD9 - X"00", -- 0xDA - X"00", -- 0xDB - X"00", -- 0xDC - X"00", -- 0xDD - X"00", -- 0xDE - X"00", -- 0xDF - X"00", -- 0xE0 - X"00", -- 0xE1 - X"00", -- 0xE2 - X"00", -- 0xE3 - X"00", -- 0xE4 - X"00", -- 0xE5 - X"00", -- 0xE6 - X"00", -- 0xE7 - X"00", -- 0xE8 - X"00", -- 0xE9 - X"00", -- 0xEA - X"00", -- 0xEB - X"00", -- 0xEC - X"00", -- 0xED - X"00", -- 0xEE - X"00", -- 0xEF - X"00", -- 0xF0 - X"00", -- 0xF1 - X"00", -- 0xF2 - X"00", -- 0xF3 - X"00", -- 0xF4 - X"00", -- 0xF5 - X"00", -- 0xF6 - X"00", -- 0xF7 - X"00", -- 0xF8 - X"00", -- 0xF9 - X"00", -- 0xFA - X"00", -- 0xFB - X"00", -- 0xFC - X"00", -- 0xFD - X"00", -- 0xFE - X"00" -- 0xFF - ); - - signal jtag_ld_clk : STD_LOGIC; - signal jtag_ld_we : STD_LOGIC; - signal jtag_ld_addr : dmem_addr_t; - signal jtag_ld_dout : dmem_data_t; - signal jtag_ld_din : dmem_data_t; - signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic; - signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic; - signal user_regi, user_rego : unsigned (15 downto 0); - constant id : unsigned (15 downto 0) := X"BEEF"; - -begin - --------------------------------------------------------------------------- --- Virtex-4: JTAG Loader --------------------------------------------------------------------------- - i00_BUFG : BUFG - port map - ( - O => bs_clk1, - I => bs_clk0 - ); - - i01_BUFG : BUFG - port map - ( - O => bs_update1, - I => bs_update0 - ); - - BSCAN_VIRTEX4_inst2 : BSCAN_VIRTEX4 - generic map - ( - JTAG_CHAIN => 2 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4) - ) - port map - ( - CAPTURE => bs_capture, -- CAPTURE output from TAP controller - DRCK => bs_clk0, -- Data register output for USER functions - RESET => bs_rst, -- Reset output from TAP controller - SEL => bs_sel, -- USER active output - SHIFT => bs_shift, -- SHIFT output from TAP controller - TDI => bs_tdi, -- TDI output from TAP controller - UPDATE => bs_update0, -- UPDATE output from TAP controller - TDO => bs_tdo -- Data input for USER function - ); - - jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-dmem_data_t'length+1); - jtag_ld_din <= user_regi(dmem_data_t'left downto 0); - jtag_ld_clk <= bs_update1; - jtag_ld_we <= bs_sel; - -sipo: - process (bs_rst, bs_clk1, bs_tdi, bs_shift) - begin - if bs_rst = '1' then - user_regi <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_regi <= bs_tdi & user_regi(user_regi'left downto 1); - end if; - end if; - end process; - -piso: - process (bs_rst, bs_clk1, bs_shift, user_rego) - begin - bs_tdo <= user_rego(0); - if bs_rst = '1' then - user_rego <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_rego <= user_rego(0) & user_rego(user_rego'left downto 1); - else - user_rego <= (user_rego'left downto dmem_data_t'length => '0') & jtag_ld_dout; --- user_rego <= id; - end if; - end if; - end process; - --------------------------------------------------------------------------- --- ROM Read/Write --------------------------------------------------------------------------- -PROM_READ: - process(clk, ce) - begin - if rising_edge(clk) and ce = '1' then - dout <= xmem_rom(to_integer(addr)); - end if; - end process; - -PROM_WRITE: - process(jtag_ld_clk, jtag_ld_we) - begin - if rising_edge(jtag_ld_clk) then - if jtag_ld_we = '1' then - xmem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din; - else - jtag_ld_dout <= xmem_rom(to_integer(jtag_ld_addr)); - end if; - end if; - end process; - --------------------------------------------------------------------------- -end loadable; diff --git a/lib/CPUs/JCpu/src/reti_issue_irom.vhdl b/lib/CPUs/JCpu/src/reti_issue_irom.vhdl deleted file mode 100644 index 9355a7d..0000000 --- a/lib/CPUs/JCpu/src/reti_issue_irom.vhdl +++ /dev/null @@ -1,89 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: The ROM file for use in your VHDL design --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library work; -use work.cpu_pkg.all; - --- JASM_ROM_INSERT_HERE -ENTITY irom IS - Port ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - addr : in inst_addr_t; - dout : out inst_t - ); -END irom; - -ARCHITECTURE reti_issue OF irom IS - - type imem_rom_t is array (0 to 27) of inst_t; - - -- Assembled from reti_issue.jsm - constant imem_rom : imem_rom_t := - ( - "110000" & X"002", -- 0x000: JMP 0x002 - "111111" & X"000", -- 0x001: RETI - "000011" & X"050", -- 0x002: MOV R00, 0x05 - "100110" & X"030", -- 0x003: COUT (0x03), R00 - "000011" & X"000", -- 0x004: MOV R00, 0x00 - "000000" & X"000", -- 0x005: NOP - "010001" & X"010", -- 0x006: INC R00 - "000000" & X"000", -- 0x007: NOP - "111011" & X"01B", -- 0x008: CALL 0x01B - "000000" & X"000", -- 0x009: NOP - "111100" & X"003", -- 0x00A: PUSH R03 - "000000" & X"000", -- 0x00B: NOP - "111100" & X"002", -- 0x00C: PUSH R02 - "000000" & X"000", -- 0x00D: NOP - "111100" & X"001", -- 0x00E: PUSH R01 - "000000" & X"000", -- 0x00F: NOP - "111100" & X"000", -- 0x010: PUSH R00 - "000000" & X"000", -- 0x011: NOP - "111101" & X"000", -- 0x012: POP R00 - "000000" & X"000", -- 0x013: NOP - "111101" & X"001", -- 0x014: POP R01 - "000000" & X"000", -- 0x015: NOP - "111101" & X"002", -- 0x016: POP R02 - "000000" & X"000", -- 0x017: NOP - "111101" & X"003", -- 0x018: POP R03 - "000000" & X"000", -- 0x019: NOP - "110000" & X"005", -- 0x01A: JMP 0x005 - "111110" & X"000" -- 0x01B: RET - ); - -begin - -PROM_READ: - process(clk, ce) - begin - if rising_edge(clk) and ce = '1' then - dout <= imem_rom(to_integer(addr)); - end if; - end process; - -end reti_issue; - diff --git a/lib/CPUs/JCpu/src/reti_issue_irom_ld.vhdl b/lib/CPUs/JCpu/src/reti_issue_irom_ld.vhdl deleted file mode 100644 index d1b4bd1..0000000 --- a/lib/CPUs/JCpu/src/reti_issue_irom_ld.vhdl +++ /dev/null @@ -1,1181 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: loadable ROM --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library UNISIM; -use UNISIM.VComponents.all; - -library work; -use work.cpu_pkg.all; - -ENTITY irom IS - Port ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - addr : in inst_addr_t; - dout : out inst_t - ); - -END irom; - -ARCHITECTURE loadable OF irom IS - - -- JASM_ROM_INSERT_HERE - - -- Assembled from reti_issue.jsm - type imem_rom_t is array (0 to 1023) of inst_t; - signal imem_rom : imem_rom_t := - ( - "110000" & X"002", -- 0x000: JMP 0x002 - "111111" & X"000", -- 0x001: RETI - "000011" & X"050", -- 0x002: MOV R00, 0x05 - "100110" & X"030", -- 0x003: COUT (0x03), R00 - "000011" & X"000", -- 0x004: MOV R00, 0x00 - "000000" & X"000", -- 0x005: NOP - "010001" & X"010", -- 0x006: INC R00 - "000000" & X"000", -- 0x007: NOP - "111011" & X"01B", -- 0x008: CALL 0x01B - "000000" & X"000", -- 0x009: NOP - "111100" & X"003", -- 0x00A: PUSH R03 - "000000" & X"000", -- 0x00B: NOP - "111100" & X"002", -- 0x00C: PUSH R02 - "000000" & X"000", -- 0x00D: NOP - "111100" & X"001", -- 0x00E: PUSH R01 - "000000" & X"000", -- 0x00F: NOP - "111100" & X"000", -- 0x010: PUSH R00 - "000000" & X"000", -- 0x011: NOP - "111101" & X"000", -- 0x012: POP R00 - "000000" & X"000", -- 0x013: NOP - "111101" & X"001", -- 0x014: POP R01 - "000000" & X"000", -- 0x015: NOP - "111101" & X"002", -- 0x016: POP R02 - "000000" & X"000", -- 0x017: NOP - "111101" & X"003", -- 0x018: POP R03 - "000000" & X"000", -- 0x019: NOP - "110000" & X"005", -- 0x01A: JMP 0x005 - "111110" & X"000", -- 0x01B: RET - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000" - ); - - signal jtag_ld_clk : STD_LOGIC; - signal jtag_ld_we : STD_LOGIC; - signal jtag_ld_addr : inst_addr_t; - signal jtag_ld_dout : inst_t; - signal jtag_ld_din : inst_t; - signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic; - signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic; - signal user_regi, user_rego : unsigned (31 downto 0); - constant id : unsigned (31 downto 0) := X"BABE" & X"BEEF"; - -begin - --------------------------------------------------------------------------- --- Virtex-4: JTAG Loader --------------------------------------------------------------------------- - i00_BUFG : BUFG - port map - ( - O => bs_clk1, - I => bs_clk0 - ); - - i01_BUFG : BUFG - port map - ( - O => bs_update1, - I => bs_update0 - ); - - BSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 - generic map - ( - JTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4) - ) - port map - ( - CAPTURE => bs_capture, -- CAPTURE output from TAP controller - DRCK => bs_clk0, -- Data register output for USER functions - RESET => bs_rst, -- Reset output from TAP controller - SEL => bs_sel, -- USER active output - SHIFT => bs_shift, -- SHIFT output from TAP controller - TDI => bs_tdi, -- TDI output from TAP controller - UPDATE => bs_update0, -- UPDATE output from TAP controller - TDO => bs_tdo -- Data input for USER function - ); - - jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-inst_addr_t'length+1); - jtag_ld_din <= user_regi(inst_t'length-1 downto 0); - jtag_ld_clk <= bs_update1; - jtag_ld_we <= bs_sel; - -sipo: - process (bs_rst, bs_clk1, bs_tdi, bs_shift) - begin - if bs_rst = '1' then - user_regi <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_regi <= bs_tdi & user_regi(user_regi'left downto 1); - end if; - end if; - end process; - -piso: - process (bs_rst, bs_clk1, bs_shift, user_rego) - begin - bs_tdo <= user_rego(0); - if bs_rst = '1' then - user_rego <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_rego <= user_rego(0) & user_rego(user_rego'left downto 1); - else - user_rego <= (user_rego'left downto inst_t'length => '0') & jtag_ld_dout; --- user_rego <= id; - end if; - end if; - end process; - --------------------------------------------------------------------------- --- ROM Read/Write --------------------------------------------------------------------------- -PROM_READ: - process(clk, ce) - begin - if rising_edge(clk) and ce = '1' then - dout <= imem_rom(to_integer(addr)); - end if; - end process; - -PROM_WRITE: - process(jtag_ld_clk, jtag_ld_we) - begin - if rising_edge(jtag_ld_clk) then - if jtag_ld_we = '1' then - imem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din; - else - jtag_ld_dout <= imem_rom(to_integer(jtag_ld_addr)); - end if; - end if; - end process; - --------------------------------------------------------------------------- -end loadable; diff --git a/lib/CPUs/JCpu/src/reti_issue_xrom.vhdl b/lib/CPUs/JCpu/src/reti_issue_xrom.vhdl deleted file mode 100644 index a7a33f9..0000000 --- a/lib/CPUs/JCpu/src/reti_issue_xrom.vhdl +++ /dev/null @@ -1,317 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: The ROM file for use in your VHDL design --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library work; -use work.cpu_pkg.all; - --- JASM_ROM_INSERT_HERE -ENTITY xrom IS - Port ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - addr : in dmem_addr_t; - dout : out dmem_data_t - ); -END xrom; - -ARCHITECTURE reti_issue OF xrom IS - - type xmem_rom_t is array (0 to 255) of dmem_data_t; - - -- Assembled from reti_issue.jsm - constant xmem_rom : xmem_rom_t := - ( - X"00", -- 0x00 - X"00", -- 0x01 - X"00", -- 0x02 - X"00", -- 0x03 - X"00", -- 0x04 - X"00", -- 0x05 - X"00", -- 0x06 - X"00", -- 0x07 - X"00", -- 0x08 - X"00", -- 0x09 - X"00", -- 0x0A - X"00", -- 0x0B - X"00", -- 0x0C - X"00", -- 0x0D - X"00", -- 0x0E - X"00", -- 0x0F - X"00", -- 0x10 - X"00", -- 0x11 - X"00", -- 0x12 - X"00", -- 0x13 - X"00", -- 0x14 - X"00", -- 0x15 - X"00", -- 0x16 - X"00", -- 0x17 - X"00", -- 0x18 - X"00", -- 0x19 - X"00", -- 0x1A - X"00", -- 0x1B - X"00", -- 0x1C - X"00", -- 0x1D - X"00", -- 0x1E - X"00", -- 0x1F - X"00", -- 0x20 - X"00", -- 0x21 - X"00", -- 0x22 - X"00", -- 0x23 - X"00", -- 0x24 - X"00", -- 0x25 - X"00", -- 0x26 - X"00", -- 0x27 - X"00", -- 0x28 - X"00", -- 0x29 - X"00", -- 0x2A - X"00", -- 0x2B - X"00", -- 0x2C - X"00", -- 0x2D - X"00", -- 0x2E - X"00", -- 0x2F - X"00", -- 0x30 - X"00", -- 0x31 - X"00", -- 0x32 - X"00", -- 0x33 - X"00", -- 0x34 - X"00", -- 0x35 - X"00", -- 0x36 - X"00", -- 0x37 - X"00", -- 0x38 - X"00", -- 0x39 - X"00", -- 0x3A - X"00", -- 0x3B - X"00", -- 0x3C - X"00", -- 0x3D - X"00", -- 0x3E - X"00", -- 0x3F - X"00", -- 0x40 - X"00", -- 0x41 - X"00", -- 0x42 - X"00", -- 0x43 - X"00", -- 0x44 - X"00", -- 0x45 - X"00", -- 0x46 - X"00", -- 0x47 - X"00", -- 0x48 - X"00", -- 0x49 - X"00", -- 0x4A - X"00", -- 0x4B - X"00", -- 0x4C - X"00", -- 0x4D - X"00", -- 0x4E - X"00", -- 0x4F - X"00", -- 0x50 - X"00", -- 0x51 - X"00", -- 0x52 - X"00", -- 0x53 - X"00", -- 0x54 - X"00", -- 0x55 - X"00", -- 0x56 - X"00", -- 0x57 - X"00", -- 0x58 - X"00", -- 0x59 - X"00", -- 0x5A - X"00", -- 0x5B - X"00", -- 0x5C - X"00", -- 0x5D - X"00", -- 0x5E - X"00", -- 0x5F - X"00", -- 0x60 - X"00", -- 0x61 - X"00", -- 0x62 - X"00", -- 0x63 - X"00", -- 0x64 - X"00", -- 0x65 - X"00", -- 0x66 - X"00", -- 0x67 - X"00", -- 0x68 - X"00", -- 0x69 - X"00", -- 0x6A - X"00", -- 0x6B - X"00", -- 0x6C - X"00", -- 0x6D - X"00", -- 0x6E - X"00", -- 0x6F - X"00", -- 0x70 - X"00", -- 0x71 - X"00", -- 0x72 - X"00", -- 0x73 - X"00", -- 0x74 - X"00", -- 0x75 - X"00", -- 0x76 - X"00", -- 0x77 - X"00", -- 0x78 - X"00", -- 0x79 - X"00", -- 0x7A - X"00", -- 0x7B - X"00", -- 0x7C - X"00", -- 0x7D - X"00", -- 0x7E - X"00", -- 0x7F - X"00", -- 0x80 - X"00", -- 0x81 - X"00", -- 0x82 - X"00", -- 0x83 - X"00", -- 0x84 - X"00", -- 0x85 - X"00", -- 0x86 - X"00", -- 0x87 - X"00", -- 0x88 - X"00", -- 0x89 - X"00", -- 0x8A - X"00", -- 0x8B - X"00", -- 0x8C - X"00", -- 0x8D - X"00", -- 0x8E - X"00", -- 0x8F - X"00", -- 0x90 - X"00", -- 0x91 - X"00", -- 0x92 - X"00", -- 0x93 - X"00", -- 0x94 - X"00", -- 0x95 - X"00", -- 0x96 - X"00", -- 0x97 - X"00", -- 0x98 - X"00", -- 0x99 - X"00", -- 0x9A - X"00", -- 0x9B - X"00", -- 0x9C - X"00", -- 0x9D - X"00", -- 0x9E - X"00", -- 0x9F - X"00", -- 0xA0 - X"00", -- 0xA1 - X"00", -- 0xA2 - X"00", -- 0xA3 - X"00", -- 0xA4 - X"00", -- 0xA5 - X"00", -- 0xA6 - X"00", -- 0xA7 - X"00", -- 0xA8 - X"00", -- 0xA9 - X"00", -- 0xAA - X"00", -- 0xAB - X"00", -- 0xAC - X"00", -- 0xAD - X"00", -- 0xAE - X"00", -- 0xAF - X"00", -- 0xB0 - X"00", -- 0xB1 - X"00", -- 0xB2 - X"00", -- 0xB3 - X"00", -- 0xB4 - X"00", -- 0xB5 - X"00", -- 0xB6 - X"00", -- 0xB7 - X"00", -- 0xB8 - X"00", -- 0xB9 - X"00", -- 0xBA - X"00", -- 0xBB - X"00", -- 0xBC - X"00", -- 0xBD - X"00", -- 0xBE - X"00", -- 0xBF - X"00", -- 0xC0 - X"00", -- 0xC1 - X"00", -- 0xC2 - X"00", -- 0xC3 - X"00", -- 0xC4 - X"00", -- 0xC5 - X"00", -- 0xC6 - X"00", -- 0xC7 - X"00", -- 0xC8 - X"00", -- 0xC9 - X"00", -- 0xCA - X"00", -- 0xCB - X"00", -- 0xCC - X"00", -- 0xCD - X"00", -- 0xCE - X"00", -- 0xCF - X"00", -- 0xD0 - X"00", -- 0xD1 - X"00", -- 0xD2 - X"00", -- 0xD3 - X"00", -- 0xD4 - X"00", -- 0xD5 - X"00", -- 0xD6 - X"00", -- 0xD7 - X"00", -- 0xD8 - X"00", -- 0xD9 - X"00", -- 0xDA - X"00", -- 0xDB - X"00", -- 0xDC - X"00", -- 0xDD - X"00", -- 0xDE - X"00", -- 0xDF - X"00", -- 0xE0 - X"00", -- 0xE1 - X"00", -- 0xE2 - X"00", -- 0xE3 - X"00", -- 0xE4 - X"00", -- 0xE5 - X"00", -- 0xE6 - X"00", -- 0xE7 - X"00", -- 0xE8 - X"00", -- 0xE9 - X"00", -- 0xEA - X"00", -- 0xEB - X"00", -- 0xEC - X"00", -- 0xED - X"00", -- 0xEE - X"00", -- 0xEF - X"00", -- 0xF0 - X"00", -- 0xF1 - X"00", -- 0xF2 - X"00", -- 0xF3 - X"00", -- 0xF4 - X"00", -- 0xF5 - X"00", -- 0xF6 - X"00", -- 0xF7 - X"00", -- 0xF8 - X"00", -- 0xF9 - X"00", -- 0xFA - X"00", -- 0xFB - X"00", -- 0xFC - X"00", -- 0xFD - X"00", -- 0xFE - X"00" -- 0xFF - ); - -begin - -PROM_READ: - process(clk, ce) - begin - if rising_edge(clk) and ce = '1' then - dout <= xmem_rom(to_integer(addr)); - end if; - end process; - -end reti_issue; - diff --git a/lib/CPUs/JCpu/src/reti_issue_xrom_ld.vhdl b/lib/CPUs/JCpu/src/reti_issue_xrom_ld.vhdl deleted file mode 100644 index 244c1b5..0000000 --- a/lib/CPUs/JCpu/src/reti_issue_xrom_ld.vhdl +++ /dev/null @@ -1,413 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: loadable ROM --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library UNISIM; -use UNISIM.VComponents.all; - -library work; -use work.cpu_pkg.all; - -ENTITY xrom IS - Port ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - addr : in dmem_addr_t; - dout : out dmem_data_t - ); - -END xrom; - -ARCHITECTURE loadable OF xrom IS - - -- JASM_ROM_INSERT_HERE - - -- Assembled from reti_issue.jsm - type xmem_rom_t is array (0 to 255) of dmem_data_t; - signal xmem_rom : xmem_rom_t := - ( - X"00", -- 0x00 - X"00", -- 0x01 - X"00", -- 0x02 - X"00", -- 0x03 - X"00", -- 0x04 - X"00", -- 0x05 - X"00", -- 0x06 - X"00", -- 0x07 - X"00", -- 0x08 - X"00", -- 0x09 - X"00", -- 0x0A - X"00", -- 0x0B - X"00", -- 0x0C - X"00", -- 0x0D - X"00", -- 0x0E - X"00", -- 0x0F - X"00", -- 0x10 - X"00", -- 0x11 - X"00", -- 0x12 - X"00", -- 0x13 - X"00", -- 0x14 - X"00", -- 0x15 - X"00", -- 0x16 - X"00", -- 0x17 - X"00", -- 0x18 - X"00", -- 0x19 - X"00", -- 0x1A - X"00", -- 0x1B - X"00", -- 0x1C - X"00", -- 0x1D - X"00", -- 0x1E - X"00", -- 0x1F - X"00", -- 0x20 - X"00", -- 0x21 - X"00", -- 0x22 - X"00", -- 0x23 - X"00", -- 0x24 - X"00", -- 0x25 - X"00", -- 0x26 - X"00", -- 0x27 - X"00", -- 0x28 - X"00", -- 0x29 - X"00", -- 0x2A - X"00", -- 0x2B - X"00", -- 0x2C - X"00", -- 0x2D - X"00", -- 0x2E - X"00", -- 0x2F - X"00", -- 0x30 - X"00", -- 0x31 - X"00", -- 0x32 - X"00", -- 0x33 - X"00", -- 0x34 - X"00", -- 0x35 - X"00", -- 0x36 - X"00", -- 0x37 - X"00", -- 0x38 - X"00", -- 0x39 - X"00", -- 0x3A - X"00", -- 0x3B - X"00", -- 0x3C - X"00", -- 0x3D - X"00", -- 0x3E - X"00", -- 0x3F - X"00", -- 0x40 - X"00", -- 0x41 - X"00", -- 0x42 - X"00", -- 0x43 - X"00", -- 0x44 - X"00", -- 0x45 - X"00", -- 0x46 - X"00", -- 0x47 - X"00", -- 0x48 - X"00", -- 0x49 - X"00", -- 0x4A - X"00", -- 0x4B - X"00", -- 0x4C - X"00", -- 0x4D - X"00", -- 0x4E - X"00", -- 0x4F - X"00", -- 0x50 - X"00", -- 0x51 - X"00", -- 0x52 - X"00", -- 0x53 - X"00", -- 0x54 - X"00", -- 0x55 - X"00", -- 0x56 - X"00", -- 0x57 - X"00", -- 0x58 - X"00", -- 0x59 - X"00", -- 0x5A - X"00", -- 0x5B - X"00", -- 0x5C - X"00", -- 0x5D - X"00", -- 0x5E - X"00", -- 0x5F - X"00", -- 0x60 - X"00", -- 0x61 - X"00", -- 0x62 - X"00", -- 0x63 - X"00", -- 0x64 - X"00", -- 0x65 - X"00", -- 0x66 - X"00", -- 0x67 - X"00", -- 0x68 - X"00", -- 0x69 - X"00", -- 0x6A - X"00", -- 0x6B - X"00", -- 0x6C - X"00", -- 0x6D - X"00", -- 0x6E - X"00", -- 0x6F - X"00", -- 0x70 - X"00", -- 0x71 - X"00", -- 0x72 - X"00", -- 0x73 - X"00", -- 0x74 - X"00", -- 0x75 - X"00", -- 0x76 - X"00", -- 0x77 - X"00", -- 0x78 - X"00", -- 0x79 - X"00", -- 0x7A - X"00", -- 0x7B - X"00", -- 0x7C - X"00", -- 0x7D - X"00", -- 0x7E - X"00", -- 0x7F - X"00", -- 0x80 - X"00", -- 0x81 - X"00", -- 0x82 - X"00", -- 0x83 - X"00", -- 0x84 - X"00", -- 0x85 - X"00", -- 0x86 - X"00", -- 0x87 - X"00", -- 0x88 - X"00", -- 0x89 - X"00", -- 0x8A - X"00", -- 0x8B - X"00", -- 0x8C - X"00", -- 0x8D - X"00", -- 0x8E - X"00", -- 0x8F - X"00", -- 0x90 - X"00", -- 0x91 - X"00", -- 0x92 - X"00", -- 0x93 - X"00", -- 0x94 - X"00", -- 0x95 - X"00", -- 0x96 - X"00", -- 0x97 - X"00", -- 0x98 - X"00", -- 0x99 - X"00", -- 0x9A - X"00", -- 0x9B - X"00", -- 0x9C - X"00", -- 0x9D - X"00", -- 0x9E - X"00", -- 0x9F - X"00", -- 0xA0 - X"00", -- 0xA1 - X"00", -- 0xA2 - X"00", -- 0xA3 - X"00", -- 0xA4 - X"00", -- 0xA5 - X"00", -- 0xA6 - X"00", -- 0xA7 - X"00", -- 0xA8 - X"00", -- 0xA9 - X"00", -- 0xAA - X"00", -- 0xAB - X"00", -- 0xAC - X"00", -- 0xAD - X"00", -- 0xAE - X"00", -- 0xAF - X"00", -- 0xB0 - X"00", -- 0xB1 - X"00", -- 0xB2 - X"00", -- 0xB3 - X"00", -- 0xB4 - X"00", -- 0xB5 - X"00", -- 0xB6 - X"00", -- 0xB7 - X"00", -- 0xB8 - X"00", -- 0xB9 - X"00", -- 0xBA - X"00", -- 0xBB - X"00", -- 0xBC - X"00", -- 0xBD - X"00", -- 0xBE - X"00", -- 0xBF - X"00", -- 0xC0 - X"00", -- 0xC1 - X"00", -- 0xC2 - X"00", -- 0xC3 - X"00", -- 0xC4 - X"00", -- 0xC5 - X"00", -- 0xC6 - X"00", -- 0xC7 - X"00", -- 0xC8 - X"00", -- 0xC9 - X"00", -- 0xCA - X"00", -- 0xCB - X"00", -- 0xCC - X"00", -- 0xCD - X"00", -- 0xCE - X"00", -- 0xCF - X"00", -- 0xD0 - X"00", -- 0xD1 - X"00", -- 0xD2 - X"00", -- 0xD3 - X"00", -- 0xD4 - X"00", -- 0xD5 - X"00", -- 0xD6 - X"00", -- 0xD7 - X"00", -- 0xD8 - X"00", -- 0xD9 - X"00", -- 0xDA - X"00", -- 0xDB - X"00", -- 0xDC - X"00", -- 0xDD - X"00", -- 0xDE - X"00", -- 0xDF - X"00", -- 0xE0 - X"00", -- 0xE1 - X"00", -- 0xE2 - X"00", -- 0xE3 - X"00", -- 0xE4 - X"00", -- 0xE5 - X"00", -- 0xE6 - X"00", -- 0xE7 - X"00", -- 0xE8 - X"00", -- 0xE9 - X"00", -- 0xEA - X"00", -- 0xEB - X"00", -- 0xEC - X"00", -- 0xED - X"00", -- 0xEE - X"00", -- 0xEF - X"00", -- 0xF0 - X"00", -- 0xF1 - X"00", -- 0xF2 - X"00", -- 0xF3 - X"00", -- 0xF4 - X"00", -- 0xF5 - X"00", -- 0xF6 - X"00", -- 0xF7 - X"00", -- 0xF8 - X"00", -- 0xF9 - X"00", -- 0xFA - X"00", -- 0xFB - X"00", -- 0xFC - X"00", -- 0xFD - X"00", -- 0xFE - X"00" -- 0xFF - ); - - signal jtag_ld_clk : STD_LOGIC; - signal jtag_ld_we : STD_LOGIC; - signal jtag_ld_addr : dmem_addr_t; - signal jtag_ld_dout : dmem_data_t; - signal jtag_ld_din : dmem_data_t; - signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic; - signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic; - signal user_regi, user_rego : unsigned (15 downto 0); - constant id : unsigned (15 downto 0) := X"BEEF"; - -begin - --------------------------------------------------------------------------- --- Virtex-4: JTAG Loader --------------------------------------------------------------------------- - i00_BUFG : BUFG - port map - ( - O => bs_clk1, - I => bs_clk0 - ); - - i01_BUFG : BUFG - port map - ( - O => bs_update1, - I => bs_update0 - ); - - BSCAN_VIRTEX4_inst2 : BSCAN_VIRTEX4 - generic map - ( - JTAG_CHAIN => 2 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4) - ) - port map - ( - CAPTURE => bs_capture, -- CAPTURE output from TAP controller - DRCK => bs_clk0, -- Data register output for USER functions - RESET => bs_rst, -- Reset output from TAP controller - SEL => bs_sel, -- USER active output - SHIFT => bs_shift, -- SHIFT output from TAP controller - TDI => bs_tdi, -- TDI output from TAP controller - UPDATE => bs_update0, -- UPDATE output from TAP controller - TDO => bs_tdo -- Data input for USER function - ); - - jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-dmem_data_t'length+1); - jtag_ld_din <= user_regi(dmem_data_t'left downto 0); - jtag_ld_clk <= bs_update1; - jtag_ld_we <= bs_sel; - -sipo: - process (bs_rst, bs_clk1, bs_tdi, bs_shift) - begin - if bs_rst = '1' then - user_regi <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_regi <= bs_tdi & user_regi(user_regi'left downto 1); - end if; - end if; - end process; - -piso: - process (bs_rst, bs_clk1, bs_shift, user_rego) - begin - bs_tdo <= user_rego(0); - if bs_rst = '1' then - user_rego <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_rego <= user_rego(0) & user_rego(user_rego'left downto 1); - else - user_rego <= (user_rego'left downto dmem_data_t'length => '0') & jtag_ld_dout; --- user_rego <= id; - end if; - end if; - end process; - --------------------------------------------------------------------------- --- ROM Read/Write --------------------------------------------------------------------------- -PROM_READ: - process(clk, ce) - begin - if rising_edge(clk) and ce = '1' then - dout <= xmem_rom(to_integer(addr)); - end if; - end process; - -PROM_WRITE: - process(jtag_ld_clk, jtag_ld_we) - begin - if rising_edge(jtag_ld_clk) then - if jtag_ld_we = '1' then - xmem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din; - else - jtag_ld_dout <= xmem_rom(to_integer(jtag_ld_addr)); - end if; - end if; - end process; - --------------------------------------------------------------------------- -end loadable; diff --git a/lib/CPUs/JCpu/src/tb_cpu_embedded.vhd b/lib/CPUs/JCpu/src/tb_cpu_embedded.vhd deleted file mode 100644 index dafb553..0000000 --- a/lib/CPUs/JCpu/src/tb_cpu_embedded.vhd +++ /dev/null @@ -1,126 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: testbench for embedded cpu with rom --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; -use std.textio.all; -- Imports the standard textio package. - -library work; -use work.cpu_pkg.all; - -ENTITY tb_cpu_embedded IS -END tb_cpu_embedded; - -ARCHITECTURE behavior OF tb_cpu_embedded IS - - COMPONENT cpu_embedded - Port ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - ce : in STD_LOGIC; - int_in : in STD_LOGIC; - int_ack : out STD_LOGIC; - xmem_we : out STD_LOGIC; - xmem_re : out STD_LOGIC; - xmem_din : in unsigned (DMEM_DATA_WIDTH-1 downto 0); - xmem_dout : out unsigned (DMEM_DATA_WIDTH-1 downto 0); - xmem_addr : out unsigned (DMEM_ADDR_WIDTH-1 downto 0); - io_sel : out STD_LOGIC - ); - END COMPONENT; - - constant CLK_PERIOD : time := 10 ns; - type sram_t is array (integer range <>) of dmem_data_t; - signal rst : std_logic := '1'; - signal clk : std_logic := '1'; - signal ce : std_logic := '0'; - signal int_in : std_logic := '0'; - signal int_ack : std_logic; - signal xmem_din : dmem_data_t := (others => '-'); - signal xmem_dout : dmem_data_t; - signal xmem_addr : dmem_addr_t; - signal xmem_we : std_logic; - signal xmem_re : std_logic; - signal io_sel : std_logic; - signal sram : sram_t(0 to 2**dmem_addr_t'length-1); - - -BEGIN - -uut: cpu_embedded - PORT MAP( - rst => rst, - clk => clk, - ce => ce, - int_in => int_in, - int_ack => int_ack, - xmem_we => xmem_we, - xmem_re => xmem_re, - xmem_din => xmem_din, - xmem_dout => xmem_dout, - xmem_addr => xmem_addr, - io_sel => io_sel - ); - -CLK_GEN: process - begin - wait for CLK_PERIOD/2; - clk <= not clk; - end process; - -STIMULUS: process - - begin - - wait for 3*CLK_PERIOD; - rst <= '0'; - wait for 2*CLK_PERIOD; - - wait until rising_edge(clk); - ce <= '1'; - - wait for 1000*CLK_PERIOD; - - assert false report "Test finished" severity error; - wait; - - end process; - -SRAM_RW: process(rst, clk, xmem_addr, xmem_dout, xmem_we) - begin - if (rst = '1') then - xmem_din <= X"00"; - elsif rising_edge(clk) then - if io_sel = '0' then - if xmem_we = '1' then - sram(to_integer(xmem_addr)) <= xmem_dout; - end if; - xmem_din <= to_01(sram(to_integer(xmem_addr))); - else - xmem_din <= X"FF"; - end if; - end if; - end process; - -END; diff --git a/lib/CPUs/JCpu/src/tb_cpu_irq.vhd b/lib/CPUs/JCpu/src/tb_cpu_irq.vhd deleted file mode 100644 index 8a19414..0000000 --- a/lib/CPUs/JCpu/src/tb_cpu_irq.vhd +++ /dev/null @@ -1,205 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: Formal test of correct function of JCPU, --- also writes 'opc.lst' for JASM-assembler --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; -use std.textio.all; -- Imports the standard textio package. - -library work; -use work.cpu_pkg.all; -use work.PCK_FIO.all; - -ENTITY tb_cpu IS -END tb_cpu; - -ARCHITECTURE behavior OF tb_cpu IS - - COMPONENT cpu - Generic ( - use_instr_register : boolean; - use_ctrl_rom : boolean - ); - Port ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - ce : in STD_LOGIC; - int_in : in STD_LOGIC; - int_ack : out STD_LOGIC; - xmem_we : out STD_LOGIC; - xmem_re : out STD_LOGIC; - instr_din : in unsigned (IMEM_DATA_WIDTH-1 downto 0); - instr_addr : out unsigned (IMEM_ADDR_WIDTH-1 downto 0); - xmem_din : in unsigned (DMEM_DATA_WIDTH-1 downto 0); - xmem_dout : out unsigned (DMEM_DATA_WIDTH-1 downto 0); - xmem_addr : out unsigned (DMEM_DATA_WIDTH-1 downto 0); - io_sel : out STD_LOGIC - - ); - END COMPONENT; - - COMPONENT irom - Port ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - addr : in inst_addr_t; - dout : out inst_t - ); - END COMPONENT; - - constant CLK_PERIOD : time := 10 ns; - type prom_t is array (integer range <>) of inst_t; - type sram_t is array (integer range <>) of dmem_data_t; - signal rst : std_logic := '1'; - signal clk : std_logic := '1'; - signal ce : std_logic := '0'; - signal int_in : std_logic := '0'; - signal int_ack : std_logic; - signal irom_data : unsigned (IMEM_DATA_WIDTH-1 downto 0) := (others => '-'); - signal irom_addr : unsigned (IMEM_ADDR_WIDTH-1 downto 0); - signal xmem_din : dmem_data_t := (others => '-'); - signal xmem_dout : dmem_data_t; - signal xmem_addr : unsigned (DMEM_DATA_WIDTH-1 downto 0); - signal xmem_we : std_logic; - signal xmem_re : std_logic; - signal io_sel : std_logic; - signal sram : sram_t(0 to 2**DMEM_DATA_WIDTH-1); - - type reg_t is record - revision : dmem_data_t; - testid : dmem_data_t; - interrupt : std_logic; - end record; - - signal reg : reg_t; - - -BEGIN - -uut: cpu - GENERIC MAP - ( - use_instr_register => false, - use_ctrl_rom => true - ) - PORT MAP( - rst => rst, - clk => clk, - ce => ce, - int_in => int_in, - int_ack => int_ack, - xmem_we => xmem_we, - xmem_re => xmem_re, - instr_din => irom_data, - instr_addr => irom_addr, - xmem_din => xmem_din, - xmem_dout => xmem_dout, - xmem_addr => xmem_addr, - io_sel => io_sel - ); - -the_irom: irom - PORT MAP( - clk => clk, - ce => ce, - addr => irom_addr, - dout => irom_data - ); - -CLK_GEN: process - begin - wait for CLK_PERIOD/2; - clk <= not clk; - end process; - -STIMULUS: process - file RESULT: text open write_mode is "../tools/opc.list"; - variable L: line; - - begin - - for i in 0 to instr_name_array'length-1 loop - fprint(RESULT, L,"%d %s\n", fo(i), instr_name_array(i)); - end loop; - - wait for 3*CLK_PERIOD; - rst <= '0'; - wait for 2*CLK_PERIOD; - - wait until rising_edge(clk); - ce <= '1'; - - wait for 1000*CLK_PERIOD; - - for i in 1 to 100 loop - wait until rising_edge(clk); - int_in <= '1'; - wait until rising_edge(clk) and int_ack = '1'; - int_in <= '0'; - wait for 300*CLK_PERIOD; - end loop; - - assert false report "Test finished" severity error; - wait; - - end process; - -SRAM_RW: process(rst, clk) - begin - if (rst = '1') then - reg.revision <= (others => '0'); - reg.testid <= (others => '0'); - elsif rising_edge(clk) then - if xmem_we = '1' then - if io_sel = '0' then - sram(to_integer(xmem_addr)) <= xmem_dout; - else - case xmem_addr is - when X"00" => - reg.revision <= xmem_dout; - when X"01" => - reg.testid <= xmem_dout; - when X"02" => - reg.interrupt <= xmem_dout(0); - when others => null; - end case; - end if; - else - if io_sel = '0' then - xmem_din <= to_01(sram(to_integer(xmem_addr))); - else - case xmem_addr is - when X"00" => - xmem_din <= reg.revision; - when X"01" => - xmem_din <= reg.testid; - when others => - xmem_din <= X"BC"; - end case; - end if; - end if; - end if; - end process; - -END; diff --git a/lib/CPUs/JCpu/src/tb_cpu_itest.vhd b/lib/CPUs/JCpu/src/tb_cpu_itest.vhd deleted file mode 100644 index 243ba8f..0000000 --- a/lib/CPUs/JCpu/src/tb_cpu_itest.vhd +++ /dev/null @@ -1,200 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: Formal test of correct function of JCPU, --- also writes 'opc.lst' for JASM-assembler --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; -use std.textio.all; -- Imports the standard textio package. - -library work; -use work.cpu_pkg.all; -use work.PCK_FIO.all; - -ENTITY tb_cpu IS -END tb_cpu; - -ARCHITECTURE behavior OF tb_cpu IS - - COMPONENT cpu - Generic ( - use_instr_register : boolean; - use_ctrl_rom : boolean - ); - Port ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - ce : in STD_LOGIC; - int_in : in STD_LOGIC; - int_ack : out STD_LOGIC; - xmem_we : out STD_LOGIC; - xmem_re : out STD_LOGIC; - instr_din : in unsigned (IMEM_DATA_WIDTH-1 downto 0); - instr_addr : out unsigned (IMEM_ADDR_WIDTH-1 downto 0); - xmem_din : in unsigned (DMEM_DATA_WIDTH-1 downto 0); - xmem_dout : out unsigned (DMEM_DATA_WIDTH-1 downto 0); - xmem_addr : out unsigned (DMEM_DATA_WIDTH-1 downto 0); - io_sel : out STD_LOGIC - - ); - END COMPONENT; - - COMPONENT irom - Port ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - addr : in inst_addr_t; - dout : out inst_t - ); - END COMPONENT; - - constant CLK_PERIOD : time := 10 ns; - type prom_t is array (integer range <>) of inst_t; - type sram_t is array (integer range <>) of dmem_data_t; - signal rst : std_logic := '1'; - signal clk : std_logic := '1'; - signal ce : std_logic := '0'; - signal int_in : std_logic := '0'; - signal int_ack : std_logic; - signal irom_data : unsigned (IMEM_DATA_WIDTH-1 downto 0) := (others => '-'); - signal irom_addr : unsigned (IMEM_ADDR_WIDTH-1 downto 0); - signal xmem_din : dmem_data_t := (others => '-'); - signal xmem_dout : dmem_data_t; - signal xmem_addr : unsigned (DMEM_DATA_WIDTH-1 downto 0); - signal xmem_we : std_logic; - signal xmem_re : std_logic; - signal io_sel : std_logic; - signal sram : sram_t(0 to 2**DMEM_DATA_WIDTH-1); - - type reg_t is record - revision : dmem_data_t; - testid : dmem_data_t; - interrupt : std_logic; - end record; - - signal reg : reg_t; - - -BEGIN - - int_in <= reg.interrupt; -uut: cpu - GENERIC MAP - ( - use_instr_register => false, - use_ctrl_rom => true - ) - PORT MAP( - rst => rst, - clk => clk, - ce => ce, - int_in => int_in, - int_ack => int_ack, - xmem_we => xmem_we, - xmem_re => xmem_re, - instr_din => irom_data, - instr_addr => irom_addr, - xmem_din => xmem_din, - xmem_dout => xmem_dout, - xmem_addr => xmem_addr, - io_sel => io_sel - ); - -the_irom: irom - PORT MAP( - clk => clk, - ce => ce, - addr => irom_addr, - dout => irom_data - ); - -CLK_GEN: process - begin - wait for CLK_PERIOD/2; - clk <= not clk; - end process; - -STIMULUS: process - file RESULT: text open write_mode is "../tools/opc.list"; - variable L: line; - - begin - - for i in 0 to instr_name_array'length-1 loop - fprint(RESULT, L,"%d %s\n", fo(i), instr_name_array(i)); - end loop; - - wait for 3*CLK_PERIOD; - rst <= '0'; - wait for 2*CLK_PERIOD; - - wait until rising_edge(clk); - ce <= '1'; - - assert false report "Test finished" severity error; - wait; - - end process; - -SRAM_RW: process(rst, clk) - begin - if (rst = '1') then - reg.revision <= (others => '0'); - reg.testid <= (others => '0'); - reg.interrupt <= '0'; - elsif rising_edge(clk) then - if int_ack = '1' then --- reg.interrupt <= '0'; - end if; - if xmem_we = '1' then - if io_sel = '0' then - sram(to_integer(xmem_addr)) <= xmem_dout; - else - case xmem_addr is - when X"00" => - reg.revision <= xmem_dout; - when X"01" => - reg.testid <= xmem_dout; - when X"02" => - reg.interrupt <= xmem_dout(0); - when others => null; - end case; - end if; - else - if io_sel = '0' then - xmem_din <= to_01(sram(to_integer(xmem_addr))); - else - case xmem_addr is - when X"00" => - xmem_din <= reg.revision; - when X"01" => - xmem_din <= reg.testid; - when others => - xmem_din <= X"BC"; - end case; - end if; - end if; - end if; - end process; - -END; diff --git a/lib/CPUs/JCpu/syn/ise91/cpu_vhdl.prj b/lib/CPUs/JCpu/syn/ise91/cpu_vhdl.prj deleted file mode 100644 index 18718bf..0000000 --- a/lib/CPUs/JCpu/syn/ise91/cpu_vhdl.prj +++ /dev/null @@ -1,10 +0,0 @@ -vhdl work "W:\vhdl\lib\CPUs\JCpu\src\core\cpu_pkg.vhd" -vhdl work "W:\vhdl\lib\CPUs\JCpu\src\core\stack_ctrl.vhd" -vhdl work "W:\vhdl\lib\CPUs\JCpu\src\core\reg_dual.vhd" -vhdl work "W:\vhdl\lib\CPUs\JCpu\src\core\pc.vhd" -vhdl work "W:\vhdl\lib\CPUs\JCpu\src\core\int_ctrl.vhd" -vhdl work "W:\vhdl\lib\CPUs\JCpu\src\core\dpath_ctrl.vhd" -vhdl work "W:\vhdl\lib\CPUs\JCpu\src\core\chipreg.vhd" -vhdl work "W:\vhdl\lib\CPUs\JCpu\src\core\chipram.vhd" -vhdl work "W:\vhdl\lib\CPUs\JCpu\src\core\alu.vhd" -vhdl work "W:\vhdl\lib\CPUs\JCpu\src\core\cpu.vhd" diff --git a/lib/CPUs/JCpu/tools/eval_scan.rb b/lib/CPUs/JCpu/tools/eval_scan.rb deleted file mode 100644 index 0c38397..0000000 --- a/lib/CPUs/JCpu/tools/eval_scan.rb +++ /dev/null @@ -1,42 +0,0 @@ -#!/usr/bin/env ruby - -str1 = %Q!lbl: dc "Hallo", ", ", 0, 1, " der","Jens"! - -i=0; - -def get_stri_lit (str) - res = [""]; - state = "out" - - j = 0; - k = 0; - for i in (0..str.length-1) - c = str[i]; - nstate = state - case state - when "out" - if c == "\""[0] - nstate = "in" - end - when "in" - if c == "\""[0] - nstate = "out" - if j > 0 - k = k + 1; - res[k] = "" - end - else - res[k] = res[k] + format("%c", c); - j = j + 1; - end - end - state = nstate - end; - return res -end - -get_stri_lit(str1).each do |word| - puts word -end - - \ No newline at end of file diff --git a/lib/CPUs/JCpu/tools/insrom.rb b/lib/CPUs/JCpu/tools/insrom.rb deleted file mode 100644 index 6713f9f..0000000 --- a/lib/CPUs/JCpu/tools/insrom.rb +++ /dev/null @@ -1,46 +0,0 @@ -#!/usr/bin/env ruby - -# ---------------------------------------------------------------------- -# Project: JCPU, a portable 8-bit RISC CPU written in VHDL -# This file: Insertion of code fragments into templates -# -# Copyright (C) 2007 J. Ahrensfeld -# -# This program is free software: you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation, either version 3 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see . -# -# For questions and ideas, please contact the author at jens@jayfield.org -# -# --------------------------------------------------------------------- - -arg = $* -rom_filename = arg[0].to_s -tpl_filename = arg[1].to_s - -subst_pattern = "JASM_ROM_INSERT_HERE" - -# -------------------------------------------------------- -# Open file -# -------------------------------------------------------- -romfile = File.open(rom_filename, "r") -tplfile = File.open(tpl_filename, "r") -re = Regexp.new(subst_pattern) - -while (line = tplfile.gets) - puts line - line.scan(re).each do |word| - romfile.each do |raw_line| - puts raw_line - end - end -end diff --git a/lib/CPUs/JCpu/tools/irom.vhd.tpl b/lib/CPUs/JCpu/tools/irom.vhd.tpl deleted file mode 100644 index 5f11f86..0000000 --- a/lib/CPUs/JCpu/tools/irom.vhd.tpl +++ /dev/null @@ -1,32 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: The ROM file for use in your VHDL design --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library work; -use work.cpu_pkg.all; - --- JASM_ROM_INSERT_HERE - diff --git a/lib/CPUs/JCpu/tools/irom_ld.vhd.tpl b/lib/CPUs/JCpu/tools/irom_ld.vhd.tpl deleted file mode 100644 index eaa41f3..0000000 --- a/lib/CPUs/JCpu/tools/irom_ld.vhd.tpl +++ /dev/null @@ -1,151 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: loadable ROM --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library UNISIM; -use UNISIM.VComponents.all; - -library work; -use work.cpu_pkg.all; - -ENTITY irom IS - Port ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - addr : in inst_addr_t; - dout : out inst_t - ); - -END irom; - -ARCHITECTURE loadable OF irom IS - - -- JASM_ROM_INSERT_HERE - - signal jtag_ld_clk : STD_LOGIC; - signal jtag_ld_we : STD_LOGIC; - signal jtag_ld_addr : inst_addr_t; - signal jtag_ld_dout : inst_t; - signal jtag_ld_din : inst_t; - signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic; - signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic; - signal user_regi, user_rego : unsigned (31 downto 0); - constant id : unsigned (31 downto 0) := X"BABE" & X"BEEF"; - -begin - --------------------------------------------------------------------------- --- Virtex-4: JTAG Loader --------------------------------------------------------------------------- - i00_BUFG : BUFG - port map - ( - O => bs_clk1, - I => bs_clk0 - ); - - i01_BUFG : BUFG - port map - ( - O => bs_update1, - I => bs_update0 - ); - - BSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 - generic map - ( - JTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4) - ) - port map - ( - CAPTURE => bs_capture, -- CAPTURE output from TAP controller - DRCK => bs_clk0, -- Data register output for USER functions - RESET => bs_rst, -- Reset output from TAP controller - SEL => bs_sel, -- USER active output - SHIFT => bs_shift, -- SHIFT output from TAP controller - TDI => bs_tdi, -- TDI output from TAP controller - UPDATE => bs_update0, -- UPDATE output from TAP controller - TDO => bs_tdo -- Data input for USER function - ); - - jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-inst_addr_t'length+1); - jtag_ld_din <= user_regi(inst_t'length-1 downto 0); - jtag_ld_clk <= bs_update1; - jtag_ld_we <= bs_sel; - -sipo: - process (bs_rst, bs_clk1, bs_tdi, bs_shift) - begin - if bs_rst = '1' then - user_regi <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_regi <= bs_tdi & user_regi(user_regi'left downto 1); - end if; - end if; - end process; - -piso: - process (bs_rst, bs_clk1, bs_shift, user_rego) - begin - bs_tdo <= user_rego(0); - if bs_rst = '1' then - user_rego <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_rego <= user_rego(0) & user_rego(user_rego'left downto 1); - else - user_rego <= (user_rego'left downto inst_t'length => '0') & jtag_ld_dout; --- user_rego <= id; - end if; - end if; - end process; - --------------------------------------------------------------------------- --- ROM Read/Write --------------------------------------------------------------------------- -PROM_READ: - process(clk, ce) - begin - if rising_edge(clk) and ce = '1' then - dout <= imem_rom(to_integer(addr)); - end if; - end process; - -PROM_WRITE: - process(jtag_ld_clk, jtag_ld_we) - begin - if rising_edge(jtag_ld_clk) then - if jtag_ld_we = '1' then - imem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din; - else - jtag_ld_dout <= imem_rom(to_integer(jtag_ld_addr)); - end if; - end if; - end process; - --------------------------------------------------------------------------- -end loadable; diff --git a/lib/CPUs/JCpu/tools/jasm.bak.rb b/lib/CPUs/JCpu/tools/jasm.bak.rb deleted file mode 100644 index 4c9feb0..0000000 --- a/lib/CPUs/JCpu/tools/jasm.bak.rb +++ /dev/null @@ -1,494 +0,0 @@ -#!/usr/bin/env ruby - -# ---------------------------------------------------------------------- -# Project: JCPU, a portable 8-bit RISC CPU written in VHDL -# This file: A small assembler for the JCPU - -# Copyright (C) 2007 J. Ahrensfeld - -# This library is free software; you can redistribute it and/or -# modify it under the terms of the GNU Lesser General Public -# License as published by the Free Software Foundation; either -# version 2.1 of the License, or (at your option) any later version. - -# This library is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -# Lesser General Public License for more details. - -# You should have received a copy of the GNU Lesser General Public -# License along with this library; if not, write to the Free Software -# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - -# For questions and ideas, please contact the author at jens@jayfield.org - -# --------------------------------------------------------------------- - -arg = $* -MAX_SIZE_ROM = 1024 -PROJECT_NAME = arg.to_s.gsub(/\..*/, "") -ENTITY_NAME = "rom" -ENTITY_DATA_TYPE = "inst_t" -ENTITY_ADDR_TYPE = "inst_addr_t" -OPC_LIST_NAME = "/cygdrive/w/vhdl/lib/CPUs/JCpu/tools/opc.list" - -# -------------------------------------------------------- -# Open file -# -------------------------------------------------------- -filename = arg.to_s -if !File.exists?(filename) - STDERR.puts "#{filename} does not exist" - exit 1 -end - -# -------------------------------------------------------- -# Pass 1 -# -------------------------------------------------------- -lc = 0 # Line counter -pc = 0 # Program counter -chip_dc = [0,0,0,0] # chip data counter -xmem_dc = 0 # xmem data counter -curr_segment = "UNDEF"; -page = 0 - -label_list=[[],[]] -instr_list=[nil] -file = File.open(filename, "r") -file.each do |raw_line| - lc += 1 - - # Make all upper case - iline = "#{raw_line}".strip.upcase - - # Remove comments - iline = iline.gsub(/;.*/, "") - - # Split instruction at spaces - iline_member = iline.split(" ") - - if iline_member[0] == nil - next - end - - mc = 0; - label = nil - clean_line = nil - if (iline_member[0] =~ /\w+:/) - mc += 1 - label = iline_member[0].delete(":") - if label_list.rindex(label) != nil - STDERR.puts format("Error in line %d: Duplicate label \"%s\" found", lc, label) - exit 1 - end - end - - case iline_member[mc] - when nil - value = format("0x%3.3X",pc) - when "EQU" - if 0 == (iline_member[mc+1] =~ /\d+/) - value = format("0x%2.2X",eval(iline_member[mc+1..iline_member.nitems].to_s)) - else - value = iline_member[mc+1] - end - when "ORG", "CODE" - pc = eval(iline_member[mc+1..iline_member.nitems].to_s) - value = format("0x%3.3X",pc) - when "CDATA", "CMEM" - if iline_member[mc+1] == nil - STDERR.puts format("Error in line %d: CDATA needs argument!", lc) - exit 1 - end - curr_segment = "CMEM"; - page = iline_member[mc+1].to_i(16) - when "XDATA", "XMEM" - curr_segment = "XMEM"; - when "DC" - len = 0; - iline.split("DC")[1].delete("0x").scan(/[0-9A-Fa-f]+/).each do |byte| - len += 1 - end - if curr_segment == "CMEM" - STDERR.puts format("Error in line %d: CDATA cannot be initialized!", lc) - exit 1 - else - value = format("0x%2.2X",xmem_dc) - puts format("Found DC defining %d bytes at 0x%4.4X in %s", len, xmem_dc, curr_segment); - xmem_dc += len - end - when "DB" - len = iline_member[mc+1].to_i - if curr_segment == "CMEM" - value = format("0x%2.2X",chip_dc[page]) - puts format("Found DB reserving %d bytes at 0x%4.4X in %s(%d)", len, chip_dc[page], curr_segment, page); - chip_dc[page] += len - else - value = format("0x%2.2X",xmem_dc) - puts format("Found DB reserving %d bytes at 0x%4.4X in %s", len, xmem_dc, curr_segment); - xmem_dc += len - end - else - op_line = iline_member[mc+1..iline_member.nitems].to_s - value = format("0x%3.3X",pc) - opc = iline_member[mc] - if iline_member[mc+1] != nil - op1 = op_line.gsub(/,+.*$/, "") - end - if iline_member[mc+2] != nil - op2 = op_line.scan(/,.+$/).to_s.delete(", ") - end - if instr_list[pc] == nil - instr_list[pc] = [lc, pc, opc , op1 , op2] - pc += 1 - else - STDERR.puts format("Error in line %d: Overlapping sections at %3.3X", lc, pc) - exit 1 - end - end; - - # Push labels - if label - label_list = label_list + [label, value] - end -end -file.close - -# -------------------------------------------------------- -def instr(opcode) - return format("\"%6.6B\" & X\"%3.3X\"",opcode ,0) -end - -def tcl_bits(pc, opcode) - return format("%10.10B%6.6B%12.12B",pc, opcode ,0) -end - -def instr_k(opcode, k) - return format("\"%6.6B\" & X\"%3.3X\"",opcode ,k) -end - -def tcl_bits_k(pc, opcode, k) - return format("%10.10B%6.6B%12.12B",pc, opcode ,k) -end - -def instr_r(opcode, r) - return format("\"%6.6B\" & X\"%2.2X%X\"",opcode ,0, r) -end - -def tcl_bits_r(pc, opcode, r) - return format("%10.10B%6.6B%8.8B%4.4B",pc, opcode ,0,r) -end - -def instr_kr(opcode, k, r) - return format("\"%6.6B\" & X\"%2.2X%X\"",opcode,k, r) -end - -def tcl_bits_kr(pc, opcode, k, r) - return format("%10.10B%6.6B%8.8B%4.4B",pc, opcode, k, r) -end - -def instr_rk(opcode, r, k) - return format("\"%6.6B\" & X\"%2.2X%X\"",opcode,k, r) -end - -def tcl_bits_rk(pc, opcode, r, k) - return format("%10.10B%6.6B%8.8B%4.4B",pc, opcode, k, r) -end - -def instr_rr(opcode, ra, rb) - return format("\"%6.6B\" & X\"%X%X%X\"",opcode,0, rb, ra) -end - -def tcl_bits_rr(pc, opcode, ra, rb) - return format("%10.10B%6.6B%4.4B%4.4B%4.4B",pc, opcode, 0, rb, ra) -end - -# -------------------------------------------------------- -# Read mnemonic set -# -------------------------------------------------------- -filename = OPC_LIST_NAME -if !File.exists?(filename) - STDERR.puts "#{filename} does not exist" - exit 1 -end - -mnemo_list = [] -num_opcodes = 0 -file = File.open(filename, "r") -file.each do |raw_line| - mnemo_list[num_opcodes] = raw_line.split(" ")[1] - num_opcodes += 1 -end - -# -------------------------------------------------------- -# Pass 2 -# -------------------------------------------------------- -pc = 0 -opc_start = 2 -num_errors = 0 -vhdl_trans_list = [nil] -vhdl_comment_list = [nil] -vhdl_tcl_list = [nil] -instr_list.each do |instruct| - - # puts instruct - if instruct == nil - vhdl_trans_list[pc] = format("\"%6.6B\" & X\"%3.3X\"",0 ,0) - vhdl_comment_list[pc] = format("0x%3.3X:", pc) - vhdl_tcl_list[pc] = tcl_bits(pc, 0) - pc += 1 - next - end - - # determine arglen of instruction - ilen = 0 - if instruct[opc_start+1] == nil - arglen = 0 - elsif instruct[opc_start+2] == nil - arglen = 1 - elsif instruct[opc_start+3] == nil - arglen = 2 - end - - # Symbol substitution - error = false - for i in (1..3) - subst_pos = opc_start+i - if instruct[subst_pos] == nil - next - end - expr_token = "" - expr_subst = nil - is_direct = true; - -# instruct[subst_pos] = instruct[subst_pos].delete(" ") - - # checks R0 .. R16, Mnemonics - instr_str = instruct[subst_pos] - if 0 == (instr_str =~ /\(.+\)/) - instr_str = instr_str.delete("()") - is_direct = false; - end - - expr_token = instr_str.split(/\+|\-|\*|\//)[0] - if (0 != (expr_token =~ /R[0-9]+/)) && (0 != (expr_token =~ /\d+/)) - idx = label_list.rindex(expr_token) - if idx != nil - expr_subst = label_list[idx+1] - instruct[subst_pos] = instruct[subst_pos].gsub(expr_token, expr_subst) - else - STDERR.puts format("Error in line %d: Symbol \"%s\" not found", instruct[0], expr_token) - error = true - end - end - - if expr_subst != nil - if 0 == (expr_subst =~ /\d+/) - if is_direct == true - instruct[subst_pos] = format("0x%2.2X", eval(instruct[subst_pos])) - else - instruct[subst_pos] = format("(0x%2.2X)", eval(instruct[subst_pos])) - end - else - if 0 != (expr_subst =~ /R[0-9]+/) - STDERR.puts format("Error in line %d: Invalid expression \"%s\"", instruct[0], expr_subst) - error = true - end - end - end - end - - # Parse operands - reg = [0,0] - kk = 0 - format = instruct[opc_start] - for i in (0..1) - if instruct[opc_start+i+1] =~ Regexp.new("R[0-9]+") - # Check indirect addressing - reg[i] = instruct[opc_start+i+1].delete("R()").to_i - format += "|R" - if reg[i] > 15 - STDERR.puts format("Error in line %d: Invalid register \"R%d\" specified", instruct[0], reg[i]) - error = true - end - else - if instruct[opc_start+i+1] =~ Regexp.new("[0-9A-F]+") - kk = instruct[opc_start+i+1].delete("()").to_i(16) - format += "|K" - end - end - if instruct[opc_start+i+1] =~ Regexp.new("\\(.+\\)") - format += "i"; - end - end - - # Output instruction - opcode = mnemo_list.rindex(format).to_i - mnemo = instruct[2]; - - case format - when "NOP", "HALT", "RET", "RETI" - vhdl_trans_list[pc] = instr(opcode) - vhdl_tcl_list[pc] = tcl_bits(pc, opcode) - minstr_comment = format("0x%3.3X: %s", pc, mnemo) - when "MOVC|R|Ri", "MOVX|R|Ri" - vhdl_trans_list[pc] = instr_rr(opcode, reg[0], reg[1]); - vhdl_tcl_list[pc] = tcl_bits_rr(pc, opcode, reg[0], reg[1]) - minstr_comment = format("0x%3.3X: %s R%2.2d, (R%2.2d)", pc, mnemo, reg[0], reg[1]) - when "MOV|R|R", "SUB|R|R", "ADD|R|R", "AND|R|R", "OR|R|R", "XOR|R|R", "CMP|R|R" - vhdl_trans_list[pc] = instr_rr(opcode, reg[0], reg[1]); - vhdl_tcl_list[pc] = tcl_bits_rr(pc, opcode, reg[0], reg[1]) - minstr_comment = format("0x%3.3X: %s R%2.2d, R%2.2d", pc, mnemo, reg[0], reg[1]) - when "MOVC|Ri|R", "MOVX|Ri|R" - vhdl_trans_list[pc] = instr_rr(opcode, reg[1], reg[0]); - vhdl_tcl_list[pc] = tcl_bits_rr(pc, opcode, reg[1], reg[0]) - minstr_comment = format("0x%3.3X: %s (R%2.2d), R%2.2d", pc, mnemo, reg[1], reg[0]) - when "MOVC|Ri|K", "MOVX|Ri|K", "COUT|Ri|K", "XOUT|Ri|K" - vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk); - vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk) - minstr_comment = format("0x%3.3X: %s (R%2.2d), 0x%2.2X", pc, mnemo, reg[0], kk) - when "MOVC|R|Ki", "MOVX|R|Ki", "CIN|R|Ki", "XIN|R|Ki" - vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk); - vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk) - minstr_comment = format("0x%3.3X: %s R%2.2d, (0x%2.2X)", pc, mnemo, reg[0], kk) - when "MOV|R|K", "SUB|R|K", "ADD|R|K", "AND|R|K", "OR|R|K", "XOR|R|K", "CMP|R|K" - vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk); - vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk) - minstr_comment = format("0x%3.3X: %s R%2.2d, 0x%2.2X", pc, mnemo, reg[0], kk) - when "MOVC|Ki|R", "MOVC|Ki|R", "MOVX|Ki|R", "MOVX|Ki|R", "COUT|Ki|R", "XOUT|Ki|R" - vhdl_trans_list[pc] = instr_kr(opcode, kk, reg[1]); - vhdl_tcl_list[pc] = tcl_bits_kr(pc, opcode, kk, reg[1]) - minstr_comment = format("0x%3.3X: %s (0x%2.2X), R%2.2d", pc, mnemo, kk, reg[1]) - when "CALL|K", "JMP|K", "JNZ|K", "JZ|K","JNC|K", "JC|K", "JLT|K", "JGT|K", "JLE|K", "JGE|K", "JEQ|K", "JNE|K" - vhdl_trans_list[pc] = instr_k(opcode, kk) - vhdl_tcl_list[pc] = tcl_bits_k(pc, opcode, kk) - minstr_comment = format("0x%3.3X: %s 0x%3.3X", pc, mnemo, kk) - when "PUSH|R", "POP|R", "SHR|R", "SHL|R", "ROR|R", "ROL|R", "RORC|R", "ROLC|R" - vhdl_trans_list[pc] = instr_r(opcode, reg[0]) - vhdl_tcl_list[pc] = tcl_bits_r(pc, opcode, reg[0]) - minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0]) - when "TST|R" - kk = 0 - minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0]) - opcode = mnemo_list.rindex("CMP|R|K").to_i - vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk); - vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk) - when "INC|R" - kk = 1 - minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0]) - opcode = mnemo_list.rindex("ADD|R|K").to_i - vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk); - vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk) - when "DEC|R" - kk = 1 - minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0]) - opcode = mnemo_list.rindex("SUB|R|K").to_i - vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk); - vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk) - else - STDERR.puts format("Error in line %d: Not yet implemented %s", instruct[0], format) - error = true - end - - if error - num_errors += 1 - break - end - vhdl_comment_list[pc] = minstr_comment - - puts vhdl_trans_list[pc] + " -- " + minstr_comment - - pc += 1 -end - -# -------------------------------------------------------- -# Output ROM file -# -------------------------------------------------------- -if num_errors == 0 - - filename = format("rom_%s.vhdl.snip", PROJECT_NAME) - file = File.open(filename, "w") - - file.puts format("ENTITY %s IS\n", ENTITY_NAME) - file.puts format("\tPort (\n") - file.puts format("\tclk\t\t\t: in STD_LOGIC;\n") - file.puts format("\tce\t\t\t: in STD_LOGIC;\n") - file.puts format("\taddr\t\t: in %s;\n", ENTITY_ADDR_TYPE) - file.puts format("\tdout\t\t: out %s\n", ENTITY_DATA_TYPE) - file.puts format("\t);\n") - file.puts format("END %s;\n", ENTITY_NAME) - file.puts format("\n") - file.puts format("ARCHITECTURE %s OF %s IS \n", PROJECT_NAME, ENTITY_NAME) - file.puts format("\n") - file.puts format("\ttype instruction_rom_t is array (0 to %d) of %s;\n", pc-1, ENTITY_DATA_TYPE) - file.puts format("\n") - file.puts format("\tconstant instruction_rom : instruction_rom_t :=\n") - file.puts format("\t(\n"); - for i in (0..pc-2) - file.puts "\t\t" + vhdl_trans_list[i] + ", -- " + vhdl_comment_list[i] + "\n" - end; - file.puts "\t\t" + vhdl_trans_list[pc-1] + " -- " + vhdl_comment_list[pc-1] + "\n" - file.puts format("\t);\n") - file.puts format("\n") - file.puts format("begin") - file.puts format("\n") - file.puts format("PROM_READ:") - file.puts format("\tprocess(clk, ce)\n") - file.puts format("\tbegin\n") - file.puts format("\t\tif rising_edge(clk) and ce = '1' then\n") - file.puts format("\t\t\tdout <= instruction_rom(to_integer(addr));\n") - file.puts format("\t\tend if;\n") - file.puts format("\tend process;\n") - file.puts format("\n") - file.puts format("end %s;\n", PROJECT_NAME) - puts format("ROM file written to \"%s\"\n",filename) - file.close -end -if num_errors == 0 - - filename = format("preinit_%s.vhdl.snip", PROJECT_NAME) - file = File.open(filename, "w") - - file.puts format("\tsignal instruction_rom : instruction_rom_t :=\n") - file.puts format("\t(\n"); - for i in (0..pc-2) - file.puts "\t\t" + vhdl_trans_list[i] + ", -- " + vhdl_comment_list[i] + "\n" - end; - if pc < (MAX_SIZE_ROM-1) - file.puts "\t\t" + vhdl_trans_list[pc-1] + ", -- " + vhdl_comment_list[pc-1] + "\n" - for i in (pc..(MAX_SIZE_ROM-2)) - file.puts "\t\t" + instr(0) + ",\n" - end; - file.puts "\t\t" + instr(0) + "\n" - else - file.puts "\t\t" + vhdl_trans_list[pc-1] + " -- " + vhdl_comment_list[pc-1] + "\n" - end - file.puts format("\t);\n") - puts format("PREINIT file written to \"%s\"\n",filename) - file.close -end -if num_errors == 0 - filename = format("rom_%s.tcl.snip", PROJECT_NAME) - file = File.open(filename, "w") - for i in (0..pc-1) - # Chipscope 8.1 -# file.puts format("jtag_shiftdr $handle -buffer \"%s\" -endstate RTI -device $devid", vhdl_tcl_list[i].reverse); - - # Chipscope 9.1 - file.puts format("\# %s", vhdl_comment_list[i]) - file.puts format("::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 %d \"%8.8X\"\n\n", vhdl_tcl_list[i].length, vhdl_tcl_list[i].to_i(2)); - end; - puts format("TCL snippet written to \"%s\"\n",filename) - file.close -end - -# -------------------------------------------------------- -# Output final statistics -# -------------------------------------------------------- -if num_errors == 0 - puts "Program uses #{pc} instruction addresses" - puts "No errors found" - exit 0 -else - puts "#{num_errors} errors found" - exit 1 -end diff --git a/lib/CPUs/JCpu/tools/jasm.rb b/lib/CPUs/JCpu/tools/jasm.rb deleted file mode 100644 index 0959ba9..0000000 --- a/lib/CPUs/JCpu/tools/jasm.rb +++ /dev/null @@ -1,814 +0,0 @@ -#!/usr/bin/env ruby - -# ---------------------------------------------------------------------- -# Project: JCPU, a portable 8-bit RISC CPU written in VHDL -# This file: A small assembler for the JCPU -# -# Copyright (C) 2007 J. Ahrensfeld -# -# This program is free software: you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation, either version 3 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see . -# -# For questions and ideas, please contact the author at jens@jayfield.org -# -# --------------------------------------------------------------------- - -arg = $* -FILE_SUFFIX = "jsm" -IROM_MAX_SIZE = 1024 -IROM_ENTITY_NAME = "irom" -IROM_DATA_TYPE = "inst_t" -IROM_ADDR_TYPE = "inst_addr_t" -XROM_MAX_SIZE = 256 -XROM_DATA_TYPE = "dmem_data_t" -XROM_ADDR_TYPE = "dmem_addr_t" -XROM_ENTITY_NAME = "xrom" -OPC_LIST_NAME = "/cygdrive/w/vhdl/lib/CPUs/JCpu/tools/opc.list" - -# -------------------------------------------------------- -class Parser - def curr_segment - @curr_segment - end - def curr_segment=(arg) - @curr_segment=arg - end - def add_label(labelname, addr) - @label_list = @label_list + [labelname, addr] - end - def getLabelIdByName(label) - return @label_list.rindex(label) - end - def getLabelNameById(id) - return @label_list[id] - end - def put_instr(name, lc, opc , op1 , op2) - if get_instr != nil - STDERR.puts format("Error in line %d: Overlapping sections at %3.3X", lc, @pc) - exit 1 - end - @instr_list[@pc] = [lc, @pc, opc , op1 , op2, name] - end - def get_instr - return @instr_list[@pc] - end - def put_xmem(value, lc) - if get_xmem != nil - STDERR.puts format("Error in line %d: Overlapping sections at %3.3X (%s)", lc, xmem_dc, curr_segment) - exit 1 - end - @xmem[xmem_dc] = value - @xmem_dc = xmem_dc + 1 - end - def get_xmem - return @xmem[xmem_dc] - end - def xmem - return @xmem - end - def put_cmem(value, lc) - if get_cmem(page) != nil - STDERR.puts format("Error in line %d: Overlapping sections at %3.3X (%s)", lc, cmem_dc, curr_segment) - exit 1 - end - @cmem[page][cmem_dc] = value - @cmem_dc[page] = cmem_dc + 1 - end - def get_cmem(pg) - return @cmem[pg][cmem_dc] - end - def cmem(page) - return @cmem[page] - end - def cmem_dc=(addr) - @cmem_dc[page] = addr - end - def cmem_dc - @cmem_dc[page] - end - def xmem_dc=(addr) - @xmem_dc = addr - end - def xmem_dc - @xmem_dc - end - def page=(page) - @page = page; - end - def page - @page; - end - def pc=(pc) - @pc = pc; - if (pc > @pc_max) - @pc_max = pc - end - end - def pc - @pc; - end - def pc_max - @pc_max; - end - def instr_list - @instr_list - end - def label_list - @label_list - end - - def initialize() - @pc_max = 0 - @pc = 0 # Program counter - @cmem_dc = [0,0,0,0] # chip data counter - @xmem_dc = 0 # xmem data counter - @curr_segment = "UNDEF"; - @page = 0 - @label_list=[[],[]] - @instr_list=[nil] - @cmem = [[],[]]; - @xmem = []; - end - def method_missing(name, *args) - puts "I don't know the method #{name}" - end -end - -# -------------------------------------------------------- -def parse(name, obj) - -lc = 0 # Line counter -file = File.open(name, "r") - -file.each do |raw_line| - lc += 1 - - # Make all upper case - iline = "#{raw_line}".strip - - # Remove comments - iline = iline.gsub(/;.*/, "") - - # Split instruction at spaces - iline_member = iline.split(" ") - - if iline_member[0] == nil - next - end - - mc = 0; - label = nil - clean_line = nil - if (iline_member[0] =~ /\w+:/) - mc += 1 - label = iline_member[0].delete(":") - if obj.getLabelIdByName(label) != nil - STDERR.puts format("Error in line %d: Duplicate label \"%s\" found", lc, label) - exit 1 - end - end - - token = iline_member[mc] - if token - token = token.upcase - end - - case token - when nil - if obj.curr_segment == "CMEM" - curr_addr = format("0x%3.3X",obj.cmem_dc) - elsif obj.curr_segment == "XMEM" - curr_addr = format("0x%3.3X",obj.xmem_dc) - elsif obj.curr_segment == "CODE" - curr_addr = format("0x%3.3X",obj.pc) - else - STDERR.puts format("Error in line %d: Undefined segment", lc) - exit 1 - end - when "INCLUDE" - if iline_member[mc+1] == nil - STDERR.puts format("Error in line %d: %s needs argument!", lc, token) - exit 1 - end - inc_name = iline_member[mc+1].delete("\"") - puts format("Inserting \"%s\" into \"%s\" at line %d", inc_name, name, lc); - parse(inc_name, obj) - when "EQU" - if iline_member[mc+1] == nil - STDERR.puts format("Error in line %d: %s needs argument!", lc, token) - exit 1 - end - if 0 == (iline_member[mc+1] =~ /\d+/) - curr_addr = format("0x%2.2X",eval(iline_member[mc+1..iline_member.nitems].to_s)) - else - curr_addr = iline_member[mc+1] - end - when "ORG" - if iline_member[mc+1] == nil - STDERR.puts format("Error in line %d: %s needs argument!", lc, token) - exit 1 - end - offset = eval(iline_member[mc+1..iline_member.nitems].to_s) - case obj.curr_segment - when "CODE" - obj.pc = offset - curr_addr = format("0x%3.3X",obj.pc) - when "CMEM" - obj.cmem_dc = offset - when "XMEM" - obj.xmem_dc = offset - - end - when "CODE" - curr_addr = format("0x%3.3X",obj.pc) - obj.curr_segment = "CODE"; - when "CDATA", "CMEM" - if iline_member[mc+1] == nil - STDERR.puts format("Error in line %d: %s needs argument!", lc, token) - exit 1 - end - obj.curr_segment = "CMEM"; - obj.page = iline_member[mc+1].to_i(16) - when "XDATA", "XMEM" - obj.curr_segment = "XMEM"; - when "DC" - len = 0; - if iline_member[mc+1] == nil - STDERR.puts format("Error in line %d: %s needs argument!", lc, token) - exit 1 - end - if obj.curr_segment == "CMEM" - STDERR.puts format("Error in line %d: %s cannot be initialized!", lc, obj.curr_segment) - exit 1 - elsif obj.curr_segment == "XMEM" - curr_addr = format("0x%2.2X",obj.xmem_dc) - dc_old = obj.xmem_dc; - val_array = raw_line.split(/dc|DC|Dc|dC/)[1].delete("\t").gsub(/;.*/, "").split(",") - - # Parse string literals - val_array.each do |item| - if 0 == (item =~ /.*\".*\"/) - str = item.delete("\"") - puts item - for nn in (0..str.length-1) - if str[nn] > 31 - obj.put_xmem(str[nn], lc); - puts "S: " + str[nn].to_s - len += 1 - end - end; - else - argument = item - puts "B: " + argument - obj.put_xmem(eval(argument), lc); - len += 1 - end - end - puts format("Found DC defining %d bytes at 0x%4.4X in %s", len, dc_old, obj.curr_segment); - else - STDERR.puts format("Error in line %d: Invalid segment %s for \"%s\"", lc, obj.curr_segment, token) - exit 1 - end - when "DB" - if iline_member[mc+1] == nil - STDERR.puts format("Error in line %d: %s needs argument!", lc, token) - exit 1 - end - len = eval(iline_member[mc+1]).to_i - if obj.curr_segment == "CMEM" - curr_addr = format("0x%2.2X",obj.cmem_dc) - puts format("Found DB reserving %d bytes at 0x%4.4X in %s(%d)", len, obj.cmem_dc, obj.curr_segment, obj.page); - for nn in (1..len) - obj.put_cmem(0, lc) - end - elsif obj.curr_segment == "XMEM" - curr_addr = format("0x%2.2X",obj.xmem_dc) - puts format("Found DB reserving %d bytes at 0x%4.4X in %s", len, obj.xmem_dc, obj.curr_segment); - for nn in (1..len) - obj.put_xmem(0, lc) - end - else - STDERR.puts format("Error in line %d: Invalid segment %s for \"%s\"", lc, obj.curr_segment, token) - exit 1 - end - else - if obj.curr_segment != "CODE" - STDERR.puts format("Error in line %d: Invalid segment %s for \"%s\"", lc, obj.curr_segment, token) - exit 1 - end - - op_line = iline_member[mc+1..iline_member.nitems].to_s - curr_addr = format("0x%3.3X",obj.pc) - opc = token - if iline_member[mc+1] != nil - op1 = op_line.gsub(/,+.*$/, "") - end - if iline_member[mc+2] != nil - op2 = op_line.scan(/,.+$/).to_s.delete(", ") - end - obj.put_instr(name, lc, opc, op1, op2) - obj.pc = obj.pc + 1 - end; - - # Push labels - if label - obj.add_label(label, curr_addr) - end -end -file.close -return obj -end - -# -------------------------------------------------------- -# Instruction formatting -# -------------------------------------------------------- -def instr(opcode) - return format("\"%6.6B\" & X\"%3.3X\"",opcode ,0) -end - -def tcl_bits(pc, opcode) - return format("%12.12B%8.8B%12.12B",pc, opcode ,0) -end - -def instr_k(opcode, k) - return format("\"%6.6B\" & X\"%3.3X\"",opcode ,k) -end - -def tcl_bits_k(pc, opcode, k) - return format("%12.12B%8.8B%12.12B",pc, opcode ,k) -end - -def instr_r(opcode, r) - return format("\"%6.6B\" & X\"%2.2X%X\"",opcode ,0, r) -end - -def tcl_bits_r(pc, opcode, r) - return format("%12.12B%8.8B%8.8B%4.4B",pc, opcode ,0,r) -end - -def instr_kr(opcode, k, r) - return format("\"%6.6B\" & X\"%2.2X%X\"",opcode,k, r) -end - -def tcl_bits_kr(pc, opcode, k, r) - return format("%12.12B%8.8B%8.8B%4.4B",pc, opcode, k, r) -end - -def instr_rk(opcode, r, k) - return format("\"%6.6B\" & X\"%2.2X%X\"",opcode,k, r) -end - -def tcl_bits_rk(pc, opcode, r, k) - return format("%12.12B%8.8B%8.8B%4.4B",pc, opcode, k, r) -end - -def instr_rr(opcode, ra, rb) - return format("\"%6.6B\" & X\"%X%X%X\"",opcode,0, rb, ra) -end - -def tcl_bits_rr(pc, opcode, ra, rb) - return format("%12.12B%8.8B%4.4B%4.4B%4.4B",pc, opcode, 0, rb, ra) -end - -# -------------------------------------------------------- -# Open file -# -------------------------------------------------------- -filename = arg.to_s -if !File.exists?(filename) - STDERR.puts "#{filename} does not exist" - exit 1 -end -PROJECT_NAME = File.basename(filename, "." + FILE_SUFFIX) - -# -------------------------------------------------------- -# Pass 1 -# -------------------------------------------------------- -first_pass = Parser.new(); -parse(filename, first_pass) - -# -------------------------------------------------------- -# Read mnemonic set -# -------------------------------------------------------- -filename = OPC_LIST_NAME -if !File.exists?(filename) - STDERR.puts "#{filename} does not exist" - exit 1 -end - -mnemo_list = [] -num_opcodes = 0 -file = File.open(filename, "r") -file.each do |raw_line| - mnemo_list[num_opcodes] = raw_line.split(" ")[1] - num_opcodes += 1 -end - -# -------------------------------------------------------- -# Pass 2 -# -------------------------------------------------------- -pc = 0 -opc_start = 2 -num_errors = 0 -vhdl_trans_list = [nil] -vhdl_comment_list = [nil] -vhdl_tcl_list = [nil] - -# ToDo: Use class-methods -label_list = first_pass.label_list -instr_list = first_pass.instr_list - -instr_list.each do |instruct| - - # puts instruct - if instruct == nil - vhdl_trans_list[pc] = format("\"%6.6B\" & X\"%3.3X\"",0 ,0) - vhdl_comment_list[pc] = format("0x%3.3X:", pc) - vhdl_tcl_list[pc] = tcl_bits(pc, 0) - pc += 1 - next - end - - # determine arglen of instruction - ilen = 0 - if instruct[opc_start+1] == nil - arglen = 0 - elsif instruct[opc_start+2] == nil - arglen = 1 - elsif instruct[opc_start+3] == nil - arglen = 2 - end - - # Symbol substitution - error = false - for i in (1..2) - subst_pos = opc_start+i - if instruct[subst_pos] == nil - next - end - expr_token = "" - expr_subst = nil - is_direct = true; - - # checks R0 .. R16, Mnemonics - instruct[subst_pos] = instruct[subst_pos].gsub(/'low/, "") - if (nil != (instruct[subst_pos] =~ /'high/)) - instruct[subst_pos]= format("%s/256", instruct[subst_pos].gsub(/'high/, "")) - end - instr_str = instruct[subst_pos] - if 0 == (instr_str =~ /\(.+\)/) - instr_str = instr_str.delete("()") - is_direct = false; - end - - expr_token = instr_str.split(/\+|\-|\*|\/|\||\&/)[0] - if (0 != (expr_token =~ /R[0-9]+/)) && (0 != (expr_token =~ /\d+/)) - idx = label_list.rindex(expr_token) - if idx != nil - expr_subst = label_list[idx+1] - instruct[subst_pos] = instruct[subst_pos].gsub(expr_token, expr_subst) - else - STDERR.puts format("%s: Error in line %d: Symbol \"%s\" not found", instruct[5], instruct[0], expr_token) - error = true - end - end - - if expr_subst != nil - if 0 == (expr_subst =~ /\d+/) - if is_direct == true - instruct[subst_pos] = format("0x%2.2X", eval(instruct[subst_pos])) - else - instruct[subst_pos] = format("(0x%2.2X)", eval(instruct[subst_pos])) - end - else - if 0 != (expr_subst =~ /R[0-9]+/) - STDERR.puts format("%s: Error in line %d: Invalid expression \"%s\"", instruct[5], instruct[0], expr_subst) - error = true - end - end - end - end - - # Parse operands - reg = [0,0] - kk = 0 - format = instruct[opc_start] - for i in (0..1) - if instruct[opc_start+i+1] =~ Regexp.new("R[0-9]+") - # Check indirect addressing - reg[i] = instruct[opc_start+i+1].delete("R()").to_i - format += "|R" - if reg[i] > 15 - STDERR.puts format("%s: Error in line %d: Invalid register \"R%d\" specified", instruct[5], instruct[0], reg[i]) - error = true - end - else - if instruct[opc_start+i+1] =~ Regexp.new("[0-9A-F]+") - kk = eval(instruct[opc_start+i+1].delete("()")) - format += "|K" - end - end - if instruct[opc_start+i+1] =~ Regexp.new("\\(.+\\)") - format += "i"; - end - end - - if error - num_errors += 1 - break - end - - # Output instruction - opcode = mnemo_list.rindex(format).to_i - mnemo = instruct[2]; - - case format - # Native instructions - when "NOP", "HALT", "RET", "RETI", "SETC" - vhdl_trans_list[pc] = instr(opcode) - vhdl_tcl_list[pc] = tcl_bits(pc, opcode) - minstr_comment = format("0x%3.3X: %s", pc, mnemo) - when "MOVC|R|Ri", "MOVX|R|Ri" - vhdl_trans_list[pc] = instr_rr(opcode, reg[0], reg[1]); - vhdl_tcl_list[pc] = tcl_bits_rr(pc, opcode, reg[0], reg[1]) - minstr_comment = format("0x%3.3X: %s R%2.2d, (R%2.2d)", pc, mnemo, reg[0], reg[1]) - when "MOV|R|R", "SUB|R|R", "SUBC|R|R", "ADD|R|R", "ADDC|R|R", "AND|R|R", "OR|R|R", "XOR|R|R", "CMP|R|R" - vhdl_trans_list[pc] = instr_rr(opcode, reg[0], reg[1]); - vhdl_tcl_list[pc] = tcl_bits_rr(pc, opcode, reg[0], reg[1]) - minstr_comment = format("0x%3.3X: %s R%2.2d, R%2.2d", pc, mnemo, reg[0], reg[1]) - when "MOVC|Ri|R", "MOVX|Ri|R" - vhdl_trans_list[pc] = instr_rr(opcode, reg[1], reg[0]); - vhdl_tcl_list[pc] = tcl_bits_rr(pc, opcode, reg[1], reg[0]) - minstr_comment = format("0x%3.3X: %s (R%2.2d), R%2.2d", pc, mnemo, reg[1], reg[0]) - when "MOVC|Ri|K", "MOVX|Ri|K", "COUT|Ri|K", "XOUT|Ri|K" - kk = kk % 256; - vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk); - vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk) - minstr_comment = format("0x%3.3X: %s (R%2.2d), 0x%2.2X", pc, mnemo, reg[0], kk) - when "MOVC|R|Ki", "MOVX|R|Ki", "CIN|R|Ki", "XIN|R|Ki" - vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk); - vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk) - minstr_comment = format("0x%3.3X: %s R%2.2d, (0x%2.2X)", pc, mnemo, reg[0], kk) - when "MOV|R|K", "SUB|R|K", "SUBC|R|K", "ADD|R|K", "ADDC|R|K", "AND|R|K", "OR|R|K", "XOR|R|K", "CMP|R|K" - kk = kk % 256; - vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk); - vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk) - minstr_comment = format("0x%3.3X: %s R%2.2d, 0x%2.2X", pc, mnemo, reg[0], kk) - when "SUB|K|R", "SUBC|K|R" - kk = kk % 256; - vhdl_trans_list[pc] = instr_kr(opcode, kk, reg[1]); - vhdl_tcl_list[pc] = tcl_bits_kr(pc, opcode, kk, reg[1]) - minstr_comment = format("0x%3.3X: %s 0x%2.2d, R%2.2X", pc, mnemo, kk, reg[1]) - when "MOVC|Ki|R", "MOVC|Ki|R", "MOVX|Ki|R", "MOVX|Ki|R", "COUT|Ki|R", "XOUT|Ki|R" - vhdl_trans_list[pc] = instr_kr(opcode, kk, reg[1]); - vhdl_tcl_list[pc] = tcl_bits_kr(pc, opcode, kk, reg[1]) - minstr_comment = format("0x%3.3X: %s (0x%2.2X), R%2.2d", pc, mnemo, kk, reg[1]) - when "CALL|K", "JMP|K", "JNZ|K", "JZ|K","JNC|K", "JC|K", "JLT|K", "JGT|K", "JLE|K", "JGE|K", "JEQ|K", "JNE|K" - vhdl_trans_list[pc] = instr_k(opcode, kk) - vhdl_tcl_list[pc] = tcl_bits_k(pc, opcode, kk) - minstr_comment = format("0x%3.3X: %s 0x%3.3X", pc, mnemo, kk) - when "PUSH|R", "POP|R", "SHR|R", "SHL|R", "ROR|R", "ROL|R", "RORC|R", "ROLC|R", "SWAP|R" - vhdl_trans_list[pc] = instr_r(opcode, reg[0]) - vhdl_tcl_list[pc] = tcl_bits_r(pc, opcode, reg[0]) - minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0]) - # Synthetic instructions - when "CLRC" - kk = 0; - minstr_comment = format("0x%3.3X: %s", pc, mnemo) - opcode = mnemo_list.rindex("SUB|R|K").to_i - vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk); - vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk) - when "TST|R" - kk = 0 - minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0]) - opcode = mnemo_list.rindex("CMP|R|K").to_i - vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk); - vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk) - when "NEG|R" - kk = 0 - minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0]) - opcode = mnemo_list.rindex("SUB|K|R").to_i - vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk); - vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk) - when "NOT|R" - kk = 0 - minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0]) - opcode = mnemo_list.rindex("XOR|R|K").to_i - vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk); - vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk) - when "INC|R" - kk = 1 - minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0]) - opcode = mnemo_list.rindex("ADD|R|K").to_i - vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk); - vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk) - when "DEC|R" - kk = 1 - minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0]) - opcode = mnemo_list.rindex("SUB|R|K").to_i - vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk); - vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk) - else - STDERR.puts format("%s: Error in line %d: Not yet implemented %s", instruct[5], instruct[0], format) - error = true - end - - if error - num_errors += 1 - break - end - - vhdl_comment_list[pc] = minstr_comment - - puts vhdl_trans_list[pc] + " -- " + minstr_comment - - pc += 1 -end - -# -------------------------------------------------------- -# Output ROM file -# -------------------------------------------------------- -if num_errors == 0 - - # I-ROM VHDL-ROM - filename = format("%s.irom.vhdl.snip", PROJECT_NAME) - file = File.open(filename, "w") - - file.puts format("ENTITY %s IS\n", IROM_ENTITY_NAME) - file.puts format("\tPort (\n") - file.puts format("\tclk\t\t\t: in STD_LOGIC;\n") - file.puts format("\tce\t\t\t: in STD_LOGIC;\n") - file.puts format("\taddr\t\t: in %s;\n", IROM_ADDR_TYPE) - file.puts format("\tdout\t\t: out %s\n", IROM_DATA_TYPE) - file.puts format("\t);\n") - file.puts format("END %s;\n", IROM_ENTITY_NAME) - file.puts format("\n") - file.puts format("ARCHITECTURE %s OF %s IS \n", PROJECT_NAME, IROM_ENTITY_NAME) - file.puts format("\n") - file.puts format("\ttype imem_rom_t is array (0 to %d) of %s;\n", [IROM_MAX_SIZE, pc].min-1 , IROM_DATA_TYPE) - file.puts format("\n") - file.puts format("\t-- Assembled from %s.%s", PROJECT_NAME, FILE_SUFFIX) - file.puts format("\tconstant imem_rom : imem_rom_t :=\n") - file.puts format("\t(\n"); - for i in (0..[IROM_MAX_SIZE, pc].min-2) - file.puts "\t\t" + vhdl_trans_list[i] + ", -- " + vhdl_comment_list[i] + "\n" - end; - file.puts "\t\t" + vhdl_trans_list[pc-1] + " -- " + vhdl_comment_list[pc-1] + "\n" - file.puts format("\t);\n") - file.puts format("\n") - file.puts format("begin") - file.puts format("\n") - file.puts format("PROM_READ:") - file.puts format("\tprocess(clk, ce)\n") - file.puts format("\tbegin\n") - file.puts format("\t\tif rising_edge(clk) and ce = '1' then\n") - file.puts format("\t\t\tdout <= imem_rom(to_integer(addr));\n") - file.puts format("\t\tend if;\n") - file.puts format("\tend process;\n") - file.puts format("\n") - file.puts format("end %s;\n", PROJECT_NAME) - puts format("I-ROM file written to \"%s\"\n",filename) - file.close - - # I-ROM VHDL-ROM (loadable) - filename = format("%s.irom_ld.vhdl.snip", PROJECT_NAME) - file = File.open(filename, "w") - - file.puts format("\n\t-- Assembled from %s.%s", PROJECT_NAME, FILE_SUFFIX) - file.puts format("\ttype imem_rom_t is array (0 to %d) of %s;\n", IROM_MAX_SIZE-1, IROM_DATA_TYPE) - file.puts format("\tsignal imem_rom : imem_rom_t :=\n") - file.puts format("\t(\n"); - for i in (0..pc-2) - file.puts "\t\t" + vhdl_trans_list[i] + ", -- " + vhdl_comment_list[i] + "\n" - end; - if pc < (IROM_MAX_SIZE-1) - file.puts "\t\t" + vhdl_trans_list[pc-1] + ", -- " + vhdl_comment_list[pc-1] + "\n" - for i in (pc..(IROM_MAX_SIZE-2)) - file.puts "\t\t" + instr(0) + ",\n" - end; - file.puts "\t\t" + instr(0) + "\n" - else - file.puts "\t\t" + vhdl_trans_list[pc-1] + " -- " + vhdl_comment_list[pc-1] + "\n" - end - file.puts format("\t);\n") - puts format("I-ROM (loadable) file written to \"%s\"\n",filename) - file.close - - # I-ROM TCL-Loader - filename = format("%s.irom.tcl.snip", PROJECT_NAME) - file = File.open(filename, "w") - file.puts format("# Assembled from %s.%s", PROJECT_NAME, FILE_SUFFIX) - file.puts format("# ---------------------------------------------------------------"); - file.puts format("# Shift the USER1 Instruction (b1111000010) into the Instruction Register of FPGA"); - file.puts format("# User 1") - file.puts format("set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength \"3C2\"]\n\n") - for i in (0..pc-1) - # Chipscope 8.1 -# file.puts format("jtag_shiftdr $handle -buffer \"%s\" -endstate RTI -device $devid", vhdl_tcl_list[i].reverse); - - # Chipscope 9.1 - file.puts format("\# %s", vhdl_comment_list[i]) - file.puts format("::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 %d \"%8.8X\"\n\n", vhdl_tcl_list[i].length, vhdl_tcl_list[i].to_i(2)); - end; - puts format("I-ROM TCL-loader written to \"%s\"\n",filename) - file.close - - # X-ROM VHDL-ROM - filename = format("%s.xrom.vhdl.snip", PROJECT_NAME) - file = File.open(filename, "w") - - file.puts format("ENTITY %s IS\n", XROM_ENTITY_NAME) - file.puts format("\tPort (\n") - file.puts format("\tclk\t\t\t: in STD_LOGIC;\n") - file.puts format("\tce\t\t\t: in STD_LOGIC;\n") - file.puts format("\taddr\t\t: in %s;\n", XROM_ADDR_TYPE) - file.puts format("\tdout\t\t: out %s\n", XROM_DATA_TYPE) - file.puts format("\t);\n") - file.puts format("END %s;\n", XROM_ENTITY_NAME) - file.puts format("\n") - file.puts format("ARCHITECTURE %s OF %s IS \n", PROJECT_NAME, XROM_ENTITY_NAME) - file.puts format("\n") - file.puts format("\ttype xmem_rom_t is array (0 to %d) of %s;\n", XROM_MAX_SIZE-1, XROM_DATA_TYPE) - file.puts format("\n") - file.puts format("\t-- Assembled from %s.%s", PROJECT_NAME, FILE_SUFFIX) - file.puts format("\tconstant xmem_rom : xmem_rom_t :=\n") - file.puts format("\t(\n"); - for i in (0..XROM_MAX_SIZE-2) - file.puts format("\t\tX\"%2.2X\", -- 0x%2.2X\n", first_pass.xmem[i], i) - end; - i = XROM_MAX_SIZE-1 - file.puts format("\t\tX\"%2.2X\" -- 0x%2.2X\n", first_pass.xmem[i], i) - file.puts format("\t);\n") - file.puts format("\n") - file.puts format("begin") - file.puts format("\n") - file.puts format("PROM_READ:") - file.puts format("\tprocess(clk, ce)\n") - file.puts format("\tbegin\n") - file.puts format("\t\tif rising_edge(clk) and ce = '1' then\n") - file.puts format("\t\t\tdout <= xmem_rom(to_integer(addr));\n") - file.puts format("\t\tend if;\n") - file.puts format("\tend process;\n") - file.puts format("\n") - file.puts format("end %s;\n", PROJECT_NAME) - puts format("X-ROM file written to \"%s\"\n",filename) - file.close - - # X-ROM VHDL-ROM (loadable) - filename = format("%s.xrom_ld.vhdl.snip", PROJECT_NAME) - file = File.open(filename, "w") - - file.puts format("\n\t-- Assembled from %s.%s", PROJECT_NAME, FILE_SUFFIX) - file.puts format("\ttype xmem_rom_t is array (0 to %d) of %s;\n", XROM_MAX_SIZE-1, XROM_DATA_TYPE) - file.puts format("\tsignal xmem_rom : xmem_rom_t :=\n") - file.puts format("\t(\n"); - for i in (0..XROM_MAX_SIZE-2) - file.puts format("\t\tX\"%2.2X\", -- 0x%2.2X\n", first_pass.xmem[i], i) - end; - i = XROM_MAX_SIZE-1 - file.puts format("\t\tX\"%2.2X\" -- 0x%2.2X\n", first_pass.xmem[i], i) - file.puts format("\t);\n") - puts format("X-ROM (loadable) file written to \"%s\"\n",filename) - file.close - - # X-ROM JTAG-Loader - filename = format("%s.xrom.tcl.snip", PROJECT_NAME) - file = File.open(filename, "w") - file.puts format("# Assembled from %s.%s", PROJECT_NAME, FILE_SUFFIX) - file.puts format("# ---------------------------------------------------------------"); - file.puts format("# Shift the USER2 Instruction (b1111000011) into the Instruction Register of FPGA"); - file.puts format("# User 2") - file.puts format("set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength \"3C3\"]\n\n") - for i in (0..first_pass.xmem.length-1) - # Chipscope 8.1 -# file.puts format("jtag_shiftdr $handle -buffer \"%s\" -endstate RTI -device $devid", vhdl_tcl_list[i].reverse); - - # Chipscope 9.1 - file.puts format("::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 %d \"%2.2X%2.2X\"\n", 16, i, first_pass.xmem[i]); - end; - puts format("X-ROM TCL-loader written to \"%s\"\n",filename) - file.close - -end - -# -------------------------------------------------------- -# Output final statistics -# -------------------------------------------------------- -if num_errors == 0 - puts "Program uses #{first_pass.pc_max} instruction addresses" - puts "No errors found" - exit 0 -else - puts "#{num_errors} errors found" - exit 1 -end - diff --git a/lib/CPUs/JCpu/tools/lib/cg.inc.jsm b/lib/CPUs/JCpu/tools/lib/cg.inc.jsm deleted file mode 100644 index 01c36c4..0000000 --- a/lib/CPUs/JCpu/tools/lib/cg.inc.jsm +++ /dev/null @@ -1,72 +0,0 @@ -; ------------------------------------------------- -; lcd.inc.jsm -; ------------------------------------------------- -; needs xio-address equates for -; reg_cg_char_addr: equ 0xXX ; RW -; reg_cg_line_addr: equ 0xXX ; RW -; reg_cg_data: equ 0xXX ; RW -; reg_cg_ctrl: equ 0xXX ; WO - -; needs delay.inc.jsm - -; ------------------------------------------------- -cg_clr_line: push R0 - mov R0, 2 - xout (reg_cg_ctrl), R0 - pop R0 - ret - -; ------------------------------------------------- -cg_clr_screen: push R0 - mov R0, 1 - xout (reg_cg_ctrl), R0 - pop R0 - ret - -; ------------------------------------------------- -; R0 : char address -; R1 : line address -cg_set_addr: call cg_wait_rdy - xout (reg_cg_line_addr), R1 - xout (reg_cg_char_addr), R0 - ret - -; ------------------------------------------------- -; R0 : character -cg_putchar: call cg_wait_rdy - xout (reg_cg_data), R0 - ret - -; ------------------------------------------------- -; R1 : ptr to string -cg_puts: push R0 -cg_p_lp: movx R0, (R1) - inc R1 - tst R0 - jz ex_cgp - call cg_putchar - jmp cg_p_lp -ex_cgp: pop R0 - ret - -; ------------------------------------------------- -; R1 : ptr to string -cg_clr_puts: call cg_clr_line - call cg_puts - ret - -; ------------------------------------------------- -; R1 : ptr to string -cg_puts_clr: call cg_puts - call cg_clr_line - ret - -; ------------------------------------------------- -cg_wait_rdy: push R0 -cg_wr_lp: xin R0, (reg_hwstat) - and R0, 0x02 - jz cg_wr_lp - pop R0 - ret - -; ------------------------------------------------- diff --git a/lib/CPUs/JCpu/tools/lib/cregs.inc.jsm b/lib/CPUs/JCpu/tools/lib/cregs.inc.jsm deleted file mode 100644 index 06d39d9..0000000 --- a/lib/CPUs/JCpu/tools/lib/cregs.inc.jsm +++ /dev/null @@ -1,7 +0,0 @@ -; JCPU On-Chip register -cpu_revision: equ 0x00 ; RO -cpu_control: equ 0x01 ; R/W -cpu_status: equ 0x02 ; RO -cpu_int_ctrl: equ 0x03 ; RW -cpu_cmem_high: equ 0x04 ; RW -cpu_stack_high: equ 0x05 ; RW diff --git a/lib/CPUs/JCpu/tools/lib/delays.inc.jsm b/lib/CPUs/JCpu/tools/lib/delays.inc.jsm deleted file mode 100644 index 6f002ee..0000000 --- a/lib/CPUs/JCpu/tools/lib/delays.inc.jsm +++ /dev/null @@ -1,64 +0,0 @@ -; ------------------------------------------------- -; Delays -; ------------------------------------------------- -delay1s: push R15 - mov R15, 10 -loop1s: call delay100ms - dec R15 - jnz loop1s - pop R15 - ret - -delay100ms: push R15 - mov R15, 10 -loop100ms: call delay10ms - dec R15 - jnz loop100ms - pop R15 - ret - -delay10ms: push R15 - mov R15, 10 -loop10ms: call delay1ms - dec R15 - jnz loop10ms - pop R15 - ret - -delay1ms: push R15 - mov R15, 10 -loop1ms: call delay100us - dec R15 - jnz loop1ms - pop R15 - ret - -delay100us: push R15 - mov R15, 10 -loop100us: call delay10us - dec R15 - jnz loop100us - pop R15 - ret - -delay10us: push R15 - mov R15, 99 -loop10us: nop - nop - nop - dec R15 - jnz loop10us - pop R15 - ret - -delay1us: push R15 - mov R15, 9 -loop1us: nop - nop - nop - dec R15 - jnz loop1us - pop R15 - ret - -; ------------------------------------------------- diff --git a/lib/CPUs/JCpu/tools/lib/lcd.inc.jsm b/lib/CPUs/JCpu/tools/lib/lcd.inc.jsm deleted file mode 100644 index d2883fa..0000000 --- a/lib/CPUs/JCpu/tools/lib/lcd.inc.jsm +++ /dev/null @@ -1,208 +0,0 @@ -; ------------------------------------------------- -; lcd.inc.jsm -; ------------------------------------------------- -; needs xmem-address definition for -; - lcd_port (LCD-Base) - -; needs delay.inc.jsm - -; ------------------------------------------------- -lcd_cmd: equ 0x00 -lcd_rd: equ 0x20 -lcd_data: equ 0x40 -lcd_enable: equ 0x80 - -LCD_CMD_Z1: equ 0x80 -LCD_CMD_Z2: equ 0xC0 -LCD_CMD_CLEAR: equ 0x01 - -; ------------------------------------------------- -; Init LCD -; ------------------------------------------------- -LCD_init: mov R2, 0x00 - mov R0, 0x03 - call _write_lcd - call delay10ms - mov R2, 0x00 - mov R0, 0x03 - call _write_lcd - call delay10ms - - mov R2, 0x00 - mov R0, 0x02 - call _write_lcd - call delay1ms - - ; 1. Function set: 4-Bit mode, two display lines - mov R0, 0x28 - call LCD_writecmd - - ; 2. Display on, no cursor - mov R0, 0x0C - call LCD_writecmd - - ; 3. Cursor shift during write - mov R0, 0x06 - call LCD_writecmd - - ; 4. Display clear - mov R0, 0x01 - call LCD_writecmd - - ret - -; ------------------------------------------------- -; LCD_waitbsy -; ------------------------------------------------- -LCD_waitbsy: push R0 -bsy_loop: call LCD_readstat - and R0, 0x80 - jz ex_bsy - call delay1us - jmp bsy_loop -ex_bsy: pop R0 - ret - -; ------------------------------------------------- -; LCD_writecmd -; ------------------------------------------------- -; R0 = cmd -LCD_writeaddr: -LCD_writecmd: push R2 - mov R2, lcd_cmd - call LCD_write - pop R2 - ret - -; ------------------------------------------------- -; LCD_putsx -; ------------------------------------------------- -; R1 = address of null-terminated string in XMEM -LCD_putsx: push R0 -putsx_loop: movx R0, (R1) - inc R1 - tst R0 - jz putsx_ex - call LCD_writechar - jmp putsx_loop -putsx_ex: pop R0 - ret - -; ------------------------------------------------- -; LCD_putsc -; ------------------------------------------------- -; R1 = address of null-terminated string in CMEM -LCD_putsc: push R0 -putsc_loop: movc R0, (R1) - inc R1 - tst R0 - jz putsc_ex - call LCD_writechar - jmp putsc_loop -putsc_ex: pop R0 - ret - -; ------------------------------------------------- -; LCD_writechar -; ------------------------------------------------- -; R0 = char -LCD_writedata: -LCD_writechar: push R2 - mov R2, lcd_data - call LCD_write - pop R2 - ret - -; ------------------------------------------------- -; LCD_write -; ------------------------------------------------- -; R0 = input -; R2 = register -LCD_write: call LCD_waitbsy - push R0 - swap R0 - call _write_lcd - pop R0 - call _write_lcd - ret - -; ------------------------------------------------- -; LCD_readstat -; ------------------------------------------------- -; R0 = status -LCD_readstat: push R2 - mov R2, lcd_cmd - call LCD_read - pop R2 - ret - -; ------------------------------------------------- -; LCD_read -; ------------------------------------------------- -; R0 = output -; R2 = register -LCD_read: call _read_lcd - swap R0 - push R0 - call _read_lcd - pop R2 - or R0, R2 - ret - -; ------------------------------------------------- -; _write -; ------------------------------------------------- -; R0 = input -_write_lcd: push R1 - - and R0, 0x0F - mov R1, R0 - or R1, R2 - xout (lcd_port), R1 - call delay1us - - mov R1, R0 - or R1, R2 - or R1, lcd_enable - xout (lcd_port), R1 - call delay1us - - mov R1, R0 - or R1, R2 - xout (lcd_port), R1 - call delay1us - - or R1, lcd_rd - xout (lcd_port), R1 - - pop R1 - ret - -; ------------------------------------------------- -; _read -; ------------------------------------------------- -; R0 = output -_read_lcd: push R1 - - mov R1, lcd_rd - or R1, R2 - xout (lcd_port), R1 - call delay1us - - mov R1, lcd_rd - or R1, R2 - or R1, lcd_enable - xout (lcd_port), R1 - call delay1us - xin R0, (lcd_port) - and R0, 0x0F - - mov R1, lcd_rd - or R1, R2 - xout (lcd_port), R1 - call delay1us - - pop R1 - ret - - \ No newline at end of file diff --git a/lib/CPUs/JCpu/tools/lib/mul8x8.inc.jsm b/lib/CPUs/JCpu/tools/lib/mul8x8.inc.jsm deleted file mode 100644 index 2f66e2a..0000000 --- a/lib/CPUs/JCpu/tools/lib/mul8x8.inc.jsm +++ /dev/null @@ -1,42 +0,0 @@ -; ------------------------------------------------- -; mul8x8.inc.jsm -; ------------------------------------------------- - -; ------------------------------------------------- -; Parameter: -; R0 : operand 1 -; R1 : operand 2 -; Return: -; R0 : product low -; R1 : product high -mul8x8: push R2 - push R3 - push R4 - - mov R4, R1 - mov R1, 0 - mov R2, 0 - mov R3, 0 - -loop1: cmp R4, 0x01 - jeq ende1 - - shr R4 - jnc next1 - - add R2, R0 - addc R3, R1 - -next1: shl R0 - rolc R1 - jmp loop1 - -ende1: add R0, R2 - addc R1, R3 - - pop R4 - pop R3 - pop R2 - ret - -; ------------------------------------------------- diff --git a/lib/CPUs/JCpu/tools/lib/uart.inc.jsm b/lib/CPUs/JCpu/tools/lib/uart.inc.jsm deleted file mode 100644 index 1733305..0000000 --- a/lib/CPUs/JCpu/tools/lib/uart.inc.jsm +++ /dev/null @@ -1,32 +0,0 @@ -; ------------------------------------------------- -; uart.inc.jsm -; ------------------------------------------------- -; needs xmem-address definition for -; - uart_status (Status register) -; - uart_data (Data register) - -; ------------------------------------------------- -; sout -; ------------------------------------------------- -; R0 = input -sout: push R1 -sout1: xin R1, (uart_status) - and R1, 0x02 - jnz sout1 - xout (uart_data), R0 - pop R1 - ret - -; ------------------------------------------------- -; sin -; ------------------------------------------------- -; R0 = output -sin: push R1 -sin1: xin R1, (uart_status) - and R1, 0x10 - jnz sin1 - xin R0, (uart_data) - pop R1 - ret - -; ------------------------------------------------- diff --git a/lib/CPUs/JCpu/tools/lib/utils.inc.jsm b/lib/CPUs/JCpu/tools/lib/utils.inc.jsm deleted file mode 100644 index f354d7c..0000000 --- a/lib/CPUs/JCpu/tools/lib/utils.inc.jsm +++ /dev/null @@ -1,32 +0,0 @@ -; ------------------------------------------------- -; utils.inc.jsm -; ------------------------------------------------- - - -; ------------------------------------------------- -; Parameter -; R0 : Bin value in lower nibble -; Return -; R0 : Hex character representing lower nibble -nibble2hex: and R0, 0x0F - cmp R0, 0x0A - jlt isNum1 - add R0, 0x07 -isNum1: add R0, 0x30 - ret - -; ------------------------------------------------- -; Parameter -; R0 : Bin value -; Return -; R0 : Hex character high -; R1 : Hex character low -bin2hex: push R0 - call nibble2hex - mov R1, R0 - pop R0 - swap R0 - call nibble2hex - ret - -; ------------------------------------------------- diff --git a/lib/CPUs/JCpu/tools/opc.list b/lib/CPUs/JCpu/tools/opc.list deleted file mode 100644 index 59b3cfa..0000000 --- a/lib/CPUs/JCpu/tools/opc.list +++ /dev/null @@ -1,64 +0,0 @@ -0 NOP -1 HALT -2 MOV|R|R -3 MOV|R|K -4 MOVX|R|Ri -5 MOVX|R|Ki -6 MOVX|Ri|R -7 MOVX|Ri|K -8 MOVX|Ki|R -9 MOVC|R|Ri -10 MOVC|R|Ki -11 MOVC|Ri|R -12 MOVC|Ri|K -13 MOVC|Ki|R -14 CMP|R|R -15 CMP|R|K -16 ADD|R|R -17 ADD|R|K -18 ADDC|R|R -19 ADDC|R|K -20 SUB|R|R -21 SUB|R|K -22 SUBC|R|R -23 SUBC|R|K -24 AND|R|R -25 AND|R|K -26 OR|R|R -27 OR|R|K -28 XOR|R|R -29 XOR|R|K -30 SHL|R -31 SHR|R -32 ROL|R -33 ROR|R -34 ROLC|R -35 RORC|R -36 XOUT|Ki|R -37 XOUT|Ri|K -38 COUT|Ki|R -39 COUT|Ri|K -40 XIN|R|Ki -41 CIN|R|Ki -42 SWAP|R -43 SETC -44 UNDEF -45 UNDEF -46 SUB|K|R -47 SUBC|K|R -48 JMP|K -49 JZ|K -50 JNZ|K -51 JC|K -52 JNC|K -53 JLT|K -54 JGT|K -55 JLE|K -56 JGE|K -57 JEQ|K -58 JNE|K -59 CALL|K -60 PUSH|R -61 POP|R -62 RET -63 RETI diff --git a/lib/CPUs/JCpu/tools/regx.rb b/lib/CPUs/JCpu/tools/regx.rb deleted file mode 100644 index 47775c9..0000000 --- a/lib/CPUs/JCpu/tools/regx.rb +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env ruby - -st = "\033[7m" -en = "\033[m" - - while TRUE - print "str> " - STDOUT.flush - str = gets - break if not str - str.chop! - print "pat> " - STDOUT.flush - re = gets - break if not re - re.chop! - str.gsub! re, "#{st}\\&#{en}" - print str, "\n" -end -print "\n" diff --git a/lib/CPUs/JCpu/tools/rom.tcl.tpl b/lib/CPUs/JCpu/tools/rom.tcl.tpl deleted file mode 100644 index 9f5c0dc..0000000 --- a/lib/CPUs/JCpu/tools/rom.tcl.tpl +++ /dev/null @@ -1,61 +0,0 @@ -# ---------------------------------------------------------------------- -# Project: JCPU, a portable 8-bit RISC CPU written in VHDL -# This file: The ROM file for upload to target over JTAG -# -# Copyright (C) 2007 J. Ahrensfeld -# -# This program is free software: you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation, either version 3 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see . -# -# For questions and ideas, please contact the author at jens@jayfield.org -# -# --------------------------------------------------------------------- - -# --------------------------------------------------------------------- -# For Chipscope 9.1 -# --------------------------------------------------------------------- -# Source JTAG/TCL frame work -cd $env(CHIPSCOPE)\\bin\\nt -source csejtag.tcl - -namespace import ::chipscope::* - -# Platform USB Cable -set PLATFORM_USB_CABLE_ARGS [list "port=USB2" "frequency=6000000"] -# frequency="24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000" - -# Create session -set handle [::chipscope::csejtag_session create 0] - -# Open JTAG and lock -set open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS] -set lock_result [::chipscope::csejtag_target lock $handle 1000] - -set devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT] - -# Get Device ID -set devtype "Virtex-4SX" -set devid 2 -set irlength [::chipscope::csejtag_tap get_irlength $handle $devid] -set idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid] - -set CSE_OP $CSEJTAG_SHIFT_READWRITE -set CSE_ES $CSEJTAG_RUN_TEST_IDLE - -# Write Program -# JASM_ROM_INSERT_HERE - -::chipscope::csejtag_target unlock $handle -::chipscope::csejtag_target close $handle -::chipscope::csejtag_session destroy $handle -exit diff --git a/lib/CPUs/JCpu/tools/templates.rb b/lib/CPUs/JCpu/tools/templates.rb deleted file mode 100644 index 632f11c..0000000 --- a/lib/CPUs/JCpu/tools/templates.rb +++ /dev/null @@ -1,44 +0,0 @@ -#!/usr/bin/env ruby - - -template = <<'END' - -- (tv #1342) read output FIFO - ( - cycles => 1, - cm_i => bus_read_init(addr => ADDR_KS_OFIFO_DOUT), - sep => msg(""), - cm_o => bus_no_ack, - irq => (others => '0') - ), - - -- (tv #1343) wait while FIFO is read - ( - cycles => 2, - cm_i => bus_wait_ack, - sep => msg(""), - cm_o => bus_no_ack, - irq => (others => '0') - ), - - -- (tv #1343) wait for ack - ( - cycles => 1, - cm_i => bus_wait_ack, - sep => msg(""), - cm_o => bus_read_ack(dat => #{exp_data}), - irq => (others => '0') - ), - -END - -puts "KS-128 testvectors:\n" -puts "\n" * 3 - - -0.upto(10) { |sk_no| - 3.downto(0) { |sl_no| - exp_data = "slice_32(TC1_SUBKEYS(#{sk_no}), #{sl_no})" - t = template.gsub(/"/, '\\"') - puts eval("format(\"#{t}\")") - } -} diff --git a/lib/CPUs/JCpu/tools/xrom.vhd.tpl b/lib/CPUs/JCpu/tools/xrom.vhd.tpl deleted file mode 100644 index 5f11f86..0000000 --- a/lib/CPUs/JCpu/tools/xrom.vhd.tpl +++ /dev/null @@ -1,32 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: The ROM file for use in your VHDL design --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library work; -use work.cpu_pkg.all; - --- JASM_ROM_INSERT_HERE - diff --git a/lib/CPUs/JCpu/tools/xrom_ld.vhd.tpl b/lib/CPUs/JCpu/tools/xrom_ld.vhd.tpl deleted file mode 100644 index 696487f..0000000 --- a/lib/CPUs/JCpu/tools/xrom_ld.vhd.tpl +++ /dev/null @@ -1,151 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: loadable ROM --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library UNISIM; -use UNISIM.VComponents.all; - -library work; -use work.cpu_pkg.all; - -ENTITY xrom IS - Port ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - addr : in dmem_addr_t; - dout : out dmem_data_t - ); - -END xrom; - -ARCHITECTURE loadable OF xrom IS - - -- JASM_ROM_INSERT_HERE - - signal jtag_ld_clk : STD_LOGIC; - signal jtag_ld_we : STD_LOGIC; - signal jtag_ld_addr : dmem_addr_t; - signal jtag_ld_dout : dmem_data_t; - signal jtag_ld_din : dmem_data_t; - signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic; - signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic; - signal user_regi, user_rego : unsigned (15 downto 0); - constant id : unsigned (15 downto 0) := X"BEEF"; - -begin - --------------------------------------------------------------------------- --- Virtex-4: JTAG Loader --------------------------------------------------------------------------- - i00_BUFG : BUFG - port map - ( - O => bs_clk1, - I => bs_clk0 - ); - - i01_BUFG : BUFG - port map - ( - O => bs_update1, - I => bs_update0 - ); - - BSCAN_VIRTEX4_inst2 : BSCAN_VIRTEX4 - generic map - ( - JTAG_CHAIN => 2 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4) - ) - port map - ( - CAPTURE => bs_capture, -- CAPTURE output from TAP controller - DRCK => bs_clk0, -- Data register output for USER functions - RESET => bs_rst, -- Reset output from TAP controller - SEL => bs_sel, -- USER active output - SHIFT => bs_shift, -- SHIFT output from TAP controller - TDI => bs_tdi, -- TDI output from TAP controller - UPDATE => bs_update0, -- UPDATE output from TAP controller - TDO => bs_tdo -- Data input for USER function - ); - - jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-dmem_data_t'length+1); - jtag_ld_din <= user_regi(dmem_data_t'left downto 0); - jtag_ld_clk <= bs_update1; - jtag_ld_we <= bs_sel; - -sipo: - process (bs_rst, bs_clk1, bs_tdi, bs_shift) - begin - if bs_rst = '1' then - user_regi <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_regi <= bs_tdi & user_regi(user_regi'left downto 1); - end if; - end if; - end process; - -piso: - process (bs_rst, bs_clk1, bs_shift, user_rego) - begin - bs_tdo <= user_rego(0); - if bs_rst = '1' then - user_rego <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_rego <= user_rego(0) & user_rego(user_rego'left downto 1); - else - user_rego <= (user_rego'left downto dmem_data_t'length => '0') & jtag_ld_dout; --- user_rego <= id; - end if; - end if; - end process; - --------------------------------------------------------------------------- --- ROM Read/Write --------------------------------------------------------------------------- -PROM_READ: - process(clk, ce) - begin - if rising_edge(clk) and ce = '1' then - dout <= xmem_rom(to_integer(addr)); - end if; - end process; - -PROM_WRITE: - process(jtag_ld_clk, jtag_ld_we) - begin - if rising_edge(jtag_ld_clk) then - if jtag_ld_we = '1' then - xmem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din; - else - jtag_ld_dout <= xmem_rom(to_integer(jtag_ld_addr)); - end if; - end if; - end process; - --------------------------------------------------------------------------- -end loadable; diff --git a/lib/CPUs/MIPS/bsp/examples/.directory_history b/lib/CPUs/MIPS/bsp/examples/.directory_history deleted file mode 100644 index b367532..0000000 --- a/lib/CPUs/MIPS/bsp/examples/.directory_history +++ /dev/null @@ -1,34 +0,0 @@ -VHDL/lib/CPUs/MIPS/bsp/examples/dbg.c - -VHDL/lib/CPUs/MIPS/bsp/examples/irq.c - -VHDL/lib/CPUs/MIPS/bsp/examples/irq.h - -VHDL/lib/CPUs/MIPS/bsp/examples/kernel.S - -VHDL/lib/CPUs/MIPS/bsp/examples/libsys.c - -VHDL/lib/CPUs/MIPS/bsp/examples/libsys.h - -VHDL/lib/CPUs/MIPS/bsp/examples/mips_gfx.c - -VHDL/lib/CPUs/MIPS/bsp/examples/mips_gfx.h - -VHDL/lib/CPUs/MIPS/bsp/examples/mips_ps2.c - -VHDL/lib/CPUs/MIPS/bsp/examples/mips_ps2.h - -VHDL/lib/CPUs/MIPS/bsp/examples/mipsdis.c - -VHDL/lib/CPUs/MIPS/bsp/examples/mipsdis.h - -VHDL/lib/CPUs/MIPS/bsp/examples/regdef.h - -VHDL/lib/CPUs/MIPS/bsp/examples/startup.S - -VHDL/lib/CPUs/MIPS/bsp/examples/xcpt.c - -VHDL/lib/CPUs/MIPS/bsp/examples/xcpt.h - -VHDL/lib/CPUs/MIPS/bsp/examples/xcpt_asm.h - diff --git a/lib/CPUs/MIPS/bsp/examples/Bessel.c b/lib/CPUs/MIPS/bsp/examples/Bessel.c deleted file mode 100644 index 080fe17..0000000 --- a/lib/CPUs/MIPS/bsp/examples/Bessel.c +++ /dev/null @@ -1,87 +0,0 @@ -/************************************************************************/ -/* Ein Programm zur Berechnung der Bessel-Koeffizienten Jn -/* Dateiname : Bessel.cpp -/* Autoren : T. Burr, J. Ahrensfeld -/* Datum : 28.10.1999 -/* letzte Änderung : 28.01.2000 -/* Version : 1.0 -/************************************************************************/ - -#include "stdio.h" -#include "math.h" -#include "stdlib.h" - - -#define MAX_SUM 25 -#define VERSION "1.0" - -/************************************************************************/ -/* Funktionsdeklarationen */ -/************************************************************************/ -// Fakultätsberechnung -double fak (int N) -{ - int index; - double erg=1; - - for (index = 1; index <= N; index++) - erg = erg * index; - - return erg; -} - -// Bessel() -// Berechnung von Jn von mfm -double bessel(int n, double mfm) -{ - int m; - double Jn=0; - - for (m=0; m < MAX_SUM; m++) - { - Jn = Jn + (pow(-1.0,m)/(fak(m)*fak(m+n))*pow(mfm/2.0,(2*m+n))); - } - return Jn; -} - - -/************************************************************************/ -/* Das Hauptprogramm -/************************************************************************/ -void main() -{ - - int N, Nmax; - double erg; - float mfm; - - printf("\n\t Besselfunktion Version %s",VERSION); - printf("\n\t ~~~~~~~~~~~~~~~~~~~~~~~~~~\n"); - printf("\n\tCopyright by J. Ahrensfeld & T. Burr\n\n"); - -// --------------------------------------------------------------------------------- - // Benutzereingaben - printf("\nBerechnungen fuer J = 0..."); - if(scanf("%d",&Nmax)==0) - exit (-1); - - printf("Bitte Modulationsindex eingeben : "); - if(scanf("%f",&mfm)==0) - exit(-1); - - printf("\n"); - -// --------------------------------------------------------------------------------- - // Berechnung - for (N=0; N <= Nmax; N++) - { - erg = bessel(N,(double)mfm); - printf("J(%d) = %10.8f\n",N,erg); - } - - printf("FERTIG.\n"); - - } - -/************************************************************************/ - diff --git a/lib/CPUs/MIPS/bsp/examples/Makefile b/lib/CPUs/MIPS/bsp/examples/Makefile deleted file mode 100644 index 71d95b0..0000000 --- a/lib/CPUs/MIPS/bsp/examples/Makefile +++ /dev/null @@ -1,333 +0,0 @@ -ENDIAN='big' - -ifeq ($(ENDIAN), 'big') - ENDIAN_FLAGS=-EB - CFLAGS=$(ENDIAN_FLAGS) -specs=specs/eb/specs -msoft-float -O2 -march=r3000 -I. -Ilibsys -Wl,-M -else - ENDIAN_FLAGS=-EL - CFLAGS=$(ENDIAN_FLAGS) -specs=specs/specs -msoft-float -O2 -march=r3000 -I. -Ilibsys -Wl,-M -endif - -LIBS=-lm -lsys - -AS=mipsel-elf-as -AR=mipsel-elf-ar -CC=mipsel-elf-gcc -LD=mipsel-elf-ld -OBJDUMP=mipsel-elf-objdump -OBJCOPY=mipsel-elf-objcopy -FLASHGEN=flashgen - -PROG = hello.elf testbench.elf test_irq.elf dhry.elf queens.elf stanford.elf paranoia.elf rmd160_test.elf Bessel.elf whet.elf phrasen.elf dttl.elf richards_benchmark.elf test_exception.elf life.elf r3.elf gunzip.elf basic_math.elf jman_patches.elf jman_patchmeshes.elf jman_polys.elf test_hpi.elf test_vga.elf - -all: $(PROG) - -libsys.a: - $(MAKE) -C libsys - -hello.elf: hello.c libsys.a - $(CC) $(CFLAGS) -o $@ -Os hello.c $(LIBS) >$@.map - $(OBJDUMP) -d $@ > $@.dis - $(OBJCOPY) $@ -O binary $@.bin - $(OBJCOPY) -O srec $@ $@.srec - $(FLASHGEN) $@.bin $(ENDIAN_FLAGS) - cat $@.srec | packhex > $@.pack - -testbench.elf: testbench.c libsys.a - $(CC) $(CFLAGS) -O3 -o $@ -DHZ=1000 -DNOSIGNAL -DBATCHMODE -DNOMAIN -Os -g testbench.c paranoia.c delay_mips.c bogomips.c $(LIBS) >$@.map - $(OBJDUMP) -d $@ > $@.dis - $(OBJCOPY) $@ -O binary $@.bin - $(OBJCOPY) -O srec $@ $@.srec - $(FLASHGEN) $@.bin $(ENDIAN_FLAGS) - cat $@.srec | packhex > $@.pack - -test_irq.elf: test_irq.c libsys.a - $(CC) $(CFLAGS) -o $@ test_irq.c $(LIBS) >$@.map - $(OBJDUMP) -d $@ > $@.dis - $(OBJCOPY) $@ -O binary $@.bin - $(OBJCOPY) -O srec $@ $@.srec - $(FLASHGEN) $@.bin $(ENDIAN_FLAGS) - cat $@.srec | packhex > $@.pack - -dhry.elf: dhry_1.c dhry_2.c dhry.h libsys.a - $(CC) $(CFLAGS) -o $@ -DHZ=1000 dhry_1.c dhry_2.c $(LIBS) >$@.map - $(OBJDUMP) -d $@ > $@.dis - $(OBJCOPY) $@ -O binary $@.bin - $(OBJCOPY) -O srec $@ $@.srec - $(FLASHGEN) $@.bin $(ENDIAN_FLAGS) - cat $@.srec | packhex > $@.pack - -queens.elf: queens.c libsys.a - $(CC) $(CFLAGS) -o $@ -DUNIX_Old -DHZ=1000 queens.c $(LIBS) >$@.map - $(OBJDUMP) -d $@ > $@.dis - $(OBJCOPY) $@ -O binary $@.bin - $(OBJCOPY) -O srec $@ $@.srec - $(FLASHGEN) $@.bin $(ENDIAN_FLAGS) - cat $@.srec | packhex > $@.pack - -stanford.elf: stanford.c libsys.a - $(CC) $(CFLAGS) -O3 -o $@ -DHZ=1000 stanford.c $(LIBS) >$@.map - $(OBJDUMP) -d $@ > $@.dis - $(OBJCOPY) $@ -O binary $@.bin - $(OBJCOPY) -O srec $@ $@.srec - $(FLASHGEN) $@.bin $(ENDIAN_FLAGS) - cat $@.srec | packhex > $@.pack - -paranoia.elf: paranoia.c libsys.a - $(CC) $(CFLAGS) -O3 -o $@ -DNOSIGNAL -DBATCHMODE paranoia.c $(LIBS) >$@.map - $(OBJDUMP) -d $@ > $@.dis - $(OBJCOPY) $@ -O binary $@.bin - $(OBJCOPY) -O srec $@ $@.srec - $(FLASHGEN) $@.bin $(ENDIAN_FLAGS) - cat $@.srec | packhex > $@.pack - -rmd160_test.elf: rmd160_test.c rmd160.c rmd160.h libsys.a - $(CC) $(CFLAGS) -O3 -o $@ rmd160_test.c rmd160.c $(LIBS) >$@.map - $(OBJDUMP) -d $@ > $@.dis - $(OBJCOPY) $@ -O binary $@.bin - $(OBJCOPY) -O srec $@ $@.srec - $(FLASHGEN) $@.bin $(ENDIAN_FLAGS) - cat $@.srec | packhex > $@.pack - -hashtest.elf: hashtest.c rmd160.c rmd160.h libsys.a - $(CC) $(CFLAGS) -O3 -o $@ hashtest.c rmd160.c $(LIBS) >$@.map - $(OBJDUMP) -d $@ > $@.dis - $(OBJCOPY) $@ -O binary $@.bin - $(OBJCOPY) -O srec $@ $@.srec - $(FLASHGEN) $@.bin $(ENDIAN_FLAGS) - cat $@.srec | packhex > $@.pack - -Bessel.elf: Bessel.c libsys.a - $(CC) $(CFLAGS) -o $@ Bessel.c $(LIBS) >$@.map - $(OBJDUMP) -d $@ > $@.dis - $(OBJCOPY) $@ -O binary $@.bin - $(OBJCOPY) -O srec $@ $@.srec - $(FLASHGEN) $@.bin $(ENDIAN_FLAGS) - cat $@.srec | packhex > $@.pack - -whet.elf: whet.c libsys.a - $(CC) $(CFLAGS) -o $@ whet.c $(LIBS) >$@.map - $(OBJDUMP) -d $@ > $@.dis - $(OBJCOPY) $@ -O binary $@.bin - $(OBJCOPY) -O srec $@ $@.srec - $(FLASHGEN) $@.bin $(ENDIAN_FLAGS) - cat $@.srec | packhex > $@.pack - -phrasen.elf: phrasen.c libsys.a - $(CC) $(CFLAGS) -o $@ phrasen.c $(LIBS) >$@.map - $(OBJDUMP) -d $@ > $@.dis - $(OBJCOPY) $@ -O binary $@.bin - $(OBJCOPY) -O srec $@ $@.srec - $(FLASHGEN) $@.bin $(ENDIAN_FLAGS) - cat $@.srec | packhex > $@.pack - -dttl.elf: dttl.c random.c libsys.a - $(CC) $(CFLAGS) -o $@ dttl.c random.c $(LIBS) >$@.map - $(OBJDUMP) -d $@ > $@.dis - $(OBJCOPY) $@ -O binary $@.bin - $(OBJCOPY) -O srec $@ $@.srec - $(FLASHGEN) $@.bin $(ENDIAN_FLAGS) - cat $@.srec | packhex > $@.pack - -richards_benchmark.elf: richards_benchmark.c libsys.a - $(CC) $(CFLAGS) -o $@ richards_benchmark.c $(LIBS) >$@.map - $(OBJDUMP) -d $@ > $@.dis - $(OBJCOPY) $@ -O binary $@.bin - $(OBJCOPY) -O srec $@ $@.srec - $(FLASHGEN) $@.bin $(ENDIAN_FLAGS) - cat $@.srec | packhex > $@.pack - -test_exception.elf: test_exception.c libsys.a - $(CC) $(CFLAGS) -o $@ -O1 test_exception.c $(LIBS) >$@.map - $(OBJDUMP) -d $@ > $@.dis - $(OBJCOPY) $@ -O binary $@.bin - $(OBJCOPY) -O srec $@ $@.srec - $(FLASHGEN) $@.bin $(ENDIAN_FLAGS) - cat $@.srec | packhex > $@.pack - -life.elf: life.c libsys.a - $(CC) $(CFLAGS) -o $@ -g life.c $(LIBS) >$@.map - $(OBJDUMP) -d $@ > $@.dis - $(OBJCOPY) $@ -O binary $@.bin - $(OBJCOPY) -O srec $@ $@.srec - $(FLASHGEN) $@.bin $(ENDIAN_FLAGS) - cat $@.srec | packhex > $@.pack - -r3.elf: r3.c libsys.a - $(CC) $(CFLAGS) -O3 -o $@ -DJMIPS_VGA -O2 r3.c $(LIBS) >$@.map - $(OBJDUMP) -d $@ > $@.dis - $(OBJCOPY) $@ -O binary $@.bin - $(OBJCOPY) -O srec $@ $@.srec - $(FLASHGEN) $@.bin $(ENDIAN_FLAGS) - cat $@.srec | packhex > $@.pack - -gunzip.elf: gunzip.c inflate.c crc32.c libsys.a - $(CC) $(CFLAGS) -o $@ -o $@ gunzip.c inflate.c crc32.c $(LIBS) >$@.map - $(OBJDUMP) -d $@ > $@.dis - $(OBJCOPY) $@ -O binary $@.bin - $(OBJCOPY) -O srec $@ $@.srec - $(FLASHGEN) $@.bin $(ENDIAN_FLAGS) - cat $@.srec | packhex > $@.pack - -basic_math.elf: basicmath_small.c rad2deg.c cubic.c isqrt.c libsys.a - $(CC) $(CFLAGS) -o $@ -o $@ basicmath_small.c rad2deg.c cubic.c isqrt.c $(LIBS) >$@.map - $(OBJDUMP) -d $@ > $@.dis - $(OBJCOPY) $@ -O binary $@.bin - $(OBJCOPY) -O srec $@ $@.srec - $(FLASHGEN) $@.bin $(ENDIAN_FLAGS) - cat $@.srec | packhex > $@.pack - -JMAN_SRC= \ - jman/bintree.c \ - jman/camset.c \ - jman/engine.c \ - jman/graph_state.c \ - jman/grid.c \ - jman/imageio.c \ - jman/linklist.c \ - jman/matrix.c \ - jman/object.c \ - jman/render.c \ - jman/ri.c \ - jman/ribgen.c \ - jman/stack.c \ - jman/vars.c - -jman_patches.elf: $(JMAN_SRC) jman/main_patches.c libsys.a - $(CC) $(CFLAGS) -I../ -o $@ -o $@ jman/main_patches.c $(JMAN_SRC) $(LIBS) >$@.map - $(OBJDUMP) -d $@ > $@.dis - $(OBJCOPY) $@ -O binary $@.bin - $(OBJCOPY) -O srec $@ $@.srec - $(FLASHGEN) $@.bin $(ENDIAN_FLAGS) - cat $@.srec | packhex > $@.pack - -jman_patchmeshes.elf: $(JMAN_SRC) jman/main_patchmeshes.c jman/patches2.c libsys.a - $(CC) $(CFLAGS) -I../ -o $@ -o $@ jman/main_patchmeshes.c jman/patches2.c $(JMAN_SRC) $(LIBS) >$@.map - $(OBJDUMP) -d $@ > $@.dis - $(OBJCOPY) $@ -O binary $@.bin - $(OBJCOPY) -O srec $@ $@.srec - $(FLASHGEN) $@.bin $(ENDIAN_FLAGS) - cat $@.srec | packhex > $@.pack - -jman_polys.elf: $(JMAN_SRC) jman/main_polypin.c jman/polys.c libsys.a - $(CC) $(CFLAGS) -I../ -o $@ -o $@ jman/main_polypin.c jman/polys.c $(JMAN_SRC) $(LIBS) >$@.map - $(OBJDUMP) -d $@ > $@.dis - $(OBJCOPY) $@ -O binary $@.bin - $(OBJCOPY) -O srec $@ $@.srec - $(FLASHGEN) $@.bin $(ENDIAN_FLAGS) - cat $@.srec | packhex > $@.pack - -serdump.elf: serdump.c libsys.a - $(CC) $(CFLAGS) -O3 -o $@ -O2 serdump.c $(LIBS) >$@.map - $(OBJDUMP) -d $@ > $@.dis - $(OBJCOPY) $@ -O binary $@.bin - $(OBJCOPY) -O srec $@ $@.srec - $(FLASHGEN) $@.bin $(ENDIAN_FLAGS) - cat $@.srec | packhex > $@.pack - -pppi.elf: pppissue/test1.c pppissue/utils.c pppissue/pppd.h libsys.a - $(CC) $(CFLAGS) -O2 -o $@ -O2 pppissue/test1.c pppissue/utils.c $(LIBS) >$@.map - $(OBJDUMP) -d $@ > $@.dis - $(OBJCOPY) $@ -O binary $@.bin - $(OBJCOPY) -O srec $@ $@.srec - $(FLASHGEN) $@.bin $(ENDIAN_FLAGS) - cat $@.srec | packhex > $@.pack - -lwl.elf: lwl.c libsys.a - $(CC) $(CFLAGS) -O2 -o $@ lwl.c $(LIBS) >$@.map - $(OBJDUMP) -d $@ > $@.dis - $(OBJCOPY) $@ -O binary $@.bin - $(OBJCOPY) -O srec $@ $@.srec - $(FLASHGEN) $@.bin $(ENDIAN_FLAGS) - cat $@.srec | packhex > $@.pack - -ucb.elf: ucb.c libsys.a - $(CC) $(CFLAGS) -O2 -o $@ ucb.c $(LIBS) >$@.map - $(OBJDUMP) -d $@ > $@.dis - $(OBJCOPY) $@ -O binary $@.bin - $(OBJCOPY) -O srec $@ $@.srec - $(FLASHGEN) $@.bin $(ENDIAN_FLAGS) - cat $@.srec | packhex > $@.pack - -test_hpi.elf: hpi.c test_hpi.c cfiflash.c libsys.a - $(CC) $(CFLAGS) -o $@ -g hpi.c test_hpi.c cfiflash.c $(LIBS) >$@.map - $(OBJDUMP) -d $@ > $@.dis - $(OBJCOPY) $@ -O binary $@.bin - $(OBJCOPY) -O srec $@ $@.srec - $(FLASHGEN) $@.bin - cat $@.srec | packhex > $@.pack - -test_vga.elf: test_vga.c libsys.a - $(CC) $(CFLAGS) -o $@ test_vga.c $(LIBS) >$@.map - $(OBJDUMP) -d $@ > $@.dis - $(OBJCOPY) $@ -O binary $@.bin - $(OBJCOPY) -O srec $@ $@.srec - $(FLASHGEN) $@.bin $(ENDIAN_FLAGS) - cat $@.srec | packhex > $@.pack - -barcode.elf: barcode.c libsys.a - $(CC) $(CFLAGS) -o $@ barcode.c $(LIBS) >$@.map - $(OBJDUMP) -d $@ > $@.dis - $(OBJCOPY) $@ -O binary $@.bin - $(OBJCOPY) -O srec $@ $@.srec - $(FLASHGEN) $@.bin $(ENDIAN_FLAGS) - cat $@.srec | packhex > $@.pack - -lua.elf: lua_init.c libsys.a - $(CC) $(CFLAGS) -I./lua-5.1.4/etc -I./lua-5.1.4/src -o $@ lua_init.c $(LIBS) >$@.map - $(OBJDUMP) -d $@ > $@.dis - $(OBJCOPY) $@ -O binary $@.bin - $(OBJCOPY) -O srec $@ $@.srec - $(FLASHGEN) $@.bin $(ENDIAN_FLAGS) - cat $@.srec | packhex > $@.pack - -mandelbrot.elf: mandelbrot.c libsys.a - $(CC) $(CFLAGS) -o $@ mandelbrot.c $(LIBS) >$@.map - $(OBJDUMP) -d $@ > $@.dis - $(OBJCOPY) $@ -O binary $@.bin - $(OBJCOPY) -O srec $@ $@.srec - $(FLASHGEN) $@.bin $(ENDIAN_FLAGS) - cat $@.srec | packhex > $@.pack - -bogomips.elf: bogomips.c delay_mips.c libsys.a - $(CC) $(CFLAGS) -DHZ=1000 -o $@ bogomips.c delay_mips.c $(LIBS) >$@.map - $(OBJDUMP) -d $@ > $@.dis - $(OBJCOPY) $@ -O binary $@.bin - $(OBJCOPY) -O srec $@ $@.srec - $(FLASHGEN) $@.bin $(ENDIAN_FLAGS) - cat $@.srec | packhex > $@.pack - -test_asm.elf: test_asm.S libsys.a - $(CC) $(CFLAGS) -DHZ=1000 -o $@ test_asm.S $(LIBS) >$@.map - $(OBJDUMP) -d $@ > $@.dis - $(OBJCOPY) $@ -O binary $@.bin - $(OBJCOPY) -O srec $@ $@.srec - $(FLASHGEN) $@.bin $(ENDIAN_FLAGS) - cat $@.srec | packhex > $@.pack - -test_ac97.elf: test_ac97.c libsys.a - $(CC) $(CFLAGS) -o $@ test_ac97.c $(LIBS) >$@.map - $(OBJDUMP) -d $@ > $@.dis - $(OBJCOPY) $@ -O binary $@.bin - $(OBJCOPY) -O srec $@ $@.srec - $(FLASHGEN) $@.bin $(ENDIAN_FLAGS) - cat $@.srec | packhex > $@.pack - -test_dcache.elf: test_dcache.c libsys.a - $(CC) $(CFLAGS) -O0 -o $@ test_dcache.c $(LIBS) >$@.map - $(OBJDUMP) -d $@ > $@.dis - $(OBJCOPY) $@ -O binary $@.bin - $(OBJCOPY) -O srec $@ $@.srec - $(FLASHGEN) $@.bin $(ENDIAN_FLAGS) - cat $@.srec | packhex > $@.pack - -aes256_1.elf: aes256_1.c aes256.c aes256.h libsys.a - $(CC) $(CFLAGS) -O3 -o $@ aes256_1.c aes256.c $(LIBS) >$@.map - $(OBJDUMP) -d $@ > $@.dis - $(OBJCOPY) $@ -O binary $@.bin - $(OBJCOPY) -O srec $@ $@.srec - $(FLASHGEN) $@.bin $(ENDIAN_FLAGS) - cat $@.srec | packhex > $@.pack - -clean: - rm -rf *.a *.o *.bin *.map *.dis *.srec *.pack *.elf $(PROG) > /dev/null diff --git a/lib/CPUs/MIPS/bsp/examples/aes256.c b/lib/CPUs/MIPS/bsp/examples/aes256.c deleted file mode 100644 index 97a5136..0000000 --- a/lib/CPUs/MIPS/bsp/examples/aes256.c +++ /dev/null @@ -1,359 +0,0 @@ -/* -* Byte-oriented AES-256 implementation. -* All lookup tables replaced with 'on the fly' calculations. -* -* Copyright (c) 2007-2009 Ilya O. Levin, http://www.literatecode.com -* Other contributors: Hal Finney -* -* Permission to use, copy, modify, and distribute this software for any -* purpose with or without fee is hereby granted, provided that the above -* copyright notice and this permission notice appear in all copies. -* -* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -*/ -#include "aes256.h" - -#define F(x) (((x)<<1) ^ ((((x)>>7) & 1) * 0x1b)) -#define FD(x) (((x) >> 1) ^ (((x) & 1) ? 0x8d : 0)) - -#define BACK_TO_TABLES -#ifdef BACK_TO_TABLES - -const uint8_t sbox[256] = { - 0x63, 0x7c, 0x77, 0x7b, 0xf2, 0x6b, 0x6f, 0xc5, - 0x30, 0x01, 0x67, 0x2b, 0xfe, 0xd7, 0xab, 0x76, - 0xca, 0x82, 0xc9, 0x7d, 0xfa, 0x59, 0x47, 0xf0, - 0xad, 0xd4, 0xa2, 0xaf, 0x9c, 0xa4, 0x72, 0xc0, - 0xb7, 0xfd, 0x93, 0x26, 0x36, 0x3f, 0xf7, 0xcc, - 0x34, 0xa5, 0xe5, 0xf1, 0x71, 0xd8, 0x31, 0x15, - 0x04, 0xc7, 0x23, 0xc3, 0x18, 0x96, 0x05, 0x9a, - 0x07, 0x12, 0x80, 0xe2, 0xeb, 0x27, 0xb2, 0x75, - 0x09, 0x83, 0x2c, 0x1a, 0x1b, 0x6e, 0x5a, 0xa0, - 0x52, 0x3b, 0xd6, 0xb3, 0x29, 0xe3, 0x2f, 0x84, - 0x53, 0xd1, 0x00, 0xed, 0x20, 0xfc, 0xb1, 0x5b, - 0x6a, 0xcb, 0xbe, 0x39, 0x4a, 0x4c, 0x58, 0xcf, - 0xd0, 0xef, 0xaa, 0xfb, 0x43, 0x4d, 0x33, 0x85, - 0x45, 0xf9, 0x02, 0x7f, 0x50, 0x3c, 0x9f, 0xa8, - 0x51, 0xa3, 0x40, 0x8f, 0x92, 0x9d, 0x38, 0xf5, - 0xbc, 0xb6, 0xda, 0x21, 0x10, 0xff, 0xf3, 0xd2, - 0xcd, 0x0c, 0x13, 0xec, 0x5f, 0x97, 0x44, 0x17, - 0xc4, 0xa7, 0x7e, 0x3d, 0x64, 0x5d, 0x19, 0x73, - 0x60, 0x81, 0x4f, 0xdc, 0x22, 0x2a, 0x90, 0x88, - 0x46, 0xee, 0xb8, 0x14, 0xde, 0x5e, 0x0b, 0xdb, - 0xe0, 0x32, 0x3a, 0x0a, 0x49, 0x06, 0x24, 0x5c, - 0xc2, 0xd3, 0xac, 0x62, 0x91, 0x95, 0xe4, 0x79, - 0xe7, 0xc8, 0x37, 0x6d, 0x8d, 0xd5, 0x4e, 0xa9, - 0x6c, 0x56, 0xf4, 0xea, 0x65, 0x7a, 0xae, 0x08, - 0xba, 0x78, 0x25, 0x2e, 0x1c, 0xa6, 0xb4, 0xc6, - 0xe8, 0xdd, 0x74, 0x1f, 0x4b, 0xbd, 0x8b, 0x8a, - 0x70, 0x3e, 0xb5, 0x66, 0x48, 0x03, 0xf6, 0x0e, - 0x61, 0x35, 0x57, 0xb9, 0x86, 0xc1, 0x1d, 0x9e, - 0xe1, 0xf8, 0x98, 0x11, 0x69, 0xd9, 0x8e, 0x94, - 0x9b, 0x1e, 0x87, 0xe9, 0xce, 0x55, 0x28, 0xdf, - 0x8c, 0xa1, 0x89, 0x0d, 0xbf, 0xe6, 0x42, 0x68, - 0x41, 0x99, 0x2d, 0x0f, 0xb0, 0x54, 0xbb, 0x16 -}; -const uint8_t sboxinv[256] = { - 0x52, 0x09, 0x6a, 0xd5, 0x30, 0x36, 0xa5, 0x38, - 0xbf, 0x40, 0xa3, 0x9e, 0x81, 0xf3, 0xd7, 0xfb, - 0x7c, 0xe3, 0x39, 0x82, 0x9b, 0x2f, 0xff, 0x87, - 0x34, 0x8e, 0x43, 0x44, 0xc4, 0xde, 0xe9, 0xcb, - 0x54, 0x7b, 0x94, 0x32, 0xa6, 0xc2, 0x23, 0x3d, - 0xee, 0x4c, 0x95, 0x0b, 0x42, 0xfa, 0xc3, 0x4e, - 0x08, 0x2e, 0xa1, 0x66, 0x28, 0xd9, 0x24, 0xb2, - 0x76, 0x5b, 0xa2, 0x49, 0x6d, 0x8b, 0xd1, 0x25, - 0x72, 0xf8, 0xf6, 0x64, 0x86, 0x68, 0x98, 0x16, - 0xd4, 0xa4, 0x5c, 0xcc, 0x5d, 0x65, 0xb6, 0x92, - 0x6c, 0x70, 0x48, 0x50, 0xfd, 0xed, 0xb9, 0xda, - 0x5e, 0x15, 0x46, 0x57, 0xa7, 0x8d, 0x9d, 0x84, - 0x90, 0xd8, 0xab, 0x00, 0x8c, 0xbc, 0xd3, 0x0a, - 0xf7, 0xe4, 0x58, 0x05, 0xb8, 0xb3, 0x45, 0x06, - 0xd0, 0x2c, 0x1e, 0x8f, 0xca, 0x3f, 0x0f, 0x02, - 0xc1, 0xaf, 0xbd, 0x03, 0x01, 0x13, 0x8a, 0x6b, - 0x3a, 0x91, 0x11, 0x41, 0x4f, 0x67, 0xdc, 0xea, - 0x97, 0xf2, 0xcf, 0xce, 0xf0, 0xb4, 0xe6, 0x73, - 0x96, 0xac, 0x74, 0x22, 0xe7, 0xad, 0x35, 0x85, - 0xe2, 0xf9, 0x37, 0xe8, 0x1c, 0x75, 0xdf, 0x6e, - 0x47, 0xf1, 0x1a, 0x71, 0x1d, 0x29, 0xc5, 0x89, - 0x6f, 0xb7, 0x62, 0x0e, 0xaa, 0x18, 0xbe, 0x1b, - 0xfc, 0x56, 0x3e, 0x4b, 0xc6, 0xd2, 0x79, 0x20, - 0x9a, 0xdb, 0xc0, 0xfe, 0x78, 0xcd, 0x5a, 0xf4, - 0x1f, 0xdd, 0xa8, 0x33, 0x88, 0x07, 0xc7, 0x31, - 0xb1, 0x12, 0x10, 0x59, 0x27, 0x80, 0xec, 0x5f, - 0x60, 0x51, 0x7f, 0xa9, 0x19, 0xb5, 0x4a, 0x0d, - 0x2d, 0xe5, 0x7a, 0x9f, 0x93, 0xc9, 0x9c, 0xef, - 0xa0, 0xe0, 0x3b, 0x4d, 0xae, 0x2a, 0xf5, 0xb0, - 0xc8, 0xeb, 0xbb, 0x3c, 0x83, 0x53, 0x99, 0x61, - 0x17, 0x2b, 0x04, 0x7e, 0xba, 0x77, 0xd6, 0x26, - 0xe1, 0x69, 0x14, 0x63, 0x55, 0x21, 0x0c, 0x7d -}; - -#define rj_sbox(x) sbox[(x)] -#define rj_sbox_inv(x) sboxinv[(x)] - -#else /* tableless subroutines */ - -/* -------------------------------------------------------------------------- */ -uint8_t gf_alog(uint8_t x) // calculate anti-logarithm gen 3 -{ - uint8_t atb = 1, z; - - while (x--) {z = atb; atb <<= 1; if (z & 0x80) atb^= 0x1b; atb ^= z;} - - return atb; -} /* gf_alog */ - -/* -------------------------------------------------------------------------- */ -uint8_t gf_log(uint8_t x) // calculate logarithm gen 3 -{ - uint8_t atb = 1, i = 0, z; - - do { - if (atb == x) break; - z = atb; atb <<= 1; if (z & 0x80) atb^= 0x1b; atb ^= z; - } while (++i > 0); - - return i; -} /* gf_log */ - - -/* -------------------------------------------------------------------------- */ -uint8_t gf_mulinv(uint8_t x) // calculate multiplicative inverse -{ - return (x) ? gf_alog(255 - gf_log(x)) : 0; -} /* gf_mulinv */ - -/* -------------------------------------------------------------------------- */ -uint8_t rj_sbox(uint8_t x) -{ - uint8_t y, sb; - - sb = y = gf_mulinv(x); - y = (y<<1)|(y>>7); sb ^= y; y = (y<<1)|(y>>7); sb ^= y; - y = (y<<1)|(y>>7); sb ^= y; y = (y<<1)|(y>>7); sb ^= y; - - return (sb ^ 0x63); -} /* rj_sbox */ - -/* -------------------------------------------------------------------------- */ -uint8_t rj_sbox_inv(uint8_t x) -{ - uint8_t y, sb; - - y = x ^ 0x63; - sb = y = (y<<1)|(y>>7); - y = (y<<2)|(y>>6); sb ^= y; y = (y<<3)|(y>>5); sb ^= y; - - return gf_mulinv(sb); -} /* rj_sbox_inv */ - -#endif - -/* -------------------------------------------------------------------------- */ -uint8_t rj_xtime(uint8_t x) -{ - return (x & 0x80) ? ((x << 1) ^ 0x1b) : (x << 1); -} /* rj_xtime */ - -/* -------------------------------------------------------------------------- */ -void aes_subBytes(uint8_t *buf) -{ - register uint8_t i = 16; - - while (i--) buf[i] = rj_sbox(buf[i]); -} /* aes_subBytes */ - -/* -------------------------------------------------------------------------- */ -void aes_subBytes_inv(uint8_t *buf) -{ - register uint8_t i = 16; - - while (i--) buf[i] = rj_sbox_inv(buf[i]); -} /* aes_subBytes_inv */ - -/* -------------------------------------------------------------------------- */ -void aes_addRoundKey(uint8_t *buf, uint8_t *key) -{ - register uint8_t i = 16; - - while (i--) buf[i] ^= key[i]; -} /* aes_addRoundKey */ - -/* -------------------------------------------------------------------------- */ -void aes_addRoundKey_cpy(uint8_t *buf, uint8_t *key, uint8_t *cpk) -{ - register uint8_t i = 16; - - while (i--) buf[i] ^= (cpk[i] = key[i]), cpk[16+i] = key[16 + i]; -} /* aes_addRoundKey_cpy */ - - -/* -------------------------------------------------------------------------- */ -void aes_shiftRows(uint8_t *buf) -{ - register uint8_t i, j; /* to make it potentially parallelable :) */ - - i = buf[1]; buf[1] = buf[5]; buf[5] = buf[9]; buf[9] = buf[13]; buf[13] = i; - i = buf[10]; buf[10] = buf[2]; buf[2] = i; - j = buf[3]; buf[3] = buf[15]; buf[15] = buf[11]; buf[11] = buf[7]; buf[7] = j; - j = buf[14]; buf[14] = buf[6]; buf[6] = j; - -} /* aes_shiftRows */ - -/* -------------------------------------------------------------------------- */ -void aes_shiftRows_inv(uint8_t *buf) -{ - register uint8_t i, j; /* same as above :) */ - - i = buf[1]; buf[1] = buf[13]; buf[13] = buf[9]; buf[9] = buf[5]; buf[5] = i; - i = buf[2]; buf[2] = buf[10]; buf[10] = i; - j = buf[3]; buf[3] = buf[7]; buf[7] = buf[11]; buf[11] = buf[15]; buf[15] = j; - j = buf[6]; buf[6] = buf[14]; buf[14] = j; - -} /* aes_shiftRows_inv */ - -/* -------------------------------------------------------------------------- */ -void aes_mixColumns(uint8_t *buf) -{ - register uint8_t i, a, b, c, d, e; - - for (i = 0; i < 16; i += 4) - { - a = buf[i]; b = buf[i + 1]; c = buf[i + 2]; d = buf[i + 3]; - e = a ^ b ^ c ^ d; - buf[i] ^= e ^ rj_xtime(a^b); buf[i+1] ^= e ^ rj_xtime(b^c); - buf[i+2] ^= e ^ rj_xtime(c^d); buf[i+3] ^= e ^ rj_xtime(d^a); - } -} /* aes_mixColumns */ - -/* -------------------------------------------------------------------------- */ -void aes_mixColumns_inv(uint8_t *buf) -{ - register uint8_t i, a, b, c, d, e, x, y, z; - - for (i = 0; i < 16; i += 4) - { - a = buf[i]; b = buf[i + 1]; c = buf[i + 2]; d = buf[i + 3]; - e = a ^ b ^ c ^ d; - z = rj_xtime(e); - x = e ^ rj_xtime(rj_xtime(z^a^c)); y = e ^ rj_xtime(rj_xtime(z^b^d)); - buf[i] ^= x ^ rj_xtime(a^b); buf[i+1] ^= y ^ rj_xtime(b^c); - buf[i+2] ^= x ^ rj_xtime(c^d); buf[i+3] ^= y ^ rj_xtime(d^a); - } -} /* aes_mixColumns_inv */ - -/* -------------------------------------------------------------------------- */ -void aes_expandEncKey(uint8_t *k, uint8_t *rc) -{ - register uint8_t i; - - k[0] ^= rj_sbox(k[29]) ^ (*rc); - k[1] ^= rj_sbox(k[30]); - k[2] ^= rj_sbox(k[31]); - k[3] ^= rj_sbox(k[28]); - *rc = F( *rc); - - for(i = 4; i < 16; i += 4) k[i] ^= k[i-4], k[i+1] ^= k[i-3], - k[i+2] ^= k[i-2], k[i+3] ^= k[i-1]; - k[16] ^= rj_sbox(k[12]); - k[17] ^= rj_sbox(k[13]); - k[18] ^= rj_sbox(k[14]); - k[19] ^= rj_sbox(k[15]); - - for(i = 20; i < 32; i += 4) k[i] ^= k[i-4], k[i+1] ^= k[i-3], - k[i+2] ^= k[i-2], k[i+3] ^= k[i-1]; - -} /* aes_expandEncKey */ - -/* -------------------------------------------------------------------------- */ -void aes_expandDecKey(uint8_t *k, uint8_t *rc) -{ - uint8_t i; - - for(i = 28; i > 16; i -= 4) k[i+0] ^= k[i-4], k[i+1] ^= k[i-3], - k[i+2] ^= k[i-2], k[i+3] ^= k[i-1]; - - k[16] ^= rj_sbox(k[12]); - k[17] ^= rj_sbox(k[13]); - k[18] ^= rj_sbox(k[14]); - k[19] ^= rj_sbox(k[15]); - - for(i = 12; i > 0; i -= 4) k[i+0] ^= k[i-4], k[i+1] ^= k[i-3], - k[i+2] ^= k[i-2], k[i+3] ^= k[i-1]; - - *rc = FD(*rc); - k[0] ^= rj_sbox(k[29]) ^ (*rc); - k[1] ^= rj_sbox(k[30]); - k[2] ^= rj_sbox(k[31]); - k[3] ^= rj_sbox(k[28]); -} /* aes_expandDecKey */ - - -/* -------------------------------------------------------------------------- */ -void aes256_init(aes256_context *ctx, uint8_t *k) -{ - uint8_t rcon = 1; - register uint8_t i; - - for (i = 0; i < sizeof(ctx->key); i++) ctx->enckey[i] = ctx->deckey[i] = k[i]; - for (i = 8;--i;) aes_expandEncKey(ctx->deckey, &rcon); -} /* aes256_init */ - -/* -------------------------------------------------------------------------- */ -void aes256_done(aes256_context *ctx) -{ - register uint8_t i; - - for (i = 0; i < sizeof(ctx->key); i++) - ctx->key[i] = ctx->enckey[i] = ctx->deckey[i] = 0; -} /* aes256_done */ - -/* -------------------------------------------------------------------------- */ -void aes256_encrypt_ecb(aes256_context *ctx, uint8_t *buf) -{ - uint8_t i, rcon; - - aes_addRoundKey_cpy(buf, ctx->enckey, ctx->key); - for(i = 1, rcon = 1; i < 14; ++i) - { - aes_subBytes(buf); - aes_shiftRows(buf); - aes_mixColumns(buf); - if( i & 1 ) aes_addRoundKey( buf, &ctx->key[16]); - else aes_expandEncKey(ctx->key, &rcon), aes_addRoundKey(buf, ctx->key); - } - aes_subBytes(buf); - aes_shiftRows(buf); - aes_expandEncKey(ctx->key, &rcon); - aes_addRoundKey(buf, ctx->key); -} /* aes256_encrypt */ - -/* -------------------------------------------------------------------------- */ -void aes256_decrypt_ecb(aes256_context *ctx, uint8_t *buf) -{ - uint8_t i, rcon; - - aes_addRoundKey_cpy(buf, ctx->deckey, ctx->key); - aes_shiftRows_inv(buf); - aes_subBytes_inv(buf); - - for (i = 14, rcon = 0x80; --i;) - { - if( ( i & 1 ) ) - { - aes_expandDecKey(ctx->key, &rcon); - aes_addRoundKey(buf, &ctx->key[16]); - } - else aes_addRoundKey(buf, ctx->key); - aes_mixColumns_inv(buf); - aes_shiftRows_inv(buf); - aes_subBytes_inv(buf); - } - aes_addRoundKey( buf, ctx->key); -} /* aes256_decrypt */ diff --git a/lib/CPUs/MIPS/bsp/examples/aes256.h b/lib/CPUs/MIPS/bsp/examples/aes256.h deleted file mode 100644 index c5a22ba..0000000 --- a/lib/CPUs/MIPS/bsp/examples/aes256.h +++ /dev/null @@ -1,42 +0,0 @@ -/* -* Byte-oriented AES-256 implementation. -* All lookup tables replaced with 'on the fly' calculations. -* -* Copyright (c) 2007-2009 Ilya O. Levin, http://www.literatecode.com -* Other contributors: Hal Finney -* -* Permission to use, copy, modify, and distribute this software for any -* purpose with or without fee is hereby granted, provided that the above -* copyright notice and this permission notice appear in all copies. -* -* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -*/ -#ifndef uint8_t -#define uint8_t unsigned char -#endif - -#ifdef __cplusplus -extern "C" { -#endif - - typedef struct { - uint8_t key[32]; - uint8_t enckey[32]; - uint8_t deckey[32]; - } aes256_context; - - - void aes256_init(aes256_context *, uint8_t * /* key */); - void aes256_done(aes256_context *); - void aes256_encrypt_ecb(aes256_context *, uint8_t * /* plaintext */); - void aes256_decrypt_ecb(aes256_context *, uint8_t * /* cipertext */); - -#ifdef __cplusplus -} -#endif diff --git a/lib/CPUs/MIPS/bsp/examples/aes256_1.c b/lib/CPUs/MIPS/bsp/examples/aes256_1.c deleted file mode 100644 index 8a987b8..0000000 --- a/lib/CPUs/MIPS/bsp/examples/aes256_1.c +++ /dev/null @@ -1,76 +0,0 @@ -/* -* Byte-oriented AES-256 implementation. -* All lookup tables replaced with 'on the fly' calculations. -* -* Copyright (c) 2007 Ilya O. Levin, http://www.literatecode.com -* -* Permission to use, copy, modify, and distribute this software for any -* purpose with or without fee is hereby granted, provided that the above -* copyright notice and this permission notice appear in all copies. -* -* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -*/ -#include -#include -#include -#include -#include -#include "aes256.h" - -#ifndef NUM_BLOCKS -#define NUM_BLOCKS 10000 -#endif - -#define DUMP(s, i, buf, sz) {printf(s); \ - for (i = 0; i < (sz);i++) \ - printf("%02x ", buf[i]); \ - printf("\n");} - - -int main (int argc, char *argv[]) -{ - aes256_context ctx; - uint8_t key[32]; - uint8_t buf[16], i; - long start, end, j; - - /* put a test vector */ - for (i = 0; i < sizeof(buf);i++) buf[i] = i * 16 + i; - for (i = 0; i < sizeof(key);i++) key[i] = i; - - DUMP("txt: ", i, buf, sizeof(buf)); - DUMP("key: ", i, key, sizeof(key)); - printf("---\n"); - - aes256_init(&ctx, key); - start = clock(); - for (j=0; j < NUM_BLOCKS; j++) - { - aes256_encrypt_ecb(&ctx, buf); - } - end = clock(); - DUMP("enc: ", i, buf, sizeof(buf)); - - printf("Speed %f blocks/s\n", (float)j/((float)(end-start)/CLOCKS_PER_SEC)); - - aes256_init(&ctx, key); - start = clock(); - for (j=0; j < NUM_BLOCKS; j++) - { - aes256_decrypt_ecb(&ctx, buf); - } - end = clock(); - DUMP("dec: ", i, buf, sizeof(buf)); - - printf("Speed %f blocks/s\n", (float)j/((float)(end-start)/CLOCKS_PER_SEC)); - - aes256_done(&ctx); - - return 0; -} /* main */ diff --git a/lib/CPUs/MIPS/bsp/examples/barcode.c b/lib/CPUs/MIPS/bsp/examples/barcode.c deleted file mode 100644 index e1dc1bc..0000000 --- a/lib/CPUs/MIPS/bsp/examples/barcode.c +++ /dev/null @@ -1,358 +0,0 @@ -#include -#include -#include -#include -#include -#include -#include - -#define CPU_FREQ_HZ 100000000 -#include "libsys.h" -#include "irq.h" - -UINT32 buffer[16384]; - -#define T_SAMPLE 5000 -#define TIMEOUT 1000 - -typedef struct _bar_t -{ - UINT32 T; - UINT32 black; -} bar_t; - -enum -{ - state_idle = 0, - state_sample, - state_finish -}; - -typedef struct _sbar_cand_t -{ - UINT32 T; - UINT32 is_primitive; -} bar_cand_t; - -bar_t bars[1024]; - -void bsort(float *pData, UINT32 len) -{ - float t; - int i, j; - - for(i=len-1; i>=0; i--) - { - for(j=1; j pData[j]) - { - t = pData[j-1]; - pData[j-1] = pData[j]; - pData[j] = t; - } - } - } -} - -typedef struct _smedian_t -{ - UINT32 N; - UINT32 is_dirty; - float *pBuf, *pSorted; - UINT32 w; - float median; -} median_t; - -void Median_init(median_t *pObj, UINT32 N, float init_val) -{ - int i; - pObj->pBuf = (float*)malloc(N*sizeof(float)); - pObj->pSorted = (float*)malloc(N*sizeof(float)); - for (i=0; i < N; i++) - pObj->pBuf[0] = init_val; - pObj->median = init_val; - pObj->is_dirty = 0; - pObj->w = 0; - pObj->N = N; -} - -void Median_free(median_t *pObj) -{ - if (pObj->pBuf) - free(pObj->pBuf); - - if (pObj->pSorted) - free(pObj->pSorted); - - pObj->pBuf = NULL; - pObj->pSorted = NULL; - -} - -void Median_value_add(median_t *pObj, float value) -{ - pObj->is_dirty = 1; - pObj->pBuf[pObj->w++] = value; - - if (pObj->w == pObj->N) - pObj->w = 0; - -} - -float Median_get(median_t *pObj) -{ - if (!pObj->is_dirty) - return pObj->median; - - memcpy(pObj->pSorted, pObj->pBuf, pObj->N*sizeof(float)); - - bsort(pObj->pSorted, pObj->N); - - if (pObj->N&1) - { - pObj->median = pObj->pSorted[(pObj->N-1)/2]; - } - else - { - pObj->median = 0.5f*(pObj->pSorted[pObj->N/2] + pObj->pSorted[pObj->N/2+1]); - } - - pObj->is_dirty = 0; - - return pObj->median; -} - -// ------------------------------------------------------------- -UINT32 detect_module(UINT32 T, UINT32 T0) -{ - UINT32 m, best_M; - float err, kc, best_err; - - best_err = 4.f; - best_M = 0; - - for (m=1; m < 5; m++) - { - kc = (float)T/(m*T0); - err = fabs(kc - 1); - - if (err < best_err) - { - best_M = m; - best_err = err; - } - } - - return best_M; -} - -void handler7(void) -{ - UINT32 volatile *pTim_ctrl = (UINT32*)SYS_ITIM_CTRL; - UINT32 volatile *pTim_stat = (UINT32*)SYS_ITIM_STAT; - UINT32 volatile *pPS20_stat = (UINT32*)SYS_PS2_0_STAT; - UINT32 volatile *pPS21_stat = (UINT32*)SYS_PS2_1_STAT; - static UINT32 state, bar_count; - static UINT32 timeout_count, timeout_reload; - static UINT32 white, pin_last, skip, start; - static UINT32 module_cnt_w, module_cnt_b, Tmod0_w, Tmod0_b, M, T0; - float ratio, error, kc; - UINT32 i; - static median_t med_b, med_w; - static bar_cand_t bc_b, bc_w; - static median_t speed_b, speed_w; - - if (*pTim_stat & 1) - { - *pTim_stat = 1; - white = ((*pPS20_stat & SYS_PS2_BIT_PIN_DATA) == 0); - - switch (state) - { - case state_idle: - timeout_reload = TIMEOUT; - if (white != pin_last) - { - if (white) - break; - - state = state_sample; - module_cnt_b = 0; - module_cnt_w = 0; - Tmod0_w = 0xFFFFFFFF; - Tmod0_b = 0xFFFFFFFF; - bar_count = 0; - Median_init(&med_b, 3, 0); - Median_init(&med_w, 3, 0); - Median_init(&speed_b, 3, 1); - Median_init(&speed_w, 3, 1); - } - break; - - case state_sample: - if (!timeout_count) - { - state = state_finish; - break; - } - - if (white) - { - module_cnt_w++; - } - else - { - module_cnt_b++; - } - if (white != pin_last) - { - if (pin_last) - { - if (bar_count < 10) - { - if (1.5*module_cnt_w < Tmod0_w) - { - Tmod0_w = module_cnt_w; - } - } - Median_value_add(&med_w, Tmod0_w); - - timeout_reload = 10*Tmod0_w; - bars[bar_count].T = module_cnt_w; - bars[bar_count].black = 0; - module_cnt_w = 0; - - } - else - { - if (bar_count < 10) - { - if (1.5*module_cnt_b < Tmod0_b) - { - Tmod0_b = module_cnt_b; - } - } - Median_value_add(&med_b, Tmod0_b); - - timeout_reload = 10*Tmod0_b; - bars[bar_count].T = module_cnt_b; - bars[bar_count].black = 1; - module_cnt_b = 0; - } - bar_count++; - - } - break; - - case state_finish: - printf("------------------------------------------------\n"); - printf(" Black White \n"); - skip = 0; - start = 1; - Tmod0_w = Median_get(&med_w); - Tmod0_b = Median_get(&med_b); - for (i=0; i < bar_count; i++) - { - if (bars[i].black) - { - T0 = Median_get(&med_b); - ratio = (float)bars[i].T/T0; - if (start) - { - if (ratio > 4) - { - skip = 1; - continue; - } - } - start = 0; - skip = 0; - M = detect_module(bars[i].T, T0); - kc = (float)bars[i].T/(M*T0); - error = kc - 1; - -// printf("M=%d, R=%2.2f, E=%+2.2f [%04d]", M, ratio, error, T0); -// if (M == 1) - Median_value_add(&med_b, (UINT32)(T0*kc)); - Median_value_add(&speed_b, (float)bars[i].T/(M*Tmod0_b)); - - printf("%06d %2.6f ", bars[i].T, Median_get(&speed_b)); - - } - else - { - if (skip) - continue; - - T0 = Median_get(&med_w); - ratio = (float)bars[i].T/T0; - if (ratio > 9) - { - start = 1; -// printf("\n"); -// printf("------------------------------------------------\n"); -// printf(" Black White \n"); - continue; - } - - - M = detect_module(bars[i].T, T0); - kc = (float)bars[i].T/(M*T0); - error = kc - 1; - -// printf(" M=%d, R=%2.2f, E=%+2.2f [%04d]", M, ratio, error, T0); -// if (M == 1) - Median_value_add(&med_w, (UINT32)(T0*kc)); - Median_value_add(&speed_w, (float)bars[i].T/(M*Tmod0_w)); - - printf("%06d %2.6f ", bars[i].T, Median_get(&speed_w)); - printf("\n"); - } - } - Median_free(&med_b); - Median_free(&med_w); - Median_free(&speed_b); - Median_free(&speed_w); - if (bar_count) - printf("\n"); - - state = state_idle; - break; - - } - if (white != pin_last) - timeout_count = timeout_reload; - - pin_last = white; - if (timeout_count) - timeout_count--; - - } -} - -int main(void) -{ - - int i; - UINT32 volatile *pTim_ctrl = (UINT32*)SYS_ITIM_CTRL; - UINT32 volatile *pTim_stat = (UINT32*)SYS_ITIM_STAT; - UINT32 volatile *pTim0_cnt = (UINT32*)SYS_ITIM0_CNT; - UINT32 volatile *pTim0_cmp = (UINT32*)SYS_ITIM0_CMP; - - *pTim0_cnt = 0; - *pTim0_cmp = (UINT32)T_SAMPLE; - *pTim_stat = 1; - *pTim_ctrl = 3; - - interrupt_register(7, (void*)handler7); - - printf("Jenners BarCoder\n"); - - interrupt_enable(7); - - while(1) - { - } - return 0; -} diff --git a/lib/CPUs/MIPS/bsp/examples/barcode.new.c b/lib/CPUs/MIPS/bsp/examples/barcode.new.c deleted file mode 100644 index 06f1152..0000000 --- a/lib/CPUs/MIPS/bsp/examples/barcode.new.c +++ /dev/null @@ -1,322 +0,0 @@ -#include -#include -#include -#include -#include -#include -#include - -#define CPU_FREQ_HZ 100000000 -#include "libsys.h" -#include "irq.h" - -UINT32 buffer[16384]; - -#define T_SAMPLE 5000 -#define TIMEOUT 1000 - -typedef struct _bar_t -{ - UINT32 T; - UINT32 black; -} bar_t; - -enum -{ - state_idle = 0, - state_sample, - state_finish -}; - -bar_t bars[1024]; - -void bsort(float *pData, UINT32 len) -{ - float t; - int i, j; - - for(i=len-1; i>=0; i--) - { - for(j=1; j pData[j]) - { - t = pData[j-1]; - pData[j-1] = pData[j]; - pData[j] = t; - } - } - } -} - -typedef struct _smedian_t -{ - UINT32 N; - UINT32 is_dirty; - float *pBuf, *pSorted; - UINT32 w; - float median; -} median_t; - -void Median_init(median_t *pObj, UINT32 N, float init_val) -{ - int i; - pObj->pBuf = (float*)malloc(N*sizeof(float)); - pObj->pSorted = (float*)malloc(N*sizeof(float)); - for (i=0; i < N; i++) - pObj->pBuf[0] = init_val; - pObj->median = init_val; - pObj->is_dirty = 0; - pObj->w = 0; - pObj->N = N; -} - -void Median_free(median_t *pObj) -{ - if (pObj->pBuf) - free(pObj->pBuf); - - if (pObj->pSorted) - free(pObj->pSorted); - - pObj->pBuf = NULL; - pObj->pSorted = NULL; - -} - -void Median_value_add(median_t *pObj, float value) -{ - pObj->is_dirty = 1; - pObj->pBuf[pObj->w++] = value; - - if (pObj->w == pObj->N) - pObj->w = 0; - -} - -float Median_get(median_t *pObj) -{ - if (!pObj->is_dirty) - return pObj->median; - - memcpy(pObj->pSorted, pObj->pBuf, pObj->N*sizeof(float)); - - bsort(pObj->pSorted, pObj->N); - - if (pObj->N&1) - { - pObj->median = pObj->pSorted[(pObj->N-1)/2]; - } - else - { - pObj->median = 0.5f*(pObj->pSorted[pObj->N/2] + pObj->pSorted[pObj->N/2+1]); - } - - pObj->is_dirty = 0; - - return pObj->median; -} - -// ------------------------------------------------------------- -UINT32 detect_module(UINT32 T, UINT32 *pBC) -{ - UINT32 m, best_M; - float err, kc, best_err; - - best_err = 4.f; - best_M = 0; - - for (m=0; m < 4; m++) - { - kc = (float)T/pBC[m]; - err = fabs(kc - 1); - - if (err < best_err) - { - best_M = m+1; - best_err = err; - } - } - - return best_M; -} - -void handler7(void) -{ - UINT32 volatile *pTim_ctrl = (UINT32*)SYS_ITIM_CTRL; - UINT32 volatile *pTim_stat = (UINT32*)SYS_ITIM_STAT; - UINT32 volatile *pPS20_stat = (UINT32*)SYS_PS2_0_STAT; - UINT32 volatile *pPS21_stat = (UINT32*)SYS_PS2_1_STAT; - static UINT32 state, bar_count; - static UINT32 timeout_count, timeout_reload; - static UINT32 white, pin_last, skip, start; - static UINT32 module_cnt_w, module_cnt_b, Tmod0_w, Tmod0_b, M, T0; - float ratio, error, kc; - UINT32 i, j; - static median_t med_b, med_w; - static UINT32 bc_b[4], bc_w[4]; - - if (*pTim_stat & 1) - { - *pTim_stat = 1; - white = ((*pPS20_stat & SYS_PS2_BIT_PIN_DATA) == 0); - - switch (state) - { - case state_idle: - timeout_reload = TIMEOUT; - if (white != pin_last) - { - if (white) - break; - - state = state_sample; - module_cnt_b = 0; - module_cnt_w = 0; - Tmod0_w = 0xFFFFFFFF; - Tmod0_b = 0xFFFFFFFF; - bar_count = 0; - Median_init(&med_b, 3, 1); - Median_init(&med_w, 3, 1); - } - break; - - case state_sample: - if (!timeout_count) - { - state = state_finish; - break; - } - - if (white) - { - module_cnt_w++; - } - else - { - module_cnt_b++; - } - if (white != pin_last) - { - if (pin_last) - { - if (bar_count < 10) - { - if (1.5*module_cnt_w < Tmod0_w) - { - Tmod0_w = module_cnt_w; - } - } - timeout_reload = 10*Tmod0_w; - bars[bar_count].T = module_cnt_w; - bars[bar_count].black = 0; - module_cnt_w = 0; - - } - else - { - if (bar_count < 10) - { - if (1.5*module_cnt_b < Tmod0_b) - { - Tmod0_b = module_cnt_b; - } - } - timeout_reload = 10*Tmod0_b; - bars[bar_count].T = module_cnt_b; - bars[bar_count].black = 1; - module_cnt_b = 0; - } - bar_count++; - - } - break; - - case state_finish: - printf("------------------------------------------------\n"); - printf(" Black White \n"); - skip = 0; - start = 1; - for (i=0; i < 4; i++) - { - bc_b[i] = (i+1)*Tmod0_b; - bc_w[i] = (i+1)*Tmod0_w; - } - for (i=0; i < bar_count; i++) - { - if (bars[i].black) - { - M = detect_module(bars[i].T, bc_b); - if (M) - { - kc = (float)bars[i].T/bc_b[M-1]; - error = kc - 1; - Median_value_add(&med_b, kc); - printf("M=%d, R=%2.2f, E=%+2.2f [%04d]", M, kc, error, bc_b[M-1]); - kc = Median_get(&med_b); - bc_b[M-1] = (UINT32)(kc*bc_b[M-1]); - } -// printf("%d", M); - - } - else - { - M = detect_module(bars[i].T, bc_w); - if (M) - { - kc = (float)bars[i].T/bc_w[M-1]; - error = kc - 1; - Median_value_add(&med_w, kc); - printf(" M=%d, R=%2.2f, E=%+2.2f [%04d]", M, kc, error, bc_w[M-1]); - kc = Median_get(&med_w); - bc_w[M-1] = (UINT32)(kc*bc_w[M-1]); - - } -// printf("%d", M); - printf("\n"); - } - } - Median_free(&med_b); - Median_free(&med_w); - if (bar_count) - printf("\n"); - - state = state_idle; - break; - - } - if (white != pin_last) - timeout_count = timeout_reload; - - pin_last = white; - if (timeout_count) - timeout_count--; - - } -} - -int main(void) -{ - - int i; - UINT32 volatile *pTim_ctrl = (UINT32*)SYS_ITIM_CTRL; - UINT32 volatile *pTim_stat = (UINT32*)SYS_ITIM_STAT; - UINT32 volatile *pTim0_cnt = (UINT32*)SYS_ITIM0_CNT; - UINT32 volatile *pTim0_cmp = (UINT32*)SYS_ITIM0_CMP; - - *pTim0_cnt = 0; - *pTim0_cmp = (UINT32)T_SAMPLE; - *pTim_stat = 1; - *pTim_ctrl = 3; - - interrupt_register(7, (void*)handler7); - - printf("Jenners BarCoder\n"); - - interrupt_enable(7); - - while(1) - { - } - return 0; -} diff --git a/lib/CPUs/MIPS/bsp/examples/basicmath_small.c b/lib/CPUs/MIPS/bsp/examples/basicmath_small.c deleted file mode 100644 index 049fea2..0000000 --- a/lib/CPUs/MIPS/bsp/examples/basicmath_small.c +++ /dev/null @@ -1,84 +0,0 @@ -#include "snipmath.h" -#include - -/* The printf's may be removed to isolate just the math calculations */ - -int main(void) -{ - double a1 = 1.0, b1 = -10.5, c1 = 32.0, d1 = -30.0; - double a2 = 1.0, b2 = -4.5, c2 = 17.0, d2 = -30.0; - double a3 = 1.0, b3 = -3.5, c3 = 22.0, d3 = -31.0; - double a4 = 1.0, b4 = -13.7, c4 = 1.0, d4 = -35.0; - double x[3]; - double X; - int solutions; - int i; - unsigned long l = 0x3fed0169L; - struct int_sqrt q; - long n = 0; - - /* solve soem cubic functions */ - printf("********* CUBIC FUNCTIONS ***********\n"); - /* should get 3 solutions: 2, 6 & 2.5 */ - SolveCubic(a1, b1, c1, d1, &solutions, x); - printf("Solutions:"); - for(i=0;i0;b1--) { - for(c1=5;c1<15;c1+=0.5) { - for(d1=-1;d1>-11;d1--) { - SolveCubic(a1, b1, c1, d1, &solutions, x); - printf("Solutions:"); - for(i=0;i -#include - -/* this should be approx 2 Bo*oMips to start (note initial shift), and will - * still work even if initially too large, it will just take slightly longer */ -unsigned long loops_per_jiffy = (1<<12); - -/* This is the number of bits of precision for the loops_per_jiffy. Each - * bit takes on average 1.5/HZ seconds. This (like the original) is a little - * better than 1% */ -#define LPS_PREC 8 - -extern void delay(unsigned int loops); - -//plagiarized straight from the 2.4 sources. -#ifdef NOMAIN -int calibrate_delay(void) -#else -int main(void) -#endif -{ - unsigned long ticks, loopbit; - int lps_precision = LPS_PREC; - - loops_per_jiffy = (1<<12); - - printf("Calibrating delay loop... "); - while (loops_per_jiffy <<= 1) { - /* wait for "start of" clock tick */ - ticks = clock(); - while (ticks == clock()) - /* nothing */; - /* Go .. */ - ticks = clock(); - delay(loops_per_jiffy); - ticks = clock() - ticks; - if (ticks) - break; - } - -/* Do a binary approximation to get loops_per_jiffy set to equal one clock - (up to lps_precision bits) */ - - loops_per_jiffy >>= 1; - loopbit = loops_per_jiffy; - while ( lps_precision-- && (loopbit >>= 1) ) { - loops_per_jiffy |= loopbit; - ticks = clock(); - while (ticks == clock()); - ticks = clock(); - delay(loops_per_jiffy); - if (clock() != ticks) /* longer than 1 tick */ - loops_per_jiffy &= ~loopbit; - } - - -/* Round the value and print it */ - printf("%lu.%02lu BogoMIPS\n", - loops_per_jiffy/(500000/HZ), - (loops_per_jiffy/(5000/HZ)) % 100); - - - return loops_per_jiffy; -} - diff --git a/lib/CPUs/MIPS/bsp/examples/bootloader/Makefile b/lib/CPUs/MIPS/bsp/examples/bootloader/Makefile deleted file mode 100644 index 513a332..0000000 --- a/lib/CPUs/MIPS/bsp/examples/bootloader/Makefile +++ /dev/null @@ -1,47 +0,0 @@ -ENDIAN='big' - -ifeq ($(ENDIAN), 'big') - ENDIAN_FLAGS=-EB - LIB_DIRS=-L $(MIPS_TOOLS_PREFIX)/mipsel-elf/lib/eb -L $(MIPS_TOOLS_PREFIX)/lib/gcc/mipsel-elf/$(MIPS_GCC_VER)/eb -else - ENDIAN_FLAGS=-EL - LIB_DIRS=-L $(MIPS_TOOLS_PREFIX)/mipsel-elf/lib -L $(MIPS_TOOLS_PREFIX)/lib/gcc/mipsel-elf/$(MIPS_GCC_VER) -endif - -CFLAGS=$(ENDIAN_FLAGS) -Os -I. -I../ -I../libsys -msoft-float -march=r3000 -LFLAGS=$(ENDIAN_FLAGS) -M -T bootloader.ld - -LIBS=-lc -lgcc - -CC=mipsel-elf-gcc -LD=mipsel-elf-ld -OBJDUMP=mipsel-elf-objdump -OBJCOPY=mipsel-elf-objcopy - -all: bootloader_flash - -libsys: startup_boot.S init_boot.S kernel_boot.S libsys_boot.c - $(CC) $(CFLAGS) -c startup_boot.S -o startup.o - $(CC) $(CFLAGS) -c init_boot.S -o init.o - $(CC) $(CFLAGS) -c kernel_boot.S -o kernel.o - $(CC) $(CFLAGS) -c libsys_boot.c -o libsys.o - -bootloader: libsys bootloader.c - $(CC) $(CFLAGS) -g -c bootloader.c - $(LD) $(LFLAGS) $(LIB_DIRS) startup.o init.o kernel.o libsys.o bootloader.o -o bootloader.elf $(LIBS) >bootloader.map - $(OBJDUMP) -d bootloader.elf > bootloader.dis - $(OBJCOPY) bootloader.elf -O binary bootloader.ROM.bin - $(OBJCOPY) -O srec bootloader.elf bootloader.srec - romgen bootloader.ROM.bin 10 $(ENDIAN_FLAGS) - -bootloader_flash: libsys bootloader_with_flash.c - $(CC) $(CFLAGS) -g -c bootloader_with_flash.c - $(CC) $(CFLAGS) -g -c ../cfiflash.c - $(LD) $(LFLAGS) $(LIB_DIRS) startup.o init.o kernel.o libsys.o cfiflash.o bootloader_with_flash.o -o bootloader.elf $(LIBS) >bootloader.map - $(OBJDUMP) -d bootloader.elf > bootloader.dis - $(OBJCOPY) bootloader.elf -O binary bootloader.ROM.bin - $(OBJCOPY) -O srec bootloader.elf bootloader.srec - romgen bootloader.ROM.bin 11 $(ENDIAN_FLAGS) - -clean: - rm -rf *.o *.bin *.map *.dis *.srec *.elf *.vhd* *.tcl bootloader > /dev/null diff --git a/lib/CPUs/MIPS/bsp/examples/bootloader/bootloader.c b/lib/CPUs/MIPS/bsp/examples/bootloader/bootloader.c deleted file mode 100644 index 7ade222..0000000 --- a/lib/CPUs/MIPS/bsp/examples/bootloader/bootloader.c +++ /dev/null @@ -1,247 +0,0 @@ -#include "libsys_boot.h" - -typedef struct _ssrec_t -{ - UINT32 addr; - UINT32 size; - UINT32 type; - UINT8 *data; - -} srec_t; - -enum srec_type -{ - srec_err, srec_sob, srec_data, srec_rec, srec_eob -}; - -UINT8 h2i(UINT8 *c) -{ - int i; - UINT8 t, b = 0; - - for (i=0; i < 2; i++) - { - t = c[i]; - if (t >= 'A') - t = t - 'A' + 10; - else - t -= '0'; - - b = (b << 4) | t; - } - return b; -} - -int decode_srec(srec_t *pRec, UINT8 *pBuf, int buflen) -{ - UINT8 chksum, byte; - int alen, i; - - if (!buflen) - return srec_err; - - pRec->type = srec_rec; - alen = 0; - if ((pBuf[1] > '0') && (pBuf[1] < '4')) - { - alen = pBuf[1] - '0' + 1; - pRec->type = srec_data; - } - else if ((pBuf[1] >= '7') && (pBuf[1] <= '9')) - { - alen = 11 - (pBuf[1] - '0'); - pRec->type = srec_eob; - } - else if (pBuf[1] == '0') - { - alen = 2; - pRec->type = srec_sob; - } - - byte = h2i(&pBuf[2]); - pRec->size = byte; - chksum = byte; - - pRec->addr = 0; - for (i=0; i < alen; i++) - { - byte = h2i(&pBuf[4+2*i]); - pRec->addr = pRec->addr << 8 | byte; - chksum += byte; - } - pRec->size -= (alen+1); - - pRec->data = (UINT8*) &pBuf[4 + 2*alen]; - for (i=0; i < (int)pRec->size; i++) - { - byte = h2i(&pRec->data[2*i]); - pRec->data[i] = byte; - chksum += byte; - } - chksum = ~chksum; - byte = h2i(&pRec->data[2*i]); - if (chksum != byte) - return 0; - - return pRec->type; -} - -int srec_getline(UINT8 *pLine) -{ - char c; - int i = 0; - - do - { - c = readchar(); - - } while ((c != 's') && (c != 'S')); - - while(((c != 0x0D) && (c != 0x0A))) - { - pLine[i++] = c; - c = readchar(); - }; - - return i; -} - -void Jump_to(void *pEntry) -{ - __asm - ( - ".set noreorder\n" - ); - __asm - ( - "jr %[pEntry]\n" // jump entry - : - : [pEntry] "r" (pEntry) - ); - __asm - ( - "nop\n" - ); - __asm - ( - ".set reorder\n" - ); -} - -void Exec_at(void *pEntry) -{ - __asm - ( - ".set noreorder\n" - ); - - __asm - ( - "mfc0 $26, $12\n" // change exception vector - "li $27, 0xFFBFFFFF\n" - "and $26, $27\n" - "mtc0 $26, $12\n" - ); - - __asm - ( - "lw $v0, 16($sp)\n" - "nop\n" - "jr $v0\n" // jump entry - "rfe\n" - ); - - __asm - ( - ".set reorder\n" - ); -} -void PrintCPUinfo(void) -{ - int result, rev_id; - - char *cpu_type_str[7] = {"invalid", "R2000", "R3000", "R6000", "R4000", "reserved", "R6000A"}; - - // Print Status register - result = CP0_SR_read(); - - sputs("Status : "); - print_word(result); - sputs("\n"); - - // Print Revision - result = CP0_PRID_read(); - rev_id = (result >> 8) & 0xFF; - sputs("CPU type: "); - if ((rev_id > 0) && (rev_id < 0x07)) - { - sputs(cpu_type_str[rev_id]); - sputs(" Rev."); - rev_id = result & 0xFF; - print_byte((char)rev_id); - } - else - sputs("Unknown"); - - sputs("\n"); - -} - -#define MAX_IMG_SIZE (1024*1024) // bytes - -int main(int argc, char *argv[]) -{ - UINT8 buf[256]; - srec_t srec; - int result, srec_state, i; - UINT32 haddr; - volatile UINT8 *pMem; - haddr = 0; - - // ---------------------------------------------------------- - sputs("\n\n"); - PrintCPUinfo(); - sputs("Booting from UART.."); - - while(1) - { - sputs("."); - while(1) - { - result = srec_getline(buf); - srec_state = decode_srec(&srec, buf, result); - switch (srec_state) - { - case srec_data: - if ((srec.addr + srec.size) > haddr) - haddr = srec.addr + srec.size; - - pMem = (UINT8*)srec.addr; - for (i=0; i < srec.size; i++) - *pMem++ = srec.data[i]; - - break; - - case srec_eob: - sputs("done\n\n"); - sputs("Execute program at "); - print_word(srec.addr); - sputs("\n\n"); - - Exec_at((void*)srec.addr); - break; - - default: - result = -1; - break; - } - if (result < 0) - { - break; - } - - }; - } - return 0; -} - diff --git a/lib/CPUs/MIPS/bsp/examples/bootloader/bootloader.ld b/lib/CPUs/MIPS/bsp/examples/bootloader/bootloader.ld deleted file mode 100644 index c3cd35e..0000000 --- a/lib/CPUs/MIPS/bsp/examples/bootloader/bootloader.ld +++ /dev/null @@ -1,53 +0,0 @@ -MEMORY -{ - rom : ORIGIN = 0xBFC00000, LENGTH = 0x00002000 /* 8K */ - ram : ORIGIN = 0x40000000, LENGTH = 0x00002000 /* 8K */ -} - -OUTPUT_ARCH(mips) -SEARCH_DIR("."); -SEARCH_DIR("/usr/local/mipsel-elf/lib:/usr/local/mipsel-elf/lib/eb"); -SEARCH_DIR("/usr/local/lib/gcc/mipsel-elf/4.3.3:/usr/local/lib/gcc/mipsel-elf/4.3.3/eb"); - -stack_ptr = 0x7FFFEFF0; -baudrate = 0x0D; -sys_led_port = 0xA0000000; -sys_uart_data = 0xA0010000; -sys_uart_stat = 0xA0010004; -sys_uart_baud = 0xA0010008; -sys_timer_usec = 0xA000008; -sys_timer_sec = 0xA000000C; - - -SECTIONS -{ - .init ORIGIN(rom) : - { - start = ALIGN(4); - entry = ALIGN(4); - _entry = ALIGN(4); - __entry = ALIGN(4); - *(.stext) - } > rom - - .ktext ORIGIN(rom) + 0x180 : - { - *(.ktext) - } > rom - - .text . : - { - *(.text) - } > rom - - .rodata . : - { - *(.rodata*) - } > rom - - .data ORIGIN(ram) : - { - *(.*data) *(.*bss) *(.*common) - } > ram - -} diff --git a/lib/CPUs/MIPS/bsp/examples/bootloader/bootloader_with_flash.c b/lib/CPUs/MIPS/bsp/examples/bootloader/bootloader_with_flash.c deleted file mode 100644 index 197ab44..0000000 --- a/lib/CPUs/MIPS/bsp/examples/bootloader/bootloader_with_flash.c +++ /dev/null @@ -1,383 +0,0 @@ -#include "libsys_boot.h" -#include "cfiflash.h" - -#define MAGIC_EB 0x4A464931 // "JFI1" in big-endian; -#define MAGIC_EL 0x3149464A // "JFI1" in little-endian; - -typedef struct _ssrec_t -{ - UINT32 addr; - UINT32 size; - UINT32 type; - UINT8 *data; - -} srec_t; -typedef struct _sflash_alloc_tbl_t -{ - UINT32 images[16]; - -} flash_alloc_tbl_t; - -typedef struct _sflash_img_hdr_t -{ - UINT32 magic; - UINT32 target_base; - UINT32 img_base; - UINT32 img_size; - UINT32 hdr_next; - UINT8 img_name[128]; - UINT8 res[108]; - -} flash_img_hdr_t; - -enum srec_type -{ - srec_err, srec_sob, srec_data, srec_rec, srec_eob -}; - -UINT8 h2i(UINT8 *c) -{ - int i; - UINT8 t, b = 0; - - for (i=0; i < 2; i++) - { - t = c[i]; - if (t >= 'A') - t = t - 'A' + 10; - else - t -= '0'; - - b = (b << 4) | t; - } - return b; -} - -int decode_srec(srec_t *pRec, UINT8 *pBuf, int buflen) -{ - UINT8 chksum, byte; - int alen, i; - - if (!buflen) - return srec_err; - - pRec->type = srec_rec; - alen = 0; - if ((pBuf[1] > '0') && (pBuf[1] < '4')) - { - alen = pBuf[1] - '0' + 1; - pRec->type = srec_data; - } - else if ((pBuf[1] >= '7') && (pBuf[1] <= '9')) - { - alen = 11 - (pBuf[1] - '0'); - pRec->type = srec_eob; - } - else if (pBuf[1] == '0') - { - alen = 2; - pRec->type = srec_sob; - } - - byte = h2i(&pBuf[2]); - pRec->size = byte; - chksum = byte; - - pRec->addr = 0; - for (i=0; i < alen; i++) - { - byte = h2i(&pBuf[4+2*i]); - pRec->addr = pRec->addr << 8 | byte; - chksum += byte; - } - pRec->size -= (alen+1); - - pRec->data = (UINT8*) &pBuf[4 + 2*alen]; - for (i=0; i < (int)pRec->size; i++) - { - byte = h2i(&pRec->data[2*i]); - pRec->data[i] = byte; - chksum += byte; - } - chksum = ~chksum; - byte = h2i(&pRec->data[2*i]); - if (chksum != byte) - return 0; - - return pRec->type; -} - -int srec_getline(UINT8 *pLine) -{ - char c; - int i = 0; - - do - { - c = readchar(); - - } while ((c != 's') && (c != 'S')); - - while(((c != 0x0D) && (c != 0x0A))) - { - pLine[i++] = c; - c = readchar(); - }; - - return i; -} - -void Jump_to(void *pEntry) -{ - __asm - ( - ".set noreorder\n" - ); - __asm - ( - "jr %[pEntry]\n" // jump entry - : - : [pEntry] "r" (pEntry) - ); - __asm - ( - "nop\n" - ); - __asm - ( - ".set reorder\n" - ); -} - -void Exec_at(void *pEntry) -{ - __asm - ( - ".set noreorder\n" - ); - - __asm - ( - "li $26, 0x10000000\n" - "mtc0 $26, $12\n" - ); - - __asm - ( - "jr %[pEntry]\n" // jump entry - : - : [pEntry] "r" (pEntry) - ); - - __asm - ( - "rfe\n" - ); - - __asm - ( - ".set reorder\n" - ); -} - -void Exec_RE_at(void *pEntry) -{ - __asm - ( - ".set noreorder\n" - ); - - __asm - ( - "mfc0 $26, $12\n" // change exception vector - "li $27, 0xFFBFFFFF\n" - "and $26, $27\n" - "li $27, 0x02000000\n" // Reverse Endianess - "or $26, $27\n" - "mtc0 $26, $12\n" - ); - - __asm - ( - "jr %[pEntry]\n" // jump entry - : - : [pEntry] "r" (pEntry) - ); - - __asm - ( - "rfe\n" - ); - - __asm - ( - ".set reorder\n" - ); -} - -#define MAX_IMG_SIZE (1024*1024) // bytes -#define SDRAM_BASE 0x40000000 -#define FLASH_USE_BLOCK 1 - -int main(int argc, char *argv[]) -{ - UINT8 buf[256]; - srec_t srec; - int srec_state, i; - UINT32 haddr, result; - flash_t flash; - flash_img_hdr_t img_hdr = {0}; - flash_img_hdr_t *pImg_hdr; - UINT32 img_size, block_sel; - - volatile UINT32 *pLED = (UINT32*)SYS_LED_PORT; - volatile UINT32 *pBtn = (UINT32*)SYS_GPIO0; - volatile UINT32 *pDip = (UINT32*)SYS_GPIO1; - volatile UINT8 *pMem; - volatile UINT32 *pFlashIO = (UINT32*)SYS_FLASH_IO; // Flash in uncached area - volatile UINT32 *pFlashMem = (UINT32*)SYS_FLASH_MEM; // Flash in cached area - volatile UINT32 *ram32 = (UINT32*)SDRAM_BASE; - UINT32 flash_offset; - - *pLED = 0; - haddr = 0; - block_sel = 0x7F & (UINT32)*pDip; - - // ---------------------------------------------------------- - if (IS_ERROR(flash_find(&flash, SYS_FLASH_IO))) - { - sputs("Cannot find flash device. Exit now!\n\n"); - return 1; - } - - // Get flash offset by value of DIP-switch - flash_offset = flash_get_offset_by_blocknum(&flash, block_sel); - - ram32 = (UINT32*)(SDRAM_BASE); - pFlashIO = (UINT32*)(SYS_FLASH_IO + flash_offset); - - if (!(*pBtn & 8)) - { - sputs("\n\n"); - pImg_hdr = (flash_img_hdr_t*)pFlashIO; - if ((pImg_hdr->magic != MAGIC_EL) && (pImg_hdr->magic != MAGIC_EB)) - { - sputs("\n\n"); - sputs("Invalid image found at ");print_word(flash_offset); sputs(". Abort.\n"); - return 1; - } - - sputs("Booting application from flash (");print_word(flash_offset);sputs(")..."); - - ram32 = (UINT32*)pImg_hdr->target_base; - img_size = pImg_hdr->img_size; - - // It's safe to use cached Flash, - // because D-Cache was invalidated during execution of start code - pFlashMem = (UINT32*)(SYS_FLASH_MEM + pImg_hdr->img_base); - - for (i=0; i < img_size/4; i++) - ram32[i] = pFlashMem[i]; - - sputs("done\n"); - - sputs("Execute at ");print_word(pImg_hdr->target_base); sputs("\n\n"); - Exec_at((void*)ram32); - } - else - { - - sputs("\n\n"); - - sputs("Reading HEX-Record from UART.."); - - // Erase SDRAM - for (i=0; i < MAX_IMG_SIZE/4; i++) - ram32[i] = 0; - - - while(1) - { - sputs("."); - while(1) - { - result = srec_getline(buf); - srec_state = decode_srec(&srec, buf, result); - *pLED = 0; - switch (srec_state) - { - case srec_data: - if ((srec.addr + srec.size) > haddr) - haddr = srec.addr + srec.size; - - pMem = (UINT8*)srec.addr; - for (i=0; i < srec.size; i++) - *pMem++ = srec.data[i]; - - break; - - case srec_eob: - sputs("done\n\n"); - img_hdr.magic = MAGIC_EB; - img_hdr.target_base = srec.addr; - img_hdr.img_size = haddr - srec.addr; - img_hdr.img_base = flash_offset + sizeof(flash_img_hdr_t); - img_hdr.hdr_next = flash_get_offset_blockaligned(&flash, img_hdr.img_base + img_hdr.img_size); - sputs("Size of application : ");print_word(img_hdr.img_size); sputs("\n"); - sputs("Programming flash at : ");print_word(flash_offset); sputs("\n"); - sputs("Next free flash offset : ");print_word(img_hdr.hdr_next); sputs("\n"); - - sputs("Flash erase..."); - result = flash_erase(&flash, flash_offset, img_hdr.img_size + sizeof(flash_img_hdr_t)); - if (IS_ERROR(result)) - { - sputs("failed (");print_word(result);sputs(")\n"); - break; - } - sputs("done\n"); - - sputs("Flash write..."); - result = flash_program(&flash, flash_offset, (UINT8*)&img_hdr, sizeof(flash_img_hdr_t)); - if (IS_ERROR(result)) - { - sputs("failed (");print_word(result);sputs(")\n"); - break; - } - result = flash_program(&flash, img_hdr.img_base, (UINT8*)img_hdr.target_base, img_hdr.img_size); - if (IS_ERROR(result)) - { - sputs("failed (");print_word(result);sputs(")\n"); - break; - } - sputs("done\n"); - - sputs("Flash verify..."); - result = flash_verify(&flash, img_hdr.img_base, (UINT8*)img_hdr.target_base, img_hdr.img_size); - if (IS_ERROR(result)) - { - sputs("failed (");print_word(result);sputs(")\n"); - break; - } - sputs("passed\n"); - - // Jump to reset vector - Jump_to((void*)0xBFC00000); - - break; - - default: - result = -1; - break; - } - if (IS_ERROR(result)) - { - *pLED = 0x40000000; - break; - } - - }; - } - } - return 0; -} - diff --git a/lib/CPUs/MIPS/bsp/examples/bootloader/init_boot.S b/lib/CPUs/MIPS/bsp/examples/bootloader/init_boot.S deleted file mode 100644 index 84a8d9d..0000000 --- a/lib/CPUs/MIPS/bsp/examples/bootloader/init_boot.S +++ /dev/null @@ -1,19 +0,0 @@ - .file "init.S" - - .text - .section .init,"ax" - .align 2 - .globl _init - .extern end - -_init: - .set noreorder - - # set uart - la $26, sys_uart_baud - addiu $27, $0, baudrate - sw $27, 0($26) - - jr $ra - - .set reorder diff --git a/lib/CPUs/MIPS/bsp/examples/bootloader/jtag_upd.bat b/lib/CPUs/MIPS/bsp/examples/bootloader/jtag_upd.bat deleted file mode 100644 index 33bc43a..0000000 --- a/lib/CPUs/MIPS/bsp/examples/bootloader/jtag_upd.bat +++ /dev/null @@ -1,13 +0,0 @@ -@rem -@rem Setup Chipscope's TCL JTAG path -@rem -@rem Usage: cs_xtclsh.bat args... -@rem -@date /T > date.tmp -@date 15.03.2009 -@set CS_PATH=%XILINX%\ChipScope\bin\nt -@echo %CS_PATH% - -@call %CS_PATH%\cs_xtclsh bootloader.ROM.tcl -@type date.tmp | date >nul -@del date.tmp diff --git a/lib/CPUs/MIPS/bsp/examples/bootloader/kernel_boot.S b/lib/CPUs/MIPS/bsp/examples/bootloader/kernel_boot.S deleted file mode 100644 index b4a8694..0000000 --- a/lib/CPUs/MIPS/bsp/examples/bootloader/kernel_boot.S +++ /dev/null @@ -1,46 +0,0 @@ - .file "kernel.S" - - .section .ktext,"ax" - .align 2 - - .macro kpush reg - addiu $sp, 4 - sw \reg, 0($sp) - .endm - - .macro kpop reg - lw \reg, 0($sp) - addiu $sp, -4 - .endm - -_exc_handler: - - .set noreorder - - # Set Error LED and ExcCode LEDs - # Get Cause - mfc0 $26, $13 - li $27, 0xC0000000 - srl $26, 2 - andi $26, 0x000F - or $26, $27 - la $27, sys_led_port - sw $26, 0($27) - - # wait for all interrupts = 0 -$w4x: mfc0 $26, $13 - nop - srl $26, 8 - andi $26, 0xFF - bnez $26, $w4x - nop - - # Get return address - mfc0 $26, $14 - - # Return - nop - jr $26 - rfe - .set reorder - diff --git a/lib/CPUs/MIPS/bsp/examples/bootloader/libsys_boot.c b/lib/CPUs/MIPS/bsp/examples/bootloader/libsys_boot.c deleted file mode 100644 index 0f39d80..0000000 --- a/lib/CPUs/MIPS/bsp/examples/bootloader/libsys_boot.c +++ /dev/null @@ -1,214 +0,0 @@ -#include -#include -#include -#include -#include -#include -#include "libsys_boot.h" - -// --------------------------------------------------------------------------------- -// MIPS specific -UINT32 CP0_SR_read(void) -{ - UINT32 result; - - __asm - ( - "mfc0 %[val], $12\n" - : [val] "=r" (result) - ); - - return result; -} - -void CP0_SR_write(UINT32 val) -{ - __asm - ( - "mtc0 %[val], $12\n" - : /* no output */ - : [val] "r" (val) - ); -} - -UINT32 CP0_CR_read(void) -{ - UINT32 result; - - __asm - ( - "mfc0 %[val], $13\n" - : [val] "=r" (result) - ); - - return result; -} - -void CP0_CR_write(UINT32 val) -{ - __asm - ( - "mtc0 %[val], $13\n" - : - : [val] "r" (val) - ); -} - -UINT32 CP0_PRID_read(void) -{ - UINT32 result; - - __asm - ( - "mfc0 %[val], $15\n" - : [val] "=r" (result) - ); - - return result; -} - -// --------------------------------------------------------------------------------- -char readchar(void) -{ - volatile UINT32 *pUART_stat = (UINT32*)SYS_UART_STAT; - volatile UINT32 *pUART_data = (UINT32*)SYS_UART_DATA; - - while(!(0x10 & *pUART_stat)); - - return (char)*pUART_data; -} - -void writechar(char c) -{ - volatile UINT32 *pUART_stat = (UINT32*)SYS_UART_STAT; - volatile UINT32 *pUART_data = (UINT32*)SYS_UART_DATA; - - while((0x02 & *pUART_stat) != 0); - - *pUART_data = (UINT32)c; -} - -void _putchar(char c) -{ - if (c == 0x0A) - { - writechar(0x0D); - } - writechar(c); -} - -int sputs(char *pStr) -{ - char *start; - start = pStr; - - while(*pStr) - _putchar(*(pStr++)); - - return pStr - start; -} - -void print_byte(char byte) -{ - int i; - unsigned char c, nibble; - - for (i=0; i < 2; i++) - { - nibble = (char)((byte >> 4) & 0xF); - byte <<= 4; - - if (nibble < 10) - c = nibble + '0'; - else - c = nibble + 'A' - 10; - - _putchar(c); - } -} - -void print_word(int word) -{ - int i; - unsigned char c, nibble; - - for (i=0; i < 4; i++) - { - c = (char) (word >> 24); - print_byte(c); - word <<= 8; - } -} - -// --------------------------------------------------------------------------------- -// PrintBuffer8() -// Prints byte buffer as hex and ascii interpretation -// --------------------------------------------------------------------------------- -// _Parameters : -// pBuf: : IN: Buffer to display -// nbpr : Number of bytes per row to display -// len : Length of input buffer -// _Return: none -// -// --------------------------------------------------------------------------- -void PrintBuffer8(UINT8 *pBuf, int nbpr, int len) -{ - memdump(pBuf, 1, nbpr, len); -} - -void memdump(UINT8 *pBuf, int print_offset_only, int num_bytes_per_row, int len) -{ - int i, j, cnt_hex, cnt_asc, base; - unsigned char c; - - i = j = 0; - cnt_hex = len; - cnt_asc = len; - base = 0; - if (!print_offset_only) - base = (int)pBuf; - - do - { - print_word(base + i); - sputs(": "); - for (j=0; j < num_bytes_per_row; j++) - { - if (cnt_hex) - { - print_byte(pBuf[i+j]); - sputs(" "); - cnt_hex--; - } - else - { - sputs(" "); - break; - } - - } - - sputs(" "); - for (j=0; j < num_bytes_per_row; j++) - { - if (cnt_asc) - { - c = pBuf[i+j]; - if((c < 0x20) || (c > 0x7F)) - c = '.'; - - _putchar(c); - cnt_asc--; - } - else - { - sputs(" "); - break; - } - } - sputs("\n"); - i += num_bytes_per_row; - - } while (cnt_hex); -} - diff --git a/lib/CPUs/MIPS/bsp/examples/bootloader/libsys_boot.h b/lib/CPUs/MIPS/bsp/examples/bootloader/libsys_boot.h deleted file mode 100644 index 3bf4ecc..0000000 --- a/lib/CPUs/MIPS/bsp/examples/bootloader/libsys_boot.h +++ /dev/null @@ -1,54 +0,0 @@ -#ifndef LIBSYS_H -#define LIBSYS_H - -// --------------------------------------------------------- -// Types -// --------------------------------------------------------- -#define INT8 char -#define INT16 short -#define INT32 long -#define UINT8 unsigned char -#define UINT16 unsigned short -#define UINT32 unsigned long -#define INT int -#define UINT unsigned int -#define FLOAT32 float -#define FLOAT64 double - -#define IS_ERROR(e) ((e & 0x80000000) == 0x80000000) - -#define SYS_GPIO0 0xA0000000 -#define SYS_GPIO1 0xA0000004 -#define SYS_LED_PORT SYS_GPIO0 -#define SYS_USB_CTRL SYS_GPIO1 -#define SYS_TIMER_USEC 0xA0000008 -#define SYS_TIMER_SEC 0xA000000C -#define SYS_UART_DATA 0xA0010000 -#define SYS_UART_STAT 0xA0010004 -#define SYS_UART_BAUD 0xA0010008 -#define SYS_USB_DATA 0xA0020000 -#define SYS_USB_MBX 0xA0020004 -#define SYS_USB_ADDR 0xA0020008 -#define SYS_USB_STATUS 0xA002000C -#define SYS_FLASH_IO 0xA4000000 -#define SYS_FLASH_MEM 0x00000000 - -// MIPS specific -UINT32 CP0_SR_read(void); -void CP0_SR_write(UINT32 val); -UINT32 CP0_CR_read(void); -void CP0_CR_write(UINT32 val); -UINT32 CP0_PRID_read(void); - -// General -char readchar(void); -void writechar(char c); -int write(int file, char *ptr, int len); -int sputs(char *pStr); -void print_byte(char byte); -void print_word(int word); -void PrintBuffer8(UINT8 *pBuf, int nbpr, int len); -void memdump(UINT8 *pBuf, int print_offset_only, int num_bytes_per_row, int len); - -#endif // LIBSYS_H - diff --git a/lib/CPUs/MIPS/bsp/examples/bootloader/startup_boot.S b/lib/CPUs/MIPS/bsp/examples/bootloader/startup_boot.S deleted file mode 100644 index 8da9ee0..0000000 --- a/lib/CPUs/MIPS/bsp/examples/bootloader/startup_boot.S +++ /dev/null @@ -1,43 +0,0 @@ - .file "startup.S" - - .text - .section .init,"ax" - .extern _init - .align 2 - -_start: - .set noreorder - - # set stack pointer - la $sp, stack_ptr - - # Set Kernel mode - li $26, 0x1040000C - mtc0 $26, $12 - li $26, 0x00000000 - mtc0 $26, $13 - - mfc0 $26, $15 - nop - mtc0 $26, $31 - - # Invalidate I-Cache - cop0 32 - - # Invalidate D-Cache - cop0 34 - - # jump init - la $26, _init - jalr $26 - nop - - la $26, main - jalr $26 - nop -_terminate: - nop - j _terminate - nop - - .set reorder diff --git a/lib/CPUs/MIPS/bsp/examples/cfiflash.c b/lib/CPUs/MIPS/bsp/examples/cfiflash.c deleted file mode 100644 index bbfbe43..0000000 --- a/lib/CPUs/MIPS/bsp/examples/cfiflash.c +++ /dev/null @@ -1,415 +0,0 @@ -#include -#include -#include "libsys.h" -#include "cfiflash.h" - -UINT32 cfi_get_status(flash_t *pObj) -{ - volatile UINT32 *pF; - UINT32 status; - - pF = (UINT32*)pObj->pBase; - - *pF = 0x00700070; - - status = *pF; - - *pF = 0x00FF00FF; - - return status; - -} - -void cfi_init(flash_t *pObj, UINT32 base_addr) -{ - int i; - UINT8 *pInfo; - UINT32 endian; - UINT8 *pEndian; - - pObj->pBase = (void*)base_addr; - - pInfo = (UINT8*)&pObj->info; - for (i=0; i < sizeof(flash_info_t); i++) - { - pInfo[i] = 0; - } - pObj->eb = 0; - endian = 0x12345678; - pEndian = (UINT8*)&endian; - if (*pEndian == 0x12) - { - pObj->eb = 1; - } - -} - -UINT32 cfi_find(flash_t *pObj) -{ - int i; - volatile UINT32 *pF; - volatile UINT16 *pF16; -// UINT8 qry_ref[12] = {0x51, 0x00, 0x51, 0x00, 0x52, 0x00, 0x52, 0x00, 0x59, 0x00, 0x59, 0x00}; - UINT32 size; - - pF = (UINT32*)pObj->pBase; - pF16 = (UINT16*)pObj->pBase; - - // Look for flash - *pF = 0x00980098; -// for (i=0; i < sizeof(qry_ref); i++) -// if (((UINT8*)(&pF[0x10]))[i] != qry_ref[i]) -// return (UINT32)-1; - - *pF = 0x00FF00FF; - *pF = 0x00900090; - -/* - printf("ManID : %8.8X\n", (UINT32)pF[0]); - printf("Device code : %8.8X\n", (UINT32)pF[1]); - printf("Block info : %8.8X\n", (UINT32)pF[2]); - - printf("VCC(min) : %8.8X\n", (UINT32)pF[0x1B]); - printf("VCC(max) : %8.8X\n", (UINT32)pF[0x1C]); - printf("VPP(min) : %8.8X\n", (UINT32)pF[0x1D]); - printf("VPP(max) : %8.8X\n", (UINT32)pF[0x1E]); - printf("Device Layout : %8.8X\n", (UINT32)pF[0x27]); - printf("Interface type : %8.8X %8.8X\n", (UINT32)pF[0x28], (UINT32)pF[0x29]); - printf("Write buffer size : %8.8X %8.8X\n", (UINT32)pF[0x2A], (UINT32)pF[0x2B]); - printf("Num. erase blocks : %8.8X\n", (UINT32)pF[0x2C]); - printf("Erase block info : %8.8X %8.8X %8.8X %8.8X\n", (UINT32)pF[0x2D], (UINT32)pF[0x2E], (UINT32)pF[0x2F], (UINT32)pF[0x30]); -*/ - pObj->info.num_flash = 2; - pObj->info.if_width = 32; - size = (UINT32)pF16[2*0x27]; - pObj->info.flashsize = pObj->info.num_flash; - for (i=0; i < size; i++) - pObj->info.flashsize *= 2; - - size = (UINT32)(pF16[2*0x2B] << 8 | pF16[2*0x2A]); - pObj->info.wbuf_size = pObj->info.num_flash; - for (i=0; i < size; i++) - pObj->info.wbuf_size *= 2; - - pObj->info.nblocks = (UINT32)(pF16[2*0x2E] << 8 | pF16[2*0x2D]) + 1; - pObj->info.blocksize = pObj->info.num_flash * ((UINT32)(pF16[2*0x30] << 8 | pF16[2*0x2F]) * 256); - - *pF = 0x00FF00FF; - - return 0; -} - -UINT32 cfi_block_is_locked(flash_t *pObj, UINT32 word_index) -{ - volatile UINT32 *pF; - UINT32 status, block_index, block_mask; - UINT32 error; - - pF = (UINT32*)pObj->pBase; - - if (word_index >= (pObj->info.flashsize/4)) - return CFI_ERR_INVPARAM; - - block_mask = ((pObj->info.nblocks-1) << 16); - block_index = word_index & block_mask; - - *pF = 0x00900090; - - error = ((UINT32)pF[block_index+2] & 0x00010001) != 0; - *pF = 0x00FF00FF; - - return error; -} - -UINT32 cfi_block_erase(flash_t *pObj, UINT32 word_index) -{ - volatile UINT32 *pF; - UINT32 status, block_index, block_mask; - UINT32 error; - - pF = (UINT32*)pObj->pBase; - - if (word_index >= (pObj->info.flashsize/4)) - return CFI_ERR_INVPARAM; - - block_mask = ((pObj->info.nblocks-1) << 16); - block_index = word_index & block_mask; - - pF[block_index] = 0x00200020; - pF[block_index] = 0x00D000D0; - - error = 0; - do - { - status = pF[block_index]; - - } while((status & SR_BIT_ISMS) != SR_BIT_ISMS); - - if (status & (SR_BIT_ECLBS | SR_BIT_VPENS | SR_BIT_DPS)) - { - error = CFI_ERR_DEV_FAIL | status; - } - - pF[block_index] = 0x00FF00FF; - - return error; -} - -UINT32 cfi_block_lock(flash_t *pObj, UINT32 word_index) -{ - volatile UINT32 *pF; - UINT32 status, block_index, block_mask; - UINT32 error; - - pF = (UINT32*)pObj->pBase; - - if (word_index >= (pObj->info.flashsize/4)) - return CFI_ERR_INVPARAM; - - block_mask = ((pObj->info.nblocks-1) << 16); - block_index = word_index & block_mask; - - pF[block_index] = 0x00600060; - pF[block_index] = 0x00010001; - - error = 0; - do - { - status = pF[block_index]; - - } while((status & SR_BIT_ISMS) != SR_BIT_ISMS); - - if (status & (SR_BIT_PSLBS | SR_BIT_VPENS | SR_BIT_ECLBS)) - { - error = CFI_ERR_DEV_FAIL | status; - } - - pF[block_index] = 0x00FF00FF; - - return error; -} - -UINT32 cfi_block_unlock(flash_t *pObj, UINT32 word_index) -{ - volatile UINT32 *pF; - UINT32 status, block_index, block_mask; - UINT32 error; - - pF = (UINT32*)pObj->pBase; - - if (word_index >= (pObj->info.flashsize/4)) - return CFI_ERR_INVPARAM; - - block_mask = ((pObj->info.nblocks-1) << 16); - block_index = word_index & block_mask; - - pF[block_index] = 0x00600060; - pF[block_index] = 0x00D000D0; - - error = 0; - do - { - status = pF[block_index]; - - } while((status & SR_BIT_ISMS) != SR_BIT_ISMS); - - if (status & (SR_BIT_PSLBS | SR_BIT_VPENS | SR_BIT_ECLBS)) - { - error = CFI_ERR_DEV_FAIL | status; - } - - pF[block_index] = 0x00FF00FF; - - return error; -} - -UINT32 cfi_program_single(flash_t *pObj, UINT32 word_index, UINT32 word) -{ - volatile UINT32 *pF; - UINT32 status, error; - - pF = (UINT32*)pObj->pBase; - - if (word_index >= (pObj->info.flashsize/4)) - return CFI_ERR_INVPARAM; - - pF[word_index] = 0x00400040; - pF[word_index] = word; - - error = 0; - do - { - status = pF[word_index]; - - } while((status & SR_BIT_ISMS) != SR_BIT_ISMS); - - if (status & (SR_BIT_PSLBS | SR_BIT_VPENS | SR_BIT_DPS)) - { - error = CFI_ERR_DEV_FAIL | status; - } - - pF[word_index] = 0x00FF00FF; - - return error; - -} - -UINT32 cfi_program_multi(flash_t *pObj, UINT32 word_index, UINT32 *pWords, UINT32 num_words) -{ - int i, j, k; - volatile UINT32 *pF; - UINT32 status, bcurr, bnext, block_mask, nblock_write, nbuf_write; - UINT32 error; - - pF = (UINT32*)pObj->pBase; - - if (word_index >= (pObj->info.flashsize/4)) - return CFI_ERR_INVPARAM; - - block_mask = ((pObj->info.nblocks-1) << 16); - - k = 0; - while(num_words) - { - - bcurr = word_index & block_mask; - bnext = bcurr + (1 << 16); - nblock_write = bnext - word_index; - if (nblock_write > num_words) - nblock_write = num_words; - - while(nblock_write) - { - error = 0; - pF[bcurr] = 0x00E800E8; - do - { - status = pF[bcurr]; - - } while((status & SR_BIT_ISMS) != SR_BIT_ISMS); - if (status & (SR_BIT_PSLBS | SR_BIT_VPENS | SR_BIT_DPS)) - { - error = CFI_ERR_DEV_FAIL | status; - break; - } - - nbuf_write = nblock_write; - if (nblock_write > pObj->info.wbuf_size/4) - nbuf_write = pObj->info.wbuf_size/4; - - pF[bcurr] = (nbuf_write-1) << 16 | (nbuf_write-1); - - for (j=0; j < nbuf_write; j++) - pF[word_index+j] = pWords[k++]; - - word_index += j; - nblock_write -= j; - num_words -= j; - - error = 0; - pF[bcurr] = 0x00D000D0; - do - { - status = pF[bcurr]; - - } while((status & SR_BIT_ISMS) != SR_BIT_ISMS); - if (status & (SR_BIT_PSLBS | SR_BIT_VPENS | SR_BIT_DPS)) - { - error = CFI_ERR_DEV_FAIL | status; - break; - } - - pF[bcurr] = 0x00FF00FF; - } - - if (IS_ERROR(error)) - { - pF[bcurr] = 0x00FF00FF; - break; - } - bcurr = bnext; - } - - return error; - -} - -UINT32 flash_find(flash_t *pObj, UINT32 base_addr) -{ - cfi_init(pObj, base_addr); - return cfi_find(pObj); -} - -UINT32 flash_erase(flash_t *pObj, UINT32 offset, UINT32 size) -{ - int i; - UINT32 offset_end, error; - - if (size % 4) - size = 4*(size/4 + 1); - - offset_end = offset + size; - - for (i=offset; i < offset_end; i += pObj->info.blocksize) - { - if (cfi_block_is_locked(pObj, i/4)) - { - error = cfi_block_unlock(pObj, i/4); - if (IS_ERROR(error)) - break; - } - error = cfi_block_erase(pObj, i/4); - if (IS_ERROR(error)) - break; - } - - return error; - -} - -UINT32 flash_program(flash_t *pObj, UINT32 offset, UINT8 *pData, UINT32 size) -{ - if (size % 4) - size = 4*(size/4 + 1); - - return cfi_program_multi(pObj, offset/4, (UINT32*)pData, size/4); -} - -UINT32 flash_verify(flash_t *pObj, UINT32 offset, UINT8 *pData, UINT32 size) -{ - int i; - UINT8 *pF; - - pF = (UINT8*)(pObj->pBase + offset); - - for (i=0; i < size; i++) - if (pF[i] != pData[i]) - return CFI_ERR_VFY_FAIL; - - return 0; -} - -UINT32 flash_get_blocknum_by_offset(flash_t *pObj, UINT32 offset) -{ - UINT32 blocknum; - - blocknum = offset/pObj->info.blocksize; - if (offset%pObj->info.blocksize) - blocknum++; - - return blocknum; -} - -UINT32 flash_get_offset_by_blocknum(flash_t *pObj, UINT32 blocknum) -{ - if (blocknum >= pObj->info.nblocks) - blocknum = pObj->info.nblocks - 1; - - return blocknum*pObj->info.blocksize; -} - -UINT32 flash_get_offset_blockaligned(flash_t *pObj, UINT32 offset) -{ - return flash_get_blocknum_by_offset(pObj, offset) * pObj->info.blocksize; -} - diff --git a/lib/CPUs/MIPS/bsp/examples/cfiflash.h b/lib/CPUs/MIPS/bsp/examples/cfiflash.h deleted file mode 100644 index 1233642..0000000 --- a/lib/CPUs/MIPS/bsp/examples/cfiflash.h +++ /dev/null @@ -1,58 +0,0 @@ -/************************************************************************/ -#ifndef CFIFLASH_H -#define CFIFLASH_H - -#include "libsys.h" - -#define SR_BIT_DPS 0x00020002 -#define SR_BIT_PSS 0x00040004 -#define SR_BIT_VPENS 0x00080008 -#define SR_BIT_PSLBS 0x00100010 -#define SR_BIT_ECLBS 0x00200020 -#define SR_BIT_ESS 0x00400040 -#define SR_BIT_ISMS 0x00800080 - -#define CFI_ERR_BASE (LSYS_ERR_BASE + 0x00100000) -#define CFI_ERR_GENERAL (CFI_ERR_BASE + 0) -#define CFI_ERR_NOTFOUND (CFI_ERR_BASE + 1) -#define CFI_ERR_INVPARAM (CFI_ERR_BASE + 2) -#define CFI_ERR_VFY_FAIL (CFI_ERR_BASE + 3) -#define CFI_ERR_DEV_FAIL (CFI_ERR_BASE + 0x10000000) - -typedef struct _sflash_info_t -{ - UINT32 flashsize; - UINT32 blocksize; - UINT32 nblocks; - UINT32 wbuf_size; - UINT32 if_width; - UINT32 num_flash; - -} flash_info_t; - -typedef struct _sflash_t -{ - void *pBase; - UINT32 eb; - flash_info_t info; - -} flash_t; - -void cfi_init(flash_t *pObj, UINT32 base_addr); -UINT32 cfi_find(flash_t *pObj); -UINT32 cfi_block_is_locked(flash_t *pObj, UINT32 word_index); -UINT32 cfi_block_erase(flash_t *pObj, UINT32 word_index); -UINT32 cfi_block_lock(flash_t *pObj, UINT32 word_index); -UINT32 cfi_block_unlock(flash_t *pObj, UINT32 word_index); -UINT32 cfi_program_single(flash_t *pObj, UINT32 word_index, UINT32 word); -UINT32 cfi_program_multi(flash_t *pObj, UINT32 word_index, UINT32 *pWords, UINT32 num_words); - -UINT32 flash_get_offset_by_blocknum(flash_t *pObj, UINT32 blocknum); -UINT32 flash_get_blocknum_by_offset(flash_t *pObj, UINT32 offset); -UINT32 flash_get_offset_blockaligned(flash_t *pObj, UINT32 offset); -UINT32 flash_find(flash_t *pObj, UINT32 base_addr); -UINT32 flash_erase(flash_t *pObj, UINT32 offset, UINT32 size); -UINT32 flash_program(flash_t *pObj, UINT32 offset, UINT8 *pData, UINT32 size); -UINT32 flash_verify(flash_t *pObj, UINT32 offset, UINT8 *pData, UINT32 size); - -#endif // CFIFLASH_H diff --git a/lib/CPUs/MIPS/bsp/examples/crc32.c b/lib/CPUs/MIPS/bsp/examples/crc32.c deleted file mode 100644 index 6f63429..0000000 --- a/lib/CPUs/MIPS/bsp/examples/crc32.c +++ /dev/null @@ -1,54 +0,0 @@ -#include - -unsigned long MakeCRC32(char *data, unsigned int len, unsigned int CRC) -{ - /* ======================================================================== - * Table of CRC-32's of all single-byte values (made by makecrc.c) - */ - unsigned long crc_32_tab[] = { - 0x00000000L, 0x77073096L, 0xee0e612cL, 0x990951baL, 0x076dc419L, 0x706af48fL, 0xe963a535L, 0x9e6495a3L, - 0x0edb8832L, 0x79dcb8a4L, 0xe0d5e91eL, 0x97d2d988L, 0x09b64c2bL, 0x7eb17cbdL, 0xe7b82d07L, 0x90bf1d91L, - 0x1db71064L, 0x6ab020f2L, 0xf3b97148L, 0x84be41deL, 0x1adad47dL, 0x6ddde4ebL, 0xf4d4b551L, 0x83d385c7L, - 0x136c9856L, 0x646ba8c0L, 0xfd62f97aL, 0x8a65c9ecL, 0x14015c4fL, 0x63066cd9L, 0xfa0f3d63L, 0x8d080df5L, - 0x3b6e20c8L, 0x4c69105eL, 0xd56041e4L, 0xa2677172L, 0x3c03e4d1L, 0x4b04d447L, 0xd20d85fdL, 0xa50ab56bL, - 0x35b5a8faL, 0x42b2986cL, 0xdbbbc9d6L, 0xacbcf940L, 0x32d86ce3L, 0x45df5c75L, 0xdcd60dcfL, 0xabd13d59L, - 0x26d930acL, 0x51de003aL, 0xc8d75180L, 0xbfd06116L, 0x21b4f4b5L, 0x56b3c423L, 0xcfba9599L, 0xb8bda50fL, - 0x2802b89eL, 0x5f058808L, 0xc60cd9b2L, 0xb10be924L, 0x2f6f7c87L, 0x58684c11L, 0xc1611dabL, 0xb6662d3dL, - 0x76dc4190L, 0x01db7106L, 0x98d220bcL, 0xefd5102aL, 0x71b18589L, 0x06b6b51fL, 0x9fbfe4a5L, 0xe8b8d433L, - 0x7807c9a2L, 0x0f00f934L, 0x9609a88eL, 0xe10e9818L, 0x7f6a0dbbL, 0x086d3d2dL, 0x91646c97L, 0xe6635c01L, - 0x6b6b51f4L, 0x1c6c6162L, 0x856530d8L, 0xf262004eL, 0x6c0695edL, 0x1b01a57bL, 0x8208f4c1L, 0xf50fc457L, - 0x65b0d9c6L, 0x12b7e950L, 0x8bbeb8eaL, 0xfcb9887cL, 0x62dd1ddfL, 0x15da2d49L, 0x8cd37cf3L, 0xfbd44c65L, - 0x4db26158L, 0x3ab551ceL, 0xa3bc0074L, 0xd4bb30e2L, 0x4adfa541L, 0x3dd895d7L, 0xa4d1c46dL, 0xd3d6f4fbL, - 0x4369e96aL, 0x346ed9fcL, 0xad678846L, 0xda60b8d0L, 0x44042d73L, 0x33031de5L, 0xaa0a4c5fL, 0xdd0d7cc9L, - 0x5005713cL, 0x270241aaL, 0xbe0b1010L, 0xc90c2086L, 0x5768b525L, 0x206f85b3L, 0xb966d409L, 0xce61e49fL, - 0x5edef90eL, 0x29d9c998L, 0xb0d09822L, 0xc7d7a8b4L, 0x59b33d17L, 0x2eb40d81L, 0xb7bd5c3bL, 0xc0ba6cadL, - 0xedb88320L, 0x9abfb3b6L, 0x03b6e20cL, 0x74b1d29aL, 0xead54739L, 0x9dd277afL, 0x04db2615L, 0x73dc1683L, - 0xe3630b12L, 0x94643b84L, 0x0d6d6a3eL, 0x7a6a5aa8L, 0xe40ecf0bL, 0x9309ff9dL, 0x0a00ae27L, 0x7d079eb1L, - 0xf00f9344L, 0x8708a3d2L, 0x1e01f268L, 0x6906c2feL, 0xf762575dL, 0x806567cbL, 0x196c3671L, 0x6e6b06e7L, - 0xfed41b76L, 0x89d32be0L, 0x10da7a5aL, 0x67dd4accL, 0xf9b9df6fL, 0x8ebeeff9L, 0x17b7be43L, 0x60b08ed5L, - 0xd6d6a3e8L, 0xa1d1937eL, 0x38d8c2c4L, 0x4fdff252L, 0xd1bb67f1L, 0xa6bc5767L, 0x3fb506ddL, 0x48b2364bL, - 0xd80d2bdaL, 0xaf0a1b4cL, 0x36034af6L, 0x41047a60L, 0xdf60efc3L, 0xa867df55L, 0x316e8eefL, 0x4669be79L, - 0xcb61b38cL, 0xbc66831aL, 0x256fd2a0L, 0x5268e236L, 0xcc0c7795L, 0xbb0b4703L, 0x220216b9L, 0x5505262fL, - 0xc5ba3bbeL, 0xb2bd0b28L, 0x2bb45a92L, 0x5cb36a04L, 0xc2d7ffa7L, 0xb5d0cf31L, 0x2cd99e8bL, 0x5bdeae1dL, - 0x9b64c2b0L, 0xec63f226L, 0x756aa39cL, 0x026d930aL, 0x9c0906a9L, 0xeb0e363fL, 0x72076785L, 0x05005713L, - 0x95bf4a82L, 0xe2b87a14L, 0x7bb12baeL, 0x0cb61b38L, 0x92d28e9bL, 0xe5d5be0dL, 0x7cdcefb7L, 0x0bdbdf21L, - 0x86d3d2d4L, 0xf1d4e242L, 0x68ddb3f8L, 0x1fda836eL, 0x81be16cdL, 0xf6b9265bL, 0x6fb077e1L, 0x18b74777L, - 0x88085ae6L, 0xff0f6a70L, 0x66063bcaL, 0x11010b5cL, 0x8f659effL, 0xf862ae69L, 0x616bffd3L, 0x166ccf45L, - 0xa00ae278L, 0xd70dd2eeL, 0x4e048354L, 0x3903b3c2L, 0xa7672661L, 0xd06016f7L, 0x4969474dL, 0x3e6e77dbL, - 0xaed16a4aL, 0xd9d65adcL, 0x40df0b66L, 0x37d83bf0L, 0xa9bcae53L, 0xdebb9ec5L, 0x47b2cf7fL, 0x30b5ffe9L, - 0xbdbdf21cL, 0xcabac28aL, 0x53b39330L, 0x24b4a3a6L, 0xbad03605L, 0xcdd70693L, 0x54de5729L, 0x23d967bfL, - 0xb3667a2eL, 0xc4614ab8L, 0x5d681b02L, 0x2a6f2b94L, 0xb40bbe37L, 0xc30c8ea1L, 0x5a05df1bL, 0x2d02ef8dL - }; - - if (data == NULL) - return 0; - - CRC = ~CRC; - while (len --) - { - CRC = crc_32_tab[((unsigned char) CRC ^ *data) & 0xFF] ^ (CRC >> 8); - data ++; - } - - return ~CRC; -} diff --git a/lib/CPUs/MIPS/bsp/examples/crc32.h b/lib/CPUs/MIPS/bsp/examples/crc32.h deleted file mode 100644 index 04687b0..0000000 --- a/lib/CPUs/MIPS/bsp/examples/crc32.h +++ /dev/null @@ -1,13 +0,0 @@ -// CRC32 function -// To create a CRC from a new buffer, use this: -// crc = MakeCRC32(mydata, data_len, 0); -// If you need to continue the CRC (e.g. your data is in multiple buffers), -// continue like this: -// crc = MakeCRC32(moredata, more_len, crc); -// -// Your desired CRC should be the complement of the CRC generated by -// MakeCRC32: -// desired = crc -// desired - crc = 0 - -unsigned long MakeCRC32(char *data, unsigned int len, unsigned long CRC); diff --git a/lib/CPUs/MIPS/bsp/examples/cubic.c b/lib/CPUs/MIPS/bsp/examples/cubic.c deleted file mode 100644 index 7740eb2..0000000 --- a/lib/CPUs/MIPS/bsp/examples/cubic.c +++ /dev/null @@ -1,64 +0,0 @@ -/* +++Date last modified: 05-Jul-1997 */ - -/* -** CUBIC.C - Solve a cubic polynomial -** public domain by Ross Cottrell -*/ - -#include -#include -#include "snipmath.h" - -void SolveCubic(double a, - double b, - double c, - double d, - int *solutions, - double *x) -{ - long double a1 = b/a, a2 = c/a, a3 = d/a; - long double Q = (a1*a1 - 3.0*a2)/9.0; - long double R = (2.0*a1*a1*a1 - 9.0*a1*a2 + 27.0*a3)/54.0; - double R2_Q3 = R*R - Q*Q*Q; - - double theta; - - if (R2_Q3 <= 0) - { - *solutions = 3; - theta = acos(R/sqrt(Q*Q*Q)); - x[0] = -2.0*sqrt(Q)*cos(theta/3.0) - a1/3.0; - x[1] = -2.0*sqrt(Q)*cos((theta+2.0*PI)/3.0) - a1/3.0; - x[2] = -2.0*sqrt(Q)*cos((theta+4.0*PI)/3.0) - a1/3.0; - } - else - { - *solutions = 1; - x[0] = pow(sqrt(R2_Q3)+fabs(R), 1/3.0); - x[0] += Q/x[0]; - x[0] *= (R < 0.0) ? 1 : -1; - x[0] -= a1/3.0; - } -} - -#ifdef TEST - -int main(void) -{ - double a1 = 1.0, b1 = -10.5, c1 = 32.0, d1 = -30.0; - double a2 = 1.0, b2 = -4.5, c2 = 17.0, d2 = -30.0; - double x[3]; - int solutions; - - SolveCubic(a1, b1, c1, d1, &solutions, x); - - /* should get 3 solutions: 2, 6 & 2.5 */ - - SolveCubic(a2, b2, c2, d2, &solutions, x); - - /* should get 1 solution: 2.5 */ - - return 0; -} - -#endif /* TEST */ diff --git a/lib/CPUs/MIPS/bsp/examples/dbg.c b/lib/CPUs/MIPS/bsp/examples/dbg.c deleted file mode 100644 index fc5a429..0000000 --- a/lib/CPUs/MIPS/bsp/examples/dbg.c +++ /dev/null @@ -1,375 +0,0 @@ -#include -#include -#include -#include "irq.h" -#include "libsys.h" -#include "mips_dis.h" - -#define MAX_USER_BP 16 -#define BP_MASK_ID 0x00FFF -#define BP_MASK_TYPE 0xFF000 - -#define BP_GET_ID(bp) ((bp >> 6) & 0xFFF) - -#define BP_USER_BASE 0x10000 -#define BP_USER(id) (((BP_USER_BASE + id) << 6) | 0x0D) - -#define BP_MGMT_BASE_SS 0x20000 -#define BP_MGMT_SS(id) (((BP_MGMT_BASE_SS + id) << 6) | 0x0D) - -#define BP_MGMT_BASE_RU 0x30000 -#define BP_MGMT_RU(id) (((BP_MGMT_BASE_RU + id) << 6) | 0x0D) - -static char g_buf[80]; - -typedef struct _sbp_t -{ - UINT32 *pAddr; - UINT32 instr; -} bp_t; - -static EXCEPTION_CONTEXT xcp_last; -static bp_t user_bp[MAX_USER_BP]; -static bp_t mgmt_bp_ss[2]; -static bp_t mgmt_bp_ru[2]; -static int g_is_ss; -static int g_bp_index; - -int IsBreak(UINT32 instr) -{ - return ((instr & 0xFC00003F) == 0x0000000D); -} - -UINT32 BreakGetType(UINT32 instr) -{ - return (instr >> 6) & BP_MASK_TYPE; -} - -char* reg_changed(UINT32 reg1, UINT32 reg2) -{ - static char chg_str[2] = {0}; - - if (reg1 != reg2) - chg_str[0] = '*'; - else - chg_str[0] = ' '; - - return chg_str; -} - -void dbg_handler(struct xcptcontext * xcp) -{ - - UINT32 bp_addr, bp_index = 0, branch_addr, reg, result, bp_type; - int junk, i, leave_isr, is_branch_shadow, is_user_bp; - UINT32 volatile *pBtn = (UINT32*)SYS_GPIO0; - UINT32 *pInstr, *pAddr_curr, *pAddr_prev, *pAddr_next; - - sputs("\n"); - PRINT_REG_CHG(" Status : ", xcp->sr, reg_changed(xcp->sr, xcp_last.sr)); - PRINT_REG_CHG(" Cause : ", xcp->cr, reg_changed(xcp->cr, xcp_last.cr)); - PRINT_REG_CHG(" EPC : ", xcp->epc, reg_changed(xcp->epc, xcp_last.epc)); - PRINT_REG_CHG("BadAddr : ", xcp->baddr, reg_changed(xcp->baddr, xcp_last.baddr)); - sputs("\n"); - PRINT_REG_CHG(" MDLO : ", xcp->mdlo, reg_changed(xcp->mdlo, xcp_last.mdlo)); - PRINT_REG_CHG(" MDHI : ", xcp->mdhi, reg_changed(xcp->mdhi, xcp_last.mdhi)); - - sputs("\n"); - - sputs("Registers:\n"); - PRINT_REG_CHG(" 0 (ze) : ", xcp->regs[0], reg_changed(xcp->regs[0], xcp_last.regs[0])); - PRINT_REG_CHG(" 1 (at) : ", xcp->regs[1], reg_changed(xcp->regs[1], xcp_last.regs[1])); - PRINT_REG_CHG(" 2 (v0) : ", xcp->regs[2], reg_changed(xcp->regs[2], xcp_last.regs[2])); - PRINT_REG_CHG(" 3 (v1) : ", xcp->regs[3], reg_changed(xcp->regs[3], xcp_last.regs[3])); - sputs("\n"); - PRINT_REG_CHG(" 4 (a0) : ", xcp->regs[4], reg_changed(xcp->regs[4], xcp_last.regs[4])); - PRINT_REG_CHG(" 5 (a1) : ", xcp->regs[5], reg_changed(xcp->regs[5], xcp_last.regs[5])); - PRINT_REG_CHG(" 6 (a2) : ", xcp->regs[6], reg_changed(xcp->regs[6], xcp_last.regs[6])); - PRINT_REG_CHG(" 7 (a3) : ", xcp->regs[7], reg_changed(xcp->regs[7], xcp_last.regs[7])); - sputs("\n"); - PRINT_REG_CHG(" 8 (t0) : ", xcp->regs[8], reg_changed(xcp->regs[8], xcp_last.regs[8])); - PRINT_REG_CHG(" 9 (t1) : ", xcp->regs[9], reg_changed(xcp->regs[9], xcp_last.regs[9])); - PRINT_REG_CHG("10 (t2) : ", xcp->regs[10], reg_changed(xcp->regs[10], xcp_last.regs[10])); - PRINT_REG_CHG("11 (t3) : ", xcp->regs[11], reg_changed(xcp->regs[11], xcp_last.regs[11])); - sputs("\n"); - PRINT_REG_CHG("12 (t4) : ", xcp->regs[12], reg_changed(xcp->regs[12], xcp_last.regs[12])); - PRINT_REG_CHG("13 (t5) : ", xcp->regs[13], reg_changed(xcp->regs[13], xcp_last.regs[13])); - PRINT_REG_CHG("14 (t6) : ", xcp->regs[14], reg_changed(xcp->regs[14], xcp_last.regs[14])); - PRINT_REG_CHG("15 (t7) : ", xcp->regs[15], reg_changed(xcp->regs[15], xcp_last.regs[15])); - sputs("\n"); - PRINT_REG_CHG("16 (s0) : ", xcp->regs[16], reg_changed(xcp->regs[16], xcp_last.regs[16])); - PRINT_REG_CHG("17 (s1) : ", xcp->regs[17], reg_changed(xcp->regs[17], xcp_last.regs[17])); - PRINT_REG_CHG("18 (s2) : ", xcp->regs[18], reg_changed(xcp->regs[18], xcp_last.regs[18])); - PRINT_REG_CHG("19 (s3) : ", xcp->regs[19], reg_changed(xcp->regs[19], xcp_last.regs[19])); - sputs("\n"); - PRINT_REG_CHG("20 (s4) : ", xcp->regs[20], reg_changed(xcp->regs[20], xcp_last.regs[20])); - PRINT_REG_CHG("21 (s5) : ", xcp->regs[21], reg_changed(xcp->regs[21], xcp_last.regs[21])); - PRINT_REG_CHG("22 (s6) : ", xcp->regs[22], reg_changed(xcp->regs[22], xcp_last.regs[22])); - PRINT_REG_CHG("23 (s7) : ", xcp->regs[23], reg_changed(xcp->regs[23], xcp_last.regs[23])); - sputs("\n"); - PRINT_REG_CHG("24 (s8) : ", xcp->regs[24], reg_changed(xcp->regs[24], xcp_last.regs[24])); - PRINT_REG_CHG("25 (s9) : ", xcp->regs[25], reg_changed(xcp->regs[25], xcp_last.regs[25])); - PRINT_REG_CHG("26 (k0) : ", xcp->regs[26], reg_changed(xcp->regs[26], xcp_last.regs[26])); - PRINT_REG_CHG("27 (k1) : ", xcp->regs[27], reg_changed(xcp->regs[27], xcp_last.regs[27])); - sputs("\n"); - PRINT_REG_CHG("28 (gp) : ", xcp->regs[28], reg_changed(xcp->regs[28], xcp_last.regs[28])); - PRINT_REG_CHG("29 (sp) : ", xcp->regs[29], reg_changed(xcp->regs[29], xcp_last.regs[29])); - PRINT_REG_CHG("30 (fp) : ", xcp->regs[30], reg_changed(xcp->regs[30], xcp_last.regs[30])); - PRINT_REG_CHG("31 (ra) : ", xcp->regs[31], reg_changed(xcp->regs[31], xcp_last.regs[31])); - sputs("\n"); - sputs("\n"); - - memcpy(&xcp_last, xcp, sizeof(EXCEPTION_CONTEXT)); - - is_user_bp = 0; - pAddr_curr = (UINT32*)xcp->epc; - is_branch_shadow = ((xcp->cr & 0x80000000) == 0x80000000); - if (is_branch_shadow) - pAddr_curr++; - - pAddr_prev = pAddr_curr - 1; - pAddr_next = pAddr_curr + 1; - - if (IsBreak(*pAddr_curr)) - { - bp_type = BreakGetType(*pAddr_curr); - - switch (bp_type) - { - case BP_MGMT_BASE_SS: - - // Restore original instructions after single-step -// sputs("1. Restore after single-step at ");print_word((long)mgmt_bp_ss[0].pAddr);sputs("\n"); - *(mgmt_bp_ss[0].pAddr) = mgmt_bp_ss[0].instr; - ICACHE_invalidate_at(mgmt_bp_ss[0].pAddr); - if (mgmt_bp_ss[1].pAddr) - { -// sputs("2. Restore after single-step at ");print_word((long)mgmt_bp_ss[1].pAddr);sputs("\n"); - *(mgmt_bp_ss[1].pAddr) = mgmt_bp_ss[1].instr; - ICACHE_invalidate_at(mgmt_bp_ss[1].pAddr); - } - - break; - - case BP_MGMT_BASE_RU: - - bp_index = BP_GET_ID(*pAddr_curr); -// sputs("Restore user break at ");print_word((long)user_bp[bp_index].pAddr);sputs("\n"); - - *(user_bp[bp_index].pAddr) = BP_USER(bp_index); - ICACHE_invalidate_at(user_bp[bp_index].pAddr); - - *(mgmt_bp_ru[0].pAddr) = mgmt_bp_ru[0].instr; - ICACHE_invalidate_at(mgmt_bp_ru[0].pAddr); -// sputs("1. Restore after RU at ");print_word((long)mgmt_bp_ru[0].pAddr);sputs("\n"); - if (mgmt_bp_ru[1].pAddr) - { - *(mgmt_bp_ru[1].pAddr) = mgmt_bp_ru[1].instr; - ICACHE_invalidate_at(mgmt_bp_ru[1].pAddr); -// sputs("2. Restore after RU at ");print_word((long)mgmt_bp_ru[1].pAddr);sputs("\n"); - } - if (!g_is_ss) - return; - - break; - - case BP_USER_BASE: - - is_user_bp = 1; - bp_index = BP_GET_ID(*pAddr_curr); -// sputs("Restore instruction at ");print_word((long)user_bp[bp_index].pAddr);sputs("\n"); - *(user_bp[bp_index].pAddr) = user_bp[bp_index].instr; - ICACHE_invalidate_at(user_bp[bp_index].pAddr); - break; - - default: -// sputs("Found ordinary break at ");print_word((long)pAddr_curr);sputs("\n"); - break; - - } - } - - pInstr = pAddr_prev; - // Disassemble instructions - for (i=0; i < 3; i++) - { - print_word((long)pInstr); - if (IsBreak(*pInstr) && (BreakGetType(*pInstr) == BP_USER_BASE)) - { - tdisasm(g_buf, (long)user_bp[BP_GET_ID(*pInstr)].pAddr, user_bp[BP_GET_ID(*pInstr)].instr, 0, &junk, &junk, &junk); - sputs(": b "); - } - else - { - tdisasm(g_buf, (long)pInstr, *pInstr, 0, &junk, &junk, &junk); - if (pInstr == pAddr_curr) - if (is_user_bp == 1) - sputs(": b-> "); - else - sputs(": -> "); - else - sputs(": "); - } - sputs(g_buf); - sputs("\n"); - pInstr++; - } - - if (is_user_bp) - { - // Save original instruction - mgmt_bp_ru[0].pAddr = pAddr_next; - mgmt_bp_ru[0].instr = *(mgmt_bp_ru[0].pAddr); - // Replace instruction with managment breakpoint - *(mgmt_bp_ru[0].pAddr) = BP_MGMT_RU(bp_index); - ICACHE_invalidate_at(mgmt_bp_ru[0].pAddr); - mgmt_bp_ru[1].pAddr = NULL; - mgmt_bp_ru[1].pAddr = 0; -// sputs("1. Insert RU-break at ");print_word((long)mgmt_bp_ru[0].pAddr);sputs("\n"); - - // We have two possible management breaks, if previous instruction was branch or jump - if (is_branch_shadow) - { - result = tdisasm(g_buf, (long)pAddr_prev, *pAddr_prev, 0, &junk, &branch_addr, ®); - // Is jump target stored in register - if (result == 3) - { - branch_addr = xcp->regs[reg&0x1F]; - } - // Save original instruction - mgmt_bp_ru[1].pAddr = (UINT32*)branch_addr; - mgmt_bp_ru[1].instr = *(mgmt_bp_ru[1].pAddr); - // Replace instruction with managment breakpoint - *(mgmt_bp_ru[1].pAddr) = BP_MGMT_RU(bp_index); - ICACHE_invalidate_at(mgmt_bp_ru[1].pAddr); -// sputs("2. Insert RU-break at ");print_word((long)mgmt_bp_ru[1].pAddr);sputs("\n"); - } - } - - do - { - leave_isr = 0; - switch(_getchar()) - { - case 'g': - leave_isr = 1; - g_is_ss = 0; - if (IsBreak(*pAddr_curr)) - { - if (BreakGetType(*pAddr_curr) != BP_USER_BASE) - { - xcp->epc += 4; // Skip ordinary program breaks - } - } - break; - - case 'b': - printf("Enter breakpoint: "); - scanf("%x", &bp_addr); - printf("Insert breakpoint at %.8X\n", bp_addr); - user_bp[g_bp_index].pAddr = (UINT32*)bp_addr; - user_bp[g_bp_index].instr = *(user_bp[g_bp_index].pAddr); - *(user_bp[g_bp_index].pAddr) = BP_USER(g_bp_index); - - tdisasm(g_buf, (long)user_bp[g_bp_index].pAddr, user_bp[g_bp_index].instr, 0, &junk, &junk, &junk); - print_word((long)user_bp[g_bp_index].pAddr);sputs(": b ");sputs(g_buf);sputs("\n"); - ICACHE_invalidate_at(user_bp[g_bp_index].pAddr); - g_bp_index++; - break; - - case 's': - g_is_ss = 1; - leave_isr = 1; - // Don't overwrite RU breaks -// printf("is_user_bp = %d, IsBreak = %d, pAddr_curr = %08X, *pAddr_curr = %08X\n", is_user_bp, IsBreak(*pAddr_curr), pAddr_curr, *pAddr_curr); - - if (is_user_bp) - break; - - // Don't overwrite user breaks - if (IsBreak(*pAddr_curr)) - { - if (BreakGetType(*pAddr_curr) == BP_USER_BASE) - { - break; - } - else - { - xcp->epc += 4; // Skip ordinary program breaks - } - } - // Save original instruction - mgmt_bp_ss[0].pAddr = pAddr_next; - mgmt_bp_ss[0].instr = *(mgmt_bp_ss[0].pAddr); - // Replace instruction with managment breakpoint - *(mgmt_bp_ss[0].pAddr) = BP_MGMT_SS(1); - ICACHE_invalidate_at(mgmt_bp_ss[0].pAddr); - mgmt_bp_ss[1].pAddr = NULL; - mgmt_bp_ss[1].pAddr = 0; - // We have two possible management breaks, if previous instruction was branch or jump - if (is_branch_shadow) - { - result = tdisasm(g_buf, (long)pAddr_prev, *pAddr_prev, 0, &junk, &branch_addr, ®); - // Is jump target stored in register - if (result == 3) - { - branch_addr = xcp->regs[reg&0x1F]; - } - // Save original instruction - mgmt_bp_ss[1].pAddr = (UINT32*)branch_addr; - mgmt_bp_ss[1].instr = *(mgmt_bp_ss[1].pAddr); - // Replace instruction with managment breakpoint - *(mgmt_bp_ss[1].pAddr) = BP_MGMT_SS(2); - ICACHE_invalidate_at(mgmt_bp_ss[1].pAddr); - } - break; - - case 'P': - g_is_ss = 1; - leave_isr = 1; - // Don't overwrite RU breaks - if (is_user_bp) - break; - // Don't overwrite user breaks - if (IsBreak(*pAddr_curr) && (BreakGetType(*pAddr_curr) == BP_USER_BASE)) - break; - - // Save original instruction - mgmt_bp_ss[0].pAddr = (UINT32*)xcp->regs[0x1F]; - mgmt_bp_ss[0].instr = *(mgmt_bp_ss[0].pAddr); - // Replace instruction with managment breakpoint - *(mgmt_bp_ss[0].pAddr) = BP_MGMT_SS(1); - ICACHE_invalidate_at(mgmt_bp_ss[0].pAddr); - mgmt_bp_ss[1].pAddr = NULL; - mgmt_bp_ss[1].pAddr = 0; - break; - - default: - break; - } - } while (!leave_isr); - -} - -void debug_int(struct xcptcontext * xcp) -{ - dbg_handler(xcp); - -} - -int debug_break(struct xcptcontext * xcp) -{ - dbg_handler(xcp); - return 0; - -} - -void dbg_init(void) -{ - memset(&xcp_last, 0, sizeof(EXCEPTION_CONTEXT)); - interrupt_register(2, debug_int); - interrupt_enable(2); - - xcpt_register(Bp, debug_break); -} - diff --git a/lib/CPUs/MIPS/bsp/examples/delay_mips.c b/lib/CPUs/MIPS/bsp/examples/delay_mips.c deleted file mode 100644 index 133a176..0000000 --- a/lib/CPUs/MIPS/bsp/examples/delay_mips.c +++ /dev/null @@ -1,15 +0,0 @@ -// MIPS delay. - -void __inline__ delay(int loops) -{ - __asm - ( - ".set noreorder\n" - "1:bnez %[loops], 1b\n" - "addiu %[loops], -1\n" - ".set reorder\n" - : - : [loops] "r" (loops) - ); -} - diff --git a/lib/CPUs/MIPS/bsp/examples/demo.c b/lib/CPUs/MIPS/bsp/examples/demo.c deleted file mode 100644 index e3fc38a..0000000 --- a/lib/CPUs/MIPS/bsp/examples/demo.c +++ /dev/null @@ -1,67 +0,0 @@ -/* -* Byte-oriented AES-256 implementation. -* All lookup tables replaced with 'on the fly' calculations. -* -* Copyright (c) 2007 Ilya O. Levin, http://www.literatecode.com -* -* Permission to use, copy, modify, and distribute this software for any -* purpose with or without fee is hereby granted, provided that the above -* copyright notice and this permission notice appear in all copies. -* -* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -*/ -#include -#include -#include -#include -#include -#include "aes256.h" - -#define DUMP(s, i, buf, sz) {printf(s); \ - for (i = 0; i < (sz);i++) \ - printf("%02x ", buf[i]); \ - printf("\n");} - - -int main (int argc, char *argv[]) -{ - aes256_context ctx; - uint8_t key[32]; - uint8_t buf[16], i; - long start, end, j; - - /* put a test vector */ - for (i = 0; i < sizeof(buf);i++) buf[i] = i * 16 + i; - for (i = 0; i < sizeof(key);i++) key[i] = i; - - DUMP("txt: ", i, buf, sizeof(buf)); - DUMP("key: ", i, key, sizeof(key)); - printf("---\n"); - - aes256_init(&ctx, key); - start = clock(); - for (j=0; j < 1000; j++) - { - aes256_encrypt_ecb(&ctx, buf); - } - end = clock(); - - printf("Speed %f blocks/s\n", (float)j/((float)(end-start)/CLOCKS_PER_SEC)); - - DUMP("enc: ", i, buf, sizeof(buf)); - printf("tst: 8e a2 b7 ca 51 67 45 bf ea fc 49 90 4b 49 60 89\n"); - - aes256_init(&ctx, key); - aes256_decrypt_ecb(&ctx, buf); - DUMP("dec: ", i, buf, sizeof(buf)); - - aes256_done(&ctx); - - return 0; -} /* main */ diff --git a/lib/CPUs/MIPS/bsp/examples/dhry.h b/lib/CPUs/MIPS/bsp/examples/dhry.h deleted file mode 100644 index c8d8f0a..0000000 --- a/lib/CPUs/MIPS/bsp/examples/dhry.h +++ /dev/null @@ -1,430 +0,0 @@ -/* - **************************************************************************** - * - * "DHRYSTONE" Benchmark Program - * ----------------------------- - * - * Version: C, Version 2.1 - * - * File: dhry.h (part 1 of 3) - * - * Date: May 25, 1988 - * - * Author: Reinhold P. Weicker - * Siemens AG, E STE 35 - * Postfach 3240 - * 8520 Erlangen - * Germany (West) - * Phone: [xxx-49]-9131-7-20330 - * (8-17 Central European Time) - * Usenet: ..!mcvax!unido!estevax!weicker - * - * Original Version (in Ada) published in - * "Communications of the ACM" vol. 27., no. 10 (Oct. 1984), - * pp. 1013 - 1030, together with the statistics - * on which the distribution of statements etc. is based. - * - * In this C version, the following C library functions are used: - * - strcpy, strcmp (inside the measurement loop) - * - printf, scanf (outside the measurement loop) - * In addition, Berkeley UNIX system calls "times ()" or "time ()" - * are used for execution time measurement. For measurements - * on other systems, these calls have to be changed. - * - * Collection of Results: - * Reinhold Weicker (address see above) and - * - * Rick Richardson - * PC Research. Inc. - * 94 Apple Orchard Drive - * Tinton Falls, NJ 07724 - * Phone: (201) 389-8963 (9-17 EST) - * Usenet: ...!uunet!pcrat!rick - * - * Please send results to Rick Richardson and/or Reinhold Weicker. - * Complete information should be given on hardware and software used. - * Hardware information includes: Machine type, CPU, type and size - * of caches; for microprocessors: clock frequency, memory speed - * (number of wait states). - * Software information includes: Compiler (and runtime library) - * manufacturer and version, compilation switches, OS version. - * The Operating System version may give an indication about the - * compiler; Dhrystone itself performs no OS calls in the measurement loop. - * - * The complete output generated by the program should be mailed - * such that at least some checks for correctness can be made. - * - *************************************************************************** - * - * History: This version C/2.1 has been made for two reasons: - * - * 1) There is an obvious need for a common C version of - * Dhrystone, since C is at present the most popular system - * programming language for the class of processors - * (microcomputers, minicomputers) where Dhrystone is used most. - * There should be, as far as possible, only one C version of - * Dhrystone such that results can be compared without - * restrictions. In the past, the C versions distributed - * by Rick Richardson (Version 1.1) and by Reinhold Weicker - * had small (though not significant) differences. - * - * 2) As far as it is possible without changes to the Dhrystone - * statistics, optimizing compilers should be prevented from - * removing significant statements. - * - * This C version has been developed in cooperation with - * Rick Richardson (Tinton Falls, NJ), it incorporates many - * ideas from the "Version 1.1" distributed previously by - * him over the UNIX network Usenet. - * I also thank Chaim Benedelac (National Semiconductor), - * David Ditzel (SUN), Earl Killian and John Mashey (MIPS), - * Alan Smith and Rafael Saavedra-Barrera (UC at Berkeley) - * for their help with comments on earlier versions of the - * benchmark. - * - * Changes: In the initialization part, this version follows mostly - * Rick Richardson's version distributed via Usenet, not the - * version distributed earlier via floppy disk by Reinhold Weicker. - * As a concession to older compilers, names have been made - * unique within the first 8 characters. - * Inside the measurement loop, this version follows the - * version previously distributed by Reinhold Weicker. - * - * At several places in the benchmark, code has been added, - * but within the measurement loop only in branches that - * are not executed. The intention is that optimizing compilers - * should be prevented from moving code out of the measurement - * loop, or from removing code altogether. Since the statements - * that are executed within the measurement loop have NOT been - * changed, the numbers defining the "Dhrystone distribution" - * (distribution of statements, operand types and locality) - * still hold. Except for sophisticated optimizing compilers, - * execution times for this version should be the same as - * for previous versions. - * - * Since it has proven difficult to subtract the time for the - * measurement loop overhead in a correct way, the loop check - * has been made a part of the benchmark. This does have - * an impact - though a very minor one - on the distribution - * statistics which have been updated for this version. - * - * All changes within the measurement loop are described - * and discussed in the companion paper "Rationale for - * Dhrystone version 2". - * - * Because of the self-imposed limitation that the order and - * distribution of the executed statements should not be - * changed, there are still cases where optimizing compilers - * may not generate code for some statements. To a certain - * degree, this is unavoidable for small synthetic benchmarks. - * Users of the benchmark are advised to check code listings - * whether code is generated for all statements of Dhrystone. - * - * Version 2.1 is identical to version 2.0 distributed via - * the UNIX network Usenet in March 1988 except that it corrects - * some minor deficiencies that were found by users of version 2.0. - * The only change within the measurement loop is that a - * non-executed "else" part was added to the "if" statement in - * Func_3, and a non-executed "else" part removed from Proc_3. - * - *************************************************************************** - * - * Defines: The following "Defines" are possible: - * -DREG=register (default: Not defined) - * As an approximation to what an average C programmer - * might do, the "register" storage class is applied - * (if enabled by -DREG=register) - * - for local variables, if they are used (dynamically) - * five or more times - * - for parameters if they are used (dynamically) - * six or more times - * Note that an optimal "register" strategy is - * compiler-dependent, and that "register" declarations - * do not necessarily lead to faster execution. - * -DNOSTRUCTASSIGN (default: Not defined) - * Define if the C compiler does not support - * assignment of structures. - * -DNOENUMS (default: Not defined) - * Define if the C compiler does not support - * enumeration types. - * -DTIMES (default) - * -DTIME - * The "times" function of UNIX (returning process times) - * or the "time" function (returning wallclock time) - * is used for measurement. - * For single user machines, "time ()" is adequate. For - * multi-user machines where you cannot get single-user - * access, use the "times ()" function. If you have - * neither, use a stopwatch in the dead of night. - * "printf"s are provided marking the points "Start Timer" - * and "Stop Timer". DO NOT use the UNIX "time(1)" - * command, as this will measure the total time to - * run this program, which will (erroneously) include - * the time to allocate storage (malloc) and to perform - * the initialization. - * -DHZ=nnn - * In Berkeley UNIX, the function "times" returns process - * time in 1/HZ seconds, with HZ = 60 for most systems. - * CHECK YOUR SYSTEM DESCRIPTION BEFORE YOU JUST APPLY - * A VALUE. - * - *************************************************************************** - * - * Compilation model and measurement (IMPORTANT): - * - * This C version of Dhrystone consists of three files: - * - dhry.h (this file, containing global definitions and comments) - * - dhry_1.c (containing the code corresponding to Ada package Pack_1) - * - dhry_2.c (containing the code corresponding to Ada package Pack_2) - * - * The following "ground rules" apply for measurements: - * - Separate compilation - * - No procedure merging - * - Otherwise, compiler optimizations are allowed but should be indicated - * - Default results are those without register declarations - * See the companion paper "Rationale for Dhrystone Version 2" for a more - * detailed discussion of these ground rules. - * - * For 16-Bit processors (e.g. 80186, 80286), times for all compilation - * models ("small", "medium", "large" etc.) should be given if possible, - * together with a definition of these models for the compiler system used. - * - ************************************************************************** - * - * Dhrystone (C version) statistics: - * - * [Comment from the first distribution, updated for version 2. - * Note that because of language differences, the numbers are slightly - * different from the Ada version.] - * - * The following program contains statements of a high level programming - * language (here: C) in a distribution considered representative: - * - * assignments 52 (51.0 %) - * control statements 33 (32.4 %) - * procedure, function calls 17 (16.7 %) - * - * 103 statements are dynamically executed. The program is balanced with - * respect to the three aspects: - * - * - statement type - * - operand type - * - operand locality - * operand global, local, parameter, or constant. - * - * The combination of these three aspects is balanced only approximately. - * - * 1. Statement Type: - * ----------------- number - * - * V1 = V2 9 - * (incl. V1 = F(..) - * V = Constant 12 - * Assignment, 7 - * with array element - * Assignment, 6 - * with record component - * -- - * 34 34 - * - * X = Y +|-|"&&"|"|" Z 5 - * X = Y +|-|"==" Constant 6 - * X = X +|- 1 3 - * X = Y *|/ Z 2 - * X = Expression, 1 - * two operators - * X = Expression, 1 - * three operators - * -- - * 18 18 - * - * if .... 14 - * with "else" 7 - * without "else" 7 - * executed 3 - * not executed 4 - * for ... 7 | counted every time - * while ... 4 | the loop condition - * do ... while 1 | is evaluated - * switch ... 1 - * break 1 - * declaration with 1 - * initialization - * -- - * 34 34 - * - * P (...) procedure call 11 - * user procedure 10 - * library procedure 1 - * X = F (...) - * function call 6 - * user function 5 - * library function 1 - * -- - * 17 17 - * --- - * 103 - * - * The average number of parameters in procedure or function calls - * is 1.82 (not counting the function values aX * - * - * 2. Operators - * ------------ - * number approximate - * percentage - * - * Arithmetic 32 50.8 - * - * + 21 33.3 - * - 7 11.1 - * * 3 4.8 - * / (int div) 1 1.6 - * - * Comparison 27 42.8 - * - * == 9 14.3 - * /= 4 6.3 - * > 1 1.6 - * < 3 4.8 - * >= 1 1.6 - * <= 9 14.3 - * - * Logic 4 6.3 - * - * && (AND-THEN) 1 1.6 - * | (OR) 1 1.6 - * ! (NOT) 2 3.2 - * - * -- ----- - * 63 100.1 - * - * - * 3. Operand Type (counted once per operand reference): - * --------------- - * number approximate - * percentage - * - * Integer 175 72.3 % - * Character 45 18.6 % - * Pointer 12 5.0 % - * String30 6 2.5 % - * Array 2 0.8 % - * Record 2 0.8 % - * --- ------- - * 242 100.0 % - * - * When there is an access path leading to the final operand (e.g. a record - * component), only the final data type on the access path is counted. - * - * - * 4. Operand Locality: - * ------------------- - * number approximate - * percentage - * - * local variable 114 47.1 % - * global variable 22 9.1 % - * parameter 45 18.6 % - * value 23 9.5 % - * reference 22 9.1 % - * function result 6 2.5 % - * constant 55 22.7 % - * --- ------- - * 242 100.0 % - * - * - * The program does not compute anything meaningful, but it is syntactically - * and semantically correct. All variables have a value assigned to them - * before they are used as a source operand. - * - * There has been no explicit effort to account for the effects of a - * cache, or to balance the use of long or short displacements for code or - * data. - * - *************************************************************************** - */ - -/* Compiler and system dependent definitions: */ - -#ifndef TIME -#undef TIMES -#define TIMES -#endif - /* Use times(2) time function unless */ - /* explicitly defined otherwise */ -#ifdef MSC_CLOCK -#undef HZ -#undef TIMES -#include -#define HZ CLK_TCK -#endif - /* Use Microsoft C hi-res clock */ - -#ifdef TIMES -#include -#include - /* for "times" */ -#endif - -#define Mic_secs_Per_Second 1000000.0 - /* Berkeley UNIX C returns process times in seconds/HZ */ - -#ifdef NOSTRUCTASSIGN -#define structassign(d, s) memcpy(&(d), &(s), sizeof(d)) -#else -#define structassign(d, s) d = s -#endif - -#ifdef NOENUM -#define Ident_1 0 -#define Ident_2 1 -#define Ident_3 2 -#define Ident_4 3 -#define Ident_5 4 - typedef int Enumeration; -#else - typedef enum {Ident_1, Ident_2, Ident_3, Ident_4, Ident_5} - Enumeration; -#endif - /* for boolean and enumeration types in Ada, Pascal */ - -/* General definitions: */ - -#include - /* for strcpy, strcmp */ - -#define Null 0 - /* Value of a Null pointer */ -#define true 1 -#define false 0 - -typedef int One_Thirty; -typedef int One_Fifty; -typedef char Capital_Letter; -typedef int Boolean; -typedef char Str_30 [31]; -typedef int Arr_1_Dim [50]; -typedef int Arr_2_Dim [50] [50]; - -typedef struct record - { - struct record *Ptr_Comp; - Enumeration Discr; - union { - struct { - Enumeration Enum_Comp; - int Int_Comp; - char Str_Comp [31]; - } var_1; - struct { - Enumeration E_Comp_2; - char Str_2_Comp [31]; - } var_2; - struct { - char Ch_1_Comp; - char Ch_2_Comp; - } var_3; - } variant; - } Rec_Type, *Rec_Pointer; - - diff --git a/lib/CPUs/MIPS/bsp/examples/dhry_1.c b/lib/CPUs/MIPS/bsp/examples/dhry_1.c deleted file mode 100644 index f7b8373..0000000 --- a/lib/CPUs/MIPS/bsp/examples/dhry_1.c +++ /dev/null @@ -1,402 +0,0 @@ -/* - **************************************************************************** - * - * "DHRYSTONE" Benchmark Program - * ----------------------------- - * - * Version: C, Version 2.1 - * - * File: dhry_1.c (part 2 of 3) - * - * Date: May 25, 1988 - * - * Author: Reinhold P. Weicker - * - **************************************************************************** - */ - -#include "dhry.h" - -/* Global Variables: */ - -Rec_Pointer Ptr_Glob, - Next_Ptr_Glob; -int Int_Glob; -Boolean Bool_Glob; -char Ch_1_Glob, - Ch_2_Glob; -int Arr_1_Glob [50]; -int Arr_2_Glob [50] [50]; - -extern char *malloc (); -Enumeration Func_1 (); - /* forward declaration necessary since Enumeration may not simply be int */ - -#ifndef REG - Boolean Reg = false; -#define REG - /* REG becomes defined as empty */ - /* i.e. no register variables */ -#else - Boolean Reg = true; -#endif - -/* variables for time measurement: */ - -#ifdef TIMES -struct tms time_info; - /* see library function "times" */ -#define Too_Small_Time (2*HZ) - /* Measurements should last at least about 2 seconds */ -#endif -#ifdef TIME -extern long time(); - /* see library function "time" */ -#define Too_Small_Time 2 - /* Measurements should last at least 2 seconds */ -#endif -#ifdef MSC_CLOCK -extern clock_t clock(); -#define Too_Small_Time (2*HZ) -#endif - -long Begin_Time, - End_Time, - User_Time; -float Microseconds, - Dhrystones_Per_Second; - -/* end of variables for time measurement */ - - -main () -/*****/ - - /* main program, corresponds to procedures */ - /* Main and Proc_0 in the Ada version */ -{ - One_Fifty Int_1_Loc; - REG One_Fifty Int_2_Loc; - One_Fifty Int_3_Loc; - REG char Ch_Index; - Enumeration Enum_Loc; - Str_30 Str_1_Loc; - Str_30 Str_2_Loc; - REG int Run_Index; - REG int Number_Of_Runs; - - /* Initializations */ - - Next_Ptr_Glob = (Rec_Pointer) malloc (sizeof (Rec_Type)); - Ptr_Glob = (Rec_Pointer) malloc (sizeof (Rec_Type)); - - Ptr_Glob->Ptr_Comp = Next_Ptr_Glob; - Ptr_Glob->Discr = Ident_1; - Ptr_Glob->variant.var_1.Enum_Comp = Ident_3; - Ptr_Glob->variant.var_1.Int_Comp = 40; - strcpy (Ptr_Glob->variant.var_1.Str_Comp, - "DHRYSTONE PROGRAM, SOME STRING"); - strcpy (Str_1_Loc, "DHRYSTONE PROGRAM, 1'ST STRING"); - - Arr_2_Glob [8][7] = 10; - /* Was missing in published program. Without this statement, */ - /* Arr_2_Glob [8][7] would have an undefined value. */ - /* Warning: With 16-Bit processors and Number_Of_Runs > 32000, */ - /* overflow may occur for this array element. */ - - /* - printf ("\n"); - printf ("Dhrystone Benchmark, Version 2.1 (Language: C)\n"); - printf ("\n"); - if (Reg) - { - printf ("Program compiled with 'register' attribute\n"); - printf ("\n"); - } - else - { - printf ("Program compiled without 'register' attribute\n"); - printf ("\n"); - } - printf ("Please give the number of runs through the benchmark: "); - { - int n; - scanf ("%d", &n); - Number_Of_Runs = n; - } - printf ("\n"); - */ -#ifdef NRUNS - Number_Of_Runs = NRUNS; -#else - Number_Of_Runs = 2000000; -#endif - printf ("Execution starts, %d runs through Dhrystone\n", Number_Of_Runs); - - /***************/ - /* Start timer */ - /***************/ - -#ifdef TIMES - times (&time_info); - Begin_Time = (long) time_info.tms_utime; -#endif -#ifdef TIME - Begin_Time = time ( (long *) 0); -#endif -#ifdef MSC_CLOCK - Begin_Time = clock(); -#endif - - for (Run_Index = 1; Run_Index <= Number_Of_Runs; ++Run_Index) - { - - Proc_5(); - Proc_4(); - /* Ch_1_Glob == 'A', Ch_2_Glob == 'B', Bool_Glob == true */ - Int_1_Loc = 2; - Int_2_Loc = 3; - strcpy (Str_2_Loc, "DHRYSTONE PROGRAM, 2'ND STRING"); - Enum_Loc = Ident_2; - Bool_Glob = ! Func_2 (Str_1_Loc, Str_2_Loc); - /* Bool_Glob == 1 */ - while (Int_1_Loc < Int_2_Loc) /* loop body executed once */ - { - Int_3_Loc = 5 * Int_1_Loc - Int_2_Loc; - /* Int_3_Loc == 7 */ - Proc_7 (Int_1_Loc, Int_2_Loc, &Int_3_Loc); - /* Int_3_Loc == 7 */ - Int_1_Loc += 1; - } /* while */ - /* Int_1_Loc == 3, Int_2_Loc == 3, Int_3_Loc == 7 */ - Proc_8 (Arr_1_Glob, Arr_2_Glob, Int_1_Loc, Int_3_Loc); - /* Int_Glob == 5 */ - Proc_1 (Ptr_Glob); - for (Ch_Index = 'A'; Ch_Index <= Ch_2_Glob; ++Ch_Index) - /* loop body executed twice */ - { - if (Enum_Loc == Func_1 (Ch_Index, 'C')) - /* then, not executed */ - { - Proc_6 (Ident_1, &Enum_Loc); - strcpy (Str_2_Loc, "DHRYSTONE PROGRAM, 3'RD STRING"); - Int_2_Loc = Run_Index; - Int_Glob = Run_Index; - } - } - /* Int_1_Loc == 3, Int_2_Loc == 3, Int_3_Loc == 7 */ - Int_2_Loc = Int_2_Loc * Int_1_Loc; - Int_1_Loc = Int_2_Loc / Int_3_Loc; - Int_2_Loc = 7 * (Int_2_Loc - Int_3_Loc) - Int_1_Loc; - /* Int_1_Loc == 1, Int_2_Loc == 13, Int_3_Loc == 7 */ - Proc_2 (&Int_1_Loc); - /* Int_1_Loc == 5 */ - - } /* loop "for Run_Index" */ - - /**************/ - /* Stop timer */ - /**************/ - -#ifdef TIMES - times (&time_info); - End_Time = (long) time_info.tms_utime; -#endif -#ifdef TIME - End_Time = time ( (long *) 0); -#endif -#ifdef MSC_CLOCK - End_Time = clock(); -#endif - /* - printf ("Execution ends\n"); - printf ("\n"); - printf ("Final values of the variables used in the benchmark:\n"); - printf ("\n"); - printf ("Int_Glob: %d\n", Int_Glob); - printf (" should be: %d\n", 5); - printf ("Bool_Glob: %d\n", Bool_Glob); - printf (" should be: %d\n", 1); - printf ("Ch_1_Glob: %c\n", Ch_1_Glob); - printf (" should be: %c\n", 'A'); - printf ("Ch_2_Glob: %c\n", Ch_2_Glob); - printf (" should be: %c\n", 'B'); - printf ("Arr_1_Glob[8]: %d\n", Arr_1_Glob[8]); - printf (" should be: %d\n", 7); - printf ("Arr_2_Glob[8][7]: %d\n", Arr_2_Glob[8][7]); - printf (" should be: Number_Of_Runs + 10\n"); - printf ("Ptr_Glob->\n"); - printf (" Ptr_Comp: %d\n", (int) Ptr_Glob->Ptr_Comp); - printf (" should be: (implementation-dependent)\n"); - printf (" Discr: %d\n", Ptr_Glob->Discr); - printf (" should be: %d\n", 0); - printf (" Enum_Comp: %d\n", Ptr_Glob->variant.var_1.Enum_Comp); - printf (" should be: %d\n", 2); - printf (" Int_Comp: %d\n", Ptr_Glob->variant.var_1.Int_Comp); - printf (" should be: %d\n", 17); - printf (" Str_Comp: %s\n", Ptr_Glob->variant.var_1.Str_Comp); - printf (" should be: DHRYSTONE PROGRAM, SOME STRING\n"); - printf ("Next_Ptr_Glob->\n"); - printf (" Ptr_Comp: %d\n", (int) Next_Ptr_Glob->Ptr_Comp); - printf (" should be: (implementation-dependent), same as above\n"); - printf (" Discr: %d\n", Next_Ptr_Glob->Discr); - printf (" should be: %d\n", 0); - printf (" Enum_Comp: %d\n", Next_Ptr_Glob->variant.var_1.Enum_Comp); - printf (" should be: %d\n", 1); - printf (" Int_Comp: %d\n", Next_Ptr_Glob->variant.var_1.Int_Comp); - printf (" should be: %d\n", 18); - printf (" Str_Comp: %s\n", - Next_Ptr_Glob->variant.var_1.Str_Comp); - printf (" should be: DHRYSTONE PROGRAM, SOME STRING\n"); - printf ("Int_1_Loc: %d\n", Int_1_Loc); - printf (" should be: %d\n", 5); - printf ("Int_2_Loc: %d\n", Int_2_Loc); - printf (" should be: %d\n", 13); - printf ("Int_3_Loc: %d\n", Int_3_Loc); - printf (" should be: %d\n", 7); - printf ("Enum_Loc: %d\n", Enum_Loc); - printf (" should be: %d\n", 1); - printf ("Str_1_Loc: %s\n", Str_1_Loc); - printf (" should be: DHRYSTONE PROGRAM, 1'ST STRING\n"); - printf ("Str_2_Loc: %s\n", Str_2_Loc); - printf (" should be: DHRYSTONE PROGRAM, 2'ND STRING\n"); - printf ("\n"); - -*/ - User_Time = End_Time - Begin_Time; - - if (User_Time < Too_Small_Time) - { - printf ("Measured time too small to obtain meaningful results\n"); - printf ("Please increase number of runs\n"); - printf ("\n"); - } - else - { -#ifdef TIME - Microseconds = (float) User_Time * Mic_secs_Per_Second - / (float) Number_Of_Runs; - Dhrystones_Per_Second = (float) Number_Of_Runs / (float) User_Time; -#else - Microseconds = (float) User_Time * Mic_secs_Per_Second - / ((float) HZ * ((float) Number_Of_Runs)); - Dhrystones_Per_Second = ((float) HZ * (float) Number_Of_Runs) - / (float) User_Time; -#endif - printf ("Microseconds for one run through Dhrystone: "); - printf ("%6.1f \n", Microseconds); - printf ("Dhrystones per Second: "); - printf ("%6.1f \n", Dhrystones_Per_Second); - printf ("\n"); - printf ("This equals to %6.1f DMIPS\n", Dhrystones_Per_Second/1757); - } - -} - - -Proc_1 (Ptr_Val_Par) -/******************/ - -REG Rec_Pointer Ptr_Val_Par; - /* executed once */ -{ - REG Rec_Pointer Next_Record = Ptr_Val_Par->Ptr_Comp; - /* == Ptr_Glob_Next */ - /* Local variable, initialized with Ptr_Val_Par->Ptr_Comp, */ - /* corresponds to "rename" in Ada, "with" in Pascal */ - - structassign (*Ptr_Val_Par->Ptr_Comp, *Ptr_Glob); - Ptr_Val_Par->variant.var_1.Int_Comp = 5; - Next_Record->variant.var_1.Int_Comp - = Ptr_Val_Par->variant.var_1.Int_Comp; - Next_Record->Ptr_Comp = Ptr_Val_Par->Ptr_Comp; - Proc_3 (&Next_Record->Ptr_Comp); - /* Ptr_Val_Par->Ptr_Comp->Ptr_Comp - == Ptr_Glob->Ptr_Comp */ - if (Next_Record->Discr == Ident_1) - /* then, executed */ - { - Next_Record->variant.var_1.Int_Comp = 6; - Proc_6 (Ptr_Val_Par->variant.var_1.Enum_Comp, - &Next_Record->variant.var_1.Enum_Comp); - Next_Record->Ptr_Comp = Ptr_Glob->Ptr_Comp; - Proc_7 (Next_Record->variant.var_1.Int_Comp, 10, - &Next_Record->variant.var_1.Int_Comp); - } - else /* not executed */ - structassign (*Ptr_Val_Par, *Ptr_Val_Par->Ptr_Comp); -} /* Proc_1 */ - - -Proc_2 (Int_Par_Ref) -/******************/ - /* executed once */ - /* *Int_Par_Ref == 1, becomes 4 */ - -One_Fifty *Int_Par_Ref; -{ - One_Fifty Int_Loc; - Enumeration Enum_Loc; - - Int_Loc = *Int_Par_Ref + 10; - do /* executed once */ - if (Ch_1_Glob == 'A') - /* then, executed */ - { - Int_Loc -= 1; - *Int_Par_Ref = Int_Loc - Int_Glob; - Enum_Loc = Ident_1; - } /* if */ - while (Enum_Loc != Ident_1); /* true */ -} /* Proc_2 */ - - -Proc_3 (Ptr_Ref_Par) -/******************/ - /* executed once */ - /* Ptr_Ref_Par becomes Ptr_Glob */ - -Rec_Pointer *Ptr_Ref_Par; - -{ - if (Ptr_Glob != Null) - /* then, executed */ - *Ptr_Ref_Par = Ptr_Glob->Ptr_Comp; - Proc_7 (10, Int_Glob, &Ptr_Glob->variant.var_1.Int_Comp); -} /* Proc_3 */ - - -Proc_4 () /* without parameters */ -/*******/ - /* executed once */ -{ - Boolean Bool_Loc; - - Bool_Loc = Ch_1_Glob == 'A'; - Bool_Glob = Bool_Loc | Bool_Glob; - Ch_2_Glob = 'B'; -} /* Proc_4 */ - - -Proc_5 () /* without parameters */ -/*******/ - /* executed once */ -{ - Ch_1_Glob = 'A'; - Bool_Glob = false; -} /* Proc_5 */ - - - /* Procedure for the assignment of structures, */ - /* if the C compiler doesn't support this feature */ -#ifdef NOSTRUCTASSIGN -memcpy (d, s, l) -register char *d; -register char *s; -register int l; -{ - while (l--) *d++ = *s++; -} -#endif - - diff --git a/lib/CPUs/MIPS/bsp/examples/dhry_2.c b/lib/CPUs/MIPS/bsp/examples/dhry_2.c deleted file mode 100644 index 63a3d3e..0000000 --- a/lib/CPUs/MIPS/bsp/examples/dhry_2.c +++ /dev/null @@ -1,192 +0,0 @@ -/* - **************************************************************************** - * - * "DHRYSTONE" Benchmark Program - * ----------------------------- - * - * Version: C, Version 2.1 - * - * File: dhry_2.c (part 3 of 3) - * - * Date: May 25, 1988 - * - * Author: Reinhold P. Weicker - * - **************************************************************************** - */ - -#include "dhry.h" - -#ifndef REG -#define REG - /* REG becomes defined as empty */ - /* i.e. no register variables */ -#endif - -extern int Int_Glob; -extern char Ch_1_Glob; - - -Proc_6 (Enum_Val_Par, Enum_Ref_Par) -/*********************************/ - /* executed once */ - /* Enum_Val_Par == Ident_3, Enum_Ref_Par becomes Ident_2 */ - -Enumeration Enum_Val_Par; -Enumeration *Enum_Ref_Par; -{ - *Enum_Ref_Par = Enum_Val_Par; - if (! Func_3 (Enum_Val_Par)) - /* then, not executed */ - *Enum_Ref_Par = Ident_4; - switch (Enum_Val_Par) - { - case Ident_1: - *Enum_Ref_Par = Ident_1; - break; - case Ident_2: - if (Int_Glob > 100) - /* then */ - *Enum_Ref_Par = Ident_1; - else *Enum_Ref_Par = Ident_4; - break; - case Ident_3: /* executed */ - *Enum_Ref_Par = Ident_2; - break; - case Ident_4: break; - case Ident_5: - *Enum_Ref_Par = Ident_3; - break; - } /* switch */ -} /* Proc_6 */ - - -Proc_7 (Int_1_Par_Val, Int_2_Par_Val, Int_Par_Ref) -/**********************************************/ - /* executed three times */ - /* first call: Int_1_Par_Val == 2, Int_2_Par_Val == 3, */ - /* Int_Par_Ref becomes 7 */ - /* second call: Int_1_Par_Val == 10, Int_2_Par_Val == 5, */ - /* Int_Par_Ref becomes 17 */ - /* third call: Int_1_Par_Val == 6, Int_2_Par_Val == 10, */ - /* Int_Par_Ref becomes 18 */ -One_Fifty Int_1_Par_Val; -One_Fifty Int_2_Par_Val; -One_Fifty *Int_Par_Ref; -{ - One_Fifty Int_Loc; - - Int_Loc = Int_1_Par_Val + 2; - *Int_Par_Ref = Int_2_Par_Val + Int_Loc; -} /* Proc_7 */ - - -Proc_8 (Arr_1_Par_Ref, Arr_2_Par_Ref, Int_1_Par_Val, Int_2_Par_Val) -/*********************************************************************/ - /* executed once */ - /* Int_Par_Val_1 == 3 */ - /* Int_Par_Val_2 == 7 */ -Arr_1_Dim Arr_1_Par_Ref; -Arr_2_Dim Arr_2_Par_Ref; -int Int_1_Par_Val; -int Int_2_Par_Val; -{ - REG One_Fifty Int_Index; - REG One_Fifty Int_Loc; - - Int_Loc = Int_1_Par_Val + 5; - Arr_1_Par_Ref [Int_Loc] = Int_2_Par_Val; - Arr_1_Par_Ref [Int_Loc+1] = Arr_1_Par_Ref [Int_Loc]; - Arr_1_Par_Ref [Int_Loc+30] = Int_Loc; - for (Int_Index = Int_Loc; Int_Index <= Int_Loc+1; ++Int_Index) - Arr_2_Par_Ref [Int_Loc] [Int_Index] = Int_Loc; - Arr_2_Par_Ref [Int_Loc] [Int_Loc-1] += 1; - Arr_2_Par_Ref [Int_Loc+20] [Int_Loc] = Arr_1_Par_Ref [Int_Loc]; - Int_Glob = 5; -} /* Proc_8 */ - - -Enumeration Func_1 (Ch_1_Par_Val, Ch_2_Par_Val) -/*************************************************/ - /* executed three times */ - /* first call: Ch_1_Par_Val == 'H', Ch_2_Par_Val == 'R' */ - /* second call: Ch_1_Par_Val == 'A', Ch_2_Par_Val == 'C' */ - /* third call: Ch_1_Par_Val == 'B', Ch_2_Par_Val == 'C' */ - -Capital_Letter Ch_1_Par_Val; -Capital_Letter Ch_2_Par_Val; -{ - Capital_Letter Ch_1_Loc; - Capital_Letter Ch_2_Loc; - - Ch_1_Loc = Ch_1_Par_Val; - Ch_2_Loc = Ch_1_Loc; - if (Ch_2_Loc != Ch_2_Par_Val) - /* then, executed */ - return (Ident_1); - else /* not executed */ - { - Ch_1_Glob = Ch_1_Loc; - return (Ident_2); - } -} /* Func_1 */ - - -Boolean Func_2 (Str_1_Par_Ref, Str_2_Par_Ref) -/*************************************************/ - /* executed once */ - /* Str_1_Par_Ref == "DHRYSTONE PROGRAM, 1'ST STRING" */ - /* Str_2_Par_Ref == "DHRYSTONE PROGRAM, 2'ND STRING" */ - -Str_30 Str_1_Par_Ref; -Str_30 Str_2_Par_Ref; -{ - REG One_Thirty Int_Loc; - Capital_Letter Ch_Loc; - - Int_Loc = 2; - while (Int_Loc <= 2) /* loop body executed once */ - if (Func_1 (Str_1_Par_Ref[Int_Loc], - Str_2_Par_Ref[Int_Loc+1]) == Ident_1) - /* then, executed */ - { - Ch_Loc = 'A'; - Int_Loc += 1; - } /* if, while */ - if (Ch_Loc >= 'W' && Ch_Loc < 'Z') - /* then, not executed */ - Int_Loc = 7; - if (Ch_Loc == 'R') - /* then, not executed */ - return (true); - else /* executed */ - { - if (strcmp (Str_1_Par_Ref, Str_2_Par_Ref) > 0) - /* then, not executed */ - { - Int_Loc += 7; - Int_Glob = Int_Loc; - return (true); - } - else /* executed */ - return (false); - } /* if Ch_Loc */ -} /* Func_2 */ - - -Boolean Func_3 (Enum_Par_Val) -/***************************/ - /* executed once */ - /* Enum_Par_Val == Ident_3 */ -Enumeration Enum_Par_Val; -{ - Enumeration Enum_Loc; - - Enum_Loc = Enum_Par_Val; - if (Enum_Loc == Ident_3) - /* then, executed */ - return (true); - else /* not executed */ - return (false); -} /* Func_3 */ - diff --git a/lib/CPUs/MIPS/bsp/examples/dttl.c b/lib/CPUs/MIPS/bsp/examples/dttl.c deleted file mode 100644 index 8efffa2..0000000 --- a/lib/CPUs/MIPS/bsp/examples/dttl.c +++ /dev/null @@ -1,261 +0,0 @@ -/* dttl.c -- simulation of Cassini/Huygens symbol synchronizer loop - * - * Author: Lorenzo Simone's (matlab script) - * Modifications by: Jon Hamkins (conversion to C, support routines, - * memory requirement reductions) - * Last Revised: Wed Jan 31 10:47:52 PST 2001 - */ -#define M_PI 3.1415926535897932384626433832795 - -#include -#include -#include "random.h" - -/* global variables */ -int delay, - L; /* samples per symbol */ -double Pt, /* transition density */ - sigma; /* noise standard deviation */ -long seed=-123; - -/* This function simulates a large 1-dimensional array without requiring - * storage for the whole array. This is possible because the array is - * accessed in roughly increasing indices. Thus, we only need to - * store a few symbols worth of samples in the array, and we can reuse - * the array indices as time goes on. */ -int drint(double v) -{ - return (int)(v+0.5); -} - -double -rec(int idx) -{ - static int firsttime = 1, - max, /* maximum index containing data */ - mod, /* length of ring buffer */ - b; /* value of last transmitted bit */ - static double r[2000]; /* need several symbols worth of samples */ - int i,j,k; - - /* First time, store samples for random delay and first few symbols */ - if (firsttime==1) { - firsttime=0; - for (i=0; i0.5) ? 1 : -1; /* first random symbol */ - for (j=0; j<3; j++) { /* 3 binary symbols with transition Pt */ - b = (ran1(&seed)>Pt) ? b : -b; /* next symbol value */ - for (k=0; kmax) /* check if we need to create another sample */ - { - b = (ran1(&seed)>Pt) ? b : -b; /* next symbol value */ - /* generate samples for one symbol and store in ring buffer */ - for (i=1; i<=L; i++) r[(int)(fmod(max+i,mod))] = b+sigma*gaussian(&seed); - max += L; /* maximum index for which samples exist */ - } - /* return appropriate sample from ring buffer */ - return(r[(int)(fmod(idx,mod))]); -} - -main() -{ - double - detout, /* detector output */ - I, old_I, /* in-phase accumulations */ - Q, old_Q, /* quadrature accumulations */ - T, /* transition detection */ - theta, /* baseband NCO output (radians) */ - lambda, /* normalized timing error (symbols) */ - A, alfa, Ampl, Bl, Df, - DR, Es_No, Es_No_lin, Fc1, Fc2, Fvco, Fs, Kd, Kv, - lambda_ss_sim = 0., lambda_ss_th, No, P, P_No, - sigma_lambda_sim = 0., sigma_lambda_th, SNR_sim, SNR_th, tau, Tc1, Tc2, - time, Ts, x1, Y, bit_I, bit_Q, bit; - int i, j, k, N, offset, k1, k2, EOB; - FILE *p1, *p2, *p3, *p4, *p5; - - /* Data settings */ - Fc1 = 48000; /* sample rate at DTTL input (F1/2 = 8.215MHz/2) */ - Tc1 = 1./Fc1; - - DR = 4800; /* data rate (symb/sec) */ - - Fc2 = DR; /* sampling rate pre-detection */ - Tc2 = 1./Fc2; - - L = drint(Tc2/Tc1); /* samples per symbol in the arm filters */ - offset = drint(L/2.); - - Es_No = 600.; /* dB */ - P_No = Es_No+10.*log10(DR); /* data power-over-noise spectral density */ - /* ratio (dBHz) */ - - N = 2500; /* number of symbols to simulate */ - Pt=.5; /* Transition density */ - - Bl=0.01*DR; /* loop bandwidth (Hz) */ - Df=0.001*DR; /* frequency offset */ - Fvco=DR+Df; - - tau=ran1(&seed)-.5; /* set symbol timing offset, -.5 to .5 */ - delay=drint(2.*L+tau*L+1); /* channel delay */ - - P=1.; /* data power */ - Ampl=sqrt(P); - - No=10.*log10(P*Tc2)-Es_No; /* noise spectral density (dBW/Hz) */ - sigma=sqrt(pow(10.,0.1*No)/(2.*Tc1)); - printf("sigma=%f\n",sigma); - - /* DPLL settings */ - Fs=DR; /* loop sampling frequency (Hz) */ - Ts=1./Fs; /* loop sampling time (s) */ - - /* Loop gain */ - Kd=2.*Ampl*Pt; /* phase detector gain (quants/rad) */ - /* @ high Es/No */ - Kv=1.; /* VCO gain (rad/quants) */ - - /* Analog loop filter components */ - alfa=4.*Bl/(Kd*Kv); - - /* Digital loop filter components */ - A=alfa*Ts; - - /* Initial condition */ - theta = 0; - old_I=1; - old_Q=1; - x1=0; - Y=0; - - /* Plot data files */ -// p1 = fopen("plot1.dat","w"); /* theta */ -// p2 = fopen("plot2.dat","w"); /* lambda */ -// p3 = fopen("plot3.dat","w"); /* detout */ -// p4 = fopen("plot4.dat","w"); /* I-Data */ -// p5 = fopen("plot5.dat","w"); /* Q-Data */ - - k1 = drint(0.5*N); - k2 = N; - - printf("Data rate: %.0f symbols/sec\n",DR); - printf("Sample rate at DTTL input: %.0f samples/sec\n",Fc1); - printf("Samples per symbol: %d\n",L); - printf("Random delay set to: %f symbols (%d samples)\n",tau,delay); - printf("Transition density used in random bit generation: %f\n",Pt); - printf("Es/No: %f dB\n",Es_No); - printf("Loop bandwidth: %f Hz\n",Bl); - printf("Doppler: %f Hz\n",Df); - printf("Simulation length: %d symbols (%d samples)\n\n",N,N*L+delay); - - /* Simulation Loop */ - for (i=2; i<=N; i++) - { - /* loop over symbols */ - /* find start of in-phase integration */ - for (j=1; j < L; j++) - { - if (fmod(theta + 2*M_PI * Fvco*(j+1+(i-1)*(Fc1/DR))/Fc1, 2*M_PI) - < fmod(theta + 2*M_PI * Fvco*(j +(i-1)*(Fc1/DR))/Fc1, 2*M_PI)) - break; - /* one could replace loop above with a direct calculation such as: */ - /* j=ceil((1.-modulo(theta/(2*M_PI),1.))/(Fvco*Tc1))-1.; */ - /* j+1 is the first index in the block */ - EOB=j+(i-1)*L; /* End of Block */ - } - /* In-phase integrator */ - bit_I = 0.; - printf("Symbol # %d\n", i); - printf("I[%d:%d] :\n", EOB-L+1, EOB); - for (j=EOB-L+1; j<=EOB; j++) - { - bit = rec(j); - if (bit > 0) - printf("-"); - else - printf("_"); - - bit_I += bit; - } - printf("\n"); - I = bit_I; - - /* Mid-Phase integrator */ - bit_Q = 0.; - printf("Q[%d:%d] :\n", EOB-L+offset+1, EOB+offset); - for (j=EOB-L+offset+1; j<=EOB+offset; j++) - { - bit = rec(j); - if (bit > 0) - printf("-"); - else - printf("_"); - - bit_Q += bit; - } - printf("\n\n"); - Q = bit_Q; - - Q *= 2.*M_PI/(Tc2/Tc1); - - /* Transition Detector */ - I = (I > 0) ? 1. : -1.; /* hard limiter */ - T = 0.5*(I - old_I); - - /* Detector Output */ - detout = fmod(old_Q*T,2*M_PI); - - /* Save accumulations for next time through loop */ - old_I = I; - old_Q = Q; - if (fabs(detout)>M_PI) - detout = -detout+2*M_PI*((detout>0) ? 1. : -1.); - - /* NCO */ - Y += detout*A; /* Loop filter */ - theta=Kv*Y; /* phase */ -// lambda = theta/(2.*M_PI)+(i*Tc2*Df+tau); /* normalized error */ - lambda = theta/(2.*M_PI)+(i*(Fvco/DR -1) + tau); /* normalized error */ - - /* error mean and variance calculation */ - lambda_ss_sim += lambda; /* partial sum */ - sigma_lambda_sim += lambda*lambda; /* partial sum of squares */ - - /* store phase and normalized error to data files */ -// fprintf(p1,"%f %f\n",(double)i,theta); -// fprintf(p2,"%f %f\n",(double)i,lambda); -// fprintf(p3,"%f %f\n",(double)i,detout); -// fprintf(p4,"%f %f\n",(double)i,I); -// fprintf(p5,"%f %f\n",(double)i,Q); - } -// fclose(p1); -// fclose(p2); -// fclose(p3); -// fclose(p4); -// fclose(p5); - - /* Statistics Analysis */ - /* ------------------- */ - /* complete the mean and variance calculation */ - lambda_ss_sim /= N; - sigma_lambda_sim = sigma_lambda_sim/N - lambda_ss_sim*lambda_ss_sim; - Es_No_lin = pow(10.,0.1*Es_No); -// sigma_lambda_th = Bl*Tc2/(4.*Pt*Es_No_lin*pow(erf(sqrt(Es_No_lin)),2.)); - sigma_lambda_th = Bl*Tc2/(4.*Pt*Es_No_lin*Es_No_lin); - SNR_sim = -10*log10(sigma_lambda_sim); - SNR_th = -10*log10(sigma_lambda_th); - /* Steady-State error */ - lambda_ss_th=Df/(4.*Bl); - printf("Simulation: var: %f rad^2 loop SNR: %f dB ss error: %f%%\n", - sigma_lambda_sim, SNR_sim, 100.*lambda_ss_sim); - printf("Theory: var: %f rad^2 loop SNR: %f dB ss error: %f%%\n", - sigma_lambda_th, SNR_th, 100.*lambda_ss_th); -// system("gnuplot < plot1.gp"); -// system("gnuplot < plot2.gp"); - printf("Done.\n"); -} diff --git a/lib/CPUs/MIPS/bsp/examples/gunzip.c b/lib/CPUs/MIPS/bsp/examples/gunzip.c deleted file mode 100644 index 066c88e..0000000 --- a/lib/CPUs/MIPS/bsp/examples/gunzip.c +++ /dev/null @@ -1,198 +0,0 @@ -#include -#include -#include -#include -#include -#include - -#define CPU_FREQ_HZ 100000000 -#include "libsys.h" - -#include "crc32.h" -#include "inflate.h" - -char buffer[1024*1024]; -char * volatile pPtr_r; -char * volatile pPtr_w; -volatile int timeout_cnt; -volatile int file_len; - -void handler3(void) -{ - volatile UINT32 *pUART_stat = (UINT32*)SYS_UART0_STAT; - volatile UINT32 *pUART_data = (UINT32*)SYS_UART0_DATA; - - while(0x200 & *pUART_stat) - { -// sputs("w: "); print_word((int)pPtr_w); sputs("\n"); - if (pPtr_w == &buffer[sizeof(buffer)-1]) - pPtr_w = buffer; - *(pPtr_w++) = *pUART_data; - timeout_cnt = 100; - file_len++; - } - -} - -int READBYTE(z_stream *zs) { - if (zs->avail_in <= 0) - return -1; - - zs->avail_in --; - return *(zs->next_in ++); -} - -#define MAX_BUFOUT 16*1024*1024 -int main(int argc, char **argv) -{ - volatile UINT32 *pUART_stat = (UINT32*)SYS_UART0_STAT; - unsigned char outData[MAX_BUFOUT]; - FILE *infp; - int i, gpflags, tmp[4]; - unsigned long size, crc; - unsigned char *fileData; - unsigned long bytes, InflatedSize, InflatedCRC, speed_count; - z_stream zs; - time_t start_time, work_time; - - UART0_setbaud(460800); - - printf("Reading gzipped stream..\n"); - - pPtr_r = buffer; - pPtr_w = buffer; - *pUART_stat = (1 << 6); - interrupt_register(3, handler3); - interrupt_enable(3); - - file_len = 0; - timeout_cnt = 1000000; - while(timeout_cnt--) - { - sleep(1); - } - - printf("file_len: %d\n", file_len); - bytes = file_len; - fileData = pPtr_r; - - zs.next_in = fileData; - zs.avail_in = (unsigned int) bytes; - zs.next_out = outData; - zs.avail_out = MAX_BUFOUT; - - tmp[0] = READBYTE(&zs); - if (tmp[0] == -1) - { - // error reading from file - printf("error reading data from file\n"); - return 0; - } - tmp[1] = READBYTE(&zs); - - if (tmp[0] != 0x1f || tmp[1] != 0x8b) { -// fprintf(stderr, "Magic number mismatch 0x%02x%02x\n", -// tmp[0], tmp[1]); - return 20; - } - - tmp[0] = READBYTE(&zs); - if(tmp[0] != 8) { -// fprintf(stderr, "Unknown compression method: 0x%02x\n", tmp[0]); - return 20; - } - - gpflags = READBYTE(&zs); - if ((gpflags & ~0x1f)) { - printf("Unknown flags set!\n"); - } - - /* Skip file modification time (4 bytes) */ - READBYTE(&zs); - READBYTE(&zs); - READBYTE(&zs); - READBYTE(&zs); - /* Skip extra flags and operating system fields (2 bytes) */ - READBYTE(&zs); - READBYTE(&zs); - - if ((gpflags & 4)) { - /* Skip extra field */ - tmp[0] = READBYTE(&zs); - tmp[1] = READBYTE(&zs); - i = tmp[0] + 256*tmp[1]; - while (i--) - { - READBYTE(&zs); - } - } - if((gpflags & 8)) { - while((READBYTE(&zs))) { - } - } - if((gpflags & 16)) { - while((READBYTE(&zs))) { - } - } - if((gpflags & 2)) { - /* Skip CRC16 */ - READBYTE(&zs); - READBYTE(&zs); - } - - printf("Go\n"); - // normal test - start_time = clock(); - if (InflateData(&zs)) - { - printf("Problem during decompression!\n"); - return 0; - } - work_time = clock() - start_time; - - -/* - // speed test - fprintf(stdout, "SPEED TEST!\n"); - speed_count = 0; - while (time(NULL) - start_time < 20) - { - zs_speed.next_in = zs.next_in; - zs_speed.next_out = zs.next_out; - zs_speed.avail_in = zs.avail_in; - zs_speed.avail_out = zs.avail_out; - if (InflateData(&zs_speed)) - { - fprintf(stdout, "Problem during decompression!\n"); - return 0; - } - speed_count ++; - } - fprintf(stdout, "speed count %ld\n", speed_count); - zs.next_in = zs_speed.next_in; - zs.next_out = zs_speed.next_out; - zs.avail_in = zs_speed.avail_in; - zs.avail_out = zs_speed.avail_out; -*/ - - crc = READBYTE(&zs); - crc |= (READBYTE(&zs)<<8); - crc |= (READBYTE(&zs)<<16); - crc |= (READBYTE(&zs)<<24); - - size = READBYTE(&zs); - size |= (READBYTE(&zs)<<8); - size |= (READBYTE(&zs)<<16); - size |= (READBYTE(&zs)<<24); - - InflatedSize = MAX_BUFOUT - zs.avail_out; - InflatedCRC = MakeCRC32(outData, InflatedSize, 0); - -// write(1, outData, InflatedSize); - fprintf(stdout, "CRC: %08lx %08lx %s\n", crc, InflatedCRC, (crc != InflatedCRC)?"**error**":""); - fprintf(stdout, "Size: %08lx %08lx %s\n", size, InflatedSize, (size != InflatedSize)?"**error**":""); - fprintf(stdout, "Time for decompression was %.2f seconds\n", (float)work_time/1000); - fprintf(stdout, "Throughput is %d kByte/s\n", InflatedSize/work_time); - - return 0; -} diff --git a/lib/CPUs/MIPS/bsp/examples/hashtest.c b/lib/CPUs/MIPS/bsp/examples/hashtest.c deleted file mode 100644 index b960966..0000000 --- a/lib/CPUs/MIPS/bsp/examples/hashtest.c +++ /dev/null @@ -1,323 +0,0 @@ -/********************************************************************\ - * - * FILE: hashtest.c - * - * CONTENTS: test file for sample C-implementation of - * RIPEMD-160 and RIPEMD128 - * * command line arguments: - * filename -- compute hash code of file read binary - * -sstring -- print string & hashcode - * -t -- perform time trial - * -x -- execute standard test suite, ASCII input - * * for linkage with rmd128.c: define RMDsize as 128 - * for linkage with rmd160.c: define RMDsize as 160 (default) - * TARGET: any computer with an ANSI C compiler - * - * AUTHOR: Antoon Bosselaers, ESAT-COSIC - * DATE: 18 April 1996 - * VERSION: 1.1 - * HISTORY: bug in RMDonemillion() corrected - * - * Copyright (c) Katholieke Universiteit Leuven - * 1996, All Rights Reserved - * - * Conditions for use of the RIPEMD-160 Software - * - * The RIPEMD-160 software is freely available for use under the terms and - * conditions described hereunder, which shall be deemed to be accepted by - * any user of the software and applicable on any use of the software: - * - * 1. K.U.Leuven Department of Electrical Engineering-ESAT/COSIC shall for - * all purposes be considered the owner of the RIPEMD-160 software and of - * all copyright, trade secret, patent or other intellectual property - * rights therein. - * 2. The RIPEMD-160 software is provided on an "as is" basis without - * warranty of any sort, express or implied. K.U.Leuven makes no - * representation that the use of the software will not infringe any - * patent or proprietary right of third parties. User will indemnify - * K.U.Leuven and hold K.U.Leuven harmless from any claims or liabilities - * which may arise as a result of its use of the software. In no - * circumstances K.U.Leuven R&D will be held liable for any deficiency, - * fault or other mishappening with regard to the use or performance of - * the software. - * 3. User agrees to give due credit to K.U.Leuven in scientific publications - * or communications in relation with the use of the RIPEMD-160 software - * as follows: RIPEMD-160 software written by Antoon Bosselaers, - * available at http://www.esat.kuleuven.be/~cosicart/ps/AB-9601/. - * -\********************************************************************/ -#ifndef RMDsize -#define RMDsize 160 -#endif - -#include -#include -#include -#include -#if RMDsize == 128 -#include "rmd128.h" -#elif RMDsize == 160 -#include "rmd160.h" -#endif - -#define TEST_BLOCK_SIZE 8000 -#define TEST_BLOCKS 1250 -#define TEST_BYTES ((long)TEST_BLOCK_SIZE * (long)TEST_BLOCKS) - -/********************************************************************/ - -byte *RMD(byte *message) -/* - * returns RMD(message) - * message should be a string terminated by '\0' - */ -{ - dword MDbuf[RMDsize/32]; /* contains (A, B, C, D(, E)) */ - static byte hashcode[RMDsize/8]; /* for final hash-value */ - dword X[16]; /* current 16-word chunk */ - unsigned int i; /* counter */ - dword length; /* length in bytes of message */ - dword nbytes; /* # of bytes not yet processed */ - - /* initialize */ - MDinit(MDbuf); - length = (dword)strlen((char *)message); - - /* process message in 16-word chunks */ - for (nbytes=length; nbytes > 63; nbytes-=64) { - for (i=0; i<16; i++) { - X[i] = BYTES_TO_DWORD(message); - message += 4; - } - compress(MDbuf, X); - } /* length mod 64 bytes left */ - - /* finish: */ - MDfinish(MDbuf, message, length, 0); - - for (i=0; i>2]; /* implicit cast to byte */ - hashcode[i+1] = (MDbuf[i>>2] >> 8); /* extracts the 8 least */ - hashcode[i+2] = (MDbuf[i>>2] >> 16); /* significant bits. */ - hashcode[i+3] = (MDbuf[i>>2] >> 24); - } - - return (byte *)hashcode; -} - -/********************************************************************/ - -byte *RMDbinary(char *fname) -/* - * returns RMD(message in file fname) - * fname is read as binary data. - */ -{ - FILE *mf; /* pointer to file */ - byte data[1024]; /* contains current mess. block */ - dword nbytes; /* length of this block */ - dword MDbuf[RMDsize/32]; /* contains (A, B, C, D(, E)) */ - static byte hashcode[RMDsize/8]; /* for final hash-value */ - dword X[16]; /* current 16-word chunk */ - unsigned int i, j; /* counters */ - dword length[2]; /* length in bytes of message */ - dword offset; /* # of unprocessed bytes at */ - /* call of MDfinish */ - - /* initialize */ - if ((mf = fopen(fname, "rb")) == NULL) { - fprintf(stderr, "\nRMDbinary: cannot open file \"%s\".\n", - fname); - exit(1); - } - MDinit(MDbuf); - length[0] = 0; - length[1] = 0; - - while ((nbytes = fread(data, 1, 1024, mf)) != 0) { - /* process all complete blocks */ - for (i=0; i<(nbytes>>6); i++) { - for (j=0; j<16; j++) - X[j] = BYTES_TO_DWORD(data+64*i+4*j); - compress(MDbuf, X); - } - /* update length[] */ - if (length[0] + nbytes < length[0]) - length[1]++; /* overflow to msb of length */ - length[0] += nbytes; - } - - /* finish: */ - offset = length[0] & 0x3C0; /* extract bytes 6 to 10 inclusive */ - MDfinish(MDbuf, data+offset, length[0], length[1]); - - for (i=0; i>2]; - hashcode[i+1] = (MDbuf[i>>2] >> 8); - hashcode[i+2] = (MDbuf[i>>2] >> 16); - hashcode[i+3] = (MDbuf[i>>2] >> 24); - } - - fclose(mf); - - return (byte *)hashcode; -} - -/********************************************************************/ - -void speedtest(void) -/* - * A time trial routine, to measure the speed of ripemd. - * Measures processor time required to process TEST_BLOCKS times - * a message of TEST_BLOCK_SIZE characters. - */ -{ - clock_t t0, t1; - byte *data; - byte hashcode[RMDsize/8]; - dword X[16]; - dword MDbuf[RMDsize/32]; - unsigned int i, j, k; - - srand(time(NULL)); - - /* allocate and initialize test data */ - if ((data = (byte*)malloc(TEST_BLOCK_SIZE)) == NULL) { - fprintf(stderr, "speedtest: allocation error\n"); - exit(1); - } - for (i=0; i> 7); - - /* start timer */ - printf("\n\nRIPEMD-%u time trial. Processing %ld characters...\n", - RMDsize, TEST_BYTES); - t0 = clock(); - - /* process data */ - MDinit(MDbuf); - for (i=0; i %3.2f Mbit/s\n\n", 8*(double)CLOCKS_PER_SEC*TEST_BYTES/((double)t1-t0)/(1024*1024)); - - for (i=0; i>2]; - hashcode[i+1] = (MDbuf[i>>2] >> 8); - hashcode[i+2] = (MDbuf[i>>2] >> 16); - hashcode[i+3] = (MDbuf[i>>2] >> 24); - } - printf("\nhashcode: "); - for (i=0; i0; i--) - compress(MDbuf, X); - MDfinish(MDbuf, NULL, 1000000UL, 0); - for (i=0; i>2]; - hashcode[i+1] = (MDbuf[i>>2] >> 8); - hashcode[i+2] = (MDbuf[i>>2] >> 16); - hashcode[i+3] = (MDbuf[i>>2] >> 24); - } - printf("\n* message: 1 million times \"a\"\n hashcode: "); - for (i=0; i -#define A 0.5 -#define B 0.55 - -_Sat long _Fract sat_add3 (_Sat long _Fract a, _Sat long _Fract b) -{ - return a + b; -} - -long _Fract mul3 (long _Fract a, long _Fract b) -{ - return a * b; -} - -int main() -{ - printf("hello %X + %X = %X\n", (_Sat long _Fract)A, (_Sat long _Fract)B, sat_add3(A, B)); - printf("hello %X * %X = %X\n", (_Sat long _Fract)A, (_Sat long _Fract)B, mul3(A, B)); -} diff --git a/lib/CPUs/MIPS/bsp/examples/hpi.c b/lib/CPUs/MIPS/bsp/examples/hpi.c deleted file mode 100644 index 3a21263..0000000 --- a/lib/CPUs/MIPS/bsp/examples/hpi.c +++ /dev/null @@ -1,949 +0,0 @@ -#include -#include -#include -#include -#include "libsys.h" -#include "hpi.h" - -static volatile UINT32 _g_int_active; -static volatile UINT32 _g_mbx_return; -static volatile UINT32 _g_mbx_in_flag; - -// --------------------------------------------------------- -// Globals -// --------------------------------------------------------- -typedef struct _susb_t -{ - fp_t fptr_ept[USB_MAX_NUM_EPT]; - void *aptr_ept[USB_MAX_NUM_EPT]; - - fp_t fptr_rst; - void *aptr_rst; - - fp_t fptr_sof; - void *aptr_sof; - - fp_t fptr_cfg; - void *aptr_cfg; - - fp_t fptr_sus; - void *aptr_sus; - - fp_t fptr_id; - void *aptr_id; - - fp_t fptr_vbus; - void *aptr_vbus; - -} usb_t; - -static usb_t _g_usb[USB_MAX_NUM_PORTS]; -//static usb_irp_t *_g_usb_irp_ptr[USB_MAX_NUM_PORTS][USB_MAX_NUM_EPT]; - -// --------------------------------------------------------- -// HPI ISR -// --------------------------------------------------------- -void cy67k3_isr(void) -{ - INT32 i; - UINT16 sie_msg, hpi_status; - UINT32 port, siemsg_handled, int_handled; - _g_int_active = 1; -// sputs("--------------------------------------------------------\n"); -// sputs("USB-Interrupt(4)\n"); -// sputs("HPI Status : "); - hpi_status = cy67k3_read_HPI_STATUS(); -// print_word(hpi_status); -// sputs("\n"); - -// sputs("MAILBOX (REG): "); - -// cy67k3_write(HPI_ADDRESS, HPI_REG_MAILBOX); -// print_word(cy67k3_read_HPI_DATA()); -// sputs("\n"); - - int_handled = 0; - if (hpi_status & HPI_STATUS_MBX_IN) - { - int_handled = 1; -// sputs("MAILBOX (HPI): "); - _g_mbx_return = cy67k3_read_HPI_MAILBOX(); - _g_mbx_in_flag = 1; -// print_word(_g_mbx_return); -// sputs("\n"); - } - - if (hpi_status & HPI_STATUS_RESET1) - { - int_handled = 1; - hpi_read_reg(SUSB1_REG_STATUS); - hpi_comm_exec_int(SUSB_INIT_INT, 2, R1, 0, R2, 1); -// sputs("RESET 1\n"); - } - - if (hpi_status & HPI_STATUS_RESET2) - { - int_handled = 1; - hpi_read_reg(SUSB2_REG_STATUS); - hpi_comm_exec_int(SUSB_INIT_INT, 2, R1, 0, R2, 2); -// sputs("RESET 2\n"); - } - - if (hpi_status & HPI_STATUS_DONE1) - { - int_handled = 1; -// sputs("DONE 1\n"); - } - - if (hpi_status & HPI_STATUS_DONE2) - { - int_handled = 1; -// sputs("DONE 2\n"); - } - - if (hpi_status & HPI_STATUS_SOFEOP1) - { - int_handled = 1; - hpi_read_reg(SUSB1_REG_STATUS); -// sputs("SOF/EOP 1\n"); - } - - if (hpi_status & HPI_STATUS_SOFEOP2) - { - int_handled = 1; - hpi_read_reg(SUSB2_REG_STATUS); -// sputs("SOF/EOP 2\n"); - } - - port = 0; - siemsg_handled = 0; - if (hpi_status & HPI_STATUS_SIEMSG1) - { - int_handled = 1; - sie_msg = hpi_read_reg(HPI_REG_SIE1MSG); - - // Reset message register - hpi_write_reg(HPI_REG_SIE1MSG, 0x0000); - - if (sie_msg & SUSB_RST_MSG) - { - siemsg_handled = 1; - if (_g_usb[port].fptr_rst) - (_g_usb[port].fptr_rst)(_g_usb[port].aptr_rst); - } - - if (sie_msg & SUSB_SOF_MSG) - { - siemsg_handled = 1; - if (_g_usb[port].fptr_sof) - (_g_usb[port].fptr_sof)(_g_usb[port].aptr_sof); - } - - if (sie_msg & SUSB_CFG_MSG) - { - siemsg_handled = 1; - if (_g_usb[port].fptr_cfg) - (_g_usb[port].fptr_cfg)(_g_usb[port].aptr_cfg); - } - - if (sie_msg & SUSB_SUS_MSG) - { - siemsg_handled = 1; - if (_g_usb[port].fptr_sus) - (_g_usb[port].fptr_sus)(_g_usb[port].aptr_sus); - } - - if (sie_msg & SUSB_ID_MSG) - { - siemsg_handled = 1; - if (_g_usb[port].fptr_id) - (_g_usb[port].fptr_id)(_g_usb[port].aptr_id); - } - - if (sie_msg & SUSB_VBUS_MSG) - { - siemsg_handled = 1; - if (_g_usb[port].fptr_vbus) - (_g_usb[port].fptr_vbus)(_g_usb[port].aptr_vbus); - } - - for (i=0; i < 8; i++) - { - if (sie_msg & (SUSB_EP0_MSG << i)) - { - siemsg_handled = 1; - if (_g_usb[port].fptr_ept[i]) - (_g_usb[port].fptr_ept[i])(_g_usb[port].aptr_ept[i]); - } - } - if (!siemsg_handled) - { - sputs("Unhandled SIE1 message "); - print_word(sie_msg); - sputs("!\n"); - } - - } - port = 1; - siemsg_handled = 0; - if (hpi_status & HPI_STATUS_SIEMSG2) - { - int_handled = 1; - sie_msg = hpi_read_reg(HPI_REG_SIE2MSG); - - // Reset message register - hpi_write_reg(HPI_REG_SIE2MSG, 0x0000); - - if (sie_msg & SUSB_RST_MSG) - { - siemsg_handled = 1; - if (_g_usb[port].fptr_rst) - (_g_usb[port].fptr_rst)(_g_usb[port].aptr_rst); - } - - if (sie_msg & SUSB_SOF_MSG) - { - siemsg_handled = 1; - if (_g_usb[port].fptr_sof) - (_g_usb[port].fptr_sof)(_g_usb[port].aptr_sof); - } - - if (sie_msg & SUSB_CFG_MSG) - { - siemsg_handled = 1; - if (_g_usb[port].fptr_cfg) - (_g_usb[port].fptr_cfg)(_g_usb[port].aptr_cfg); - } - - if (sie_msg & SUSB_SUS_MSG) - { - siemsg_handled = 1; - if (_g_usb[port].fptr_sus) - (_g_usb[port].fptr_sus)(_g_usb[port].aptr_sus); - } - - if (sie_msg & SUSB_ID_MSG) - { - siemsg_handled = 1; - if (_g_usb[port].fptr_id) - (_g_usb[port].fptr_id)(_g_usb[port].aptr_id); - } - - if (sie_msg & SUSB_VBUS_MSG) - { - siemsg_handled = 1; - if (_g_usb[port].fptr_vbus) - (_g_usb[port].fptr_vbus)(_g_usb[port].aptr_vbus); - } - - for (i=0; i < 8; i++) - { - if (sie_msg & (SUSB_EP0_MSG << i)) - { - siemsg_handled = 1; - if (_g_usb[port].fptr_ept[i]) - (_g_usb[port].fptr_ept[i])(_g_usb[port].aptr_ept[i]); - } - } - if (!siemsg_handled) - { - sputs("Unhandled SIE2 message "); - print_word(sie_msg); - sputs("!\n"); - } - - } - if (!int_handled) - { - sputs("Unhandled interrupt (status = "); - print_word(hpi_status); - sputs(")!\n"); - } - -// sputs("--------------------------------------------------------\n"); - _g_int_active = 0; -} - -// --------------------------------------------------------- -// CY7C67300 low-level routines -// --------------------------------------------------------- -void cy67k3_reset(void) -{ - int i; - volatile UINT32 *pHpi = (UINT32*)SYS_USB_CTRL; - - *pHpi = 3; - for (i=0; i <160; i++) - { - __asm __volatile - ( - ".set noreorder\n" - "nop\n" - "nop\n" - "nop\n" - "nop\n" - ".set reorder\n" - ); - } - - *pHpi = 2; - -} - -UINT16 cy67k3_read_HPI_DATA(void) -{ - volatile UINT32 *pHpi = (UINT32*)SYS_USB_DATA; - - return (UINT16)*pHpi; -} - -UINT16 cy67k3_read_HPI_MAILBOX(void) -{ - volatile UINT32 *pHpi = (UINT32*)SYS_USB_MBX; - - return (UINT16)*pHpi; -} - -UINT16 cy67k3_read_HPI_ADDRESS(void) -{ - volatile UINT32 *pHpi = (UINT32*)SYS_USB_ADDR; - - return (UINT16)*pHpi; -} - -UINT16 cy67k3_read_HPI_STATUS(void) -{ - volatile UINT32 *pHpi = (UINT32*)SYS_USB_STATUS; - - return (UINT16)*pHpi; -} - -void cy67k3_write_HPI_DATA(UINT16 data) -{ - volatile UINT32 *pHpi = (UINT32*)SYS_USB_DATA; - - *pHpi = (UINT32)data; -} - -void cy67k3_write_HPI_MAILBOX(UINT16 data) -{ - volatile UINT32 *pHpi = (UINT32*)SYS_USB_MBX; - - *pHpi = (UINT32)data; -} - -void cy67k3_write_HPI_ADDRESS(UINT16 data) -{ - volatile UINT32 *pHpi = (UINT32*)SYS_USB_ADDR; - - *pHpi = (UINT32)data; -} - -void cy67k3_write_HPI_STATUS(UINT16 data) -{ - volatile UINT32 *pHpi = (UINT32*)SYS_USB_STATUS; - - *pHpi = (UINT32)data; -} - -// --------------------------------------------------------- -// HPI API -// --------------------------------------------------------- -UINT32 hpi_init(void) -{ - volatile UINT32 *pHpi = (UINT32*)SYS_USB_CTRL; - int i; - UINT16 reg; - - // ToDo: Enable HPI interrupt - _g_int_active = 0; - - hpi_write_reg(HPI_REG_SIE1MSG, 0x0000); - hpi_write_reg(HPI_REG_SIE2MSG, 0x0000); - hpi_write_reg(SUSB1_REG_STATUS, 0xFFFF); - hpi_write_reg(SUSB2_REG_STATUS, 0xFFFF); - - // Init 1 - for(i=0; i < USB_MAX_NUM_EPT; i++) - { - hpi_write_reg(SUSB1_REG_EP_ADDR0 + 16*i, 0); - hpi_write_reg(SUSB1_REG_EP_CNTRES0 + 16*i, 0); - hpi_write_reg(SUSB1_REG_EP_COUNT0 + 16*i, 0); - hpi_write_reg(SUSB1_REG_EP_CTRL0 + 16*i, 0); - hpi_write_reg(SUSB1_REG_EP_STATUS0 + 16*i, 0); - } - // Init 2 - for(i=0; i < USB_MAX_NUM_EPT; i++) - { - hpi_write_reg(SUSB2_REG_EP_ADDR0 + 16*i, 0); - hpi_write_reg(SUSB2_REG_EP_CNTRES0 + 16*i, 0); - hpi_write_reg(SUSB2_REG_EP_COUNT0 + 16*i, 0); - hpi_write_reg(SUSB2_REG_EP_CTRL0 + 16*i, 0); - hpi_write_reg(SUSB2_REG_EP_STATUS0 + 16*i, 0); - } - - hpi_write_reg(HPI_REG_INTROUTE, 0x0000); - reg = hpi_read_reg(HPI_REG_INTROUTE); -// hpi_write_reg(HPI_REG_INTROUTE, reg | 0x0202); // Route reset {1,2} to HPI only -// hpi_write_reg(HPI_REG_INTROUTE, reg | 0x2800); // Route SOF/EOP {1,2} to HPI only -// hpi_write_reg(HPI_REG_INTROUTE, reg | 0x1400); // Route SOF/EOP {1,2} to CY16 only - hpi_write_reg(HPI_REG_INTROUTE, reg | 0x3C00); // Route SOF/EOP {1,2} to HPI and CY16 - - - interrupt_register(4, cy67k3_isr); - interrupt_enable(4); - *pHpi = 0x02; - - return HPI_NOERROR; -} - -void hpi_mbx_write(UINT16 msgcode) -{ - _g_mbx_in_flag = 0; - cy67k3_write_HPI_MAILBOX(msgcode); -} - -UINT32 hpi_mbx_read(void) -{ - UINT32 err; - UINT16 cy_return; - - if (_g_int_active) - { - while (!(cy67k3_read_HPI_STATUS() & HPI_STATUS_MBX_IN)); - cy_return = cy67k3_read_HPI_MAILBOX(); - } - else - { - while(!_g_mbx_in_flag); - cy_return = _g_mbx_return; - } - - switch (cy_return) - { - case COMM_ACK: - err = cy_return; - break; - - case COMM_NAK: - case COMM_ASYNC: - err = HPI_ERR_PREFIX_MBX | cy_return; - break; - - default: - err = HPI_ERR_PREFIX_MBX | cy_return; - break; - } - return err; -} - -UINT32 hpi_check_addr(UINT16 addr) -{ - if ((addr >= 0x0000) && (addr < 0x4000)) - return 0; - - if ((addr >= 0xC080) && (addr < 0xC0BC)) - return 0; - - if (addr >= 0xE000) - return 0; - - sputs("Invalid address for HPI direct access! Use LCP-command instead!\n"); - return HPI_ERR_INVPARAM; -} - -UINT32 hpi_read_reg(UINT16 addr) -{ - UINT32 result; - - result = hpi_check_addr(addr); - if (IS_ERROR(result)) - return result; - - cy67k3_write_HPI_ADDRESS(addr); - return cy67k3_read_HPI_DATA(); -} - -UINT32 hpi_write_reg(UINT16 addr, UINT16 data) -{ - UINT32 result; - - result = hpi_check_addr(addr); - if (IS_ERROR(result)) - return result; - - cy67k3_write_HPI_ADDRESS(addr); - cy67k3_write_HPI_DATA(data); -} - -UINT32 hpi_write_ram(UINT16 addr, UINT16 *pData, UINT32 len) -{ - int i, num_words; - - if (addr > 0x3FFE) - return HPI_ERR_INVPARAM; - - if (addr & 1) // Not 16bit aligned? - return HPI_ERR_INVPARAM; - - cy67k3_write_HPI_ADDRESS(addr); - - num_words = len/2; - if (len % 2) - num_words++; - - for (i=0; i < num_words; i++) - cy67k3_write_HPI_DATA(pData[i]); - - return len; -} - -UINT32 hpi_read_ram(UINT16 addr, UINT16 *pData, UINT32 len) -{ - int i, num_words; - - if (addr > 0x3FFE) - return HPI_ERR_INVPARAM; - - if (addr & 1) // Not 16bit aligned? - return HPI_ERR_INVPARAM; - - cy67k3_write_HPI_ADDRESS(addr); - - num_words = len/2; - if (len % 2) - num_words++; - - for (i=0; i < num_words; i++) - pData[i] = cy67k3_read_HPI_DATA(); - - return len; -} - -UINT32 hpi_comm_reset(void) -{ - hpi_mbx_write(COMM_RESET); - - return hpi_mbx_read(); -} - -UINT32 hpi_comm_jump2code(UINT16 addr) -{ - cy67k3_write_HPI_ADDRESS(addr); - hpi_mbx_write(COMM_JUMP2CODE); - - return hpi_mbx_read(); -} - -UINT32 hpi_comm_callcode(UINT16 addr) -{ - hpi_write_reg(COMM_CODE_ADDR, addr); - - hpi_mbx_write(COMM_CALL_CODE); - - return hpi_mbx_read(); -} - -UINT32 hpi_comm_write_ctrl_reg(UINT16 addr, UINT16 data, UINT16 logic) -{ - - hpi_write_reg(COMM_CTRL_REG_ADDR, addr); - hpi_write_reg(COMM_CTRL_REG_DATA, data); - hpi_write_reg(COMM_CTRL_REG_LOGIC, logic); - - hpi_mbx_write(COMM_WRITE_CTRL_REG); - - return hpi_mbx_read(); -} - -UINT32 hpi_comm_read_ctrl_reg(UINT16 addr) -{ - UINT32 result; - - hpi_write_reg(COMM_CTRL_REG_ADDR, addr); - - hpi_mbx_write(COMM_READ_CTRL_REG); - - result = hpi_mbx_read(); - if (IS_ERROR(result)) - return result; - - cy67k3_write_HPI_ADDRESS(COMM_CTRL_REG_DATA); - return (UINT32)cy67k3_read_HPI_DATA(); - -} - -UINT32 hpi_comm_write_xmem(UINT16 addr, UINT8 *pData, UINT16 len) -{ - return HPI_ERR_NOTIMPL; - -} - -UINT32 hpi_comm_read_xmem(UINT16 addr, UINT8 *pData, UINT16 len) -{ - return HPI_ERR_NOTIMPL; - -} - -typedef struct _sreg_param_t -{ - UINT32 id; - UINT16 val; - -} reg_param_t; - -UINT32 hpi_comm_exec_int(UINT16 intnum, UINT32 nargs, ...) -{ - int i; - UINT32 result; - va_list args; - reg_param_t reg_param[MAX_NUM_REGS]; - - va_start(args, nargs); - - if (nargs > MAX_NUM_REGS) - { - fprintf(stderr, "hpi_comm_exec_int(): Number (%d), of arguments exceeds %d!\n", nargs, MAX_NUM_REGS); - return HPI_ERR_INVPARAM; - } - - for (i=0; i < nargs; i++) - { - reg_param[i].id = va_arg(args, UINT32); - if (reg_param[i].id > MAX_NUM_REGS) - { - fprintf(stderr, "hpi_comm_exec_int(): Invalid register R%d!\n", reg_param[i].id); - return HPI_ERR_INVPARAM; - } - - reg_param[i].val = (UINT16)va_arg(args, UINT32); - } - va_end(args); - - hpi_write_reg(COMM_INT_NUM, intnum); - - for (i=0; i < nargs; i++) - { - hpi_write_reg(COMM_R0 + 2*reg_param[i].id, reg_param[i].val); - } - - hpi_mbx_write(COMM_EXEC_INT); - - result = hpi_mbx_read(); - if (IS_ERROR(result)) - return result; - - return (UINT32)hpi_read_reg(COMM_R0); -} - -UINT32 usb_init(void) -{ - INT32 i; - - for (i=0; i < USB_MAX_NUM_PORTS; i++) - { - memset(&_g_usb[i], 0, sizeof(usb_t)); - } - return 0; -} - -UINT32 usb_callback_register(UINT32 port, UINT32 type, fp_t pFunc, void *pArg) -{ - UINT32 result; - if (port >= USB_MAX_NUM_PORTS) - return -1; - - result = 0; - switch (type) - { - case SUSB_EP0_MSG: - _g_usb[port].fptr_ept[0] = pFunc; - _g_usb[port].aptr_ept[0] = pArg; - break; - - case SUSB_EP1_MSG: - _g_usb[port].fptr_ept[1] = pFunc; - _g_usb[port].aptr_ept[1] = pArg; - break; - - case SUSB_EP2_MSG: - _g_usb[port].fptr_ept[2] = pFunc; - _g_usb[port].aptr_ept[2] = pArg; - break; - - case SUSB_EP3_MSG: - _g_usb[port].fptr_ept[3] = pFunc; - _g_usb[port].aptr_ept[3] = pArg; - break; - - case SUSB_EP4_MSG: - _g_usb[port].fptr_ept[4] = pFunc; - _g_usb[port].aptr_ept[4] = pArg; - break; - - case SUSB_EP5_MSG: - _g_usb[port].fptr_ept[5] = pFunc; - _g_usb[port].aptr_ept[5] = pArg; - break; - - case SUSB_EP6_MSG: - _g_usb[port].fptr_ept[6] = pFunc; - _g_usb[port].aptr_ept[6] = pArg; - break; - - case SUSB_EP7_MSG: - _g_usb[port].fptr_ept[7] = pFunc; - _g_usb[port].aptr_ept[7] = pArg; - break; - - case SUSB_RST_MSG: - _g_usb[port].fptr_rst = pFunc; - _g_usb[port].aptr_rst = pArg; - break; - - case SUSB_SOF_MSG: - _g_usb[port].fptr_sof = pFunc; - _g_usb[port].aptr_sof = pArg; - break; - - case SUSB_CFG_MSG: - _g_usb[port].fptr_cfg = pFunc; - _g_usb[port].aptr_cfg = pArg; - break; - - case SUSB_SUS_MSG: - _g_usb[port].fptr_sus = pFunc; - _g_usb[port].aptr_sus = pArg; - break; - - case SUSB_ID_MSG: - _g_usb[port].fptr_id = pFunc; - _g_usb[port].aptr_id = pArg; - break; - - case SUSB_VBUS_MSG: - _g_usb[port].fptr_vbus = pFunc; - _g_usb[port].aptr_vbus = pArg; - break; - - default: - result = -1; - break; - } - - return result; -} - -UINT32 usb_irp_register(usb_irp_t *pIRP, UINT32 port, UINT32 ept, UINT32 size, UINT32 is_out) -{ - - if (!pIRP) - return -1; - - if (port >= USB_MAX_NUM_PORTS) - return -1; - - if (ept >= USB_MAX_NUM_EPT) - return -1; - - if (size >= USB_MAX_IMG_SIZE) - return -1; - - memset(pIRP, 0, sizeof(usb_irp_t)); - pIRP->is_out = is_out; - pIRP->is_in = !is_out; - pIRP->tsize = size; - pIRP->port = port; - pIRP->ept = ept; - pIRP->cy_irp_addr = USB_IRP_BASE + port*USB_MAX_NUM_EPT*sizeof(cy_req_t) + ept*sizeof(cy_req_t); - pIRP->cy_req.next = 0; - pIRP->cy_req.addr = USB_IMG_BASE + port*USB_MAX_NUM_EPT*USB_MAX_IMG_SIZE + ept*USB_MAX_IMG_SIZE; - pIRP->cy_req.size = size; - pIRP->cy_req.callback = 0; - fifo_alloc(&pIRP->fifo, 8*USB_MAX_IMG_SIZE); - - return 0; -} - -UINT32 usb_irp_enqueue(usb_irp_t *pIRP) -{ - UINT32 result; - - if (!pIRP) - { -// sputs ("usb_irp_enqueue(): Invalid IRP!\n"); - return -1; - } - -// printf("cy_addr: %4.4X, Next: %4.4X, Addr: %4.4X, Size: %4.4X, CB: %4.4X\n", pIRP->cy_irp_addr, pIRP->cy_req.next, pIRP->cy_req.addr, pIRP->cy_req.size, pIRP->cy_req.callback); - - if (pIRP->is_out) - { - hpi_write_ram(pIRP->cy_irp_addr, (UINT16*)&pIRP->cy_req, sizeof(cy_req_t)); - if (pIRP->port == 0) - result = hpi_comm_exec_int(SUSB1_RECEIVE_INT, 2, R1, pIRP->ept, R8, pIRP->cy_irp_addr); - - if (pIRP->port == 1) - result = hpi_comm_exec_int(SUSB2_RECEIVE_INT, 2, R1, pIRP->ept, R8, pIRP->cy_irp_addr); - } - if (pIRP->is_in) - { - pIRP->tx_in_progress = 1; - hpi_write_ram(pIRP->cy_irp_addr, (UINT16*)&pIRP->cy_req, sizeof(cy_req_t)); - if (pIRP->port == 0) - result = hpi_comm_exec_int(SUSB1_SEND_INT, 2, R1, pIRP->ept, R8, pIRP->cy_irp_addr); - - if (pIRP->port == 1) - result = hpi_comm_exec_int(SUSB2_SEND_INT, 2, R1, pIRP->ept, R8, pIRP->cy_irp_addr); - } - -// if (result) -// printf ("usb_irp_enqueue(): Result = %8.8X\n", result); - - return result; - -} - -UINT32 fifo_alloc(fifo_t *pObj, UINT32 size) -{ - pObj->pBuf = (UINT8*)malloc(size); - if (!pObj->pBuf) - { -// printf ("fifo_alloc(): Error allocating memory!\n"); - return -1; - } -// printf ("fifo_alloc(): pBuf at %8.8X\n", (UINT32)pObj->pBuf); - pObj->size = size; - pObj->pPtr_wr = pObj->pBuf; - pObj->pPtr_rd = pObj->pBuf; - - return 0; -} - -UINT32 fifo_free(fifo_t *pObj) -{ - if (pObj->pBuf) - free(pObj->pBuf); - - return 0; -} - -UINT32 fifo_flush(fifo_t *pObj) -{ - pObj->pPtr_wr = pObj->pBuf; - pObj->pPtr_rd = pObj->pBuf; - - return 0; -} - -UINT32 fifo_is_empty(fifo_t *pObj) -{ - return (pObj->pPtr_wr == pObj->pPtr_rd); -} - -UINT32 fifo_is_full(fifo_t *pObj) -{ - UINT8 *pNext, *pEnd; - - pEnd = pObj->pBuf + pObj->size; - pNext = pObj->pPtr_wr + 1; - if (pNext == pEnd) - pNext = pObj->pBuf; - - return (pNext == pObj->pPtr_rd); -} - -UINT32 fifo_read(fifo_t *pObj, UINT8 *pData, UINT32 size, UINT32 timeout, UINT32 do_block) -{ - UINT32 i; - UINT32 wait_4ever, timeout_cnt, cnt; - UINT8 *pEnd; - - pEnd = pObj->pBuf + pObj->size; - wait_4ever = (timeout == 0); - - cnt = 0; - while(size) - { - timeout_cnt = timeout; - - while(fifo_is_empty(pObj)) - { - if (!do_block) - return cnt; - - if (!wait_4ever) - { - if (timeout_cnt) - { - timeout_cnt--; - sleep(1); - } - else - { - return cnt; - } - } - } - - if (pData) - pData[cnt] = *(pObj->pPtr_rd); - - cnt++; - pObj->pPtr_rd++; - if (pObj->pPtr_rd == pEnd) - pObj->pPtr_rd = pObj->pBuf; - - size--; - } - - return cnt; -} - -UINT32 fifo_write(fifo_t *pObj, UINT8 *pData, UINT32 size, UINT32 timeout, UINT32 do_block) -{ - UINT32 wait_4ever, timeout_cnt, cnt; - UINT8 *pEnd; - - pEnd = pObj->pBuf + pObj->size; - wait_4ever = (timeout == 0); - - cnt = 0; - while(size) - { - timeout_cnt = timeout; - - while(fifo_is_full(pObj)) - { - if (!do_block) - return cnt; - - if (!wait_4ever) - { - if (timeout_cnt) - { - timeout_cnt--; - sleep(1); - } - else - { - return cnt; - } - } - } - - if (pData) - *(pObj->pPtr_wr) = pData[cnt]; - - cnt++; - pObj->pPtr_wr++; - if (pObj->pPtr_wr == pEnd) - pObj->pPtr_wr = pObj->pBuf; - - size--; - } - - return cnt; -} - -// --------------------------------------------------------- diff --git a/lib/CPUs/MIPS/bsp/examples/hpi.h b/lib/CPUs/MIPS/bsp/examples/hpi.h deleted file mode 100644 index 58edabe..0000000 --- a/lib/CPUs/MIPS/bsp/examples/hpi.h +++ /dev/null @@ -1,384 +0,0 @@ -#ifndef HPI_H -#define HPI_H - -// --------------------------------------------------------- -// API related -// --------------------------------------------------------- -//#define IS_ERROR(e) (0 != (e & HPI_ERROR)) -#define HPI_NOERROR 0 -#define HPI_ERROR 0x80000000 -#define HPI_ERR_NOTIMPL (HPI_ERROR + 1) -#define HPI_ERR_INVPARAM (HPI_ERROR + 2) -#define HPI_ERR_TIMEOUT (HPI_ERROR + 3) -#define HPI_ERR_PREFIX_MBX (HPI_ERROR + 0x00010000) - -#define MAX_NUM_REGS 14 -#define R0 0 -#define R1 1 -#define R2 2 -#define R3 3 -#define R4 4 -#define R5 5 -#define R6 6 -#define R7 7 -#define R8 8 -#define R9 9 -#define R10 10 -#define R11 11 -#define R12 12 -#define R13 13 - -#define USB_MAX_NUM_PORTS 2 -#define USB_MAX_NUM_EPT 8 -#define USB_MAX_IMG_SIZE 512 -#define USB_IRP_BASE 0x0F80 -#define USB_IMG_BASE 0x1000 - -typedef void (*fp_t)(void*); - -// Receive buffer on EP -typedef struct _scy_req_t -{ - UINT16 next; - UINT16 addr; - UINT16 size; - UINT16 callback; -} cy_req_t; - -typedef struct _sfifo_t -{ - UINT32 size; - UINT8 *pBuf; - UINT8 * volatile pPtr_wr, * volatile pPtr_rd; - -} fifo_t; - -typedef struct _susb_irp_t -{ - UINT16 tsize; - UINT32 is_in, is_out; - UINT32 port, ept; - UINT16 cy_irp_addr; - fifo_t fifo; - UINT32 tx_in_progress; - cy_req_t cy_req; -} usb_irp_t; - -// --------------------------------------------------------- -// CY7C67300 related -// --------------------------------------------------------- -#define HPI_WAITACK 1 -#define HPI_NOWAIT 0 - -// --------------------------------------------------------- -// HPI status flags -#define HPI_STATUS_MBX_IN 0x0001 -#define HPI_STATUS_RESET1 0x0002 -#define HPI_STATUS_DONE1 0x0004 -#define HPI_STATUS_DONE2 0x0008 -#define HPI_STATUS_SIEMSG1 0x0010 -#define HPI_STATUS_SIEMSG2 0x0020 -#define HPI_STATUS_RESUME1 0x0040 -#define HPI_STATUS_RESUME2 0x0080 -#define HPI_STATUS_MBX_OUT 0x0100 -#define HPI_STATUS_RESET2 0x0200 -#define HPI_STATUS_SOFEOP1 0x0400 -#define HPI_STATUS_SOFEOP2 0x1000 -#define HPI_STATUS_ID 0x4000 -#define HPI_STATUS_VBUS 0x8000 - -// --------------------------------------------------------- -// LCP command codes -#define COMM_RESET 0xFA50 -#define COMM_JUMP2CODE 0xCE00 -#define COMM_EXEC_INT 0xCE01 -#define COMM_READ_CTRL_REG 0xCE02 -#define COMM_WRITE_CTRL_REG 0xCE03 -#define COMM_CALL_CODE 0xCE04 -#define COMM_READ_XMEM 0xCE05 -#define COMM_WRITE_XMEM 0xCE06 -#define C0MM_CONFIG 0xCE07 -#define COMM_READ_MEM 0xCE08 -#define COMM_WRITE_MEM 0xCE09 -// LCP response codes -#define COMM_ACK 0x0FED -#define COMM_NAK 0xDEAD -#define COMM_ASYNC 0xF00D - -// --------------------------------------------------------- -// LCP memory addresses -#define COMM_PORT_CMD 0x01BA // For PORT Command -#define COMM_MEM_ADDR 0x01BC // Address for COMM_RD/WR_MEM -#define COMM_MEM_LEN 0x01BE // Address for COMM_RD/WR_MEM -#define COMM_LAST_DATA 0x01C0 // memory pointer for xmem -#define COMM_CTRL_REG_ADDR 0x01BC // Address for COMM_RD/WR_CTRL_REG -#define COMM_CTRL_REG_DATA 0x01BE // Address for COMM_RD/WR_CTRL_REG -#define COMM_CTRL_REG_LOGIC 0x01C0 // Address used for AND/OR -#define REG_WRITE_FLG 0x0000 // Value for COMM_CTRL_REG_LOGIC -#define REG_AND_FLG 0x0001 // Value for COMM_CTRL_REG_LOGIC -#define REG_OR_FLG 0x0002 // Value for COMM_CTRL_REG_LOGIC -#define COMM_TIMEOUT 0x01BE // Address setting Timeout for sending response to host -#define COMM_CODE_ADDR 0x01BC // Address for COMM_CALL_CODE and COMM_JUMP2CODE -#define COMM_INT_NUM 0x01C2 // Address used for COMM_EXEC_INT -#define COMM_R0 0x01C4 // CY16-R0 register -#define COMM_R1 0x01C6 // CY16-R1 register -#define COMM_R2 0x01C8 // CY16-R2 register -#define COMM_R3 0x01CA // CY16-R3 register -#define COMM_R4 0x01CC // CY16-R4 register -#define COMM_R5 0x01CE // CY16-R5 register -#define COMM_R6 0x01D0 // CY16-R6 register -#define COMM_R7 0x01D2 // CY16-R7 register -#define COMM_R8 0x01D4 // CY16-R8 register -#define COMM_R9 0x01D6 // CY16-R9 register -#define COMM_R10 0x01D8 // CY16-R10 register -#define COMM_R11 0x01DA // CY16-R11 register -#define COMM_R12 0x01DC // CY16-R12 register -#define COMM_R13 0x01DE // CY16-R13 register - -// for COMM_CTRL_REG_LOGIC -#define LOGIC_DIRECT 0 -#define LOGIC_AND 1 -#define LOGIC_OR 2 - -// --------------------------------------------------------- -// Software interrupts -#define SUSB_INIT_INT 113 -// USB 1 -#define SUSB1_DEVICE_DESCRIPTOR_VEC 90 -#define SUSB1_CONFIGURATION_DESCRIPTOR_VEC 91 -#define SUSB1_STRING_DESCRIPTOR_VEC 92 -#define SUSB1_FINISH_INT 89 -#define SUSB1_STALL_INT 82 -#define SUSB1_STANDARD_INT 83 -#define SUSB1_SEND_INT 80 -#define SUSB1_RECEIVE_INT 81 -#define SUSB1_VENDOR_INT 85 -#define SUSB1_CLASS_INT 87 -#define SUSB1_LOADER_INT 94 -#define SUSB1_DELTA_CONFIG_INT 95 - -// USB 2 -#define SUSB2_DEVICE_DESCRIPTOR_VEC 106 -#define SUSB2_CONFIGURATION_DESCRIPTOR_VEC 107 -#define SUSB2_STRING_DESCRIPTOR_VEC 108 -#define SUSB2_FINISH_INT 105 -#define SUSB2_STALL_INT 98 -#define SUSB2_STANDARD_INT 99 -#define SUSB2_SEND_INT 96 -#define SUSB2_RECEIVE_INT 97 -#define SUSB2_VENDOR_INT 101 -#define SUSB2_CLASS_INT 103 -#define SUSB2_LOADER_INT 110 -#define SUSB2_DELTA_CONFIG_INT 111 - -// --------------------------------------------------------- -// General USB Registers -#define USB_REG_FLAGS 0xC000 // CPU Flags -#define USB_REG_BANK 0xC002 // Register Bank -#define USB_REG_REVISON 0xC004 // Hardware Revision -#define USB_REG_SPEED 0xC008 // CPU Speed -#define USB_REG_PWRCTRL 0xC00A // Power Control -#define USB_REG_INTEN 0xC00E // Interrupt Enable -#define USB_REG_BP 0xC014 // Breakpoint -#define USB_REG_USBDIAG 0xC03C // USB Diagnostic -#define USB_REG_MEMDIAG 0xC03E // Memory Diagnostic - -// HPI registers -#define HPI_REG_BP 0x0140 // HPI Breakpoint -#define HPI_REG_INTROUTE 0x0142 // Interrupt Routing -#define HPI_REG_SIE1MSG 0x0144 // SIE1msg -#define HPI_REG_SIE2MSG 0x0148 // SIE2msg -#define HPI_REG_MAILBOX 0xC0C6 // HPI Mailbox - -// --------------------------------------------------------- -// General Device Registers -// Device 1 -#define SUSB1_REG_PORTSEL 0xC084 // Port select -#define SUSB1_REG_USBCTRL 0xC08A // USB control -#define SUSB1_REG_INTEN 0xC08C // Interrupt enable -#define SUSB1_REG_ADDR 0xC08E // Address -#define SUSB1_REG_STATUS 0xC090 // Status -#define SUSB1_REG_FRAMENUM 0xC092 // Frame number -#define SUSB1_REG_SOFEOPCNT 0xC094 // SOF/EOP count - -// Device 2 -#define SUSB2_REG_PORTSEL 0xC0A4 // Port select -#define SUSB2_REG_USBCTRL 0xC0AA // USB control -#define SUSB2_REG_INTEN 0xC0AC // Interrupt enable -#define SUSB2_REG_ADDR 0xC0AE // Address -#define SUSB2_REG_STATUS 0xC0B0 // Status -#define SUSB2_REG_FRAMENUM 0xC0B2 // Frame number -#define SUSB2_REG_SOFEOPCNT 0xC0B4 // SOF/EOP count - -// --------------------------------------------------------- -// Endpoint Registers -// Device 1 Control -#define SUSB1_REG_EP_CTRL0 0x0200 -#define SUSB1_REG_EP_CTRL1 0x0210 -#define SUSB1_REG_EP_CTRL2 0x0220 -#define SUSB1_REG_EP_CTRL3 0x0230 -#define SUSB1_REG_EP_CTRL4 0x0240 -#define SUSB1_REG_EP_CTRL5 0x0250 -#define SUSB1_REG_EP_CTRL6 0x0260 -#define SUSB1_REG_EP_CTRL7 0x0270 -// Device 1 Address -#define SUSB1_REG_EP_ADDR0 0x0202 -#define SUSB1_REG_EP_ADDR1 0x0212 -#define SUSB1_REG_EP_ADDR2 0x0222 -#define SUSB1_REG_EP_ADDR3 0x0232 -#define SUSB1_REG_EP_ADDR4 0x0242 -#define SUSB1_REG_EP_ADDR5 0x0252 -#define SUSB1_REG_EP_ADDR6 0x0262 -#define SUSB1_REG_EP_ADDR7 0x0272 -// Device 1 Count -#define SUSB1_REG_EP_COUNT0 0x0204 -#define SUSB1_REG_EP_COUNT1 0x0214 -#define SUSB1_REG_EP_COUNT2 0x0224 -#define SUSB1_REG_EP_COUNT3 0x0234 -#define SUSB1_REG_EP_COUNT4 0x0244 -#define SUSB1_REG_EP_COUNT5 0x0254 -#define SUSB1_REG_EP_COUNT6 0x0264 -#define SUSB1_REG_EP_COUNT7 0x0274 -// Device 1 Status -#define SUSB1_REG_EP_STATUS0 0x0206 -#define SUSB1_REG_EP_STATUS1 0x0216 -#define SUSB1_REG_EP_STATUS2 0x0226 -#define SUSB1_REG_EP_STATUS3 0x0236 -#define SUSB1_REG_EP_STATUS4 0x0246 -#define SUSB1_REG_EP_STATUS5 0x0256 -#define SUSB1_REG_EP_STATUS6 0x0266 -#define SUSB1_REG_EP_STATUS7 0x0276 -// Device 1 Count result -#define SUSB1_REG_EP_CNTRES0 0x0208 -#define SUSB1_REG_EP_CNTRES1 0x0218 -#define SUSB1_REG_EP_CNTRES2 0x0228 -#define SUSB1_REG_EP_CNTRES3 0x0238 -#define SUSB1_REG_EP_CNTRES4 0x0248 -#define SUSB1_REG_EP_CNTRES5 0x0258 -#define SUSB1_REG_EP_CNTRES6 0x0268 -#define SUSB1_REG_EP_CNTRES7 0x0278 - -// Device 2 Control -#define SUSB2_REG_EP_CTRL0 0x0280 -#define SUSB2_REG_EP_CTRL1 0x0290 -#define SUSB2_REG_EP_CTRL2 0x02A0 -#define SUSB2_REG_EP_CTRL3 0x02B0 -#define SUSB2_REG_EP_CTRL4 0x02C0 -#define SUSB2_REG_EP_CTRL5 0x02D0 -#define SUSB2_REG_EP_CTRL6 0x02E0 -#define SUSB2_REG_EP_CTRL7 0x02F0 -// Device 2 Address -#define SUSB2_REG_EP_ADDR0 0x0282 -#define SUSB2_REG_EP_ADDR1 0x0292 -#define SUSB2_REG_EP_ADDR2 0x02A2 -#define SUSB2_REG_EP_ADDR3 0x02B2 -#define SUSB2_REG_EP_ADDR4 0x02C2 -#define SUSB2_REG_EP_ADDR5 0x02D2 -#define SUSB2_REG_EP_ADDR6 0x02E2 -#define SUSB2_REG_EP_ADDR7 0x02F2 -// Device 2 Count -#define SUSB2_REG_EP_COUNT0 0x0284 -#define SUSB2_REG_EP_COUNT1 0x0294 -#define SUSB2_REG_EP_COUNT2 0x02A4 -#define SUSB2_REG_EP_COUNT3 0x02B4 -#define SUSB2_REG_EP_COUNT4 0x02C4 -#define SUSB2_REG_EP_COUNT5 0x02D4 -#define SUSB2_REG_EP_COUNT6 0x02E4 -#define SUSB2_REG_EP_COUNT7 0x02F4 -// Device 2 Status -#define SUSB2_REG_EP_STATUS0 0x0286 -#define SUSB2_REG_EP_STATUS1 0x0296 -#define SUSB2_REG_EP_STATUS2 0x02A6 -#define SUSB2_REG_EP_STATUS3 0x02B6 -#define SUSB2_REG_EP_STATUS4 0x02C6 -#define SUSB2_REG_EP_STATUS5 0x02D6 -#define SUSB2_REG_EP_STATUS6 0x02E6 -#define SUSB2_REG_EP_STATUS7 0x02F6 -// Device 2 Count result -#define SUSB2_REG_EP_CNTRES0 0x0288 -#define SUSB2_REG_EP_CNTRES1 0x0298 -#define SUSB2_REG_EP_CNTRES2 0x02A8 -#define SUSB2_REG_EP_CNTRES3 0x02B8 -#define SUSB2_REG_EP_CNTRES4 0x02C8 -#define SUSB2_REG_EP_CNTRES5 0x02D8 -#define SUSB2_REG_EP_CNTRES6 0x02E8 -#define SUSB2_REG_EP_CNTRES7 0x02F8 - -// --------------------------------------------------------- -// others -#define HUSB_TDLISTDONE 0x1000 -#define HUSB_SOF 0x2000 -#define HUSB_ARMV 0x0001 -#define HUSB_AINS_FS 0x0002 -#define HUSB_AINS_LS 0x0004 -#define HUSB_AWAKEUP 0x0008 -#define HUSB_BRMV 0x0010 -#define HUSB_BINS_FS 0x0020 -#define HUSB_BINS_LS 0x0040 -#define HUSB_BWAKEUP 0x0080 - -#define SUSB_EP0_MSG 0x0001 -#define SUSB_EP1_MSG 0x0002 -#define SUSB_EP2_MSG 0x0004 -#define SUSB_EP3_MSG 0x0008 -#define SUSB_EP4_MSG 0x0010 -#define SUSB_EP5_MSG 0x0020 -#define SUSB_EP6_MSG 0x0040 -#define SUSB_EP7_MSG 0x0080 -#define SUSB_RST_MSG 0x0100 -#define SUSB_SOF_MSG 0x0200 -#define SUSB_CFG_MSG 0x0400 -#define SUSB_SUS_MSG 0x0800 -#define SUSB_ID_MSG 0x4000 -#define SUSB_VBUS_MSG 0x8000 - -// --------------------------------------------------------- -// Functions -// --------------------------------------------------------- - -// HPI low-level routines -void cy67k3_isr(void); -void cy67k3_reset(void); -UINT16 cy67k3_read_HPI_DATA(void); -UINT16 cy67k3_read_HPI_MAILBOX(void); -UINT16 cy67k3_read_HPI_ADDRESS(void); -UINT16 cy67k3_read_HPI_STATUS(void); -void cy67k3_write_HPI_DATA(UINT16 data); -void cy67k3_write_HPI_MAILBOX(UINT16 data); -void cy67k3_write_HPI_ADDRESS(UINT16 data); -void cy67k3_write_HPI_STATUS(UINT16 data); - -// HPI API -UINT32 hpi_init(void); -void hpi_mbx_write(UINT16 msgcode); -UINT32 hpi_mbx_read(void); -UINT32 hpi_read_reg(UINT16 addr); -UINT32 hpi_write_reg(UINT16 addr, UINT16 data); -UINT32 hpi_write_ram(UINT16 addr, UINT16 *pData, UINT32 num_words); -UINT32 hpi_read_ram(UINT16 addr, UINT16 *pData, UINT32 num_words); -UINT32 hpi_comm_reset(void); -UINT32 hpi_comm_jump2code(UINT16 addr); -UINT32 hpi_comm_callcode(UINT16 addr); -UINT32 hpi_comm_write_ctrl_reg(UINT16 addr, UINT16 data, UINT16 logic); -UINT32 hpi_comm_read_ctrl_reg(UINT16 addr); -UINT32 hpi_comm_write_xmem(UINT16 addr, UINT8 *pData, UINT16 len); -UINT32 hpi_comm_read_xmem(UINT16 addr, UINT8 *pData, UINT16 len); -UINT32 hpi_comm_exec_int(UINT16 intnum, UINT32 nargs, ...); - -// USB API -UINT32 usb_init(void); -UINT32 usb_irp_register(usb_irp_t *pIRP, UINT32 port, UINT32 ept, UINT32 size, UINT32 is_out); -UINT32 usb_irp_enqueue(usb_irp_t *pIRP); -UINT32 usb_callback_register(UINT32 port, UINT32 type, fp_t pFunc, void *pArg); - -#define FIFO_BLOCK 1 -#define FIFO_NONBLOCK 0 -UINT32 fifo_alloc(fifo_t *pObj, UINT32 size); -UINT32 fifo_free(fifo_t *pObj); -UINT32 fifo_flush(fifo_t *pObj); -UINT32 fifo_is_full(fifo_t *pObj); -UINT32 fifo_is_empty(fifo_t *pObj); -UINT32 fifo_read(fifo_t *pObj, UINT8 *pData, UINT32 size, UINT32 timeout, UINT32 do_block); -UINT32 fifo_write(fifo_t *pObj, UINT8 *pData, UINT32 size, UINT32 timeout, UINT32 do_block); - -#endif // HPI_H diff --git a/lib/CPUs/MIPS/bsp/examples/inflate.c b/lib/CPUs/MIPS/bsp/examples/inflate.c deleted file mode 100644 index b50581d..0000000 --- a/lib/CPUs/MIPS/bsp/examples/inflate.c +++ /dev/null @@ -1,504 +0,0 @@ -/* inflate routines for Palm OS (to inflate a deflated stream) - * - * Based heavily upon gunzip.c by Pasi Ojala - * http://www.cs.tut.fi/~albert/Dev/gunzip/ - * Many, many thanks for that code! - * - * Changes: - * 2002-12-30 - Added #defines to use zlib's struct instead of mine, just - * in case you want to compile it that way. - * 2002-12-29 - Found out that this is VERY slow. ZLib is 3x faster. - * Worked on speeding it up. Partially successful. Profiled - * code and marked critical areas. 1932 bytes added to a - * Palm program by linking in the .o file. Schweet! - * 2002-12-21 - Finished surgery. Only one function to inflate dynamic and - * fixed data. Rewrote table generation to be iterative. - * Hacked and slashed my way through unnecessary code. - * The size is now down to 3512 bytes. - * 2002-12-20 - Started major surgery - * 2002-12-19 - Looked at the code a bit more - * 2002-12-17 - Continued work. Down to about 6k for the .o file - * 2002-12-09 - Continued work, added z_stream_fid instead of globals - * 2002-12-08 - Started work so that it decompresses up to 64k (one memory - * chunk on the Palm. - * 2002-12-07 - Removed bit reverse table. Removed unzip code. - */ -#include "libsys.h" -#include "inflate.h" -#ifdef VERBOSE -#include // Just in case you put a printf() function back in -#endif - -void Status(char *, int); - -typedef struct HufNode_struct { - // b0 and b1 are either values in the tree array to jump to (branches) - // or are literal values. - // if (bX & 0x8000) - // value = bX ^ 0x8000; - // else - // link_to_array_element = bX; - unsigned int b0; // Bigger than 1 byte (2 is ideal) - unsigned int b1; // Bigger than 1 byte (2 is ideal) -} HufNode; - - -// Not that rhobust anymore -- If out of data, this will -// return a whole lot of 1 bits. -// -// This function consumes a large percentage of time (#1) -char READBIT(z_stream *zs) -{ - char carry; - - if (zs->reserved == 1) - { - if (zs->avail_in == 0) - return 1; - zs->reserved = *(zs->next_in ++) | 0x0100; - zs->avail_in --; - } - - carry = zs->reserved & 1; - zs->reserved >>= 1; - - return carry; -} - - -// Make sure that [a] is <= 16 -// If there are endian problems, force [a] to be <= 8 -// Might be faster if all (up to [a] bits) of zs->reserved was read into res -// right away. -// -// This function consumes a large percentage of time (#4) -int READBITS(z_stream *zs, int a) -{ - int res = 0, pos = 0; - - while (a --) - { - if (zs->reserved == 1) - { - if (zs->avail_in == 0) - return 1; - zs->reserved = *(zs->next_in ++) | 0x0100; - zs->avail_in --; - } - - res += (zs->reserved & 1) << pos; - zs->reserved >>= 1; - pos ++; - } - - return res; -} - - -// Huffman tree structures, variables and related routines -// -// These routines are one-bit-at-a-time decode routines. They -// are not as fast as multi-bit routines, but maybe a bit easier -// to understand and use a lot less memory. -// -// The tree is created in an array -// -// currentTree = where to put the tree (in an array) -// numval = Number of elements in the lengths array -// lengths = array of lengths -// -// -// This function consumes a large percentage of time (#5) -int CreateTree(HufNode *currentTree, int numval, unsigned char *lengths) { - int i, j, len; // basically scratch values - int BlankNode; // Where is the next blank array index - int this_code, mask, *bitData; // used in tree generation - int bl_count[16] = { 0, }; // Counter of code lengths - int next_code[16] = { 0, }; // Code for a specific length - // 16 = (15 is max length of a code when inflating) + (1 for zero) - - // Step 1: Count the code lengths - for (i = 0; i < numval; i ++) - { - j = lengths[i]; - if (j > 15) - return 1; - bl_count[j] ++; - } - - // Step 2: Find numerical value of the smallest code of each length - // Also note that I've inserted some weak validation code here. I'm - // not 100% sure that it is up to RFC specs, but it seems to work fine - // in my tests - // - // The validation theory is that at the root node, you have 2 branches or - // values possible. If you branch, you get 2 more potentials. If you - // get a value, you lose one potential. So, if the root node has one of - // each, the number of potentials at the next level is still two. If that - // node just has branches, the number of potentials is four. If both of - // the nodes on the following level just have values, the number of - // potentials is 0, leaving us with a complete tree. - // - // If I don't validate and if an invalid tree gets generated, an - // infinite loop is possible - bl_count[0] = 0; - j = 0; - len = 2; - for (i = 1; i < 16; i ++) - { - len -= bl_count[i]; - len *= 2; - j = (j + bl_count[i - 1]) << 1; - next_code[i] = j; - } - if (len) - return 1; - - // Step 3: Assign numerical values to all codes - BlankNode = 1; - currentTree[0].b0 = 0x0000; - currentTree[0].b1 = 0x0000; - for (i = 0; i < numval; i ++) - { - len = lengths[i]; - if (len != 0) - { - this_code = next_code[len]; - next_code[len] ++; - mask = 1 << (len - 1); - j = 0; - while (mask > 1) - { - if (this_code & mask) - bitData = &(currentTree[j].b1); - else - bitData = &(currentTree[j].b0); - - if (*bitData == 0x0000) - { - *bitData = BlankNode; - j = BlankNode; - BlankNode ++; - currentTree[j].b0 = 0x0000; - currentTree[j].b1 = 0x0000; - } - else - j = *bitData; - - mask >>= 1; - } - if (this_code & 0x01) - currentTree[j].b1 = 0x8000 | i; - else - currentTree[j].b0 = 0x8000 | i; - } - } - -#ifdef VERBOSE - fprintf(stderr, "%d table entries used\n", - BlankNode); - if (numval < 20) { - for (i = 0; i < BlankNode; i ++) - { - fprintf(stderr, "0x%03x - ", i); - if (currentTree[i].b0 & 0x8000) - fprintf(stderr, "value: 0x%03x ", currentTree[i].b0 ^ 0x8000); - else - fprintf(stderr, " link: 0x%03x ", currentTree[i].b0); - - if (currentTree[i].b1 & 0x8000) - fprintf(stderr, "value: 0x%03x\n", currentTree[i].b1 ^ 0x8000); - else - fprintf(stderr, " link: 0x%03x\n", currentTree[i].b1); - } - } -#endif - - return 0; -} - - -// Using the tree passed in, read bits from the data stream until we arrive -// at the proper value -// -// This function consumes a large percentage of time (#2) -int DecodeValue(z_stream *zs, HufNode *currentTree) -{ - unsigned int i = 0; - - // decode one symbol of the data per iteration - // Infinite loop detection code could go here. Maximum - // bits to read is 15. - while (i < 0x8000) - { - if (READBIT(zs)) - i = currentTree[i].b1; - else - i = currentTree[i].b0; - } - return i & 0x7FFF; -} - - -int Decompress_Stored(z_stream *zs) -{ - int blockLen, cSum; - -#ifdef VERBOSE - fprintf(stderr, "Stored\n"); -#endif - - zs->reserved = 1;; - if (zs->avail_in < 4) - return -1; - - zs->avail_in -= 4; - blockLen = *(zs->next_in ++); - blockLen |= *(zs->next_in ++) << 8; - - cSum = *(zs->next_in ++); - cSum |= (*(zs->next_in ++) << 8); - - if ((blockLen + cSum) ^ 0xFFFF) - return 1; - if (zs->avail_in < blockLen || zs->avail_out < blockLen) - return -1; - zs->avail_in -= blockLen; - zs->avail_out -= blockLen; - - while (blockLen --) - { - *(zs->next_out) = *(zs->next_in); - zs->next_out ++; - zs->next_in ++; - } - - return 0; -} - - -int MakeTrees(z_stream *zs, char is_fixed, HufNode *literalTree, - HufNode *distanceTree) -{ - // Order of the bit length code lengths - static const unsigned border[] = { - 16, 17, 18, 0, 8, 7, 9, 6, 10, 5, 11, 4, 12, 3, 13, 2, 14, 1, 15 }; - unsigned char ll[288+32]; - int i, j, n, l, literalCodes, distCodes; - - if (is_fixed) - { - literalCodes = 288; - - // Set a large range to 8 - for (i = 0; i < 288; i ++) - ll[i] = 8; - // In that range, set some to 9 and others to 7 - // (smaller code, but slightly slower table generation) - for (i = 144; i < 256; i ++) - ll[i] = 9; - for (; i < 280; i ++) - ll[i] = 7; - - distCodes = 32; - - for (i = 288; i < 320; i ++) - ll[i] = 5; - } - else - { - literalCodes = 257 + READBITS(zs, 5); - distCodes = 1 + READBITS(zs, 5); - l = 4 + READBITS(zs, 4); - - for (j = 0; j < 19; j ++) - ll[j] = 0; - - // Get the decode tree code lengths - // The decode tree is Huffman encoded - - for (j = 0; j < l; j++) - { - ll[border[j]] = READBITS(zs, 3); - } - if (CreateTree(distanceTree, 19, ll)) - return 1; - - // read in literal and distance code lengths - n = literalCodes + distCodes; - i = 0; - while (i < n) - { - j = DecodeValue(zs, distanceTree); - if (j < 16) // length of code in bits (0..15) - ll[i++] = j; - else if (j == 16) - { // repeat last length 3 to 6 times - j = 3 + READBITS(zs, 2); - - if (i + j > n) - return 1; - - l = i ? ll[i-1] : 0; - while (j --) - ll[i++] = l; - } - else - { - if (j == 17) // 3 to 10 zero length codes - j = 3 + READBITS(zs, 3); - else // j == 18: 11 to 138 zero length codes - j = 11 + READBITS(zs, 7); - - if (i + j > n) - return 1; - - while (j --) - ll[i++] = 0; - } - } - } - - - // Can overwrite tree decode tree as it is not used anymore - if (CreateTree(literalTree, literalCodes, &ll[0])) - return 1; - - if(CreateTree(distanceTree, distCodes, &ll[literalCodes])) - return 1; - - return 0; -} - - -// This function consumes a large percentage of time (#3) -// Most output produced by gzip/zlib/etc is dynamic. -int Decompress_DynamicOrFixed(z_stream *zs, char is_fixed) -{ - // Copy lengths for literal codes 257..285 - static const unsigned short cplens[] = { - 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 15, 17, 19, 23, 27, 31, - 35, 43, 51, 59, 67, 83, 99, 115, 131, 163, 195, 227, 258, 0, 0 }; - // Extra bits for literal codes 257..285 - static const unsigned short cplext[] = { - 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2, 2, - 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 0, 99, 99 }; // 99==invalid - // Copy offsets for distance codes 0..29 - static const unsigned short cpdist[] = { - 0x0001, 0x0002, 0x0003, 0x0004, 0x0005, 0x0007, 0x0009, 0x000d, - 0x0011, 0x0019, 0x0021, 0x0031, 0x0041, 0x0061, 0x0081, 0x00c1, - 0x0101, 0x0181, 0x0201, 0x0301, 0x0401, 0x0601, 0x0801, 0x0c01, - 0x1001, 0x1801, 0x2001, 0x3001, 0x4001, 0x6001 }; - // Extra bits for distance codes - static const unsigned short cpdext[] = { - 0, 0, 0, 0, 1, 1, 2, 2, - 3, 3, 4, 4, 5, 5, 6, 6, - 7, 7, 8, 8, 9, 9, 10, 10, - 11, 11, 12, 12, 13, 13 }; - HufNode literalTree[288]; - HufNode distanceTree[32]; - int j, l, dist; - -#ifdef VERBOSE - if (is_fixed) - fprintf(stderr, "Fixed Huffman codes\n"); - else - fprintf(stderr, "Dynamic Huffman codes\n"); -#endif - - if (MakeTrees(zs, is_fixed, literalTree, distanceTree)) - return 1; - - while (1) - { - j = DecodeValue(zs, literalTree); - if (j >= 256) - { - if (j == 256) // EOF - break; - - //printf("%04x ", j); - j -= 256 + 1; // bytes + EOF - - l = READBITS(zs, cplext[j]) + cplens[j]; - //printf("%04x ", l); - - j = DecodeValue(zs, distanceTree); - //printf("%02x ", j); - - dist = READBITS(zs, cpdext[j]) + cpdist[j]; - //printf("%04x ", dist); - - //printf("LZ77 len %d dist %d @%04x\n", l, dist, bIdx); - while(l--) - { - //printf("%02x ", c); - if (! zs->avail_out --) - return -1; - - *(zs->next_out ++) = *(zs->next_out - dist); - } - //printf("\n"); - } - else - { - //printf("%02x\n", j); - if (! zs->avail_out --) - return -1; - *(zs->next_out ++) = (unsigned char) j; - } - } - return 0; -} - - -// Returns 0 if success -int InflateData(z_stream *zs) { - int last, type; - - zs->reserved = 1;; - - do - { - last = READBIT(zs); -#ifdef VERBOSE - if (last) - fprintf(stderr, "Last Block: "); - else - fprintf(stderr, "Not Last Block: "); -#endif - - type = READBITS(zs, 2); - - if (type == 0) - { -#ifdef VERBOSE - fprintf(stderr, "Decompress_Stored.."); -#endif - if (Decompress_Stored(zs)) - return 1; - } - else if (type > 2) - { -#ifdef VERBOSE - if (type == 3) - fprintf(stderr, "Reserved block type!!\n"); - else // the "else" should never happen - fprintf(stderr, "Unexpected value %d!\n", type); -#endif - zs->reserved = 1;; - return 1; - } - else - { -#ifdef VERBOSE - fprintf(stderr, "Decompress_DynamicOrFixed.."); -#endif - if (Decompress_DynamicOrFixed(zs, type & 0x01)) - return 1; - } - } while(!last); - - zs->reserved = 1;; - return 0; -} diff --git a/lib/CPUs/MIPS/bsp/examples/inflate.h b/lib/CPUs/MIPS/bsp/examples/inflate.h deleted file mode 100644 index 1f6fd38..0000000 --- a/lib/CPUs/MIPS/bsp/examples/inflate.h +++ /dev/null @@ -1,15 +0,0 @@ -#ifdef USE_ZLIB_STRUCT -#include "SysZLib.h" // For PalmOS. Change to your liking. -#else -typedef struct z_stream_s -{ - unsigned char *next_in; // Next input byte (CHANGES) - unsigned int avail_in; // number of bytes left at next_in - unsigned char *next_out; // Next output byte goes here (CHANGES) - unsigned int avail_out; // number of bytes left at next_out - unsigned int reserved; // For the readbit() and readbits() functions - // Bigger than 1 byte -} z_stream; -#endif - -int InflateData(z_stream *zs); diff --git a/lib/CPUs/MIPS/bsp/examples/irq.c b/lib/CPUs/MIPS/bsp/examples/irq.c deleted file mode 100644 index 85e1320..0000000 --- a/lib/CPUs/MIPS/bsp/examples/irq.c +++ /dev/null @@ -1,92 +0,0 @@ -#include -#include -#include -#include -#include -#include "libsys.h" -#include "regdef.h" -#include "xcpt.h" -#include "irq.h" - -static fp_irq_t g_irq_handler[MAX_NUM_IRQ] = {NULL}; - -int _irq_dispatch(struct xcptcontext * xcp) -{ - int i, ip, cause; - - cause = xcp->cr & xcp->sr; - ip = (cause >> 8) & 0xFF; - - for (i=0; i < MAX_NUM_IRQ; i++) - { - if (ip & 1) - if (g_irq_handler[i]) - (g_irq_handler[i])(xcp); - - ip >>= 1; - } - - return 0; -} - -void interrupt_register(int irq_num, fp_irq_t fp) -{ - if ((irq_num >= 0) && (irq_num < MAX_NUM_IRQ)) - g_irq_handler[irq_num] = fp; - -} - -void interrupt_enable(int irq_num) -{ - reg_t reg, im; - - if ((irq_num >= 0) && (irq_num < MAX_NUM_IRQ)) - { - im = 1 << irq_num; - reg = CP0_SR_read(); - reg |= (SR_MASK_IM & (im << 8)); - CP0_SR_write(reg); - } - -} - -void interrupt_disable(int irq_num) -{ - reg_t reg, im; - - if ((irq_num >= 0) && (irq_num < MAX_NUM_IRQ)) - { - im = 1 << irq_num; - reg = CP0_SR_read(); - reg &= ~(SR_MASK_IM & (im << 8)); - CP0_SR_write(reg); - } -} - -void interrupt_set(int irq_num) -{ - reg_t reg, ip; - - if ((irq_num >= 0) && (irq_num < MAX_NUM_IRQ)) - { - ip = 1 << irq_num; - reg = CP0_CR_read(); - reg |= (CR_MASK_IP & (ip << 8)); - CP0_CR_write(reg); - } -} - -void interrupt_clr(int irq_num) -{ - reg_t reg, ip; - - if ((irq_num >= 0) && (irq_num < MAX_NUM_IRQ)) - { - ip = 1 << irq_num; - reg = CP0_CR_read(); - reg &= ~(CR_MASK_IP & (ip << 8)); - CP0_CR_write(reg); - } -} - - diff --git a/lib/CPUs/MIPS/bsp/examples/irq.h b/lib/CPUs/MIPS/bsp/examples/irq.h deleted file mode 100644 index d6c343c..0000000 --- a/lib/CPUs/MIPS/bsp/examples/irq.h +++ /dev/null @@ -1,15 +0,0 @@ -#ifndef IRQ_H -#define IRQ_H - -#include "xcpt.h" - -#define MAX_NUM_IRQ 8 - -typedef void (*fp_irq_t)(struct xcptcontext * xcp); - -int _irq_dispatch(struct xcptcontext * xcp); -void interrupt_register(int irq_num, fp_irq_t fp); -void interrupt_enable(int irq_num); -void interrupt_disable(int irq_num); - -#endif // IRQ_H diff --git a/lib/CPUs/MIPS/bsp/examples/isqrt.c b/lib/CPUs/MIPS/bsp/examples/isqrt.c deleted file mode 100644 index 6022fc1..0000000 --- a/lib/CPUs/MIPS/bsp/examples/isqrt.c +++ /dev/null @@ -1,89 +0,0 @@ -/* +++Date last modified: 05-Jul-1997 */ - -#include -#include "snipmath.h" - -#define BITSPERLONG 32 - -#define TOP2BITS(x) ((x & (3L << (BITSPERLONG-2))) >> (BITSPERLONG-2)) - - -/* usqrt: - ENTRY x: unsigned long - EXIT returns floor(sqrt(x) * pow(2, BITSPERLONG/2)) - - Since the square root never uses more than half the bits - of the input, we use the other half of the bits to contain - extra bits of precision after the binary point. - - EXAMPLE - suppose BITSPERLONG = 32 - then usqrt(144) = 786432 = 12 * 65536 - usqrt(32) = 370727 = 5.66 * 65536 - - NOTES - (1) change BITSPERLONG to BITSPERLONG/2 if you do not want - the answer scaled. Indeed, if you want n bits of - precision after the binary point, use BITSPERLONG/2+n. - The code assumes that BITSPERLONG is even. - (2) This is really better off being written in assembly. - The line marked below is really a "arithmetic shift left" - on the double-long value with r in the upper half - and x in the lower half. This operation is typically - expressible in only one or two assembly instructions. - (3) Unrolling this loop is probably not a bad idea. - - ALGORITHM - The calculations are the base-two analogue of the square - root algorithm we all learned in grammar school. Since we're - in base 2, there is only one nontrivial trial multiplier. - - Notice that absolutely no multiplications or divisions are performed. - This means it'll be fast on a wide range of processors. -*/ - -void usqrt(unsigned long x, struct int_sqrt *q) -{ - unsigned long a = 0L; /* accumulator */ - unsigned long r = 0L; /* remainder */ - unsigned long e = 0L; /* trial product */ - - int i; - - for (i = 0; i < BITSPERLONG; i++) /* NOTE 1 */ - { - r = (r << 2) + TOP2BITS(x); x <<= 2; /* NOTE 2 */ - a <<= 1; - e = (a << 1) + 1; - if (r >= e) - { - r -= e; - a++; - } - } - memcpy(q, &a, sizeof(long)); -} - -#ifdef TEST - -#include -#include - -main(void) -{ - int i; - unsigned long l = 0x3fed0169L; - struct int_sqrt q; - - for (i = 0; i < 101; ++i) - { - usqrt(i, &q); - printf("sqrt(%3d) = %2d, remainder = %2d\n", - i, q.sqrt, q.frac); - } - usqrt(l, &q); - printf("\nsqrt(%lX) = %X, remainder = %X\n", l, q.sqrt, q.frac); - return 0; -} - -#endif /* TEST */ diff --git a/lib/CPUs/MIPS/bsp/examples/kernel.S b/lib/CPUs/MIPS/bsp/examples/kernel.S deleted file mode 100644 index aa0648b..0000000 --- a/lib/CPUs/MIPS/bsp/examples/kernel.S +++ /dev/null @@ -1,184 +0,0 @@ -#include -#include - - .section .exc_vect -_xcpt_vector_tbl: - .fill 16, 4, 0 - - .text - -LEAF(_xcpt_handler) - .set noreorder - .set noat - /* Note: exceptions do not save and restore registers k0 and k1. - * on entry, k1 = exception class. - */ - - /* allocate exception stack frame (on 8-byte boundary) */ - subu k1, sp, XCP_SIZE - srl k1, 3 /* shift right/left -> alligned on boundary */ - sll k1, 3 - - /* save enough registers to get by */ - sw AT, XCP_AT(k1) - sw v0, XCP_V0(k1) - sw v1, XCP_V1(k1) - sw a0, XCP_A0(k1) - sw a1, XCP_A1(k1) - sw a2, XCP_A2(k1) - sw a3, XCP_A3(k1) - sw sp, XCP_SP(k1) - sw ra, XCP_RA(k1) - - /* get coprocessor 0 exception state */ - mfc0 a0, CP0_CR - mfc0 a1, CP0_SR - mfc0 a2, CP0_BADDR - mfc0 a3, CP0_EPC - - /* we can safely use AT now */ - .set at - - /* switch to using sp to point at exception frame */ - move sp, k1 - - /* nothing sensible to store for k0/k1, store zero */ - sw zero, XCP_K0(sp) - sw zero, XCP_K1(sp) - - /* we are now interruptible: dump all remaining state - * into the exception stack frame. - */ - /* coprocessor exception state */ - sw a0, XCP_CR(sp) - sw a1, XCP_SR(sp) - sw a2, XCP_BADDR(sp) - sw a3, XCP_EPC(sp) - - /* mdhi and mdlo */ - mfhi v0 - mflo v1 - sw v0, XCP_MDHI(sp) - sw v1, XCP_MDLO(sp) - - /* Save all the other general registers. - * We save zero, s0-s7 and s8 as well, as instruction emulators (e.g. FP - * operations) and debuggers rely on all registers stored together in - * well-defined structure. - */ - sw zero, XCP_ZERO(sp) - sw t0, XCP_T0(sp) - sw t1, XCP_T1(sp) - sw t2, XCP_T2(sp) - sw t3, XCP_T3(sp) - sw t4, XCP_T4(sp) - sw t5, XCP_T5(sp) - sw t6, XCP_T6(sp) - sw t7, XCP_T7(sp) - sw s0, XCP_S0(sp) - sw s1, XCP_S1(sp) - sw s2, XCP_S2(sp) - sw s3, XCP_S3(sp) - sw s4, XCP_S4(sp) - sw s5, XCP_S5(sp) - sw s6, XCP_S6(sp) - sw s7, XCP_S7(sp) - sw t8, XCP_T8(sp) - sw t9, XCP_T9(sp) - sw gp, XCP_GP(sp) - sw s8, XCP_S8(sp) - - /* I don't know what the following does. [rb] */ - /* load our _gp pointer */ -# la gp, _gp - - /* and call the C exception handler */ - move a0, sp # arg1 = &xcp - subu sp, 16 # (arg save area) - j _xcpt_call - move ra, zero # fake return address - - /* This strange call to _xcpt_call with zero return address is to - * help exception-aware debuggers to trace back over the exception event. - * We are basically interposing a bogus stackframe (with a zero return - * address) between the C exception handler and the actual machine - * exception. - */ -$xcptrest: - .set noat - add AT, sp, 16 - - /* at points to exception frame */ -$xcptrestother: - /* restore all state */ - /* restore most general registers */ - lw t0, XCP_T0(AT) - lw t1, XCP_T1(AT) - lw t2, XCP_T2(AT) - lw t3, XCP_T3(AT) - lw t4, XCP_T4(AT) - lw t5, XCP_T5(AT) - lw t6, XCP_T6(AT) - lw t7, XCP_T7(AT) - lw s0, XCP_S0(AT) - lw s1, XCP_S1(AT) - lw s2, XCP_S2(AT) - lw s3, XCP_S3(AT) - lw s4, XCP_S4(AT) - lw s5, XCP_S5(AT) - lw s6, XCP_S6(AT) - lw s7, XCP_S7(AT) - lw t8, XCP_T8(AT) - lw t9, XCP_T9(AT) - lw gp, XCP_GP(AT) - lw s8, XCP_S8(AT) - - /* mdhi and mdlo */ - lw v0, XCP_MDHI(AT) - lw v1, XCP_MDLO(AT) - mthi v0 - mtlo v1 - - /* remaining general registers */ - lw a0, XCP_A0(AT) - lw a1, XCP_A1(AT) - lw a2, XCP_A2(AT) - lw a3, XCP_A3(AT) - lw ra, XCP_RA(AT) - - /* restore the exception-time status register */ - .set noreorder - lw v0, XCP_SR(AT) - nop - mtc0 v0, CP0_SR - lw v1, XCP_V1(AT) - lw v0, XCP_V0(AT) - lw sp, XCP_SP(AT) - - /* we are not uninterruptible and can use k1 safely */ - lw k1, XCP_EPC(AT) - lw AT, XCP_AT(AT) - mtc0 k1, CP0_EPC - j k1 - rfe - - .set reorder - .set at -END(_xcpt_handler) - - -LEAF(_xcpt_call) - /* on entry: a0 == &xcp */ - subu sp, 24 - sw ra, 16(sp) - - /* punt out to _xcpt_deliver */ - jal _xcpt_deliver - nop - lw ra, 16(sp) - addu sp, 24 - beqz ra, $xcptrest - nop - j ra - nop -END(_xcpt_call) diff --git a/lib/CPUs/MIPS/bsp/examples/libsys.c b/lib/CPUs/MIPS/bsp/examples/libsys.c deleted file mode 100644 index 93721da..0000000 --- a/lib/CPUs/MIPS/bsp/examples/libsys.c +++ /dev/null @@ -1,1101 +0,0 @@ -#include -#include -#include -#include -#include -#include -#include -#include "libsys.h" - - -// --------------------------------------------------------------------------------- -// Forward declarations -// --------------------------------------------------------------------------------- -void flush(UINT32 port); -UINT32 GetPort(int file); - -// --------------------------------------------------------------------------------- -// Types -// --------------------------------------------------------------------------------- -void libsys_init(void) -{ - UINT32 volatile *pVGA_ctrl = (UINT32*)SYS_VGA_CTRL; - UINT32 volatile *pITIM_ctrl = (UINT32*)SYS_ITIM_CTRL; - - Screen_clr(); - - // Disable timers - *pITIM_ctrl = 0; - - // Disable all VGA stuff - *pVGA_ctrl = 0; - - // Initialzie syscall support - syscalls_init(); - - // Initalize debugger - dbg_init(); - - // flush stdin - flush(GetPort(0)); - - // Do some initializations here - -} - -UINT32 GetPort(int file) -{ - if (file == 0) - return 0; - - if (file == 1) - return 0; - - if (file == 2) - return 2; -} - -enum -{ - IF_TYPE_INVALID = 0, - IF_TYPE_UART, - IF_TYPE_PS2, - IF_TYPE_VGA -}; - -typedef struct _suart_if_t -{ - volatile UINT32 *pCTRL; - volatile UINT32 *pDATA; - volatile UINT32 *pBAUD; -} uart_if_t; - -typedef struct _sps2_if_t -{ - volatile UINT32 *pCTRL; - volatile UINT32 *pDATA; -} ps2_if_t; - -typedef struct _svga_if_t -{ - volatile UINT32 *pCTRL; - volatile UINT32 *pDATA; - volatile UINT32 *pCSRX; - volatile UINT32 *pCSRY; -} vga_if_t; - -typedef struct _scon_if_in_t -{ - UINT32 type; - void *pIF; -} con_if_in_t; - -typedef struct _scon_if_out_t -{ - UINT32 type; - void *pIF; -} con_if_out_t; - -// --------------------------------------------------------------------------------- -// Globals -// --------------------------------------------------------------------------------- -static uart_if_t uart_if[2] = -{ - {(UINT32*)SYS_UART0_STAT, (UINT32*)SYS_UART0_DATA, (UINT32*)SYS_UART0_BAUD}, - {(UINT32*)SYS_UART1_STAT, (UINT32*)SYS_UART1_DATA, (UINT32*)SYS_UART1_BAUD} -}; - -extern ps2_if_t ps2_if[]; - -static vga_if_t vga_if = -{ - (UINT32*)SYS_VGA_CTRL, (UINT32*)SYS_VGA_ASCII, (UINT32*)SYS_VGA_POSX, (UINT32*)SYS_VGA_POSY -}; - -static con_if_in_t con_if_in[4] = -{ - {IF_TYPE_UART, &uart_if[0]}, - {IF_TYPE_UART, &uart_if[1]}, - {IF_TYPE_PS2, &ps2_if[0]}, - {IF_TYPE_PS2, &ps2_if[1]} -}; - -static con_if_out_t con_if_out[4] = -{ - {IF_TYPE_UART, &uart_if[0]}, - {IF_TYPE_UART, &uart_if[1]}, - {IF_TYPE_VGA, &vga_if}, - {IF_TYPE_INVALID, NULL} -}; - -// --------------------------------------------------------------------------------- -// MIPS specific -// --------------------------------------------------------------------------------- -UINT32 CP0_SR_read(void) -{ - UINT32 result; - - __asm__ - ( - "mfc0 %[val], $12\n" - : [val] "=r" (result) - ); - - return result; -} - -void CP0_SR_write(UINT32 val) -{ - __asm__ - ( - "mtc0 %[val], $12\n" - : /* no output */ - : [val] "r" (val) - ); -} - -UINT32 CP0_CR_read(void) -{ - UINT32 result; - - __asm__ - ( - "mfc0 %[val], $13\n" - : [val] "=r" (result) - ); - - return result; -} - -void CP0_CR_write(UINT32 val) -{ - __asm__ - ( - "mtc0 %[val], $13\n" - : - : [val] "r" (val) - ); -} - -UINT32 CP0_TR_read(void) -{ - UINT32 result; - - __asm__ - ( - "mfc0 %[val], $31\n" - : [val] "=r" (result) - ); - - return result; -} - -void CP0_TR_write(UINT32 val) -{ - __asm__ - ( - "mtc0 %[val], $31\n" - : - : [val] "r" (val) - ); -} - -UINT32 CP0_PRID_read(void) -{ - UINT32 result; - - __asm__ - ( - "mfc0 %[val], $15\n" - : [val] "=r" (result) - ); - - return result; -} - -void CP0_TR_write_ptr(UINT32* pPtr) -{ - __asm__ - ( - "swc0 $31, 0(%[pPtr])\n" - : - : [pPtr] "r" (pPtr) - ); -} - -void CP0_TR_read_ptr(UINT32* pPtr) -{ - __asm__ - ( - "lwc0 $31, 0(%[pPtr])\n" - : - : [pPtr] "r" (pPtr) - ); -} - -void ICACHE_invalidate_all(void) -{ - __asm__ - ( - "cop0 32\n" - ); -} - -void ICACHE_invalidate_at(UINT32* pPtr) -{ - __asm__ - ( - "mtc0 %[pPtr], $31\n" - "cop0 33\n" - : - : [pPtr] "r" (pPtr) - ); -} - -void DCACHE_invalidate_all(void) -{ - __asm__ - ( - "cop0 34\n" - ); -} - -void DCACHE_invalidate_at(UINT32* pPtr) -{ - __asm__ - ( - "mtc0 %[pPtr], $31\n" - "cop0 35\n" - : - : [pPtr] "r" (pPtr) - ); -} - -// ------------------------------------------------------------- -// BEGIN QUICK AND DIRTY -// ------------------------------------------------------------- -//keymap for the AT keyboard SG layout -typedef struct -{ - UINT8 scancode; - UINT8 unshifted; - UINT8 shifted; - UINT8 altered; -} libsys_key_entry_t; - -#define SHIFTED (1<<0) -#define ALTERED (1<<1) -#define CONTROLLED (1<<2) - -static const libsys_key_entry_t __keymap_german[] = -{ - {0x1c, 'a', 'A', 'a'}, - {0x32, 'b', 'B', 'b'}, - {0x21, 'c', 'C', 'c'}, - {0x23, 'd', 'D', 'd'}, - {0x24, 'e', 'E', '€'}, - {0x2b, 'f', 'F', 'f'}, - {0x34, 'g', 'G', 'g'}, - {0x33, 'h', 'H', 'h'}, - {0x43, 'i', 'I', 'i'}, - {0x3b, 'j', 'J', 'j'}, - {0x42, 'k', 'K', 'k'}, - {0x4b, 'l', 'L', 'l'}, - {0x3a, 'm', 'M', 'µ'}, - {0x31, 'n', 'N', 'n'}, - {0x44, 'o', 'O', 'o'}, - {0x4d, 'p', 'P', 'p'}, - {0x15, 'q', 'Q', '@'}, - {0x2d, 'r', 'R', 'r'}, - {0x1b, 's', 'S', 's'}, - {0x2c, 't', 'T', 't'}, - {0x3c, 'u', 'U', 'u'}, - {0x2a, 'v', 'V', 'v'}, - {0x1d, 'w', 'W', 'w'}, - {0x22, 'x', 'X', 'x'}, - {0x1a, 'y', 'Y', 'y'}, - {0x35, 'z', 'Z', 'z'}, - {0x16, '1', '!', '1'}, - {0x1e, '2', '"', '2'}, - {0x26, '3', '§', '3'}, - {0x25, '4', '$', '4'}, - {0x2e, '5', '%', '5'}, - {0x36, '6', '&', '6'}, - {0x3d, '7', '/', '{'}, - {0x3e, '8', '(', '['}, - {0x46, '9', ')', ']'}, - {0x45, '0', '=', '}'}, - {0x4e, 'ß', '?', '\\'}, - {0x29, ' ', ' ', ' '}, - {0x41, ',', ';', ','}, - {0x49, '.', ':', '.'}, - {0x4a, '-', '_', '-'}, - {0x52, 'ä', 'Ä', 'ä'}, - {0x4c, 'ö', 'Ö', 'ö'}, - {0x54, 'ü', 'Ü', 'ü'}, - {0x5a, '\n', '\n', '\n'}, //RETURN - {0x5b, '+', '*', '~'}, - {0x5d, '#', '\'', '#'}, - {0x0e, '^', '°', '^'}, - {0x61, '<', '>', '|'}, - {0x66, '\b', '\b', '\b'}, - {0} //sentinel -}; - -static char __findkey(char scancode, int mode) -{ - const libsys_key_entry_t *p = __keymap_german; - while (p->scancode) - { - if (p->scancode == scancode) - { - switch (mode) - { - case SHIFTED: - return p->shifted; - case ALTERED: - return p->altered; - case ALTERED|SHIFTED: - default: - return p->unshifted; - } - } - p++; - } - return 0; -} - -#define RELEASE 0x8000 -#define SPECIALKEY 0x4000 -#define EXTENDED 0x2000 -#define X_CONTROLLED 0x0400 -#define X_ALTERED 0x0200 -#define X_SHIFTED 0x0100 -#define CAPS (SPECIALKEY|0x58) -#define F1 (SPECIALKEY|0x05) -#define F2 (SPECIALKEY|0x06) -#define F3 (SPECIALKEY|0x04) -#define F4 (SPECIALKEY|0x0c) -#define F5 (SPECIALKEY|0x03) -#define F6 (SPECIALKEY|0x0b) -#define F7 (SPECIALKEY|0x83) -#define F8 (SPECIALKEY|0x0a) -#define F9 (SPECIALKEY|0x01) -#define F10 (SPECIALKEY|0x09) -#define F11 (SPECIALKEY|0x78) -#define F12 (SPECIALKEY|0x07) -#define ARROW_UP (SPECIALKEY|EXTENDED|0x75) -#define ARROW_DOWN (SPECIALKEY|EXTENDED|0x72) -#define ARROW_LEFT (SPECIALKEY|EXTENDED|0x6b) -#define ARROW_RIGHT (SPECIALKEY|EXTENDED|0x74) - -UINT32 PS2_readchar(ps2_if_t *pIF) -{ - if (!pIF) - return -1; - - while (!(SYS_PS2_BIT_RX_AVAIL & *pIF->pCTRL)); - - return (*pIF->pDATA & 0xFF); - -} - -UINT32 con_readchar(ps2_if_t *pIF) -{ - UINT8 c; - static char mode = 0; - static char nextrelease = 0; - static char extended = 0; - int flags = 0; - int char_valid = 0; - UINT8 key; - - key = PS2_readchar(pIF); - - switch (key) - { - case 0xf0: //release key - nextrelease = 1; - break; - case 0x14: //control key - if (nextrelease) - { - mode &= ~CONTROLLED; - } else - { - mode |= CONTROLLED; - } - nextrelease = 0; - break; - case 0x12: //left SHIFT - case 0x59: //right SHIFT - if (nextrelease) - { - mode &= ~SHIFTED; - } else - { - mode |= SHIFTED; - } - nextrelease = 0; - break; - case 0x11: //left and right ALT (right one also with E0) - if (nextrelease) - { - mode &= ~ALTERED; - } else - { - mode |= ALTERED; - } - nextrelease = 0; - break; - case 0xe0: //extended key following - extended = 1; - break; - default: - if (nextrelease) flags |= RELEASE; - if (extended) flags |= EXTENDED; - flags |= mode << 8; - c = __findkey(key, mode); - char_valid = (c && ((flags & RELEASE) != RELEASE)); - nextrelease = 0; - extended = 0; - break; - } - - if (char_valid) - { - // fprintf(stderr, "c = %c (%d), flags = 0x%08X, mode = 0x%08X\n", c, c, flags, mode); - return c; - } - - return -1; -} -// ------------------------------------------------------------- -// END QUICK AND DIRTY -// ------------------------------------------------------------- - -// ------------------------------------ -// Low-level I/O -// ------------------------------------ -int UART_readchar(uart_if_t *pIF) -{ - if (!pIF) - return -1; - - if (SYS_UART_BIT_RX_AVAIL & *pIF->pCTRL) - return (*pIF->pDATA & 0xFF); - - return -1; -} - -void UART_writechar(uart_if_t *pIF, char c) -{ - if (!pIF) - return; - - while((SYS_UART_BIT_TX_HALFFULL & *pIF->pCTRL) != 0); - - *pIF->pDATA = (UINT32)c; -} - -void cg_writechar(vga_if_t *pIF, char c) -{ - UINT32 code; - - if (!pIF) - return; - - // Output translation - switch(c) - { - case 'Ä': - code = 196; - break; - - case 'ä': - code = 228; - break; - - case 'Ö': - code = 214; - break; - - case 'ö': - code = 246; - break; - - case 'Ü': - code = 220; - break; - - case 'ü': - code = 252; - break; - - case '&': - code = 230; - break; - - case '§': - code = 167; - break; - - case 'ß': - code = 223; - break; - - case '°': - code = 176; - break; - - case 'µ': - code = 181; - break; - - default: - code = (UINT32)c; - break; - } - - while (!(*pIF->pCTRL & SYS_VGA_BIT_CGRDY)); - *pIF->pDATA = code; -} - -void cg_set_csr_x(vga_if_t *pIF, UINT32 coord) -{ - if (!pIF) - return; - - // Set cursor - while (!(*pIF->pCTRL & SYS_VGA_BIT_CGRDY)); - *pIF->pCSRX = coord; -} - -void cg_set_csr_y(vga_if_t *pIF, UINT32 coord) -{ - if (!pIF) - return; - - // Set cursor - while (!(*pIF->pCTRL & SYS_VGA_BIT_CGRDY)); - *pIF->pCSRY = coord; -} - -void cg_clr_line(vga_if_t *pIF) -{ - if (!pIF) - return; - - while (!(*pIF->pCTRL & SYS_VGA_BIT_CGRDY)); - *pIF->pCTRL |= SYS_VGA_BIT_CLRLINE; -} - -void cg_clr_screen(vga_if_t *pIF) -{ - - if (!pIF) - return; - - while (!(*pIF->pCTRL & SYS_VGA_BIT_CGRDY)); - *pIF->pCTRL |= SYS_VGA_BIT_CLRSCR; - - // Cursor home - while (!(*pIF->pCTRL & SYS_VGA_BIT_CGRDY)); - *pIF->pCSRX = 0; - - while (!(*pIF->pCTRL & SYS_VGA_BIT_CGRDY)); - *pIF->pCSRY = 0; - -} - -void Screen_clr(void) -{ - cg_clr_screen(&vga_if); -} - -void Screen_line_clr(void) -{ - cg_clr_line(&vga_if); -} - -void Screen_csr_set_x(UINT32 coord) -{ - cg_set_csr_x(&vga_if, coord); -} - -void Screen_csr_set_y(UINT32 coord) -{ - cg_set_csr_y(&vga_if, coord); -} - -UINT32 Screen_get_resx(void) -{ - UINT32 volatile *pVGA_res = (UINT32*)SYS_VGA_RES; - - return (0xFFF & (*pVGA_res >> 0)); -} - -UINT32 Screen_get_resy(void) -{ - UINT32 volatile *pVGA_res = (UINT32*)SYS_VGA_RES; - - return (0xFFF & (*pVGA_res >> 12)); -} - -UINT32 Screen_get_fps(void) -{ - UINT32 volatile *pVGA_res = (UINT32*)SYS_VGA_RES; - - return (0xFF & (*pVGA_res >> 24)); -} - -// --------------------------------------------------------------------------------- -void flush(UINT32 port) -{ - int c; - con_if_in_t *pIF; - - pIF = &con_if_in[port]; - - do - { - switch(pIF->type) - { - case IF_TYPE_UART: - c = UART_readchar((uart_if_t*)pIF->pIF); - break; - - case IF_TYPE_PS2: - c = con_readchar((ps2_if_t*)pIF->pIF); - break; - - default: - break; - } - - } while(c > 0); -} - -char readchar(UINT32 port) -{ - int c; - con_if_in_t *pIF; - - pIF = &con_if_in[port]; - - do - { - switch(pIF->type) - { - case IF_TYPE_UART: - c = UART_readchar((uart_if_t*)pIF->pIF); - break; - - case IF_TYPE_PS2: - c = con_readchar((ps2_if_t*)pIF->pIF); - break; - - default: - break; - } - - } while(c < 0); - - return (char)c; -} - -void writechar(UINT32 port, char c) -{ - con_if_out_t *pIF; - - pIF = &con_if_out[port]; - - switch(pIF->type) - { - case IF_TYPE_UART: - UART_writechar((uart_if_t*)pIF->pIF, c); - break; - - case IF_TYPE_VGA: - cg_writechar((vga_if_t*)pIF->pIF, c); - break; - - default: - break; - } -} - -void _putchar(UINT32 port, char c) -{ - - con_if_out_t *pIF; - - pIF = &con_if_out[port]; - - switch(pIF->type) - { - case IF_TYPE_UART: - if (c == 0x0A) - UART_writechar((uart_if_t*)pIF->pIF, 0x0D); - UART_writechar((uart_if_t*)pIF->pIF, c); - break; - - case IF_TYPE_VGA: - cg_writechar((vga_if_t*)pIF->pIF, c); - if (c == 0x0A) - { - cg_clr_line((vga_if_t*)pIF->pIF); - cg_writechar((vga_if_t*)pIF->pIF, 0x0D); - } - break; - - default: - break; - } -} - -char _getchar(void) -{ - return readchar(GetPort(0)); -} - -void _exit (int exitcode) -{ - fflush(stdout); - fflush(stderr); - while(1); -} - -void sleep(unsigned ms) -{ - unsigned stop; - struct tms t; - - times(&t); - stop = t.tms_utime + ms; - - do - { - times(&t); - } while (t.tms_utime < stop); - -} - - -int getrusage(int who, struct rusage *usage) -{ - volatile long *pReg_usec = (long*)SYS_TIMER_USEC; - volatile long *pReg_sec = (long*)SYS_TIMER_SEC; - - // who: RUSAGE_SELF or RUSAGE_CHILDREN - usage->ru_utime.tv_usec = *pReg_usec; - usage->ru_utime.tv_sec = *pReg_sec; - usage->ru_stime.tv_usec = *pReg_usec; - usage->ru_stime.tv_sec = *pReg_sec; -} - -clock_t times(struct tms *buffer) -{ - volatile long *pReg_usec = (long*)SYS_TIMER_USEC; - volatile long *pReg_sec = (long*)SYS_TIMER_SEC; - long sec; - long usec; - - sec = *pReg_sec; - usec = *pReg_usec; - - if (buffer) - { - buffer->tms_utime = sec*1000 + usec/1000; - buffer->tms_stime = 0; - buffer->tms_cutime = 0; - buffer->tms_cstime = 0; - } - - return (clock_t)sec; -} - -int gettimeofday(struct timeval *tp, void *tzp) -{ - volatile long *pReg_usec = (long*)SYS_TIMER_USEC; - volatile long *pReg_sec = (long*)SYS_TIMER_SEC; - - if (tp) - { - tp->tv_sec = *pReg_sec; - tp->tv_usec = *pReg_usec; - } - - return 0; -} - -int settimeofday(const struct timeval *tp, const struct timezone *tzp) -{ - volatile long *pReg_usec = (long*)SYS_TIMER_USEC; - volatile long *pReg_sec = (long*)SYS_TIMER_SEC; - div_t res; - - res = div(tp->tv_usec, 1E6); - - if (tp) - { - *pReg_usec = res.rem; - *pReg_sec = tp->tv_sec + res.quot; - } - - return 0; -} - -caddr_t sbrk(int incr) -{ - extern char end; - extern char stack_ptr; - static char *heap_end; - char *prev_heap_end; - - if (heap_end == 0) - { - heap_end = &end; - } - - prev_heap_end = heap_end; - if (heap_end + incr > &stack_ptr) - { -// sputs("Heap and stack collision\n"); -// sputs("Stack Ptr = ");print_word(&stack_ptr);sputs("\n"); -// sputs("Heap end = ");print_word(heap_end);sputs("\n"); -// sputs("Increment = ");print_word(incr);sputs("\n"); - exit(1); - } - heap_end += incr; - return (caddr_t) prev_heap_end; -} - -int fstat(int file, struct stat *st) -{ -// sputs("fstat ("); print_word(file); sputs(")\n"); - st->st_mode = S_IFCHR; - st->st_blksize = 0; - return 0; -} - -int lseek(int file, int ptr, int dir) -{ -// sputs("lseek ("); print_word(file); sputs(")\n"); - errno = ESPIPE; - return -1; -} - -int open(const char *name, int flags, int mode) -{ -// sputs("open (\""); sputs(name); sputs("\")\n"); - errno = EIO; - return -1; -} - -int close(int file) -{ -// sputs("close ("); print_word(file); sputs(")\n"); - return 0; -} - -int read(int file, char *ptr, int len) -{ - UINT32 port; - int i; - char c; - -// sputs("read (file="); print_word(file); sputs(", len ="); print_word(len); sputs(")\n"); - i = 0; - port = GetPort(file); - - while (i < len) - { - c = readchar(port); - - if (c == 0x04) - break; - - if ((c == 0x0D) || (c == 0x0A)) - { - writechar(port, 0x0D); - ptr[i++] = 0x0D; - writechar(port, 0x0A); - ptr[i++] = 0x0A; - break; - } - - writechar(port, c); - ptr[i++] = c; - - } - return i; -} - -int write(int file, char *ptr, int len) -{ - UINT32 port; - int i = 0; - -// sputs("write ("); print_word(file); sputs(")\n"); - - port = GetPort(file); - for (i=0; i < len; i++) - _putchar(port, *ptr++); - - return i; -} - -int isatty(int file) -{ -// sputs("isatty ("); print_word(file); sputs(")\n"); - return 1; -} - -int getpid(void) -{ - return 1; -} - -#include -#undef errno -extern int errno; -int kill(int pid, int sig) -{ - errno = EINVAL; - return -1; -} - -#include -#undef errno -extern int errno; -int link(char *old, char *new) -{ - errno = EMLINK; - return -1; -} - -#include -#undef errno -extern int errno; -int unlink(char *name) -{ - errno = ENOENT; - return -1; -} - -int sputs(char *pStr) -{ - char *start; - start = pStr; - - while(*pStr) - _putchar(GetPort(0), *(pStr++)); - - return pStr - start; -} - -void print_byte(char byte) -{ - int i; - unsigned char c, nibble; - - for (i=0; i < 2; i++) - { - nibble = (char)((byte >> 4) & 0xF); - byte <<= 4; - - if (nibble < 10) - c = nibble + '0'; - else - c = nibble + 'A' - 10; - - _putchar(GetPort(0), c); - } -} - -void print_word(int word) -{ - int i; - unsigned char c, nibble; - - for (i=0; i < 4; i++) - { - c = (char) (word >> 24); - print_byte(c); - word <<= 8; - } -} - -// --------------------------------------------------------------------------------- -// PrintBuffer8() -// Prints byte buffer as hex and ascii interpretation -// --------------------------------------------------------------------------------- -// _Parameters : -// pBuf: : IN: Buffer to display -// nbpr : Number of bytes per row to display -// len : Length of input buffer -// _Return: none -// -// --------------------------------------------------------------------------- -void PrintBuffer8(UINT8 *pBuf, int nbpr, int len) -{ - memdump(pBuf, 1, nbpr, len); -} - -void memdump(UINT8 *pBuf, int print_offset_only, int num_bytes_per_row, int len) -{ - int i, j, cnt_hex, cnt_asc, base; - unsigned char c; - - i = j = 0; - cnt_hex = len; - cnt_asc = len; - base = 0; - if (!print_offset_only) - base = (int)pBuf; - - do - { - print_word(base + i); - sputs(": "); - for (j=0; j < num_bytes_per_row; j++) - { - if (cnt_hex) - { - print_byte(pBuf[i+j]); - sputs(" "); - cnt_hex--; - } - else - { - sputs(" "); - break; - } - - } - - sputs(" "); - for (j=0; j < num_bytes_per_row; j++) - { - if (cnt_asc) - { - c = pBuf[i+j]; - if((c < 0x20) || (c > 0x7F)) - c = '.'; - - _putchar(GetPort(0), c); - cnt_asc--; - } - else - { - sputs(" "); - break; - } - } - sputs("\n"); - i += num_bytes_per_row; - - } while (cnt_hex); -} - diff --git a/lib/CPUs/MIPS/bsp/examples/libsys.h b/lib/CPUs/MIPS/bsp/examples/libsys.h deleted file mode 100644 index d14d2d9..0000000 --- a/lib/CPUs/MIPS/bsp/examples/libsys.h +++ /dev/null @@ -1,187 +0,0 @@ -#ifndef LIBSYS_H -#define LIBSYS_H - -// --------------------------------------------------------- -// Types -// --------------------------------------------------------- -#define INT8 signed char -#define INT16 signed short -#define INT32 signed int -#define INT64 signed long long -#define UINT8 unsigned char -#define UINT16 unsigned short -#define UINT32 unsigned int -#define UINT64 unsigned long long -#define INT INT32 -#define UINT UINT32 -#define FLOAT32 float -#define FLOAT64 double - -#define NO_ERROR LSYS_SUCCESS -#define ERROR LSYS_ERR_BASE -#define LSYS_SUCCESS 0 -#define LSYS_ERR_BASE 0x80000000 - -#define IS_ERROR(e) ((e & LSYS_ERR_BASE) == LSYS_ERR_BASE) - -// GPIO -#define SYS_GPIO0 0xA0000000 -#define SYS_GPIO1 0xA0000004 -#define SYS_LED_PORT SYS_GPIO0 -#define SYS_USB_CTRL SYS_GPIO1 -#define SYS_TIMER_USEC 0xA0000008 -#define SYS_TIMER_SEC 0xA000000C - -// TIMERs -#define SYS_ITIM_CTRL 0xA0000018 -#define SYS_ITIM_STAT 0xA000001C -#define SYS_ITIM0_CNT 0xA0000020 -#define SYS_ITIM1_CNT 0xA0000024 -#define SYS_ITIM2_CNT 0xA0000028 -#define SYS_ITIM3_CNT 0xA000002C -#define SYS_ITIM0_CMP 0xA0000030 -#define SYS_ITIM1_CMP 0xA0000034 -#define SYS_ITIM2_CMP 0xA0000038 -#define SYS_ITIM3_CMP 0xA000003C - -// UARTs -#define SYS_UART_BIT_TX_HALFFULL 0x00000001 -#define SYS_UART_BIT_TX_FULL 0x00000002 -#define SYS_UART_BIT_RX_HALFFULL 0x00000004 -#define SYS_UART_BIT_RX_FULL 0x00000008 -#define SYS_UART_BIT_RX_AVAIL 0x00000010 -#define SYS_UART_BIT_TX_INTEN 0x00000020 -#define SYS_UART_BIT_RX_INTEN 0x00000040 -#define SYS_UART_BIT_TX_IRQ 0x00000100 -#define SYS_UART_BIT_RX_IRQ 0x00000200 -#define SYS_UART_DATA SYS_UART0_DATA -#define SYS_UART_STAT SYS_UART0_STAT -#define SYS_UART_BAUD SYS_UART0_BAUD -#define SYS_UART0_DATA 0xA0010000 -#define SYS_UART0_STAT 0xA0010004 -#define SYS_UART0_BAUD 0xA0010008 -#define SYS_UART1_DATA 0xA0010100 -#define SYS_UART1_STAT 0xA0010104 -#define SYS_UART1_BAUD 0xA0010108 - -// PS2s -#define SYS_PS2_BIT_TX_EMPTY 0x00000001 -#define SYS_PS2_BIT_RX_AVAIL 0x00000004 -#define SYS_PS2_BIT_PIN_CLOCK 0x00000008 -#define SYS_PS2_BIT_PIN_DATA 0x00000010 -#define SYS_PS2_BIT_TX_INTEN 0x00000020 -#define SYS_PS2_BIT_RX_INTEN 0x00000040 -#define SYS_PS2_BIT_TX_IRQ 0x00000100 -#define SYS_PS2_BIT_RX_IRQ 0x00000200 -#define SYS_PS2_BIT_RX_ERR_PAR 0x00000800 -#define SYS_PS2_BIT_RX_ERR_FLAG 0x00008000 -#define SYS_PS2_0_DATA 0xA0010200 -#define SYS_PS2_0_STAT 0xA0010204 -#define SYS_PS2_1_DATA 0xA0010300 -#define SYS_PS2_1_STAT 0xA0010304 - -// USB -#define SYS_USB_DATA 0xA0020000 -#define SYS_USB_MBX 0xA0020004 -#define SYS_USB_ADDR 0xA0020008 -#define SYS_USB_STATUS 0xA002000C - -// VGA -#define SYS_VGA_CTRL 0xA0030000 // R/W -#define SYS_VGA_BIT_CGRDY 0x00000001 // RO -#define SYS_VGA_BIT_MSTEN 0x00000002 // R/W -#define SYS_VGA_BIT_BUFCHG_INTEN 0x00000004 // RO -#define SYS_VGA_BIT_BUFCHG_FLAG 0x00000008 // RO -#define SYS_VGA_BIT_CLRSCR 0x00000010 // WO -#define SYS_VGA_BIT_CLRLINE 0x00000020 // WO -#define SYS_VGA_BIT_BLIT_REQ 0x00000100 // R/W -#define SYS_VGA_BIT_BLIT_BSY 0x00000100 // R/W -#define SYS_VGA_BIT_BLIT_FIN 0x00000200 // R/W -#define SYS_VGA_BIT_BLIT_ACK 0x00000200 // R/W -#define SYS_VGA_BIT_BLIT_FIN_INTEN 0x00000400 // R/W -#define SYS_VGA_ASCII 0xA0030004 // R/W -#define SYS_VGA_POSX 0xA0030008 // R/W -#define SYS_VGA_POSY 0xA003000C // R/W -#define SYS_VGA_CGCOL 0xA0030010 // R/W -#define SYS_VGA_RES 0xA0030014 // RO -#define SYS_VGA_FB_FRONT 0xA0030018 // R/W -#define SYS_VGA_FB_BACK 0xA003001C // R/W -#define SYS_VGA_BLIT_SRC0 SYS_VGA_BLIT_SRC0_FIRST // R/W -#define SYS_VGA_BLIT_SRC0_FIRST 0xA0030020 // R/W -#define SYS_VGA_BLIT_SRC0_LAST 0xA0030024 // R/W -#define SYS_VGA_BLIT_SRC0_DIMX 0xA0030028 // R/W -#define SYS_VGA_BLIT_DST SYS_VGA_BLIT_DST_FIRST // R/W -#define SYS_VGA_BLIT_DST_FIRST 0xA0030050 // R/W -#define SYS_VGA_BLIT_DST_LAST 0xA0030054 // R/W -#define SYS_VGA_BLIT_DST_DIMX 0xA0030058 // R/W -#define SYS_VGA_BLIT_NX 0xA0030060 // R/W -#define SYS_VGA_BLIT_NY 0xA0030064 // R/W - -// AC'97 -#define SYS_AC97_STAT 0xA0040000 -#define SYS_AC97_CTRL 0xA0040000 -#define SYS_AC97_ACSTAT 0xA0040400 -#define SYS_AC97_ACCTRL 0xA0040600 -#define SYS_AC97_PCM 0xA0040800 -#define SYS_AC97_WAVIN SYS_AC97_PCM -#define SYS_AC97_WAVOUT SYS_AC97_PCM - -// Flash -#define SYS_FLASH_IO 0xA4000000 -#define SYS_FLASH_MEM 0x00000000 - -// Sync. SRAM -#define SYS_SSRAM_IO 0xA8000000 - -UINT32 CP0_SR_read(void); -void CP0_SR_write(UINT32 val); -UINT32 CP0_CR_read(void); -void CP0_CR_write(UINT32 val); -UINT32 CP0_PRID_read(void); -UINT32 CP0_TR_read(void); -void CP0_TR_write(UINT32 val); -void CP0_TR_write_ptr(UINT32* pPtr); -void CP0_TR_read_ptr(UINT32* pPtr); -void ICACHE_invalidate_all(void); -void ICACHE_invalidate_at(UINT32* pPtr); -void DCACHE_invalidate_all(void); -void DCACHE_invalidate_at(UINT32* pPtr); - -#define CALC_BAUD(b) \ - ((UINT32)((float)CPU_FREQ_HZ/(16*b) + 0.5f) - 1); - -#define UART0_setbaud(b) \ - *((UINT32*)SYS_UART0_BAUD) = CALC_BAUD(b); - -#define UART1_setbaud(b) \ - *((UINT32*)SYS_UART1_BAUD) = CALC_BAUD(b); - -#define UART2_setbaud(b) \ - *((UINT32*)SYS_UART2_BAUD) = CALC_BAUD(b); - -char readchar(UINT32 port); -void writechar(UINT32 port, char c); -int write(int file, char *ptr, int len); -int sputs(char *pStr); -void print_byte(char byte); -void print_word(int word); -void _exit (int exitcode); -void sleep(unsigned ms); - -char _getchar(void); - -void PrintBuffer8(UINT8 *pBuf, int nbpr, int len); -void memdump(UINT8 *pBuf, int print_offset_only, int num_bytes_per_row, int len); - -void Screen_clr(void); -void Screen_line_clr(void); -void Screen_csr_set_x(UINT32 coord); -void Screen_csr_set_y(UINT32 coord); -UINT32 Screen_get_resx(void); -UINT32 Screen_get_resy(void); -UINT32 Screen_get_fps(void); - - - -#endif // LIBSYS_H - diff --git a/lib/CPUs/MIPS/bsp/examples/libsys/.directory_history b/lib/CPUs/MIPS/bsp/examples/libsys/.directory_history deleted file mode 100644 index f347082..0000000 --- a/lib/CPUs/MIPS/bsp/examples/libsys/.directory_history +++ /dev/null @@ -1,70 +0,0 @@ -VHDL/lib/CPUs/MIPS/bsp/examples/dbg.c -VHDL/lib/CPUs/MIPS/bsp/examples/libsys/dbg.c -VHDL/lib/CPUs/MIPS/bsp/examples/irq.c -VHDL/lib/CPUs/MIPS/bsp/examples/libsys/irq.c -VHDL/lib/CPUs/MIPS/bsp/examples/irq.h -VHDL/lib/CPUs/MIPS/bsp/examples/libsys/irq.h -VHDL/lib/CPUs/MIPS/bsp/examples/kernel.S -VHDL/lib/CPUs/MIPS/bsp/examples/libsys/kernel.S -VHDL/lib/CPUs/MIPS/bsp/examples/libsys.c -VHDL/lib/CPUs/MIPS/bsp/examples/libsys/libsys.c -VHDL/lib/CPUs/MIPS/bsp/examples/libsys.h -VHDL/lib/CPUs/MIPS/bsp/examples/libsys/libsys.h -VHDL/lib/CPUs/MIPS/bsp/examples/libsys/dbg.c - -VHDL/lib/CPUs/MIPS/bsp/examples/libsys/irq.c - -VHDL/lib/CPUs/MIPS/bsp/examples/libsys/irq.h - -VHDL/lib/CPUs/MIPS/bsp/examples/libsys/kernel.S - -VHDL/lib/CPUs/MIPS/bsp/examples/libsys/libsys.c - -VHDL/lib/CPUs/MIPS/bsp/examples/libsys/libsys.h - -VHDL/lib/CPUs/MIPS/bsp/examples/libsys/mips_dis.c - -VHDL/lib/CPUs/MIPS/bsp/examples/libsys/mips_dis.h - -VHDL/lib/CPUs/MIPS/bsp/examples/libsys/mips_gfx.c - -VHDL/lib/CPUs/MIPS/bsp/examples/libsys/mips_gfx.h - -VHDL/lib/CPUs/MIPS/bsp/examples/libsys/mips_ps2.c - -VHDL/lib/CPUs/MIPS/bsp/examples/libsys/mips_ps2.h - -VHDL/lib/CPUs/MIPS/bsp/examples/libsys/mips_xcpt.c - -VHDL/lib/CPUs/MIPS/bsp/examples/libsys/regdef.h - -VHDL/lib/CPUs/MIPS/bsp/examples/libsys/startup.S - -VHDL/lib/CPUs/MIPS/bsp/examples/libsys/xcpt.c - -VHDL/lib/CPUs/MIPS/bsp/examples/libsys/xcpt.h - -VHDL/lib/CPUs/MIPS/bsp/examples/libsys/xcpt_asm.h - -VHDL/lib/CPUs/MIPS/bsp/examples/mips_gfx.c -VHDL/lib/CPUs/MIPS/bsp/examples/libsys/mips_gfx.c -VHDL/lib/CPUs/MIPS/bsp/examples/mips_gfx.h -VHDL/lib/CPUs/MIPS/bsp/examples/libsys/mips_gfx.h -VHDL/lib/CPUs/MIPS/bsp/examples/mips_ps2.c -VHDL/lib/CPUs/MIPS/bsp/examples/libsys/mips_ps2.c -VHDL/lib/CPUs/MIPS/bsp/examples/mips_ps2.h -VHDL/lib/CPUs/MIPS/bsp/examples/libsys/mips_ps2.h -VHDL/lib/CPUs/MIPS/bsp/examples/mipsdis.c -VHDL/lib/CPUs/MIPS/bsp/examples/libsys/mips_dis.c -VHDL/lib/CPUs/MIPS/bsp/examples/mipsdis.h -VHDL/lib/CPUs/MIPS/bsp/examples/libsys/mips_dis.h -VHDL/lib/CPUs/MIPS/bsp/examples/regdef.h -VHDL/lib/CPUs/MIPS/bsp/examples/libsys/regdef.h -VHDL/lib/CPUs/MIPS/bsp/examples/startup.S -VHDL/lib/CPUs/MIPS/bsp/examples/libsys/startup.S -VHDL/lib/CPUs/MIPS/bsp/examples/xcpt.c -VHDL/lib/CPUs/MIPS/bsp/examples/libsys/xcpt.c -VHDL/lib/CPUs/MIPS/bsp/examples/xcpt.h -VHDL/lib/CPUs/MIPS/bsp/examples/libsys/xcpt.h -VHDL/lib/CPUs/MIPS/bsp/examples/xcpt_asm.h -VHDL/lib/CPUs/MIPS/bsp/examples/libsys/xcpt_asm.h diff --git a/lib/CPUs/MIPS/bsp/examples/libsys/Makefile b/lib/CPUs/MIPS/bsp/examples/libsys/Makefile deleted file mode 100644 index 376b961..0000000 --- a/lib/CPUs/MIPS/bsp/examples/libsys/Makefile +++ /dev/null @@ -1,29 +0,0 @@ -ENDIAN_FLAGS=-EL -CFLAGS=$(ENDIAN_FLAGS) -msoft-float -O2 -march=r3000 -I. -Wl,-M - -AS=mipsel-elf-as -AR=mipsel-elf-ar -CC=mipsel-elf-gcc -LD=mipsel-elf-ld -OBJDUMP=mipsel-elf-objdump -OBJCOPY=mipsel-elf-objcopy -FLASHGEN=flashgen - -SRCS=libsys.c xcpt.c syscalls.c irq.c dbg.c mips_dis.c mips_gfx.c mips_ps2.c -OBJS=libsys.o xcpt.o syscalls.o irq.o dbg.o mips_dis.o mips_gfx.o mips_ps2.o - -all: libsys.a - $(MAKE) -C eb - -%.o : %.c %.h - $(CC) $(CFLAGS) -G 0 -c $(SRCS) - -libsys.a: $(OBJS) - $(AR) -r libsys.a $(OBJS) - $(CC) $(CFLAGS) -G 0 -c startup.S - $(CC) $(CFLAGS) -G 0 -c kernel.S - -clean: - rm -rf *.a *.o *.map *.dis *.elf > /dev/null - $(MAKE) -C eb clean - diff --git a/lib/CPUs/MIPS/bsp/examples/libsys/mips_ps2.c b/lib/CPUs/MIPS/bsp/examples/libsys/mips_ps2.c deleted file mode 100644 index 960c240..0000000 --- a/lib/CPUs/MIPS/bsp/examples/libsys/mips_ps2.c +++ /dev/null @@ -1,268 +0,0 @@ -#include -#include -#include -#include "libsys.h" -#include "mips_ps2.h" - -ps2_if_t ps2_if[2] = -{ - {ps2_type_unknown, (UINT32*)SYS_PS2_0_STAT, (UINT32*)SYS_PS2_0_DATA}, - {ps2_type_unknown, (UINT32*)SYS_PS2_1_STAT, (UINT32*)SYS_PS2_1_DATA} -}; - -UINT32 PS2_get_num_if(void) -{ - return (sizeof(ps2_if)/sizeof(ps2_if_t)); -} - -ps2_if_t *PS2_get_if(UINT32 port) -{ - if (port < PS2_get_num_if()) - return &ps2_if[port]; - - return NULL; -} - -void PS2_byte_write(UINT32 port, UINT8 byte) -{ - ps2_if_t *pIF; - - pIF = &ps2_if[port]; - - while(!(*pIF->pCTRL & SYS_PS2_BIT_TX_EMPTY)); - - *pIF->pDATA = (UINT32)byte; -} - -UINT32 PS2_byte_read(UINT32 port, UINT32 timeout_ms) -{ - ps2_if_t *pIF; - - pIF = &ps2_if[port]; - - while(!(*pIF->pCTRL & SYS_PS2_BIT_RX_AVAIL)) - { - timeout_ms--; - if (!timeout_ms) - return PS2_ERR_TIMEOUT; - - sleep(1); - } - return (UINT32)*pIF->pDATA; -} - -UINT32 PS2_cmd(UINT32 port, UINT8 cmd, UINT32 ack_timeout_ms) -{ - UINT32 result; - - PS2_byte_write(port, cmd); - result = PS2_byte_read(port, ack_timeout_ms); - if (0xFA != result) - { - printf ("PS2_cmd(%d): no ACK received. Result = %08X\n", port, result); - return PS2_ERR_PS2_PREFIX | result; - } - return 0; -} - -void PS2_flush(UINT32 port) -{ - while (!IS_ERROR(PS2_byte_read(port, 10))); -} - -UINT32 PS2_init(UINT32 port) -{ - int i; - ps2_if_t *pIF; - UINT8 id[2]; - - pIF = &ps2_if[port]; - pIF->type = ps2_type_unknown; - - UINT32 result; - - // Disable RX-interrupt - *pIF->pCTRL &= ~SYS_PS2_BIT_RX_INTEN; - - printf ("PS2_init(%d) - Initialize... ", port); - - // Flush buffer - PS2_flush(port); - - // send RESET - result = PS2_cmd(port, 0xFF, 1000); - if (IS_ERROR(result)) - { - printf ("Reset error %08X\n", result); - return result; - } - - // Read BAT - result = PS2_byte_read(port, 1000); - if (0xAA != result) - { - printf ("BAT error %08X\n", result); - return result; - } - - printf ("Success\n"); - - while(1) - { - // Read ID - result = PS2_byte_read(port, 10); - if (IS_ERROR(result)) - { - // No ID => keyboard - printf ("PS2_init(%d) - Keyboard detected\n", port); - - // send Get Device-ID - result = PS2_cmd(port, 0xF2, 1000); - if (IS_ERROR(result)) - { - printf ("Get Device-ID error %08X\n", result); - break; - } - id[0] = PS2_byte_read(port, 1000); - id[1] = PS2_byte_read(port, 1000); - printf ("PS2_init(%d) - Device-ID: %02X%02X\n", port, id[0], id[1]); - - // Get Scan code set (phase 1) - result = PS2_cmd(port, 0xF0, 1000); - if (IS_ERROR(result)) - { - printf ("1. Get Scan code error %08X\n", result); - break; - } - // Get Scan code set (phase 2) - result = PS2_cmd(port, 0x00, 1000); - if (IS_ERROR(result)) - { - printf ("2. Get Scan code error %08X\n", result); - break; - } - result = PS2_byte_read(port, 1000); - printf ("PS2_init(%d) - Current scan code set = %d\n", port, result); - - // if Scan code SET != 2 - if (result != 2) - { - printf ("PS2_init(%d) - Set scan code set = 2\n", port); - // Set Scan code set (phase 1) - result = PS2_cmd(port, 0xF0, 1000); - if (IS_ERROR(result)) - { - printf ("1. Set Scan code error %08X\n", result); - break; - } - // Set Scan code set (phase 2) - result = PS2_cmd(port, 0x02, 1000); - if (IS_ERROR(result)) - { - printf ("2. Set Scan code error %08X\n", result); - break; - } - } - - // Test LEDs - for (i=0; i < 4; i++) - { - result = PS2_cmd(port, 0xED, 1000); - if (IS_ERROR(result)) - { - printf ("1. LED error %08X\n", result); - break; - } - result = PS2_cmd(port, 0x02, 1000); - if (IS_ERROR(result)) - { - printf ("2. LED error %08X\n", result); - break; - } - sleep(100); - result = PS2_cmd(port, 0xED, 1000); - if (IS_ERROR(result)) - { - printf ("1. LED error %08X\n", result); - break; - } - result = PS2_cmd(port, 0x04, 1000); - if (IS_ERROR(result)) - { - printf ("2. LED error %08X\n", result); - break; - } - sleep(100); - result = PS2_cmd(port, 0xED, 1000); - if (IS_ERROR(result)) - { - printf ("1. LED error %08X\n", result); - break; - } - result = PS2_cmd(port, 0x01, 1000); - if (IS_ERROR(result)) - { - printf ("2. LED error %08X\n", result); - break; - } - sleep(100); - } - result = PS2_cmd(port, 0xED, 1000); - if (IS_ERROR(result)) - { - printf ("1. LED error %08X\n", result); - break; - } - result = PS2_cmd(port, 0x00, 1000); - if (IS_ERROR(result)) - { - printf ("2. LED error %08X\n", result); - break; - } - - pIF->type = ps2_type_keyb; - result = pIF->type; - break; - } - - // We got a byte => maybe mouse - if (result == 0) - { - // We got zero => yes, it's a mouse - printf ("PS2_init(%d) - Mouse device detected\n", port); - - // send Get Device-ID - result = PS2_cmd(port, 0xF2, 1000); - if (IS_ERROR(result)) - { - printf ("Get Device-ID error %08X\n", result); - break; - } - id[0] = PS2_byte_read(port, 1000); - printf ("PS2_init(%d) - Device-ID: %02X\n", port, id[0]); - printf ("PS2_init(%d) - Enable stream mode...", port); - result = PS2_cmd(port, 0xF4, 1000); - if (IS_ERROR(result)) - { - printf ("error %08X\n", result); - break; - } - printf ("Success\n"); - pIF->type = ps2_type_mouse; - result = pIF->type; - break; - } - } - - // Flush buffer - PS2_flush(port); - - if (IS_ERROR(result)) - return result; - - // Enable RX-interrupt - *pIF->pCTRL |= SYS_PS2_BIT_RX_INTEN; - - return result; - -} diff --git a/lib/CPUs/MIPS/bsp/examples/libsys/mips_ps2.h b/lib/CPUs/MIPS/bsp/examples/libsys/mips_ps2.h deleted file mode 100644 index 9bfee72..0000000 --- a/lib/CPUs/MIPS/bsp/examples/libsys/mips_ps2.h +++ /dev/null @@ -1,43 +0,0 @@ -#ifndef PS2_H -#define PS2_H - -#include "libsys.h" - -// -------------------------------------------------- -// Types -// -------------------------------------------------- -enum -{ - ps2_type_unknown = 0, - ps2_type_keyb, - ps2_type_mouse -}; - -typedef struct _sps2_if_t -{ - UINT32 type; - volatile UINT32 *pCTRL; - volatile UINT32 *pDATA; -} ps2_if_t; - -// -------------------------------------------------- -// Constants -// -------------------------------------------------- -#define PS2_MODULE_PREFIX 0x1000000 -#define PS2_SUCCESS LSYS_SUCCESS -#define PS2_ERROR (LSYS_ERR_BASE | PS2_MODULE_PREFIX) -#define PS2_ERR_TIMEOUT (PS2_ERROR | 0x0000001) -#define PS2_ERR_PS2_PREFIX (PS2_ERROR | 0x0010000) - -// -------------------------------------------------- -// Functions -// -------------------------------------------------- -UINT32 PS2_get_num_if(void); -ps2_if_t *PS2_get_if(UINT32 port); -UINT32 PS2_init(UINT32 port); -void PS2_byte_write(UINT32 port, UINT8 byte); -UINT32 PS2_byte_read(UINT32 port, UINT32 timeout_ms); -UINT32 PS2_cmd(UINT32 port, UINT8 cmd, UINT32 ack_timeout_ms); -void PS2_flush(UINT32 port); - -#endif // PS2_H diff --git a/lib/CPUs/MIPS/bsp/examples/libsys/syscalls.c b/lib/CPUs/MIPS/bsp/examples/libsys/syscalls.c deleted file mode 100644 index 040372b..0000000 --- a/lib/CPUs/MIPS/bsp/examples/libsys/syscalls.c +++ /dev/null @@ -1,86 +0,0 @@ -#include -#include "libsys.h" -#include "xcpt.h" - -/* 10 digits + 1 sign + 1 trailing nul */ -static char itoa_buf[12]; - -char *itoa(int i) -{ - char *pos = itoa_buf + sizeof(itoa_buf) - 1; - unsigned int u; - int negative = 0; - - if (i < 0) - { - negative = 1; - u = ((unsigned int)(-(1+i))) + 1; - } - else - { - u = i; - } - - *pos = 0; - - do - { - *--pos = '0' + (u % 10); - u /= 10; - } while (u); - - if (negative) - { - *--pos = '-'; - } - - return pos; -} - -int syscalls_handler(struct xcptcontext * xcp) -{ - int syscall_code; - char *pStr, buf[33]; - - syscall_code = xcp->regs[2]; - - switch(syscall_code) - { - case 1: // print integer - sputs(itoa(xcp->regs[4])); - break; - - case 4: // print string - pStr = (char*)xcp->regs[4]; - sputs(pStr); - break; - - case 5: // read integer - pStr = fgets(buf, sizeof(buf), stdin); - xcp->regs[2] = atoi(pStr); - break; - - case 8: // read string - pStr = (char*)xcp->regs[4]; - fgets(pStr, xcp->regs[5], stdin); - break; - - case 10: // exit - _exit(0); - break; - - default: - sputs("\nUnknown syscall (");print_word(syscall_code);sputs(") at ");print_word(xcp->epc);sputs("\n"); - break; - } - - xcp->epc += 4; // set return address to instruction after syscall - - return 0; -} - -void syscalls_init(void) -{ - xcpt_register(Syscall, syscalls_handler); -} - diff --git a/lib/CPUs/MIPS/bsp/examples/life.c b/lib/CPUs/MIPS/bsp/examples/life.c deleted file mode 100644 index bba5a0e..0000000 --- a/lib/CPUs/MIPS/bsp/examples/life.c +++ /dev/null @@ -1,251 +0,0 @@ -/* life.c - demonstrator for later Mips+LCD game of life - * - * 23.03.06 - MACRO-based version - * 22.02.06 - new file - */ - -//#include "ks0108.h" - -#include -#include -#include -#include "libsys.h" - - -#define NX 200 // 70 // 128 // 48 // 128 -#define NY 150 // 31 // 64 // 27 // 64 - -#define SCREEN_X 800 -#define SCREEN_Y 600 - -#define SCALE_X (4) -#define SCALE_Y (4) -#define OFFSET_X ((SCREEN_X-(SCALE_X*NX))/2) -#define OFFSET_Y ((SCREEN_Y-(SCALE_Y*NY))/2) - -// OCCUPIED must be uneven, EMPTY even. -#define OCCUPIED 0x77771111 -#define EMPTY 0xeeee0000 - -#define MATRIX( row, col ) (*(matrix + (NX*col) + row )) -#define FUTURE( row, col ) (*(future + (NX*col) + row )) - -UINT32 *g_gx_buff; - -int clock_lfsr32() -{ - return rand(); -} - - -/* return a pseudo-random integer in the range 0..1023 */ -int random1023() { - int tmp; - - tmp = clock_lfsr32(); - return tmp & 0x000003ff; -} - -typedef struct _scolor_t -{ - UINT8 r, g, b, a; -} __attribute__ ((__packed__)) color_t; - - -void DrawPixel(UINT32 x, UINT32 y, color_t *pColor) -{ - int i, j; - for (i=0; i < SCALE_Y; i++) - for (j=0; j < SCALE_X; j++) - g_gx_buff[(OFFSET_X+SCALE_X*x+j) + SCREEN_X*(OFFSET_Y+SCALE_Y*y+i)] = *((UINT32*)pColor); -} - - -/* MSB/LSB in y-Richtung vertauscht */ -void displayBoard1( int* matrix ) -{ - int x, y; - int mask, accu; - UINT32 color; - - for( x=0; x < NX; x++ ) - { - mask = 0x80; - accu = 0x00; - for( y=0; y < NY; y++ ) - { - color = (UINT32)-(MATRIX(x,y) & 0x1); - DrawPixel(x, y, (color_t*)&color); -// if (MATRIX( x, y ) != OCCUPIED) -// { -// accu |= mask; -// } -// mask = mask >> 1; - -// color = 0; -// DrawPixel(x, (y>>3), (color_t*)&color); -// if (mask == 0) -// { -// color = accu; -// DrawPixel(x, (y>>3), (color_t*)&color); -// mask = 0x80; -// accu = 0x00; -// } - } -// color = accu; -// DrawPixel(x, (y>>3), (color_t*)&color); - - } -// *(matrix-15) = 0xdead0000; -// *(matrix-16) = *(matrix-16) + 1; -} - -void initializeBoard( int* matrix ) { - int x, y; - for( x=0; x < NX; x++ ) { - for( y=0; y < NY; y++ ) { - int d = random1023(); - if (d > 920) MATRIX( x, y ) = OCCUPIED; - else MATRIX( x, y ) = EMPTY; - } - } -} - - -int countNeighbors( int* matrix, int i, int j ) { - int im = i-1; - int ip = i+1; - - int jm = j-1; - int jp = j+1; - - int n = 0; - // wrap-around - if (ip >= NX) ip = 0; - if (jp >= NY) jp = 0; - - if (im < 0) im = NX-1; - if (jm < 0) jm = NY-1; - - // check eight neighbors - n += MATRIX(im, jm ) & 0x1; // nw - n += MATRIX(im, j ) & 0x1; // west - n += MATRIX(im, jp ) & 0x1; // sw - - n += MATRIX(i, jm ) & 0x1; // north - // n += MATRIX(i, j ) & 0x1; // center - n += MATRIX(i, jp ) & 0x1; // south - - n += MATRIX(ip, jm ) & 0x1; // ne - n += MATRIX(ip, j ) & 0x1; // east - n += MATRIX(ip, jp ) & 0x1; // se - - return n; -} - - -/** - * the actual game of life algorithm: cell is born when three neighbors, - * survives when exactly two live neighbors, dies otherwise. - */ -void nextGeneration( int* matrix, int* future ) { - int i, j; - int lifes = 0; - - for( i=0; i < NX; i++ ) { - for( j=0; j < NY; j++ ) { - // count neighbors - int n = countNeighbors( matrix, i, j ); - - //if ((n != 0) && (random1023() > 990)) { // some slight random offset - // if (random1023() > 500) FUTURE(i,j) = OCCUPIED; - // else FUTURE(i,j) = EMPTY; - //} - // else if (n == 3) FUTURE(i,j) = OCCUPIED; - - if (n == 3) FUTURE(i,j) = OCCUPIED; - else if ((n == 2) && (MATRIX(i,j) == OCCUPIED)) FUTURE(i,j) = OCCUPIED; - else FUTURE(i,j) = EMPTY; - - if (FUTURE(i,j) == OCCUPIED) lifes++; - } - } - // generation ++; - - // avoid extinction :-) - if (lifes < 10) { - // printf( "CREATING A NEW POPULATION\n\n\n" ); - initializeBoard( matrix ); - } - else { // swap buffers: C PROHIBITS ASSIGNING TO ARRAY TYPES - for( i=0; i < NX; i++ ) { - for( j=0; j < NY; j++ ) { - MATRIX(i,j) = FUTURE(i,j); - } - } - } -} - -void gx_init(void) -{ - volatile UINT32 *pVGA_ctrl = (UINT32*)SYS_VGA_CTRL; - volatile UINT32 *pVGA_front = (UINT32*)SYS_VGA_FB_FRONT; - volatile UINT32 *pVGA_back = (UINT32*)SYS_VGA_FB_BACK; - - sleep(500); - - g_gx_buff = (UINT32*)malloc(SCREEN_X*SCREEN_Y*sizeof(UINT32)); - memset(g_gx_buff, 0, SCREEN_X*SCREEN_Y*sizeof(UINT32)); - printf("g_gx_buff : %8.8X\n", (UINT32)g_gx_buff); - - *pVGA_ctrl |= SYS_VGA_BIT_MSTEN; - *pVGA_front = (UINT32)g_gx_buff; - *pVGA_back = (UINT32)g_gx_buff; - -} - -int main( int argc, char* argv[] ) { - - int* ptr, cnt = 0; - - int* matrix; - int* future; - volatile UINT32 *pBtn = (UINT32*)SYS_GPIO0; - - // lcdEnableDisplay( 1 ); - // lcdSetColor( 1 ); - // lcdSetPixel( 0, 0 ); - // lcdSetPixel( 3, 5 ); - - // if we have stdlib: - matrix = (void*) malloc( NX*NY*sizeof(int) ); - future = (void*) malloc( NX*NY*sizeof(int) ); - - - gx_init(); - -// matrix = (void *) 0x00004000; -// future = (void *) 0x00014000; - - // init_lfsr32( 0xcafebabe ); - // init_lfsr32( 0x13 ); - - srand(clock()); - initializeBoard( matrix ); - - while( 1 ) - { - - if (*pBtn) - { - srand(clock()); - initializeBoard( matrix ); - cnt = 0; - } - sputs("Generation #"); print_word(cnt++); sputs("\n"); - displayBoard1( matrix ); - nextGeneration( matrix, future ); - } - - // return 0 -} diff --git a/lib/CPUs/MIPS/bsp/examples/link/link.ld b/lib/CPUs/MIPS/bsp/examples/link/link.ld deleted file mode 100644 index bf3b367..0000000 --- a/lib/CPUs/MIPS/bsp/examples/link/link.ld +++ /dev/null @@ -1,225 +0,0 @@ -/* Script for -z combreloc: combine and sort reloc sections */ -OUTPUT_FORMAT("elf32-littlemips", "elf32-bigmips", - "elf32-littlemips") -OUTPUT_ARCH(mips) -ENTRY(_start) -SEARCH_DIR("./libsys"); -SEARCH_DIR("/usr/local/mipsel-elf/lib:/usr/local/mipsel-elf/lib/eb"); -SEARCH_DIR("/usr/local/lib/gcc/mipsel-elf/4.3.3:/usr/local/lib/gcc/mipsel-elf/4.3.3/eb"); - -stack_ptr = 0x7FFFEFF0; -baudrate = 0x0D; -sys_led_port = 0xA0000000; -sys_uart_data = 0xA0010000; -sys_uart_stat = 0xA0010004; -sys_uart_baud = 0xA0010008; -sys_timer_usec = 0xA000008; -sys_timer_sec = 0xA000000C; - -STARTUP(startup.o) -INPUT(kernel.o) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - PROVIDE (__executable_start = 0x40000000); . = 0x40000000; - .start __executable_start : - { - start = ALIGN(2); - entry = ALIGN(2); - _entry = ALIGN(2); - __entry = ALIGN(2); - *(.start) - } - /* Kernel text with low-level exception handler */ - .exc_vector __executable_start + 0x080 : - { - _exc_vect_start = .; - *(.exc_vect) - _exc_vect_end = .; - } - .init : - { - KEEP (*(.init)) - } =0 - .plt : { *(.plt) } - .text : - { - _ftext = . ; - *(.text .stub .text.* .gnu.linkonce.t.*) - /* .gnu.warning sections are handled specially by elf32.em. */ - *(.gnu.warning) - *(.mips16.fn.*) *(.mips16.call.*) - } =0 - .fini : - { - KEEP (*(.fini)) - } =0 - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - .rodata : { *(.rodata .rodata.* .gnu.linkonce.r.*) } - .rodata1 : { *(.rodata1) } - .sdata2 : - { - *(.sdata2 .sdata2.* .gnu.linkonce.s2.*) - } - .sbss2 : { *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*) } - .eh_frame_hdr : { *(.eh_frame_hdr) } - .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } - .gcc_except_table : ONLY_IF_RO { *(.gcc_except_table .gcc_except_table.*) } - /* Adjust the address for the data segment. We want to adjust up to - the same address within the page on the next page up. */ - . = ALIGN (CONSTANT (MAXPAGESIZE)) - ((CONSTANT (MAXPAGESIZE) - .) & (CONSTANT (MAXPAGESIZE) - 1)); . = DATA_SEGMENT_ALIGN (CONSTANT (MAXPAGESIZE), CONSTANT (COMMONPAGESIZE)); - /* Exception handling */ - .eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) } - .gcc_except_table : ONLY_IF_RW { *(.gcc_except_table .gcc_except_table.*) } - /* Thread Local Storage sections */ - .tdata : { *(.tdata .tdata.* .gnu.linkonce.td.*) } - .tbss : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } - .preinit_array : - { - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - } - .init_array : - { - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - } - .fini_array : - { - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - PROVIDE_HIDDEN (__fini_array_end = .); - } - .ctors : - { - /* gcc uses crtbegin.o to find the start of - the constructors, so we make sure it is - first. Because this is a wildcard, it - doesn't matter if the user does not - actually link against crtbegin.o; the - linker won't look for a file to match a - wildcard. The wildcard also means that it - doesn't matter which directory crtbegin.o - is in. */ - KEEP (*crtbegin.o(.ctors)) - KEEP (*crtbegin?.o(.ctors)) - /* We don't want to include the .ctor section from - the crtend.o file until after the sorted ctors. - The .ctor section from the crtend file contains the - end of ctors marker and it must be last */ - KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*(.ctors)) - } - .dtors : - { - KEEP (*crtbegin.o(.dtors)) - KEEP (*crtbegin?.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - } - .jcr : { KEEP (*(.jcr)) } - .data.rel.ro : { *(.data.rel.ro.local* .gnu.linkonce.d.rel.ro.local.*) *(.data.rel.ro* .gnu.linkonce.d.rel.ro.*) } - . = DATA_SEGMENT_RELRO_END (0, .); - .data : - { - _fdata = . ; - *(.data .data.* .gnu.linkonce.d.*) - SORT(CONSTRUCTORS) - } - .data1 : { *(.data1) } - .got.plt : { *(.got.plt) } - . = .; - _gp = ALIGN(16) + 0x7ff0; - .got : { *(.got) } - /* We want the small data sections together, so single-instruction offsets - can access them all, and initialized data all before uninitialized, so - we can shorten the on-disk segment size. */ - .sdata : - { - *(.sdata .sdata.* .gnu.linkonce.s.*) - } - .lit8 : { *(.lit8) } - .lit4 : { *(.lit4) } - _edata = .; PROVIDE (edata = .); - __bss_start = .; - _fbss = .; - .sbss : - { - *(.dynsbss) - *(.sbss .sbss.* .gnu.linkonce.sb.*) - *(.scommon) - } - .bss : - { - *(.dynbss) - *(.bss .bss.* .gnu.linkonce.b.*) - *(COMMON) - /* Align here to ensure that the .bss section occupies space up to - _end. Align after .bss to ensure correct alignment even if the - .bss section disappears because there are no input sections. - FIXME: Why do we need it? When there is no .bss section, we don't - pad the .data section. */ - . = ALIGN(. != 0 ? 32 / 8 : 1); - } - . = ALIGN(32 / 8); - . = ALIGN(32 / 8); - _end = .; PROVIDE (end = .); - . = DATA_SEGMENT_END (.); - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - /* DWARF debug sections. - Symbols in the DWARF debugging sections are relative to the beginning - of the section so we begin them at 0. */ - /* DWARF 1 */ - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - /* GNU DWARF 1 extensions */ - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - /* DWARF 1.1 and DWARF 2 */ - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - /* DWARF 2 */ - .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - /* SGI/MIPS DWARF 2 extensions */ - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } - /* DWARF 3 */ - .debug_pubtypes 0 : { *(.debug_pubtypes) } - .debug_ranges 0 : { *(.debug_ranges) } - .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) } - .gptab.sdata : { *(.gptab.data) *(.gptab.sdata) } - .gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) } - .mdebug.abi32 : { KEEP(*(.mdebug.abi32)) } - .mdebug.abiN32 : { KEEP(*(.mdebug.abiN32)) } - .mdebug.abi64 : { KEEP(*(.mdebug.abi64)) } - .mdebug.abiO64 : { KEEP(*(.mdebug.abiO64)) } - .mdebug.eabi32 : { KEEP(*(.mdebug.eabi32)) } - .mdebug.eabi64 : { KEEP(*(.mdebug.eabi64)) } - .gcc_compiled_long32 : { KEEP(*(.gcc_compiled_long32)) } - .gcc_compiled_long64 : { KEEP(*(.gcc_compiled_long64)) } - /DISCARD/ : { *(.note.GNU-stack) *(.gnu_debuglink) } -} diff --git a/lib/CPUs/MIPS/bsp/examples/lua_init.c b/lib/CPUs/MIPS/bsp/examples/lua_init.c deleted file mode 100644 index 0edd3d5..0000000 --- a/lib/CPUs/MIPS/bsp/examples/lua_init.c +++ /dev/null @@ -1 +0,0 @@ -#include "all.c" diff --git a/lib/CPUs/MIPS/bsp/examples/lwl.c b/lib/CPUs/MIPS/bsp/examples/lwl.c deleted file mode 100644 index 3905cf0..0000000 --- a/lib/CPUs/MIPS/bsp/examples/lwl.c +++ /dev/null @@ -1,46 +0,0 @@ -#include "libsys.h" - -int non_aligned_load(UINT32* pMem) -{ - UINT32 result; - __asm__ - ( - "li $t0, 0x01234567\n" - "li $t1, 0x89ABCDEF\n" - "sw $t0, 0(%[pMem])\n" - "sw $t1, 64(%[pMem])\n" - "lw %[val], 0(%[pMem])\n" - "lw %[val], 64(%[pMem])\n" - "nop\n" - "nop\n" - "nop\n" - "nop\n" - "nop\n" - "nop\n" - "nop\n" - "nop\n" - "nop\n" - "nop\n" - "nop\n" - "nop\n" - "nop\n" - "nop\n" - "nop\n" - "li %[val], 0x55555555\n" - "lw %[val], 0(%[pMem])\n" - "lwl %[val], 65(%[pMem])\n" - : [val] "=r" (result) - : [pMem] "r" (pMem) - ); - return result; -} - -int main() -{ - int buf[256], res, i; - - res = non_aligned_load(buf); - - return res; - -} diff --git a/lib/CPUs/MIPS/bsp/examples/mandelbrot.c b/lib/CPUs/MIPS/bsp/examples/mandelbrot.c deleted file mode 100644 index ce7aa9d..0000000 --- a/lib/CPUs/MIPS/bsp/examples/mandelbrot.c +++ /dev/null @@ -1,54 +0,0 @@ -// by Erik Wrenholt -#include -#include - -#define BAILOUT 16 -#define MAX_ITERATIONS 1000 - -int mandelbrot(double x, double y) -{ - double cr = y - 0.5; - double ci = x; - double zi = 0.0; - double zr = 0.0; - int i = 0; - - while(1) { - i ++; - double temp = zr * zi; - double zr2 = zr * zr; - double zi2 = zi * zi; - zr = zr2 - zi2 + cr; - zi = temp + temp + ci; - if (zi2 + zr2 > BAILOUT) - return i; - if (i > MAX_ITERATIONS) - return 0; - } - -} - -int main (int argc, const char * argv[]) { - struct timeval aTv; - gettimeofday(&aTv, NULL); - long init_time = aTv.tv_sec; - long init_usec = aTv.tv_usec; - - int x,y; - for (y = -39; y < 39; y++) { - printf("\n"); - for (x = -39; x < 39; x++) { - int i = mandelbrot(x/40.0, y/40.0); - if (i==0) - printf("*"); - else - printf(" "); - } - } - printf ("\n"); - - gettimeofday(&aTv,NULL); - double query_time = (aTv.tv_sec - init_time) + (double)(aTv.tv_usec - init_usec)/1000000.0; - printf ("C Elapsed %0.2f\n", query_time); - return 0; -} diff --git a/lib/CPUs/MIPS/bsp/examples/mips_gfx.c b/lib/CPUs/MIPS/bsp/examples/mips_gfx.c deleted file mode 100644 index ee06438..0000000 --- a/lib/CPUs/MIPS/bsp/examples/mips_gfx.c +++ /dev/null @@ -1,566 +0,0 @@ -#include -#include -#include -#include "libsys.h" -#include "mips_gfx.h" - -#define USE_HW_BLITTER - -// ------------------------------------------------------------- -// Functions -// ------------------------------------------------------------- -void __gfx_block_set_8(UINT32* pDst, UINT32 value) -{ - __asm__ volatile - ( - "sw %[value], 0(%[pDst])\n" - "sw %[value], 4(%[pDst])\n" - "sw %[value], 8(%[pDst])\n" - "sw %[value], 12(%[pDst])\n" - "sw %[value], 16(%[pDst])\n" - "sw %[value], 20(%[pDst])\n" - "sw %[value], 24(%[pDst])\n" - "sw %[value], 28(%[pDst])\n" - : - : [pDst] "r" (pDst), [value] "r" (value) - ); -} - -void __gfx_block_copy_8(UINT32* pDst, UINT32* pSrc) -{ - __asm__ volatile - ( - ".set noreorder\n" - ".set nomacro\n" - "lw $s0, 0(%[pSrc])\n" - "lw $s1, 4(%[pSrc])\n" - "sw $s0, 0(%[pDst])\n" - "lw $s0, 8(%[pSrc])\n" - "sw $s1, 4(%[pDst])\n" - "lw $s1, 12(%[pSrc])\n" - "sw $s0, 8(%[pDst])\n" - "lw $s0, 16(%[pSrc])\n" - "sw $s1, 12(%[pDst])\n" - "lw $s1, 20(%[pSrc])\n" - "sw $s0, 16(%[pDst])\n" - "lw $s0, 24(%[pSrc])\n" - "sw $s1, 20(%[pDst])\n" - "lw $s1, 28(%[pSrc])\n" - "sw $s0, 24(%[pDst])\n" - "sw $s1, 28(%[pDst])\n" - ".set macro\n" - ".set reorder\n" - : - : [pDst] "r" (pDst), [pSrc] "r" (pSrc) - : "s0", "s1" - ); -} - -void __gfx_copy_32(UINT32* pDst, UINT32* pSrc, UINT32 nblocks) -{ - while (nblocks) - { - __gfx_block_copy_8(pDst, pSrc); - pDst += 8; - pSrc += 8; - nblocks--; - } - -} - -void GFX_DirtyRectSetClean(buf_t *pBuf) -{ - pBuf->rect.xmin = pBuf->w; - pBuf->rect.xmax = 0; - pBuf->rect.ymin = pBuf->h; - pBuf->rect.ymax = 0; - pBuf->is_dirty = 0; -} - -void GFX_DirtyRectInit(buf_t *pBuf, UINT32 w, UINT32 h) -{ - pBuf->w = w; - pBuf->h = h; - pBuf->regs = (vga_hw_t*)SYS_VGA_CTRL; - GFX_DirtyRectSetClean(pBuf); -} - -void GFX_DirtyRectUpdate(buf_t *pBuf, UINT32 xmin, UINT32 xmax, UINT32 ymin, UINT32 ymax) -{ - - if (xmin < pBuf->rect.xmin) - { - pBuf->is_dirty = 1; - pBuf->rect.xmin = xmin; - } - - if (xmax > pBuf->rect.xmax) - { - pBuf->is_dirty = 1; - pBuf->rect.xmax = xmax; - } - - if (ymin < pBuf->rect.ymin) - { - pBuf->is_dirty = 1; - pBuf->rect.ymin = ymin; - } - - if (ymax > pBuf->rect.ymax) - { - pBuf->is_dirty = 1; - pBuf->rect.ymax = ymax; - } - - if (pBuf->is_dirty && ((pBuf->rect.xmax-pBuf->rect.xmin)%8)) - pBuf->rect.xmax = pBuf->rect.xmin + ((pBuf->rect.xmax-pBuf->rect.xmin)/8 + 1) * 8; // Make len_x multiple of 8 - -} - -void GFX_DirtyRectCopy(buf_t *pBuf) -{ - UINT32 xmin, xmax, ymin, ymax, x, y; - UINT32 *pDst, *pDst_end; - UINT32 *pSrc, *pSrc_end; - - xmin = pBuf->rect.xmin; - xmax = pBuf->rect.xmax; - - ymin = pBuf->rect.ymin; - ymax = pBuf->rect.ymax; - - ymin *= pBuf->w; - ymax *= pBuf->w; - -#ifdef USE_HW_BLITTER - pSrc = (UINT32*)&pBuf->pLast->pFB[xmin + ymin]; - pDst = (UINT32*)&pBuf->pFB[xmin + ymin]; - - while (pBuf->regs->pVGA_ctrl & SYS_VGA_BIT_BLIT_BSY); - - pBuf->regs->pVGA_src0 = (UINT32)pSrc; - pBuf->regs->pVGA_dst = (UINT32)pDst; - pBuf->regs->pVGA_src0_dimx = (UINT32)4*pBuf->w; - pBuf->regs->pVGA_dst_dimx = (UINT32)4*pBuf->w; - pBuf->regs->pVGA_nx = (UINT32)(pBuf->rect.xmax-pBuf->rect.xmin); - pBuf->regs->pVGA_ny = (UINT32)(pBuf->rect.ymax-pBuf->rect.ymin); - pBuf->regs->pVGA_ctrl |= SYS_VGA_BIT_BLIT_REQ; - -#else - - if (!((xmax-xmin)%8)) - { - for (y=ymin; y < ymax; y += pBuf->w) - { - pSrc = &pBuf->pLast->pFB[xmin + y]; - pSrc_end = &pBuf->pLast->pFB[xmax + y]; - pDst = &pBuf->pFB[xmin + y]; - pDst_end = &pBuf->pFB[xmax + y]; - while(pDst < pDst_end) - { - __gfx_block_copy_8(pDst, pSrc); - pDst += 8; - pSrc += 8; - } - } - return; - } - -// fprintf(stderr, "GFX_DirtyRectCopy(): Slow copy!\n"); - for (y=ymin; y < ymax; y += pBuf->w) - { - for (x=xmin; x < xmax; x++) - { - pBuf->pFB[x + y] = pBuf->pLast->pFB[x + y]; - } - } -#endif - -} - -void GFX_init(gfx_t *pObj) -{ - int i; - buf_t *pBuf; - UINT32 w, h, fps; - - pObj->regs = (vga_hw_t*)SYS_VGA_CTRL; - - pObj->regs->pVGA_ctrl &= ~SYS_VGA_BIT_MSTEN; - - w = Screen_get_resx(); - h = Screen_get_resy(); - fps = Screen_get_fps(); - - printf("VGA screen = %d x %d @ %d fps\n", w, h, fps); - - pObj->w = w; - pObj->h = h; - - // Init background buffer - pObj->pBG = (UINT32*)calloc(w * h, sizeof(buf_t)); - - // Init framebuffers - pObj->pBuf = (buf_t*)calloc(1, sizeof(buf_t)); - pBuf = pObj->pBuf; - pBuf->pFB = (UINT32*)calloc((w+8) * h, sizeof(UINT32)); // w+8 because of dirty rectangle 8 byte min. x-size - for (i=1; i < GFX_NUM_FRAME_BUFFERS; i++) - { - - pBuf->pNext = (buf_t*)calloc(1, sizeof(buf_t)); - pBuf->pNext->pLast = pBuf; - pBuf = pBuf->pNext; - pBuf->pFB = (UINT32*)calloc((w+8) * h, sizeof(UINT32)); // w+8 because of dirty rectangle 8 byte min. x-size - } - pObj->pBuf->pLast = pBuf; - pBuf->pNext = pObj->pBuf; - - pBuf = pObj->pBuf; - for (i=0; i < GFX_NUM_FRAME_BUFFERS; i++) - { - GFX_DirtyRectInit(pBuf, w, h); - -// fprintf(stderr, "pBuf = %08X, pLast = %08X, pNext = %08X\n", pBuf, pBuf->pLast, pBuf->pNext); - pBuf = pBuf->pNext; - } - - pObj->regs->pVGA_front = (UINT32)pObj->pBuf->pLast->pFB; - pObj->regs->pVGA_back = (UINT32)pObj->pBuf->pLast->pFB; - pObj->regs->pVGA_ctrl |= SYS_VGA_BIT_MSTEN; - - -} - -void GFX_set_background(gfx_t *pObj, UINT32 *pImage, UINT32 image_nx, UINT32 image_ny, UINT32 image_scale_x, UINT32 image_scale_y) -{ - - UINT32 off_x, off_y; - UINT32 i, j; - UINT32 *pDst, *pSrc; - buf_t *pBuf; - - if (!pImage) - return; - - off_x = (pObj->w-(image_scale_x*image_nx))/2; - off_y = (pObj->h-(image_scale_y*image_ny))/2; - - pDst = ((UINT32*)pObj->pBG) + pObj->w*off_y + off_x; - pSrc = pImage; - - for (i=0; i < image_ny*image_nx; i += 8) - { - __gfx_block_copy_8(pDst, pSrc); - pDst += 8; - pSrc += 8; - } - - pBuf = pObj->pBuf; - - pDst = pBuf->pFB; - pSrc = pObj->pBG; - - for (i=0; i < image_ny*image_nx; i += 8) - { - __gfx_block_copy_8(pDst, pSrc); - pDst += 8; - pSrc += 8; - } - - do - { - GFX_DirtyRectUpdate(pBuf, 0, pObj->w, 0, pObj->h); - pBuf = pBuf->pNext; - - } while(pBuf != pObj->pBuf); - - -} - -void GFX_frame(gfx_t *pObj, UINT32 sync_mode) -{ - - // Wait until back buffer becomes front - if (sync_mode == GFX_FRAME_SYNC) - { - while(pObj->regs->pVGA_front == (UINT32)pObj->pBuf->pFB); - } - - GFX_copy_front2back(pObj); - - // Invalidate D-Cache after blitting has finished - while (pObj->regs->pVGA_ctrl & SYS_VGA_BIT_BLIT_BSY); - - DCACHE_invalidate_all(); - -} - -void GFX_show(gfx_t *pObj) -{ - - pObj->regs->pVGA_back = (UINT32)pObj->pBuf->pFB; - pObj->pBuf = pObj->pBuf->pNext; - -} - -void GFX_copy_front2back(gfx_t *pObj) -{ - buf_t *pBuf; - - pBuf = pObj->pBuf; - - // Lopp over all frame buffers, except front buffer - while(pBuf != pObj->pBuf->pLast) - { - if (pBuf->is_dirty) - { -// fprintf(stderr, "Dirty rect [%08X]: w=%d, h=%d\n", (int)pBuf, pBuf->rect.xmax - pBuf->rect.xmin, pBuf->rect.ymax - pBuf->rect.ymin); - GFX_DirtyRectCopy(pBuf); - GFX_DirtyRectSetClean(pBuf); - } - pBuf = pBuf->pNext; - } -} - -void GFX_get_FB_front(gfx_t *pObj, UINT32 **ppFB) -{ - *ppFB = pObj->pBuf->pLast->pFB; -} - -void box_create(box_t *pObj, UINT32 w, UINT32 h) -{ - pObj->w = w; - pObj->h = h; -} - -void GFX_restore(gfx_t *pObj, box_t *pBox, UINT32 posx, UINT32 posy) -{ - UINT32 xmin, xmax, ymin, ymax, x, y; - UINT32 *pDst, *pDst_end; - UINT32 *pSrc, *pSrc_end; - buf_t *pBuf; - - xmin = posx; - xmax = pBox->w + posx; - if (xmax > pObj->w) - xmax = pObj->w; - - ymin = posy; - ymax = pBox->h + posy; - if (ymax > pObj->h) - ymax = pObj->h; - - pBuf = pObj->pBuf->pNext; - - // Lopp over all frame buffers, except current back buffer - while(pBuf != pObj->pBuf) - { - GFX_DirtyRectUpdate(pBuf, xmin, xmax, ymin, ymax); - pBuf = pBuf->pNext; - - } - pBuf = pObj->pBuf; - - x = xmax - xmin + 1; - if (x%2) - x++; - y = ymax - ymin + 1; - if (y%2) - y++; - - ymin *= pObj->w; - ymax *= pObj->w; - -#ifdef USE_HW_BLITTER - pSrc = (UINT32*)&pObj->pBG[xmin + ymin]; - pDst = (UINT32*)&pBuf->pFB[xmin + ymin]; - - while (pObj->regs->pVGA_ctrl & SYS_VGA_BIT_BLIT_BSY); - - pObj->regs->pVGA_src0 = (UINT32)pSrc; - pObj->regs->pVGA_dst = (UINT32)pDst; - pObj->regs->pVGA_src0_dimx = (UINT32)4*pObj->w; - pObj->regs->pVGA_dst_dimx = (UINT32)4*pObj->w; - pObj->regs->pVGA_nx = (UINT32)x - 1; - pObj->regs->pVGA_ny = (UINT32)y - 1; - pObj->regs->pVGA_ctrl |= SYS_VGA_BIT_BLIT_REQ; - -#else - - if (!((xmax-xmin)%8)) - { - for (y=ymin; y < ymax; y += pBuf->w) - { - pSrc = &pObj->pBG[xmin + y]; - pSrc_end = &pObj->pBG[xmax + y]; - pDst = &pBuf->pFB[xmin + y]; - pDst_end = &pBuf->pFB[xmax + y]; - while(pDst < pDst_end) - { - __gfx_block_copy_8(pDst, pSrc); - pDst += 8; - pSrc += 8; - } - } - return; - } - -// fprintf(stderr, "GFX_DirtyRectCopy(): Slow copy!\n"); - for (y=ymin; y < ymax; y += pBuf->w) - { - for (x=xmin; x < xmax; x++) - { - pBuf->pFB[x + y] = pObj->pBG[x + y]; - } - } -#endif - -} - -void GFX_box_draw(gfx_t *pObj, box_t *pBox, UINT32 posx, UINT32 posy, UINT32 color) -{ - UINT32 xmin, xmax, ymin, ymax, x, y; - UINT32 *pFB, *pFB_end; - buf_t *pBuf; - - xmin = posx; - xmax = pBox->w + posx; - if (xmax > pObj->w) - xmax = pObj->w; - - ymin = posy; - ymax = pBox->h + posy; - if (ymax > pObj->h) - ymax = pObj->h; - - pBuf = pObj->pBuf->pNext; - - // Lopp over all frame buffers, except current back buffer - while(pBuf != pObj->pBuf) - { - GFX_DirtyRectUpdate(pBuf, xmin, xmax, ymin, ymax); - pBuf = pBuf->pNext; - - } - pBuf = pObj->pBuf; - - ymin *= pObj->w; - ymax *= pObj->w; - - while (pObj->regs->pVGA_ctrl & SYS_VGA_BIT_BLIT_BSY); - - if (!((xmax-xmin)%8)) - { - for (y=ymin; y < ymax; y += pObj->w) - { - pFB = &pBuf->pFB[xmin + y]; - pFB_end = &pBuf->pFB[xmax + y]; - while(pFB < pFB_end) - { - __gfx_block_set_8(pFB, color); - pFB += 8; - } - } - return; - } - -// fprintf(stderr, "GFX_box_draw(): Slow copy!\n"); - for (y=ymin; y < ymax; y += pObj->w) - { - for (x=xmin; x < xmax; x++) - { - pBuf->pFB[x + y] = color; - } - } -} - -void GFX_box_draw_bg(gfx_t *pObj, box_t *pBox, UINT32 posx, UINT32 posy, UINT32 color) -{ - UINT32 xmin, xmax, ymin, ymax, x, y; - UINT32 *pFB, *pFB_end; - - xmin = posx; - xmax = pBox->w + posx; - if (xmax > pObj->w) - xmax = pObj->w; - - ymin = posy; - ymax = pBox->h + posy; - if (ymax > pObj->h) - ymax = pObj->h; - - ymin *= pObj->w; - ymax *= pObj->w; - - while (pObj->regs->pVGA_ctrl & SYS_VGA_BIT_BLIT_BSY); - - if (!((xmax-xmin)%8)) - { - for (y=ymin; y < ymax; y += pObj->w) - { - pFB = &pObj->pBG[xmin + y]; - pFB_end = &pObj->pBG[xmax + y]; - while(pFB < pFB_end) - { - __gfx_block_set_8(pFB, color); - pFB += 8; - } - } - return; - } - -// fprintf(stderr, "GFX_box_draw_bg(): Slow copy!\n"); - for (y=ymin; y < ymax; y += pObj->w) - { - for (x=xmin; x < xmax; x++) - { - pObj->pBG[x + y] = color; - } - } -} - -void GFX_box_draw_direct(gfx_t *pObj, box_t *pBox, UINT32 posx, UINT32 posy, UINT32 color) -{ - UINT32 xmin, xmax, ymin, ymax, x, y; - UINT32 *pFB, *pFB_end; - buf_t *pBuf; - - pBuf = pObj->pBuf->pLast; - - xmin = posx; - xmax = pBox->w + posx; - if (xmax > pObj->w) - xmax = pObj->w; - - ymin = posy; - ymax = pBox->h + posy; - if (ymax > pObj->h) - ymax = pObj->h; - - ymin *= pObj->w; - ymax *= pObj->w; - - if (!((xmax-xmin)%8)) - { - for (y=ymin; y < ymax; y += pObj->w) - { - pFB = &pBuf->pFB[xmin + y]; - pFB_end = &pBuf->pFB[xmax + y]; - while(pFB < pFB_end) - { - __gfx_block_set_8(pFB, color); - pFB += 8; - } - } - return; - } - -// fprintf(stderr, "GFX_box_draw_direct(): Slow copy!\n"); - for (y=ymin; y < ymax; y += pObj->w) - { - for (x=xmin; x < xmax; x++) - { - pBuf->pFB[x + y] = color; - } - } -} diff --git a/lib/CPUs/MIPS/bsp/examples/mips_gfx.h b/lib/CPUs/MIPS/bsp/examples/mips_gfx.h deleted file mode 100644 index 1363e07..0000000 --- a/lib/CPUs/MIPS/bsp/examples/mips_gfx.h +++ /dev/null @@ -1,91 +0,0 @@ -#ifndef GFX_H -#define GFX_H - -#include "libsys.h" - -#define GFX_NUM_FRAME_BUFFERS 2 -#define GFX_FRAME_NOSYNC 0 -#define GFX_FRAME_SYNC 1 - -// ------------------------------------------------------------- -// Types -// ------------------------------------------------------------- -typedef struct _sbox_t -{ - UINT32 w, h; -} box_t; - -typedef struct _srect_t -{ - UINT32 xmin, xmax; - UINT32 ymin, ymax; -} rect_t; - -typedef struct _svga_hw_t -{ - UINT32 volatile pVGA_ctrl; // 0xA0030000 // R/W - UINT32 volatile pVGA_ascii; // 0xA0030004 // R/W - UINT32 volatile pVGA_posx; // 0xA0030008 // R/W - UINT32 volatile pVGA_posy; // 0xA003000C // R/W - UINT32 volatile pVGA_cgcol; // 0xA0030010 // R/W - UINT32 volatile pVGA_res; // 0xA0030014 // RO - UINT32 volatile pVGA_front; // 0xA0030018 // R/W - UINT32 volatile pVGA_back; // 0xA003001C // R/W - UINT32 volatile pVGA_src0; // 0xA0030020 // R/W - UINT32 volatile pVGA_src0_last; // 0xA0030024 // R/W - UINT32 volatile pVGA_src0_dimx; // 0xA0030028 // R/W - UINT32 volatile pVGA_src0_res; // 0xA003002C // R/W - UINT32 volatile pVGA_src1; // 0xA0030030 // R/W - UINT32 volatile pVGA_src1_last; // 0xA0030034 // R/W - UINT32 volatile pVGA_src1_dimx; // 0xA0030038 // R/W - UINT32 volatile pVGA_src1_res; // 0xA003003C // R/W - UINT32 volatile pVGA_src2; // 0xA0030040 // R/W - UINT32 volatile pVGA_src2_last; // 0xA0030044 // R/W - UINT32 volatile pVGA_src2_dimx; // 0xA0030048 // R/W - UINT32 volatile pVGA_src2_res; // 0xA003004C // R/W - UINT32 volatile pVGA_dst; // 0xA0030050 // R/W - UINT32 volatile pVGA_dst_last; // 0xA0030054 // R/W - UINT32 volatile pVGA_dst_dimx; // 0xA0030058 // R/W - UINT32 volatile pVGA_dst_res; // 0xA003005C // R/W - UINT32 volatile pVGA_nx; // 0xA0030060 // R/W - UINT32 volatile pVGA_ny; // 0xA0030064 // R/W - -} vga_hw_t; - -typedef struct _sbuf_t -{ - UINT32 *pFB; - struct _sbuf_t *pNext; - struct _sbuf_t *pLast; - UINT32 is_dirty; - rect_t rect; - UINT32 w, h; - vga_hw_t *regs; -} buf_t; - -typedef struct _sgfx_t -{ - UINT32 w, h; - buf_t *pBuf; - UINT32 *pBG; - vga_hw_t *regs; - -} gfx_t; - -// ------------------------------------------------------------- -// Functions -// ------------------------------------------------------------- -void __gfx_block_set_8(UINT32* pDst, UINT32 value); -void __gfx_block_copy_8(UINT32* pDst, UINT32* pSrc); -void __gfx_copy_32(UINT32* pDst, UINT32* pSrc, UINT32 nblocks); -void GFX_init(gfx_t *pObj); -void GFX_frame(gfx_t *pObj, UINT32 sync_mode); -void GFX_show(gfx_t *pObj); -void GFX_copy_front2back(gfx_t *pObj); -void GFX_get_FB_front(gfx_t *pObj, UINT32 **ppFB); -void box_create(box_t *pObj, UINT32 w, UINT32 h); -void GFX_restore(gfx_t *pObj, box_t *pBox, UINT32 posx, UINT32 posy); -void GFX_box_draw(gfx_t *pObj, box_t *pBox, UINT32 posx, UINT32 posy, UINT32 color); -void GFX_box_draw_bg(gfx_t *pObj, box_t *pBox, UINT32 posx, UINT32 posy, UINT32 color); - -#endif // GFX_H diff --git a/lib/CPUs/MIPS/bsp/examples/mipsdis.c b/lib/CPUs/MIPS/bsp/examples/mipsdis.c deleted file mode 100644 index d05e965..0000000 --- a/lib/CPUs/MIPS/bsp/examples/mipsdis.c +++ /dev/null @@ -1,625 +0,0 @@ -/* +----------------------------------------------------------------+ */ -/* | Copyright (c) 1994 Stanford University. | */ -/* | All Rights Reserved. | */ -/* | | */ -/* | This software is distributed with *ABSOLUTELY NO SUPPORT* | */ -/* | and *NO WARRANTY*. Use or reproduction of this code for | */ -/* | commerical gains is strictly prohibited. Otherwise, you | */ -/* | are given permission to use or modify this code as long | */ -/* | as you do not remove this notice. | */ -/* +----------------------------------------------------------------+ */ -/* --------------------------------------------------- */ -/* | Copyright (c) 1986 MIPS Computer Systems, Inc. | */ -/* | All Rights Reserved. | */ -/* --------------------------------------------------- */ - -/* - * Copyright 1985 by MIPS Computer Systems, Inc. - */ - -/* TORCH disassembler */ -/* derived from MIPS instruction dissassembler by PGL October 91 */ - -#include -#include -#include "mips_dis.h" - -#define false 0 -#define true 1 -typedef int boolean; -char *strcat(); - -#define ZERO 0 - -#define COMPILER_NAMES tdis_reg_names[0] -#define HARDWARE_NAMES tdis_reg_names[1] -#define ASSEMBLER_NAMES tdis_reg_names[2] -#define DIS_REG_NAMES(x) tdis_reg_names[x] - -union extension_byte { - unsigned char byte; - struct { /* extension byte bits in little-endian order */ -#if (defined __MIPSEB || defined _MIPSEB || defined MIPSEB) - unsigned reserved:1; - unsigned dyn_nop:1; - unsigned rs_boost:2; - unsigned rt_boost:2; - unsigned rd_boost:2; -#elif (defined __MIPSEL || defined _MIPSEL || defined MIPSEL) - unsigned rd_boost:2; - unsigned rt_boost:2; - unsigned rs_boost:2; - unsigned dyn_nop:1; - unsigned reserved:1; -#endif /*MIPSEB*/ - } e; -}; - -#define blez_op_T blez_op -#define blez_op_N (blez_op | 0x10) -#define bgtz_op_T bgtz_op -#define bgtz_op_N (bgtz_op | 0x10) -#define beq_op_T beq_op -#define beq_op_N (beq_op | 0x10) -#define bne_op_T bne_op -#define bne_op_N (bne_op | 0x10) -#define bc_op_T bc_op -#define bc_op_N (bc_op | 0x02) - -static char *op_name[64] = { -/* 0 */ "special", "regimm","j", "jal", "beq", "bne", "blez", "bgtz", -/* 8 */ "addi", "addiu","slti", "sltiu","andi", "ori", "xori", "lui", -/*16 */ "cop0", "cop1", "cop2", "cop3", "beql","bnel","blezl","bgtzl", -/*24 */ "op60", "op64", "op68", "op6c", "op70", "op74", "op78", "op7c", -/*32 */ "lb", "lh", "lwl", "lw", "lbu", "lhu", "lwr", "ld", -/*40 */ "sb", "sh", "swl", "sw", "opb0", "opb4", "swr", "sd", -/*48 */ "lwc0", "lwc1", "lwc2", "lwc3", "ldc0", "ldc1", "ldc2", "ldc3", -/*56 */ "swc0", "swc1", "swc2", "swc3", "sdc0", "sdc1", "sdc2", "sdc3" -}; - -static char *spec_name[64] = { -/* 0*/ "sll", "spec01","srl", "sra", "sllv", "spec05","srlv","srav", -/* 8*/ "jr", "jalr", "spec12","spec13","syscall","break","vcall","spec17", -/*16*/ "mfhi", "mthi", "mflo", "mtlo", "spec24","spec25","spec26","spec27", -/*24*/ "mult", "multu","div", "divu", "spec34","spec35","spec36","spec37", -/*32*/ "add", "addu", "sub", "subu", "and", "or", "xor", "nor", -/*40*/ "spec50","spec51","slt","sltu", "spec54","spec55","spec56","spec57", -/*48*/ "spec60","spec61","spec62","spec63","spec64","spec65","spec66","spec67", -/*56*/ "spec70","spec71","spec72","spec73","spec74","spec75","spec76","spec77" -}; - -static char *bcond_name[32] = { - "bltz", - "bgez", - "bltzl", - "bgezl", - "bcond04", - "bcond05", - "bcond06", - "bcond07", - "tgei", - "tgeiu", - "tlti", - "tltiu", - "teqi", - "bcond0d", - "tnei", - "bcond0f", - "bltzal", - "bgezal", - "bltzall", - "bgezall", - "bcond14", - "bcond15", - "bcond16", - "bcond17", - "bcond18", - "bcond19", - "bcond1a", - "bcond1b", - "bcond1c", - "bcond1d", - "bcond1e", - "bcond1f" -}; - -static char *cop1_name[64] = { -/* 0 */ "add", "sub", "mul", "div", "sqrt", "abs", "mov", "neg", -/* 8 */ "fop08","fop09","fop0a","fop0b","fop0c","fop0d","fop0e","fop0f", -/*16 */ "fop10","fop11","fop12","fop13","fop14","fop15","fop16","fop17", -/*24 */ "fop18","fop19","fop1a","fop1b","fop1c","fop1d","fop1e","fop1f", -/*32 */ "cvt.s","cvt.d","cvt.e","fop23","cvt.w","fop25","fop26","fop27", -/*40 */ "fop28","fop29","fop2a","fop2b","fop2c","fop2d","fop2e","fop2f", -/*48 */ "c.f", "c.un","c.eq","c.ueq","c.olt","c.ult","c.ole","c.ule", -/*56 */ "c.sf","c.ngle","c.seq","c.ngl","c.lt","c.nge","c.le","c.ngt" -}; - -static char *fmt_name[16] = { - "s", "d", "e", "q", - "w", "fmt5", "fmt6", "fmt7", - "fmt8", "fmt9", "fmta", "fmtb", - "fmtc", "fmtd", "fmte", "fmtf" -}; - -/* public */ -/* Three sets of commonly used register names */ -const char *tdis_reg_names[3][64] = { - { /* compiler names */ - "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", - "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", - "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", - "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", - "zero.B","at.B","v0.B", "v1.B", "a0.B", "a1.B", "a2.B", "a3.B", - "t0.B", "t1.B", "t2.B", "t3.B", "t4.B", "t5.B", "t6.B", "t7.B", - "s0.B", "s1.B", "s2.B", "s3.B", "s4.B", "s5.B", "s6.B", "s7.B", - "t8.B", "t9.B", "k0.B", "k1.B", "gp.B", "sp.B", "s8.B", "ra.B" - }, - { /* hardware names */ - "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", - "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", - "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", - "r24", "r25", "r26", "r27", "gp", "sp", "r30", "r31", - "r0.B", "r1.B", "r2.B", "r3.B", "r4.B", "r5.B", "r6.B", "r7.B", - "r8.B", "r9.B", "r10.B","r11.B","r12.B","r13.B","r14.B","r15.B", - "r16.B","r17.B","r18.B","r19.B","r20.B","r21.B","r22.B","r23.B", - "r24.B","r25.B","r26.B","r27.B","gp.B", "sp.B", "r30.B","r31.B" - }, - { /* assembler names */ - "$0", "$at", "$2", "$3", "$4", "$5", "$6", "$7", - "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", - "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", - "$24", "$25", "$26", "$27", "$gp", "$sp", "$30", "$31", - "$0.B", "$at.B","$2.B", "$3.B", "$4.B", "$5.B", "$6.B", "$7.B", - "$8.B", "$9.B", "$10.B","$11.B","$12.B","$13.B","$14.B","$15.B", - "$16.B","$17.B","$18.B","$19.B","$20.B","$21.B","$22.B","$23.B", - "$24.B","$25.B","$26.B","$27.B","$gp.B","$sp.B","$30.B","$31.B" - } -}; - -static char *c0_opname[64] = { - "c0op0","tlbr","tlbwi","c0op3","c0op4","c0op5","tlbwr","c0op7", - "tlbp","c0op9","c0op10","c0op11","c0op12","c0op13","c0op14","c0op15", - "rfe","c0op17","c0op18","c0op19","c0op20","c0op21","c0op22","c0op23", - "c0op24","c0op25","c0op26","c0op27","c0op28","c0op29","c0op30","c0op31", - "c0op32","c0op33","c0op34","c0op35","c0op36","c0op37","c0op38","c0op39", - "c0op40","c0op41","c0op42","c0op43","c0op44","c0op45","c0op46","c0op47", - "c0op48","c0op49","c0op50","c0op51","c0op52","c0op53","c0op54","c0op55", - "c0op56","c0op57","c0op58","c0op59","c0op60","c0op61","c0op62","c0op63" -}; - -static char *c0_reg[32] = { - "index","random","tlblo","c0r3","context","c0r5","c0r6","c0r7", - "badvaddr","c0r9","tlbhi","epcn","sr", "cause","epc", "c0r15", - "c0r16","c0r17","c0r18","c0r19","c0r20","c0r21","c0r22","c0r23", - "c0r24","c0r25","c0r26","c0r27","c0r28","c0r29","c0r30","c0r31" -}; - -/* Remember the options set by dis_init */ -//#define ADDR_DEFAULT "%#010x:\t" -#define ADDR_DEFAULT 0 -//#define VALUE_DEFAULT "%#010x\t" -#define VALUE_DEFAULT 0 -#define NAME_DEFAULT COMPILER_NAMES -static struct { - char *addr_format; - char *value_format; - const char **reg_names; - int print_jal_targets; -} save = { - ADDR_DEFAULT, - VALUE_DEFAULT, - NAME_DEFAULT, - true -}; - -/* Update regmask to reflect the use of this general-purpose (not fp) - register, and return its name */ -static const char * -register_name(ireg, boosted, regmask) -unsigned ireg, *regmask; -int boosted; -{ - if (!boosted) - *regmask |= (1 << ireg); - return save.reg_names[boosted ? ireg + 32 : ireg]; -} - -/* public -- see dissassembler.h */ -int -tdisasm(buffer, address, iword, ext, regmask, symbol_value, ls_register) -char *buffer; -unsigned char ext; /* extension byte */ -unsigned address, iword, *regmask, *symbol_value, *ls_register; -{ - int return_value = 0; - char *bufptr = buffer; - boolean do_b_displacement = false; - boolean do_loadstore = false; - union mips_instruction i; - union extension_byte e; - - *bufptr = 0; - i.word = iword; - e.byte = ext; - *regmask = *symbol_value = *ls_register = 0; - - /* Put out the address and hex value of the instruction, - leaving bufptr set at the end */ - if (save.addr_format) { - sprintf(bufptr, save.addr_format, address); - bufptr += strlen(bufptr); - } - if (save.value_format) { - sprintf(bufptr, save.value_format, iword); - bufptr += strlen(bufptr); - } - - /* check for dynamic NOP */ - if (e.e.dyn_nop) { - strcat(bufptr, "D."); - bufptr += 2; - } - - /* decode the instruction */ - switch (i.j_format.opcode) { - - case spec_op: - - if (i.word == 0x20) { - strcat(bufptr, "nop"); - if (e.e.rd_boost) - strcat(bufptr, ".B"); - bufptr += strlen(bufptr); - break; - } else if (i.r_format.func == addu_op && i.r_format.rt == ZERO) { - sprintf(bufptr, "move%s\t%s,%s", - e.e.rd_boost ? ".B" : "", - register_name(i.r_format.rd, e.e.rd_boost, regmask), - register_name(i.r_format.rs, e.e.rs_boost, regmask)); - bufptr += strlen(bufptr); - break; - } - strcat(bufptr, spec_name[i.r_format.func]); - if (e.e.rd_boost) - strcat(bufptr, ".B"); - bufptr += strlen(bufptr); - - switch (i.r_format.func) { - case sll_op: - case srl_op: - case sra_op: - sprintf(bufptr, "\t%s,%s,%d", - register_name(i.r_format.rd, e.e.rd_boost, regmask), - register_name(i.r_format.rt, e.e.rt_boost, regmask), - i.r_format.re); - break; - case sllv_op: - case srlv_op: - case srav_op: - sprintf(bufptr, "\t%s,%s,%s", - register_name(i.r_format.rd, e.e.rd_boost, regmask), - register_name(i.r_format.rt, e.e.rt_boost, regmask), - register_name(i.r_format.rs, e.e.rs_boost, regmask)); - break; - case mfhi_op: - case mflo_op: - sprintf(bufptr, "\t%s", - register_name(i.r_format.rd, e.e.rd_boost, regmask)); - break; - case jalr_op: - return_value = 3; - sprintf(bufptr, "\t%s,%s", - register_name(i.r_format.rd, e.e.rd_boost, regmask), - register_name(i.r_format.rs, e.e.rs_boost, regmask)); - *ls_register = i.r_format.rs; - break; - case jr_op: - return_value = 3; - *ls_register = i.r_format.rs; - /* fall through */ - case mtlo_op: - case mthi_op: - sprintf(bufptr, "\t%s", - register_name(i.r_format.rs, e.e.rs_boost, regmask)); - break; - case mult_op: - case multu_op: - case div_op: - case divu_op: - sprintf(bufptr, "\t%s,%s", - register_name(i.r_format.rs, e.e.rs_boost, regmask), - register_name(i.r_format.rt, e.e.rt_boost, regmask)); - break; - case syscall_op: - break; - case break_op: - case vcall_op: - { - char *format = "\t%d"; - unsigned op2 = i.r_format.rd * 32 + i.r_format.re; - - if (op2) - format = "\t%d,%d"; - sprintf(bufptr, format, i.r_format.rs*32+i.r_format.rt, - op2); - } - break; - default: - sprintf(bufptr, "\t%s,%s,%s", - register_name(i.r_format.rd, e.e.rd_boost, regmask), - register_name(i.r_format.rs, e.e.rs_boost, regmask), - register_name(i.r_format.rt, e.e.rt_boost, regmask)); - break; - }; - break; - - case bcond_op: - sprintf(bufptr, "%s%s\t%s,", - bcond_name[i.i_format.rt], - e.e.rd_boost ? ".B" : "", - register_name(i.i_format.rs, e.e.rs_boost, regmask)); - do_b_displacement = true; - break; - - case blez_op_T: - case bgtz_op_T: - case blez_op_N: - case bgtz_op_N: - sprintf(bufptr, "%s%s\t%s,", op_name[i.i_format.opcode], - e.e.rd_boost ? ".B" : "", - register_name(i.i_format.rs, e.e.rs_boost, regmask)); - do_b_displacement = true; - break; - case beq_op_T: - case beq_op_N: - if (i.i_format.rs == ZERO && i.i_format.rt == ZERO) { - strcat(bufptr, "b"); - if (i.j_format.opcode == beq_op_T) - strcat(bufptr, ".T"); - else - strcat(bufptr, ".N"); - if (e.e.rd_boost) - strcat(bufptr, ".B\t"); - else - strcat(bufptr, "\t"); - do_b_displacement = true; - break; - } - /* fall through */ - case bne_op_T: - case bne_op_N: - sprintf(bufptr, "%s%s\t%s,%s,", op_name[i.i_format.opcode], - e.e.rd_boost ? ".B" : "", - register_name(i.i_format.rs, e.e.rs_boost, regmask), - register_name(i.i_format.rt, e.e.rt_boost, regmask)); - do_b_displacement = true; - break; - - case cop0_op: - case cop1_op: - case cop2_op: - case cop3_op: - { - unsigned which_cop = i.j_format.opcode - cop0_op; - char *f_or_r = "rf"; - - switch (i.r_format.rs) { - case bc_op_T: - sprintf(bufptr, "bc%d%c.T%s\t", which_cop, - "ft"[i.r_format.rt], - e.e.rd_boost ? ".B" : ""); - do_b_displacement = true; - break; - case bc_op_N: - sprintf(bufptr, "bc%d%c.N%s\t", which_cop, - "ft"[i.r_format.rt], - e.e.rd_boost ? ".B" : ""); - do_b_displacement = true; - break; - case mtc_op: - if (which_cop == 0) - sprintf(bufptr, "mtc%d%s\t%s,%s", which_cop, - e.e.rd_boost ? ".B" : "", - register_name(i.r_format.rt, e.e.rt_boost,regmask), - c0_reg[i.f_format.rd]); - else - sprintf(bufptr, "mtc%d%s\t%s,%c%d", which_cop, - e.e.rd_boost ? ".B" : "", - register_name(i.r_format.rt, e.e.rt_boost,regmask), - f_or_r[(which_cop == 1)], - i.f_format.rd); - break; - case mfc_op: - if (which_cop == 0) - sprintf(bufptr, "mfc%d%s\t%s,%s", which_cop, - e.e.rd_boost ? ".B" : "", - register_name(i.r_format.rt, e.e.rt_boost,regmask), - c0_reg[i.f_format.rd]); - else - sprintf(bufptr, "mfc%d%s\t%s,%c%d", which_cop, - e.e.rd_boost ? ".B" : "", - register_name(i.r_format.rt, e.e.rt_boost,regmask), - f_or_r[(which_cop == 1)], - i.f_format.rd); - break; - case cfc_op: - sprintf(bufptr, "cfc%d%s\t%s,%c%d", which_cop, - e.e.rd_boost ? ".B" : "", - register_name(i.r_format.rt, e.e.rt_boost, regmask), - f_or_r[(which_cop == 1)], - i.f_format.rd); - break; - case ctc_op: - sprintf(bufptr, "ctc%d%s\t%s,%c%d", which_cop, - e.e.rd_boost ? ".B" : "", - register_name(i.r_format.rt, e.e.rt_boost, regmask), - f_or_r[(which_cop == 1)], - i.f_format.rd); - break; - default: - if (which_cop != 1) - sprintf(bufptr, "c0%s\t%s", e.e.rd_boost ? ".B" : "", - c0_opname[i.f_format.func]); - else - { - sprintf(bufptr, "%s.%s%s\t", - cop1_name[i.f_format.func], - fmt_name[i.f_format.fmt], - e.e.rd_boost ? ".B" : ""); - bufptr += strlen(bufptr); - switch (i.f_format.func) { - case fsqrt_op: - case fabs_op: - case fmov_op: - case fcvts_op: - case fcvtd_op: - case fcvte_op: - case fcvtw_op: - sprintf(bufptr, "f%d,f%d", - i.f_format.re, - i.f_format.rd); - break; - case fcmp_op+0x0: - case fcmp_op+0x1: - case fcmp_op+0x2: - case fcmp_op+0x3: - case fcmp_op+0x4: - case fcmp_op+0x5: - case fcmp_op+0x6: - case fcmp_op+0x7: - case fcmp_op+0x8: - case fcmp_op+0x9: - case fcmp_op+0xa: - case fcmp_op+0xb: - case fcmp_op+0xc: - case fcmp_op+0xd: - case fcmp_op+0xe: - case fcmp_op+0xf: - sprintf(bufptr, "f%d,f%d", - i.f_format.rd, - i.f_format.rt); - break; - default: - sprintf(bufptr, "f%d,f%d,f%d", - i.f_format.re, - i.f_format.rd, - i.f_format.rt); - break; - } /* switch on func */ - } - break; /* End of default */ - } /* switch on rs */ - } - break; /* End of cop0, cop1, cop2, cop3 */ - - case jal_op: - case j_op: - sprintf(bufptr, "%s%s\t", op_name[i.j_format.opcode], - e.e.rd_boost ? ".B" : ""); - *symbol_value = (address & 0xF0000000) | i.j_format.target << 2; - if (save.print_jal_targets) - { - bufptr += strlen(bufptr); - sprintf(bufptr, "%#x", *symbol_value); - } - return_value = 1; - break; - - case swc1_op: - case sdc1_op: - case lwc1_op: - case ldc1_op: - sprintf(bufptr, "%s%s\tf%d,", op_name[i.i_format.opcode], - e.e.rd_boost ? ".B" : "", - i.i_format.rt); - do_loadstore = true; - break; - - case lb_op: - case lh_op: - case lw_op: - case ld_op: - case lbu_op: - case lhu_op: - case sb_op: - case sh_op: - case sw_op: - case sd_op: - case lwl_op: - case lwr_op: - sprintf(bufptr, "%s%s\t%s,", op_name[i.i_format.opcode], - e.e.rd_boost ? ".B" : "", - register_name(i.i_format.rt, e.e.rt_boost, regmask)); - do_loadstore = true; - break; - - case ori_op: - case xori_op: - if (i.u_format.rs == ZERO) { - sprintf(bufptr, "li%s\t%s,%d", - e.e.rd_boost ? ".B" : "", - register_name(i.u_format.rt, e.e.rt_boost, regmask), - i.u_format.uimmediate); - break; - } - /* fall through */ - case andi_op: - sprintf(bufptr, "%s%s\t%s,%s,%#x", op_name[i.u_format.opcode], - e.e.rd_boost ? ".B" : "", - register_name(i.u_format.rt, e.e.rt_boost, regmask), - register_name(i.u_format.rs, e.e.rs_boost, regmask), - i.u_format.uimmediate); - break; - case lui_op: - sprintf(bufptr, "%s%s\t%s,%#x", op_name[i.u_format.opcode], - e.e.rd_boost ? ".B" : "", - register_name(i.u_format.rt, e.e.rt_boost, regmask), - i.u_format.uimmediate); - break; - case addi_op: - case addiu_op: - if (i.i_format.rs == ZERO) { - short sign_extender = i.i_format.simmediate; - sprintf(bufptr, "li%s\t%s,%d", - e.e.rd_boost ? ".B" : "", - register_name(i.i_format.rt, e.e.rt_boost, regmask), - sign_extender); - break; - } - /* fall through */ - default: - { - short sign_extender = i.i_format.simmediate; - sprintf(bufptr, "%s%s\t%s,%s,%d", op_name[i.i_format.opcode], - e.e.rd_boost ? ".B" : "", - register_name(i.i_format.rt, e.e.rt_boost, regmask), - register_name(i.i_format.rs, e.e.rs_boost, regmask), - sign_extender); - } - break; - } - - /* Some instructions require more than just registers */ - - if (do_loadstore) - { - short sign_extender = i.i_format.simmediate; - *symbol_value = sign_extender; - *ls_register = i.i_format.rs; - bufptr += strlen(bufptr); - sprintf(bufptr, "%d(%s)", sign_extender, - register_name(i.i_format.rs, e.e.rs_boost, regmask)); - return_value = -1; - } - else if (do_b_displacement) - { - short sign_extender = i.i_format.simmediate; - bufptr += strlen(bufptr); - *symbol_value = 4 + address + ((((long)sign_extender & 0xFFFD0000) | (0x3FFFF & (sign_extender << 2)))); - sprintf(bufptr, "%#x", *symbol_value); - return_value = 2; - } - - return return_value; -} - diff --git a/lib/CPUs/MIPS/bsp/examples/mipsdis.h b/lib/CPUs/MIPS/bsp/examples/mipsdis.h deleted file mode 100644 index 2e9aca4..0000000 --- a/lib/CPUs/MIPS/bsp/examples/mipsdis.h +++ /dev/null @@ -1,450 +0,0 @@ -/* ------------------------------------------------------------------ */ -/* | Copyright Unpublished, MIPS Computer Systems, Inc. All Rights | */ -/* | Reserved. This software contains proprietary and confidential | */ -/* | information of MIPS and its suppliers. Use, disclosure or | */ -/* | reproduction is prohibited without the prior express written | */ -/* | consent of MIPS. | */ -/* ------------------------------------------------------------------ */ -/* inst.h 4.2 */ -/* - * inst.h -- instruction format defines - */ - -/** - ** UPDATE - 19 Sept 89 by Michael Smith - ** - ** Removed signed type to remove obnoxious C++ warning message. - **/ - -#ifdef LANGUAGE_C -#ifdef MIPSEB -union mips_instruction { - unsigned word; - unsigned char byte[4]; - struct { - unsigned opcode : 6; - unsigned target : 26; - } j_format; - struct { - unsigned opcode : 6; - unsigned rs : 5; - unsigned rt : 5; - unsigned simmediate : 16; - } i_format; - struct { - unsigned opcode : 6; - unsigned rs : 5; - unsigned rt : 5; - unsigned uimmediate : 16; - } u_format; - struct { - unsigned opcode : 6; - unsigned rs : 5; - unsigned rt : 5; - unsigned rd : 5; - unsigned re : 5; - unsigned func : 6; - } r_format; - struct { - unsigned opcode : 6; - unsigned : 1; - unsigned fmt : 4; - unsigned rt : 5; - unsigned rd : 5; - unsigned re : 5; - unsigned func : 6; - } f_format; -}; -#endif - -#ifdef MIPSEL -union mips_instruction { - unsigned word; - unsigned char byte[4]; - struct { - unsigned target : 26; - unsigned opcode : 6; - } j_format; - struct { - unsigned simmediate : 16; - unsigned rt : 5; - unsigned rs : 5; - unsigned opcode : 6; - } i_format; - struct { - unsigned uimmediate : 16; - unsigned rt : 5; - unsigned rs : 5; - unsigned opcode : 6; - } u_format; - struct { - unsigned func : 6; - unsigned re : 5; - unsigned rd : 5; - unsigned rt : 5; - unsigned rs : 5; - unsigned opcode : 6; - } r_format; - struct { - unsigned func : 6; - unsigned re : 5; - unsigned rd : 5; - unsigned rt : 5; - unsigned fmt : 4; - unsigned : 1; - unsigned opcode : 6; - } f_format; -}; -#endif - -#define spec_op 0x00 -#define bcond_op 0x01 -#define j_op 0x02 -#define jal_op 0x03 - -#define beq_op 0x04 -#define bne_op 0x05 -#define blez_op 0x06 -#define bgtz_op 0x07 - -#define addi_op 0x08 -#define addiu_op 0x09 -#define slti_op 0x0A -#define sltiu_op 0x0B - -#define andi_op 0x0C -#define ori_op 0x0D -#define xori_op 0x0E -#define lui_op 0x0F - -#define lb_op 0x20 -#define lh_op 0x21 -#define lw_op 0x23 -#define lbu_op 0x24 -#define lhu_op 0x25 -#define ld_op 0x27 -#define sb_op 0x28 -#define sh_op 0x29 -#define sw_op 0x2B -#define sd_op 0x2F -#define lwl_op 0x22 -#define lwr_op 0x26 -#define swl_op 0x2a -#define swr_op 0x2e - -/* Co-processor sub-opcodes */ -#define bc_op 0x08 -#define mfc_op 0x00 -#define cfc_op 0x02 -#define mtc_op 0x04 -#define ctc_op 0x06 - -/* Co-processor 0 opcodes */ -#define cop0_op 0x10 -#define lwc0_op 0x30 -#define ldc0_op 0x34 -#define swc0_op 0x38 -#define sdc0_op 0x3c - -/* Co-processor 0 sub-opcodes */ -#define tlbr_op 0x1 -#define tlbwi_op 0x2 -#define tlbwr_op 0x6 -#define tlbp_op 0x8 -#define rfe_op 0x10 - -/* Co-processor 1 opcodes */ -#define cop1_op 0x11 -#define lwc1_op 0x31 -#define ldc1_op 0x35 -#define swc1_op 0x39 -#define sdc1_op 0x3D - -/* Co-processor 1 sub-opcodes */ -#define fadd_op 0x00 -#define fsub_op 0x01 -#define fmpy_op 0x02 -#define fdiv_op 0x03 -#define fsqrt_op 0x04 -#define fabs_op 0x05 -#define fmov_op 0x06 -#define fneg_op 0x07 -#define fcvts_op 0x20 -#define fcvtd_op 0x21 -#define fcvte_op 0x22 -#define fcvtw_op 0x24 -#define fcmp_op 0x30 -#define s_fmt 0 -#define d_fmt 1 -#define e_fmt 2 -#define w_fmt 4 - -/* Other coprocessor opcodes */ -#define cop2_op 0x12 -#define lwc2_op 0x32 -#define ldc2_op 0x36 -#define swc2_op 0x3a -#define sdc2_op 0x3e - -#define cop3_op 0x13 -#define lwc3_op 0x33 -#define ldc3_op 0x37 -#define swc3_op 0x3b -#define sdc3_op 0x3f - - -/* bcond subopcodes */ -#define bltz_op 0x00 -#define bgez_op 0x01 -#define bltzal_op 0x10 -#define bgezal_op 0x11 - -/* special subopcodes */ -#define sll_op 0x00 -#define srl_op 0x02 -#define sra_op 0x03 -#define sllv_op 0x04 -#define srlv_op 0x06 -#define srav_op 0x07 -#define jr_op 0x08 -#define jalr_op 0x09 -#define syscall_op 0x0C -#define break_op 0x0D -#define vcall_op 0x0E - -#define mfhi_op 0x10 -#define mthi_op 0x11 -#define mflo_op 0x12 -#define mtlo_op 0x13 -#define mult_op 0x18 -#define multu_op 0x19 -#define div_op 0x1A -#define divu_op 0x1B - -#define add_op 0x20 -#define addu_op 0x21 -#define and_op 0x24 -#define or_op 0x25 -#define xor_op 0x26 -#define nor_op 0x27 -#define sub_op 0x22 -#define subu_op 0x23 -#define slt_op 0x2A -#define sltu_op 0x2B - -#endif /* LANGUAGE_C */ - -#ifdef LANGUAGE_PASCAL - -#ifdef MIPSEB -type - mips_instruction = - packed record - case cardinal of - 0: ( - word: cardinal; - ); - 1: ( - byte: packed array[0..3] of 0..255; - ); - 2: ( - opcode: 0..63; - target: 0..67108863; - ); - 3: ( - opcode3: 0..63; - rs: 0..31; - rt: 0..31; - simmediate: -32768..32767; - ); - 4: ( - opcode4: 0..63; - rs4: 0..63; - rt4: 0..63; - uimmediate: 0..65535; - ); - 5: ( - opcode5: 0..63; - rs5: 0..63; - rt5: 0..63; - rd5: 0..63; - re5: 0..63; - func: 0..63; - ); - end {record}; -#endif - -#ifdef MIPSEL -type - mips_instruction = - packed record - case cardinal of - 0: ( - word: cardinal; - ); - 1: ( - byte: packed array[0..3] of 0..255; - ); - 2: ( - target: 0..67108863; - opcode: 0..63; - ); - 3: ( - simmediate: -32768..32767; - rt: 0..31; - rs: 0..31; - opcode3: 0..63; - ); - 4: ( - uimmediate: 0..65535; - rt4: 0..63; - rs4: 0..63; - opcode4: 0..63; - ); - 5: ( - func: 0..63; - re5: 0..63; - rd5: 0..63; - rt5: 0..63; - rs5: 0..63; - opcode5: 0..63; - ); - end {record}; -#endif - -#define spec_op 16#00 -#define bcond_op 16#01 -#define j_op 16#02 -#define jal_op 16#03 - -#define beq_op 16#04 -#define bne_op 16#05 -#define blez_op 16#06 -#define bgtz_op 16#07 - -#define addi_op 16#08 -#define addiu_op 16#09 -#define slti_op 16#0A -#define sltiu_op 16#0B - -#define andi_op 16#0C -#define ori_op 16#0D -#define xori_op 16#0E -#define lui_op 16#0F - -#define lb_op 16#20 -#define lh_op 16#21 -#define lw_op 16#23 -#define lbu_op 16#24 -#define lhu_op 16#25 -#define ld_op 16#27 -#define sb_op 16#28 -#define sh_op 16#29 -#define sw_op 16#2B -#define sd_op 16#2F -#define lwl_op 16#22 -#define lwr_op 16#26 -#define swl_op 16#2a -#define swr_op 16#2e - -/* Co-processor sub-opcodes */ -#define bc_op 16#08 -#define mfc_op 16#00 -#define cfc_op 16#02 -#define mtc_op 16#04 -#define ctc_op 16#06 - -/* Co-processor 0 opcodes */ -#define cop0_op 16#10 -#define lwc0_op 16#30 -#define ldc0_op 16#34 -#define swc0_op 16#38 -#define sdc0_op 16#3c - -/* Co-processor 0 sub-opcodes */ -#define tlbr_op 16#1 -#define tlbwi_op 16#2 -#define tlbwr_op 16#6 -#define tlbp_op 16#8 -#define rfe_op 16#10 - -/* Co-processor 1 opcodes */ -#define cop1_op 16#11 -#define lwc1_op 16#31 -#define ldc1_op 16#35 -#define swc1_op 16#39 -#define sdc1_op 16#3D - -/* Co-processor 1 sub-opcodes */ -#define fadd_op 16#00 -#define fsub_op 16#01 -#define fmpy_op 16#02 -#define fdiv_op 16#03 -#define fsqrt_op 16#04 -#define fabs_op 16#05 -#define fmov_op 16#06 -#define fneg_op 16#07 -#define fcvts_op 16#20 -#define fcvtd_op 16#21 -#define fcvte_op 16#22 -#define fcvtw_op 16#24 -#define fcmp_op 16#30 -#define s_fmt 0 -#define d_fmt 1 -#define e_fmt 2 -#define w_fmt 4 - -/* Other coprocessor opcodes */ -#define cop2_op 16#12 -#define lwc2_op 16#32 -#define ldc2_op 16#36 -#define swc2_op 16#3a -#define sdc2_op 16#3e - -#define cop3_op 16#13 -#define lwc3_op 16#33 -#define ldc3_op 16#37 -#define swc3_op 16#3b -#define sdc3_op 16#3f - - -/* bcond subopcodes */ -#define bltz_op 16#00 -#define bgez_op 16#01 -#define bltzal_op 16#10 -#define bgezal_op 16#11 - -/* special subopcodes */ -#define sll_op 16#00 -#define srl_op 16#02 -#define sra_op 16#03 -#define sllv_op 16#04 -#define srlv_op 16#06 -#define srav_op 16#07 -#define jr_op 16#08 -#define jalr_op 16#09 -#define syscall_op 16#0C -#define break_op 16#0D -#define vcall_op 16#0E - -#define mfhi_op 16#10 -#define mthi_op 16#11 -#define mflo_op 16#12 -#define mtlo_op 16#13 -#define mult_op 16#18 -#define multu_op 16#19 -#define div_op 16#1A -#define divu_op 16#1B - -#define add_op 16#20 -#define addu_op 16#21 -#define and_op 16#24 -#define or_op 16#25 -#define xor_op 16#26 -#define nor_op 16#27 -#define sub_op 16#22 -#define subu_op 16#23 -#define slt_op 16#2A -#define sltu_op 16#2B - -#endif /* LANGUAGE_PASCAL */ diff --git a/lib/CPUs/MIPS/bsp/examples/paranoia.c b/lib/CPUs/MIPS/bsp/examples/paranoia.c deleted file mode 100644 index 38f08e1..0000000 --- a/lib/CPUs/MIPS/bsp/examples/paranoia.c +++ /dev/null @@ -1,2302 +0,0 @@ -/* - * paranoia.c,v 1.4 1995/08/23 19:26:32 joel Exp - * - * A C version of Kahan's Floating Point Test "Paranoia" - * - * Thos Sumner, UCSF, Feb. 1985 - * David Gay, BTL, Jan. 1986 - * - * This is a rewrite from the Pascal version by - * - * B. A. Wichmann, 18 Jan. 1985 - * - * (and does NOT exhibit good C programming style). - * - * Sun May 16 18:21:51 MDT 1993 Jeffrey Wheat (cassidy@cygnus.com) - * Removed KR_headers defines, removed ANSI prototyping - * Cleaned up and reformated code. Added special CYGNUS - * "verbose" mode type messages (-DCYGNUS). - * Note: This code is VERY NASTY. - * - * Adjusted to use Standard C headers 19 Jan. 1992 (dmg); - * compile with -DKR_headers or insert - * #define KR_headers - * at the beginning if you have an old-style C compiler. - * - * (C) Apr 19 1983 in BASIC version by: - * Professor W. M. Kahan, - * 567 Evans Hall - * Electrical Engineering & Computer Science Dept. - * University of California - * Berkeley, California 94720 - * USA - * - * converted to Pascal by: - * B. A. Wichmann - * National Physical Laboratory - * Teddington Middx - * TW11 OLW - * UK - * - * converted to C by: - * - * David M. Gay and Thos Sumner - * AT&T Bell Labs Computer Center, Rm. U-76 - * 600 Mountain Avenue University of California - * Murray Hill, NJ 07974 San Francisco, CA 94143 - * USA USA - * - * with simultaneous corrections to the Pascal source (reflected - * in the Pascal source available over netlib). - * [A couple of bug fixes from dgh = sun!dhough incorporated 31 July 1986.] - * - * Reports of results on various systems from all the versions - * of Paranoia are being collected by Richard Karpinski at the - * same address as Thos Sumner. This includes sample outputs, - * bug reports, and criticisms. - * - * You may copy this program freely if you acknowledge its source. - * Comments on the Pascal version to NPL, please. - * - * - * The C version catches signals from floating-point exceptions. - * If signal(SIGFPE,...) is unavailable in your environment, you may - * #define NOSIGNAL to comment out the invocations of signal. - * - * This source file is too big for some C compilers, but may be split - * into pieces. Comments containing "SPLIT" suggest convenient places - * for this splitting. At the end of these comments is an "ed script" - * (for the UNIX(tm) editor ed) that will do this splitting. - * - * By #defining SINGLE_PRECISION when you compile this source, you may - * obtain a single-precision C version of Paranoia. - * - * The following is from the introductory commentary from Wichmann's work: - * - * The BASIC program of Kahan is written in Microsoft BASIC using many - * facilities which have no exact analogy in Pascal. The Pascal - * version below cannot therefore be exactly the same. Rather than be - * a minimal transcription of the BASIC program, the Pascal coding - * follows the conventional style of block-structured languages. Hence - * the Pascal version could be useful in producing versions in other - * structured languages. - * - * Rather than use identifiers of minimal length (which therefore have - * little mnemonic significance), the Pascal version uses meaningful - * identifiers as follows [Note: A few changes have been made for C]: - * - * - * BASIC C BASIC C BASIC C - * - * A J S StickyBit - * A1 AInverse J0 NoErrors T - * B Radix [Failure] T0 Underflow - * B1 BInverse J1 NoErrors T2 ThirtyTwo - * B2 RadixD2 [SeriousDefect] T5 OneAndHalf - * B9 BMinusU2 J2 NoErrors T7 TwentySeven - * C [Defect] T8 TwoForty - * C1 CInverse J3 NoErrors U OneUlp - * D [Flaw] U0 UnderflowThreshold - * D4 FourD K PageNo U1 - * E0 L Milestone U2 - * E1 M V - * E2 Exp2 N V0 - * E3 N1 V8 - * E5 MinSqEr O Zero V9 - * E6 SqEr O1 One W - * E7 MaxSqEr O2 Two X - * E8 O3 Three X1 - * E9 O4 Four X8 - * F1 MinusOne O5 Five X9 Random1 - * F2 Half O8 Eight Y - * F3 Third O9 Nine Y1 - * F6 P Precision Y2 - * F9 Q Y9 Random2 - * G1 GMult Q8 Z - * G2 GDiv Q9 Z0 PseudoZero - * G3 GAddSub R Z1 - * H R1 RMult Z2 - * H1 HInverse R2 RDiv Z9 - * I R3 RAddSub - * IO NoTrials R4 RSqrt - * I3 IEEE R9 Random9 - * - * SqRWrng - * - * All the variables in BASIC are true variables and in consequence, - * the program is more difficult to follow since the "constants" must - * be determined (the glossary is very helpful). The Pascal version - * uses Real constants, but checks are added to ensure that the values - * are correctly converted by the compiler. - * - * The major textual change to the Pascal version apart from the - * identifiersis that named procedures are used, inserting parameters - * wherehelpful. New procedures are also introduced. The - * correspondence is as follows: - * - * - * BASIC Pascal - * lines - * - * 90- 140 Pause - * 170- 250 Instructions - * 380- 460 Heading - * 480- 670 Characteristics - * 690- 870 History - * 2940-2950 Random - * 3710-3740 NewD - * 4040-4080 DoesYequalX - * 4090-4110 PrintIfNPositive - * 4640-4850 TestPartialUnderflow - * -*/ - -#include -#include - -/* - * To compile this on host using only libm from newlib (and using host libc) - * do: - * gcc -g -DNEED_REENT -DCYGNUS paranoia.c .../newlib-1.6/newlib/libm.a - */ - -#ifdef NEED_REENT -#include -struct _reent libm_reent = _REENT_INIT(libm_reent); -struct _reent *_impure_ptr = &libm_reent; -#endif - -#ifndef NOSIGNAL -#include -#include -#else /* NOSIGNAL */ -#define longjmp(e,v) -#define setjmp(e) 0 -#define jmp_buf int -#endif /* NOSIGNAL */ - -#ifdef SINGLE_PRECISION -#define FLOAT float -#define FABS(x) (float)fabs((double)(x)) -#define FLOOR(x) (float)floor((double)(x)) -#define LOG(x) (float)log((double)(x)) -#define POW(x,y) (float)pow((double)(x),(double)(y)) -#define SQRT(x) (float)sqrt((double)(x)) -#else /* !SINGLE_PRECISION */ -#define FLOAT double -#define FABS(x) fabs(x) -#define FLOOR(x) floor(x) -#define LOG(x) log(x) -#define POW(x,y) pow(x,y) -#define SQRT(x) sqrt(x) -#endif /* SINGLE_PRECISION */ - -jmp_buf ovfl_buf; -extern double fabs (), floor (), log (), pow (), sqrt (); -extern void exit (); -typedef void (*Sig_type) (); -FLOAT Sign (), Random (); -extern void BadCond (); -extern void SqXMinX (); -extern void TstCond (); -extern void notify (); -extern int read (); -extern void Characteristics (); -extern void Heading (); -extern void History (); -extern void Instructions (); -extern void IsYeqX (); -extern void NewD (); -extern void Pause (); -extern void PrintIfNPositive (); -extern void SR3750 (); -extern void SR3980 (); -extern void TstPtUf (); - -Sig_type sigsave; - -#define KEYBOARD 0 - -FLOAT Radix, BInvrse, RadixD2, BMinusU2; - -/*Small floating point constants.*/ -FLOAT Zero = 0.0; -FLOAT Half = 0.5; -FLOAT One = 1.0; -FLOAT Two = 2.0; -FLOAT Three = 3.0; -FLOAT Four = 4.0; -FLOAT Five = 5.0; -FLOAT Eight = 8.0; -FLOAT Nine = 9.0; -FLOAT TwentySeven = 27.0; -FLOAT ThirtyTwo = 32.0; -FLOAT TwoForty = 240.0; -FLOAT MinusOne = -1.0; -FLOAT OneAndHalf = 1.5; - -/*Integer constants*/ -int NoTrials = 20; /*Number of tests for commutativity. */ -#define False 0 -#define True 1 - -/* - * Definitions for declared types - * Guard == (Yes, No); - * Rounding == (Chopped, Rounded, Other); - * Message == packed array [1..40] of char; - * Class == (Flaw, Defect, Serious, Failure); - */ -#define Yes 1 -#define No 0 -#define Chopped 2 -#define Rounded 1 -#define Other 0 -#define Flaw 3 -#define Defect 2 -#define Serious 1 -#define Failure 0 -typedef int Guard, Rounding, Class; -typedef char Message; - -/* Declarations of Variables */ -int Indx; -char ch[8]; -FLOAT AInvrse, A1; -FLOAT C, CInvrse; -FLOAT D, FourD; -FLOAT E0, E1, Exp2, E3, MinSqEr; -FLOAT SqEr, MaxSqEr, E9; -FLOAT Third; -FLOAT F6, F9; -FLOAT H, HInvrse; -int I; -FLOAT StickyBit, J; -FLOAT MyZero; -FLOAT Precision; -FLOAT Q, Q9; -FLOAT R, Random9; -FLOAT T, Underflow, S; -FLOAT OneUlp, UfThold, U1, U2; -FLOAT V, V0, V9; -FLOAT W; -FLOAT X, X1, X2, X8, Random1; -FLOAT Y, Y1, Y2, Random2; -FLOAT Z, PseudoZero, Z1, Z2, Z9; -int ErrCnt[4]; -int fpecount; -int Milestone; -int PageNo; -int M, N, N1; -Guard GMult, GDiv, GAddSub; -Rounding RMult, RDiv, RAddSub, RSqrt; -int Break, Done, NotMonot, Monot, Anomaly, IEEE, SqRWrng, UfNGrad; - -/* Computed constants. - * U1 gap below 1.0, i.e, 1.0 - U1 is next number below 1.0 - * U2 gap above 1.0, i.e, 1.0 + U2 is next number above 1.0 - */ - -int batchmode; /* global batchmode test */ - -/* program name and version variables and macro */ -char *temp; -char *program_name; -char *program_vers; - -#ifndef VERSION -#define VERSION "1.1 [cygnus]" -#endif /* VERSION */ - -#define basename(cp) ((temp=(char *)strrchr((cp), '/')) ? temp+1 : (cp)) - -#ifndef BATCHMODE -# ifdef CYGNUS -# define BATCHMODE -# endif -#endif - -/* floating point exception receiver */ -void -_sigfpe (x) -int x; -{ - fpecount++; - printf ("\n* * * FLOATING-POINT ERROR %d * * *\n", x); - fflush (stdout); - if (sigsave) { -#ifndef NOSIGNAL - signal (SIGFPE, sigsave); -#endif /* NOSIGNAL */ - sigsave = 0; - longjmp (ovfl_buf, 1); - } - exit (1); -} - -#ifdef NOMAIN -#define main paranoia -#endif - -int -main (argc, argv) -int argc; -char **argv; -{ - /* First two assignments use integer right-hand sides. */ - Zero = 0; - One = 1; - Two = One + One; - Three = Two + One; - Four = Three + One; - Five = Four + One; - Eight = Four + Four; - Nine = Three * Three; - TwentySeven = Nine * Three; - ThirtyTwo = Four * Eight; - TwoForty = Four * Five * Three * Four; - MinusOne = -One; - Half = One / Two; - OneAndHalf = One + Half; - ErrCnt[Failure] = 0; - ErrCnt[Serious] = 0; - ErrCnt[Defect] = 0; - ErrCnt[Flaw] = 0; - PageNo = 1; - -#ifdef BATCHMODE - batchmode = 1; /* run test in batchmode? */ -#else /* !BATCHMODE */ - batchmode = 0; /* run test interactively */ -#endif /* BATCHMODE */ - -/* - program_name = basename (argv[0]); -*/ - program_vers = VERSION; - - printf ("%s version %s\n", "Paranoia", program_vers); - - /*=============================================*/ - Milestone = 0; - /*=============================================*/ -#ifndef NOSIGNAL - signal (SIGFPE, _sigfpe); -#endif - - if (!batchmode) { - Instructions (); - Pause (); - Heading (); - Instructions (); - Pause (); - Heading (); - Pause (); - Characteristics (); - Pause (); - History (); - Pause (); - } - - /*=============================================*/ - Milestone = 7; - /*=============================================*/ - printf ("Program is now RUNNING tests on small integers:\n"); - TstCond (Failure, (Zero + Zero == Zero) && (One - One == Zero) - && (One > Zero) && (One + One == Two), - "0+0 != 0, 1-1 != 0, 1 <= 0, or 1+1 != 2"); - Z = -Zero; - if (Z != 0.0) { - ErrCnt[Failure] = ErrCnt[Failure] + 1; - printf ("Comparison alleges that -0.0 is Non-zero!\n"); - U1 = 0.001; - Radix = 1; - TstPtUf (); - } - TstCond (Failure, (Three == Two + One) && (Four == Three + One) - && (Four + Two * (-Two) == Zero) - && (Four - Three - One == Zero), - "3 != 2+1, 4 != 3+1, 4+2*(-2) != 0, or 4-3-1 != 0"); - TstCond (Failure, (MinusOne == (0 - One)) - && (MinusOne + One == Zero) && (One + MinusOne == Zero) - && (MinusOne + FABS (One) == Zero) - && (MinusOne + MinusOne * MinusOne == Zero), - "-1+1 != 0, (-1)+abs(1) != 0, or -1+(-1)*(-1) != 0"); - TstCond (Failure, Half + MinusOne + Half == Zero, - "1/2 + (-1) + 1/2 != 0"); - /*=============================================*/ - Milestone = 10; - /*=============================================*/ - TstCond (Failure, (Nine == Three * Three) - && (TwentySeven == Nine * Three) && (Eight == Four + Four) - && (ThirtyTwo == Eight * Four) - && (ThirtyTwo - TwentySeven - Four - One == Zero), - "9 != 3*3, 27 != 9*3, 32 != 8*4, or 32-27-4-1 != 0"); - TstCond (Failure, (Five == Four + One) && - (TwoForty == Four * Five * Three * Four) - && (TwoForty / Three - Four * Four * Five == Zero) - && (TwoForty / Four - Five * Three * Four == Zero) - && (TwoForty / Five - Four * Three * Four == Zero), - "5 != 4+1, 240/3 != 80, 240/4 != 60, or 240/5 != 48"); - if (ErrCnt[Failure] == 0) { - printf ("-1, 0, 1/2, 1, 2, 3, 4, 5, 9, 27, 32 & 240 are O.K.\n"); - printf ("\n"); - } - printf ("Searching for Radix and Precision.\n"); - W = One; - do { - W = W + W; - Y = W + One; - Z = Y - W; - Y = Z - One; - } - while (MinusOne + FABS (Y) < Zero); - /*.. now W is just big enough that |((W+1)-W)-1| >= 1 ...*/ - Precision = Zero; - Y = One; - do { - Radix = W + Y; - Y = Y + Y; - Radix = Radix - W; - } - while (Radix == Zero); - if (Radix < Two) - Radix = One; - printf ("Radix = %f .\n", Radix); - if (Radix != 1) { - W = One; - do { - Precision = Precision + One; - W = W * Radix; - Y = W + One; - } - while ((Y - W) == One); - } - /*... now W == Radix^Precision is barely too big to satisfy (W+1)-W == 1 - ...*/ - U1 = One / W; - U2 = Radix * U1; - printf ("Closest relative separation found is U1 = %.7e .\n\n", U1); - printf ("Recalculating radix and precision\n "); - - /*save old values*/ - E0 = Radix; - E1 = U1; - E9 = U2; - E3 = Precision; - - X = Four / Three; - Third = X - One; - F6 = Half - Third; - X = F6 + F6; - X = FABS (X - Third); - if (X < U2) - X = U2; - - /*... now X = (unknown no.) ulps of 1+...*/ - do { - U2 = X; - Y = Half * U2 + ThirtyTwo * U2 * U2; - Y = One + Y; - X = Y - One; - } - while (!((U2 <= X) || (X <= Zero))); - - /*... now U2 == 1 ulp of 1 + ... */ - X = Two / Three; - F6 = X - Half; - Third = F6 + F6; - X = Third - Half; - X = FABS (X + F6); - if (X < U1) - X = U1; - - /*... now X == (unknown no.) ulps of 1 -... */ - do { - U1 = X; - Y = Half * U1 + ThirtyTwo * U1 * U1; - Y = Half - Y; - X = Half + Y; - Y = Half - X; - X = Half + Y; - } - while (!((U1 <= X) || (X <= Zero))); - /*... now U1 == 1 ulp of 1 - ... */ - if (U1 == E1) - printf ("confirms closest relative separation U1 .\n"); - else - printf ("gets better closest relative separation U1 = %.7e .\n", U1); - W = One / U1; - F9 = (Half - U1) + Half; - Radix = FLOOR (0.01 + U2 / U1); - if (Radix == E0) - printf ("Radix confirmed.\n"); - else - printf ("MYSTERY: recalculated Radix = %.7e .\n", Radix); - TstCond (Defect, Radix <= Eight + Eight, - "Radix is too big: roundoff problems"); - TstCond (Flaw, (Radix == Two) || (Radix == 10) - || (Radix == One), "Radix is not as good as 2 or 10"); - /*=============================================*/ - Milestone = 20; - /*=============================================*/ - TstCond (Failure, F9 - Half < Half, - "(1-U1)-1/2 < 1/2 is FALSE, prog. fails?"); - X = F9; - I = 1; - Y = X - Half; - Z = Y - Half; - TstCond (Failure, (X != One) - || (Z == Zero), "Comparison is fuzzy,X=1 but X-1/2-1/2 != 0"); - X = One + U2; - I = 0; - /*=============================================*/ - Milestone = 25; - /*=============================================*/ - /*... BMinusU2 = nextafter(Radix, 0) */ - BMinusU2 = Radix - One; - BMinusU2 = (BMinusU2 - U2) + One; - /* Purify Integers */ - if (Radix != One) { - X = -TwoForty * LOG (U1) / LOG (Radix); - Y = FLOOR (Half + X); - if (FABS (X - Y) * Four < One) - X = Y; - Precision = X / TwoForty; - Y = FLOOR (Half + Precision); - if (FABS (Precision - Y) * TwoForty < Half) - Precision = Y; - } - if ((Precision != FLOOR (Precision)) || (Radix == One)) { - printf ("Precision cannot be characterized by an Integer number\n"); - printf ("of significant digits but, by itself, this is a minor flaw.\n"); - } - if (Radix == One) - printf ("logarithmic encoding has precision characterized solely by U1.\n"); - else - printf ("The number of significant digits of the Radix is %f .\n", - Precision); - TstCond (Serious, U2 * Nine * Nine * TwoForty < One, - "Precision worse than 5 decimal figures "); - /*=============================================*/ - Milestone = 30; - /*=============================================*/ - /* Test for extra-precise subepressions */ - X = FABS (((Four / Three - One) - One / Four) * Three - One / Four); - do { - Z2 = X; - X = (One + (Half * Z2 + ThirtyTwo * Z2 * Z2)) - One; - } - while (!((Z2 <= X) || (X <= Zero))); - X = Y = Z = FABS ((Three / Four - Two / Three) * Three - One / Four); - do { - Z1 = Z; - Z = (One / Two - ((One / Two - (Half * Z1 + ThirtyTwo * Z1 * Z1)) - + One / Two)) + One / Two; - } - while (!((Z1 <= Z) || (Z <= Zero))); - do { - do { - Y1 = Y; - Y = (Half - ((Half - (Half * Y1 + ThirtyTwo * Y1 * Y1)) + Half - )) + Half; - } - while (!((Y1 <= Y) || (Y <= Zero))); - X1 = X; - X = ((Half * X1 + ThirtyTwo * X1 * X1) - F9) + F9; - } - while (!((X1 <= X) || (X <= Zero))); - if ((X1 != Y1) || (X1 != Z1)) { - BadCond (Serious, "Disagreements among the values X1, Y1, Z1,\n"); - printf ("respectively %.7e, %.7e, %.7e,\n", X1, Y1, Z1); - printf ("are symptoms of inconsistencies introduced\n"); - printf ("by extra-precise evaluation of arithmetic subexpressions.\n"); - notify ("Possibly some part of this"); - if ((X1 == U1) || (Y1 == U1) || (Z1 == U1)) - printf ( - "That feature is not tested further by this program.\n"); - } else { - if ((Z1 != U1) || (Z2 != U2)) { - if ((Z1 >= U1) || (Z2 >= U2)) { - BadCond (Failure, ""); - notify ("Precision"); - printf ("\tU1 = %.7e, Z1 - U1 = %.7e\n", U1, Z1 - U1); - printf ("\tU2 = %.7e, Z2 - U2 = %.7e\n", U2, Z2 - U2); - } else { - if ((Z1 <= Zero) || (Z2 <= Zero)) { - printf ("Because of unusual Radix = %f", Radix); - printf (", or exact rational arithmetic a result\n"); - printf ("Z1 = %.7e, or Z2 = %.7e ", Z1, Z2); - notify ("of an\nextra-precision"); - } - if (Z1 != Z2 || Z1 > Zero) { - X = Z1 / U1; - Y = Z2 / U2; - if (Y > X) - X = Y; - Q = -LOG (X); - printf ("Some subexpressions appear to be calculated extra\n"); - printf ("precisely with about %g extra B-digits, i.e.\n", - (Q / LOG (Radix))); - printf ("roughly %g extra significant decimals.\n", - Q / LOG (10.)); - } - printf ("That feature is not tested further by this program.\n"); - } - } - } - Pause (); - /*=============================================*/ - Milestone = 35; - /*=============================================*/ - if (Radix >= Two) { - X = W / (Radix * Radix); - Y = X + One; - Z = Y - X; - T = Z + U2; - X = T - Z; - TstCond (Failure, X == U2, - "Subtraction is not normalized X=Y,X+Z != Y+Z!"); - if (X == U2) - printf ( - "Subtraction appears to be normalized, as it should be."); - } - printf ("\nChecking for guard digit in *, /, and -.\n"); - Y = F9 * One; - Z = One * F9; - X = F9 - Half; - Y = (Y - Half) - X; - Z = (Z - Half) - X; - X = One + U2; - T = X * Radix; - R = Radix * X; - X = T - Radix; - X = X - Radix * U2; - T = R - Radix; - T = T - Radix * U2; - X = X * (Radix - One); - T = T * (Radix - One); - if ((X == Zero) && (Y == Zero) && (Z == Zero) && (T == Zero)) - GMult = Yes; - else { - GMult = No; - TstCond (Serious, False, - "* lacks a Guard Digit, so 1*X != X"); - } - Z = Radix * U2; - X = One + Z; - Y = FABS ((X + Z) - X * X) - U2; - X = One - U2; - Z = FABS ((X - U2) - X * X) - U1; - TstCond (Failure, (Y <= Zero) - && (Z <= Zero), "* gets too many final digits wrong.\n"); - Y = One - U2; - X = One + U2; - Z = One / Y; - Y = Z - X; - X = One / Three; - Z = Three / Nine; - X = X - Z; - T = Nine / TwentySeven; - Z = Z - T; - TstCond (Defect, X == Zero && Y == Zero && Z == Zero, - "Division lacks a Guard Digit, so error can exceed 1 ulp\n\ -or 1/3 and 3/9 and 9/27 may disagree"); - Y = F9 / One; - X = F9 - Half; - Y = (Y - Half) - X; - X = One + U2; - T = X / One; - X = T - X; - if ((X == Zero) && (Y == Zero) && (Z == Zero)) - GDiv = Yes; - else { - GDiv = No; - TstCond (Serious, False, - "Division lacks a Guard Digit, so X/1 != X"); - } - X = One / (One + U2); - Y = X - Half - Half; - TstCond (Serious, Y < Zero, - "Computed value of 1/1.000..1 >= 1"); - X = One - U2; - Y = One + Radix * U2; - Z = X * Radix; - T = Y * Radix; - R = Z / Radix; - StickyBit = T / Radix; - X = R - X; - Y = StickyBit - Y; - TstCond (Failure, X == Zero && Y == Zero, - "* and/or / gets too many last digits wrong"); - Y = One - U1; - X = One - F9; - Y = One - Y; - T = Radix - U2; - Z = Radix - BMinusU2; - T = Radix - T; - if ((X == U1) && (Y == U1) && (Z == U2) && (T == U2)) - GAddSub = Yes; - else { - GAddSub = No; - TstCond (Serious, False, - "- lacks Guard Digit, so cancellation is obscured"); - } - if (F9 != One && F9 - One >= Zero) { - BadCond (Serious, "comparison alleges (1-U1) < 1 although\n"); - printf (" subtraction yields (1-U1) - 1 = 0 , thereby vitiating\n"); - printf (" such precautions against division by zero as\n"); - printf (" ... if (X == 1.0) {.....} else {.../(X-1.0)...}\n"); - } - if (GMult == Yes && GDiv == Yes && GAddSub == Yes) - printf ( - " *, /, and - appear to have guard digits, as they should.\n"); - /*=============================================*/ - Milestone = 40; - /*=============================================*/ - Pause (); - printf ("Checking rounding on multiply, divide and add/subtract.\n"); - RMult = Other; - RDiv = Other; - RAddSub = Other; - RadixD2 = Radix / Two; - A1 = Two; - Done = False; - do { - AInvrse = Radix; - do { - X = AInvrse; - AInvrse = AInvrse / A1; - } - while (!(FLOOR (AInvrse) != AInvrse)); - Done = (X == One) || (A1 > Three); - if (!Done) - A1 = Nine + One; - } - while (!(Done)); - if (X == One) - A1 = Radix; - AInvrse = One / A1; - X = A1; - Y = AInvrse; - Done = False; - do { - Z = X * Y - Half; - TstCond (Failure, Z == Half, - "X * (1/X) differs from 1"); - Done = X == Radix; - X = Radix; - Y = One / X; - } - while (!(Done)); - Y2 = One + U2; - Y1 = One - U2; - X = OneAndHalf - U2; - Y = OneAndHalf + U2; - Z = (X - U2) * Y2; - T = Y * Y1; - Z = Z - X; - T = T - X; - X = X * Y2; - Y = (Y + U2) * Y1; - X = X - OneAndHalf; - Y = Y - OneAndHalf; - if ((X == Zero) && (Y == Zero) && (Z == Zero) && (T <= Zero)) { - X = (OneAndHalf + U2) * Y2; - Y = OneAndHalf - U2 - U2; - Z = OneAndHalf + U2 + U2; - T = (OneAndHalf - U2) * Y1; - X = X - (Z + U2); - StickyBit = Y * Y1; - S = Z * Y2; - T = T - Y; - Y = (U2 - Y) + StickyBit; - Z = S - (Z + U2 + U2); - StickyBit = (Y2 + U2) * Y1; - Y1 = Y2 * Y1; - StickyBit = StickyBit - Y2; - Y1 = Y1 - Half; - if ((X == Zero) && (Y == Zero) && (Z == Zero) && (T == Zero) - && (StickyBit == Zero) && (Y1 == Half)) { - RMult = Rounded; - printf ("Multiplication appears to round correctly.\n"); - } else if ((X + U2 == Zero) && (Y < Zero) && (Z + U2 == Zero) - && (T < Zero) && (StickyBit + U2 == Zero) - && (Y1 < Half)) { - RMult = Chopped; - printf ("Multiplication appears to chop.\n"); - } else - printf ("* is neither chopped nor correctly rounded.\n"); - if ((RMult == Rounded) && (GMult == No)) - notify ("Multiplication"); - } else - printf ("* is neither chopped nor correctly rounded.\n"); - /*=============================================*/ - Milestone = 45; - /*=============================================*/ - Y2 = One + U2; - Y1 = One - U2; - Z = OneAndHalf + U2 + U2; - X = Z / Y2; - T = OneAndHalf - U2 - U2; - Y = (T - U2) / Y1; - Z = (Z + U2) / Y2; - X = X - OneAndHalf; - Y = Y - T; - T = T / Y1; - Z = Z - (OneAndHalf + U2); - T = (U2 - OneAndHalf) + T; - if (!((X > Zero) || (Y > Zero) || (Z > Zero) || (T > Zero))) { - X = OneAndHalf / Y2; - Y = OneAndHalf - U2; - Z = OneAndHalf + U2; - X = X - Y; - T = OneAndHalf / Y1; - Y = Y / Y1; - T = T - (Z + U2); - Y = Y - Z; - Z = Z / Y2; - Y1 = (Y2 + U2) / Y2; - Z = Z - OneAndHalf; - Y2 = Y1 - Y2; - Y1 = (F9 - U1) / F9; - if ((X == Zero) && (Y == Zero) && (Z == Zero) && (T == Zero) - && (Y2 == Zero) && (Y2 == Zero) - && (Y1 - Half == F9 - Half)) { - RDiv = Rounded; - printf ("Division appears to round correctly.\n"); - if (GDiv == No) - notify ("Division"); - } else if ((X < Zero) && (Y < Zero) && (Z < Zero) && (T < Zero) - && (Y2 < Zero) && (Y1 - Half < F9 - Half)) { - RDiv = Chopped; - printf ("Division appears to chop.\n"); - } - } - if (RDiv == Other) - printf ("/ is neither chopped nor correctly rounded.\n"); - BInvrse = One / Radix; - TstCond (Failure, (BInvrse * Radix - Half == Half), - "Radix * ( 1 / Radix ) differs from 1"); - /*=============================================*/ - Milestone = 50; - /*=============================================*/ - TstCond (Failure, ((F9 + U1) - Half == Half) - && ((BMinusU2 + U2) - One == Radix - One), - "Incomplete carry-propagation in Addition"); - X = One - U1 * U1; - Y = One + U2 * (One - U2); - Z = F9 - Half; - X = (X - Half) - Z; - Y = Y - One; - if ((X == Zero) && (Y == Zero)) { - RAddSub = Chopped; - printf ("Add/Subtract appears to be chopped.\n"); - } - if (GAddSub == Yes) { - X = (Half + U2) * U2; - Y = (Half - U2) * U2; - X = One + X; - Y = One + Y; - X = (One + U2) - X; - Y = One - Y; - if ((X == Zero) && (Y == Zero)) { - X = (Half + U2) * U1; - Y = (Half - U2) * U1; - X = One - X; - Y = One - Y; - X = F9 - X; - Y = One - Y; - if ((X == Zero) && (Y == Zero)) { - RAddSub = Rounded; - printf ("Addition/Subtraction appears to round correctly.\n"); - if (GAddSub == No) - notify ("Add/Subtract"); - } else - printf ("Addition/Subtraction neither rounds nor chops.\n"); - } else - printf ("Addition/Subtraction neither rounds nor chops.\n"); - } else - printf ("Addition/Subtraction neither rounds nor chops.\n"); - S = One; - X = One + Half * (One + Half); - Y = (One + U2) * Half; - Z = X - Y; - T = Y - X; - StickyBit = Z + T; - if (StickyBit != Zero) { - S = Zero; - BadCond (Flaw, "(X - Y) + (Y - X) is non zero!\n"); - } - StickyBit = Zero; - if ((GMult == Yes) && (GDiv == Yes) && (GAddSub == Yes) - && (RMult == Rounded) && (RDiv == Rounded) - && (RAddSub == Rounded) && (FLOOR (RadixD2) == RadixD2)) { - printf ("Checking for sticky bit.\n"); - X = (Half + U1) * U2; - Y = Half * U2; - Z = One + Y; - T = One + X; - if ((Z - One <= Zero) && (T - One >= U2)) { - Z = T + Y; - Y = Z - X; - if ((Z - T >= U2) && (Y - T == Zero)) { - X = (Half + U1) * U1; - Y = Half * U1; - Z = One - Y; - T = One - X; - if ((Z - One == Zero) && (T - F9 == Zero)) { - Z = (Half - U1) * U1; - T = F9 - Z; - Q = F9 - Y; - if ((T - F9 == Zero) && (F9 - U1 - Q == Zero)) { - Z = (One + U2) * OneAndHalf; - T = (OneAndHalf + U2) - Z + U2; - X = One + Half / Radix; - Y = One + Radix * U2; - Z = X * Y; - if (T == Zero && X + Radix * U2 - Z == Zero) { - if (Radix != Two) { - X = Two + U2; - Y = X / Two; - if ((Y - One == Zero)) - StickyBit = S; - } else - StickyBit = S; - } - } - } - } - } - } - if (StickyBit == One) - printf ("Sticky bit apparently used correctly.\n"); - else - printf ("Sticky bit used incorrectly or not at all.\n"); - TstCond (Flaw, !(GMult == No || GDiv == No || GAddSub == No || - RMult == Other || RDiv == Other || RAddSub == Other), - "lack(s) of guard digits or failure(s) to correctly round or chop\n\ -(noted above) count as one flaw in the final tally below"); - /*=============================================*/ - Milestone = 60; - /*=============================================*/ - printf ("\n"); - printf ("Does Multiplication commute? "); - printf ("Testing on %d random pairs.\n", NoTrials); - Random9 = SQRT (3.0); - Random1 = Third; - I = 1; - do { - X = Random (); - Y = Random (); - Z9 = Y * X; - Z = X * Y; - Z9 = Z - Z9; - I = I + 1; - } - while (!((I > NoTrials) || (Z9 != Zero))); - if (I == NoTrials) { - Random1 = One + Half / Three; - Random2 = (U2 + U1) + One; - Z = Random1 * Random2; - Y = Random2 * Random1; - Z9 = (One + Half / Three) * ((U2 + U1) + One) - (One + Half / - Three) * ((U2 + U1) + One); - } - if (!((I == NoTrials) || (Z9 == Zero))) - BadCond (Defect, "X * Y == Y * X trial fails.\n"); - else - printf (" No failures found in %d integer pairs.\n", NoTrials); - /*=============================================*/ - Milestone = 70; - /*=============================================*/ - printf ("\nRunning test of square root(x).\n"); - TstCond (Failure, (Zero == SQRT (Zero)) - && (-Zero == SQRT (-Zero)) - && (One == SQRT (One)), "Square root of 0.0, -0.0 or 1.0 wrong"); - MinSqEr = Zero; - MaxSqEr = Zero; - J = Zero; - X = Radix; - OneUlp = U2; - SqXMinX (Serious); - X = BInvrse; - OneUlp = BInvrse * U1; - SqXMinX (Serious); - X = U1; - OneUlp = U1 * U1; - SqXMinX (Serious); - if (J != Zero) - Pause (); - printf ("Testing if sqrt(X * X) == X for %d Integers X.\n", NoTrials); - J = Zero; - X = Two; - Y = Radix; - if ((Radix != One)) - do { - X = Y; - Y = Radix * Y; - } - while (!((Y - X >= NoTrials))); - OneUlp = X * U2; - I = 1; - while (I <= NoTrials) { - X = X + One; - SqXMinX (Defect); - if (J > Zero) - break; - I = I + 1; - } - printf ("Test for sqrt monotonicity.\n"); - I = -1; - X = BMinusU2; - Y = Radix; - Z = Radix + Radix * U2; - NotMonot = False; - Monot = False; - while (!(NotMonot || Monot)) { - I = I + 1; - X = SQRT (X); - Q = SQRT (Y); - Z = SQRT (Z); - if ((X > Q) || (Q > Z)) - NotMonot = True; - else { - Q = FLOOR (Q + Half); - if ((I > 0) || (Radix == Q * Q)) - Monot = True; - else if (I > 0) { - if (I > 1) - Monot = True; - else { - Y = Y * BInvrse; - X = Y - U1; - Z = Y + U1; - } - } else { - Y = Q; - X = Y - U2; - Z = Y + U2; - } - } - } - if (Monot) - printf ("sqrt has passed a test for Monotonicity.\n"); - else { - BadCond (Defect, ""); - printf ("sqrt(X) is non-monotonic for X near %.7e .\n", Y); - } - /*=============================================*/ - Milestone = 80; - /*=============================================*/ - MinSqEr = MinSqEr + Half; - MaxSqEr = MaxSqEr - Half; - Y = (SQRT (One + U2) - One) / U2; - SqEr = (Y - One) + U2 / Eight; - if (SqEr > MaxSqEr) - MaxSqEr = SqEr; - SqEr = Y + U2 / Eight; - if (SqEr < MinSqEr) - MinSqEr = SqEr; - Y = ((SQRT (F9) - U2) - (One - U2)) / U1; - SqEr = Y + U1 / Eight; - if (SqEr > MaxSqEr) - MaxSqEr = SqEr; - SqEr = (Y + One) + U1 / Eight; - if (SqEr < MinSqEr) - MinSqEr = SqEr; - OneUlp = U2; - X = OneUlp; - for (Indx = 1; Indx <= 3; ++Indx) { - Y = SQRT ((X + U1 + X) + F9); - Y = ((Y - U2) - ((One - U2) + X)) / OneUlp; - Z = ((U1 - X) + F9) * Half * X * X / OneUlp; - SqEr = (Y + Half) + Z; - if (SqEr < MinSqEr) - MinSqEr = SqEr; - SqEr = (Y - Half) + Z; - if (SqEr > MaxSqEr) - MaxSqEr = SqEr; - if (((Indx == 1) || (Indx == 3))) - X = OneUlp * Sign (X) * FLOOR (Eight / (Nine * SQRT (OneUlp))); - else { - OneUlp = U1; - X = -OneUlp; - } - } - /*=============================================*/ - Milestone = 85; - /*=============================================*/ - SqRWrng = False; - Anomaly = False; - RSqrt = Other; /* ~dgh */ - if (Radix != One) { - printf ("Testing whether sqrt is rounded or chopped.\n"); - D = FLOOR (Half + POW (Radix, One + Precision - FLOOR (Precision))); - /* ... == Radix^(1 + fract) if (Precision == Integer + fract. */ - X = D / Radix; - Y = D / A1; - if ((X != FLOOR (X)) || (Y != FLOOR (Y))) { - Anomaly = True; - } else { - X = Zero; - Z2 = X; - Y = One; - Y2 = Y; - Z1 = Radix - One; - FourD = Four * D; - do { - if (Y2 > Z2) { - Q = Radix; - Y1 = Y; - do { - X1 = FABS (Q + FLOOR (Half - Q / Y1) * Y1); - Q = Y1; - Y1 = X1; - } - while (!(X1 <= Zero)); - if (Q <= One) { - Z2 = Y2; - Z = Y; - } - } - Y = Y + Two; - X = X + Eight; - Y2 = Y2 + X; - if (Y2 >= FourD) - Y2 = Y2 - FourD; - } - while (!(Y >= D)); - X8 = FourD - Z2; - Q = (X8 + Z * Z) / FourD; - X8 = X8 / Eight; - if (Q != FLOOR (Q)) - Anomaly = True; - else { - Break = False; - do { - X = Z1 * Z; - X = X - FLOOR (X / Radix) * Radix; - if (X == One) - Break = True; - else - Z1 = Z1 - One; - } - while (!(Break || (Z1 <= Zero))); - if ((Z1 <= Zero) && (!Break)) - Anomaly = True; - else { - if (Z1 > RadixD2) - Z1 = Z1 - Radix; - do { - NewD (); - } - while (!(U2 * D >= F9)); - if (D * Radix - D != W - D) - Anomaly = True; - else { - Z2 = D; - I = 0; - Y = D + (One + Z) * Half; - X = D + Z + Q; - SR3750 (); - Y = D + (One - Z) * Half + D; - X = D - Z + D; - X = X + Q + X; - SR3750 (); - NewD (); - if (D - Z2 != W - Z2) - Anomaly = True; - else { - Y = (D - Z2) + (Z2 + (One - Z) * Half); - X = (D - Z2) + (Z2 - Z + Q); - SR3750 (); - Y = (One + Z) * Half; - X = Q; - SR3750 (); - if (I == 0) - Anomaly = True; - } - } - } - } - } - if ((I == 0) || Anomaly) { - BadCond (Failure, "Anomalous arithmetic with Integer < "); - printf ("Radix^Precision = %.7e\n", W); - printf (" fails test whether sqrt rounds or chops.\n"); - SqRWrng = True; - } - } - if (!Anomaly) { - if (!((MinSqEr < Zero) || (MaxSqEr > Zero))) { - RSqrt = Rounded; - printf ("Square root appears to be correctly rounded.\n"); - } else { - if ((MaxSqEr + U2 > U2 - Half) || (MinSqEr > Half) - || (MinSqEr + Radix < Half)) - SqRWrng = True; - else { - RSqrt = Chopped; - printf ("Square root appears to be chopped.\n"); - } - } - } - if (SqRWrng) { - printf ("Square root is neither chopped nor correctly rounded.\n"); - printf ("Observed errors run from %.7e ", MinSqEr - Half); - printf ("to %.7e ulps.\n", Half + MaxSqEr); - TstCond (Serious, MaxSqEr - MinSqEr < Radix * Radix, - "sqrt gets too many last digits wrong"); - } - /*=============================================*/ - Milestone = 90; - /*=============================================*/ - Pause (); - printf ("Testing powers Z^i for small Integers Z and i.\n"); - N = 0; - /* ... test powers of zero. */ - I = 0; - Z = -Zero; - M = 3; - Break = False; - do { - X = One; - SR3980 (); - if (I <= 10) { - I = 1023; - SR3980 (); - } - if (Z == MinusOne) - Break = True; - else { - Z = MinusOne; - /* .. if(-1)^N is invalid, replace MinusOne by One. */ - I = -4; - } - } - while (!Break); - PrintIfNPositive (); - N1 = N; - N = 0; - Z = A1; - M = (int) FLOOR (Two * LOG (W) / LOG (A1)); - Break = False; - do { - X = Z; - I = 1; - SR3980 (); - if (Z == AInvrse) - Break = True; - else - Z = AInvrse; - } - while (!(Break)); - /*=============================================*/ - Milestone = 100; - /*=============================================*/ - /* Powers of Radix have been tested, */ - /* next try a few primes */ - M = NoTrials; - Z = Three; - do { - X = Z; - I = 1; - SR3980 (); - do { - Z = Z + Two; - } - while (Three * FLOOR (Z / Three) == Z); - } - while (Z < Eight * Three); - if (N > 0) { - printf ("Errors like this may invalidate financial calculations\n"); - printf ("\tinvolving interest rates.\n"); - } - PrintIfNPositive (); - N += N1; - if (N == 0) - printf ("... no discrepancies found.\n"); - if (N > 0) - Pause (); - else - printf ("\n"); - /*=============================================*/ - Milestone = 110; - /*=============================================*/ - printf ("Seeking Underflow thresholds UfThold and E0.\n"); - D = U1; - if (Precision != FLOOR (Precision)) { - D = BInvrse; - X = Precision; - do { - D = D * BInvrse; - X = X - One; - } - while (X > Zero); - } - Y = One; - Z = D; - /* ... D is power of 1/Radix < 1. */ - do { - C = Y; - Y = Z; - Z = Y * Y; - } - while ((Y > Z) && (Z + Z > Z)); - Y = C; - Z = Y * D; - do { - C = Y; - Y = Z; - Z = Y * D; - } - while ((Y > Z) && (Z + Z > Z)); - if (Radix < Two) - HInvrse = Two; - else - HInvrse = Radix; - H = One / HInvrse; - /* ... 1/HInvrse == H == Min(1/Radix, 1/2) */ - CInvrse = One / C; - E0 = C; - Z = E0 * H; - /* ...1/Radix^(BIG Integer) << 1 << CInvrse == 1/C */ - do { - Y = E0; - E0 = Z; - Z = E0 * H; - } - while ((E0 > Z) && (Z + Z > Z)); - UfThold = E0; - E1 = Zero; - Q = Zero; - E9 = U2; - S = One + E9; - D = C * S; - if (D <= C) { - E9 = Radix * U2; - S = One + E9; - D = C * S; - if (D <= C) { - BadCond (Failure, "multiplication gets too many last digits wrong.\n"); - Underflow = E0; - Y1 = Zero; - PseudoZero = Z; - Pause (); - } - } else { - Underflow = D; - PseudoZero = Underflow * H; - UfThold = Zero; - do { - Y1 = Underflow; - Underflow = PseudoZero; - if (E1 + E1 <= E1) { - Y2 = Underflow * HInvrse; - E1 = FABS (Y1 - Y2); - Q = Y1; - if ((UfThold == Zero) && (Y1 != Y2)) - UfThold = Y1; - } - PseudoZero = PseudoZero * H; - } - while ((Underflow > PseudoZero) - && (PseudoZero + PseudoZero > PseudoZero)); - } - /* Comment line 4530 .. 4560 */ - if (PseudoZero != Zero) { - printf ("\n"); - Z = PseudoZero; - /* ... Test PseudoZero for "phoney- zero" violates */ - /* ... PseudoZero < Underflow or PseudoZero < PseudoZero + PseudoZero - ... */ - if (PseudoZero <= Zero) { - BadCond (Failure, "Positive expressions can underflow to an\n"); - printf ("allegedly negative value\n"); - printf ("PseudoZero that prints out as: %g .\n", PseudoZero); - X = -PseudoZero; - if (X <= Zero) { - printf ("But -PseudoZero, which should be\n"); - printf ("positive, isn't; it prints out as %g .\n", X); - } - } else { - BadCond (Flaw, "Underflow can stick at an allegedly positive\n"); - printf ("value PseudoZero that prints out as %g .\n", PseudoZero); - } - TstPtUf (); - } - /*=============================================*/ - Milestone = 120; - /*=============================================*/ - if (CInvrse * Y > CInvrse * Y1) { - S = H * S; - E0 = Underflow; - } - if (!((E1 == Zero) || (E1 == E0))) { - BadCond (Defect, ""); - if (E1 < E0) { - printf ("Products underflow at a higher"); - printf (" threshold than differences.\n"); - if (PseudoZero == Zero) - E0 = E1; - } else { - printf ("Difference underflows at a higher"); - printf (" threshold than products.\n"); - } - } - printf ("Smallest strictly positive number found is E0 = %g .\n", E0); - Z = E0; - TstPtUf (); - Underflow = E0; - if (N == 1) - Underflow = Y; - I = 4; - if (E1 == Zero) - I = 3; - if (UfThold == Zero) - I = I - 2; - UfNGrad = True; - switch (I) { - case 1: - UfThold = Underflow; - if ((CInvrse * Q) != ((CInvrse * Y) * S)) { - UfThold = Y; - BadCond (Failure, "Either accuracy deteriorates as numbers\n"); - printf ("approach a threshold = %.17e\n", UfThold);; - printf (" coming down from %.17e\n", C); - printf (" or else multiplication gets too many last digits wrong.\n"); - } - Pause (); - break; - - case 2: - BadCond (Failure, "Underflow confuses Comparison, which alleges that\n"); - printf ("Q == Y while denying that |Q - Y| == 0; these values\n"); - printf ("print out as Q = %.17e, Y = %.17e .\n", Q, Y2); - printf ("|Q - Y| = %.17e .\n", FABS (Q - Y2)); - UfThold = Q; - break; - - case 3: - X = X; - break; - - case 4: - if ((Q == UfThold) && (E1 == E0) - && (FABS (UfThold - E1 / E9) <= E1)) { - UfNGrad = False; - printf ("Underflow is gradual; it incurs Absolute Error =\n"); - printf ("(roundoff in UfThold) < E0.\n"); - Y = E0 * CInvrse; - Y = Y * (OneAndHalf + U2); - X = CInvrse * (One + U2); - Y = Y / X; - IEEE = (Y == E0); - } - } - if (UfNGrad) { - printf ("\n"); - sigsave = _sigfpe; - if (setjmp (ovfl_buf)) { - printf ("Underflow / UfThold failed!\n"); - R = H + H; - } else - R = SQRT (Underflow / UfThold); - sigsave = 0; - if (R <= H) { - Z = R * UfThold; - X = Z * (One + R * H * (One + H)); - } else { - Z = UfThold; - X = Z * (One + H * H * (One + H)); - } - if (!((X == Z) || (X - Z != Zero))) { - BadCond (Flaw, ""); - printf ("X = %.17e\n\tis not equal to Z = %.17e .\n", X, Z); - Z9 = X - Z; - printf ("yet X - Z yields %.17e .\n", Z9); - printf (" Should this NOT signal Underflow, "); - printf ("this is a SERIOUS DEFECT\nthat causes "); - printf ("confusion when innocent statements like\n");; - printf (" if (X == Z) ... else"); - printf (" ... (f(X) - f(Z)) / (X - Z) ...\n"); - printf ("encounter Division by Zero although actually\n"); - sigsave = _sigfpe; - if (setjmp (ovfl_buf)) - printf ("X / Z fails!\n"); - else - printf ("X / Z = 1 + %g .\n", (X / Z - Half) - Half); - sigsave = 0; - } - } - printf ("The Underflow threshold is %.17e, %s\n", UfThold, - " below which"); - printf ("calculation may suffer larger Relative error than "); - printf ("merely roundoff.\n"); - Y2 = U1 * U1; - Y = Y2 * Y2; - Y2 = Y * U1; - if (Y2 <= UfThold) { - if (Y > E0) { - BadCond (Defect, ""); - I = 5; - } else { - BadCond (Serious, ""); - I = 4; - } - printf ("Range is too narrow; U1^%d Underflows.\n", I); - } - /*=============================================*/ - Milestone = 130; - /*=============================================*/ - Y = -FLOOR (Half - TwoForty * LOG (UfThold) / LOG (HInvrse)) / TwoForty; - Y2 = Y + Y; - printf ("Since underflow occurs below the threshold\n"); - printf ("UfThold = (%.17e) ^ (%.17e)\nonly underflow ", HInvrse, Y); - printf ("should afflict the expression\n\t(%.17e) ^ (%.17e);\n", - HInvrse, Y2); - printf ("actually calculating yields:"); - if (setjmp (ovfl_buf)) { - sigsave = 0; - BadCond (Serious, "trap on underflow.\n"); - } else { - sigsave = _sigfpe; - V9 = POW (HInvrse, Y2); - sigsave = 0; - printf (" %.17e .\n", V9); - if (!((V9 >= Zero) && (V9 <= (Radix + Radix + E9) * UfThold))) { - BadCond (Serious, "this is not between 0 and underflow\n"); - printf (" threshold = %.17e .\n", UfThold); - } else if (!(V9 > UfThold * (One + E9))) - printf ("This computed value is O.K.\n"); - else { - BadCond (Defect, "this is not between 0 and underflow\n"); - printf (" threshold = %.17e .\n", UfThold); - } - } - /*=============================================*/ - Milestone = 140; - /*=============================================*/ - printf ("\n"); - /* ...calculate Exp2 == exp(2) == 7.389056099... */ - X = Zero; - I = 2; - Y = Two * Three; - Q = Zero; - N = 0; - do { - Z = X; - I = I + 1; - Y = Y / (I + I); - R = Y + Q; - X = Z + R; - Q = (Z - X) + R; - } - while (X > Z); - Z = (OneAndHalf + One / Eight) + X / (OneAndHalf * ThirtyTwo); - X = Z * Z; - Exp2 = X * X; - X = F9; - Y = X - U1; - printf ("Testing X^((X + 1) / (X - 1)) vs. exp(2) = %.17e as X -> 1.\n", - Exp2); - for (I = 1;;) { - Z = X - BInvrse; - Z = (X + One) / (Z - (One - BInvrse)); - Q = POW (X, Z) - Exp2; - if (FABS (Q) > TwoForty * U2) { - N = 1; - V9 = (X - BInvrse) - (One - BInvrse); - BadCond (Defect, "Calculated"); - printf (" %.17e for\n", POW (X, Z)); - printf ("\t(1 + (%.17e) ^ (%.17e);\n", V9, Z); - printf ("\tdiffers from correct value by %.17e .\n", Q); - printf ("\tThis much error may spoil financial\n"); - printf ("\tcalculations involving tiny interest rates.\n"); - break; - } else { - Z = (Y - X) * Two + Y; - X = Y; - Y = Z; - Z = One + (X - F9) * (X - F9); - if (Z > One && I < NoTrials) - I++; - else { - if (X > One) { - if (N == 0) - printf ("Accuracy seems adequate.\n"); - break; - } else { - X = One + U2; - Y = U2 + U2; - Y += X; - I = 1; - } - } - } - } - /*=============================================*/ - Milestone = 150; - /*=============================================*/ - printf ("Testing powers Z^Q at four nearly extreme values.\n"); - N = 0; - Z = A1; - Q = FLOOR (Half - LOG (C) / LOG (A1)); - Break = False; - do { - X = CInvrse; - Y = POW (Z, Q); - IsYeqX (); - Q = -Q; - X = C; - Y = POW (Z, Q); - IsYeqX (); - if (Z < One) - Break = True; - else - Z = AInvrse; - } - while (!(Break)); - PrintIfNPositive (); - if (N == 0) - printf (" ... no discrepancies found.\n"); - printf ("\n"); - - /*=============================================*/ - Milestone = 160; - /*=============================================*/ - Pause (); - printf ("Searching for Overflow threshold:\n"); - printf ("This may generate an error.\n"); - Y = -CInvrse; - V9 = HInvrse * Y; - sigsave = _sigfpe; - if (setjmp (ovfl_buf)) { - I = 0; - V9 = Y; - goto overflow; - } - do { - V = Y; - Y = V9; - V9 = HInvrse * Y; - } - while (V9 < Y); - I = 1; - overflow: - sigsave = 0; - Z = V9; - printf ("Can `Z = -Y' overflow?\n"); - printf ("Trying it on Y = %.17e .\n", Y); - V9 = -Y; - V0 = V9; - if (V - Y == V + V0) - printf ("Seems O.K.\n"); - else { - printf ("finds a "); - BadCond (Flaw, "-(-Y) differs from Y.\n"); - } - if (Z != Y) { - BadCond (Serious, ""); - printf ("overflow past %.17e\n\tshrinks to %.17e .\n", Y, Z); - } - if (I) { - Y = V * (HInvrse * U2 - HInvrse); - Z = Y + ((One - HInvrse) * U2) * V; - if (Z < V0) - Y = Z; - if (Y < V0) - V = Y; - if (V0 - V < V0) - V = V0; - } else { - V = Y * (HInvrse * U2 - HInvrse); - V = V + ((One - HInvrse) * U2) * Y; - } - printf ("Overflow threshold is V = %.17e .\n", V); - if (I) - printf ("Overflow saturates at V0 = %.17e .\n", V0); - else - printf ("There is no saturation value because \ -the system traps on overflow.\n"); - V9 = V * One; - printf ("No Overflow should be signaled for V * 1 = %.17e\n", V9); - V9 = V / One; - printf (" nor for V / 1 = %.17e .\n", V9); - printf ("Any overflow signal separating this * from the one\n"); - printf ("above is a DEFECT.\n"); - /*=============================================*/ - Milestone = 170; - /*=============================================*/ - if (!(-V < V && -V0 < V0 && -UfThold < V && UfThold < V)) { - BadCond (Failure, "Comparisons involving "); - printf ("+-%g, +-%g\nand +-%g are confused by Overflow.", - V, V0, UfThold); - } - /*=============================================*/ - Milestone = 175; - /*=============================================*/ - printf ("\n"); - for (Indx = 1; Indx <= 3; ++Indx) { - switch (Indx) { - case 1: - Z = UfThold; - break; - case 2: - Z = E0; - break; - case 3: - Z = PseudoZero; - break; - } - if (Z != Zero) { - V9 = SQRT (Z); - Y = V9 * V9; - if (Y / (One - Radix * E9) < Z - || Y > (One + Radix * E9) * Z) { /* dgh: + E9 --> * E9 */ - if (V9 > U1) - BadCond (Serious, ""); - else - BadCond (Defect, ""); - printf ("Comparison alleges that what prints as Z = %.17e\n", Z); - printf (" is too far from sqrt(Z) ^ 2 = %.17e .\n", Y); - } - } - } - /*=============================================*/ - Milestone = 180; - /*=============================================*/ - for (Indx = 1; Indx <= 2; ++Indx) { - if (Indx == 1) - Z = V; - else - Z = V0; - V9 = SQRT (Z); - X = (One - Radix * E9) * V9; - V9 = V9 * X; - if (((V9 < (One - Two * Radix * E9) * Z) || (V9 > Z))) { - Y = V9; - if (X < W) - BadCond (Serious, ""); - else - BadCond (Defect, ""); - printf ("Comparison alleges that Z = %17e\n", Z); - printf (" is too far from sqrt(Z) ^ 2 (%.17e) .\n", Y); - } - } - /*=============================================*/ - Milestone = 190; - /*=============================================*/ - Pause (); - X = UfThold * V; - Y = Radix * Radix; - if (X * Y < One || X > Y) { - if (X * Y < U1 || X > Y / U1) - BadCond (Defect, "Badly"); - else - BadCond (Flaw, ""); - - printf (" unbalanced range; UfThold * V = %.17e\n\t%s\n", - X, "is too far from 1.\n"); - } - /*=============================================*/ - Milestone = 200; - /*=============================================*/ - for (Indx = 1; Indx <= 5; ++Indx) { - X = F9; - switch (Indx) { - case 2: - X = One + U2; - break; - case 3: - X = V; - break; - case 4: - X = UfThold; - break; - case 5: - X = Radix; - } - Y = X; - sigsave = _sigfpe; - if (setjmp (ovfl_buf)) - printf (" X / X traps when X = %g\n", X); - else { - V9 = (Y / X - Half) - Half; - if (V9 == Zero) - continue; - if (V9 == -U1 && Indx < 5) - BadCond (Flaw, ""); - else - BadCond (Serious, ""); - printf (" X / X differs from 1 when X = %.17e\n", X); - printf (" instead, X / X - 1/2 - 1/2 = %.17e .\n", V9); - } - sigsave = 0; - } - /*=============================================*/ - Milestone = 210; - /*=============================================*/ - MyZero = Zero; - printf ("\n"); - printf ("What message and/or values does Division by Zero produce?\n"); -#ifndef BATCHMODE - printf ("This can interupt your program. You can "); - printf ("skip this part if you wish.\n"); - printf ("Do you wish to compute 1 / 0? "); - fflush (stdout); - read (KEYBOARD, ch, 8); - if ((ch[0] == 'Y') || (ch[0] == 'y')) { -#endif /* !BATCHMODE */ - sigsave = _sigfpe; - printf (" Trying to compute 1 / 0 produces ..."); - if (!setjmp (ovfl_buf)) - printf (" %.7e .\n", One / MyZero); - sigsave = 0; -#ifndef BATCHMODE - } else - printf ("O.K.\n"); - printf ("\nDo you wish to compute 0 / 0? "); - fflush (stdout); - read (KEYBOARD, ch, 80); - if ((ch[0] == 'Y') || (ch[0] == 'y')) { -#endif /* !BATCHMODE */ - sigsave = _sigfpe; - printf ("\n Trying to compute 0 / 0 produces ..."); - if (!setjmp (ovfl_buf)) - printf (" %.7e .\n", Zero / MyZero); - sigsave = 0; -#ifndef BATCHMODE - } else - printf ("O.K.\n"); -#endif /* !BATCHMODE */ - /*=============================================*/ - Milestone = 220; - /*=============================================*/ - - Pause (); - printf ("\n"); - { - static char *msg[] = - { - "FAILUREs encountered =", - "SERIOUS DEFECTs discovered =", - "DEFECTs discovered =", - "FLAWs discovered ="}; - int i; - for (i = 0; i < 4; i++) - if (ErrCnt[i]) - printf ("The number of %-29s %d.\n", - msg[i], ErrCnt[i]); - } - - printf ("\n"); - if ((ErrCnt[Failure] + ErrCnt[Serious] + ErrCnt[Defect] - + ErrCnt[Flaw]) > 0) { - if ((ErrCnt[Failure] + ErrCnt[Serious] + ErrCnt[ - Defect] == 0) && (ErrCnt[Flaw] > 0)) { - printf ("The arithmetic diagnosed seems "); - printf ("Satisfactory though flawed.\n"); - } - if ((ErrCnt[Failure] + ErrCnt[Serious] == 0) - && (ErrCnt[Defect] > 0)) { - printf ("The arithmetic diagnosed may be Acceptable\n"); - printf ("despite inconvenient Defects.\n"); - } - if ((ErrCnt[Failure] + ErrCnt[Serious]) > 0) { - printf ("The arithmetic diagnosed has "); - printf ("unacceptable Serious Defects.\n"); - } - if (ErrCnt[Failure] > 0) { - printf ("Potentially fatal FAILURE may have spoiled this"); - printf (" program's subsequent diagnoses.\n"); - } - } else { - - printf ("No failures, defects nor flaws have been discovered.\n"); - if (!((RMult == Rounded) && (RDiv == Rounded) - && (RAddSub == Rounded) && (RSqrt == Rounded))) - printf ("The arithmetic diagnosed seems Satisfactory.\n"); - else { - if (StickyBit >= One && - (Radix - Two) * (Radix - Nine - One) == Zero) { - printf ("Rounding appears to conform to "); - printf ("the proposed IEEE standard P"); - if ((Radix == Two) && - ((Precision - Four * Three * Two) * - (Precision - TwentySeven - - TwentySeven + One) == Zero)) - printf ("754"); - else - printf ("854"); - if (IEEE) - printf (".\n"); - else { - printf (",\nexcept for possibly Double Rounding"); - printf (" during Gradual Underflow.\n"); - } - } - printf ("The arithmetic diagnosed appears to be Excellent!\n"); - } - } - - if (fpecount) - printf ("\nA total of %d floating point exceptions were registered.\n", - fpecount); - printf ("END OF TEST.\n"); - return 0; -} - -FLOAT -Sign (X) - FLOAT X; -{ - return X >= 0. ? 1.0 : -1.0; -} - -void -Pause () -{ -#ifndef BATCHMODE - char ch[8]; - - printf ("\nTo continue, press RETURN"); - fflush (stdout); - read (KEYBOARD, ch, 8); -#endif /* !BATCHMODE */ -#ifndef CYGNUS - printf ("\nDiagnosis resumes after milestone Number %d", Milestone); - printf (" Page: %d\n\n", PageNo); - ++Milestone; - ++PageNo; -#endif /* !CYGNUS */ -} - -void -TstCond (K, Valid, T) - int K, Valid; - char *T; -{ -#ifdef CYGNUS - printf ("TEST: %s\n", T); -#endif /* CYGNUS */ - if (!Valid) { - BadCond (K, T); - printf (".\n"); - } -#ifdef CYGNUS - printf ("PASS: %s\n", T); -#endif /* CYGNUS */ -} - -void -BadCond (K, T) - int K; - char *T; -{ - static char *msg[] = - {"FAILURE", "SERIOUS DEFECT", "DEFECT", "FLAW"}; - - ErrCnt[K] = ErrCnt[K] + 1; -#ifndef CYGNUS - printf ("%s: %s", msg[K], T); -#else - printf ("ERROR: Severity: %s: %s", msg[K], T); -#endif /* CYGNUS */ -} - -/* - * Random computes - * X = (Random1 + Random9)^5 - * Random1 = X - FLOOR(X) + 0.000005 * X; - * and returns the new value of Random1 -*/ -FLOAT -Random () -{ - FLOAT X, Y; - - X = Random1 + Random9; - Y = X * X; - Y = Y * Y; - X = X * Y; - Y = X - FLOOR (X); - Random1 = Y + X * 0.000005; - return (Random1); -} - -void -SqXMinX (ErrKind) - int ErrKind; -{ - FLOAT XA, XB; - - XB = X * BInvrse; - XA = X - XB; - SqEr = ((SQRT (X * X) - XB) - XA) / OneUlp; - if (SqEr != Zero) { - if (SqEr < MinSqEr) - MinSqEr = SqEr; - if (SqEr > MaxSqEr) - MaxSqEr = SqEr; - J = J + 1.0; - BadCond (ErrKind, "\n"); - printf ("sqrt( %.17e) - %.17e = %.17e\n", X * X, X, OneUlp * SqEr); - printf ("\tinstead of correct value 0 .\n"); - } -} - -void -NewD () -{ - X = Z1 * Q; - X = FLOOR (Half - X / Radix) * Radix + X; - Q = (Q - X * Z) / Radix + X * X * (D / Radix); - Z = Z - Two * X * D; - if (Z <= Zero) { - Z = -Z; - Z1 = -Z1; - } - D = Radix * D; -} - -void -SR3750 () -{ - if (!((X - Radix < Z2 - Radix) || (X - Z2 > W - Z2))) { - I = I + 1; - X2 = SQRT (X * D); - Y2 = (X2 - Z2) - (Y - Z2); - X2 = X8 / (Y - Half); - X2 = X2 - Half * X2 * X2; - SqEr = (Y2 + Half) + (Half - X2); - if (SqEr < MinSqEr) - MinSqEr = SqEr; - SqEr = Y2 - X2; - if (SqEr > MaxSqEr) - MaxSqEr = SqEr; - } -} - -void -IsYeqX () -{ - if (Y != X) { - if (N <= 0) { - if (Z == Zero && Q <= Zero) - printf ("WARNING: computing\n"); - else - BadCond (Defect, "computing\n"); - printf ("\t(%.17e) ^ (%.17e)\n", Z, Q); - printf ("\tyielded %.17e;\n", Y); - printf ("\twhich compared unequal to correct %.17e ;\n", - X); - printf ("\t\tthey differ by %.17e .\n", Y - X); - } - N = N + 1; /* ... count discrepancies. */ - } -} - -void -SR3980 () -{ - do { - Q = (FLOAT) I; - Y = POW (Z, Q); - IsYeqX (); - if (++I > M) - break; - X = Z * X; - } - while (X < W); -} - -void -PrintIfNPositive () -{ - if (N > 0) - printf ("Similar discrepancies have occurred %d times.\n", N); -} - -void -TstPtUf () -{ - N = 0; - if (Z != Zero) { - printf ("Since comparison denies Z = 0, evaluating "); - printf ("(Z + Z) / Z should be safe.\n"); - sigsave = _sigfpe; - if (setjmp (ovfl_buf)) - goto very_serious; - Q9 = (Z + Z) / Z; - printf ("What the machine gets for (Z + Z) / Z is %.17e .\n", - Q9); - if (FABS (Q9 - Two) < Radix * U2) { - printf ("This is O.K., provided Over/Underflow"); - printf (" has NOT just been signaled.\n"); - } else { - if ((Q9 < One) || (Q9 > Two)) { - very_serious: - N = 1; - ErrCnt[Serious] = ErrCnt[Serious] + 1; - printf ("This is a VERY SERIOUS DEFECT!\n"); - } else { - N = 1; - ErrCnt[Defect] = ErrCnt[Defect] + 1; - printf ("This is a DEFECT!\n"); - } - } - sigsave = 0; - V9 = Z * One; - Random1 = V9; - V9 = One * Z; - Random2 = V9; - V9 = Z / One; - if ((Z == Random1) && (Z == Random2) && (Z == V9)) { - if (N > 0) - Pause (); - } else { - N = 1; - BadCond (Defect, "What prints as Z = "); - printf ("%.17e\n\tcompares different from ", Z); - if (Z != Random1) - printf ("Z * 1 = %.17e ", Random1); - if (!((Z == Random2) - || (Random2 == Random1))) - printf ("1 * Z == %g\n", Random2); - if (!(Z == V9)) - printf ("Z / 1 = %.17e\n", V9); - if (Random2 != Random1) { - ErrCnt[Defect] = ErrCnt[Defect] + 1; - BadCond (Defect, "Multiplication does not commute!\n"); - printf ("\tComparison alleges that 1 * Z = %.17e\n", - Random2); - printf ("\tdiffers from Z * 1 = %.17e\n", Random1); - } - Pause (); - } - } -} - -void -notify (s) - char *s; -{ - printf ("%s test appears to be inconsistent...\n", s); - printf (" PLEASE NOTIFY KARPINKSI!\n"); -} - -void -msglist (s) - char **s; -{ - while (*s) - printf ("%s\n", *s++); -} - -void -Instructions () -{ - static char *instr[] = - { - "Lest this program stop prematurely, i.e. before displaying\n", - " `END OF TEST',\n", - "try to persuade the computer NOT to terminate execution when an", - "error like Over/Underflow or Division by Zero occurs, but rather", - "to persevere with a surrogate value after, perhaps, displaying some", - "warning. If persuasion avails naught, don't despair but run this", - "program anyway to see how many milestones it passes, and then", - "amend it to make further progress.\n", - "Answer questions with Y, y, N or n (unless otherwise indicated).\n", - 0}; - - msglist (instr); -} - -void -Heading () -{ - static char *head[] = - { - "Users are invited to help debug and augment this program so it will", - "cope with unanticipated and newly uncovered arithmetic pathologies.\n", - "Please send suggestions and interesting results to", - "\tRichard Karpinski", - "\tComputer Center U-76", - "\tUniversity of California", - "\tSan Francisco, CA 94143-0704, USA\n", - "In doing so, please include the following information:", -#ifdef SINGLE_PRECISION - "\tPrecision:\tsingle;", -#else /* !SINGLE_PRECISION */ - "\tPrecision:\tdouble;", -#endif /* SINGLE_PRECISION */ - "\tVersion:\t10 February 1989;", - "\tComputer:\n", - "\tCompiler:\n", - "\tOptimization level:\n", - "\tOther relevant compiler options:", - 0}; - - msglist (head); -} - -void -Characteristics () -{ - static char *chars[] = - { - "Running this program should reveal these characteristics:", - " Radix = 1, 2, 4, 8, 10, 16, 100, 256 ...", - " Precision = number of significant digits carried.", - " U2 = Radix/Radix^Precision = One Ulp", - "\t(OneUlpnit in the Last Place) of 1.000xxx .", - " U1 = 1/Radix^Precision = One Ulp of numbers a little less than 1.0 .", - " Adequacy of guard digits for Mult., Div. and Subt.", - " Whether arithmetic is chopped, correctly rounded, or something else", - "\tfor Mult., Div., Add/Subt. and Sqrt.", - " Whether a Sticky Bit used correctly for rounding.", - " UnderflowThreshold = an underflow threshold.", - " E0 and PseudoZero tell whether underflow is abrupt, gradual, or fuzzy.", - " V = an overflow threshold, roughly.", - " V0 tells, roughly, whether Infinity is represented.", - " Comparisions are checked for consistency with subtraction", - "\tand for contamination with pseudo-zeros.", - " Sqrt is tested. Y^X is not tested.", - " Extra-precise subexpressions are revealed but NOT YET tested.", - " Decimal-Binary conversion is NOT YET tested for accuracy.", - 0}; - - msglist (chars); -} - -void -History () -{ /* History */ - /* Converted from Brian Wichmann's Pascal version to C by Thos Sumner, - with further massaging by David M. Gay. */ - - static char *hist[] = - { - "The program attempts to discriminate among", - " FLAWs, like lack of a sticky bit,", - " Serious DEFECTs, like lack of a guard digit, and", - " FAILUREs, like 2+2 == 5 .", - "Failures may confound subsequent diagnoses.\n", - "The diagnostic capabilities of this program go beyond an earlier", - "program called `MACHAR', which can be found at the end of the", - "book `Software Manual for the Elementary Functions' (1980) by", - "W. J. Cody and W. Waite. Although both programs try to discover", - "the Radix, Precision and range (over/underflow thresholds)", - "of the arithmetic, this program tries to cope with a wider variety", - "of pathologies, and to say how well the arithmetic is implemented.", - "\nThe program is based upon a conventional radix representation for", - "floating-point numbers, but also allows logarithmic encoding", - "as used by certain early WANG machines.\n", - "BASIC version of this program (C) 1983 by Prof. W. M. Kahan;", - "see source comments for more history.", - 0}; - - msglist (hist); -} diff --git a/lib/CPUs/MIPS/bsp/examples/phrasen.c b/lib/CPUs/MIPS/bsp/examples/phrasen.c deleted file mode 100644 index 08abf97..0000000 --- a/lib/CPUs/MIPS/bsp/examples/phrasen.c +++ /dev/null @@ -1,298 +0,0 @@ -#include -#include -#include "libsys.h" - -struct substantive -{ - char *subst; - int sex; -}; - -struct verben -{ - char *verb_k; - char *verb_gr; - int art; -}; - -struct adjektive -{ - char *adj; -}; - - char *art[4]={"er","ie","as","en"}; - -char getch(void) -{ - return _getchar(); -} - -void randomize(void) -{ - srand(clock()); -} - -struct substantive namen[]= -{ - {"Gerhard Schröder",1},{"Helmut Kohl",1},{"Rudolf Scharping",1}, - {"Claudia Nolte",2}, {"Johannes Rau",1},{"Wolfgang Schäuble",1}, - {"Joschka Fischer",1},{"Toni Blair",1},{"Kleopatra",2}, - {"Claudia Schiffer",2},{"Hannelore Kohl",2},{"Konrad Adenauer",1}, - {"Michael Jackson",1},{"Karl Marx",1}, {"Helmut Kohl",1},{"Heino",1}, - {"Gerhard Schröder",1},{"Donald Duck",1},{"Madonna",2},{"Jesus",1}, - {"Gott",1},{"Sheryl Crow",2},{"Verona Feldbusch",2},{"Pipi Langstrumpf",2}, - {"Bill Gates",1},{"Bill Clinton",1},{"Cleopatra",2},{"Winnetou",1}, - {"Käpt'n Blaubär",1},{"Rita Süssmuth",2},{"Boris Becker",1}, - {"Lilo Wanders",2},{"Queen Elizabeth",2},{"Lady Di",2},{"Steffi Graf",2}, - {"Frank Zappa",1},{"Dolly Buster",2},{"Mao Tse Tung",1},{"Ghandi",1}, - {"Dalai Lama",1},{"Teufel",1},{"Lenin",1},{"Edmund Stoiber",1}, - {"Ludwig van Beethoven",1},{"Wolfgang Amadeus Mozart",1}, - {"Richard Wagner",1},{"Erich Honecker",1},{"Adam Riese",1}, - {"Bill Clinton",1},{"Josef Stalin",1},{"Willy Brandt",1}, - {"John F. Kennedy",1},{"E.T.",1},{"Donald Duck",1},{"Lothar Matthäus",1}, - {"Hans Dietrich Genscher",1},{"Franz Josef Strauss",1},{"Sting",1}, - {"Hermann Hesse",1},{"Albert Einstein",1},{"Max Planck",1}, - {"Tom Jones",1},{"Heidi Kabel",2},{"Homer Simpson",1},{"Zeus",1}, - {"Helmut Schmidt",1},{"Antje Vollmer",2},{"Politiker",1},{"Papst",1}, - {"Bundeskanzler",1},{"Arzt",1},{"Friseuse",2},{"Teufel",1}, - {"Sandmännchen",3},{"Mutter",2},{"Vater",1},{"Säufer",1},{"Student",1}, - {"Bauer",1},{"Leiche",2},{"Polizist",1},{"Patientin",2},{"Bäcker",1}, - {"Wirt",1}, {"Schlachter",1},{"Baby",3},{"Reporter",1},{"Politiker",1}, - {"Beamtin",2},{"Oma",2},{"Putzfrau",2},{"Blinde",2},{"Wahnsinnige",2}, - {"Mörder",1},{"Psychiater",1},{"Prinz Charles",1},{"Onkel",1},{"Tante",2} -}; - -struct substantive sachen[]= -{ - {"Haus",3},{"Buch",3},{"Fahrrad",3},{"Schule",2},{"Auto",3},{"Nase",2}, - {"Mund",1},{"Kopf",1},{"Kaffee",1},{"Telephon",3},{"Tasse",2},{"Katze",2}, - {"Hund",1},{"Maus",2},{"Stuhl",1},{"Mann",1},{"Frau",2},{"Kind",3}, - {"Idiotin",2},{"Lampe",2},{"Panzer",1},{"Klavier",3},{"Gitarre",2}, - {"Straße",2},{"Wasser",3},{"Luft",2},{"Feuer",3},{"Erde",2},{"Mond",1}, - {"Sonne",2},{"Bild",3},{"Stadt",2},{"Land",3},{"Fluss",1}, - {"Bundeskanzler",1},{"Ball",1},{"Hut",1},{"Hose",2},{"Hemd",3},{"Tod",1}, - {"Geld",3},{"Tisch",1},{"Hand",2},{"Baum",1},{"Bier",3},{"Ratte",2}, - {"Esel",1},{"Musik",2},{"Blech",3},{"Dose",2},{"Zahn",1},{"Humor",1}, - {"Unterhose",2},{"Gift",3},{"Gesicht",3},{"Fuß",1},{"Auge",3},{"Warze",2}, - {"Ohr",3},{"Kanone",2},{"Milch",2},{"Messer",3},{"Papier",3},{"Haar",3}, - {"Welt",2},{"Motor",1},{"Langeweile",2},{"Grab",3},{"Schnaps",1}, - {"Vogel",1},{"Fisch",1},{"Meer",3},{"Banane",2},{"Brot",3}, - {"Sitzung",2},{"Labor",3},{"Kurzschluß",1},{"Lüge",2},{"Axt",2}, - {"Abstimmung",2},{"Toilette",2},{"Zigarette",2},{"Winter",1}, - {"Torte",2},{"Bahnhof",1},{"Sarg",1},{"Imbiss",1},{"Mund",1},{"Seife",2}, - {"Fernseher",1},{"Flasche",2},{"Eimer",1},{"Uhr",2},{"Irrenhaus",3}, - {"Wüste",2},{"Klumpen",1},{"Glück",3},{"Schiff",3},{"Käse",1},{"Quark",1}, - {"Sommer",1},{"Witz",1},{"Idee",2},{"Nacht",2},{"Dreck",1},{"Meer",3}, - {"Blut",3},{"Herz",3},{"Apfel",1},{"Banane",2},{"Mist",1},{"Atom",3}, - {"Note",2},{"Gehirn",3},{"Gefühl",3},{"Bombe",2},{"Vakuum",3}, - {"Zahl",2},{"Wort",3},{"Programm",3},{"Computer",1},{"Orient",1}, - {"Gabelstapler",1} -}; - -struct adjektive ad[]= -{ - {"schön"},{"doof"},{"gut"},{"schlecht"},{"gelb"},{"grün"},{"rot"}, - {"blau"},{"schnell"},{"lang"},{"kurz"},{"hell"},{"düster"},{"sanft"}, - {"hart"},{"langsam"},{"bitter"},{"süß"},{"kaputt"},{"nett"},{"groß"}, - {"klein"},{"leicht"},{"schwer"},{"dick"},{"dünn"},{"rund"},{"eckig"}, - {"heiß"},{"kalt"},{"schlau"},{"elektrisch"},{"nass"},{"trocken"},{"ratlos"}, - {"abartig"},{"genial"},{"bestechlich"},{"irr"},{"steif"},{"angespannt"}, - {"laut"},{"leis"},{"warm"},{"wütend"},{"sauber"},{"schmutzig"},{"arm"}, - {"ätzend"},{"langweilig"},{"interessant"},{"erfahren"},{"abgewählt"}, - {"durchgeknallt"},{"angenehm"},{"widerwärtig"},{"willig"},{"mutig"}, - {"schwach"},{"stark"},{"nervend"},{"spießig"},{"alt"},{"neu"},{"spitz"}, - {"stumpf"},{"teuflisch"},{"scharf"},{"lecker"},{"übelriechend"},{"halb"}, - {"ganz"},{"bleich"},{"peinlich"},{"taktlos"},{"gewieft"},{"windig"}, - {"größenwahnsinnig"},{"verrückt"},{"uralt"},{"aalglatt"},{"korrekt"}, - {"kompetent"},{"einfühlsam"},{"tot"},{"schleimig"},{"gestört"},{"hohl"}, - {"beknackt"},{"nackt"},{"barfüßig"},{"schwitzend"},{"laufend"},{"knackig"}, - {"unverschämt"},{"schläfrig"},{"wohlgeformt"},{"kugelförmig"},{"rauh"}, - {"degeneriert"},{"ekelhaft"},{"brutal"},{"gemein"},{"aggressiv"}, - {"aufdringlich"},{"betroffen"},{"geliebt"},{"gehasst"},{"beharrlich"}, - {"unmenschlich"},{"verblödet"},{"wichtig"},{"gigantisch"},{"winzig"}, - {"witzig"},{"komisch"},{"pervers"},{"fett"},{"stinkend"},{"lausig"}, - {"wendig"},{"breit"},{"locker"},{"einzigartig"},{"sterbend"},{"munter"}, - {"ungepflegt"},{"eisern"},{"echt"},{"besser"},{"wild"},{"ächzend"}, - {"frohlockend"},{"unscheinbar"},{"nebulös"},{"skandalös"},{"obzön"}, - {"beschränkt"},{"genervt"},{"hilflos"},{"unwürdig"},{"geleckt"}, - {"betrunken"},{"unwürdig"},{"bissig"},{"verkalkt"},{"senil"}, - {"jungfräulich"},{"ausgeleiert"},{"beleibt"},{"nachtragend"},{"errötend"}, - {"kahl"},{"würgend"},{"abwesend"},{"ruhig"},{"albern"},{"trostlos"}, - {"salzig"},{"lachend"},{"merkwürdig"},{"behaart"},{"leblos"},{"aufgeblasen"}, - {"frech"},{"kopflos"},{"schmierig"} -}; - -struct verben verb[]= -{ - {"geht","gehen",6},{"steht","stehen",2},{"sitzt","sitzen",2}, - {"spielt","spielen",7},{"singt","singen",2},{"trinkt","trinken",3}, - {"redet","reden",2}, {"liebt","lieben",7},{"schläft","schlafen",2}, - {"ißt","essen",3},{"lacht","lachen",2},{"tötet","töten",7}, - {"lügt","lügen",2},{"fliegt","fliegen",2},{"überfährt","überfahren",7}, - {"sieht","sehen",3},{"hört","hören",3},{"spricht","sprechen",2}, - {"berechnet","rechnen",3},{"schwimmt","schwimmen",2}, - {"zerschneidet","zerschnitten werden",3},{"raucht","rauchen",3}, - {"spaltet","spalten",3},{"verbrennt","verbrennen",2},{"ist","sein",2}, - {"hat","haben",1},{"zerbricht","zerbrechen",3},{"muss","müssen",4}, - {"kann","können",4},{"darf","dürfen",4},{"will","wollen",5}, - {"klaut","klauen",1},{"soll","sollen",4},{"studiert","studieren",3}, - {"reibt","reiben",3},{"liest","lesen",2},{"irrt","irren",2}, - {"spendiert","spendieren",1},{"schlägt","schlagen",3},{"fragt","fragen",7}, - {"zerstört","zerstören",1},{"erschießt","sich erschießen",1}, - {"überlegt","überlegen",2},{"trifft","treffen",7},{"leckt","lecken",1}, - {"wirft","werfen",1},{"vergiftet","vergiftet werden",1}, - {"öffnet","öffnen",1},{"schreit","schreien",2},{"sprengt","explodieren",3}, - {"erwürgt","würgen",7},{"arbeitet","arbeiten",2},{"erlegt","erlegen",1}, - {"putzt","putzen",1},{"stirbt","sterben",2}, {"kauft","kaufen",1}, - {"brüllt","brüllen",2},{"versteht","es verstehen",7}, - {"zertritt","zertreten werden",1},{"verendet","verenden",2}, - {"labert","labern",2},{"kratzt","kratzen",1},{"wird","nichts werden",2}, - {"entkleidet","sich entkleiden",7},{"verbiegt","sich verbiegen",1}, - {"verschenkt","es verschenken",7},{"vergisst","es vergessen",1}, - {"ergreift","greifen",1},{"baut","bauen",1},{"betet","beten",}, - {"rollt","rollen",3},{"bleibt","bleiben",2},{"wäscht","sich waschen",1}, - {"heiratet","heiraten",7},{"hebt","heben",1},{"denkt","nachdenken",2} -}; - -void end_sach_aus(void); -void nam_aus(void); -void end_nam_aus(void); -void adj_aus(void); -int verb_aus_k(void); -int verb_aus_gr(void); -int zufall(int); - -int main() -{ - int vindx; - int rem=0; - char end; - - setbuf(stdout, NULL); - randomize(); - printf("\n\t\t************************"); - printf("\n\t\t* DER ELEKTRISCHE POET *"); - printf("\n\t\t************************\n"); - printf("\n\tCopyright by J. Ahrensfeld & T. Burr"); - printf("\n\n\tFür die Texte ist Ihr Computer verantwortlich :-)\n"); - printf("\n\tZum beenden des Programmes 'x' eingeben!\n"); - printf("\n\tWeiter mit beliebiger Taste!\n"); - end = getch(); - - while(end != 'x') - { - if(rem >= 10) - { - printf("\n\n\tZum beenden des Programmes 'x' eingeben!\n"); - rem = 0; - if(getch() == 'x') - break; - } - printf("\n\n"); - nam_aus(); - - vindx=verb_aus_k(); - - switch (vindx) - { - case 1: end_sach_aus(); break; - - case 2: adj_aus(); break; - - case 3: end_sach_aus(); break; - - case 4: verb_aus_gr(); break; - - case 5: verb_aus_gr(); break; - - case 6: adj_aus(); break; - - case 7: end_nam_aus(); break; - } - - printf("."); - end = getch(); - rem++; - - } - printf("\n\n\tDas ist das Ende!"); - return 0; -} - -int zufall(int max) -{ - - return (rand()%max); -} - -void adj_aus(void) -{ - printf("%s", ad[zufall((sizeof(ad)/sizeof(*ad)))].adj); - return; -} - -void end_sach_aus(void) -{ - int index; - - index = zufall(sizeof(sachen)/sizeof(*sachen)); - if (sachen[index].sex==1) - printf("d%s", art[3]); - else - printf("d%s", art[(sachen[index].sex)-1]); - printf(" "); - adj_aus(); - if (sachen[index].sex==1) - printf("en %s", sachen[index].subst); - else - printf("e %s", sachen[index].subst); - return; -} - -void nam_aus(void) -{ - int index; - - index = zufall(sizeof(namen)/sizeof(*namen)); - printf("D%s", art[(namen[index].sex)-1]); - printf(" "); - adj_aus(); - printf("e %s " ,namen[index].subst); - return; -} - -void end_nam_aus(void) -{ - int index; - - index = zufall(sizeof(namen)/sizeof(*namen)); - if (namen[index].sex==1) - printf("d%s", art[3]); - else - printf("d%s", art[(namen[index].sex)-1]); - printf(" "); - adj_aus(); - if (namen[index].sex==1) - printf("en %s", namen[index].subst); - else - printf("e %s", namen[index].subst); - return; -} - -int verb_aus_k(void) -{ - int index; - - index = zufall(sizeof(verb)/sizeof(*verb)); - printf("%s ", verb[index].verb_k); - return (verb[index].art); -} - -int verb_aus_gr(void) -{ - int index; - - index = zufall(sizeof(verb)/sizeof(*verb)); - printf("%s", verb[index].verb_gr); - return index; -} diff --git a/lib/CPUs/MIPS/bsp/examples/pi.h b/lib/CPUs/MIPS/bsp/examples/pi.h deleted file mode 100644 index 5cfed9b..0000000 --- a/lib/CPUs/MIPS/bsp/examples/pi.h +++ /dev/null @@ -1,13 +0,0 @@ -/* +++Date last modified: 05-Jul-1997 */ - -#ifndef PI__H -#define PI__H - -#ifndef PI - #define PI (4*atan(1)) -#endif - -#define deg2rad(d) ((d)*PI/180) -#define rad2deg(r) ((r)*180/PI) - -#endif /* PI__H */ diff --git a/lib/CPUs/MIPS/bsp/examples/queens.c b/lib/CPUs/MIPS/bsp/examples/queens.c deleted file mode 100644 index f9735e6..0000000 --- a/lib/CPUs/MIPS/bsp/examples/queens.c +++ /dev/null @@ -1,856 +0,0 @@ -/* -** Queens.c -- Find solutions to the Eight-Queens chess problem. -** Roberto Sierra 7/25/93 Version 1.1 -** 3/19/84 Version 1.0 -** -** Description: -** This program finds all the possible ways that N queens can -** be placed on an NxN chessboard so that the queens cannot -** capture one another -- that is, so that no rank, file or -** diagonal is occupied by more than one queen. By default, -** the program prints the first solution it finds. You can -** use the -a option to print all solutions, or the -c option -** just to count them. The program allows the chess board -** to be from 1x1 (trivial case) to 100x100. Warning: the -** larger the chess board, the longer it typically takes to -** find each solution, even though there may be more of them. -** -** This is a terrific example of the utility of recursion. The -** algorithm uses recursion to drastically limit the number -** of board positions that are tested. The program is able -** to find all 8x8 queen solutions in a fraction of a second -** (not counting print time). The code makes no attempt to -** eliminate symmetrical solutions, so the number of solutions -** reported will always be higher than the actual number of -** distinct solutions. -** -** -** Usage: -** Queens [-ac] n -** -** n number of queens (rows and columns). -** An integer from 1 to 100. -** -a Find (and print) all solutions. -** -c Count all solutions, but do not print them. -** -** The output is sent to stdout. All errors messages are -** sent to stderr. If a problem arises, the return code is -1. -** -** -** Examples: -** -** Queens 8 ## Show an 8x8 solution -** 8 queens on a 8x8 board... -** Q - - - - - - - -** - - - - Q - - - -** - - - - - - - Q -** - - - - - Q - - -** - - Q - - - - - -** - - - - - - Q - -** - Q - - - - - - -** - - - Q - - - - -** -** Queens -c 8 ## Count all 8x8 solutions -** 8 queens on a 8x8 board... -** ...there are 92 solutions. -** -** Queens -a 4 ## Show all 4x4 solutions -** 4 queens on a 4x4 board... -** -** Solution #1: -** - Q - - -** - - - Q -** Q - - - -** - - Q - -** -** Solution #2: -** - - Q - -** Q - - - -** - - - Q -** - Q - - -** -** ...there are 2 solutions. -** -** -** Build Instructions: -** You'll need an ANSI C compiler (or the willingness to edit -** the program a bit). If you've got Gnu C, then you can -** compile and load the program as follows: -** -** gcc Queens.c -ansi -o Queens -** -** [If you're using MPW on the Mac, define '-d MPW' on the -** compile line so that background processing will occur.] -** -** -** Algorithm: -** In a 1984 Byte article, I ran across an interesting letter -** from a high school student who was attempting to solve the -** Eight Queens problem using a BASIC interpreter. He had -** developed a program which placed eight queens successively -** on all sixty-four squares, testing for conflicts at each -** iteration. Of course, such a program would require 64^8 -** iterations (about 2.8x10^14 iterations). Even in C on a, -** fast CPU, this could take months or years. Byte's answer was -** to alter the loops so that the queens resided on separate -** ranks, thereby reducing the number of iterations required -** to find all solutions to 8^8 iterations (about 16 million). -** More reasonable, but still requiring a chunk of CPU time. -** -** I puzzled about this problem a bit, and came to realize that -** this was still wasting a lot of CPU cycles. Though I'm sure -** others have come up with good algorithms, I decided to come -** up with my own, with a particular eye on efficiency. The -** resulting algorithm finds all 8x8 solutions in a fraction -** of a second (there are 92 solutions, including rotations). -** On a Sun 4, it'll find all 365,596 solutions on a 14x14 board -** in a bit over 2 minutes (printing them out requires extra -** time, of course). Even Byte's solution would require 14^14 -** iterations (about 10^16) which would take aeons. -** -** My algorithm works as follows: -** (1) Place a queen in the top left corner. -** (2) Place another queen immediately below. -** (3) Test for conflicts. If the second queen conflicts (it -** does at first), then move it one square to the right. -** (4) Loop step 3 until there are no conflicts. Place -** the next queen on the board and recurse. -** (5) If any queen reaches the right edge of the board, -** remove it and 'pop' to the previous recursion level. -** (6) Now repeat these steps recursively until all eight -** queens (or however many) have been placed without -** conflict -- the result is a solution to the problem, -** which is counted and optionally printed. -** -** Because conflicts are tested as the recursion proceeds, -** this has the effect of 'pruning' the recursion so that -** a large number of board positions are not even attempted. -** The result is that the algorithm runs in reasonable time. -** -** I used a few tricks to make the test-for-conflict code -** extremely efficient -- there is no 'inner' loop to search -** along ranks, files, or diagonals. A series of arrays are -** maintained instead which indicate which queen currently -** 'owns' each rank, file or diagonal. This makes the -** algorithm really fly, though the code is a little hard to -** read. Lastly, pointer arithmetic is used to reduce the -** number of implicit multiplications used in array addressing. -** -** -** Contact: -** For queries regarding this program, contact Roberto Sierra -** at any of the following addresses: -** -** Roberto Sierra -** bert@netcom.com (preferred address) -** 73557.2101@compuserve.com -** -** Tempered MicroDesigns -** P.O. Box 170638 -** San Francisco, CA 94117 -** -** -** Fine Print: -** This program is in the public domain and can be used for -** any purpose whatsoever, including commercial application. -** [I'd like to hear what you do with it, though.] -** Absolutely no warranty or liability is implied or extended -** by the author. -** -** -** Modification History: -** PRS 3/19/84 v1.0 -- Original version. -** PRS 7/25/93 v1.1 -- ANSIfied the code. More efficient pointers. -** -*/ - -/***************************************************************/ -/* Timer options. You MUST uncomment one of the options below */ -/* or compile, for example, with the '-DUNIX' option. */ -/***************************************************************/ -/* #define Amiga */ -/* #define UNIX */ -/* #define UNIX_Old */ -/* #define VMS */ -/* #define BORLAND_C */ -/* #define MSC */ -/* #define MAC */ -/* #define IPSC */ -/* #define FORTRAN_SEC */ -/* #define GTODay */ -/* #define CTimer */ -/* #define UXPM */ -/* #define MAC_TMgr */ -/* #define PARIX */ -/* #define POSIX */ -/* #define WIN32 */ -/* #define POSIX1 */ -/***********************/ - -#include /* Need standard I/O functions */ -#include /* Need exit() routine interface */ -#include /* Need strcmp() interface */ -#ifdef MPW /* Macintosh MPW ONLY */ -#include /* Need cursor control interfaces */ -#endif - -#define MAXQUEENS 100 /* Maximum number of queens */ -#define MAXRANKS MAXQUEENS /* Maximum number of ranks (rows) */ -#define MAXFILES MAXQUEENS /* Maximum number of files (columns) */ -#define MAXDIAGS (MAXRANKS+MAXFILES-1) /* Maximum number of diagonals */ -#define EMPTY (MAXQUEENS+1) /* Marks unoccupied file or diagonal */ - -/* GLOBAL VARIABLES */ - -int queens; /* Number of queens to place */ -int ranks; /* Number of ranks (rows) */ -int files; /* Number of files (columns) */ -int printing = 1; /* TRUE if printing positions */ -int findall = 0; /* TRUE if finding all solutions */ - -unsigned long solutions = 0; /* Number of solutions found */ -int queen[MAXRANKS]; /* File on which each queen is located */ -int file[MAXFILES]; /* Which queen 'owns' each file */ -int fordiag[MAXDIAGS]; /* Which queen 'owns' forward diagonals */ -int bakdiag[MAXDIAGS]; /* Which queen 'owns' reverse diagonals */ -char *progname = 0; /* The name of this program */ - - - - - -/***********************/ -/**** ROUTINES ****/ -/***********************/ - -/* Internal prototypes */ -//void main(int argc,char **argv); /* Main program */ -void find(int level); /* Algorithm to find solutions */ -void pboard(void); /* Print a solution */ -void run_queens(int argc,char **argv); - - - - -/*---------------------- main() --------------------------- -** MAIN program. The main purpose of this routine is -** to deal with decoding the command line arguments, -** initializing the various arrays, and starting the -** recursive search routine. -*/ -int main(void) -{ - char *args[] = {"queens", "-c", "12"}; - run_queens(3, args); -} - -void run_queens(int argc,char **argv) -{ - register int i; /* Loop variable */ - register char *p; /* Pointer to argument */ - double starttime, benchtime, dtime(); - -#ifdef MPW /* Macintosh MPW ONLY */ - InitCursorCtl(0); /* Enable cursor control */ -#endif - - progname = argv[0]; /* The name of the program */ - - /**** DECODE COMMAND LINE ARGUMENTS ****/ - - for (i=1; i MAXQUEENS) { /* N can't be too large */ - fprintf(stderr,"%s: can't have more than %d queens\n", - progname, MAXQUEENS); - exit(-1); - } - } /* End of argument test */ - } /* End of argument scan loop */ - if (queens == 0) { - fprintf(stderr,"%s: missing queens argument\n",progname); - fprintf(stderr,"usage: %s [-ac] queens\n",progname); - exit(-1); - } - - - ranks = files = queens; /* NxN board for N queens */ - printf("%d queen%s on a %dx%d board...\n", - queens, queens>1? "s" : "", ranks, files); - fflush(stdout); - - starttime = dtime(); - - /* Initialization */ - solutions = 0; /* No solutions yet */ - for (i=0; i= level && /* No queen on the file? */ - *fdp >= level && *bdp >= level /* No queens on diagonals? */ - ) { - queen[level] = f; /* Note new position of queen */ - *fp = *fdp = *bdp = level; /* Place queen on file & diags */ - find(level+1); /* This level OK, recurse to next */ - *fp = *fdp = *bdp = EMPTY; /* Remove queen from file & diags */ - } /* End of conflict test */ - } /* End of file loop */ - } /* End if (level == queens) */ -} /* End of find() */ - - - - -/*------------------------- pboard() ----------------------- -** This routines prints the board for a particular solution. -** The output is sent to stdout. -*/ - -void pboard(void) -{ - register int i,j; /* Rank/File indices */ - - if (findall) { /* Only if searching for all */ - printf("\nSolution #%lu:\n",solutions); /* Print solution number */ - } - for (i=0; i -#define HZ 50 - -double dtime() -{ - double q; - - struct tt - { - long days; - long minutes; - long ticks; - } tt; - - DateStamp(&tt); - - q = ((double)(tt.ticks + (tt.minutes * 60L * 50L))) / (double)HZ; - - return q; -} -#endif - -/*****************************************************/ -/* UNIX dtime(). This is the preferred UNIX timer. */ -/* Provided by: Markku Kolkka, mk59200@cc.tut.fi */ -/* HP-UX Addition by: Bo Thide', bt@irfu.se */ -/*****************************************************/ -#ifdef UNIX -#include -#include - -#ifdef hpux -#include -#define getrusage(a,b) syscall(SYS_getrusage,a,b) -#endif - -struct rusage rusage; - -double dtime() -{ - double q; - - getrusage(RUSAGE_SELF,&rusage); - - q = (double)(rusage.ru_utime.tv_sec); - q = q + (double)(rusage.ru_utime.tv_usec) * 1.0e-06; - - return q; -} -#endif - -/***************************************************/ -/* UNIX_Old dtime(). This is the old UNIX timer. */ -/* Make sure HZ is properly defined in param.h !! */ -/***************************************************/ -#ifdef UNIX_Old -#include -#include -#include - -#ifndef HZ -#define HZ 60 -#endif - -struct tms tms; - -double dtime() -{ - double q; - - times(&tms); - - q = (double)(tms.tms_utime) / (double)HZ; - - return q; -} -#endif - -/*********************************************************/ -/* VMS dtime() for VMS systems. */ -/* Provided by: RAMO@uvphys.phys.UVic.CA */ -/* Some people have run into problems with this timer. */ -/*********************************************************/ -#ifdef VMS -#include time - -#ifndef HZ -#define HZ 100 -#endif - -struct tbuffer_t - { - int proc_user_time; - int proc_system_time; - int child_user_time; - int child_system_time; - }; - -struct tbuffer_t tms; - -double dtime() -{ - double q; - - times(&tms); - - q = (double)(tms.proc_user_time) / (double)HZ; - - return q; -} -#endif - -/******************************/ -/* BORLAND C dtime() for DOS */ -/******************************/ -#ifdef BORLAND_C -#include -#include -#include - -#define HZ 100 -struct time tnow; - -double dtime() -{ - double q; - - gettime(&tnow); - - q = 60.0 * (double)(tnow.ti_min); - q = q + (double)(tnow.ti_sec); - q = q + (double)(tnow.ti_hund)/(double)HZ; - - return q; -} -#endif - -/**************************************/ -/* Microsoft C (MSC) dtime() for DOS */ -/**************************************/ -#ifdef MSC -#include -#include - -#define HZ CLOCKS_PER_SEC -clock_t tnow; - -double dtime() -{ - double q; - - tnow = clock(); - - q = (double)tnow / (double)HZ; - - return q; -} -#endif - -/*************************************/ -/* Macintosh (MAC) Think C dtime() */ -/*************************************/ -#ifdef MAC -#include - -#define HZ 60 - -double dtime() -{ - double q; - - q = (double)clock() / (double)HZ; - - return q; -} -#endif - -/************************************************************/ -/* iPSC/860 (IPSC) dtime() for i860. */ -/* Provided by: Dan Yergeau, yergeau@gloworm.Stanford.EDU */ -/************************************************************/ -#ifdef IPSC -extern double dclock(); - -double dtime() -{ - double q; - - q = dclock(); - - return q; -} -#endif - -/**************************************************/ -/* FORTRAN dtime() for Cray type systems. */ -/* This is the preferred timer for Cray systems. */ -/**************************************************/ -#ifdef FORTRAN_SEC - -fortran double second(); - -double dtime() -{ - double q; - - second(&q); - - return q; -} -#endif - -/***********************************************************/ -/* UNICOS C dtime() for Cray UNICOS systems. Don't use */ -/* unless absolutely necessary as returned time includes */ -/* 'user+system' time. Provided by: R. Mike Dority, */ -/* dority@craysea.cray.com */ -/***********************************************************/ -#ifdef CTimer -#include - -double dtime() -{ - double q; - clock_t clock(void); - - q = (double)clock() / (double)CLOCKS_PER_SEC; - - return q; -} -#endif - -/********************************************/ -/* Another UNIX timer using gettimeofday(). */ -/* However, getrusage() is preferred. */ -/********************************************/ -#ifdef GTODay -#include - -struct timeval tnow; - -double dtime() -{ - double q; - - gettimeofday(&tnow,NULL); - q = (double)tnow.tv_sec + (double)tnow.tv_usec * 1.0e-6; - - return q; -} -#endif - -/*****************************************************/ -/* Fujitsu UXP/M timer. */ -/* Provided by: Mathew Lim, ANUSF, M.Lim@anu.edu.au */ -/*****************************************************/ -#ifdef UXPM -#include -#include -struct tmsu rusage; - -double dtime() -{ - double q; - - timesu(&rusage); - - q = (double)(rusage.tms_utime) * 1.0e-06; - - return q; -} -#endif - -/**********************************************/ -/* Macintosh (MAC_TMgr) Think C dtime() */ -/* requires Think C Language Extensions or */ -/* #include in the prefix */ -/* provided by Francis H Schiffer 3rd (fhs) */ -/* skipschiffer@genie.geis.com */ -/**********************************************/ -#ifdef MAC_TMgr -#include -#include - -static TMTask mgrTimer; -static Boolean mgrInited = false; -static double mgrClock; - -#define RMV_TIMER RmvTime( (QElemPtr)&mgrTimer ) -#define MAX_TIME 1800000000L -/* MAX_TIME limits time between calls to */ -/* dtime( ) to no more than 30 minutes */ -/* this limitation could be removed by */ -/* creating a completion routine to sum */ -/* 30 minute segments (fhs 1994 feb 9) */ - -static void Remove_timer( ) -{ - RMV_TIMER; - mgrInited = false; -} - -double dtime( ) -{ - if( mgrInited ) { - RMV_TIMER; - mgrClock += (MAX_TIME + mgrTimer.tmCount)*1.0e-6; - } else { - if( _atexit( &Remove_timer ) == 0 ) mgrInited = true; - mgrClock = 0.0; - } - - if ( mgrInited ) - { - mgrTimer.tmAddr = NULL; - mgrTimer.tmCount = 0; - mgrTimer.tmWakeUp = 0; - mgrTimer.tmReserved = 0; - InsTime( (QElemPtr)&mgrTimer ); - PrimeTime( (QElemPtr)&mgrTimer, -MAX_TIME ); - } - return( mgrClock ); -} -#endif - -/***********************************************************/ -/* Parsytec GCel timer. */ -/* Provided by: Georg Wambach, gw@informatik.uni-koeln.de */ -/***********************************************************/ -#ifdef PARIX -#include - -double dtime() -{ - double q; - - q = (double) (TimeNowHigh()) / (double) CLK_TCK_HIGH; - - return q; -} -#endif - -/************************************************/ -/* Sun Solaris POSIX dtime() routine */ -/* Provided by: Case Larsen, CTLarsen.lbl.gov */ -/************************************************/ -#ifdef POSIX -#include -#include -#include - -#ifdef __hpux -#include -#endif - -struct rusage rusage; - -double dtime() -{ - double q; - - getrusage(RUSAGE_SELF,&rusage); - - q = (double)(rusage.ru_utime.tv_sec); - q = q + (double)(rusage.ru_utime.tv_nsec) * 1.0e-09; - - return q; -} -#endif - - -/****************************************************/ -/* Windows NT (32 bit) dtime() routine */ -/* Provided by: Piers Haken, piersh@microsoft.com */ -/****************************************************/ -#ifdef WIN32 -#include - -double dtime(void) -{ - double q; - - q = (double)GetTickCount() * 1.0e-03; - - return q; -} -#endif - -/*****************************************************/ -/* Time according to POSIX.1 - */ -/* Ref: "POSIX Programmer's Guide" O'Reilly & Assoc.*/ -/*****************************************************/ -#ifdef POSIX1 -#define _POSIX_SOURCE 1 -#include -#include -#include - -struct tms tms; - -double dtime() -{ - double q; - times(&tms); - q = (double)tms.tms_utime / (double)CLK_TCK; - return q; -} -#endif - -/*-------- End of queens.c, Say goodnight Linda! --------*/ diff --git a/lib/CPUs/MIPS/bsp/examples/r3.c b/lib/CPUs/MIPS/bsp/examples/r3.c deleted file mode 100644 index adba0bc..0000000 --- a/lib/CPUs/MIPS/bsp/examples/r3.c +++ /dev/null @@ -1,471 +0,0 @@ -/* - * IOCCC Raytracer by Anders Gavare. - * - * The raytracer was one of the winners of the 17th IOCCC. - * - * NOTE: This is the UNOBFUSCATED version of the raytracer I used - * during development, not the actual entry sent to the contest. - * - * - * How to build: - * cc r3.c -o r3 (plus optimization flags) - * - * How to run: - * ./r3 > ray.ppm - * or - * ./r3 | xv - - */ -#include "libsys.h" -UINT32 *pP; - -xsize = 800; -ysize = 600; -An = 1; - -camera_X = 0; -camera_Y = -10; -camera_Z = -7; - -scale = 1296; -RootOfScale = 36; -maxcolor = 255; - -MaxDepth=9; -_=1<<15; - -/* -double sphere_x[44] = { - -15,-15,-15,-15, // I - -8,-8,-10,-6,-10,-6, // O - -1,-1, 1,1, // C - 6, 6, 8,8, // C - 13,13,15,15, // C - -11,-11,-11,-11,-9,-9,-7,-7, // r - 0,0,-2,-2,-2,2,2,2, // a - 7,7,9,9,11,11, // y - }; -double sphere_z[44] = { - 3,0,-3,-6, // I - -6, 3,0,0,-3,-3, // O - 0,-3,-6, 3, // C - 0,-3,-6, 3, // C - 0,-3,-6, 3, // C - -11,-13,-15,-17,-11,-15,-13,-17, // r - -11,-15,-13,-15,-17,-13,-15,-17, // a - -11,-13,-15,-17,-11,-13, // y - }; -*/ - -/* Common return variable: */ -return_var; -return_var2; -return_var3; -return_var4; - - -get_sphere_coordinates(b) -{ - return_var = "1111886:6:??AAFFHHMMOO55557799@@>>>BBBGGIIKK"[b]-64; - return_var3 = "C@=::C@@==@=:C@=:C@=:C531/513/5131/31/531/53"[b]-64; - -/* return_var = sphere_x[b]; */ - return_var2 = b<22? 9 : 0; -/* return_var3 = sphere_z[b]; */ - return_var4 = 2; -} - - -/* sqroot(x) returns the square root of x in return_var */ -sqroot_sub(x, mask, guess) -{ - mask? - ( - guess ^= mask, - guess*guess > x ? - ( guess ^= mask ) - : - 0, - sqroot_sub(x, mask/2, guess) - ) - : - ( return_var = guess ); -} - - -sqroot(x) -{ - sqroot_sub(x, _, 0); -} - - -/* - * hit_sphere(): - * - * returns where on a sphere we hit - * Returns distance in hit_sphere_q. (Negative return - * value if we didn't hit anything.) - */ -hit_sphere_q; -hit_sphere(objnr, x, y, z, - dx, dy, dz, - a, b) -{ - get_sphere_coordinates(objnr); - x -= return_var*scale; - y -= return_var2*scale; - z -= return_var3*scale; - - /* - * Solve the following equation: - * - * q^2 (dx^2+dy^2+dz^2) + q * 2(x*dx+y*dy+z*dz) - * + x^2+y^2+z^2 - r^2 = 0 - * - * We assume that |dx,dy,dz| is 1. - * - * q^2 + a q + b = 0 - * - * The solution is (of course) - * - * q = -a/2 +- sqrt(a^2/4 - b) - */ - - b = x*x/scale+y*y/scale+z*z/scale-return_var4*return_var4*scale; - - /* a = 2*(...), and then divide by -2 */ - a = -x*dx/scale-y*dy/scale-z*dz/scale; - - hit_sphere_q = - ( - (b = a*a/scale - b) >= 0 ? - ( -/* b = scale*sqrt((double)b/(double)scale), */ -/* sqroot(b*scale), */ - -/* sqroot_sub(b, _, 0), - b = return_var * RootOfScale, -*/ - sqroot_sub(b*scale, _, 0), - b = return_var, - - /* - * Return the lowest q (a+b or a-b) which is more - * than 0. Return negative if neither - * a+b or a-b is more than 0. - */ - - a + (a>b? -b : b) - ) - : - -1.0 - ); -} - - -/* - * find_closest(): - * - * find_closest() scans objects and returns an index - * to the object which was closest (has the lowest 'q'). - * x,y,z,dx,dy,dz are scaled. - * find_closest_i is the index number of the found object, - * -1 if none was found. find_closest_q is the distance - * (scaled). - */ -find_closest_i; /* index ("sphere number") */ -find_closest_q; /* distance (scaled) */ -find_closest(objnr, x, y, z, - dx, dy, dz, notindex) -{ - /* Initialize find_closest_i on first call: */ - find_closest_i = - !objnr ? -1 : find_closest_i; - - objnr < 44 ? - ( - hit_sphere(objnr, x,y,z, dx,dy,dz, 0,0), - (hit_sphere_q > 0 && objnr!=notindex && - (hit_sphere_q0 && find_closest_i >= 0? - ( - /* find_closest_i and _q are the object - number and distance of the object we - hit. */ - - orig_x += dir_x*find_closest_q/scale, - orig_y += dir_y*find_closest_q/scale, - orig_z += dir_z*find_closest_q/scale, - - /* - * Calculate color (diffuse light): - * (Note: use nZ as a temp variable while - * calculating nY) - */ - get_sphere_coordinates(find_closest_i), - nX = orig_x - return_var*scale, - nY = orig_y - return_var2*scale, - nZ = orig_z - return_var3*scale, - - tmpcol = (-2*nX -2*nY + nZ) / 3, /* sqrt(9), */ - /* Set return_var to the length of the normal - vector (in this case the sphere radius) */ -/* return_var = sqrt(nX*nX + nY*nY +nZ*nZ), */ - sqroot(nX*nX + nY*nY +nZ*nZ), -// return_var = return_var4*scale, - /* divide by return_var to get the color */ -// tmpcol = return_var!=0? tmpcol*scale/return_var : 0, - tmpcol /= return_var4, - - /* color is now -1..1 */ - tmpcol *= tmpcol, /* square the color 1..-1 => 1..1 */ - tmpcol *= 200, - tmpcol /= (scale*scale), -/* tmpcol += 5, */ - - closest_i_saved = find_closest_i, - - /* Mirror: out = in - 2*(-normal)*cos v - where v is the angle between in and - -normal */ - - /* -normal: (normalized to len=1.0) */ -/* return_var = sqrt(nX*nX + nY*nY + nZ*nZ), */ - return_var!=0? - ( - nX = -nX * scale / return_var, - nY = -nY * scale / return_var, - nZ = -nZ * scale / return_var - ) : 0, - - /* use return_var as a temp variable, - calculate cosinus between the vectors */ - return_var = (dir_x*nX + dir_y*nY + dir_z*nZ)/scale, -/* - dir_x -= 2 * nX * return_var / scale, - dir_y -= 2 * nY * return_var / scale, - dir_z -= 2 * nZ * return_var / scale, -*/ - dir_x -= nX * return_var / (scale/2), - dir_y -= nY * return_var / (scale/2), - dir_z -= nZ * return_var / (scale/2), - - trace_ray(orig_x, orig_y, orig_z, - dir_x, dir_y, dir_z, - depth-1, find_closest_i, 0,0), - - trace_ray_R /= 2, - trace_ray_G /= 2, - trace_ray_B /= 2, -/* - closest_i_saved &= 7, - !closest_i_saved? (closest_i_saved++) : 0, -*/ -/* - closest_i_saved = closest_i_saved<4? closest_i_saved+1 : 7, -*/ -/* - tvinga gråskalor: closest_i_saved = 7, -*/ -closest_i_saved = closest_i_saved<22? 7 : - ( - closest_i_saved<30 ? 1 : - ( - closest_i_saved<38 ? 2 : - ( - closest_i_saved<44 ? 4 : - ( - closest_i_saved == 44 ? 6 : - 3 - ) - ) - ) - ), - - trace_ray_R += closest_i_saved & 1 ? tmpcol : 0, - trace_ray_G += closest_i_saved & 2 ? tmpcol : 0, - trace_ray_B += closest_i_saved & 4 ? tmpcol : 0 - ) - : - ( - /* If we didn't hit anything, set the color anyway: */ - - depth==MaxDepth? /* True if this is a ray originating - from the camera */ - ( - orig_z += 2, - dir_z = orig_z > 0? orig_z / 8 : orig_z / 20 - ) - : 0, - - /* - * Colors according to Horizon_1 in gimp: - * At top of sky: 13,92,146 (light blue) - * At bottom sky: 255,255,255 (white) - * Top of ground: 213,168,111 (light brown) - * Bottom of ground: 103, 55, 26 (brown) - */ - - dir_z > 0? - ( - trace_ray_B = dir_z * dir_z / scale, - trace_ray_R = 255 - 250 * trace_ray_B / scale, - trace_ray_G = 255 - 150 * trace_ray_B / scale, - trace_ray_B = 255 - 100 * trace_ray_B / scale - ) - : - ( - trace_ray_B = dir_z * dir_z / scale, - trace_ray_B < scale/5? - ( - trace_ray_R = 255 - 210 * trace_ray_B / scale, - trace_ray_G = 255 - 435 * trace_ray_B / scale, - trace_ray_B = 255 - 720 * trace_ray_B / scale - ) - : - ( - trace_ray_B -= scale/5, - trace_ray_R = 213 - 110 * trace_ray_B / scale, - trace_ray_G = 168 - 113 * trace_ray_B / scale, - trace_ray_B = 111 - 85 * trace_ray_B / scale - ) - ), - - depth!=MaxDepth? - ( - trace_ray_R /= 2, - trace_ray_G /= 2, - trace_ray_B /= 2 - ) - : 0 - ); - - trace_ray_R = trace_ray_R<0? 0 : trace_ray_R>maxcolor? maxcolor: trace_ray_R; - trace_ray_G = trace_ray_G<0? 0 : trace_ray_G>maxcolor? maxcolor : trace_ray_G; - trace_ray_B = trace_ray_B<0? 0 : trace_ray_B>maxcolor? maxcolor : trace_ray_B; -} - - -/* - * do_pixels_in_line(): - * - * the horizontal "for loop" - */ -R; G; B; -dpil_helper(x,y, a,b) -{ - trace_ray( - scale*camera_X + scale*40*(An*x+a)/xsize/An - scale*20, - scale*camera_Y, - scale*camera_Z - scale*30*(An*y+b)/ysize/An + scale*15, - 0, scale, 0, MaxDepth, -1, 0,0); - - R += trace_ray_R; - G += trace_ray_G; - B += trace_ray_B; - - ++a -#include "snipmath.h" - -#undef rad2deg /* These are macros defined in PI.H */ -#undef deg2rad - -double rad2deg(double rad) -{ - return (180.0 * rad / (PI)); -} - -double deg2rad(double deg) -{ - return (PI * deg / 180.0); -} - -#ifdef TEST - -#include - -main() -{ - double X; - - for (X = 0.0; X <= 360.0; X += 45.0) - printf("%3.0f degrees = %.12f radians\n", X, deg2rad(X)); - puts(""); - for (X = 0.0; X <= (2 * PI + 1e-6); X += (PI / 6)) - printf("%.12f radians = %3.0f degrees\n", X, rad2deg(X)); - return 0; -} - -#endif /* TEST */ diff --git a/lib/CPUs/MIPS/bsp/examples/random.c b/lib/CPUs/MIPS/bsp/examples/random.c deleted file mode 100644 index c5f6615..0000000 --- a/lib/CPUs/MIPS/bsp/examples/random.c +++ /dev/null @@ -1,86 +0,0 @@ -/* random.c - - Author: Numerical recipes (ran1, gaussian), Jon Hamkins (others) - Revised by: Jon Hamkins - Date: 4-16-98 -*/ - -#include - -#define IA 16807 -#define IM 2147483647 -#define AM (1.0/IM) -#define IQ 127773 -#define IR 2836 -#define NTAB 32 -#define NDIV (1+(IM-1)/NTAB) -#define EPS 1.2e-14 -#define RNMX (1.0-EPS) -/* From Numerical Recipes, p. 280, modified from float to double */ -/* returns a uniform deviate in (0,1) */ -double ran1(long *idum) -{ - int j; - long k; - static long iy=0; - static long iv[NTAB]; - double temp; - - if (*idum <=0 || !iy) { - if (-(*idum) < 1) *idum=1; - else *idum = -(*idum); - for (j=NTAB+7; j>=0; j--) { - k=(*idum)/IQ; - *idum=IA*(*idum-k*IQ)-IR*k; - if (*idum < 0) *idum += IM; - if (j < NTAB) iv[j] = *idum; - } - iy = iv[0]; - } - k=(*idum)/IQ; - *idum=IA*(*idum-k*IQ)-IR*k; - if (*idum < 0) *idum += IM; - j=iy/NDIV; - iy=iv[j]; - iv[j] = *idum; - if ((temp=AM*iy) > RNMX) return RNMX; - else return temp; -} -#undef IA -#undef IM -#undef AM -#undef IQ -#undef IR -#undef NTAB -#undef NDIV -#undef EPS -#undef RNMX - -/* Generate a N(0,1) r.v. */ -double gaussian(long *idum) -{ - static int iset=0; - static double gset; - double fac,r,v1,v2; - double ran1(); - if (iset == 0) { - do { - v1=2.0*ran1(idum)-1.0; - v2=2.0*ran1(idum)-1.0; - r=v1*v1+v2*v2; - } while (r >= 1.0 || r == 0.0); - fac=sqrt(-2.0*log(r)/r); - gset=v1*fac; - iset=1; - return v2*fac; - } else { - iset=0; - return gset; - } -} - -/* generate a random bit */ -int random_bit(long *idum) -{ - return((ran1(idum)<0.5) ? 0 : 1); -} diff --git a/lib/CPUs/MIPS/bsp/examples/random.h b/lib/CPUs/MIPS/bsp/examples/random.h deleted file mode 100644 index 673d6af..0000000 --- a/lib/CPUs/MIPS/bsp/examples/random.h +++ /dev/null @@ -1,6 +0,0 @@ -/* random.h */ - -/* functions provided by random.c */ -extern double ran1(long *idum); -extern double gaussian(long *idum); -extern int random_bit(long *idum); diff --git a/lib/CPUs/MIPS/bsp/examples/regdef.h b/lib/CPUs/MIPS/bsp/examples/regdef.h deleted file mode 100644 index 60c6c2a..0000000 --- a/lib/CPUs/MIPS/bsp/examples/regdef.h +++ /dev/null @@ -1,81 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1985 MIPS Computer Systems, Inc. - * Copyright (C) 1994, 95, 99, 2003 by Ralf Baechle - * Copyright (C) 1990 - 1992, 1999 Silicon Graphics, Inc. - */ -#ifndef _ASM_REGDEF_H -#define _ASM_REGDEF_H - -/* - * Symbolic register names for 32 bit ABI - */ -#define zero $0 /* wired zero */ -#define AT $1 /* assembler temp - uppercase because of ".set at" */ -#define v0 $2 /* return value */ -#define v1 $3 -#define a0 $4 /* argument registers */ -#define a1 $5 -#define a2 $6 -#define a3 $7 -#define t0 $8 /* caller saved */ -#define t1 $9 -#define t2 $10 -#define t3 $11 -#define t4 $12 -#define t5 $13 -#define t6 $14 -#define t7 $15 -#define s0 $16 /* callee saved */ -#define s1 $17 -#define s2 $18 -#define s3 $19 -#define s4 $20 -#define s5 $21 -#define s6 $22 -#define s7 $23 -#define t8 $24 /* caller saved */ -#define t9 $25 -#define jp $25 /* PIC jump register */ -#define k0 $26 /* kernel scratch */ -#define k1 $27 -#define gp $28 /* global pointer */ -#define sp $29 /* stack pointer */ -#define fp $30 /* frame pointer */ -#define s8 $30 /* same like fp! */ -#define ra $31 /* return address */ - -/* CP0 registers */ -#define CP0_INDEX $0 /* R3000 available */ -#define CP0_RANDOM $1 /* R3000 available */ -#define CP0_ENTRYLO $2 /* R3000 available */ -#define CP0_CONTEXT $4 /* R3000 available */ -#define CP0_BADDR $8 /* R3000 available */ -#define CP0_ENTRYHI $10 /* R3000 available */ -#define CP0_SR $12 /* R3000 available */ -#define CP0_CR $13 /* R3000 available */ -#define CP0_EPC $14 /* R3000 available */ -#define CP0_PRID $15 /* R3000 available */ - -/* Status register masks */ -#define SR_MASK_IEC 0x00000001 -#define SR_MASK_KUC 0x00000002 -#define SR_MASK_IEP 0x00000004 -#define SR_MASK_KUP 0x00000008 -#define SR_MASK_IEO 0x00000010 -#define SR_MASK_KUO 0x00000020 -#define SR_MASK_IM 0x0000FF00 -#define SR_MASK_DS 0x00FF0000 -#define SR_MASK_RE 0x01000000 -#define SR_MASK_CU 0xF0000000 - -/* Cause register masks */ -#define CR_MASK_EXC 0x0000007C -#define CR_MASK_IP 0x0000FF00 -#define CR_MASK_CE 0x40000000 -#define CR_MASK_BD 0x80000000 - -#endif /* _ASM_REGDEF_H */ diff --git a/lib/CPUs/MIPS/bsp/examples/richards_benchmark.c b/lib/CPUs/MIPS/bsp/examples/richards_benchmark.c deleted file mode 100644 index f1fdfd0..0000000 --- a/lib/CPUs/MIPS/bsp/examples/richards_benchmark.c +++ /dev/null @@ -1,408 +0,0 @@ - -/* C version of the systems programming language benchmark -** Author: M. J. Jordan Cambridge Computer Laboratory. -** -** Modified by: M. Richards, Nov 1996 -** to be ANSI C and runnable on 64 bit machines + other minor changes -** Modified by: M. Richards, 20 Oct 1998 -** made minor corrections to improve ANSI compliance (suggested -** by David Levine) -** -** Compile with, say -** -** gcc -o bench bench.c -** -** or -** -** gcc -o bench100 -Dbench100 bench.c (for a version that obeys -** the main loop 100x more often) -*/ - -#include -#include - -#ifdef SMALL_PROBLEM_SIZE -#define Count 1000*1000 -#define Qpktcountval 2326389 -#define Holdcountval 930555 -#else -#define Count 10000*1000 -#define Qpktcountval 23263894 -#define Holdcountval 9305557 -#endif - - -#define TRUE 1 -#define FALSE 0 -#define MAXINT 32767 - -#define BUFSIZE 3 -#define I_IDLE 1 -#define I_WORK 2 -#define I_HANDLERA 3 -#define I_HANDLERB 4 -#define I_DEVA 5 -#define I_DEVB 6 -#define PKTBIT 1 -#define WAITBIT 2 -#define HOLDBIT 4 -#define NOTPKTBIT !1 -#define NOTWAITBIT !2 -#define NOTHOLDBIT 0XFFFB - -#define S_RUN 0 -#define S_RUNPKT 1 -#define S_WAIT 2 -#define S_WAITPKT 3 -#define S_HOLD 4 -#define S_HOLDPKT 5 -#define S_HOLDWAIT 6 -#define S_HOLDWAITPKT 7 - -#define K_DEV 1000 -#define K_WORK 1001 - -struct packet -{ - struct packet *p_link; - int p_id; - int p_kind; - int p_a1; - char p_a2[4]; -}; - -struct task -{ - struct task *t_link; - int t_id; - int t_pri; - struct packet *t_wkq; - int t_state; - struct task *(*t_fn)(struct packet *); - long t_v1; - long t_v2; -}; - -char alphabet[28] = "0ABCDEFGHIJKLMNOPQRSTUVWXYZ"; -struct task *tasktab[11] = {0,0,0,0,0,0,0,0,0,0,0}; -struct task *tasklist = 0; -struct task *tcb; -long taskid; -long v1; -long v2; -int qpktcount = 0; -int holdcount = 0; -int tracing = 1; -int layout = 0; - -void append(struct packet *pkt, struct packet *ptr); - -void createtask(int id, - int pri, - struct packet *wkq, - int state, - struct task *(*fn)(struct packet *), - long v1, - long v2) -{ - struct task *t = (struct task *)malloc(sizeof(struct task)); - - tasktab[id] = t; - t->t_link = tasklist; - t->t_id = id; - t->t_pri = pri; - t->t_wkq = wkq; - t->t_state = state; - t->t_fn = fn; - t->t_v1 = v1; - t->t_v2 = v2; - tasklist = t; -} - -struct packet *pkt(struct packet *link, int id, int kind) -{ - int i; - struct packet *p = (struct packet *)malloc(sizeof(struct packet)); - - for (i=0; i<=BUFSIZE; i++) - p->p_a2[i] = 0; - - p->p_link = link; - p->p_id = id; - p->p_kind = kind; - p->p_a1 = 0; - - return (p); -} - -void trace(char a) -{ - if ( --layout <= 0 ) - { - printf("\n"); - layout = 50; - } - - printf("%c", a); -} - -void schedule() -{ - while ( tcb != 0 ) - { - struct packet *pkt; - struct task *newtcb; - - pkt=0; - - switch ( tcb->t_state ) - { - case S_WAITPKT: - pkt = tcb->t_wkq; - tcb->t_wkq = pkt->p_link; - tcb->t_state = tcb->t_wkq == 0 ? S_RUN : S_RUNPKT; - - case S_RUN: - case S_RUNPKT: - taskid = tcb->t_id; - v1 = tcb->t_v1; - v2 = tcb->t_v2; - if (tracing==TRUE) trace(taskid+'0'); - - newtcb = (*(tcb->t_fn))(pkt); - tcb->t_v1 = v1; - tcb->t_v2 = v2; - tcb = newtcb; - break; - - case S_WAIT: - case S_HOLD: - case S_HOLDPKT: - case S_HOLDWAIT: - case S_HOLDWAITPKT: - tcb = tcb->t_link; - break; - - default: - return; - } - } -} - -struct task *Wait(void) -{ - tcb->t_state |= WAITBIT; - return (tcb); -} - -struct task *holdself(void) -{ - ++holdcount; - tcb->t_state |= HOLDBIT; - return (tcb->t_link) ; -} - -struct task *findtcb(int id) -{ - struct task *t = 0; - - if (1<=id && id<=(long)10) - t = tasktab[id]; - if (t==0) printf("\nBad task id %d\n", id); - return(t); -} - -struct task *release(int id) -{ - struct task *t; - - t = findtcb(id); - if ( t==0 ) return (0); - - t->t_state &= NOTHOLDBIT; - if ( t->t_pri > tcb->t_pri ) return (t); - - return (tcb) ; -} - - -struct task *qpkt(struct packet *pkt) -{ - struct task *t; - - t = findtcb(pkt->p_id); - if (t==0) return (t); - - qpktcount++; - - pkt->p_link = 0; - pkt->p_id = taskid; - - if (t->t_wkq==0) - { - t->t_wkq = pkt; - t->t_state |= PKTBIT; - if (t->t_pri > tcb->t_pri) return (t); - } - else - { - append(pkt, (struct packet *)&(t->t_wkq)); - } - - return (tcb); -} - -struct task *idlefn(struct packet *pkt) -{ - --v2; - if ( v2==0 ) return ( holdself() ); - - if ( (v1&1) == 0 ) - { - v1 = ( v1>>1) & MAXINT; - return ( release(I_DEVA) ); - } - else - { - v1 = ( (v1>>1) & MAXINT) ^ 0XD008; - return ( release(I_DEVB) ); - } -} - -struct task *workfn(struct packet *pkt) -{ - if ( pkt==0 ) return ( Wait() ); - else - { - int i; - - v1 = I_HANDLERA + I_HANDLERB - v1; - pkt->p_id = v1; - - pkt->p_a1 = 0; - for (i=0; i<=BUFSIZE; i++) - { - v2++; - if ( v2 > 26 ) v2 = 1; - (pkt->p_a2)[i] = alphabet[v2]; - } - return ( qpkt(pkt) ); - } -} - -struct task *handlerfn(struct packet *pkt) -{ - if ( pkt!=0) append(pkt, - (struct packet *)(pkt->p_kind==K_WORK ? &v1 : &v2)); - - if ( v1!=0 ) - { - int count; - struct packet *workpkt = (struct packet *)v1; - count = workpkt->p_a1; - - if ( count > BUFSIZE ) - { - v1 = (long)(((struct packet *)v1)->p_link); - return ( qpkt(workpkt) ); - } - - if ( v2!=0 ) - { - struct packet *devpkt; - - devpkt = (struct packet *)v2; - v2 = (long)(((struct packet *)v2)->p_link); - devpkt->p_a1 = workpkt->p_a2[count]; - workpkt->p_a1 = count+1; - return( qpkt(devpkt) ); - } - } - return ( Wait() ); -} - -struct task *devfn(struct packet *pkt) -{ - if ( pkt==0 ) - { - if ( v1==0 ) return ( Wait() ); - pkt = (struct packet *)v1; - v1 = 0; - return ( qpkt(pkt) ); - } - else - { - v1 = (long)pkt; - if (tracing==TRUE) trace(pkt->p_a1); - return ( holdself() ); - } -} - -void append(struct packet *pkt, struct packet *ptr) -{ - pkt->p_link = 0; - - while ( ptr->p_link ) ptr = ptr->p_link; - - ptr->p_link = pkt; -} - -int main() -{ - struct packet *wkq = 0; - int retval; - - printf("Bench mark starting\n"); - - createtask(I_IDLE, 0, wkq, S_RUN, idlefn, 1, Count); - - wkq = pkt(0, 0, K_WORK); - wkq = pkt(wkq, 0, K_WORK); - - createtask(I_WORK, 1000, wkq, S_WAITPKT, workfn, I_HANDLERA, 0); - - wkq = pkt(0, I_DEVA, K_DEV); - wkq = pkt(wkq, I_DEVA, K_DEV); - wkq = pkt(wkq, I_DEVA, K_DEV); - - createtask(I_HANDLERA, 2000, wkq, S_WAITPKT, handlerfn, 0, 0); - - wkq = pkt(0, I_DEVB, K_DEV); - wkq = pkt(wkq, I_DEVB, K_DEV); - wkq = pkt(wkq, I_DEVB, K_DEV); - - createtask(I_HANDLERB, 3000, wkq, S_WAITPKT, handlerfn, 0, 0); - - wkq = 0; - createtask(I_DEVA, 4000, wkq, S_WAIT, devfn, 0, 0); - createtask(I_DEVB, 5000, wkq, S_WAIT, devfn, 0, 0); - - tcb = tasklist; - - qpktcount = holdcount = 0; - - printf("Starting\n"); - - tracing = FALSE; - layout = 0; - - schedule(); - - printf("finished\n"); - - printf("qpkt count = %d holdcount = %d\n", - qpktcount, holdcount); - - printf("These results are "); - if (qpktcount == Qpktcountval && holdcount == Holdcountval) { - printf("correct"); - retval = 0; - } else { - printf("incorrect"); - retval = 1; - } - - printf("\nend of run\n"); - return retval; -} - diff --git a/lib/CPUs/MIPS/bsp/examples/rmd160.c b/lib/CPUs/MIPS/bsp/examples/rmd160.c deleted file mode 100644 index 8b0f2c7..0000000 --- a/lib/CPUs/MIPS/bsp/examples/rmd160.c +++ /dev/null @@ -1,294 +0,0 @@ -/********************************************************************\ - * - * FILE: rmd160.c - * - * CONTENTS: A sample C-implementation of the RIPEMD-160 - * hash-function. - * TARGET: any computer with an ANSI C compiler - * - * AUTHOR: Antoon Bosselaers, ESAT-COSIC - * DATE: 1 March 1996 - * VERSION: 1.0 - * - * Copyright (c) Katholieke Universiteit Leuven - * 1996, All Rights Reserved - * - * Conditions for use of the RIPEMD-160 Software - * - * The RIPEMD-160 software is freely available for use under the terms and - * conditions described hereunder, which shall be deemed to be accepted by - * any user of the software and applicable on any use of the software: - * - * 1. K.U.Leuven Department of Electrical Engineering-ESAT/COSIC shall for - * all purposes be considered the owner of the RIPEMD-160 software and of - * all copyright, trade secret, patent or other intellectual property - * rights therein. - * 2. The RIPEMD-160 software is provided on an "as is" basis without - * warranty of any sort, express or implied. K.U.Leuven makes no - * representation that the use of the software will not infringe any - * patent or proprietary right of third parties. User will indemnify - * K.U.Leuven and hold K.U.Leuven harmless from any claims or liabilities - * which may arise as a result of its use of the software. In no - * circumstances K.U.Leuven R&D will be held liable for any deficiency, - * fault or other mishappening with regard to the use or performance of - * the software. - * 3. User agrees to give due credit to K.U.Leuven in scientific publications - * or communications in relation with the use of the RIPEMD-160 software - * as follows: RIPEMD-160 software written by Antoon Bosselaers, - * available at http://www.esat.kuleuven.be/~cosicart/ps/AB-9601/. - * -\********************************************************************/ - -/* header files */ -#include -#include -#include -#include "rmd160.h" - -/********************************************************************/ - -void MDinit(dword *MDbuf) -{ - MDbuf[0] = 0x67452301UL; - MDbuf[1] = 0xefcdab89UL; - MDbuf[2] = 0x98badcfeUL; - MDbuf[3] = 0x10325476UL; - MDbuf[4] = 0xc3d2e1f0UL; - - return; -} - -/********************************************************************/ - -void compress(dword *MDbuf, dword *X) -{ - dword aa = MDbuf[0], bb = MDbuf[1], cc = MDbuf[2], - dd = MDbuf[3], ee = MDbuf[4]; - dword aaa = MDbuf[0], bbb = MDbuf[1], ccc = MDbuf[2], - ddd = MDbuf[3], eee = MDbuf[4]; - - /* round 1 */ - FF(aa, bb, cc, dd, ee, X[ 0], 11); - FF(ee, aa, bb, cc, dd, X[ 1], 14); - FF(dd, ee, aa, bb, cc, X[ 2], 15); - FF(cc, dd, ee, aa, bb, X[ 3], 12); - FF(bb, cc, dd, ee, aa, X[ 4], 5); - FF(aa, bb, cc, dd, ee, X[ 5], 8); - FF(ee, aa, bb, cc, dd, X[ 6], 7); - FF(dd, ee, aa, bb, cc, X[ 7], 9); - FF(cc, dd, ee, aa, bb, X[ 8], 11); - FF(bb, cc, dd, ee, aa, X[ 9], 13); - FF(aa, bb, cc, dd, ee, X[10], 14); - FF(ee, aa, bb, cc, dd, X[11], 15); - FF(dd, ee, aa, bb, cc, X[12], 6); - FF(cc, dd, ee, aa, bb, X[13], 7); - FF(bb, cc, dd, ee, aa, X[14], 9); - FF(aa, bb, cc, dd, ee, X[15], 8); - - /* round 2 */ - GG(ee, aa, bb, cc, dd, X[ 7], 7); - GG(dd, ee, aa, bb, cc, X[ 4], 6); - GG(cc, dd, ee, aa, bb, X[13], 8); - GG(bb, cc, dd, ee, aa, X[ 1], 13); - GG(aa, bb, cc, dd, ee, X[10], 11); - GG(ee, aa, bb, cc, dd, X[ 6], 9); - GG(dd, ee, aa, bb, cc, X[15], 7); - GG(cc, dd, ee, aa, bb, X[ 3], 15); - GG(bb, cc, dd, ee, aa, X[12], 7); - GG(aa, bb, cc, dd, ee, X[ 0], 12); - GG(ee, aa, bb, cc, dd, X[ 9], 15); - GG(dd, ee, aa, bb, cc, X[ 5], 9); - GG(cc, dd, ee, aa, bb, X[ 2], 11); - GG(bb, cc, dd, ee, aa, X[14], 7); - GG(aa, bb, cc, dd, ee, X[11], 13); - GG(ee, aa, bb, cc, dd, X[ 8], 12); - - /* round 3 */ - HH(dd, ee, aa, bb, cc, X[ 3], 11); - HH(cc, dd, ee, aa, bb, X[10], 13); - HH(bb, cc, dd, ee, aa, X[14], 6); - HH(aa, bb, cc, dd, ee, X[ 4], 7); - HH(ee, aa, bb, cc, dd, X[ 9], 14); - HH(dd, ee, aa, bb, cc, X[15], 9); - HH(cc, dd, ee, aa, bb, X[ 8], 13); - HH(bb, cc, dd, ee, aa, X[ 1], 15); - HH(aa, bb, cc, dd, ee, X[ 2], 14); - HH(ee, aa, bb, cc, dd, X[ 7], 8); - HH(dd, ee, aa, bb, cc, X[ 0], 13); - HH(cc, dd, ee, aa, bb, X[ 6], 6); - HH(bb, cc, dd, ee, aa, X[13], 5); - HH(aa, bb, cc, dd, ee, X[11], 12); - HH(ee, aa, bb, cc, dd, X[ 5], 7); - HH(dd, ee, aa, bb, cc, X[12], 5); - - /* round 4 */ - II(cc, dd, ee, aa, bb, X[ 1], 11); - II(bb, cc, dd, ee, aa, X[ 9], 12); - II(aa, bb, cc, dd, ee, X[11], 14); - II(ee, aa, bb, cc, dd, X[10], 15); - II(dd, ee, aa, bb, cc, X[ 0], 14); - II(cc, dd, ee, aa, bb, X[ 8], 15); - II(bb, cc, dd, ee, aa, X[12], 9); - II(aa, bb, cc, dd, ee, X[ 4], 8); - II(ee, aa, bb, cc, dd, X[13], 9); - II(dd, ee, aa, bb, cc, X[ 3], 14); - II(cc, dd, ee, aa, bb, X[ 7], 5); - II(bb, cc, dd, ee, aa, X[15], 6); - II(aa, bb, cc, dd, ee, X[14], 8); - II(ee, aa, bb, cc, dd, X[ 5], 6); - II(dd, ee, aa, bb, cc, X[ 6], 5); - II(cc, dd, ee, aa, bb, X[ 2], 12); - - /* round 5 */ - JJ(bb, cc, dd, ee, aa, X[ 4], 9); - JJ(aa, bb, cc, dd, ee, X[ 0], 15); - JJ(ee, aa, bb, cc, dd, X[ 5], 5); - JJ(dd, ee, aa, bb, cc, X[ 9], 11); - JJ(cc, dd, ee, aa, bb, X[ 7], 6); - JJ(bb, cc, dd, ee, aa, X[12], 8); - JJ(aa, bb, cc, dd, ee, X[ 2], 13); - JJ(ee, aa, bb, cc, dd, X[10], 12); - JJ(dd, ee, aa, bb, cc, X[14], 5); - JJ(cc, dd, ee, aa, bb, X[ 1], 12); - JJ(bb, cc, dd, ee, aa, X[ 3], 13); - JJ(aa, bb, cc, dd, ee, X[ 8], 14); - JJ(ee, aa, bb, cc, dd, X[11], 11); - JJ(dd, ee, aa, bb, cc, X[ 6], 8); - JJ(cc, dd, ee, aa, bb, X[15], 5); - JJ(bb, cc, dd, ee, aa, X[13], 6); - - /* parallel round 1 */ - JJJ(aaa, bbb, ccc, ddd, eee, X[ 5], 8); - JJJ(eee, aaa, bbb, ccc, ddd, X[14], 9); - JJJ(ddd, eee, aaa, bbb, ccc, X[ 7], 9); - JJJ(ccc, ddd, eee, aaa, bbb, X[ 0], 11); - JJJ(bbb, ccc, ddd, eee, aaa, X[ 9], 13); - JJJ(aaa, bbb, ccc, ddd, eee, X[ 2], 15); - JJJ(eee, aaa, bbb, ccc, ddd, X[11], 15); - JJJ(ddd, eee, aaa, bbb, ccc, X[ 4], 5); - JJJ(ccc, ddd, eee, aaa, bbb, X[13], 7); - JJJ(bbb, ccc, ddd, eee, aaa, X[ 6], 7); - JJJ(aaa, bbb, ccc, ddd, eee, X[15], 8); - JJJ(eee, aaa, bbb, ccc, ddd, X[ 8], 11); - JJJ(ddd, eee, aaa, bbb, ccc, X[ 1], 14); - JJJ(ccc, ddd, eee, aaa, bbb, X[10], 14); - JJJ(bbb, ccc, ddd, eee, aaa, X[ 3], 12); - JJJ(aaa, bbb, ccc, ddd, eee, X[12], 6); - - /* parallel round 2 */ - III(eee, aaa, bbb, ccc, ddd, X[ 6], 9); - III(ddd, eee, aaa, bbb, ccc, X[11], 13); - III(ccc, ddd, eee, aaa, bbb, X[ 3], 15); - III(bbb, ccc, ddd, eee, aaa, X[ 7], 7); - III(aaa, bbb, ccc, ddd, eee, X[ 0], 12); - III(eee, aaa, bbb, ccc, ddd, X[13], 8); - III(ddd, eee, aaa, bbb, ccc, X[ 5], 9); - III(ccc, ddd, eee, aaa, bbb, X[10], 11); - III(bbb, ccc, ddd, eee, aaa, X[14], 7); - III(aaa, bbb, ccc, ddd, eee, X[15], 7); - III(eee, aaa, bbb, ccc, ddd, X[ 8], 12); - III(ddd, eee, aaa, bbb, ccc, X[12], 7); - III(ccc, ddd, eee, aaa, bbb, X[ 4], 6); - III(bbb, ccc, ddd, eee, aaa, X[ 9], 15); - III(aaa, bbb, ccc, ddd, eee, X[ 1], 13); - III(eee, aaa, bbb, ccc, ddd, X[ 2], 11); - - /* parallel round 3 */ - HHH(ddd, eee, aaa, bbb, ccc, X[15], 9); - HHH(ccc, ddd, eee, aaa, bbb, X[ 5], 7); - HHH(bbb, ccc, ddd, eee, aaa, X[ 1], 15); - HHH(aaa, bbb, ccc, ddd, eee, X[ 3], 11); - HHH(eee, aaa, bbb, ccc, ddd, X[ 7], 8); - HHH(ddd, eee, aaa, bbb, ccc, X[14], 6); - HHH(ccc, ddd, eee, aaa, bbb, X[ 6], 6); - HHH(bbb, ccc, ddd, eee, aaa, X[ 9], 14); - HHH(aaa, bbb, ccc, ddd, eee, X[11], 12); - HHH(eee, aaa, bbb, ccc, ddd, X[ 8], 13); - HHH(ddd, eee, aaa, bbb, ccc, X[12], 5); - HHH(ccc, ddd, eee, aaa, bbb, X[ 2], 14); - HHH(bbb, ccc, ddd, eee, aaa, X[10], 13); - HHH(aaa, bbb, ccc, ddd, eee, X[ 0], 13); - HHH(eee, aaa, bbb, ccc, ddd, X[ 4], 7); - HHH(ddd, eee, aaa, bbb, ccc, X[13], 5); - - /* parallel round 4 */ - GGG(ccc, ddd, eee, aaa, bbb, X[ 8], 15); - GGG(bbb, ccc, ddd, eee, aaa, X[ 6], 5); - GGG(aaa, bbb, ccc, ddd, eee, X[ 4], 8); - GGG(eee, aaa, bbb, ccc, ddd, X[ 1], 11); - GGG(ddd, eee, aaa, bbb, ccc, X[ 3], 14); - GGG(ccc, ddd, eee, aaa, bbb, X[11], 14); - GGG(bbb, ccc, ddd, eee, aaa, X[15], 6); - GGG(aaa, bbb, ccc, ddd, eee, X[ 0], 14); - GGG(eee, aaa, bbb, ccc, ddd, X[ 5], 6); - GGG(ddd, eee, aaa, bbb, ccc, X[12], 9); - GGG(ccc, ddd, eee, aaa, bbb, X[ 2], 12); - GGG(bbb, ccc, ddd, eee, aaa, X[13], 9); - GGG(aaa, bbb, ccc, ddd, eee, X[ 9], 12); - GGG(eee, aaa, bbb, ccc, ddd, X[ 7], 5); - GGG(ddd, eee, aaa, bbb, ccc, X[10], 15); - GGG(ccc, ddd, eee, aaa, bbb, X[14], 8); - - /* parallel round 5 */ - FFF(bbb, ccc, ddd, eee, aaa, X[12] , 8); - FFF(aaa, bbb, ccc, ddd, eee, X[15] , 5); - FFF(eee, aaa, bbb, ccc, ddd, X[10] , 12); - FFF(ddd, eee, aaa, bbb, ccc, X[ 4] , 9); - FFF(ccc, ddd, eee, aaa, bbb, X[ 1] , 12); - FFF(bbb, ccc, ddd, eee, aaa, X[ 5] , 5); - FFF(aaa, bbb, ccc, ddd, eee, X[ 8] , 14); - FFF(eee, aaa, bbb, ccc, ddd, X[ 7] , 6); - FFF(ddd, eee, aaa, bbb, ccc, X[ 6] , 8); - FFF(ccc, ddd, eee, aaa, bbb, X[ 2] , 13); - FFF(bbb, ccc, ddd, eee, aaa, X[13] , 6); - FFF(aaa, bbb, ccc, ddd, eee, X[14] , 5); - FFF(eee, aaa, bbb, ccc, ddd, X[ 0] , 15); - FFF(ddd, eee, aaa, bbb, ccc, X[ 3] , 13); - FFF(ccc, ddd, eee, aaa, bbb, X[ 9] , 11); - FFF(bbb, ccc, ddd, eee, aaa, X[11] , 11); - - /* combine results */ - ddd += cc + MDbuf[1]; /* final result for MDbuf[0] */ - MDbuf[1] = MDbuf[2] + dd + eee; - MDbuf[2] = MDbuf[3] + ee + aaa; - MDbuf[3] = MDbuf[4] + aa + bbb; - MDbuf[4] = MDbuf[0] + bb + ccc; - MDbuf[0] = ddd; - - return; -} - -/********************************************************************/ - -void MDfinish(dword *MDbuf, byte *strptr, dword lswlen, dword mswlen) -{ - unsigned int i; /* counter */ - dword X[16]; /* message words */ - - memset(X, 0, 16*sizeof(dword)); - - /* put bytes from strptr into X */ - for (i=0; i<(lswlen&63); i++) { - /* byte i goes into word X[i div 4] at pos. 8*(i mod 4) */ - X[i>>2] ^= (dword) *strptr++ << (8 * (i&3)); - } - - /* append the bit m_n == 1 */ - X[(lswlen>>2)&15] ^= (dword)1 << (8*(lswlen&3) + 7); - - if ((lswlen & 63) > 55) { - /* length goes to next block */ - compress(MDbuf, X); - memset(X, 0, 16*sizeof(dword)); - } - - /* append length in bits*/ - X[14] = lswlen << 3; - X[15] = (lswlen >> 29) | (mswlen << 3); - compress(MDbuf, X); - - return; -} - -/************************ end of file rmd160.c **********************/ - diff --git a/lib/CPUs/MIPS/bsp/examples/rmd160.h b/lib/CPUs/MIPS/bsp/examples/rmd160.h deleted file mode 100644 index 70a33a6..0000000 --- a/lib/CPUs/MIPS/bsp/examples/rmd160.h +++ /dev/null @@ -1,154 +0,0 @@ -/********************************************************************\ - * - * FILE: rmd160.h - * - * CONTENTS: Header file for a sample C-implementation of the - * RIPEMD-160 hash-function. - * TARGET: any computer with an ANSI C compiler - * - * AUTHOR: Antoon Bosselaers, ESAT-COSIC - * DATE: 1 March 1996 - * VERSION: 1.0 - * - * Copyright (c) Katholieke Universiteit Leuven - * 1996, All Rights Reserved - * - * Conditions for use of the RIPEMD-160 Software - * - * The RIPEMD-160 software is freely available for use under the terms and - * conditions described hereunder, which shall be deemed to be accepted by - * any user of the software and applicable on any use of the software: - * - * 1. K.U.Leuven Department of Electrical Engineering-ESAT/COSIC shall for - * all purposes be considered the owner of the RIPEMD-160 software and of - * all copyright, trade secret, patent or other intellectual property - * rights therein. - * 2. The RIPEMD-160 software is provided on an "as is" basis without - * warranty of any sort, express or implied. K.U.Leuven makes no - * representation that the use of the software will not infringe any - * patent or proprietary right of third parties. User will indemnify - * K.U.Leuven and hold K.U.Leuven harmless from any claims or liabilities - * which may arise as a result of its use of the software. In no - * circumstances K.U.Leuven R&D will be held liable for any deficiency, - * fault or other mishappening with regard to the use or performance of - * the software. - * 3. User agrees to give due credit to K.U.Leuven in scientific publications - * or communications in relation with the use of the RIPEMD-160 software - * as follows: RIPEMD-160 software written by Antoon Bosselaers, - * available at http://www.esat.kuleuven.be/~cosicart/ps/AB-9601/. - * -\********************************************************************/ - -#ifndef RMD160H /* make sure this file is read only once */ -#define RMD160H - -/********************************************************************/ - -/* typedef 8 and 32 bit types, resp. */ -/* adapt these, if necessary, - for your operating system and compiler */ -typedef unsigned char byte; -typedef unsigned long dword; - - -/********************************************************************/ - -/* macro definitions */ - -/* collect four bytes into one word: */ -#define BYTES_TO_DWORD(strptr) \ - (((dword) *((strptr)+3) << 24) | \ - ((dword) *((strptr)+2) << 16) | \ - ((dword) *((strptr)+1) << 8) | \ - ((dword) *(strptr))) - -/* ROL(x, n) cyclically rotates x over n bits to the left */ -/* x must be of an unsigned 32 bits type and 0 <= n < 32. */ -#define ROL(x, n) (((x) << (n)) | ((x) >> (32-(n)))) - -/* the five basic functions F(), G() and H() */ -#define F(x, y, z) ((x) ^ (y) ^ (z)) -#define G(x, y, z) (((x) & (y)) | (~(x) & (z))) -#define H(x, y, z) (((x) | ~(y)) ^ (z)) -#define I(x, y, z) (((x) & (z)) | ((y) & ~(z))) -#define J(x, y, z) ((x) ^ ((y) | ~(z))) - -/* the ten basic operations FF() through III() */ -#define FF(a, b, c, d, e, x, s) {\ - (a) += F((b), (c), (d)) + (x);\ - (a) = ROL((a), (s)) + (e);\ - (c) = ROL((c), 10);\ - } -#define GG(a, b, c, d, e, x, s) {\ - (a) += G((b), (c), (d)) + (x) + 0x5a827999UL;\ - (a) = ROL((a), (s)) + (e);\ - (c) = ROL((c), 10);\ - } -#define HH(a, b, c, d, e, x, s) {\ - (a) += H((b), (c), (d)) + (x) + 0x6ed9eba1UL;\ - (a) = ROL((a), (s)) + (e);\ - (c) = ROL((c), 10);\ - } -#define II(a, b, c, d, e, x, s) {\ - (a) += I((b), (c), (d)) + (x) + 0x8f1bbcdcUL;\ - (a) = ROL((a), (s)) + (e);\ - (c) = ROL((c), 10);\ - } -#define JJ(a, b, c, d, e, x, s) {\ - (a) += J((b), (c), (d)) + (x) + 0xa953fd4eUL;\ - (a) = ROL((a), (s)) + (e);\ - (c) = ROL((c), 10);\ - } -#define FFF(a, b, c, d, e, x, s) {\ - (a) += F((b), (c), (d)) + (x);\ - (a) = ROL((a), (s)) + (e);\ - (c) = ROL((c), 10);\ - } -#define GGG(a, b, c, d, e, x, s) {\ - (a) += G((b), (c), (d)) + (x) + 0x7a6d76e9UL;\ - (a) = ROL((a), (s)) + (e);\ - (c) = ROL((c), 10);\ - } -#define HHH(a, b, c, d, e, x, s) {\ - (a) += H((b), (c), (d)) + (x) + 0x6d703ef3UL;\ - (a) = ROL((a), (s)) + (e);\ - (c) = ROL((c), 10);\ - } -#define III(a, b, c, d, e, x, s) {\ - (a) += I((b), (c), (d)) + (x) + 0x5c4dd124UL;\ - (a) = ROL((a), (s)) + (e);\ - (c) = ROL((c), 10);\ - } -#define JJJ(a, b, c, d, e, x, s) {\ - (a) += J((b), (c), (d)) + (x) + 0x50a28be6UL;\ - (a) = ROL((a), (s)) + (e);\ - (c) = ROL((c), 10);\ - } - -/********************************************************************/ - -/* function prototypes */ - -void MDinit(dword *MDbuf); -/* - * initializes MDbuffer to "magic constants" - */ - -void compress(dword *MDbuf, dword *X); -/* - * the compression function. - * transforms MDbuf using message bytes X[0] through X[15] - */ - -void MDfinish(dword *MDbuf, byte *strptr, dword lswlen, dword mswlen); -/* - * puts bytes from strptr into X and pad out; appends length - * and finally, compresses the last block(s) - * note: length in bits == 8 * (lswlen + 2^32 mswlen). - * note: there are (lswlen mod 64) bytes left in strptr. - */ - -#endif /* RMD160H */ - -/*********************** end of file rmd160.h ***********************/ - diff --git a/lib/CPUs/MIPS/bsp/examples/rmd160_test.c b/lib/CPUs/MIPS/bsp/examples/rmd160_test.c deleted file mode 100644 index d46b86e..0000000 --- a/lib/CPUs/MIPS/bsp/examples/rmd160_test.c +++ /dev/null @@ -1,113 +0,0 @@ -#include -#include -#include -#include "libsys.h" - -#include "rmd160.h" - -#ifndef RMDsize -#define RMDsize 160 -#endif - -byte *RMD(byte *message) -/* - * returns RMD(message) - * message should be a string terminated by '\0' - */ -{ - dword MDbuf[RMDsize/32]; /* contains (A, B, C, D(, E)) */ - static byte hashcode[RMDsize/8]; /* for final hash-value */ - dword X[16]; /* current 16-word chunk */ - unsigned int i; /* counter */ - dword length; /* length in bytes of message */ - dword nbytes; /* # of bytes not yet processed */ - - /* initialize */ - MDinit(MDbuf); - length = (dword)strlen((char *)message); - - /* process message in 16-word chunks */ - for (nbytes=length; nbytes > 63; nbytes-=64) { - for (i=0; i<16; i++) { - X[i] = BYTES_TO_DWORD(message); - message += 4; - } - compress(MDbuf, X); - } /* length mod 64 bytes left */ - - /* finish: */ - MDfinish(MDbuf, message, length, 0); - - for (i=0; i>2]; /* implicit cast to byte */ - hashcode[i+1] = (MDbuf[i>>2] >> 8); /* extracts the 8 least */ - hashcode[i+2] = (MDbuf[i>>2] >> 16); /* significant bits. */ - hashcode[i+3] = (MDbuf[i>>2] >> 24); - } - - return (byte *)hashcode; -} - -#define MSG_SIZE (1*1024*1024) // Bit -#define TIME_STEP 2 - -char msg[MSG_SIZE/8+1]; -byte hashref[] = {0xFC,0x20,0x7B,0x84,0x40,0x1C,0x49,0x0B,0x8D,0x69,0x88,0xD2,0x49,0x20,0x01,0x90,0x41,0x77,0x72,0x59}; - -int main (void) -{ - int result, i, j, cnt; - byte *hashcode; - UINT32 start, stop; - - for (i=0; i < MSG_SIZE/8; i++) - msg[i] = 0x55; - - msg[i] = 0; - - setbuf(stdout, NULL); - - cnt = 0; - while(1) - { - while (start == time(NULL)); - - start = time(NULL); - stop = start + TIME_STEP; - - - while(1) - { - hashcode = RMD((byte *)msg); - cnt++; - - if (memcmp(hashcode, hashref, sizeof(hashref))) - { - printf("Error RipeMD-160!\n"); - printf("Hash expected: "); - for (i=0; i %d Mbit/s\n\n", cnt, MSG_SIZE/(1024*1024), TIME_STEP, cnt*MSG_SIZE/(1024*1024)/TIME_STEP); - cnt = 0; - break; - } - } - } - - return 0; -} - diff --git a/lib/CPUs/MIPS/bsp/examples/round.h b/lib/CPUs/MIPS/bsp/examples/round.h deleted file mode 100644 index 4dcbb58..0000000 --- a/lib/CPUs/MIPS/bsp/examples/round.h +++ /dev/null @@ -1,55 +0,0 @@ -/* +++Date last modified: 05-Jul-1997 */ - -/* -** rounding macros by Dave Knapp, Thad Smith, Jon Strayer, & Bob Stout -*/ - -#ifndef ROUND__H -#define ROUND__H - -#include - -#if defined(__cplusplus) && __cplusplus - -/* -** Safe C++ inline versions -*/ - -/* round to integer */ - -inline int iround(double x) -{ - return (int)floor(x + 0.5); -} - -/* round number n to d decimal points */ - -inline double fround(double n, unsigned d) -{ - return floor(n * pow(10., d) + .5) / pow(10., d); -} - -#else - -/* -** NOTE: These C macro versions are unsafe since arguments are referenced -** more than once. -** -** Avoid using these with expression arguments to be safe. -*/ - -/* -** round to integer -*/ - -#define iround(x) floor((x) + 0.5) - -/* -** round number n to d decimal points -*/ - -#define fround(n,d) (floor((n)*pow(10.,(d))+.5)/pow(10.,(d))) - -#endif - -#endif /* ROUND__H */ diff --git a/lib/CPUs/MIPS/bsp/examples/serdump.c b/lib/CPUs/MIPS/bsp/examples/serdump.c deleted file mode 100644 index 066d0ea..0000000 --- a/lib/CPUs/MIPS/bsp/examples/serdump.c +++ /dev/null @@ -1,83 +0,0 @@ -#include -#include -#include -#include -#include -#include -#include "libsys.h" - -#define BUF_SIZE 1024 -char buffer[BUF_SIZE]; -char rxbuf[BUF_SIZE]; -char * volatile pPtr_r; -char * volatile pPtr_w; -UINT32 volatile timeout_cnt; - -void handler3(void) -{ - volatile UINT32 *pUART_stat = (UINT32*)SYS_UART_STAT; - volatile UINT32 *pUART_data = (UINT32*)SYS_UART_DATA; - - while((0x10 & *pUART_stat)) - { -/// sputs("w: "); print_word((int)pPtr_w); sputs("\n"); - if (pPtr_w == &buffer[BUF_SIZE-1]) - pPtr_w = buffer; - *(pPtr_w++) = *pUART_data; - timeout_cnt = 200; - - } - -} - -int main(int argc, char **argv) -{ - volatile UINT32 *pUART_stat = (UINT32*)SYS_UART_STAT; - unsigned char *fileData; - unsigned long file_len, state; - - pPtr_r = buffer; - pPtr_w = buffer; - interrupt_register(3, handler3); - interrupt_enable(3); - *pUART_stat |= (1 << 6); - setbuf(stderr, NULL); - - state = 0; - while(1) - { - fprintf(stdout,"Reading serial stream..\n"); - file_len = 0; - timeout_cnt = 20000000; - while(timeout_cnt--) - { - sleep(1); - } - while(pPtr_w != pPtr_r) - { -// sputs("r: "); print_word((int)pPtr_r); sputs("\n"); - if (pPtr_r == &buffer[BUF_SIZE-1]) - pPtr_r = buffer; - rxbuf[file_len++] = *(pPtr_r++); - } - if (file_len) - { - PrintBuffer8(rxbuf, 16, file_len); - } - switch(state) - { - case 0: - if (!memcmp(rxbuf, "CLIENT", file_len)) - { - fprintf(stdout,"Send response\n"); - fprintf(stderr,"SERVER"); - state = 1; - } - break; - default: - break; - } - } - - return 0; -} diff --git a/lib/CPUs/MIPS/bsp/examples/snipmath.h b/lib/CPUs/MIPS/bsp/examples/snipmath.h deleted file mode 100644 index 9ef5841..0000000 --- a/lib/CPUs/MIPS/bsp/examples/snipmath.h +++ /dev/null @@ -1,75 +0,0 @@ -/* +++Date last modified: 05-Jul-1997 */ - -/* -** SNIPMATH.H - Header file for SNIPPETS math functions and macros -*/ - -#ifndef SNIPMATH__H -#define SNIPMATH__H - -#include -#include "sniptype.h" -#include "round.h" - -/* -** Callable library functions begin here -*/ - -void SetBCDLen(int n); /* Bcdl.C */ -long BCDtoLong(char *BCDNum); /* Bcdl.C */ -void LongtoBCD(long num, char BCDNum[]); /* Bcdl.C */ -double bcd_to_double(void *buf, size_t len, /* Bcdd.C */ - int digits); -int double_to_bcd(double arg, char *buf, /* Bcdd.C */ - size_t length, size_t digits ); -DWORD ncomb1 (int n, int m); /* Combin.C */ -DWORD ncomb2 (int n, int m); /* Combin.C */ -void SolveCubic(double a, double b, double c, /* Cubic.C */ - double d, int *solutions, - double *x); -DWORD dbl2ulong(double t); /* Dbl2Long.C */ -long dbl2long(double t); /* Dbl2Long.C */ -double dround(double x); /* Dblround.C */ - -/* Use #defines for Permutations and Combinations -- Factoryl.C */ - -#define log10P(n,r) (log10factorial(n)-log10factorial((n)-(r))) -#define log10C(n,r) (log10P((n),(r))-log10factorial(r)) - -double log10factorial(double N); /* Factoryl.C */ - -double fibo(unsigned short term); /* Fibo.C */ -double frandom(int n); /* Frand.C */ -double ipow(double x, int n); /* Ipow.C */ -int ispow2(int x); /* Ispow2.C */ -long double ldfloor(long double a); /* Ldfloor.C */ -int initlogscale(long dmax, long rmax); /* Logscale.C */ -long logscale(long d); /* Logscale.C */ - -float MSBINToIEEE(float f); /* Msb2Ieee.C */ -float IEEEToMSBIN(float f); /* Msb2Ieee.C */ -int perm_index (char pit[], int size); /* Perm_Idx.C */ -int round_div(int n, int d); /* Rnd_Div.C */ -long round_ldiv(long n, long d); /* Rnd_Div.C */ -double rad2deg(double rad); /* Rad2Deg.C */ -double deg2rad(double deg); /* Rad2Deg.C */ - -#include "pi.h" -#ifndef PHI - #define PHI ((1.0+sqrt(5.0))/2.0) /* the golden number */ - #define INV_PHI (1.0/PHI) /* the golden ratio */ -#endif - -/* -** File: ISQRT.C -*/ - -struct int_sqrt { - unsigned sqrt, - frac; -}; - -void usqrt(unsigned long x, struct int_sqrt *q); - - -#endif /* SNIPMATH__H */ diff --git a/lib/CPUs/MIPS/bsp/examples/sniptype.h b/lib/CPUs/MIPS/bsp/examples/sniptype.h deleted file mode 100644 index 399935d..0000000 --- a/lib/CPUs/MIPS/bsp/examples/sniptype.h +++ /dev/null @@ -1,37 +0,0 @@ -/* +++Date last modified: 05-Jul-1997 */ - -/* -** SNIPTYPE.H - Include file for SNIPPETS data types and commonly used macros -*/ - -#ifndef SNIPTYPE__H -#define SNIPTYPE__H - -#include /* For free() */ -#include /* For NULL & strlen() */ - -typedef enum {Error_ = -1, Success_, False_ = 0, True_} Boolean_T; - -/*#if !defined(WIN32) && !defined(_WIN32) && !defined(__NT__) \ - && !defined(_WINDOWS) - #if !defined(OS2)*/ - typedef unsigned char BYTE; - typedef unsigned long DWORD; -/* #endif*/ - typedef unsigned short WORD; -/*#else - #define WIN32_LEAN_AND_MEAN - #define NOGDI - #define NOSERVICE - #undef INC_OLE1 - #undef INC_OLE2 - #include - #define HUGE - #endif*/ - -#define NUL '\0' -#define LAST_CHAR(s) (((char *)s)[strlen(s) - 1]) -#define TOBOOL(x) (!(!(x))) -#define FREE(p) (free(p),(p)=NULL) - -#endif /* SNIPTYPE__H */ diff --git a/lib/CPUs/MIPS/bsp/examples/specs/specs b/lib/CPUs/MIPS/bsp/examples/specs/specs deleted file mode 100644 index 3871b63..0000000 --- a/lib/CPUs/MIPS/bsp/examples/specs/specs +++ /dev/null @@ -1,147 +0,0 @@ -*asm: -%{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips32r2} %{mips64} %{mips16} %{mno-mips16:-no-mips16} %{mips3d} %{mno-mips3d:-no-mips3d} %{mdmx} %{mno-mdmx:-no-mdmx} %{mdsp} %{mno-dsp} %{mdspr2} %{mno-dspr2} %{msmartmips} %{mno-smartmips} %{mmt} %{mno-mt} %{mfix-vr4120} %{mfix-vr4130} %(subtarget_asm_optimizing_spec) %(subtarget_asm_debugging_spec) %{mabi=*} %{!mabi*: %(asm_abi_default_spec)} %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} %{mfp32} %{mfp64} %{mshared} %{mno-shared} %{msym32} %{mno-sym32} %{mtune=*} %{v} %(subtarget_asm_spec) - -*asm_debug: -%{gstabs*:--gstabs}%{!gstabs*:%{g*:--gdwarf2}} %{fdebug-prefix-map=*:--debug-prefix-map %*} - -*asm_final: - - -*asm_options: -%{--target-help:%:print-asm-header()} %a %Y %{c:%W{o*}%{!o*:-o %w%b%O}}%{!c:-o %d%w%u%O} - -*invoke_as: -%{!S:-o %|.s | - as %(asm_options) %m.s %A } - -*cpp: -%(subtarget_cpp_spec) - -*cpp_options: -%(cpp_unique_options) %1 %{m*} %{std*&ansi&trigraphs} %{W*&pedantic*} %{w} %{f*} %{g*:%{!g0:%{!fno-working-directory:-fworking-directory}}} %{O*} %{undef} %{save-temps:-fpch-preprocess} - -*cpp_debug_options: -%{d*} - -*cpp_unique_options: -%{C|CC:%{!E:%eGCC does not support -C or -CC without -E}} %{!Q:-quiet} %{nostdinc*} %{C} %{CC} %{v} %{I*&F*} %{P} %I %{MD:-MD %{!o:%b.d}%{o*:%.d%*}} %{MMD:-MMD %{!o:%b.d}%{o*:%.d%*}} %{M} %{MM} %{MF*} %{MG} %{MP} %{MQ*} %{MT*} %{!E:%{!M:%{!MM:%{!MT:%{!MQ:%{MD|MMD:%{o*:-MQ %*}}}}}}} %{remap} %{g3|ggdb3|gstabs3|gcoff3|gxcoff3|gvms3:-dD} %{H} %C %{D*&U*&A*} %{i*} %Z %i %{fmudflap:-D_MUDFLAP -include mf-runtime.h} %{fmudflapth:-D_MUDFLAP -D_MUDFLAPTH -include mf-runtime.h} %{E|M|MM:%W{o*}} - -*trad_capable_cpp: -cc1 -E %{traditional|ftraditional|traditional-cpp:-traditional-cpp} - -*cc1: -%{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} %{save-temps: } %(subtarget_cc1_spec) - -*cc1_options: -%{pg:%{fomit-frame-pointer:%e-pg and -fomit-frame-pointer are incompatible}} %1 %{!Q:-quiet} -dumpbase %B %{d*} %{m*} %{a*} %{c|S:%{o*:-auxbase-strip %*}%{!o*:-auxbase %b}}%{!c:%{!S:-auxbase %b}} %{g*} %{O*} %{W*&pedantic*} %{w} %{std*&ansi&trigraphs} %{v:-version} %{pg:-p} %{p} %{f*} %{undef} %{Qn:-fno-ident} %{--help:--help} %{--target-help:--target-help} %{--help=*:--help=%(VALUE)} %{!fsyntax-only:%{S:%W{o*}%{!o*:-o %b.s}}} %{fsyntax-only:-o %j} %{-param*} %{fmudflap|fmudflapth:-fno-builtin -fno-merge-constants} %{coverage:-fprofile-arcs -ftest-coverage} - -*cc1plus: - - -*link_gcc_c_sequence: -%G %L %G - -*link_ssp: -%{fstack-protector|fstack-protector-all:-lssp_nonshared -lssp} - -*endfile: -crtend%O%s crtn%O%s - -*link: -%(endian_spec) %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips32r2} %{mips64} %{bestGnum} %{shared} %{non_shared} - -*lib: ---start-group %o -lc --end-group - -*mfwrap: - %{static: %{fmudflap|fmudflapth: --wrap=malloc --wrap=free --wrap=calloc --wrap=realloc --wrap=mmap --wrap=munmap --wrap=alloca} %{fmudflapth: --wrap=pthread_create}} %{fmudflap|fmudflapth: --wrap=main} - -*mflib: -%{fmudflap|fmudflapth: -export-dynamic} - -*link_gomp: - - -*libgcc: --lgcc - -*startfile: -crti%O%s crtbegin%O%s - -*switches_need_spaces: - - -*cross_compile: -1 - -*version: -4.3.3 - -*multilib: -. !msoft-float !EL !EB;soft-float msoft-float !EL !EB;el !msoft-float EL !EB;eb !msoft-float !EL EB;soft-float/el msoft-float EL !EB;soft-float/eb msoft-float !EL EB; - -*multilib_defaults: -EL mips1 mabi=32 - -*multilib_extra: - - -*multilib_matches: -mel EL;meb EB;m4650 msingle-float;msoft-float msoft-float;EL EL;EB EB; - -*multilib_exclusions: - - -*multilib_options: -msoft-float EL/EB - -*linker: -collect2 - -*link_libgcc: -%D - -*md_exec_prefix: - - -*md_startfile_prefix: - - -*md_startfile_prefix_1: - - -*startfile_prefix_spec: - -*sysroot_spec: ---sysroot=%R - -*sysroot_suffix_spec: - - -*sysroot_hdrs_suffix_spec: - - -*subtarget_cc1_spec: - - -*subtarget_cpp_spec: - - -*subtarget_asm_optimizing_spec: -%{noasmopt:-O0} %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}} - -*subtarget_asm_debugging_spec: -%{g} %{g0} %{g1} %{g2} %{g3} %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} %{gcoff*:-mdebug} %{!gcoff*:-no-mdebug} - -*subtarget_asm_spec: - - -*asm_abi_default_spec: --mabi=32 - -*endian_spec: -%{!EB:%{!meb:-EL}} %{EB|meb:-EB} - -*link_command: -%{!fsyntax-only:%{!c:%{!M:%{!MM:%{!E:%{!S: %(linker) -T link/link.ld %l %{pie:-pie} %X %{o*} %{A} %{d} %{e*} %{m} %{N} %{n} %{r} %{s} %{t} %{u*} %{x} %{z} %{Z} %{!A:%{!nostdlib:%{!nostartfiles:%S}}} %{static:} %{L*} %(mfwrap) %(link_libgcc) %{lib} %{fopenmp|ftree-parallelize-loops=*:%:include(libgomp.spec)%(link_gomp)} %(mflib) %{fprofile-arcs|fprofile-generate|coverage:-lgcov} %{!nostdlib:%{!nodefaultlibs:%(link_ssp) %(link_gcc_c_sequence)}} %{!A:%{!nostdlib:%{!nostartfiles:%E}}} %{T*} }}}}}} - diff --git a/lib/CPUs/MIPS/bsp/examples/stanford.c b/lib/CPUs/MIPS/bsp/examples/stanford.c deleted file mode 100644 index 907477b..0000000 --- a/lib/CPUs/MIPS/bsp/examples/stanford.c +++ /dev/null @@ -1,1117 +0,0 @@ -/* stanford baby benchmark suite from john hennessy -- - -There are copies all around; the MIPS performance brief has up-to-date -numbers for a bunch of machines. BUT, these wouldn't be my first -choice. SPEC, the industry benchmark collection group, will probably -specify a new set of benchmarks shortly and release then right after -that. I imagine they will include espresso, gcc, and other large, but -public domain programs, for real things. - -here's bench.c - John Hennessy -*/ - - -/* This is a suite of benchmarks that are relatively short, both in program - size and execution time. It requires no input, and prints the execution - time for each program, using the system- dependent routine Getclock, - below, to find out the current CPU time. It does a rudimentary check to - make sure each program gets the right output. These programs were - gathered by John Hennessy and modified by Peter Nye. - -4.2 VERSION */ - -#include -#include -#include -#include - -#ifndef HZ -#define HZ 60 -#endif -#define nil 0 -#define false 0 -#define true 1 -#define bubblebase 1.61 -#define dnfbase 3.5 -#define permbase 1.75 -#define queensbase 1.83 -#define towersbase 2.39 -#define quickbase 1.92 -#define intmmbase 1.46 -#define treebase 2.5 -#define mmbase 0.0 -#define fpmmbase 2.92 -#define puzzlebase 0.5 -#define fftbase 0.0 -#define fpfftbase 4.44 - /* Towers */ -#define maxcells 18 - - /* Intmm, Mm */ -#define rowsize 40 - - /* Puzzle */ -#define size 511 -#define classmax 3 -#define typemax 12 -#define d 8 - - /* Bubble, Quick */ -#define sortelements 5000 -#define srtelements 500 - - /* fft */ -#define fftsize 256 -#define fftsize2 129 -/* -type */ - /* Perm */ -#define permrange 10 - - /* tree */ -struct node -{ - struct node *left, *right; - int val; -}; - -/* Towers *//* - discsizrange = 1..maxcells; */ -#define stackrange 3 -/* cellcursor = 0..maxcells; */ -struct element -{ - int discsize; - int next; -}; -/* emsgtype = packed array[1..15] of char; -*/ -/* Intmm, Mm *//* - index = 1 .. rowsize; - intmatrix = array [index,index] of integer; - realmatrix = array [index,index] of real; - */ -/* Puzzle *//* - piececlass = 0..classmax; - piecetype = 0..typemax; - position = 0..size; - */ -/* Bubble, Quick *//* - listsize = 0..sortelements; - sortarray = array [listsize] of integer; - */ - /* FFT */ -struct complex -{ - float rp, ip; -}; -/* - carray = array [1..fftsize] of complex ; - c2array = array [1..fftsize2] of complex ; -*/ - -float value; -float fixed, floated; - - /* global */ -int timer; -int xtimes[11]; -int seed; - - /* Perm */ -int permarray[permrange + 1]; -int pctr; - - /* tree */ -struct node *tree; - - /* Towers */ -int stack[stackrange + 1]; -struct element cellspace[maxcells + 1]; -int freelist, movesdone; - - /* Intmm, Mm */ -int ima[rowsize + 1][rowsize + 1], imb[rowsize + 1][rowsize + 1], - imr[rowsize + 1][rowsize + 1]; -float rma[rowsize + 1][rowsize + 1], rmb[rowsize + 1][rowsize + 1], - rmr[rowsize + 1][rowsize + 1]; - - /* Puzzle */ -int piececount[classmax + 1], - class[typemax + 1], - piecemax[typemax + 1], - puzzl[size + 1], p[typemax + 1][size + 1], n, kount; - - /* Bubble, Quick */ -int sortlist[sortelements + 1], biggest, littlest, top; - - /* FFT */ -struct complex z[fftsize + 1], w[fftsize + 1], e[fftsize2 + 1]; -float zr, zi; - -/* global procedures */ - -int -Getclock () -{ - struct tms rusage; - times (&rusage); - return ((60*rusage.tms_utime/HZ) * 50 / 3); -}; - -Initrand () -{ - seed = 74755; -}; - -int -Rand () -{ - seed = (seed * 1309 + 13849) & 65535; - return (seed); -}; - - - - /* Permutation program, heavily recursive, written by Denny Brown. */ - -Swap (a, b) - int *a, *b; -{ - int t; - t = *a; - *a = *b; - *b = t; -}; - -Initialize () -{ - int i; - for (i = 1; i <= 7; i++) - { - permarray[i] = i - 1; - }; -}; - -Permute (n) - int n; -{ /* permute */ - int k; - pctr = pctr + 1; - if (n != 1) - { - Permute (n - 1); - for (k = n - 1; k >= 1; k--) - { - Swap (&permarray[n], &permarray[k]); - Permute (n - 1); - Swap (&permarray[n], &permarray[k]); - }; - }; -} /* permute */ ; - -Perm () -{ /* Perm */ - int i; - pctr = 0; - for (i = 1; i <= 5; i++) - { - Initialize (); - Permute (7); - }; - if (pctr != 43300) - printf (" Error in Perm.\n"); -} /* Perm */ ; - - - - /* Program to Solve the Towers of Hanoi */ - -Error (emsg) - char *emsg; -{ - printf (" Error in Towers: %s\n", emsg); -}; - -Makenull (s) -{ - stack[s] = 0; -}; - -int -Getelement () -{ - int temp; - if (freelist > 0) - { - temp = freelist; - freelist = cellspace[freelist].next; - } - else - Error ("out of space "); - return (temp); -}; - -Push (i, s) - int i, s; -{ - int errorfound, localel; - errorfound = false; - if (stack[s] > 0) - if (cellspace[stack[s]].discsize <= i) - { - errorfound = true; - Error ("disc size error"); - }; - if (!errorfound) - { - localel = Getelement (); - cellspace[localel].next = stack[s]; - stack[s] = localel; - cellspace[localel].discsize = i; - } -}; - -Init (s, n) - int s, n; -{ - int discctr; - Makenull (s); - for (discctr = n; discctr >= 1; discctr--) - Push (discctr, s); -}; - -int -Pop (s) - int s; -{ - int temp, temp1; - if (stack[s] > 0) - { - temp1 = cellspace[stack[s]].discsize; - temp = cellspace[stack[s]].next; - cellspace[stack[s]].next = freelist; - freelist = stack[s]; - stack[s] = temp; - return (temp1); - } - else - Error ("nothing to pop "); -}; - -Move (s1, s2) - int s1, s2; -{ - Push (Pop (s1), s2); - movesdone = movesdone + 1; -}; - -tower (i, j, k) - int i, j, k; -{ - int other; - if (k == 1) - Move (i, j); - else - { - other = 6 - i - j; - tower (i, other, k - 1); - Move (i, j); - tower (other, j, k - 1); - } -}; - - -Towers () -{ /* Towers */ - int i; - for (i = 1; i <= maxcells; i++) - cellspace[i].next = i - 1; - freelist = maxcells; - Init (1, 14); - Makenull (2); - Makenull (3); - movesdone = 0; - tower (1, 2, 14); - if (movesdone != 16383) - printf (" Error in Towers.\n"); -}; /* Towers */ - - - /* The eight queens problem, solved 50 times. */ -/* - type - doubleboard = 2..16; - doublenorm = -7..7; - boardrange = 1..8; - aarray = array [boardrange] of boolean; - barray = array [doubleboard] of boolean; - carray = array [doublenorm] of boolean; - xarray = array [boardrange] of boardrange; -*/ - -Try (i, q, a, b, c, x) - int i, *q, a[], b[], c[], x[]; -{ - int j; - j = 0; - *q = false; - while ((!*q) && (j != 8)) - { - j = j + 1; - *q = false; - if (b[j] && a[i + j] && c[i - j + 7]) - { - x[i] = j; - b[j] = false; - a[i + j] = false; - c[i - j + 7] = false; - if (i < 8) - { - Try (i + 1, q, a, b, c, x); - if (!*q) - { - b[j] = true; - a[i + j] = true; - c[i - j + 7] = true; - } - } - else - *q = true; - } - } -}; - -Doit () -{ - int i, q; - int a[9], b[17], c[15], x[9]; - i = 0 - 7; - while (i <= 16) - { - if ((i >= 1) && (i <= 8)) - a[i] = true; - if (i >= 2) - b[i] = true; - if (i <= 7) - c[i + 7] = true; - i = i + 1; - }; - - Try (1, &q, b, a, c, x); - if (!q) - printf (" Error in Queens.\n"); -}; - -Queens () -{ - int i; - for (i = 1; i <= 50; i++) - Doit (); -}; - - /* Multiplies two integer matrices. */ - -Initmatrix (m) - int m[rowsize + 1][rowsize + 1]; -{ - int temp, i, j; - for (i = 1; i <= rowsize; i++) - for (j = 1; j <= rowsize; j++) - { - temp = Rand (); - m[i][j] = temp - (temp / 120) * 120 - 60; - } -}; - -Innerproduct (result, a, b, row, column) - int *result, a[rowsize + 1][rowsize + 1], b[rowsize + 1][rowsize + 1], - row, column; - /* computes the inner product of A[row,*] and B[*,column] */ -{ - int i; - *result = 0; - for (i = 1; i <= rowsize; i++) - *result = *result + a[row][i] * b[i][column]; -}; - -Intmm () -{ - int i, j; - Initrand (); - Initmatrix (ima); - Initmatrix (imb); - for (i = 1; i <= rowsize; i++) - for (j = 1; j <= rowsize; j++) - Innerproduct (&imr[i][j], ima, imb, i, j); -}; - - - /* Multiplies two real matrices. */ - -rInitmatrix (m) - float m[rowsize + 1][rowsize + 1]; -{ - int temp, i, j; - for (i = 1; i <= rowsize; i++) - for (j = 1; j <= rowsize; j++) - { - temp = Rand (); - m[i][j] = (temp - (temp / 120) * 120 - 60) / 3; - } -}; - -rInnerproduct (result, a, b, row, column) - float *result, a[rowsize + 1][rowsize + 1], b[rowsize + 1][rowsize + 1]; - int row, column; - /* computes the inner product of A[row,*] and B[*,column] */ -{ - int i; - *result = 0.0; - for (i = 1; i <= rowsize; i++) - *result = *result + a[row][i] * b[i][column]; -}; - -Mm () -{ - int i, j; - Initrand (); - rInitmatrix (rma); - rInitmatrix (rmb); - for (i = 1; i <= rowsize; i++) - for (j = 1; j <= rowsize; j++) - rInnerproduct (&rmr[i][j], rma, rmb, i, j); -}; - - - - - /* A compute-bound program from Forest Baskett. */ - -int -Fit (i, j) - int i, j; -{ - int k; - for (k = 0; k <= piecemax[i]; k++) - if (p[i][k]) - if (puzzl[j + k]) - return (false); - return (true); -}; - -int -Place (i, j) - int i, j; -{ - int k; - for (k = 0; k <= piecemax[i]; k++) - if (p[i][k]) - puzzl[j + k] = true; - piececount[class[i]] = piececount[class[i]] - 1; - for (k = j; k <= size; k++) - if (!puzzl[k]) - { - return (k); - }; - return (0); -}; - -Remove (i, j) - int i, j; -{ - int k; - for (k = 0; k <= piecemax[i]; k++) - if (p[i][k]) - puzzl[j + k] = false; - piececount[class[i]] = piececount[class[i]] + 1; -}; - -int -Trial (j) - int j; -{ - int i, k; - kount = kount + 1; - for (i = 0; i <= typemax; i++) - if (piececount[class[i]] != 0) - if (Fit (i, j)) - { - k = Place (i, j); - if (Trial (k) || (k == 0)) - { - return (true); - } - else - Remove (i, j); - }; - return (false); -}; - -Puzzle () -{ - int i, j, k, m; - for (m = 0; m <= size; m++) - puzzl[m] = true; - for (i = 1; i <= 5; i++) - for (j = 1; j <= 5; j++) - for (k = 1; k <= 5; k++) - puzzl[i + d * (j + d * k)] = false; - for (i = 0; i <= typemax; i++) - for (m = 0; m <= size; m++) - p[i][m] = false; - for (i = 0; i <= 3; i++) - for (j = 0; j <= 1; j++) - for (k = 0; k <= 0; k++) - p[0][i + d * (j + d * k)] = true; - class[0] = 0; - piecemax[0] = 3 + d * 1 + d * d * 0; - for (i = 0; i <= 1; i++) - for (j = 0; j <= 0; j++) - for (k = 0; k <= 3; k++) - p[1][i + d * (j + d * k)] = true; - class[1] = 0; - piecemax[1] = 1 + d * 0 + d * d * 3; - for (i = 0; i <= 0; i++) - for (j = 0; j <= 3; j++) - for (k = 0; k <= 1; k++) - p[2][i + d * (j + d * k)] = true; - class[2] = 0; - piecemax[2] = 0 + d * 3 + d * d * 1; - for (i = 0; i <= 1; i++) - for (j = 0; j <= 3; j++) - for (k = 0; k <= 0; k++) - p[3][i + d * (j + d * k)] = true; - class[3] = 0; - piecemax[3] = 1 + d * 3 + d * d * 0; - for (i = 0; i <= 3; i++) - for (j = 0; j <= 0; j++) - for (k = 0; k <= 1; k++) - p[4][i + d * (j + d * k)] = true; - class[4] = 0; - piecemax[4] = 3 + d * 0 + d * d * 1; - for (i = 0; i <= 0; i++) - for (j = 0; j <= 1; j++) - for (k = 0; k <= 3; k++) - p[5][i + d * (j + d * k)] = true; - class[5] = 0; - piecemax[5] = 0 + d * 1 + d * d * 3; - for (i = 0; i <= 2; i++) - for (j = 0; j <= 0; j++) - for (k = 0; k <= 0; k++) - p[6][i + d * (j + d * k)] = true; - class[6] = 1; - piecemax[6] = 2 + d * 0 + d * d * 0; - for (i = 0; i <= 0; i++) - for (j = 0; j <= 2; j++) - for (k = 0; k <= 0; k++) - p[7][i + d * (j + d * k)] = true; - class[7] = 1; - piecemax[7] = 0 + d * 2 + d * d * 0; - for (i = 0; i <= 0; i++) - for (j = 0; j <= 0; j++) - for (k = 0; k <= 2; k++) - p[8][i + d * (j + d * k)] = true; - class[8] = 1; - piecemax[8] = 0 + d * 0 + d * d * 2; - for (i = 0; i <= 1; i++) - for (j = 0; j <= 1; j++) - for (k = 0; k <= 0; k++) - p[9][i + d * (j + d * k)] = true; - class[9] = 2; - piecemax[9] = 1 + d * 1 + d * d * 0; - for (i = 0; i <= 1; i++) - for (j = 0; j <= 0; j++) - for (k = 0; k <= 1; k++) - p[10][i + d * (j + d * k)] = true; - class[10] = 2; - piecemax[10] = 1 + d * 0 + d * d * 1; - for (i = 0; i <= 0; i++) - for (j = 0; j <= 1; j++) - for (k = 0; k <= 1; k++) - p[11][i + d * (j + d * k)] = true; - class[11] = 2; - piecemax[11] = 0 + d * 1 + d * d * 1; - for (i = 0; i <= 1; i++) - for (j = 0; j <= 1; j++) - for (k = 0; k <= 1; k++) - p[12][i + d * (j + d * k)] = true; - class[12] = 3; - piecemax[12] = 1 + d * 1 + d * d * 1; - piececount[0] = 13; - piececount[1] = 3; - piececount[2] = 1; - piececount[3] = 1; - m = 1 + d * (1 + d * 1); - kount = 0; - if (Fit (0, m)) - n = Place (0, m); - else - printf ("Error1 in Puzzle\n"); - if (!Trial (n)) - printf ("Error2 in Puzzle.\n"); - else if (kount != 2005) - printf ("Error3 in Puzzle.\n"); -}; - - - - /* Sorts an array using quicksort */ - -Initarr () -{ - int i, temp; - Initrand (); - biggest = 0; - littlest = 0; - for (i = 1; i <= sortelements; i++) - { - temp = Rand (); - sortlist[i] = temp - (temp / 100000) * 100000 - 50000; - - if (sortlist[i] > biggest) - biggest = sortlist[i]; - else if (sortlist[i] < littlest) - littlest = sortlist[i]; - }; -}; - -Quicksort (a, l, r) - int a[], l, r; - /* quicksort the array A from start to finish */ -{ - int i, j, x, w; - - i = l; - j = r; - x = a[(l + r) / 2]; - do - { - while (a[i] < x) - i = i + 1; - while (x < a[j]) - j = j - 1; - if (i <= j) - { - w = a[i]; - a[i] = a[j]; - a[j] = w; - i = i + 1; - j = j - 1; - } - } - while (i <= j); - if (l < j) - Quicksort (a, l, j); - if (i < r) - Quicksort (a, i, r); -}; - - -Quick () -{ - Initarr (); - Quicksort (sortlist, 1, sortelements); - if ((sortlist[1] != littlest) || (sortlist[sortelements] != biggest)) - { - printf (" Error in Quick.\n"); - } - -}; - - - /* Sorts an array using treesort */ - -tInitarr () -{ - int i, temp; - Initrand (); - biggest = 0; - littlest = 0; - for (i = 1; i <= sortelements; i++) - { - temp = Rand (); - sortlist[i] = temp - (temp / 100000) * 100000 - 50000; - if (sortlist[i] > biggest) - biggest = sortlist[i]; - else if (sortlist[i] < littlest) - littlest = sortlist[i]; - }; - -}; - -CreateNode (t, n) - struct node **t; - int n; -{ - *t = (struct node *) malloc (sizeof (struct node)); - (*t)->left = nil; - (*t)->right = nil; - (*t)->val = n; -}; - -Insert (n, t) - int n; - struct node *t; - /* insert n into tree */ -{ - if (n > t->val) - if (t->left == nil) - CreateNode (&t->left, n); - else - Insert (n, t->left); - else if (n < t->val) - if (t->right == nil) - CreateNode (&t->right, n); - else - Insert (n, t->right); -}; - -int -Checktree (p) - struct node *p; - /* check by inorder traversal */ -{ - int result; - result = true; - if (p->left != nil) - if (p->left->val <= p->val) - result = false; - else - result = Checktree (p->left) && result; - if (p->right != nil) - if (p->right->val >= p->val) - result = false; - else - result = Checktree (p->right) && result; - return (result); -}; /* checktree */ - -Trees () -{ - int i; - tInitarr (); - tree = (struct node *) malloc (sizeof (struct node)); - tree->left = nil; - tree->right = nil; - tree->val = sortlist[1]; - for (i = 2; i <= sortelements; i++) - Insert (sortlist[i], tree); - if (!Checktree (tree)) - printf (" Error in Tree.\n"); -}; - - - /* Sorts an array using bubblesort */ - -bInitarr () -{ - int i, temp; - Initrand (); - biggest = 0; - littlest = 0; - for (i = 1; i <= srtelements; i++) - { - temp = Rand (); - sortlist[i] = temp - (temp / 100000) * 100000 - 50000; - if (sortlist[i] > biggest) - biggest = sortlist[i]; - else if (sortlist[i] < littlest) - littlest = sortlist[i]; - }; -}; - -Bubble () -{ - int i, j; - bInitarr (); - top = srtelements; - - while (top > 1) - { - - i = 1; - while (i < top) - { - - if (sortlist[i] > sortlist[i + 1]) - { - j = sortlist[i]; - sortlist[i] = sortlist[i + 1]; - sortlist[i + 1] = j; - }; - i = i + 1; - }; - - top = top - 1; - }; - if ((sortlist[1] != littlest) || (sortlist[srtelements] != biggest)) - printf ("Error3 in Bubble.\n"); -}; - - -float -Cos (x) - float x; -/* computes cos of x (x in radians) by an expansion */ -{ - int i, factor; - float result, power; - - result = 1.0; - factor = 1; - power = x; - for (i = 2; i <= 10; i++) - { - factor = factor * i; - power = power * x; - if ((i & 1) == 0) - { - if ((i & 3) == 0) - result = result + power / factor; - else - result = result - power / factor; - }; - }; - return (result); -}; - -int -Min0 (arg1, arg2) - int arg1, arg2; -{ - if (arg1 < arg2) - return (arg1); - else - return (arg2); -}; - -Printcomplex (arg1, arg2, zarray, start, finish, increment) - int arg1, arg2, start, finish, increment; - struct complex zarray[]; -{ - int i; - printf ("\n"); - - i = start; - do - { - printf (" %15.3e%15.3e", zarray[i].rp, zarray[i].ip); - i = i + increment; - printf (" %15.3e%15.3e", zarray[i].rp, zarray[i].ip); - printf ("\n"); - i = i + increment; - } - while (i <= finish); - -}; - -Uniform11 (iy, yfl) - int iy; - float yfl; -{ - iy = (4855 * iy + 1731) & 8191; - yfl = iy / 8192.0; -} /* uniform */ ; - -Exptab (n, e) - int n; - struct complex e[]; - -{ /* exptab */ - float theta, divisor, h[26]; - int i, j, k, l, m; - - theta = 3.1415926536; - divisor = 4.0; - for (i = 1; i <= 25; i++) - { - h[i] = 1 / (2 * Cos (theta / divisor)); - divisor = divisor + divisor; - }; - - m = n / 2; - l = m / 2; - j = 1; - e[1].rp = 1.0; - e[1].ip = 0.0; - e[l + 1].rp = 0.0; - e[l + 1].ip = 1.0; - e[m + 1].rp = -1.0; - e[m + 1].ip = 0.0; - - do - { - i = l / 2; - k = i; - - do - { - e[k + 1].rp = h[j] * (e[k + i + 1].rp + e[k - i + 1].rp); - e[k + 1].ip = h[j] * (e[k + i + 1].ip + e[k - i + 1].ip); - k = k + l; - } - while (k <= m); - - j = Min0 (j + 1, 25); - l = i; - } - while (l > 1); - -} /* exptab */ ; - -Fft (n, z, w, e, sqrinv) - int n; - struct complex z[], w[]; - struct complex e[]; - float sqrinv; -{ - int i, j, k, l, m, index; - m = n / 2; - l = 1; - - do - { - k = 0; - j = l; - i = 1; - - do - { - - do - { - w[i + k].rp = z[i].rp + z[m + i].rp; - w[i + k].ip = z[i].ip + z[m + i].ip; - w[i + j].rp = e[k + 1].rp * (z[i].rp - z[i + m].rp) - - e[k + 1].ip * (z[i].ip - z[i + m].ip); - w[i + j].ip = e[k + 1].rp * (z[i].ip - z[i + m].ip) - + e[k + 1].ip * (z[i].rp - z[i + m].rp); - i = i + 1; - } - while (i <= j); - - k = j; - j = k + l; - } - while (j <= m); - - /*z = w ; */ index = 1; - do - { - z[index] = w[index]; - index = index + 1; - } - while (index <= n); - l = l + l; - } - while (l <= m); - - for (i = 1; i <= n; i++) - { - z[i].rp = sqrinv * z[i].rp; - z[i].ip = -sqrinv * z[i].ip; - }; - -}; - -Oscar () -{ /* oscar */ - int i; - Exptab (fftsize, e); - seed = 5767; - for (i = 1; i <= fftsize; i++) - { - Uniform11 (seed, zr); - Uniform11 (seed, zi); - z[i].rp = 20.0 * zr - 10.0; - z[i].ip = 20.0 * zi - 10.0; - }; - - - for (i = 1; i <= 20; i++) - { - Fft (fftsize, z, w, e, 0.0625); -// Printcomplex( 6, 99, z, 1, 256, 17 ); - }; -} /* oscar */ ; - -main () -{ - int i; - fixed = 0.0; - floated = 0.0; - printf ("Starting \n"); -/* rewrite (output); */ - setbuf(stdout, nil); - printf (" Perm"); - timer = Getclock (); - Perm (); - xtimes[1] = Getclock () - timer; - fixed = fixed + permbase * xtimes[1]; - floated = floated + permbase * xtimes[1]; - printf (" Towers"); - timer = Getclock (); - Towers (); - xtimes[2] = Getclock () - timer; - fixed = fixed + towersbase * xtimes[2]; - floated = floated + towersbase * xtimes[2]; - printf (" Queens"); - timer = Getclock (); - Queens (); - xtimes[3] = Getclock () - timer; - fixed = fixed + queensbase * xtimes[3]; - floated = floated + queensbase * xtimes[3]; - printf (" Intmm"); - timer = Getclock (); - Intmm (); - xtimes[4] = Getclock () - timer; - fixed = fixed + intmmbase * xtimes[4]; - floated = floated + intmmbase * xtimes[4]; - printf (" Mm"); - timer = Getclock (); - Mm (); - xtimes[5] = Getclock () - timer; - fixed = fixed + mmbase * xtimes[5]; - floated = floated + fpmmbase * xtimes[5]; - printf (" Puzzle"); - timer = Getclock (); - Puzzle (); - xtimes[6] = Getclock () - timer; - fixed = fixed + puzzlebase * xtimes[6]; - floated = floated + puzzlebase * xtimes[6]; - printf (" Quick"); - timer = Getclock (); - Quick (); - xtimes[7] = Getclock () - timer; - fixed = fixed + quickbase * xtimes[7]; - floated = floated + quickbase * xtimes[7]; - printf (" Bubble"); - timer = Getclock (); - Bubble (); - xtimes[8] = Getclock () - timer; - fixed = fixed + bubblebase * xtimes[8]; - floated = floated + bubblebase * xtimes[8]; - printf (" Tree"); - timer = Getclock (); - Trees (); - xtimes[9] = Getclock () - timer; - fixed = fixed + treebase * xtimes[9]; - floated = floated + treebase * xtimes[9]; - printf (" FFT"); - timer = Getclock (); - Oscar (); - xtimes[10] = Getclock () - timer; - fixed = fixed + fftbase * xtimes[10]; - floated = floated + fpfftbase * xtimes[10]; - printf ("\n"); - for (i = 1; i <= 10; i++) - printf ("%8d", xtimes[i]); - printf ("\n"); - /* compute composites */ - printf ("\n"); - printf ("Nonfloating point composite is %10.0f\n", fixed / 10.0); - printf ("\n"); - printf ("Floating point composite is %10.0f\n", floated / 10.0); -} diff --git a/lib/CPUs/MIPS/bsp/examples/startup.S b/lib/CPUs/MIPS/bsp/examples/startup.S deleted file mode 100644 index b3eb382..0000000 --- a/lib/CPUs/MIPS/bsp/examples/startup.S +++ /dev/null @@ -1,87 +0,0 @@ - .file "startup.S" - - .section .rodata - .data -argv0: .asciz "\"This-MIPS-program\"" -argv: .word argv0 - - .text - .section .start, "ax" - .extern _init - .extern libsys_init - .extern _exc_vect_start - .extern _xcpt_handler - .align 2 - .globl _start -_start: - .set noreorder - j init - nop - .set reorder - - .text - .set noreorder -init: - # Set stack pointer - la $sp, stack_ptr - # Set global pointer - la $gp, _gp - - # zero bss - la $8, __bss_start - la $9, _end -$zeroise: - sw $0, 0($8) - bne $8, $9, $zeroise - addiu $8, 4 - - # Install exception vector jump code - la $t1, _exc_vect_copy_start - la $t2, _exc_vect_copy_end - la $t0, _exc_vect_start - -$install: lw $v0, 0($t1) - addiu $t1, 4 - sw $v0, 0($t0) - bne $t1, $t2, $install - addiu $t0, 4 - - # Call _init - la $k0, _init - jalr $k0 - nop - - # Call libsys_init - la $k0, libsys_init - jalr $k0 - nop - - # Set user-mode - mfc0 $a0, $12 - li $a1, 3 - or $a0, $a1 - mtc0 $a0, $12 - - # Set environment - li $a0, 1 - la $a1, argv - - # Call main - la $k0, main - jalr $k0 - nop - - # Terminate after main returns -_terminate: - nop - la $t0, exit - jalr $t0 - move $a0, $v0 - -_exc_vect_copy_start: - la $k0, _xcpt_handler - jr $k0 - nop -_exc_vect_copy_end: - - .set reorder diff --git a/lib/CPUs/MIPS/bsp/examples/test_ac97.c b/lib/CPUs/MIPS/bsp/examples/test_ac97.c deleted file mode 100644 index 12dce79..0000000 --- a/lib/CPUs/MIPS/bsp/examples/test_ac97.c +++ /dev/null @@ -1,310 +0,0 @@ -#include -#include -#include -#include -#include -#include "libsys.h" - -#define PI 3.1415926535897932384626433832795 -#define SAMPLE_RATE 48000 -#define BUF_SIZE (2*4800) -#define REC_BUF_SIZE (5*60*2*SAMPLE_RATE) - -INT32 *buffer; -INT32 *rec_buffer; -UINT32 buf_size; - -INT32 * volatile pPtr_r; -INT32 * volatile pPtr_w; -UINT32 gcnt, led_cnt; -volatile INT32 sample_left, sample_right; - -#define AC97_REG_RESET 0x00 -#define AC97_REG_VOLO_MST 0x02 -#define AC97_REG_VOLO_HP 0x04 -#define AC97_REG_VOLO_MONO 0x06 -#define AC97_REG_VOLI_BEEP 0x0A -#define AC97_REG_VOLI_PHONE 0x0C -#define AC97_REG_VOLI_MIC 0x0E -#define AC97_REG_VOLI_LINE 0x10 -#define AC97_REG_VOLI_CD 0x12 -#define AC97_REG_VOLI_VIDEO 0x14 -#define AC97_REG_VOLI_AUX 0x16 -#define AC97_REG_VOLI_PCM 0x18 -#define AC97_REG_REC_SRC 0x1A -#define AC97_REG_REC_GAIN 0x1C -#define AC97_REG_EXTCTRL 0x2A -#define AC97_REG_RATE_DAC 0x2C -#define AC97_REG_RATE_ADC 0x32 - -UINT32 ac97_status(UINT32 reg) -{ - UINT32 offset; - volatile UINT32 *pAC_stat = (UINT32*)SYS_AC97_STAT; - volatile UINT32 *pAC_stat_ac = (UINT32*)SYS_AC97_ACSTAT; - - offset = (reg & 0x7E); - - // Wait if previous command is still pending - while(*pAC_stat & 1); - - *(pAC_stat_ac + offset) = 0; - - // Wait for data valid - while(!(*pAC_stat & 2)); - - return *pAC_stat_ac; -} - -void ac97_ctrl(UINT32 reg, UINT16 value) -{ - UINT32 offset; - volatile UINT32 *pAC_stat = (UINT32*)SYS_AC97_STAT; - volatile UINT32 *pAC_ctrl_ac = (UINT32*)SYS_AC97_ACCTRL; - - offset = (reg & 0x7E); - - // Wait if previous command is still pending - while(*pAC_stat & 1); - - *(pAC_ctrl_ac + offset) = value; - -} - -void ac97_isr_rec(void) -{ - int i, size; - volatile UINT32 *pReg = (UINT32*)SYS_LED_PORT; - volatile UINT32 *pAC_stat = (UINT32*)SYS_AC97_STAT; - volatile INT32 *pAC_pcm = (INT32*)SYS_AC97_PCM; - - if (!gcnt) - { - gcnt = SAMPLE_RATE; - *pReg = led_cnt++; - } - gcnt--; - - *pPtr_w++ = pAC_pcm[3]; - if (pPtr_w == &buffer[buf_size]) - pPtr_w = buffer; - - *pPtr_w++ = pAC_pcm[4]; - if (pPtr_w == &buffer[buf_size]) - pPtr_w = buffer; - - CP0_TR_write(pAC_pcm[3]); - CP0_TR_write(pAC_pcm[4]); - -} - -void ac97_isr_play(void) -{ - int i, size; - volatile UINT32 *pReg = (UINT32*)SYS_LED_PORT; - volatile UINT32 *pAC_stat = (UINT32*)SYS_AC97_STAT; - volatile INT32 *pAC_pcm = (INT32*)SYS_AC97_PCM; - - if (!gcnt) - { - gcnt = SAMPLE_RATE; - *pReg = led_cnt++; - } - gcnt--; - - *pAC_pcm = *pPtr_r++; - if (pPtr_r == &buffer[buf_size]) - pPtr_r = buffer; -} - -void ac97_isr_pass(void) -{ - int i, size; - volatile UINT32 *pReg = (UINT32*)SYS_LED_PORT; - volatile UINT32 *pAC_stat = (UINT32*)SYS_AC97_STAT; - volatile INT32 *pAC_pcm = (INT32*)SYS_AC97_PCM; - - if (!gcnt) - { - gcnt = SAMPLE_RATE; - *pReg = led_cnt++; - } - gcnt--; - - if (*pAC_stat & 0x08) - { - -// CP0_TR_write(pAC_pcm[3]); -// CP0_TR_write(pAC_pcm[4]); - - *pPtr_w++ = pAC_pcm[3]; - if (pPtr_w == &buffer[buf_size]) - pPtr_w = buffer; - - *pPtr_w++ = pAC_pcm[4]; - if (pPtr_w == &buffer[buf_size]) - pPtr_w = buffer; - } - - if (pPtr_r != pPtr_w) - { - *pAC_pcm = *pPtr_r++; - if (pPtr_r == &buffer[buf_size]) - pPtr_r = buffer; - } - -} - -int main (void) -{ - int result, i, j; - volatile UINT32 *pReg = (UINT32*)SYS_LED_PORT; - volatile UINT32 *pGPIO1 = (UINT32*)SYS_GPIO1; - volatile UINT32 *pAC_ctrl = (UINT32*)SYS_AC97_CTRL; - volatile UINT32 *pAC_stat = (UINT32*)SYS_AC97_STAT; - volatile UINT32 *pAC_ctrl_ac = (UINT32*)SYS_AC97_ACCTRL; - volatile UINT32 *pAC_stat_ac = (UINT32*)SYS_AC97_ACSTAT; - volatile UINT32 *pAC_pcm = (UINT32*)SYS_AC97_PCM; - double phi, dphi, y, mean; - char sel, cmd; - char buf[1024]; - FILE *pFile = stdout; - -// setbuf(stderr, NULL); -// - fprintf(pFile, "AC-97 Test\n"); - fprintf(pFile, "Status : %8.8X\n", *pAC_ctrl); - - ac97_ctrl(AC97_REG_VOLO_MST, 0); - ac97_ctrl(AC97_REG_VOLO_HP, 0); - ac97_ctrl(AC97_REG_VOLI_LINE, 0x8808); - ac97_ctrl(AC97_REG_VOLI_PCM, 0x0808); - ac97_ctrl(AC97_REG_REC_SRC, 0x0404); - ac97_ctrl(AC97_REG_REC_GAIN, 0); - ac97_ctrl(AC97_REG_EXTCTRL, 1); - - ac97_ctrl(AC97_REG_RATE_DAC, SAMPLE_RATE); - ac97_ctrl(AC97_REG_RATE_ADC, SAMPLE_RATE); - - led_cnt = 0; - gcnt = SAMPLE_RATE; - - fprintf(pFile, "DAC-Rate : %d\n", ac97_status(AC97_REG_RATE_DAC)); - fprintf(pFile, "ADC-Rate : %d\n", ac97_status(AC97_REG_RATE_ADC)); - - *pGPIO1 = 0x04; - - while(1) - { - fprintf(pFile, "Aufnehmen und Abspielen (1)\n"); - fprintf(pFile, "Sinus Ton (2)\n"); - fprintf(pFile, "Pass through (3)\n"); - fprintf(pFile, "Eingabe: "); - - scanf("%c", &sel); -// sel = 0x31; - - if (sel == 0x31) - { - buf_size = REC_BUF_SIZE; - buffer = (INT32*)malloc(REC_BUF_SIZE*sizeof(INT32)); -// memset(buffer, 0, sizeof(REC_BUF_SIZE*sizeof(INT32))); - pPtr_r = buffer; - pPtr_w = buffer; - - ac97_ctrl(AC97_REG_VOLI_LINE, 0x0808); - - cmd = 0; - while(1) - { - switch (cmd) - { - case 'r': - ac97_ctrl(AC97_REG_VOLI_LINE, 0x0808); - pPtr_w = buffer; - fprintf(pFile, "Aufnahme\n"); - interrupt_register(5, ac97_isr_rec); - interrupt_enable(5); - *pAC_ctrl = 0x24; - break; - - case 'p': - ac97_ctrl(AC97_REG_VOLI_LINE, 0x8808); - pPtr_r = buffer; - fprintf(pFile, "Wiedergabe\n"); - interrupt_register(5, ac97_isr_play); - interrupt_enable(5); - *pAC_ctrl = 0x12; - break; - - case ' ': - ac97_ctrl(AC97_REG_VOLI_LINE, 0x0808); - fprintf(pFile, "Stop\n"); - memset(buffer, 0, sizeof(REC_BUF_SIZE*sizeof(INT32))); - *pAC_ctrl = 0x00; - pPtr_r = buffer; - pPtr_w = buffer; - break; - - default: - fprintf(pFile, "Aufnahme (R)\n"); - fprintf(pFile, "Wiedergabe (P)\n"); - fprintf(pFile, "Stop (Space)\n"); - break; - } - cmd = readchar(0); - } - } - if (sel == 0x32) - { - buf_size = BUF_SIZE; - buffer = (INT32*)malloc(REC_BUF_SIZE*sizeof(INT32)); - memset(buffer, 0, sizeof(REC_BUF_SIZE*sizeof(INT32))); - pPtr_r = buffer; - pPtr_w = buffer; - - dphi = 120*2*PI/BUF_SIZE; - phi = 0; - for (i=0; i < BUF_SIZE/2; i++) - { - y = cos(phi); - buffer[2*i+0] = (INT32)(32000*y); - buffer[2*i+1] = (INT32)(32000*y); - phi = fmod((phi + dphi), 2.0*PI); - } - - fprintf(stderr, "Status : %8.8X\n", *pAC_ctrl); - - interrupt_register(5, ac97_isr_play); - interrupt_enable(5); - *pAC_ctrl = 0x12; - - fprintf(stderr, "Status : %8.8X\n", *pAC_ctrl); - - while(1) - { - fprintf(stderr, "Status : %8.8X\n", *pAC_ctrl); - } - } - if (sel == 0x33) - { - - buf_size = BUF_SIZE; - buffer = (INT32*)malloc(BUF_SIZE*sizeof(INT32)); - memset(buffer, 0, sizeof(BUF_SIZE*sizeof(INT32))); - pPtr_r = buffer; - pPtr_w = buffer; - *pAC_ctrl = 0x32; - interrupt_register(5, ac97_isr_pass); - interrupt_enable(5); - - fprintf(stdout, "Status : %8.8X\n", *pAC_ctrl); - - while(1); - } - } - - return 0; - -} - diff --git a/lib/CPUs/MIPS/bsp/examples/test_dcache.c b/lib/CPUs/MIPS/bsp/examples/test_dcache.c deleted file mode 100644 index 74327d1..0000000 --- a/lib/CPUs/MIPS/bsp/examples/test_dcache.c +++ /dev/null @@ -1,61 +0,0 @@ -#include -#include -#include "libsys.h" -#include "libsys.h" - -UINT32 tset(UINT32 *pMem) -{ - - __asm__ - ( - ".set noreorder\n" - ".set nomacro\n" - "addiu $t1, $0, 0x5555\n" - "lw $t0, 0(%[pMem])\n" - "sw $t1, 24(%[pMem])\n" - "addiu $t0, 8\n" - "sw $t0, 0(%[pMem])\n" - "nop\n" - "nop\n" - "nop\n" - "nop\n" - "nop\n" - "nop\n" - "nop\n" - "nop\n" - "nop\n" - "nop\n" - "nop\n" - "nop\n" - "lw $v0, 24(%[pMem])\n" - ".set macro\n" - ".set reorder\n" - : - : [pMem] "r" (pMem) - : "t0", "t1" - ); -} - -int main(void) -{ - int i; - volatile int *pLED = (int*)SYS_LED_PORT; - UINT64 *pBuf64; - UINT32 *pPtr; - - pBuf64 = (UINT64*)0x4000FC80; //malloc(1024*sizeof(UINT32)); - - pPtr = (UINT32*)pBuf64; - - for(i=0; i < 1024; i++) - *pPtr++ = i; - - pPtr = (UINT32*)pBuf64; - sputs("Ptr: "); print_word((int)pPtr); sputs("\n"); - DCACHE_invalidate_all(); - - - *pLED = tset(pPtr); - - return 0; -} diff --git a/lib/CPUs/MIPS/bsp/examples/test_endianess.c b/lib/CPUs/MIPS/bsp/examples/test_endianess.c deleted file mode 100644 index 8f0d737..0000000 --- a/lib/CPUs/MIPS/bsp/examples/test_endianess.c +++ /dev/null @@ -1,64 +0,0 @@ -#include -#include -#include -#include "libsys.h" - -#define TEST_SIZE 32768 -int main (void) -{ - int i; - UINT16 *ram16; - UINT32 sr; - UINT32 volatile *pReg = (UINT32*)SYS_LED_PORT; - - *pReg = 0; - - sr = CP0_SR_read(); - - ram16 = (UINT16*)calloc(TEST_SIZE/2,sizeof(UINT16)); - - CP0_SR_write(sr | (1 << 25)); - - for (i=0; i < TEST_SIZE/2; i++) - ram16[i] = (UINT16)i; - - for (i=TEST_SIZE/2-1; i >= 0; i--) - if (ram16[i] != (UINT16)i) - break; - - i++; - if (i) - *pReg = 0xFFFFFFFF; - else - *pReg = 1; - - - free(ram16); - - ram16 = (UINT16*)calloc(TEST_SIZE/2,sizeof(UINT16)); - - *pReg = 0; - CP0_SR_write(sr & ~(1 << 25)); - - for (i=0; i < TEST_SIZE/2; i++) - ram16[i] = (UINT16)i; - - for (i=TEST_SIZE/2-1; i >= 0; i--) - if (ram16[i] != (UINT16)i) - break; - - i++; - if (i) - *pReg = 0xFFFFFFFF; - else - *pReg = 1; - - - free(ram16); - - -// sputs("Status : ");print_word(sr);sputs("\n"); - - return 0; -} - diff --git a/lib/CPUs/MIPS/bsp/examples/test_exception.c b/lib/CPUs/MIPS/bsp/examples/test_exception.c deleted file mode 100644 index 34a0bca..0000000 --- a/lib/CPUs/MIPS/bsp/examples/test_exception.c +++ /dev/null @@ -1,282 +0,0 @@ -#include -#include -#include "libsys.h" - -void _exc_break(void) -{ - __asm - ( - ".set noreorder\n" - "break 0x9\n" - ".set reorder\n" - - ); -} - -void _exc_syscall(UINT32 code, UINT32 arg) -{ - __asm - ( - "move $v0, %[code]\n" - "move $a0, %[arg]\n" - "syscall\n" - : - : [code] "r" (code), [arg] "r" (arg) - : "v0", "a0" - - ); -} - -void _exc_arith(void) -{ - __asm - ( - ".set noreorder\n" - " li $t0, 0x7FFFFFFF\n" - " addi $t1, $t0, 2\n" - ".set reorder\n" - - ); -} - -void _exc_store_err(void) -{ - volatile int *pSrc = (int*)SYS_TIMER_SEC; - volatile int *pDst = (int*)0x40000001; - - *pDst = *pSrc; - -} - -void _exc_load_err(void) -{ - __asm - ( - ".set noreorder\n" - " li $t0, 0x40000000\n" - " li $t1, 0x40000000\n" - " lw $t1, 0($t1)\n" - " lw $t0, 2($t0)\n" - " lw $t1, 4($t0)\n" - "nop\n" - ".set reorder\n" - - ); - -} - -void _exc_kaddr_err(void) -{ - __asm - ( - ".set noreorder\n" - " li $t0, 0x80000000\n" - " jr $t0\n" - "nop\n" - ".set reorder\n" - - ); - -} - -void _exc_iaddr_daddr_err(void) -{ - __asm - ( - ".set noreorder\n" - " li $t0, 0x40000003\n" - " li $t1, 0x40000002\n" - " jr $t0\n" - " lw $t1, 0($t1)\n" - "nop\n" - ".set reorder\n" - - ); - -} - -void _exc_daddr_iaddr_err(void) -{ - __asm - ( - ".set noreorder\n" - " li $t0, 0x40000003\n" - " li $t1, 0x40000002\n" - " lw $t1, 0($t1)\n" - " jr $t0\n" - "nop\n" - ".set reorder\n" - - ); - -} - -void _exc_iaddr_err(void) -{ - __asm - ( - ".set noreorder\n" - " li $t0, 0x40000003\n" - " jr $t0\n" - "nop\n" - ".set reorder\n" - - ); - -} - -void _exc_ri(void) -{ - __asm - ( - ".set noreorder\n" - " li $t0, 0x40010000\n" - " li $t1, 0x9c563442\n" - " sw $t1, 0($t0)\n" - " jr $t0\n" - "nop\n" - ".set reorder\n" - - ); - -} - -void _exc_ibe(void) -{ - __asm - ( - ".set noreorder\n" - " li $t1, 0x10000000\n" - " jr $t1\n" - "nop\n" - ".set reorder\n" - - ); - -} - -void _exc_dbe(void) -{ - __asm - ( - ".set noreorder\n" - " li $t1, 0x10000000\n" - " lw $t0, 0($t1)\n" - "nop\n" - " jr $t0\n" - "nop\n" - ".set reorder\n" - - ); - -} - -void handler0(void) -{ - printf("Interrupt 0\n"); - interrupt_clr(0); -} - -void handler1(void) -{ - printf("Interrupt 1\n"); - interrupt_clr(1); -} - -int main(void) -{ - int buf[256]; - int i, sel; - - interrupt_register(0, handler0); - interrupt_enable(0); - interrupt_register(1, handler1); - interrupt_enable(1); - - while(1) - { - printf("Welche exception möchten Sie testen?\n"); - printf(" 1 : Reserved instruction\n"); - printf(" 2 : Privileged address (BadVAddr = 0x80000000)\n"); - printf(" 3 : Arithmetic overflow\n"); - printf(" 4 : Syscall\n"); - printf(" 5 : Breakpoint\n"); - printf(" 6 : Load error on instruction (BadVAddr = 0x40000003)\n"); - printf(" 7 : Load error on data (BadVAddr = 0x40000002)\n"); - printf(" 8 : Store error on data (BadVAddr = 0x40000001)\n"); - printf(" 9 : Bus error on instruction\n"); - printf("10 : Bus error on data\n"); - printf("11 : SW-interrupt 0\n"); - printf("12 : SW-interrupt 1\n"); - printf("13 : Load error on instruction and Load error on data (BadVAddr = 0x40000003)\n"); - printf("14 : Load error on data and Load error on instruction (BadVAddr = 0x40000002)\n"); - - scanf("%d", &sel); - printf("Jetzt kommt die exception (%d)!\n", sel); - - switch(sel) - { - case 1: - _exc_ri(); - break; - - case 2: - _exc_kaddr_err(); - break; - - case 3: - _exc_arith(); - break; - - case 4: - _exc_syscall(4, (UINT32)((char*)"Hallo Syscall (")); - _exc_syscall(1, 12345678); - _exc_syscall(4, (UINT32)((char*)")\n")); - break; - - case 5: - _exc_break(); - break; - - case 6: - _exc_iaddr_err(); - break; - - case 7: - _exc_load_err(); - break; - - case 8: - _exc_store_err(); - break; - - case 9: - printf("IBE: Exception not implemented in current CPU!\nPush reset to restart!\n"); - _exc_ibe(); - break; - - case 10: - printf("DBE: Exception not implemented in current CPU!\nPush reset to restart!\n"); - _exc_dbe(); - break; - - case 11: - case 12: - interrupt_set(sel-11); - break; - - case 13: - _exc_iaddr_daddr_err(); - break; - - case 14: - _exc_daddr_iaddr_err(); - break; - - default: - break; - } - sel = 0; - } - return 0; -} diff --git a/lib/CPUs/MIPS/bsp/examples/test_flash.c b/lib/CPUs/MIPS/bsp/examples/test_flash.c deleted file mode 100644 index 7d40961..0000000 --- a/lib/CPUs/MIPS/bsp/examples/test_flash.c +++ /dev/null @@ -1,94 +0,0 @@ -/************************************************************************/ -/* */ -/* AMD CFI Enabled Flash Memory Drivers */ -/* File name: CFIDRIVE.C */ -/* Revision: 1.0 5/07/98 */ -/* */ -/* Copyright (c) 1998 ADVANCED MICRO DEVICES, INC. All Rights Reserved. */ -/* This software is unpublished and contains the trade secrets and */ -/* confidential proprietary information of AMD. Unless otherwise */ -/* provided in the Software Agreement associated herewith, it is */ -/* licensed in confidence "AS IS" and is not to be reproduced in whole */ -/* or part by any means except for backup. Use, duplication, or */ -/* disclosure by the Government is subject to the restrictions in */ -/* paragraph (b) (3) (B) of the Rights in Technical Data and Computer */ -/* Software clause in DFAR 52.227-7013 (a) (Oct 1988). */ -/* Software owned by */ -/* Advanced Micro Devices, Inc., */ -/* One AMD Place, */ -/* P.O. Box 3453 */ -/* Sunnyvale, CA 94088-3453. */ -/************************************************************************/ -/* This software constitutes a basic shell of source code for */ -/* programming all AMD Flash components. AMD */ -/* will not be responsible for misuse or illegal use of this */ -/* software for devices not supported herein. AMD is providing */ -/* this source code "AS IS" and will not be responsible for */ -/* issues arising from incorrect user implementation of the */ -/* source code herein. It is the user's responsibility to */ -/* properly design-in this source code. */ -/* */ -/************************************************************************/ - -#include -#include -#include "cfiflash.h" -#include "libsys.h" - -#define TEST_SIZE (1024*1024) -#define FLASH_OFFSET 0x700000 -int main(void) -{ - int i; - flash_t flash; - UINT8 *pFlash = (UINT8*)0xA4000000; - UINT32 result; - UINT8 *pBuf; - - setbuf(stdout, NULL); - result = flash_find(&flash, 0xA4000000); - - if (result < 0) - { - printf("flash_find() error!\n"); - return 1; - } - - printf("Found Flash at %8.8X\n", (UINT32)flash.pBase); - - pBuf = (UINT8*)malloc(TEST_SIZE); - - for (i=0; i < TEST_SIZE; i++) - pBuf[i] = i; - - printf("Flash erase from %8.8X to %8.8X...", FLASH_OFFSET, FLASH_OFFSET+TEST_SIZE); - result = flash_erase(&flash, FLASH_OFFSET, TEST_SIZE); - if (result < 0) - { - printf("error!\n"); - return 1; - } - printf("OK\n"); - - printf("Flash program from %8.8X to %8.8X...", FLASH_OFFSET, FLASH_OFFSET+TEST_SIZE); - result = flash_program(&flash, FLASH_OFFSET, pBuf, TEST_SIZE); - if (result < 0) - { - printf("error!\n"); - return 1; - } - printf("OK\n"); - - printf("Flash verify from %8.8X to %8.8X...", FLASH_OFFSET, FLASH_OFFSET+TEST_SIZE); - result = flash_verify(&flash, FLASH_OFFSET, pBuf, TEST_SIZE); - if (result < 0) - { - printf("error!\n"); - return 1; - } - printf("OK\n"); - -// PrintBuffer8((UINT8*)pFlash, 16, TEST_SIZE); - - return 0; -} diff --git a/lib/CPUs/MIPS/bsp/examples/test_hpi.c b/lib/CPUs/MIPS/bsp/examples/test_hpi.c deleted file mode 100644 index 407d070..0000000 --- a/lib/CPUs/MIPS/bsp/examples/test_hpi.c +++ /dev/null @@ -1,848 +0,0 @@ -#include -#include -#include -#include -#include "libsys.h" -#include "cfiflash.h" -#include "hpi.h" - -static volatile UINT32 _g_uart_msg; -static volatile UINT32 _g_rst; -static volatile UINT32 _g_sus; -static volatile UINT32 _g_cfg; - -void uart_handler(void) -{ - volatile UINT32 *pUART_stat = (UINT32*)SYS_UART_STAT; - volatile UINT32 *pUART_data = (UINT32*)SYS_UART_DATA; - - while((SYS_PS2_BIT_RX_AVAIL & *pUART_stat)) - { - _g_uart_msg = *pUART_data; - } - -} - -void PrintDevRegs(UINT devid) -{ - int i; - UINT32 reg_base1, reg_base2, reg_addr; - - if ((devid < 1) || (devid > 2)) - return; - - printf("********************************************************\n"); - printf("Device %d status\n", devid); - printf("********************************************************\n"); - reg_base1 = 0x0200 + (devid-1)*0x80; - reg_base2 = 0xC080 + (devid-1)*0x20; - reg_addr = reg_base2 + 4; - printf("Port select (%4.4X) : %4.4X\n", reg_addr, hpi_read_reg(reg_addr)); - - reg_addr = reg_base2 + 10; - printf("USB control (%4.4X) : %4.4X\n", reg_addr, hpi_read_reg(reg_addr)); - - reg_addr = reg_base2 + 12; - printf("Int. enable (%4.4X) : %4.4X\n", reg_addr, hpi_read_reg(reg_addr)); - - reg_addr = reg_base2 + 14; - printf("Address (%4.4X) : %4.4X\n", reg_addr, hpi_read_reg(reg_addr)); - - reg_addr = reg_base2 + 16; - printf("Status (%4.4X) : %4.4X\n", reg_addr, hpi_read_reg(reg_addr)); - - reg_addr = reg_base2 + 18; - printf("Frame # reg (%4.4X) : %4.4X\n", reg_addr, hpi_read_reg(reg_addr)); - - reg_addr = reg_base2 + 20; - printf("SOF/EOP cnt (%4.4X) : %4.4X\n", reg_addr, hpi_read_reg(reg_addr)); - - for (i=0; i < 8; i++) - { - printf("EP# %d\n", i); - reg_addr = reg_base1 + 16*i + 0; - printf("Control (%4.4X) : %4.4X\n", reg_addr, hpi_read_reg(reg_addr)); - - reg_addr = reg_base1 + 16*i + 2; - printf("Address (%4.4X) : %4.4X\n", reg_addr, hpi_read_reg(reg_addr)); - - reg_addr = reg_base1 + 16*i + 4; - printf("Count (%4.4X) : %4.4X\n", reg_addr, hpi_read_reg(reg_addr)); - - reg_addr = reg_base1 + 16*i + 6; - printf("Status (%4.4X) : %4.4X\n", reg_addr, hpi_read_reg(reg_addr)); - - reg_addr = reg_base1 + 16*i + 8; - printf("Count result (%4.4X) : %4.4X\n", reg_addr, hpi_read_reg(reg_addr)); - - } -} - -typedef struct _sdev_descr_t -{ - UINT8 size; // length - UINT8 type; // desc type - UINT16 usb_spec; // USB spec - UINT8 devclass; // device class - UINT8 subclass; // sub class - UINT8 protocol; // protocol - UINT8 max_packet_size; // max packet size for endpoint 0 - UINT16 vendor_id; // Vendor ID - UINT16 product_id; // Product ID - UINT16 device_id; // device release number - UINT8 man_str_index; // index of manufacture string - UINT8 prod_str_index; // index of product string - UINT8 sn_str_index; // index of serial number string - UINT8 nconfs; // number of configurations -} __attribute__ ((__packed__)) dev_descr_t; - -typedef struct _sconf_descr_t -{ - UINT8 size; // length of this config - UINT8 type; // desc type - UINT16 total_size; // Total configuration desc length including this config and following descriptions - UINT8 nifaces; // Number of interface descriptions following this - UINT8 conf_id; // config number - UINT8 conf_str_index; // index of string describing config - UINT8 attr; // attributes (e.g. bus powered) - UINT8 current; // 2mA x (max. 250 => 500mA) -} __attribute__ ((__packed__)) conf_descr_t; - -typedef struct _siface_descr_t -{ - UINT8 size; // length of this config - UINT8 type; // desc type - UINT8 base; // base number - UINT8 alt; // alt - UINT8 neps; // number of endpoint description following this - UINT8 iface_class; // interface class (vendor) - UINT8 subclass; // subclass - UINT8 iface_proto; // interface proto (vendor) - UINT8 iface_str_index; -} __attribute__ ((__packed__)) iface_descr_t; - -typedef struct _sep_descr_t -{ - UINT8 size; // length of this config - UINT8 type; // type (endpoint) - UINT8 type_num; // type/number (Host use WriteFile) - UINT8 bulk; // Bulk - UINT16 pkt_size; // packet size - UINT8 interval; // interval -} __attribute__ ((__packed__)) ep_descr_t; - -typedef struct _sotg_descr_t -{ - UINT8 size; // length of this config - UINT8 type; // type (OTG) - UINT8 hnp_srp; // HNP|SRP support -} __attribute__ ((__packed__)) otg_descr_t; - -typedef struct _sstr_descr_hdr_t -{ - UINT8 size; // length of this config - UINT8 type; // type -} __attribute__ ((__packed__)) str_descr_hdr_t; - -typedef struct _scfg_inst_t -{ - usb_irp_t *pIRP_rx; - usb_irp_t *pIRP_tx; -} cfg_inst_t; - -UINT32 conf_write(UINT8 *pConfDescr, UINT32 neps, ep_descr_t *pEP) -{ - UINT32 pos, size; - conf_descr_t cfg; - iface_descr_t iface; - otg_descr_t otg_descr; - - // Fill config description - cfg.size = sizeof(conf_descr_t); - cfg.type = 2; - cfg.total_size = sizeof(conf_descr_t) + sizeof(iface_descr_t) + neps*sizeof(ep_descr_t) + sizeof(otg_descr_t); - cfg.nifaces = 1; // can handle only one interface per config - cfg.conf_id = 1; - cfg.conf_str_index = 0; - cfg.attr = 0x80; - cfg.current = 50; - - // Copy config description - pos = 0; - size = sizeof(conf_descr_t); - memcpy(&pConfDescr[pos], &cfg, size); - - // Fill interface description - iface.size = sizeof(iface_descr_t); - iface.type = 4; - iface.base = 0; - iface.alt = 0; - iface.neps = neps; - iface.iface_class = 0; - iface.subclass = 0; - iface.iface_proto = 0; - iface.iface_str_index = 0; - - // Copy interface description - pos += size; - size = sizeof(iface_descr_t); - memcpy(&pConfDescr[pos], &iface, size); - - // Copy N end point descriptions - pos += size; - size = neps*sizeof(ep_descr_t); - memcpy(&pConfDescr[pos], pEP, size); - - // Fill OTG description - otg_descr.size = sizeof(otg_descr_t); - otg_descr.type = 9; // OTG - otg_descr.hnp_srp = 3; // HNP|SRP supported - - // Copy OTG description - pos += size; - size = sizeof(ep_descr_t); - memcpy(&pConfDescr[pos], &otg_descr, size); - - pos += size; - - return pos; -} - -UINT32 str_write(UINT8 *pStrDescr, UINT8 *pStr0, UINT8 *pStr1, UINT8 *pStr2) -{ - int i; - UINT32 pos, size, strsize; - str_descr_hdr_t *pStrHdr; - UINT16 *pStr; - - pos = 0; - size = sizeof(str_descr_hdr_t); - strsize = 2; - pStrHdr = (str_descr_hdr_t*)&pStrDescr[pos]; - pStrHdr->size = size + strsize; - pStrHdr->type = 3; - - pos += size; - pStr = (UINT16*)&pStrDescr[pos]; - - *pStr = 0x0409; - - // String 0 - pos += size; - size = sizeof(str_descr_hdr_t); - strsize = strlen(pStr0); - - pStrHdr = (str_descr_hdr_t*)&pStrDescr[pos]; - pStrHdr->size = sizeof(str_descr_hdr_t) + 2*strsize; - pStrHdr->type = 3; - - pos += size; - size = 2*strsize; - pStr = (UINT16*)&pStrDescr[pos]; - - for (i=0; i < strsize; i++) - pStr[i] = (UINT16)pStr0[i]; - - // String 1 - pos += size; - size = sizeof(str_descr_hdr_t); - strsize = strlen(pStr1); - - pStrHdr = (str_descr_hdr_t*)&pStrDescr[pos]; - pStrHdr->size = sizeof(str_descr_hdr_t) + 2*strsize; - pStrHdr->type = 3; - - pos += size; - size = 2*strsize; - pStr = (UINT16*)&pStrDescr[pos]; - - for (i=0; i < strsize; i++) - pStr[i] = (UINT16)pStr1[i]; - - // String 2 - pos += size; - size = sizeof(str_descr_hdr_t); - strsize = strlen(pStr2); - - pStrHdr = (str_descr_hdr_t*)&pStrDescr[pos]; - pStrHdr->size = sizeof(str_descr_hdr_t) + 2*strsize; - pStrHdr->type = 3; - - pos += size; - size = 2*strsize; - pStr = (UINT16*)&pStrDescr[pos]; - - for (i=0; i < strsize; i++) - pStr[i] = (UINT16)pStr2[i]; - - pos += size; - - return pos; -} - -void ep0_func(void *pArg) -{ - UINT32 result; - UINT16 buf[USB_MAX_IMG_SIZE/2], ep_cntres, ep_status, ep_count, tsize; - usb_irp_t *pIRP = (usb_irp_t*)pArg; - -// printf("Callback with pArg = %8.8X\n", (UINT32)pArg); - ep_status = hpi_read_reg (SUSB2_REG_EP_STATUS0); - ep_cntres = hpi_read_reg (SUSB2_REG_EP_CNTRES0); - ep_count = hpi_read_reg (SUSB2_REG_EP_COUNT0); - - if (ep_status & 0x10) - { - printf("Setup-flag detected. Status = %4.4X\n", ep_status); - } -} - -void ep1_func(void *pArg) -{ - UINT32 result; - UINT16 buf[USB_MAX_IMG_SIZE/2], ep_cntres, ep_status, ep_count, tsize; - usb_irp_t *pIRP = (usb_irp_t*)pArg; - -// printf("Callback with pArg = %8.8X\n", (UINT32)pArg); - ep_status = hpi_read_reg (SUSB2_REG_EP_STATUS1); - ep_cntres = hpi_read_reg (SUSB2_REG_EP_CNTRES1); - ep_count = hpi_read_reg (SUSB2_REG_EP_COUNT1); - - tsize = pIRP->tsize; - if (ep_status & 0x0020) - { - printf("Length exception result %4.4X with count = %d\n", ep_status, (INT16)ep_cntres); - if (ep_status & 0x0400) - tsize = (UINT16)((INT16)tsize - (INT16)ep_cntres); - if (ep_status & 0x0800) - tsize = (UINT16)((INT16)tsize - (INT16)ep_cntres); - - } - result = hpi_read_ram(pIRP->cy_req.addr, buf, tsize); - usb_irp_enqueue(pIRP); - fifo_write(&pIRP->fifo, (UINT8*)buf, result, 0, FIFO_BLOCK); - -// printf("Read %d bytes\n", result); - -} - -void ep2_func(void *pArg) -{ - UINT32 result; - UINT16 buf[USB_MAX_IMG_SIZE/2], ep_cntres, ep_status, ep_count, tsize; - usb_irp_t *pIRP = (usb_irp_t*)pArg; - -// printf("Callback with pArg = %8.8X\n", (UINT32)pArg); - ep_status = hpi_read_reg (SUSB2_REG_EP_STATUS2); - ep_cntres = hpi_read_reg (SUSB2_REG_EP_CNTRES2); - ep_count = hpi_read_reg (SUSB2_REG_EP_COUNT2); - - tsize = pIRP->tsize; - if (ep_status & 0x0020) - { - printf("Length exception result %4.4X with count = %d\n", ep_status, (INT16)ep_cntres); - if (ep_status & 0x0400) - tsize = (UINT16)((INT16)tsize - (INT16)ep_cntres); - if (ep_status & 0x0800) - tsize = (UINT16)((INT16)tsize - (INT16)ep_cntres); - } - - pIRP->tx_in_progress = 0; - result = fifo_read(&pIRP->fifo, (UINT8*)buf, pIRP->tsize, 0, FIFO_NONBLOCK); - if (!result) - return; - - pIRP->cy_req.size = result; - hpi_write_ram(pIRP->cy_req.addr, (UINT16*)buf, result); - - usb_irp_enqueue(pIRP); - -// printf("Wrote %d bytes\n", result); - -} - -void rst_func(void *pArg) -{ - volatile int *pLED = (int*)SYS_LED_PORT; - -// printf("Callback with pArg = %8.8X\n", (UINT32)pArg); - sputs("SUSB_RST_MSG\n"); -/// hpi_comm_reset(); - - _g_rst = 1; - - *pLED = 0x40000000 + 1; - -} - -void sof_func(void *pArg) -{ - volatile int *pLED = (int*)SYS_LED_PORT; - -// printf("Callback with pArg = %8.8X\n", (UINT32)pArg); - sputs("SUSB_SOF_MSG\n"); - - *pLED = 0x40000000 + 2; - -} - -void cfg_func(void *pArg) -{ - volatile int *pLED = (int*)SYS_LED_PORT; - cfg_inst_t *pCFG = (cfg_inst_t*)pArg; - usb_irp_t *pIRP_rx = (usb_irp_t*)pCFG->pIRP_rx; - usb_irp_t *pIRP_tx = (usb_irp_t*)pCFG->pIRP_tx; - -// printf("Callback with pArg = %8.8X\n", (UINT32)pArg); - sputs("SUSB_CFG_MSG\n"); - _g_cfg = 1; - usb_irp_enqueue(pIRP_rx); - fifo_flush(&pIRP_rx->fifo); - fifo_flush(&pIRP_tx->fifo); - pIRP_tx->tx_in_progress = 0; - *pLED = 0; - -} - -void sus_func(void *pArg) -{ - volatile int *pLED = (int*)SYS_LED_PORT; - -// printf("Callback with pArg = %8.8X\n", (UINT32)pArg); - sputs("SUSB_SUS_MSG\n"); - - *pLED = 0x40000000 + 3; - - _g_sus = 1; - -} - -void id_func(void *pArg) -{ - volatile int *pLED = (int*)SYS_LED_PORT; - -// printf("Callback with pArg = %8.8X\n", (UINT32)pArg); - sputs("SUSB_ID_MSG\n"); - - *pLED = 0x40000000 + 4; - -} - -void vbus_func(void *pArg) -{ - volatile int *pLED = (int*)SYS_LED_PORT; - -// printf("Callback with pArg = %8.8X\n", (UINT32)pArg); - sputs("SUSB_VBUS_MSG\n"); - - *pLED = 0x40000000 + 5; - -} - -UINT32 usb_init_descr(void) -{ - UINT32 result; - - UINT16 buffer16[0x100]; - UINT16 addr; - dev_descr_t dev_descr = {sizeof(dev_descr_t), 1, 0x0200, 0xFF, 0, 0, 8, 0x04B4, 0x7200, 0x0099, 1, 2, 3, 1}; - ep_descr_t ep_descr[2] = {{sizeof(ep_descr_t), 5, 1, 2, 64, 0}, {sizeof(ep_descr_t), 5, 0x82, 2, 64, 0}}; - - // Set device descriptor - addr = 0xf516; // default - addr = 0xA00; - hpi_write_ram(addr, (UINT16*)&dev_descr, sizeof(dev_descr_t)); - hpi_write_reg(2*SUSB2_DEVICE_DESCRIPTOR_VEC, addr); - - // Set new configuration descriptor - - // Write config and interface descriptor - result = conf_write((UINT8*)buffer16, sizeof(ep_descr)/sizeof(ep_descr_t), ep_descr); - - addr = 0xf528; // default - addr = 0xB00; - hpi_write_ram(addr, (UINT16*)buffer16, result); - hpi_write_reg(2*SUSB2_CONFIGURATION_DESCRIPTOR_VEC, addr); - - // Set string description - result = str_write((UINT8*)buffer16, "JDI Inc.", "JDI-USB (MIPS)", "311070"); - addr = 0xf528; // default - addr = 0xC00; - hpi_write_ram(addr, (UINT16*)buffer16, result); - hpi_write_reg(2*SUSB2_STRING_DESCRIPTOR_VEC, addr); - - return 0; -} - -UINT32 usb_force_reconnect(UINT32 port) -{ - UINT32 result; - UINT16 addr; - - if (port >= USB_MAX_NUM_PORTS) - return -1; - - if (port == 0) - { - // R1 = 0 : Full speed - // R2 = 1 : SIE1 - addr = hpi_read_reg(SUSB1_REG_USBCTRL); - hpi_write_reg(SUSB1_REG_USBCTRL, addr | 0x0010); - result = hpi_comm_exec_int(SUSB_INIT_INT, 2, R1, 0, R2, 1); - hpi_write_reg(SUSB1_REG_USBCTRL, addr); - } - else - { - // R1 = 0 : Full speed - // R2 = 2 : SIE2 - addr = hpi_read_reg(SUSB2_REG_USBCTRL); - hpi_write_reg(SUSB2_REG_USBCTRL, addr | 0x0010); - result = hpi_comm_exec_int(SUSB_INIT_INT, 2, R1, 0, R2, 2); - hpi_write_reg(SUSB2_REG_USBCTRL, addr); - } - return result; -} - -UINT32 usb_recv(usb_irp_t *pObj, UINT8 *pData, UINT32 len, UINT32 timeout) -{ - UINT32 result; - - result = fifo_read(&pObj->fifo, pData, len, timeout, FIFO_BLOCK); - - return result; -} - -UINT32 usb_send(usb_irp_t *pObj, UINT8 *pData, UINT32 len, UINT32 timeout) -{ - UINT32 result; - UINT8 buf[USB_MAX_IMG_SIZE]; - - // Fill-up FIFO - result = fifo_write(&pObj->fifo, pData, len, 0, FIFO_NONBLOCK); - if (!result) - return 0; - - // Trigger TX - if (!pObj->tx_in_progress) - { - pObj->cy_req.size = fifo_read(&pObj->fifo, (UINT8*)buf, pObj->tsize, 0, FIFO_NONBLOCK); - hpi_write_ram(pObj->cy_req.addr, (UINT16*)buf, pObj->cy_req.size); - usb_irp_enqueue(pObj); - } - - // If necessary, write rest to FIFO - result += fifo_write(&pObj->fifo, &pData[result], len - result, timeout, FIFO_BLOCK); - - return result; - -} - -#define TEST_SIZE (2*1024*1024) -#define TRANSFER_SIZE 64 -#define FLASH_IMAGE_SIZE (2*1024*1024) - -int main(void) -{ - int i; - UINT32 result, sync, cmd, len, buf_count, led_count, remain, tx_cnt, flash_offset; - UINT8 buffer8[2048]; - UINT16 buffer16[0x2000]; - UINT16 addr; - volatile UINT32 *pLED = (UINT32*)SYS_LED_PORT; - volatile UINT32 *pUART0_stat = (UINT32*)SYS_UART0_STAT; - UINT32 start, end; - UINT32 *pFlash32; - UINT8 *pFlash8; - UINT32 buffer32[16], *pBuf; - UINT64 *pBuf64; - usb_irp_t irp_rx, irp_tx; - fifo_t fifo_rx, fifo_tx; - cfg_inst_t cfg_inst; - flash_t flash; - volatile UINT32 *pVGA_ctrl = (UINT32*)SYS_VGA_CTRL; - volatile UINT32 *pVGA_front = (UINT32*)SYS_VGA_FB_FRONT; - volatile UINT32 *pVGA_back = (UINT32*)SYS_VGA_FB_BACK; - - _g_rst = 0; - _g_sus = 0; - _g_cfg = 0; - - usb_init(); - - // enable EP#0 callback - usb_callback_register(1, SUSB_EP0_MSG, ep0_func, NULL); - - // enable EP#1 callback - usb_irp_register(&irp_rx, 1, 1, TRANSFER_SIZE, 1); - usb_callback_register(1, SUSB_EP1_MSG, ep1_func, &irp_rx); - - // enable EP#2 callback - usb_irp_register(&irp_tx, 1, 2, TRANSFER_SIZE, 0); - usb_callback_register(1, SUSB_EP2_MSG, ep2_func, &irp_tx); - - usb_callback_register(1, SUSB_RST_MSG, rst_func, NULL); - usb_callback_register(1, SUSB_SOF_MSG, sof_func, NULL); - cfg_inst.pIRP_rx = &irp_rx; - cfg_inst.pIRP_tx = &irp_tx; - usb_callback_register(1, SUSB_CFG_MSG, cfg_func, &cfg_inst); - usb_callback_register(1, SUSB_SUS_MSG, sus_func, NULL); - usb_callback_register(1, SUSB_ID_MSG, id_func, NULL); - usb_callback_register(1, SUSB_VBUS_MSG, vbus_func, NULL); - - printf("HPI-Test\n\n"); - - if (IS_ERROR(hpi_init())) - { - sputs("hpi_init(): error\n"); - return 1; - } - - printf("cy67k3_reset\n"); - cy67k3_reset(); - - while(!_g_rst); - - printf("hpi_comm_reset\n"); - hpi_comm_reset(); - - while(!_g_sus); - - printf("usb_init_descr\n"); - usb_init_descr(); - printf("hpi_comm_exec_int\n"); - hpi_comm_exec_int(SUSB_INIT_INT, 2, R1, 0, R2, 2); - printf("usb_force_reconnect\n"); - usb_force_reconnect(1); - - while(!_g_cfg); - - printf("USB-Ready\n"); - - printf("CY-Read.."); - start = clock(); - for (i=0; i < TEST_SIZE; i+=0x2000) - hpi_read_ram(0x2000, buffer16, 0x2000); - - end = clock(); - printf("done (%.2f Mbyte/s)\n", (double)TEST_SIZE/(1000*(end-start))); - - printf("CY-Write.."); - start = clock(); - for (i=0; i < TEST_SIZE; i+=0x2000) - hpi_write_ram(0x2000, buffer16, 0x2000); - - end = clock(); - printf("done (%.2f Mbyte/s)\n", (double)TEST_SIZE/(1000*(end-start))); - - sputs("HPI-Status : "); - print_word(cy67k3_read_HPI_STATUS()); - sputs("\n"); - - sputs("HPI BP : "); - print_word(hpi_read_reg(HPI_REG_BP)); - sputs("\n"); - - sputs("HPI IRR : "); - print_word(hpi_read_reg(HPI_REG_INTROUTE)); - sputs("\n"); - - sputs("CPU Revision : "); - print_word(hpi_comm_read_ctrl_reg(USB_REG_REVISON)); - sputs("\n"); - - hpi_comm_write_ctrl_reg(USB_REG_SPEED, 0x0000, LOGIC_DIRECT); - sputs("CPU Speed : "); - print_word(hpi_comm_read_ctrl_reg(USB_REG_SPEED)); - sputs("\n"); - -// usb_init_descr(); -// usb_force_reconnect(1); - - // enable RX interrupt - *pUART0_stat |= (1 << 6); - interrupt_register(3, uart_handler); - interrupt_enable(3); - - // Enable EP#1 - hpi_write_reg(SUSB2_REG_EP_COUNT1, TRANSFER_SIZE); - hpi_write_reg(SUSB2_REG_EP_CTRL1, 2); - hpi_write_reg(SUSB2_REG_EP_CNTRES1, 0); - hpi_write_reg(SUSB2_REG_EP_STATUS1, 0); - - // Enable EP#2 - hpi_write_reg(SUSB2_REG_EP_COUNT2, TRANSFER_SIZE); - hpi_write_reg(SUSB2_REG_EP_CTRL2, 2); - hpi_write_reg(SUSB2_REG_EP_CNTRES2, 0); - hpi_write_reg(SUSB2_REG_EP_STATUS2, 0); - - led_count = 0; - buf_count = 0; - - pBuf64 = (UINT64*)malloc(FLASH_IMAGE_SIZE); - pBuf = (UINT32*)pBuf64; - - *pVGA_front = (UINT32)pBuf64; - *pVGA_back = (UINT32)pBuf64; - *pVGA_ctrl |= SYS_VGA_BIT_MSTEN; - - if (IS_ERROR(flash_find(&flash, SYS_FLASH_IO))) - { - printf("Cannot find flash device. Exit now!\n"); - return 1; - } - - // Get flash offset by value of DIP-switch - flash_offset = flash_get_offset_by_blocknum(&flash, flash.info.nblocks-FLASH_IMAGE_SIZE/flash.info.blocksize); - printf("flash_offset: %08X\n", flash_offset); - pFlash32 = (UINT32*)(SYS_FLASH_IO + flash_offset); - pFlash8 = (UINT8*)pFlash32; - - while(1) - { - switch (_g_uart_msg) - { - case '1': - _g_uart_msg = 0; - PrintDevRegs(1); - printf("\nSIEmsg1: %4.4X\n", hpi_read_reg(HPI_REG_SIE1MSG)); - break; - - case '2': - _g_uart_msg = 0; - PrintDevRegs(2); - printf("\nSIEmsg2: %4.4X\n", hpi_read_reg(HPI_REG_SIE2MSG)); - break; - - default: - break; - } - result = usb_recv(&irp_rx, (UINT8*)&sync, 4, 100); - if (!result) - continue; - - *pLED = led_count++; - - if (sync == 0xC24755AA) - { - printf("Sync found\n"); - result = usb_recv(&irp_rx, (UINT8*)&cmd, 4, 1000); - if (!result) - continue; - - result = usb_recv(&irp_rx, (UINT8*)&len, 4, 1000); - if (!result) - continue; - - printf("Command %d with len %d found\n",cmd, len); - switch(cmd) - { - case 0x00000001: - result = usb_recv(&irp_rx, NULL, len, 1000); - if (result) - { - printf("Read %d bytes\n", result); - } - break; - - case 0x00000002: - remain = len; - tx_cnt = 0; - while(remain) - { - len = sizeof(buffer8); - if (remain < len) - len = remain; - - for (i=0; i < len; i++) - buffer8[i] = buf_count+i; - - result = usb_send(&irp_tx, buffer8, len, 1000); - if (!result) - break; - tx_cnt += result; - remain -= result; - buf_count++; - } - printf("Wrote %d bytes\n", tx_cnt); - break; - - case 0x00000003: - remain = len; - tx_cnt = 0; - while(remain) - { - len = 256; - if (remain < len) - len = remain; - - result = usb_send(&irp_tx, (UINT8*)&pFlash8[tx_cnt], len, 1000); - if (!result) - break; - tx_cnt += result; - remain -= result; - buf_count++; - } - printf("Wrote %d bytes\n", tx_cnt); - break; - - case 0x00000004: - *pVGA_ctrl &= ~SYS_VGA_BIT_MSTEN; - result = usb_recv(&irp_rx, (UINT8*)pBuf, len, 1000); - if (result) - { - printf("Read %d bytes\n", result); - } - - len = result; - if (len > FLASH_IMAGE_SIZE) - { - printf("Cannot write flash: image to large!\n"); - break; - } - - printf("Flash erase..."); - result = flash_erase(&flash, flash_offset, len); - if (IS_ERROR(result)) - { - printf("failed (%08X)\n", result); - break; - } - printf("done\n"); - - printf("Flash write..."); - result = flash_program(&flash, flash_offset, (UINT8*)pBuf, len); - if (IS_ERROR(result)) - { - printf("failed (%08X)\n", result); - break; - } - printf("done\n"); - - printf("Flash verify..."); - result = flash_verify(&flash, flash_offset, (UINT8*)pBuf, len); - if (IS_ERROR(result)) - { - printf("failed (%08X)\n", result); - break; - } - printf("passed\n"); - *pVGA_ctrl |= SYS_VGA_BIT_MSTEN; - break; - - case 0x000000FF: - usb_force_reconnect(1); - break; - - default: - break; - } - } - } - - return 0; -} - -// pMem = (UINT8*)0x40000000; -// result = fifo_write(&fifo_tx, pMem, 640, 0, FIFO_NONBLOCK); -// pMem += result; -// usb_irp_enqueue(&irp_tx); diff --git a/lib/CPUs/MIPS/bsp/examples/test_irq.c b/lib/CPUs/MIPS/bsp/examples/test_irq.c deleted file mode 100644 index b1a9213..0000000 --- a/lib/CPUs/MIPS/bsp/examples/test_irq.c +++ /dev/null @@ -1,335 +0,0 @@ -#include -#include -#include -#include -#include -#include - -#define CPU_FREQ_HZ 100000000 -#include "libsys.h" -#include "irq.h" -#include "mips_gfx.h" -#include "mips_ps2.h" - -char buffer[16384]; -char * volatile pPtr_r; -char * volatile pPtr_w; -static volatile INT32 mouse_x; -static volatile INT32 mouse_y; -static box_t box; -static gfx_t gfx; -static volatile int _g_posx, _g_posy; -static volatile g_btn_l, g_btn_r; -static volatile UINT32 g_color; - -// ------------------------------------------------------------- -void handler0(void) -{ - printf("Interrupt 0\n"); - interrupt_clr(0); -} - -void handler1(void) -{ - printf("Interrupt 1\n"); - interrupt_clr(1); -} - -void handler2(void) -{ - printf("Interrupt 2\n"); -} - -void handler3(void) -{ - volatile UINT32 *pUART0_stat = (UINT32*)SYS_UART0_STAT; - volatile UINT32 *pUART0_data = (UINT32*)SYS_UART0_DATA; - volatile UINT32 *pUART1_stat = (UINT32*)SYS_UART1_STAT; - volatile UINT32 *pUART1_data = (UINT32*)SYS_UART1_DATA; - - while(0x200 & *pUART0_stat) - { -// sputs("w: "); print_word((int)pPtr_w); sputs("\n"); - if (pPtr_w == &buffer[16383]) - pPtr_w = buffer; - *(pPtr_w++) = *pUART0_data; - } - - while(0x200 & *pUART1_stat) - { -// sputs("w: "); print_word((int)pPtr_w); sputs("\n"); - if (pPtr_w == &buffer[16383]) - pPtr_w = buffer; - *(pPtr_w++) = *pUART1_data; - } - -} - -void handler4(void) -{ - printf("Interrupt 4\n"); -} - -void handler5(void) -{ - UINT32 volatile *pVGA_ctrl = (UINT32*)SYS_VGA_CTRL; - - // Ack - *pVGA_ctrl |= SYS_VGA_BIT_BUFCHG_FLAG; - -} - -void handler6(void) -{ - int p, i; - ps2_if_t *pIF; - UINT8 mouse_rsp[3]; - UINT32 timeout_count, key; - - INT32 dx, dy; - - for (p=0; p < PS2_get_num_if(); p++) - { - pIF = PS2_get_if(p); - if (SYS_PS2_BIT_RX_ERR_FLAG & *pIF->pCTRL) - fprintf(stderr, "PS2[%d]: Status = 0x%08X\n", p, *pIF->pCTRL); - - if (pIF->type == ps2_type_keyb) - { - while(SYS_PS2_BIT_RX_IRQ & *pIF->pCTRL) - { - key = *pIF->pDATA; - printf("Keyboard scan code = 0x%02X\n", key); - } - } - if (pIF->type == ps2_type_mouse) - { - if(!(SYS_PS2_BIT_RX_IRQ & *pIF->pCTRL)) - continue; - - for (i=0; i < 3; i++) - { - timeout_count = 100; - while(!(SYS_PS2_BIT_RX_IRQ & *pIF->pCTRL)) - { - timeout_count--; - if (!timeout_count) - { - break; - } - sleep(1); - } - if (!timeout_count) - { - break; - } - mouse_rsp[i] = (UINT8)*pIF->pDATA; - } - if (!timeout_count) - { - continue; - } - dx = mouse_rsp[1]; - if (mouse_rsp[0] & 0x10) - dx |= 0xFFFFFF00; - dy = mouse_rsp[2]; - if (mouse_rsp[0] & 0x20) - dy |= 0xFFFFFF00; - -// printf("dx = %5d, dy = %5d\n", dx, dy); - - mouse_x += dx; - mouse_y -= dy; - g_btn_l = 0; - if (mouse_rsp[0] & 0x01) - g_btn_l = 1; - - if (mouse_rsp[0] & 0x02) - { - if (g_btn_r == 0) - { - g_color = (UINT32)rand(); - } - g_btn_r = 1; - } - else - g_btn_r = 0; - - - if (mouse_x < 0) - mouse_x = 0; - if (mouse_y < 0) - mouse_y = 0; - if (mouse_x > (gfx.w-1)) - mouse_x = gfx.w-1; - if (mouse_y >= (gfx.h-1)) - mouse_y = gfx.h-1; - -// Screen_csr_set_x(mouse_x); -// Screen_csr_set_y(mouse_y); - -// printf("x = %5d, y = %5d\n", mouse_x, mouse_y); - - } - } -} - -void handler7(void) -{ - printf("Interrupt 7\n"); -} - -int main(void) -{ - - int i; - volatile UINT32 *pUART0_stat = (UINT32*)SYS_UART0_STAT; - volatile UINT32 *pUART1_stat = (UINT32*)SYS_UART1_STAT; - volatile UINT32 *pUART0_baud = (UINT32*)SYS_UART0_BAUD; - volatile UINT32 *pUART1_baud = (UINT32*)SYS_UART1_BAUD; - UINT32 volatile *pVGA_ctrl = (UINT32*)SYS_VGA_CTRL; - UINT32 volatile *pVGA_moffs_0 = (UINT32*)SYS_VGA_FB_FRONT; - UINT32 volatile *pVGA_moffs_1 = (UINT32*)SYS_VGA_FB_BACK; - UINT32 volatile *pVGA_cgcol = (UINT32*)SYS_VGA_CGCOL; - UINT32 volatile *pFlashPicture = (UINT32*)(SYS_FLASH_MEM + 0x00600000); - UINT32 framecount; - UINT32 start, end; - char string[65]; - - interrupt_register(0, (void*)handler0); - interrupt_register(1, (void*)handler1); -// interrupt_register(2, (void*)handler2); - interrupt_register(3, (void*)handler3); -// interrupt_register(4, (void*)handler4); -// interrupt_register(5, (void*)handler5); - interrupt_register(6, (void*)handler6); - interrupt_register(7, (void*)handler7); - - srand(clock()); - UART1_setbaud(460800); - printf("Hello\n"); - memset(buffer, 0, sizeof(buffer)); - - *pVGA_cgcol = 0x00FFFFFF; - _g_posx = _g_posy = 0; - g_color = 0xFFFFFFFF; - GFX_init(&gfx); - - GFX_set_background(&gfx, pFlashPicture, 800, 600, 1, 1); - box_create(&box, 256, 256); - GFX_box_draw(&gfx, &box, _g_posx, _g_posy, g_color); - GFX_show(&gfx); - printf("VGA status = %08X\n", *pVGA_ctrl); - - pPtr_r = buffer; - pPtr_w = buffer; - - printf("UART0 Status = 0x%8.8X\n", *pUART0_stat); - printf("UART0 Baud = 0x%8.8X\n", *pUART0_baud); - printf("UART1 Status = 0x%8.8X\n", *pUART1_stat); - printf("UART1 Baud = 0x%8.8X\n", *pUART1_baud); - - // UART: enable RX interrupt - *pUART0_stat |= (1 << 6); - *pUART1_stat |= (1 << 6); - printf("UART0 Status = 0x%8.8X\n", *pUART0_stat); - printf("UART1 Status = 0x%8.8X\n", *pUART1_stat); - - PS2_init(0); - PS2_init(1); - - sputs("r: "); print_word((int)pPtr_r); sputs("\n"); - sputs("w: "); print_word((int)pPtr_w); sputs("\n"); - - // Print Status register - sputs("Status : "); - print_word(CP0_SR_read()); - sputs("\n"); - sputs("\n"); - - interrupt_disable(6); - printf("Bitte gebe ein: "); - scanf("%s", string); - printf("Du schriebst: %s\n", string); - - // Flush buffer - PS2_flush(0); - PS2_flush(1); - - printf("Start:\n"); - - interrupt_enable(0); - interrupt_enable(1); -// interrupt_enable(2); - interrupt_enable(3); -// interrupt_enable(4); -// interrupt_enable(5); - interrupt_enable(6); - interrupt_enable(7); - - interrupt_set(0); - interrupt_set(1); - interrupt_set(2); - interrupt_set(3); - interrupt_set(4); - interrupt_set(5); - interrupt_set(6); - interrupt_set(7); - -// while(1) -// { -// printf("PS2-Status : 0x%08X\n", *(ps2_if[0].pCTRL)); -// printf("PS2-Data : 0x%08X\n", *(ps2_if[0].pDATA)); -// sleep(1000); -// } - - interrupt_enable(6); - framecount = Screen_get_fps(); - start = clock(); - - while(1) - { - if (!framecount) - { - end = clock(); - framecount = Screen_get_fps(); - printf("%f FPS\n", (float)framecount/((float)(end-start)/CLOCKS_PER_SEC)); - start = clock(); - } - - GFX_frame(&gfx, GFX_FRAME_SYNC); - framecount--; - - while ((_g_posx != (UINT32)mouse_x) || (_g_posy != (UINT32)mouse_y) || g_btn_r || g_btn_l) - { - - GFX_restore(&gfx, &box, _g_posx, _g_posy); - - _g_posx = (UINT32)mouse_x; - _g_posy = (UINT32)mouse_y; - - if (g_btn_l && !g_btn_r) - { - GFX_box_draw_bg(&gfx, &box, _g_posx, _g_posy, g_color); - } - - if (g_btn_l && g_btn_r) - { - GFX_set_background(&gfx, pFlashPicture, 800, 600, 1, 1); - } - - GFX_box_draw(&gfx, &box, _g_posx, _g_posy, g_color); - break; - } - GFX_show(&gfx); - - if(pPtr_w != pPtr_r) - { -// sputs("r: "); print_word((int)pPtr_r); sputs("\n"); - if (pPtr_r == &buffer[16383]) - pPtr_r = buffer; - writechar(0, *(pPtr_r++)); - } - } - return 0; -} diff --git a/lib/CPUs/MIPS/bsp/examples/test_mipsdis.c b/lib/CPUs/MIPS/bsp/examples/test_mipsdis.c deleted file mode 100644 index eb3a61b..0000000 --- a/lib/CPUs/MIPS/bsp/examples/test_mipsdis.c +++ /dev/null @@ -1,651 +0,0 @@ -/* +----------------------------------------------------------------+ */ -/* | Copyright (c) 1994 Stanford University. | */ -/* | All Rights Reserved. | */ -/* | | */ -/* | This software is distributed with *ABSOLUTELY NO SUPPORT* | */ -/* | and *NO WARRANTY*. Use or reproduction of this code for | */ -/* | commerical gains is strictly prohibited. Otherwise, you | */ -/* | are given permission to use or modify this code as long | */ -/* | as you do not remove this notice. | */ -/* +----------------------------------------------------------------+ */ -/* --------------------------------------------------- */ -/* | Copyright (c) 1986 MIPS Computer Systems, Inc. | */ -/* | All Rights Reserved. | */ -/* --------------------------------------------------- */ - -/* - * Copyright 1985 by MIPS Computer Systems, Inc. - */ - -/* TORCH disassembler */ -/* derived from MIPS instruction dissassembler by PGL October 91 */ - -#include -#include -#include "mipsdis.h" - -#define false 0 -#define true 1 -typedef int boolean; -char *strcat(); - -#define ZERO 0 - -#define COMPILER_NAMES tdis_reg_names[0] -#define HARDWARE_NAMES tdis_reg_names[1] -#define ASSEMBLER_NAMES tdis_reg_names[2] -#define DIS_REG_NAMES(x) tdis_reg_names[x] - -union extension_byte { - unsigned char byte; - struct { /* extension byte bits in little-endian order */ -#if (defined __MIPSEB || defined _MIPSEB || defined MIPSEB) - unsigned reserved:1; - unsigned dyn_nop:1; - unsigned rs_boost:2; - unsigned rt_boost:2; - unsigned rd_boost:2; -#elif (defined __MIPSEL || defined _MIPSEL || defined MIPSEL) - unsigned rd_boost:2; - unsigned rt_boost:2; - unsigned rs_boost:2; - unsigned dyn_nop:1; - unsigned reserved:1; -#endif /*MIPSEB*/ - } e; -}; - -#define blez_op_T blez_op -#define blez_op_N (blez_op | 0x10) -#define bgtz_op_T bgtz_op -#define bgtz_op_N (bgtz_op | 0x10) -#define beq_op_T beq_op -#define beq_op_N (beq_op | 0x10) -#define bne_op_T bne_op -#define bne_op_N (bne_op | 0x10) -#define bc_op_T bc_op -#define bc_op_N (bc_op | 0x02) - -static char *op_name[64] = { -/* 0 */ "special", "regimm","j", "jal", "beq", "bne", "blez", "bgtz", -/* 8 */ "addi", "addiu","slti", "sltiu","andi", "ori", "xori", "lui", -/*16 */ "cop0", "cop1", "cop2", "cop3", "beql","bnel","blezl","bgtzl", -/*24 */ "op60", "op64", "op68", "op6c", "op70", "op74", "op78", "op7c", -/*32 */ "lb", "lh", "lwl", "lw", "lbu", "lhu", "lwr", "ld", -/*40 */ "sb", "sh", "swl", "sw", "opb0", "opb4", "swr", "sd", -/*48 */ "lwc0", "lwc1", "lwc2", "lwc3", "ldc0", "ldc1", "ldc2", "ldc3", -/*56 */ "swc0", "swc1", "swc2", "swc3", "sdc0", "sdc1", "sdc2", "sdc3" -}; - -static char *spec_name[64] = { -/* 0*/ "sll", "spec01","srl", "sra", "sllv", "spec05","srlv","srav", -/* 8*/ "jr", "jalr", "spec12","spec13","syscall","break","vcall","spec17", -/*16*/ "mfhi", "mthi", "mflo", "mtlo", "spec24","spec25","spec26","spec27", -/*24*/ "mult", "multu","div", "divu", "spec34","spec35","spec36","spec37", -/*32*/ "add", "addu", "sub", "subu", "and", "or", "xor", "nor", -/*40*/ "spec50","spec51","slt","sltu", "spec54","spec55","spec56","spec57", -/*48*/ "spec60","spec61","spec62","spec63","spec64","spec65","spec66","spec67", -/*56*/ "spec70","spec71","spec72","spec73","spec74","spec75","spec76","spec77" -}; - -static char *bcond_name[32] = { - "bltz", - "bgez", - "bltzl", - "bgezl", - "bcond04", - "bcond05", - "bcond06", - "bcond07", - "tgei", - "tgeiu", - "tlti", - "tltiu", - "teqi", - "bcond0d", - "tnei", - "bcond0f", - "bltzal", - "bgezal", - "bltzall", - "bgezall", - "bcond14", - "bcond15", - "bcond16", - "bcond17", - "bcond18", - "bcond19", - "bcond1a", - "bcond1b", - "bcond1c", - "bcond1d", - "bcond1e", - "bcond1f" -}; - -static char *cop1_name[64] = { -/* 0 */ "add", "sub", "mul", "div", "sqrt", "abs", "mov", "neg", -/* 8 */ "fop08","fop09","fop0a","fop0b","fop0c","fop0d","fop0e","fop0f", -/*16 */ "fop10","fop11","fop12","fop13","fop14","fop15","fop16","fop17", -/*24 */ "fop18","fop19","fop1a","fop1b","fop1c","fop1d","fop1e","fop1f", -/*32 */ "cvt.s","cvt.d","cvt.e","fop23","cvt.w","fop25","fop26","fop27", -/*40 */ "fop28","fop29","fop2a","fop2b","fop2c","fop2d","fop2e","fop2f", -/*48 */ "c.f", "c.un","c.eq","c.ueq","c.olt","c.ult","c.ole","c.ule", -/*56 */ "c.sf","c.ngle","c.seq","c.ngl","c.lt","c.nge","c.le","c.ngt" -}; - -static char *fmt_name[16] = { - "s", "d", "e", "q", - "w", "fmt5", "fmt6", "fmt7", - "fmt8", "fmt9", "fmta", "fmtb", - "fmtc", "fmtd", "fmte", "fmtf" -}; - -/* public */ -/* Three sets of commonly used register names */ -const char *tdis_reg_names[3][64] = { - { /* compiler names */ - "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", - "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", - "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", - "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", - "zero.B","at.B","v0.B", "v1.B", "a0.B", "a1.B", "a2.B", "a3.B", - "t0.B", "t1.B", "t2.B", "t3.B", "t4.B", "t5.B", "t6.B", "t7.B", - "s0.B", "s1.B", "s2.B", "s3.B", "s4.B", "s5.B", "s6.B", "s7.B", - "t8.B", "t9.B", "k0.B", "k1.B", "gp.B", "sp.B", "s8.B", "ra.B" - }, - { /* hardware names */ - "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", - "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", - "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", - "r24", "r25", "r26", "r27", "gp", "sp", "r30", "r31", - "r0.B", "r1.B", "r2.B", "r3.B", "r4.B", "r5.B", "r6.B", "r7.B", - "r8.B", "r9.B", "r10.B","r11.B","r12.B","r13.B","r14.B","r15.B", - "r16.B","r17.B","r18.B","r19.B","r20.B","r21.B","r22.B","r23.B", - "r24.B","r25.B","r26.B","r27.B","gp.B", "sp.B", "r30.B","r31.B" - }, - { /* assembler names */ - "$0", "$at", "$2", "$3", "$4", "$5", "$6", "$7", - "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", - "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", - "$24", "$25", "$26", "$27", "$gp", "$sp", "$30", "$31", - "$0.B", "$at.B","$2.B", "$3.B", "$4.B", "$5.B", "$6.B", "$7.B", - "$8.B", "$9.B", "$10.B","$11.B","$12.B","$13.B","$14.B","$15.B", - "$16.B","$17.B","$18.B","$19.B","$20.B","$21.B","$22.B","$23.B", - "$24.B","$25.B","$26.B","$27.B","$gp.B","$sp.B","$30.B","$31.B" - } -}; - -static char *c0_opname[64] = { - "c0op0","tlbr","tlbwi","c0op3","c0op4","c0op5","tlbwr","c0op7", - "tlbp","c0op9","c0op10","c0op11","c0op12","c0op13","c0op14","c0op15", - "rfe","c0op17","c0op18","c0op19","c0op20","c0op21","c0op22","c0op23", - "c0op24","c0op25","c0op26","c0op27","c0op28","c0op29","c0op30","c0op31", - "c0op32","c0op33","c0op34","c0op35","c0op36","c0op37","c0op38","c0op39", - "c0op40","c0op41","c0op42","c0op43","c0op44","c0op45","c0op46","c0op47", - "c0op48","c0op49","c0op50","c0op51","c0op52","c0op53","c0op54","c0op55", - "c0op56","c0op57","c0op58","c0op59","c0op60","c0op61","c0op62","c0op63" -}; - -static char *c0_reg[32] = { - "index","random","tlblo","c0r3","context","c0r5","c0r6","c0r7", - "badvaddr","c0r9","tlbhi","epcn","sr", "cause","epc", "c0r15", - "c0r16","c0r17","c0r18","c0r19","c0r20","c0r21","c0r22","c0r23", - "c0r24","c0r25","c0r26","c0r27","c0r28","c0r29","c0r30","c0r31" -}; - -/* Remember the options set by dis_init */ -#define ADDR_DEFAULT 0 -//#define ADDR_DEFAULT "%#010x:\t" -//#define VALUE_DEFAULT "%#010x\t" -#define VALUE_DEFAULT 0 -#define NAME_DEFAULT COMPILER_NAMES -static struct { - char *addr_format; - char *value_format; - const char **reg_names; - int print_jal_targets; -} save = { - ADDR_DEFAULT, - VALUE_DEFAULT, - NAME_DEFAULT, - true -}; - -/* Update regmask to reflect the use of this general-purpose (not fp) - register, and return its name */ -static const char * -register_name(ireg, boosted, regmask) -unsigned ireg, *regmask; -int boosted; -{ - if (!boosted) - *regmask |= (1 << ireg); - return save.reg_names[boosted ? ireg + 32 : ireg]; -} - -/* public -- see dissassembler.h */ -int -tdisasm(buffer, address, iword, ext, regmask, symbol_value, ls_register) -char *buffer; -unsigned char ext; /* extension byte */ -unsigned address, iword, *regmask, *symbol_value, *ls_register; -{ - int return_value = 0; - char *bufptr = buffer; - boolean do_b_displacement = false; - boolean do_loadstore = false; - union mips_instruction i; - union extension_byte e; - - *bufptr = 0; - i.word = iword; - e.byte = ext; - *regmask = *symbol_value = *ls_register = 0; - - /* Put out the address and hex value of the instruction, - leaving bufptr set at the end */ - if (save.addr_format) { - sprintf(bufptr, save.addr_format, address); - bufptr += strlen(bufptr); - } - if (save.value_format) { - sprintf(bufptr, save.value_format, iword); - bufptr += strlen(bufptr); - } - - /* check for dynamic NOP */ - if (e.e.dyn_nop) { - strcat(bufptr, "D."); - bufptr += 2; - } - - /* decode the instruction */ - switch (i.j_format.opcode) { - - case spec_op: - - if (i.word == 0x20) { - strcat(bufptr, "nop"); - if (e.e.rd_boost) - strcat(bufptr, ".B"); - bufptr += strlen(bufptr); - break; - } else if (i.r_format.func == addu_op && i.r_format.rt == ZERO) { - sprintf(bufptr, "move%s\t%s,%s", - e.e.rd_boost ? ".B" : "", - register_name(i.r_format.rd, e.e.rd_boost, regmask), - register_name(i.r_format.rs, e.e.rs_boost, regmask)); - bufptr += strlen(bufptr); - break; - } - strcat(bufptr, spec_name[i.r_format.func]); - if (e.e.rd_boost) - strcat(bufptr, ".B"); - bufptr += strlen(bufptr); - - switch (i.r_format.func) { - case sll_op: - case srl_op: - case sra_op: - sprintf(bufptr, "\t%s,%s,%d", - register_name(i.r_format.rd, e.e.rd_boost, regmask), - register_name(i.r_format.rt, e.e.rt_boost, regmask), - i.r_format.re); - break; - case sllv_op: - case srlv_op: - case srav_op: - sprintf(bufptr, "\t%s,%s,%s", - register_name(i.r_format.rd, e.e.rd_boost, regmask), - register_name(i.r_format.rt, e.e.rt_boost, regmask), - register_name(i.r_format.rs, e.e.rs_boost, regmask)); - break; - case mfhi_op: - case mflo_op: - sprintf(bufptr, "\t%s", - register_name(i.r_format.rd, e.e.rd_boost, regmask)); - break; - case jalr_op: - return_value = 2; - sprintf(bufptr, "\t%s,%s", - register_name(i.r_format.rd, e.e.rd_boost, regmask), - register_name(i.r_format.rs, e.e.rs_boost, regmask)); - break; - case jr_op: - return_value = 2; - /* fall through */ - case mtlo_op: - case mthi_op: - sprintf(bufptr, "\t%s", - register_name(i.r_format.rs, e.e.rs_boost, regmask)); - break; - case mult_op: - case multu_op: - case div_op: - case divu_op: - sprintf(bufptr, "\t%s,%s", - register_name(i.r_format.rs, e.e.rs_boost, regmask), - register_name(i.r_format.rt, e.e.rt_boost, regmask)); - break; - case syscall_op: - break; - case break_op: - case vcall_op: - { - char *format = "\t%d"; - unsigned op2 = i.r_format.rd * 32 + i.r_format.re; - - if (op2) - format = "\t%d,%d"; - sprintf(bufptr, format, i.r_format.rs*32+i.r_format.rt, - op2); - } - break; - default: - sprintf(bufptr, "\t%s,%s,%s", - register_name(i.r_format.rd, e.e.rd_boost, regmask), - register_name(i.r_format.rs, e.e.rs_boost, regmask), - register_name(i.r_format.rt, e.e.rt_boost, regmask)); - break; - }; - break; - - case bcond_op: - sprintf(bufptr, "%s%s\t%s,", - bcond_name[i.i_format.rt], - e.e.rd_boost ? ".B" : "", - register_name(i.i_format.rs, e.e.rs_boost, regmask)); - do_b_displacement = true; - break; - - case blez_op_T: - case bgtz_op_T: - case blez_op_N: - case bgtz_op_N: - sprintf(bufptr, "%s%s\t%s,", op_name[i.i_format.opcode], - e.e.rd_boost ? ".B" : "", - register_name(i.i_format.rs, e.e.rs_boost, regmask)); - do_b_displacement = true; - break; - case beq_op_T: - case beq_op_N: - if (i.i_format.rs == ZERO && i.i_format.rt == ZERO) { - strcat(bufptr, "b"); - if (i.j_format.opcode == beq_op_T) - strcat(bufptr, ".T"); - else - strcat(bufptr, ".N"); - if (e.e.rd_boost) - strcat(bufptr, ".B\t"); - else - strcat(bufptr, "\t"); - do_b_displacement = true; - break; - } - /* fall through */ - case bne_op_T: - case bne_op_N: - sprintf(bufptr, "%s%s\t%s,%s,", op_name[i.i_format.opcode], - e.e.rd_boost ? ".B" : "", - register_name(i.i_format.rs, e.e.rs_boost, regmask), - register_name(i.i_format.rt, e.e.rt_boost, regmask)); - do_b_displacement = true; - break; - - case cop0_op: - case cop1_op: - case cop2_op: - case cop3_op: - { - unsigned which_cop = i.j_format.opcode - cop0_op; - char *f_or_r = "rf"; - - switch (i.r_format.rs) { - case bc_op_T: - sprintf(bufptr, "bc%d%c.T%s\t", which_cop, - "ft"[i.r_format.rt], - e.e.rd_boost ? ".B" : ""); - do_b_displacement = true; - break; - case bc_op_N: - sprintf(bufptr, "bc%d%c.N%s\t", which_cop, - "ft"[i.r_format.rt], - e.e.rd_boost ? ".B" : ""); - do_b_displacement = true; - break; - case mtc_op: - if (which_cop == 0) - sprintf(bufptr, "mtc%d%s\t%s,%s", which_cop, - e.e.rd_boost ? ".B" : "", - register_name(i.r_format.rt, e.e.rt_boost,regmask), - c0_reg[i.f_format.rd]); - else - sprintf(bufptr, "mtc%d%s\t%s,%c%d", which_cop, - e.e.rd_boost ? ".B" : "", - register_name(i.r_format.rt, e.e.rt_boost,regmask), - f_or_r[(which_cop == 1)], - i.f_format.rd); - break; - case mfc_op: - if (which_cop == 0) - sprintf(bufptr, "mfc%d%s\t%s,%s", which_cop, - e.e.rd_boost ? ".B" : "", - register_name(i.r_format.rt, e.e.rt_boost,regmask), - c0_reg[i.f_format.rd]); - else - sprintf(bufptr, "mfc%d%s\t%s,%c%d", which_cop, - e.e.rd_boost ? ".B" : "", - register_name(i.r_format.rt, e.e.rt_boost,regmask), - f_or_r[(which_cop == 1)], - i.f_format.rd); - break; - case cfc_op: - sprintf(bufptr, "cfc%d%s\t%s,%c%d", which_cop, - e.e.rd_boost ? ".B" : "", - register_name(i.r_format.rt, e.e.rt_boost, regmask), - f_or_r[(which_cop == 1)], - i.f_format.rd); - break; - case ctc_op: - sprintf(bufptr, "ctc%d%s\t%s,%c%d", which_cop, - e.e.rd_boost ? ".B" : "", - register_name(i.r_format.rt, e.e.rt_boost, regmask), - f_or_r[(which_cop == 1)], - i.f_format.rd); - break; - default: - if (which_cop != 1) - sprintf(bufptr, "c0%s\t%s", e.e.rd_boost ? ".B" : "", - c0_opname[i.f_format.func]); - else - { - sprintf(bufptr, "%s.%s%s\t", - cop1_name[i.f_format.func], - fmt_name[i.f_format.fmt], - e.e.rd_boost ? ".B" : ""); - bufptr += strlen(bufptr); - switch (i.f_format.func) { - case fsqrt_op: - case fabs_op: - case fmov_op: - case fcvts_op: - case fcvtd_op: - case fcvte_op: - case fcvtw_op: - sprintf(bufptr, "f%d,f%d", - i.f_format.re, - i.f_format.rd); - break; - case fcmp_op+0x0: - case fcmp_op+0x1: - case fcmp_op+0x2: - case fcmp_op+0x3: - case fcmp_op+0x4: - case fcmp_op+0x5: - case fcmp_op+0x6: - case fcmp_op+0x7: - case fcmp_op+0x8: - case fcmp_op+0x9: - case fcmp_op+0xa: - case fcmp_op+0xb: - case fcmp_op+0xc: - case fcmp_op+0xd: - case fcmp_op+0xe: - case fcmp_op+0xf: - sprintf(bufptr, "f%d,f%d", - i.f_format.rd, - i.f_format.rt); - break; - default: - sprintf(bufptr, "f%d,f%d,f%d", - i.f_format.re, - i.f_format.rd, - i.f_format.rt); - break; - } /* switch on func */ - } - break; /* End of default */ - } /* switch on rs */ - } - break; /* End of cop0, cop1, cop2, cop3 */ - - case jal_op: - case j_op: - sprintf(bufptr, "%s%s\t", op_name[i.j_format.opcode], - e.e.rd_boost ? ".B" : ""); - *symbol_value = (address & 0xF0000000) | i.j_format.target << 2; - if (save.print_jal_targets) - { - bufptr += strlen(bufptr); - sprintf(bufptr, "%#x", *symbol_value); - } - return_value = 1; - break; - - case swc1_op: - case sdc1_op: - case lwc1_op: - case ldc1_op: - sprintf(bufptr, "%s%s\tf%d,", op_name[i.i_format.opcode], - e.e.rd_boost ? ".B" : "", - i.i_format.rt); - do_loadstore = true; - break; - - case lb_op: - case lh_op: - case lw_op: - case ld_op: - case lbu_op: - case lhu_op: - case sb_op: - case sh_op: - case sw_op: - case sd_op: - case lwl_op: - case lwr_op: - sprintf(bufptr, "%s%s\t%s,", op_name[i.i_format.opcode], - e.e.rd_boost ? ".B" : "", - register_name(i.i_format.rt, e.e.rt_boost, regmask)); - do_loadstore = true; - break; - - case ori_op: - case xori_op: - if (i.u_format.rs == ZERO) { - sprintf(bufptr, "li%s\t%s,%d", - e.e.rd_boost ? ".B" : "", - register_name(i.u_format.rt, e.e.rt_boost, regmask), - i.u_format.uimmediate); - break; - } - /* fall through */ - case andi_op: - sprintf(bufptr, "%s%s\t%s,%s,%#x", op_name[i.u_format.opcode], - e.e.rd_boost ? ".B" : "", - register_name(i.u_format.rt, e.e.rt_boost, regmask), - register_name(i.u_format.rs, e.e.rs_boost, regmask), - i.u_format.uimmediate); - break; - case lui_op: - sprintf(bufptr, "%s%s\t%s,%#x", op_name[i.u_format.opcode], - e.e.rd_boost ? ".B" : "", - register_name(i.u_format.rt, e.e.rt_boost, regmask), - i.u_format.uimmediate); - break; - case addi_op: - case addiu_op: - if (i.i_format.rs == ZERO) { - short sign_extender = i.i_format.simmediate; - sprintf(bufptr, "li%s\t%s,%d", - e.e.rd_boost ? ".B" : "", - register_name(i.i_format.rt, e.e.rt_boost, regmask), - sign_extender); - break; - } - /* fall through */ - default: - { - short sign_extender = i.i_format.simmediate; - sprintf(bufptr, "%s%s\t%s,%s,%d", op_name[i.i_format.opcode], - e.e.rd_boost ? ".B" : "", - register_name(i.i_format.rt, e.e.rt_boost, regmask), - register_name(i.i_format.rs, e.e.rs_boost, regmask), - sign_extender); - } - break; - } - - /* Some instructions require more than just registers */ - - if (do_loadstore) - { - short sign_extender = i.i_format.simmediate; - *symbol_value = sign_extender; - *ls_register = i.i_format.rs; - bufptr += strlen(bufptr); - sprintf(bufptr, "%d(%s)", sign_extender, - register_name(i.i_format.rs, e.e.rs_boost, regmask)); - return_value = -1; - } - else if (do_b_displacement) - { - short sign_extender = i.i_format.simmediate; - bufptr += strlen(bufptr); - sprintf(bufptr, "%#x", 4 + address + ((((long)sign_extender & 0xFFFD0000) | (0x3FFFF & (sign_extender << 2))))); -// sprintf(bufptr, "%#x", (long)sign_extender); - return_value = 2; - } - - return return_value; -} - -static long instrs[10]={ - 0x0411000a, - 0x03e0f021, - 0x02feb023, - 0x24010050, - 0x10360044, - 0x24010090, - 0x10360046, - 0x240100b8, - 0x10360048, - 0x240100d0 - }; - -int main(void) -{ - int i; - int junk; - char buf[80]; - long *pInstr = (long*)instrs; - - for (i=0; i < 10; i++) - { - tdisasm(buf, (long)&pInstr[i], pInstr[i], 0, &junk, &junk, &junk); - printf("%s\n", buf); - } - return 0; - -} diff --git a/lib/CPUs/MIPS/bsp/examples/test_timer.c b/lib/CPUs/MIPS/bsp/examples/test_timer.c deleted file mode 100644 index 91b5a78..0000000 --- a/lib/CPUs/MIPS/bsp/examples/test_timer.c +++ /dev/null @@ -1,40 +0,0 @@ -#include "libsys.h" - - -int g_cnt; -void handler7(void) -{ - UINT32 *pGPIO0 = (UINT32*)SYS_GPIO0; - UINT32 *pTim_stat = (UINT32*)SYS_ITIM_STAT; - if (*pTim_stat & 1) - { - *pTim_stat = 1; - *pGPIO0 = g_cnt++; - } - -} - -int main (void) -{ - UINT32 *pTim_ctrl = (UINT32*)SYS_ITIM_CTRL; - UINT32 *pTim_stat = (UINT32*)SYS_ITIM_STAT; - UINT32 *pTim_cnt = (UINT32*)SYS_ITIM_CNT; - UINT32 *pTim_cmp = (UINT32*)SYS_ITIM_CMP; - UINT32 *pGPIO0 = (UINT32*)SYS_GPIO0; - - g_cnt = 1; - *pGPIO0 = 0; - - interrupt_register(7, handler7); - interrupt_enable(7); - - *pTim_cnt = 0; - *pTim_cmp = 2000; - *pTim_stat = 1; - *pTim_ctrl = 3; - - while(1); - - return 0; -} - diff --git a/lib/CPUs/MIPS/bsp/examples/test_vga.c b/lib/CPUs/MIPS/bsp/examples/test_vga.c deleted file mode 100644 index 7919abd..0000000 --- a/lib/CPUs/MIPS/bsp/examples/test_vga.c +++ /dev/null @@ -1,206 +0,0 @@ -#include -#include -#include -#include -#include -#include - -#define CPU_FREQ_HZ 100000000 -#include "libsys.h" -#include "irq.h" -#include "mips_gfx.h" -#include "mips_ps2.h" - -static volatile INT32 mouse_x; -static volatile INT32 mouse_y; -static box_t box; -static gfx_t gfx; -static volatile int _g_posx, _g_posy; -static volatile g_btn_l, g_btn_r; -static volatile UINT32 g_color; - -// ------------------------------------------------------------- -void handler5(void) -{ - UINT32 volatile *pVGA_ctrl = (UINT32*)SYS_VGA_CTRL; - - // Ack - *pVGA_ctrl |= SYS_VGA_BIT_BUFCHG_FLAG; - -} - -void handler6(void) -{ - int p, i; - ps2_if_t *pIF; - UINT8 mouse_rsp[3]; - UINT32 timeout_count, key; - - INT32 dx, dy; - - for (p=0; p < PS2_get_num_if(); p++) - { - pIF = PS2_get_if(p); - if (SYS_PS2_BIT_RX_ERR_FLAG & *pIF->pCTRL) - fprintf(stderr, "PS2[%d]: Status = 0x%08X\n", p, *pIF->pCTRL); - - if (pIF->type == ps2_type_keyb) - { - while(SYS_PS2_BIT_RX_IRQ & *pIF->pCTRL) - { - key = *pIF->pDATA; - printf("Keyboard scan code = 0x%02X\n", key); - } - } - if (pIF->type == ps2_type_mouse) - { - if(!(SYS_PS2_BIT_RX_IRQ & *pIF->pCTRL)) - continue; - - for (i=0; i < 3; i++) - { - timeout_count = 100; - while(!(SYS_PS2_BIT_RX_IRQ & *pIF->pCTRL)) - { - timeout_count--; - if (!timeout_count) - { - break; - } - sleep(1); - } - if (!timeout_count) - { - break; - } - mouse_rsp[i] = (UINT8)*pIF->pDATA; - } - if (!timeout_count) - { - continue; - } - dx = mouse_rsp[1]; - if (mouse_rsp[0] & 0x10) - dx |= 0xFFFFFF00; - dy = mouse_rsp[2]; - if (mouse_rsp[0] & 0x20) - dy |= 0xFFFFFF00; - -// printf("dx = %5d, dy = %5d\n", dx, dy); - - mouse_x += dx; - mouse_y -= dy; - g_btn_l = 0; - if (mouse_rsp[0] & 0x01) - g_btn_l = 1; - - if (mouse_rsp[0] & 0x02) - { - if (g_btn_r == 0) - { - g_color = (UINT32)rand(); - } - g_btn_r = 1; - } - else - g_btn_r = 0; - - - if (mouse_x < 0) - mouse_x = 0; - if (mouse_y < 0) - mouse_y = 0; - if (mouse_x > (gfx.w-1)) - mouse_x = gfx.w-1; - if (mouse_y >= (gfx.h-1)) - mouse_y = gfx.h-1; - -// Screen_csr_set_x(mouse_x); -// Screen_csr_set_y(mouse_y); - -// printf("x = %5d, y = %5d\n", mouse_x, mouse_y); - - } - } -} - -int main(void) -{ - - int i; - UINT32 volatile *pVGA_ctrl = (UINT32*)SYS_VGA_CTRL; - UINT32 volatile *pVGA_moffs_0 = (UINT32*)SYS_VGA_FB_FRONT; - UINT32 volatile *pVGA_moffs_1 = (UINT32*)SYS_VGA_FB_BACK; - UINT32 volatile *pVGA_cgcol = (UINT32*)SYS_VGA_CGCOL; - UINT32 volatile *pFlashPicture = (UINT32*)(SYS_FLASH_MEM + 0x00600000); - UINT32 framecount; - UINT32 start, end; - - interrupt_register(5, (void*)handler5); - interrupt_register(6, (void*)handler6); - - srand(clock()); - UART1_setbaud(460800); - - *pVGA_cgcol = 0x00FFFFFF; - _g_posx = _g_posy = 0; - g_color = 0xFFFFFFFF; - GFX_init(&gfx); - - GFX_set_background(&gfx, pFlashPicture, 800, 600, 1, 1); - box_create(&box, 256, 256); - GFX_box_draw(&gfx, &box, _g_posx, _g_posy, g_color); - GFX_show(&gfx); - printf("VGA status = %08X\n", *pVGA_ctrl); - - PS2_init(0); - PS2_init(1); - - // Flush buffer - PS2_flush(0); - PS2_flush(1); - -// interrupt_enable(5); - interrupt_enable(6); - - framecount = Screen_get_fps(); - start = clock(); - - while(1) - { - if (!framecount) - { - end = clock(); - framecount = Screen_get_fps(); - printf("%f FPS\n", (float)framecount/((float)(end-start)/CLOCKS_PER_SEC)); - start = clock(); - } - - GFX_frame(&gfx, GFX_FRAME_SYNC); - framecount--; - - while ((_g_posx != (UINT32)mouse_x) || (_g_posy != (UINT32)mouse_y) || g_btn_r || g_btn_l) - { - - GFX_restore(&gfx, &box, _g_posx, _g_posy); - - _g_posx = (UINT32)mouse_x; - _g_posy = (UINT32)mouse_y; - - if (g_btn_l && !g_btn_r) - { - GFX_box_draw_bg(&gfx, &box, _g_posx, _g_posy, g_color); - } - - if (g_btn_l && g_btn_r) - { - GFX_set_background(&gfx, pFlashPicture, 800, 600, 1, 1); - } - - GFX_box_draw(&gfx, &box, _g_posx, _g_posy, g_color); - break; - } - GFX_show(&gfx); - } - return 0; -} diff --git a/lib/CPUs/MIPS/bsp/examples/testbench.c b/lib/CPUs/MIPS/bsp/examples/testbench.c deleted file mode 100644 index 15d921d..0000000 --- a/lib/CPUs/MIPS/bsp/examples/testbench.c +++ /dev/null @@ -1,1229 +0,0 @@ -#include -#include -#include -#include -#include -#include -#include -#include "libsys.h" -#include "mips_gfx.h" - -#define TEST10_ERROR (ERROR | 0x1000) -#define TEST11_ERROR (ERROR | 0x1100) -#define TEST12_ERROR (ERROR | 0x1200) -#define TEST13_ERROR (ERROR | 0x1300) -#define TEST14_ERROR (ERROR | 0x1400) -#define TEST15_ERROR (ERROR | 0x1500) -#define TEST16_ERROR (ERROR | 0x1600) - -#define PIC_NX 800 -#define PIC_NY 600 - -extern int paranoia(int argc, char **argv); - -UINT32* pf(void) -{ - static UINT32 p; - - return &p; -} - -volatile UINT32 _g_blitter_rdy; -void ISR_blitter_rdy(void) -{ - UINT32 volatile *pVGA_ctrl = (UINT32*)SYS_VGA_CTRL; - - if (*pVGA_ctrl & SYS_VGA_BIT_BLIT_FIN) - { - putchar('.'); - // Ack - *pVGA_ctrl |= SYS_VGA_BIT_BLIT_ACK; - _g_blitter_rdy = 1; - } -} - -// ------------------------------------------------------------- -void LoadPic(UINT64 *pScreen, UINT32 screen_nx, UINT32 screen_ny, UINT32 *pImage, UINT32 image_nx, UINT32 image_ny, UINT32 image_scale_x, UINT32 image_scale_y) -{ - - UINT32 off_x, off_y; - UINT32 i, j, black; - UINT32 *pScr, *pImg; - - off_x = (screen_nx-(image_scale_x*image_nx))/2; - off_y = (screen_ny-(image_scale_y*image_ny))/2; - - black = 0; - pScr = (UINT32*)pScreen; - for (i=0; i < screen_nx*screen_ny; i += 8) - { - __gfx_block_set_8(pScr, 0); - pScr += 8; - } - - if (!pImage) - return; - - pScr = ((UINT32*)pScreen) + screen_nx*off_y + off_x; - pImg = pImage; - - for (i=0; i < image_ny*image_nx; i += 8) - { - __gfx_block_copy_8(pScr, pImg); - pScr += 8; - pImg += 8; - } - -/* - UINT32 off_x, off_y; - UINT32 i; - UINT32 *pScr; - - off_x = (screen_nx-(image_scale_x*image_nx))/2; - off_y = (screen_ny-(image_scale_y*image_ny))/2; - - memset(pScreen, 0, screen_nx*screen_ny*sizeof(UINT32)); - pScr = ((UINT32*)pScreen) + screen_nx*off_y + off_x; - - for (i=0; i < image_ny; i++) - { - memcpy(pScr, &pImage[i*image_nx], image_nx*sizeof(UINT32)); - pScr += screen_nx; - } -*/ -} - -int IsEndianBig(void) -{ - UINT8 *pBuf; - UINT32 word; - word = 0x12345678; - pBuf = (UINT8*)&word; - if (((*pBuf+0) == 0x12) && (*(pBuf+1) == 0x34) && (*(pBuf+2) == 0x56) && (*(pBuf+3) == 0x78)) - { - return 1; - } - if (((*pBuf+0) == 0x78) && (*(pBuf+1) == 0x56) && (*(pBuf+2) == 0x34) && (*(pBuf+3) == 0x12)) - { - return 0; - } - return -1; -} - -void handler3(void) -{ - volatile UINT32 *pUART_stat = (UINT32*)SYS_UART_STAT; - volatile UINT32 *pUART_data = (UINT32*)SYS_UART_DATA; - - if((0x10 & *pUART_stat)) - { - _putchar(0, (char)*pUART_data); - } - -} - -int g_cnt; -box_t box; -gfx_t gfx; -int posx, posy; - -void handler7(void) -{ - UINT32 volatile *pGPIO0 = (UINT32*)SYS_GPIO0; - UINT32 volatile *pTim_stat = (UINT32*)SYS_ITIM_STAT; - UINT32 volatile *pTim_ctrl = (UINT32*)SYS_ITIM_CTRL; - UINT32 volatile *pTim0_cmp = (UINT32*)SYS_ITIM0_CMP; - time_t curr_date; - struct tm *pDate; - - if (*pTim0_cmp < 0x200) - { - *pTim0_cmp = 0x200; - } - if (*pTim_stat & 1) - { - *pTim_stat = 1; - *pGPIO0 = g_cnt++; - GFX_frame(&gfx, GFX_FRAME_NOSYNC); - GFX_restore(&gfx, &box, posx, posy); - GFX_show(&gfx); - - posx = (UINT32)rand()%800; - posy = (UINT32)rand()%600; - GFX_frame(&gfx, GFX_FRAME_NOSYNC); - GFX_box_draw(&gfx, &box, posx, posy, (UINT32)rand()); - GFX_show(&gfx); - } - - if (*pTim_stat & 4) - { - *pTim_stat = 4; - curr_date = time(NULL); - pDate = gmtime(&curr_date); - fprintf(stderr, "%s", asctime(pDate)); - } - -} - -int fibonacci(int f0, int f1, int *pDst, int len) -{ - int i; - - i = 0; - - pDst[i++] = f0; - pDst[i++] = f1; - - for (; i < len; i++) - { - pDst[i] = pDst[i-2] + pDst[i-1]; - } - - return i; -} - -void PrintCPUinfo(void) -{ - int result, rev_id; - int cache_size, cache_line; - int eb; - - char *cpu_type_str[7] = {"invalid", "R2000", "R3000", "R6000", "R4000", "reserved", "R6000A"}; - - // Print Status register - result = CP0_SR_read(); - - printf("--------------------------------------------------\n"); - printf("Status : %8.8X\n", result); - - // Print Revision - result = CP0_PRID_read(); - rev_id = (result >> 8) & 0xFF; - printf("CPU type : MIPS "); - if ((rev_id > 0) && (rev_id < 0x07)) - { - printf(cpu_type_str[rev_id]); - printf(" Rev. "); - rev_id = result & 0xFF; - printf("%d", rev_id); - } - else - printf("Unknown"); - - eb = IsEndianBig(); - if (eb) - printf(" [Big-endian]\n"); - if (!eb) - printf(" [Little-endian]\n"); - if (eb < 0) - printf(" [Unknown endian]\n"); - - cache_size = (result >> 16) & 7; - cache_line = (result >> 19) & 7; - printf("I-Cache : %d kBytes (%d Bytes per line)\n", 4*(int)pow(2.0, (double)(8+cache_size))/1024, 4*(int)pow(2.0, (double)(cache_line))); - cache_size = (result >> 24) & 7; - cache_line = (result >> 27) & 7; - printf("D-Cache : %d kBytes (%d Bytes per line)\n", 4*(int)pow(2.0, (double)(8+cache_size))/1024, 4*(int)pow(2.0, (double)(cache_line))); - printf("--------------------------------------------------\n"); - -} - -UINT32 uncached_cachemiss_bug(void) -{ - UINT32 result; - UINT32 pMem[2]; - - pMem[0] = 0x12345678; - pMem[1] = 0xFFFFFFFF; - - __asm__ - ( - "cop0 34\n" - "lui $s0, 0xA000\n" - "lw $a0, 48($s0)\n" - "or $s1, $a0, $0\n" - "or $a2, $0, $0\n" - "addiu $a2, 0x7F00\n" - "sw $a2, 48($s0)\n" -// "lw $a1, 0(%[pMem])\n" - "lw $a0, 48($s0)\n" - "lw $a2, 4(%[pMem])\n" - "lw $a1, 0(%[pMem])\n" - "nop\n" - "sw $s1, 48($s0)\n" - "or %[val], $a0, $0\n" - : [val] "=r" (result) - : [pMem] "r" (pMem) - : "a0", "a1", "a2", "s0", "s1" - ); - return result; -} - -UINT32 non_aligned_load() -{ - UINT32 result; - UINT32 pMem[3]; - - __asm__ - ( - "li $t0, 0x01234567\n" - "li $t1, 0x89ABCDEF\n" - "sw $t0, 0(%[pMem])\n" - "sw $t1, 4(%[pMem])\n" - "li %[val], 0x55555555\n" - "lw %[val], 0(%[pMem])\n" - "lwl %[val], 5(%[pMem])\n" - : [val] "=r" (result) - : [pMem] "r" (pMem) - : "t0", "t1" - ); - - if (0 == IsEndianBig()) - { - if (0xCDEF4567 != result) - return ERROR; - } - else - { - if (0xABCDEF67 != result) - return ERROR; - } - return 0; - -} - -int Test10_LoadStore() -{ - int *buf, i, result, data, err; - volatile int *pPtr; - - buf = (int*)malloc(32*sizeof(int)); -// sputs("buf = "); -// print_word((int)buf); -// sputs("\n"); - - while(1) - { - err = TEST10_ERROR; - // Basic Load/Store - pPtr = buf; - *pPtr++ = 0x00000000; - *pPtr++ = 0x55555555; - *pPtr++ = 0xAAAAAAAA; - *pPtr++ = 0xFFFFFFFF; - pPtr = buf; - if (*pPtr++ != 0x00000000) - break; - if (*pPtr++ != 0x55555555) - break; - if (*pPtr++ != 0xAAAAAAAA) - break; - if (*pPtr++ != 0xFFFFFFFF) - break; - - // Filling from left - pPtr = buf; - data = 0x00000000; - for (i=0; i < 32; i++) - { - *pPtr++ = data; - data = data >> 1 | 0x80000000; - - } - pPtr = buf; - data = 0x00000000; - for (i=0; i < 32; i++) - { - - if (*pPtr++ != data) - break; - - data = data >> 1 | 0x80000000; - } - if (i != 32) - break; - - // Filling from right - pPtr = buf; - data = 0x00000000; - for (i=0; i < 32; i++) - { - *pPtr++ = data; - data = data << 1 | 1; - - } - pPtr = buf; - data = 0x00000000; - for (i=0; i < 32; i++) - { - - if (*pPtr++ != data) - break; - - data = data << 1 | 1; - } - if (i != 32) - break; - - // Walking ones - pPtr = buf; - data = 0x00000001; - for (i=0; i < 32; i++) - { - *pPtr++ = data; - data = data << 1; - - } - pPtr = buf; - data = 0x00000001; - for (i=0; i < 32; i++) - { - - if (*pPtr++ != data) - break; - - data = data << 1; - } - if (i != 32) - break; - - // Walking zeros - pPtr = buf; - data = 0xFFFFFFFE; - for (i=0; i < 32; i++) - { - *pPtr++ = data; - data = data << 1 | 1; - - } - pPtr = buf; - data = 0xFFFFFFFE; - for (i=0; i < 32; i++) - { - - if (*pPtr++ != data) - break; - - data = data << 1 | 1; - - } - if (i != 32) - break; - - err = NO_ERROR; - break; - } - free(buf); - - if (IS_ERROR(err)) - return err; - - if (IS_ERROR(non_aligned_load())) - return TEST10_ERROR | 1; - - if (IS_ERROR(uncached_cachemiss_bug())) - return TEST10_ERROR | 2; - - return NO_ERROR; - -} - - -#define NUM_ELEMENTS 10000 -#define NUM_RUNS 3 -int Test11_AddSub() -{ - int buf[NUM_ELEMENTS], result, i, j, diff, fill, num_right_elements, num_right_runs; - - fill = 0xAAAAAAAA; - - num_right_runs = 0; - - for (i=0; i < NUM_RUNS; i++) - { - for (j=0; j < NUM_ELEMENTS; j++) - { - buf[j] = fill; - fill = ((fill ^ j) - 1) << 1; - } - num_right_elements = 2; - result = fibonacci(i, i+1, buf, NUM_ELEMENTS); - for (j=2; j < NUM_ELEMENTS; j++) - { - diff = buf[j] - buf[j-1]; - if (diff == buf[j-2]) - num_right_elements++; - } - if (num_right_elements == NUM_ELEMENTS) - num_right_runs++; - - } - - if (num_right_runs != NUM_RUNS) - return TEST11_ERROR; - - return NO_ERROR; -} - -int Test12_MulDiv() -{ - int mix, i, j; - int s1, s2, sp, st; - div_t div_res; - long cl; - - cl = (long)clock(); - srand(cl); - for (i=0; i < 100; i++) - { - for (j=1; j < 100; j++) - { - mix = (int)rand(); - mix = (mix << 8) ^ (mix << 16); - s1 = (int)rand() ^ mix; - mix = (int)rand(); - mix = (mix << 8) ^ (mix << 16); - s2 = (int)rand() ^ mix; - if (!s2) - { - fprintf(stderr, "Test12_MulDiv(): Division by zero!\n"); - fprintf(stderr, "Clock() was 0x%8.8X\n", cl); - continue; - } - - div_res = div(s1, s2); - - sp = s2*div_res.quot; - st = div_res.rem + sp; - if (st != s1) - return TEST12_ERROR; - } - } - return NO_ERROR; -} - -int Test13_COP0_Load_Store(void) -{ - int i,size; - UINT32 *pSrc32, *pDst32; - - size = 0x2000; - pSrc32 = (UINT32*)0xBFC00000; - pDst32 = (UINT32*)calloc(size,sizeof(UINT32)); - for (i=0; i < size/4; i++) - { - CP0_TR_read_ptr(&pSrc32[i]); - CP0_TR_write_ptr(&pDst32[i]); - } - for (i=size/4-1; i >= 0; i--) - if (pDst32[i] != pSrc32[i]) - break; - - free(pDst32); - i++; - if (i) - return TEST13_ERROR; - - return NO_ERROR; -} - -int Test14_DCACHE_invalidate(void) -{ - int i,size; - UINT32 *pSrc32, *pDst32; - - size = 0x2000; - pSrc32 = (UINT32*)0xBFC00000; - pDst32 = (UINT32*)calloc(size,sizeof(UINT32)); - for (i=0; i < size/4; i++) - { - pDst32[i] = pSrc32[i]; - DCACHE_invalidate_at(&pDst32[i]); - } - for (i=size/4-1; i >= 0; i--) - { - DCACHE_invalidate_at(&pDst32[i]); - if (pDst32[i] != pSrc32[i]) - break; - } - - free(pDst32); - i++; - if (i) - return TEST14_ERROR; - - pDst32 = (UINT32*)calloc(size,sizeof(UINT32)); - for (i=0; i < size/4; i++) - { - pDst32[i] = pSrc32[i]; - } - DCACHE_invalidate_all(); - for (i=size/4-1; i >= 0; i--) - if (pDst32[i] != pSrc32[i]) - break; - - free(pDst32); - i++; - if (i) - return TEST14_ERROR; - - return NO_ERROR; -} - -#define PI_SCALE 10000 -#define PI_MAXARR 2800 -#define PI_ARRINIT 2000 - -int Test15_pi_calc() -{ - int i, j, k; - int carry = 0; - int arr[PI_MAXARR+1]; - UINT32 int_part, result; - UINT16 pi_res[200] = {0}; - UINT16 pi_ref[200] = - { - 3141,5926,5358,9793,2384,6264,3383,2795, 288,4197,1693,9937,5105,8209,7494,4592,3078,1640,6286,2089,9862,8034,8253,4211, - 7067,9821,4808,6513,2823, 664,7093,8446, 955, 582,2317,2535,9408,1284,8111,7450,2841, 270,1938,5211, 555,9644,6229,4895, - 4930,3819,6442,8810,9756,6593,3446,1284,7564,8233,7867,8316,5271,2019, 914,5648,5669,2346, 348,6104,5432,6648,2133,9360, - 7260,2491,4127,3724,5870, 660,6315,5881,7488,1520,9209,6282,9254, 917,1536,4367,8925,9036, 11,3305,3054,8820,4665,2138, - 4146,9519,4151,1609,4330,5727, 365,7595,9195,3092,1861,1738,1932,6117,9310,5118,5480,7446,2379,9627,4956,7351,8857,5272, - 4891,2279,3818,3011,9491,2983,3673,3624,4065,6643, 860,2139,4946,3952,2473,7190,7021,7986, 943,7027,7053,9217,1762,9317, - 6752,3846,7481,8467,6694, 513,2000,5681,2714,5263,5608,2778,5771,3427,5778,9609,1736,3717,8721,4684,4090,1224,9534,3014, - 6549,5853,7105, 792,2796,8925,8923,5420,1995,6112,1290,2196, 864, 344,1815,9813,6297,7477,1309,9605,1870,7211,3499,9999, - 8372,9780,4995,1059,7317,3281,6096,3185 - }; - - // setbuf(stdout, NULL); - k = 0; - for (i = 0; i <= PI_MAXARR; ++i) - arr[i] = PI_ARRINIT; - - for (i = PI_MAXARR; i; i -= 14) - { - int sum = 0; - for (j = i; j > 0; --j) - { - sum = sum*j + PI_SCALE*arr[j]; - arr[j] = sum % (j*2-1); - sum /= (j*2-1); - } - result = carry + sum/PI_SCALE; - int_part = PI_SCALE * (result / PI_SCALE); - pi_res[k] = (UINT16)(result - int_part); - carry = sum % PI_SCALE; - k++; - } - - for (k=0; k < sizeof(pi_ref)/sizeof(UINT16); k++) - { - printf("%d", pi_res[k]); - } - printf("\n"); - - if(memcmp(pi_res, pi_ref, sizeof(pi_ref))) - return TEST15_ERROR; - - return NO_ERROR; -} - -#define TEST_SIZE (16*1024*1024) // Bytes -#define SMALL_TEST_SIZE (8192) // Bytes -#define FLASH_SIZE (8*1024*1024) // Bytes - -int Test16_MemTest(void) -{ - int result, i, j, cnt, size; - UINT8 *ram8 = NULL; - UINT16 *ram16 = NULL; - UINT32 *ram32 = NULL; - UINT32 volatile *pFlashIO = (UINT32*)SYS_FLASH_IO; - UINT32 volatile *pFlashMem = (UINT32*)SYS_FLASH_MEM; - UINT32 volatile *pROM = (UINT32*)0xBFC00000; - UINT32 volatile *pVGA_src0 = (UINT32*)SYS_VGA_BLIT_SRC0; - UINT32 volatile *pVGA_dst = (UINT32*)SYS_VGA_BLIT_DST; - UINT32 volatile *pVGA_dimx_src0 = (UINT32*)SYS_VGA_BLIT_SRC0_DIMX; - UINT32 volatile *pVGA_dimx_dst = (UINT32*)SYS_VGA_BLIT_DST_DIMX; - UINT32 volatile *pVGA_nx = (UINT32*)SYS_VGA_BLIT_NX; - UINT32 volatile *pVGA_ny = (UINT32*)SYS_VGA_BLIT_NY; - UINT32 volatile *pVGA_ctrl = (UINT32*)SYS_VGA_CTRL; - UINT32 volatile *pVGA_moffs_0 = (UINT32*)SYS_VGA_FB_FRONT; - - - UINT32 *pSrc32, *pDst32; - UINT32 start, end; - - // ---------------------------------------------------------- - // Memtest BEGIN -/* printf("SSRAM Memory Test\r\n"); - printf("Small data test\r\n"); - printf("Write (32-Bit access)..."); - start = clock(); - for (j=0; j < TEST_SIZE/SMALL_TEST_SIZE; j++) - for (i=0; i < SMALL_TEST_SIZE/4; i++) - pSSRAM[i] = (UINT32)i; - - end = clock(); - printf("done (%.2f MByte/s)\n", (double)TEST_SIZE/(1000*(end-start))); - - PrintBuffer8((UINT8*)pSSRAM, 16, 256); - - printf("Verify (32-Bit access)..."); - start = clock(); - for (j=0; j < TEST_SIZE/SMALL_TEST_SIZE; j++) - for (i=SMALL_TEST_SIZE/4-1; i >= 0; i--) - if (pSSRAM[i] != (UINT32)i) - break; - - end = clock(); - i++; - if (i) - printf("failed\r\n"); - else - printf("passed (%.2f MByte/s)\n", (double)TEST_SIZE/(1000*(end-start))); -*/ - // ---------------------------------------------------------- - pSrc32 = (UINT32*)calloc(TEST_SIZE/4,sizeof(UINT32)); - pDst32 = (UINT32*)calloc(TEST_SIZE/4,sizeof(UINT32)); - - // Memtest BEGIN - printf("Dump first 16 bytes of flash blocks\n"); - for (i=0; i < FLASH_SIZE; i += 0x40000) - memdump((UINT8*)(pFlashIO+i/4), 0, 16, 16); - - printf("\n"); - - printf("SDRAM Memory Test\n"); - printf("Test size %d kByte\n\n", TEST_SIZE/1024); - - ram8 = (UINT8*)pDst32; - printf("Zeroize SDRAM (memset)..."); - start = clock(); - memset(ram8, 0, TEST_SIZE); - end = clock(); - printf("done (%.2f MByte/s)\n", (double)TEST_SIZE/(1024*1024*(double)(end-start)/CLOCKS_PER_SEC)); - - printf("Zeroize SDRAM (8-Bit access)..."); - start = clock(); - for (i=0; i < TEST_SIZE; i++) - ram8[i] = (UINT8)0; - - end = clock(); - printf("done (%.2f MByte/s)\n", (double)TEST_SIZE/(1024*1024*(double)(end-start)/CLOCKS_PER_SEC)); - - ram16 = (UINT16*)pDst32; - printf("Zeroize SDRAM (16-Bit access)..."); - start = clock(); - for (i=0; i < TEST_SIZE/2; i++) - ram16[i] = (UINT16)0; - - end = clock(); - printf("done (%.2f MByte/s)\n", (double)TEST_SIZE/(1024*1024*(double)(end-start)/CLOCKS_PER_SEC)); - - ram32 = (UINT32*)pDst32; - printf("Zeroize SDRAM (32-Bit access)..."); - start = clock(); - for (i=0; i < TEST_SIZE/4; i++) - ram32[i] = (UINT32)0; - - end = clock(); - printf("done (%.2f MByte/s)\n", (double)TEST_SIZE/(1024*1024*(double)(end-start)/CLOCKS_PER_SEC)); - - ram8 = (UINT8*)pDst32; - printf("Write SDRAM (8-Bit access)..."); - start = clock(); - for (i=0; i < TEST_SIZE; i++) - ram8[i] = (UINT8)i; - - end = clock(); - printf("done (%.2f MByte/s)\n", (double)TEST_SIZE/(1024*1024*(double)(end-start)/CLOCKS_PER_SEC)); - - printf("Verify SDRAM (8-Bit access)..."); - start = clock(); - for (i=TEST_SIZE-1; i >= 0; i--) - if (ram8[i] != (UINT8)i) - break; - - end = clock(); - i++; - if (i) - { - printf("failed\r\n"); - return TEST16_ERROR; - } - else - printf("passed (%.2f MByte/s)\n", (double)TEST_SIZE/(1024*1024*(double)(end-start)/CLOCKS_PER_SEC)); - - ram16 = (UINT16*)pDst32; - printf("Write SDRAM (16-Bit access)..."); - start = clock(); - for (i=0; i < TEST_SIZE/2; i++) - ram16[i] = (UINT16)i; - - end = clock(); - printf("done (%.2f MByte/s)\n", (double)TEST_SIZE/(1024*1024*(double)(end-start)/CLOCKS_PER_SEC)); - - printf("Verify SDRAM (16-Bit access)..."); - start = clock(); - for (i=TEST_SIZE/2-1; i >= 0; i--) - if (ram16[i] != (UINT16)i) - break; - - end = clock(); - i++; - if (i) - { - printf("failed\r\n"); - return TEST16_ERROR; - } - else - printf("passed (%.2f MByte/s)\n", (double)TEST_SIZE/(1024*1024*(double)(end-start)/CLOCKS_PER_SEC)); - - - ram32 = (UINT32*)pDst32; - printf("Write SDRAM (32-Bit access)..."); - start = clock(); - for (i=0; i < TEST_SIZE/4; i++) - { - ram32[i] = (UINT32)i; - } - - end = clock(); - printf("done (%.2f MByte/s)\n", (double)TEST_SIZE/(1024*1024*(double)(end-start)/CLOCKS_PER_SEC)); - - printf("Verify SDRAM (32-Bit access)..."); - start = clock(); - for (i=TEST_SIZE/4-1; i >= 0; i--) - { - if (ram32[i] != (UINT32)i) - break; - } - - end = clock(); - i++; - if (i) - { - printf("failed\r\n"); - return TEST16_ERROR; - } - else - printf("passed (%.2f MByte/s)\n", (double)TEST_SIZE/(1024*1024*(double)(end-start)/CLOCKS_PER_SEC)); - - printf("\n"); - printf("Small data test (size = %d kByte)\n", SMALL_TEST_SIZE/1024); - printf("Write SDRAM (32-Bit access)..."); - ram32 = (UINT32*)pDst32; - start = clock(); - for (j=0; j < TEST_SIZE/SMALL_TEST_SIZE; j++) - for (i=0; i < SMALL_TEST_SIZE/4; i++) - ram32[i] = (UINT32)i; - - end = clock(); - printf("done (%.2f MByte/s)\n", (double)TEST_SIZE/(1024*1024*(double)(end-start)/CLOCKS_PER_SEC)); - - // ------------------------------------------------------------------- - // Verify - printf("Verify SDRAM (32-Bit access)..."); - start = clock(); - for (j=0; j < TEST_SIZE/SMALL_TEST_SIZE; j++) - for (i=SMALL_TEST_SIZE/4-1; i >= 0; i--) - if (ram32[i] != (UINT32)i) - break; - - end = clock(); - i++; - if (i) - { - printf("failed\r\n"); - return TEST16_ERROR; - } - else - printf("passed (%.2f MByte/s)\n", (double)TEST_SIZE/(1024*1024*(double)(end-start)/CLOCKS_PER_SEC)); - - for (i=1024; i < 4*65536; i *= 2) - { - printf("Memcpy() (%d kByte)...", i/1024); - start = clock(); - for (j=0; j < TEST_SIZE/i; j++) - memcpy(pDst32, pSrc32, i); - - end = clock(); - printf("done (%.2f MByte/s)\n", (double)TEST_SIZE/(1024*1024*(double)(end-start)/CLOCKS_PER_SEC)); - } - for (i=1024; i < 4*65536; i *= 2) - { - printf("__gfx_copy_32() (%d kByte)...", i/1024); - start = clock(); - for (j=0; j < TEST_SIZE/i; j++) - __gfx_copy_32(pDst32, pSrc32, i/32); - - end = clock(); - printf("done (%.2f MByte/s)\n", (double)TEST_SIZE/(1024*1024*(double)(end-start)/CLOCKS_PER_SEC)); - } - // ------------------------------------------------------------------- - printf("\n"); - - printf("Memcpy() Flash(IO) => SDRAM \n"); - printf("Copying %d kBytes...", FLASH_SIZE/(1024)); - start = clock(); - memcpy(pDst32, (UINT32*)pFlashIO, FLASH_SIZE); - end = clock(); - printf("done (%.2f MByte/s)\n", (double)TEST_SIZE/(1024*1024*(double)(end-start)/CLOCKS_PER_SEC)); - printf("\n"); - - printf("Memcpy() Flash(MEM) => SDRAM \n"); - printf("Copying %d kBytes...", FLASH_SIZE/(1024)); - start = clock(); - memcpy(pDst32, (UINT32*)pFlashMem, FLASH_SIZE); - end = clock(); - printf("done (%.2f MByte/s)\n", (double)TEST_SIZE/(1024*1024*(double)(end-start)/CLOCKS_PER_SEC)); - printf("\n"); - - interrupt_register(5, (void*)ISR_blitter_rdy); - interrupt_enable(5); - *pVGA_ctrl |= SYS_VGA_BIT_BLIT_FIN_INTEN; - printf("Blitter speed test (scan disabled)..."); - *pVGA_src0 = (UINT32)pSrc32; - *pVGA_dst = (UINT32)pDst32; - *pVGA_dimx_src0 = (UINT32)0; - *pVGA_dimx_dst = (UINT32)0; - *pVGA_nx = (UINT32)TEST_SIZE/4 - 1; - *pVGA_ny = (UINT32)0; - - start = clock(); - for (i=0; i < 10; i++) - { - _g_blitter_rdy = 0; - *pVGA_ctrl |= SYS_VGA_BIT_BLIT_REQ; - while (!_g_blitter_rdy); - } - end = clock(); - printf("done (%.2f MByte/s)\n", (double)(10*TEST_SIZE)/(1024*1024*(double)(end-start)/CLOCKS_PER_SEC)); - printf("\n"); - - printf("Blitter speed test (scan enabled)..."); - *pVGA_ctrl |= SYS_VGA_BIT_MSTEN; - sleep(500); - *pVGA_src0 = (UINT32)pSrc32; - *pVGA_dst = (UINT32)pDst32; - *pVGA_dimx_src0 = (UINT32)0; - *pVGA_dimx_dst = (UINT32)0; - *pVGA_nx = (UINT32)TEST_SIZE/4 - 1; - *pVGA_ny = (UINT32)0; - - start = clock(); - for (i=0; i < 10; i++) - { - _g_blitter_rdy = 0; - *pVGA_ctrl |= SYS_VGA_BIT_BLIT_REQ; - while (!_g_blitter_rdy); - } - end = clock(); - printf("done (%.2f MByte/s)\n", (double)(10*TEST_SIZE)/(1024*1024*(double)(end-start)/CLOCKS_PER_SEC)); - printf("\n"); - *pVGA_ctrl &= ~SYS_VGA_BIT_MSTEN; - *pVGA_ctrl &= ~SYS_VGA_BIT_BLIT_FIN_INTEN; - interrupt_disable(5); - - size = 0x2000; - memcpy(pDst32, (UINT32*)pROM, size); - printf("Verify boot ROM..."); - for (i=size/4-1; i >= 0; i--) - if (pDst32[i] != pROM[i]) - break; - i++; - if (i) - { - printf("failed\r\n"); - return TEST16_ERROR; - } - else - printf("passed\r\n"); - - printf("Verify FLASH(IO) <=> FLASH(MEM)..."); - if (!memcmp((UINT32*)pFlashIO, (UINT32*)pFlashMem, FLASH_SIZE)) - printf("passed\r\n"); - else - { - printf("failed\r\n"); - return TEST16_ERROR; - } - -// memdump((UINT8*)pSrc32, 0, 16, size); -// memdump((UINT8*)0x40000000, 0, 16, 1024); - - // Memtest END - // ---------------------------------------------------------- - free(pSrc32); - free(pDst32); - - sputs("\r\n"); - return 0; -} - -int main (void) -{ - int result, i, j, cnt, size; - UINT32 volatile *pUART_baud = (UINT32*)SYS_UART_BAUD; - UINT32 volatile *pUART_stat = (UINT32*)SYS_UART_STAT; - UINT32 volatile *pReg = (UINT32*)SYS_LED_PORT; - UINT32 volatile *pReg_usec = (UINT32*)SYS_TIMER_USEC; - UINT32 volatile *pReg_sec = (UINT32*)SYS_TIMER_SEC; - UINT32 volatile *pSSRAM = (UINT32*)SYS_SSRAM_IO; - UINT32 volatile *pTim_ctrl = (UINT32*)SYS_ITIM_CTRL; - UINT32 volatile *pTim_stat = (UINT32*)SYS_ITIM_STAT; - UINT32 volatile *pTim0_cnt = (UINT32*)SYS_ITIM0_CNT; - UINT32 volatile *pTim0_cmp = (UINT32*)SYS_ITIM0_CMP; - UINT32 volatile *pTim1_cnt = (UINT32*)SYS_ITIM1_CNT; - UINT32 volatile *pTim1_cmp = (UINT32*)SYS_ITIM1_CMP; - UINT32 volatile *pVGA_cgcol = (UINT32*)SYS_VGA_CGCOL; - UINT32 volatile *pFlashPicture = (UINT32*)(SYS_FLASH_MEM + 0x00600000); - - UINT32 volatile *pVGA_src0 = (UINT32*)SYS_VGA_BLIT_SRC0; - UINT32 volatile *pVGA_dst = (UINT32*)SYS_VGA_BLIT_DST; - UINT32 volatile *pVGA_dimx_src0 = (UINT32*)SYS_VGA_BLIT_SRC0_DIMX; - UINT32 volatile *pVGA_dimx_dst = (UINT32*)SYS_VGA_BLIT_DST_DIMX; - UINT32 volatile *pVGA_nx = (UINT32*)SYS_VGA_BLIT_NX; - UINT32 volatile *pVGA_ny = (UINT32*)SYS_VGA_BLIT_NY; - UINT32 volatile *pVGA_ctrl = (UINT32*)SYS_VGA_CTRL; - UINT32 volatile *pVGA_moffs_0 = (UINT32*)SYS_VGA_FB_FRONT; - - UINT32 screen_res_x, screen_res_y, screen_fps; - UINT64 *pBuf64_0, *pBuf64_1; - time_t curr_date; - struct tm *pDate, date; - UINT32 start, end; - char sel[80]; - struct timeval time_sec; - - - g_cnt = 1; - Screen_clr(); - - *pVGA_cgcol = 0x00FFFFFF; - - *pTim0_cnt = 0; - *pTim1_cnt = 0; - *pTim0_cmp = 0x4000; - *pTim1_cmp = 100000000; - *pTim_stat = (1 << 2) | (1 << 0); - *pTim_ctrl = (3 << 2); - -// *pUART_baud = 1; - - setbuf(stdout, NULL); - PrintCPUinfo(); - - interrupt_register(3, handler3); - fprintf(stderr, "UART interrupt registered.\n"); - - interrupt_register(7, handler7); - fprintf(stderr, "Timer interrupt registered.\n"); - - calibrate_delay(); - - printf("\n"); - - printf("Aktuelles Datum\n"); - curr_date = time(NULL); - pDate = gmtime(&curr_date); - puts(asctime(pDate)); - - if (curr_date < 2) - { - printf("Datum und Uhrzeit setzen? [j/N]: "); - scanf("%s", sel); - if (toupper(sel[0]) == 'J') - { - do - { - printf("Datum\n"); - printf("Jahr : "); - scanf("%d", &date.tm_year); - printf("Monat : "); - scanf("%d", &date.tm_mon); - printf("Tag : "); - scanf("%d", &date.tm_mday); - - printf("Uhrzeit\n"); - printf("Stunde : "); - scanf("%d", &date.tm_hour); - printf("Minute : "); - scanf("%d", &date.tm_min); - printf("Sekunde : "); - scanf("%d", &date.tm_sec); - - date.tm_year -= 1900; - date.tm_mon -= 1; - time_sec.tv_sec = mktime(&date); - time_sec.tv_usec = 0; - settimeofday(&time_sec, NULL); - - printf("Datum\n"); - curr_date = time(NULL); - pDate = gmtime(&curr_date); - puts(asctime(pDate)); - printf("\nOK? [J/n]: "); - scanf("%s", sel); - printf("sel=%d\n", (int)sel[0]); - - - } while(toupper(sel[0]) == 'N'); - } - } - srand(clock()); - *pReg = uncached_cachemiss_bug(); - Test16_MemTest(); - - printf("pf = %08X\n", (UINT32)pf()); - *pf() = 0x1234; - printf("*pf = %08X\n", (UINT32)*pf()); - - box_create(&box, 32, 32); - GFX_init(&gfx); - - start = clock(); - for (i=0; i < 100000; i++) - { - GFX_box_draw_direct(&gfx, &box, (UINT32)rand()%800, (UINT32)rand()%600, (UINT32)rand()); - } - - end = clock(); - printf("Fillrate %f rect/s\n", (float)i/((float)(end-start)/CLOCKS_PER_SEC)); - sleep(2000); - - GFX_frame(&gfx, GFX_FRAME_SYNC); - GFX_set_background(&gfx, pFlashPicture, 800, 600, 1, 1); - posx = posy = 0; - GFX_show(&gfx); - -// while(1) - { - // Blitter test - fprintf(stderr, "Blit start\n"); - *pVGA_src0 = (UINT32)*pFlashPicture; - *pVGA_dst = (UINT32)*pVGA_moffs_0; - *pVGA_dimx_src0 = (UINT32)4*800; - *pVGA_dimx_dst = (UINT32)4*800; - *pVGA_nx = (UINT32)800 - 1; - *pVGA_ny = (UINT32)600 - 1; - *pVGA_ctrl |= SYS_VGA_BIT_BLIT_REQ; - while (*pVGA_ctrl & SYS_VGA_BIT_BLIT_BSY); - - fprintf(stderr, "Blit end\n"); - sleep(250); - - // Blitter test - fprintf(stderr, "Blit start\n"); - *pVGA_src0 = (UINT32)gfx.pBG; - *pVGA_dst = (UINT32)*pVGA_moffs_0; - *pVGA_dimx_src0 = (UINT32)4*800; - *pVGA_dimx_dst = (UINT32)4*800; - *pVGA_nx = (UINT32)800 - 1; - *pVGA_ny = (UINT32)600 - 1; - *pVGA_ctrl |= SYS_VGA_BIT_BLIT_REQ; - while (*pVGA_ctrl & SYS_VGA_BIT_BLIT_BSY); - - fprintf(stderr, "Blit end\n"); - sleep(1000); - } - - - interrupt_enable(7); - interrupt_enable(3); - *pTim_ctrl |= 3; - *pUART_stat |= (1 << 6); - - cnt = 0; - while (1) - { - for (i=0; i < 100000; i++) - { - interrupt_disable(7); - } - for (i=0; i < 100000; i++) - { - interrupt_enable(7); - } - - *pReg = cnt & 0x3FFFFFFF; - - printf("-------------------------------------------\n"); - printf("-- LoadStore ------------------------------\n"); - printf("-------------------------------------------\n"); - result = Test10_LoadStore(); - if (IS_ERROR(result)) - break; - printf("passed\n\n"); - - printf("-------------------------------------------\n"); - printf("-- AddSub ---------------------------------\n"); - printf("-------------------------------------------\n"); - result = Test11_AddSub(); - if (IS_ERROR(result)) - break; - printf("passed\n\n"); - - printf("-------------------------------------------\n"); - printf("-- MulDiv ---------------------------------\n"); - printf("-------------------------------------------\n"); - result = Test12_MulDiv(); - if (IS_ERROR(result)) - break; - printf("passed\n\n"); - - printf("-------------------------------------------\n"); - printf("-- Cop0 LWZ0 and SWC0 ---------------------\n"); - printf("-------------------------------------------\n"); - result = Test13_COP0_Load_Store(); - if (IS_ERROR(result)) - break; - printf("passed\n\n"); - - printf("-------------------------------------------\n"); - printf("-- D-Cache invalidate ---------------------\n"); - printf("-------------------------------------------\n"); - result = Test14_DCACHE_invalidate(); - if (IS_ERROR(result)) - break; - printf("passed\n\n"); - - printf("-------------------------------------------\n"); - printf("-- PI calc --------------------------------\n"); - printf("-------------------------------------------\n"); - result = Test15_pi_calc(); - if (IS_ERROR(result)) - break; - printf("passed\n\n"); - - printf("-------------------------------------------\n"); - printf("-- Paranoia -------------------------------\n"); - printf("-------------------------------------------\n"); - paranoia(1, NULL); - printf("passed\n\n"); - -// printf("-------------------------------------------\n"); -// printf("-- Mem Test -------------------------------\n"); -// printf("-------------------------------------------\n"); -// result = Test16_MemTest(); -// if (IS_ERROR(result)) -// break; -// printf("passed\n\n"); - - printf("Iteration %d: Passed\n", cnt); - curr_date = time(NULL); - pDate = gmtime(&curr_date); - puts(asctime(pDate)); - cnt++; - *pTim0_cmp = 0x4000 + (UINT32)(rand() & 0x00FFFFFF); - *pTim_ctrl |= 1; - -// printf("V=%.17e\n", pow((double)cnt-1, (double)cnt)); - } - *pReg = 0x40000000 | cnt; - fprintf(stderr, "Failed with error %8.8X\n", result); - - return 1; - -} - diff --git a/lib/CPUs/MIPS/bsp/examples/testlibusb.c b/lib/CPUs/MIPS/bsp/examples/testlibusb.c deleted file mode 100644 index 5b48601..0000000 --- a/lib/CPUs/MIPS/bsp/examples/testlibusb.c +++ /dev/null @@ -1,210 +0,0 @@ -/* testlibusb.c */ - -#include -#include -#include -#include -#include -#include -#include "tiffio.h" - - -#define BUFLEN (256*1024) -#define FLASHSIZE (2*1024*1024) -int main(int argc, char *argv[]) -{ - char *pBuf; - int ret, i, xfer_cnt, filesize, size; - char string[256]; - double start, end; - struct timeval t; - FILE *pFile; - TIFF *pTif; - ttag_t config, photometric; - uint16 nSamples, nBits; - uint32 width, height; - uint32* raster; - - typedef struct _scmd_t - { - unsigned sync; - unsigned code; - unsigned len; - } cmd_t; - - cmd_t cmd_read = {0xC24755AA, 2, BUFLEN}; - cmd_t cmd_write = {0xC24755AA, 1, BUFLEN}; - cmd_t cmd_flash_read = {0xC24755AA, 3, FLASHSIZE}; - cmd_t cmd_flash_write = {0xC24755AA, 4, FLASHSIZE}; - - libusb_context *pCtx; - libusb_device_handle *handle; - size_t cnt; - - ret = libusb_init(&pCtx); - if (ret != LIBUSB_SUCCESS) - { - printf("Error %08X\n", ret); - return 1; - } - - libusb_set_debug(pCtx, 3); - - handle = libusb_open_device_with_vid_pid (pCtx, 0x04B4, 0x7200); - if (!handle) - { - printf("Error on opening device\n"); - return 1; - } - - pBuf = (char*)malloc(BUFLEN); - memset(pBuf, 0, BUFLEN); - - // ------------------------------------------------------ - printf("Send command\n"); - // ------------------------------------------------------ - ret = libusb_bulk_transfer (handle, 0x01, (char*)&cmd_write, sizeof(cmd_t), &xfer_cnt, 5000); - if (ret != LIBUSB_SUCCESS) - { - printf("Error %08X\n", ret); - return 1; - } - gettimeofday(&t, NULL); - start = t.tv_sec + 1E-6*t.tv_usec; - ret = libusb_bulk_transfer(handle, 0x01, (char*)pBuf, cmd_write.len, &xfer_cnt, 5000); - size = xfer_cnt; - gettimeofday(&t, NULL); - end = t.tv_sec + 1E-6*t.tv_usec; - if (ret != LIBUSB_SUCCESS) - { - printf("Error %08X\n", ret); - return 1; - } - printf("Sent %d bytes\n", size); - printf("Data rate: %.2f kbyte/s\n", (double)size/(1024*(end-start))); - - // ------------------------------------------------------ - printf("Read command\n"); - // ------------------------------------------------------ - ret = libusb_bulk_transfer(handle, 0x01, (char*)&cmd_read, sizeof(cmd_t), &xfer_cnt, 5000); - if (ret != LIBUSB_SUCCESS) - { - printf("Error %08X\n", ret); - return 1; - } - gettimeofday(&t, NULL); - start = t.tv_sec + 1E-6*t.tv_usec; - ret = libusb_bulk_transfer(handle, 0x82, (char*)pBuf, cmd_read.len, &xfer_cnt, 5000); - size = xfer_cnt; - gettimeofday(&t, NULL); - end = t.tv_sec + 1E-6*t.tv_usec; - if (ret != LIBUSB_SUCCESS) - { - printf("Error %08X\n", ret); - return 1; - } - printf("Received %d bytes\n", size); - printf("Data rate: %.2f kbyte/s\n", (double)size/(1024*(end-start))); - free(pBuf); - - // ------------------------------------------------------ - printf("Read Flash\n"); - // ------------------------------------------------------ - pBuf = (char*)malloc(FLASHSIZE); - memset(pBuf, 0, FLASHSIZE); - ret = libusb_bulk_transfer(handle, 0x01, (char*)&cmd_flash_read, sizeof(cmd_t), &xfer_cnt, 5000); - if (ret != LIBUSB_SUCCESS) - { - printf("Error %08X\n", ret); - return 1; - } - - gettimeofday(&t, NULL); - start = t.tv_sec + 1E-6*t.tv_usec; - ret = libusb_bulk_transfer(handle, 0x82, (char*)pBuf, cmd_flash_read.len, &xfer_cnt, 500000); - size = xfer_cnt; - gettimeofday(&t, NULL); - end = t.tv_sec + 1E-6*t.tv_usec; - if (ret != LIBUSB_SUCCESS) - { - printf("Error %08X\n", ret); - return 1; - } - printf("Received %d bytes\n", size); - printf("Data rate: %.2f kbyte/s\n", (double)size/(1024*(end-start))); - - pFile = fopen("./flash.bin", "wb"); - fwrite(pBuf, 1, size, pFile); - fclose(pFile); - free(pBuf); - - if (argc > 1) - { - // ------------------------------------------------------ - printf("Write Flash (File = %s)\n", argv[1]); - // ------------------------------------------------------ - pTif = TIFFOpen(argv[1],"r"); - if (!pTif) - { - printf("Unable to open TIFF-file!\n"); - return 1; - } - ret = TIFFGetField(pTif, TIFFTAG_IMAGEWIDTH, &width); - ret = TIFFGetField(pTif, TIFFTAG_IMAGELENGTH, &height); - - printf("TIFFTAG_IMAGEWIDTH = %d\n", width); - printf("TIFFTAG_IMAGELENGTH = %d\n", height); - - filesize = width * height * sizeof (uint32); - - raster = (uint32*) _TIFFmalloc(filesize); - if (raster != NULL) - { - ret = TIFFReadRGBAImageOriented(pTif, width, height, raster, ORIENTATION_TOPLEFT, 0); - if (!ret) - { - printf("Unable to reading TIFF-file!\n"); - return 1; - } - } - TIFFClose(pTif); - - printf ("File size = %d\n", filesize); - if (filesize > FLASHSIZE) - { - printf("Cannot write flash: image to large!\n"); - return 1; - } - - cmd_flash_write.len = filesize; - ret = libusb_bulk_transfer(handle, 0x01, (char*)&cmd_flash_write, sizeof(cmd_t), &xfer_cnt, 5000); - if (ret != LIBUSB_SUCCESS) - { - printf("Error %08X\n", ret); - return 1; - } - - gettimeofday(&t, NULL); - start = t.tv_sec + 1E-6*t.tv_usec; - size = 0; - ret = libusb_bulk_transfer(handle, 0x01, (char*)raster, filesize, &xfer_cnt, 500000); - if (ret != LIBUSB_SUCCESS) - { - printf("Error %08X\n", ret); - return 1; - } - size += xfer_cnt; - gettimeofday(&t, NULL); - end = t.tv_sec + 1E-6*t.tv_usec; - printf("Sent %d bytes\n", size); - printf("Data rate: %.2f kbyte/s\n", (double)size/(1024*(end-start))); - - _TIFFfree(raster); - - } - - libusb_close(handle); - libusb_exit(pCtx); - return 0; - -} diff --git a/lib/CPUs/MIPS/bsp/examples/ucb.c b/lib/CPUs/MIPS/bsp/examples/ucb.c deleted file mode 100644 index d3b9a82..0000000 --- a/lib/CPUs/MIPS/bsp/examples/ucb.c +++ /dev/null @@ -1,44 +0,0 @@ -#include "libsys.h" - -int uncached_cachemiss_bug(UINT32* pMem) -{ - UINT32 result; - - pMem[0] = 0x12345678; - pMem[1] = 0xFFFFFFFF; - - DCACHE_invalidate_all(); - - __asm__ - ( - "lui $s0, 0xA000\n" - "lw $a0, 32($s0)\n" - "or $s1, $a0, $0\n" - "or $a2, $0, $0\n" - "addiu $a2, 1\n" - "sw $a2, 32($s0)\n" -// "lw $a1, 0(%[pMem])\n" - "lw $a0, 32($s0)\n" - "lw $a2, 4(%[pMem])\n" - "lw $a1, 0(%[pMem])\n" - "nop\n" - "sw $s1, 8($s0)\n" - "or %[val], $a0, $0\n" - : [val] "=r" (result) - : [pMem] "r" (pMem) - : "a0", "a1", "a2", "s0", "s1" - ); - return result; -} - -int main() -{ - UINT32 volatile *pLed = (UINT32*)SYS_LED_PORT; - int buf[256], res; - - res = uncached_cachemiss_bug(buf); - *pLed = res; - - return res; - -} diff --git a/lib/CPUs/MIPS/bsp/examples/whet.c b/lib/CPUs/MIPS/bsp/examples/whet.c deleted file mode 100644 index d939910..0000000 --- a/lib/CPUs/MIPS/bsp/examples/whet.c +++ /dev/null @@ -1,265 +0,0 @@ -/* - * @(#)whet.c 1.1 - */ - -/* - * Whetstone benchmark in C. This program is a translation of the - * original Algol version in "A Synthetic Benchmark" by H.J. Curnow - * and B.A. Wichman in Computer Journal, Vol 19 #1, February 1976. - * - * Used to test compiler optimization and floating point performance. - */ - -/* - * Compile with -DMEASURE_TIME for time measurement. - * - * Compile with -DPOUT to print intermediate results. - * Running this benchmark without printing the intermediate results is - * contrary to the authors' intentions! But using serial I/O can draw back - * the performance extremely when low baud rate communication is used. - */ -#define MEASURE_TIME 1 -//#define POUT 1 - -#define ITERATIONS 10 /* 10 Million Whetstone instructions */ - -#include -#include - -#ifdef MEASURE_TIME -#include -unsigned long Begin_Time,End_Time,Total_Time; -double whetstones; -#endif - -#define Pout(n, j, k, x1, x2, x3, x4) pout(n, j, k, x1, x2, x3, x4); - -double xx1, xx2, xx3, xx4, x, y, z, t, t1, t2; -double e1[4]; -unsigned int i, j, k, l, n1, n2, n3, n4, n6, n7, n8, n9, n10, n11; - -main() -{ - printf("\nWhetstone Benchmark\n\n"); - - printf( "%d iterations\n", ITERATIONS ); - -#ifdef MEASURE_TIME - Begin_Time = clock(); -#endif - - /* initialize constants */ - - t = 0.499975; - t1 = 0.50025; - t2 = 2.0; - - /* set values of module weights */ - - n1 = 0 * ITERATIONS; - n2 = 12 * ITERATIONS; - n3 = 14 * ITERATIONS; - n4 = 345 * ITERATIONS; - n6 = 210 * ITERATIONS; - n7 = 32 * ITERATIONS; - n8 = 899 * ITERATIONS; - n9 = 616 * ITERATIONS; - n10 = 0 * ITERATIONS; - n11 = 93 * ITERATIONS; - -/* MODULE 1: simple identifiers */ - - xx1 = 1.0; - xx2 = xx3 = xx4 = -1.0; - - for(i = 1; i <= n1; i += 1) { - xx1 = ( xx1 + xx2 + xx3 - xx4 ) * t; - xx2 = ( xx1 + xx2 - xx3 + xx4 ) * t; - xx3 = ( xx1 - xx2 + xx3 + xx4 ) * t; - xx4 = (-xx1 + xx2 + xx3 + xx4 ) * t; - } -#ifdef POUT - Pout(n1, n1, n1, xx1, xx2, xx3, xx4); -#endif - - -/* MODULE 2: array elements */ - - e1[0] = 1.0; - e1[1] = e1[2] = e1[3] = -1.0; - - for (i = 1; i <= n2; i +=1) { - e1[0] = ( e1[0] + e1[1] + e1[2] - e1[3] ) * t; - e1[1] = ( e1[0] + e1[1] - e1[2] + e1[3] ) * t; - e1[2] = ( e1[0] - e1[1] + e1[2] + e1[3] ) * t; - e1[3] = (-e1[0] + e1[1] + e1[2] + e1[3] ) * t; - } -#ifdef POUT - Pout(n2, n3, n2, e1[0], e1[1], e1[2], e1[3]); -#endif - -/* MODULE 3: array as parameter */ - - for (i = 1; i <= n3; i += 1) - pa(e1); -#ifdef POUT - Pout(n3, n2, n2, e1[0], e1[1], e1[2], e1[3]); -#endif - -/* MODULE 4: conditional jumps */ - - j = 1; - for (i = 1; i <= n4; i += 1) { - if (j == 1) - j = 2; - else - j = 3; - - if (j > 2) - j = 0; - else - j = 1; - - if (j < 1 ) - j = 1; - else - j = 0; - } -#ifdef POUT - Pout(n4, j, j, xx1, xx2, xx3, xx4); -#endif - -/* MODULE 5: omitted */ - -/* MODULE 6: integer arithmetic */ - - j = 1; - k = 2; - l = 3; - - for (i = 1; i <= n6; i += 1) { - j = j * (k - j) * (l -k); - k = l * k - (l - j) * k; - l = (l - k) * (k + j); - - e1[l - 2] = j + k + l; /* C arrays are zero based */ - e1[k - 2] = j * k * l; - } -#ifdef POUT - Pout(n6, j, k, e1[0], e1[1], e1[2], e1[3]); -#endif - -/* MODULE 7: trig. functions */ - - x = y = 0.5; - - for(i = 1; i <= n7; i +=1) { - x = t * atan(t2*sin(x)*cos(x)/(cos(x+y)+cos(x-y)-1.0)); - y = t * atan(t2*sin(y)*cos(y)/(cos(x+y)+cos(x-y)-1.0)); - } -#ifdef POUT - Pout(n7, j, k, x, x, y, y); -#endif - -/* MODULE 8: procedure calls */ - - x = y = z = 1.0; - - for (i = 1; i <= n8; i +=1) - p3(x, y, &z); -#ifdef POUT - Pout(n8, j, k, x, y, z, z); -#endif - -/* MODULE9: array references */ - - j = 1; - k = 2; - l = 3; - - e1[0] = 1.0; - e1[1] = 2.0; - e1[2] = 3.0; - - for(i = 1; i <= n9; i += 1) - p0(); -#ifdef POUT - Pout(n9, j, k, e1[0], e1[1], e1[2], e1[3]); -#endif - -/* MODULE10: integer arithmetic */ - - j = 2; - k = 3; - - for(i = 1; i <= n10; i +=1) { - j = j + k; - k = j + k; - j = k - j; - k = k - j - j; - } -#ifdef POUT - Pout(n10, j, k, xx1, xx2, xx3, xx4); -#endif - -/* MODULE11: standard functions */ - - x = 0.75; - for(i = 1; i <= n11; i +=1) - x = sqrt( exp( log(x) / t1)); - -#ifdef POUT - Pout(n11, j, k, x, x, x, x); -#endif - -#ifdef MEASURE_TIME - End_Time = clock(); - - Total_Time = End_Time - Begin_Time; /* in 1/ seconds */ - - whetstones = (1e5 * ITERATIONS * CLOCKS_PER_SEC) / Total_Time; - printf("\nWhetstone runs in %ld clock ticks (%d). %ld Kwhets/second\n", - Total_Time, CLOCKS_PER_SEC, (long) whetstones / 1000 ); -#endif -} - -pa(e) -double e[4]; -{ - register int j; - - j = 0; - lab: - e[0] = ( e[0] + e[1] + e[2] - e[3] ) * t; - e[1] = ( e[0] + e[1] - e[2] + e[3] ) * t; - e[2] = ( e[0] - e[1] + e[2] + e[3] ) * t; - e[3] = ( -e[0] + e[1] + e[2] + e[3] ) / t2; - j += 1; - if (j < 6) - goto lab; -} - -p3(x, y, z) -double x, y, *z; -{ - x = t * (x + y); - y = t * (x + y); - *z = (x + y) /t2; -} - -p0() -{ - e1[j] = e1[k]; - e1[k] = e1[l]; - e1[l] = e1[j]; -} - -#ifdef POUT -pout(n, j, k, x1, x2, x3, x4) -unsigned int n, j, k; -double x1, x2, x3, x4; -{ - printf("%5u %5u %5u %11.3e %11.3e %11.3e %11.3e\n", - n, j, k, x1, x2, x3, x4); -} -#endif diff --git a/lib/CPUs/MIPS/bsp/examples/xcpt.c b/lib/CPUs/MIPS/bsp/examples/xcpt.c deleted file mode 100644 index a6eca43..0000000 --- a/lib/CPUs/MIPS/bsp/examples/xcpt.c +++ /dev/null @@ -1,139 +0,0 @@ -#include -#include -#include -#include -#include -#include "libsys.h" -#include "xcpt.h" -#include "irq.h" - -static fp_xcpt_t g_xcpt_handler[MAX_NUM_XCPT] = {NULL}; - -char *_xcpt_code_str[MAX_NUM_XCPT] = -{ - "Int", "Mod", "TLBL", "TLBS", "AdEL", "AdES", "IBE", "DBE", - "Sys", "Bp", "RI", "CpU", "Ov", "Tr", "NCD/VCEI", "MC/FPE", - "Res(16)", "Res(17)", "Res(18)", "Res(19)", "Res(20)", "Res(21)", "Res(22)", "WATCH", - "Res(24)", "Res(25)", "Res(26)", "Res(27)", "Res(28)", "Res(29)", "Res(30)", "VCED" - }; - -void xcpt_register(int xcpt_num, fp_xcpt_t fp) -{ - if ((xcpt_num >= Mod) && (xcpt_num <= VCED)) - g_xcpt_handler[xcpt_num] = fp; - -} - -int _xcpt_dispatch(struct xcptcontext * xcp) -{ - int xcpt_code, result, i; - - xcpt_code = ((0xFF & xcp->cr) >> 2); - - result = XCPT_ERR_NOTHANDLED; - switch(xcpt_code) - { - case Int: - result = _irq_dispatch(xcp); - break; - - default: - if (g_xcpt_handler[xcpt_code]) - { - result = (g_xcpt_handler[xcpt_code])(xcp); - } - break; - } - return result; -} - -int _xcpt_deliver(struct xcptcontext * _xcp) -{ - - int exc_code; - volatile int *pInstr; - - /* This function gets called by the low-level exception handler. */ - if (_xcpt_dispatch(_xcp) == XCPT_ERR_NOTHANDLED) - { - sputs("\n"); - PRINT_REG(" Status : ", _xcp->sr); - PRINT_REG(" Cause : ", _xcp->cr); - PRINT_REG(" EPC : ", _xcp->epc); - PRINT_REG("BadAddr : ", _xcp->baddr); - sputs("\n"); - PRINT_REG(" MDLO : ", _xcp->mdlo); - PRINT_REG(" MDHI : ", _xcp->mdhi); - - sputs("\n"); - - sputs("Registers:\n"); - PRINT_REG(" 0 (ze) : ", _xcp->regs[0]); - PRINT_REG(" 1 (at) : ", _xcp->regs[1]); - PRINT_REG(" 2 (v0) : ", _xcp->regs[2]); - PRINT_REG(" 3 (v1) : ", _xcp->regs[3]); - sputs("\n"); - PRINT_REG(" 4 (a0) : ", _xcp->regs[4]); - PRINT_REG(" 5 (a1) : ", _xcp->regs[5]); - PRINT_REG(" 6 (a2) : ", _xcp->regs[6]); - PRINT_REG(" 7 (a3) : ", _xcp->regs[7]); - sputs("\n"); - PRINT_REG(" 8 (t0) : ", _xcp->regs[8]); - PRINT_REG(" 9 (t1) : ", _xcp->regs[9]); - PRINT_REG("10 (t2) : ", _xcp->regs[10]); - PRINT_REG("11 (t3) : ", _xcp->regs[11]); - sputs("\n"); - PRINT_REG("12 (t4) : ", _xcp->regs[12]); - PRINT_REG("13 (t5) : ", _xcp->regs[13]); - PRINT_REG("14 (t6) : ", _xcp->regs[14]); - PRINT_REG("15 (t7) : ", _xcp->regs[15]); - sputs("\n"); - PRINT_REG("16 (s0) : ", _xcp->regs[16]); - PRINT_REG("17 (s1) : ", _xcp->regs[17]); - PRINT_REG("18 (s2) : ", _xcp->regs[18]); - PRINT_REG("19 (s3) : ", _xcp->regs[19]); - sputs("\n"); - PRINT_REG("20 (s4) : ", _xcp->regs[20]); - PRINT_REG("21 (s5) : ", _xcp->regs[21]); - PRINT_REG("22 (s6) : ", _xcp->regs[22]); - PRINT_REG("23 (s7) : ", _xcp->regs[23]); - sputs("\n"); - PRINT_REG("24 (t8) : ", _xcp->regs[24]); - PRINT_REG("25 (t9) : ", _xcp->regs[25]); - PRINT_REG("26 (k0) : ", _xcp->regs[26]); - PRINT_REG("27 (k1) : ", _xcp->regs[27]); - sputs("\n"); - PRINT_REG("28 (gp) : ", _xcp->regs[28]); - PRINT_REG("29 (sp) : ", _xcp->regs[29]); - PRINT_REG("30 (fp) : ", _xcp->regs[30]); - PRINT_REG("31 (ra) : ", _xcp->regs[31]); - sputs("\n"); - sputs("\n"); - - exc_code = (_xcp->cr >> 2) & 0x1F; - - sputs("Unhandled exception <"); - sputs(_xcpt_code_str[exc_code]); - sputs("> at PC : "); - - if (_xcp->cr & 0x80000000) - { - pInstr = (int*)(_xcp->epc + 4); - } - else - { - pInstr = (int*)(_xcp->epc); - } - print_word((int)pInstr); - sputs("\n"); - - sputs("Instruction at exception address : "); - print_word(*pInstr); - sputs("\n"); - - sputs("Terminate.\n"); - _exit(exc_code); - } - - return 0; -} diff --git a/lib/CPUs/MIPS/bsp/examples/xcpt.h b/lib/CPUs/MIPS/bsp/examples/xcpt.h deleted file mode 100644 index 7958912..0000000 --- a/lib/CPUs/MIPS/bsp/examples/xcpt.h +++ /dev/null @@ -1,55 +0,0 @@ -#ifndef XCPT_H -#define XCPT_H - -#define MAX_NUM_XCPT 32 -#define XCPT_ERR_NOTHANDLED 0x80000000 - -typedef enum -{ - Int = 0, Mod = 1, TLBL = 2, TLBS = 3, AdEL = 4, AdES = 5, - IBE = 6, DBE = 7, Syscall = 8, Bp = 9, RI = 10, CpU = 11, - Ov = 12, TRAP = 13, VCEI = 14, FPE = 15, C2E = 16, Watch = 23, VCED = 31 - -} EXCEPTION_CODE; - -typedef unsigned int reg_t; - -typedef struct xcptcontext -{ - /* This is the exception context frame that is passed to the exception - handlers. It gets filled in by the low-level exception handler in - "machine.S". An assembler version of this structure can be found at the - bottom of "machine.H".*/ - reg_t sr; /* Status Register */ - reg_t cr; /* Cause Register */ - reg_t epc; /* PC at time of exception. */ - reg_t baddr; - reg_t regs[32]; /* Copy of all general purpose registers */ - reg_t mdlo; /* HI/LO registers (used for memory management) */ - reg_t mdhi; - reg_t count; /* Timer registers */ - reg_t compare; - struct xcptcontext * prev; /* To link exceptions. (unused for now) */ - unsigned xclass; /* Priority class of this exception. (unused for now). */ - -} EXCEPTION_CONTEXT; - -typedef int (*fp_xcpt_t)(struct xcptcontext * xcp); - -#define PRINT_REG(tag_str, reg) \ - sputs(tag_str); \ - print_word(reg); \ - sputs(" "); - - -#define PRINT_REG_CHG(tag_str, reg, chg_tag) \ - sputs(tag_str); \ - print_word(reg); \ - sputs(chg_tag); \ - sputs(" "); - - -// Public functions -void xcpt_register(int xcpt_num, fp_xcpt_t fp); - -#endif // XCPT_H diff --git a/lib/CPUs/MIPS/bsp/examples/xcpt_asm.h b/lib/CPUs/MIPS/bsp/examples/xcpt_asm.h deleted file mode 100644 index 5735422..0000000 --- a/lib/CPUs/MIPS/bsp/examples/xcpt_asm.h +++ /dev/null @@ -1,67 +0,0 @@ -#ifndef XCPT_ASM_H -#define XCPT_ASM_H - -/* LEAF - declare leaf routine */ -#define LEAF(symbol) \ - .globl symbol; \ - .align 2; \ - .type symbol, @function; \ - .ent symbol, 0; \ -symbol: .frame sp, 0, ra - -/* END - mark end of function */ -#define END(function) \ - .end function; \ - .size function, .-function - -/* Exception stack size */ -#define XCP_SIZE 32768 - -/* save location for registers */ -#define XCP_SR 0 -#define XCP_CR 4 -#define XCP_EPC 8 -#define XCP_BADDR 12 -#define XCP_ZERO 16 -#define XCP_AT 20 -#define XCP_V0 24 -#define XCP_V1 28 -#define XCP_A0 32 -#define XCP_A1 36 -#define XCP_A2 40 -#define XCP_A3 44 -#define XCP_T0 48 -#define XCP_T1 52 -#define XCP_T2 56 -#define XCP_T3 60 -#define XCP_T4 64 -#define XCP_T5 68 -#define XCP_T6 72 -#define XCP_T7 76 -#define XCP_S0 80 -#define XCP_S1 84 -#define XCP_S2 88 -#define XCP_S3 92 -#define XCP_S4 96 -#define XCP_S5 100 -#define XCP_S6 104 -#define XCP_S7 108 -#define XCP_T8 112 -#define XCP_T9 116 -#define XCP_JP 116 -#define XCP_K0 120 -#define XCP_K1 124 -#define XCP_GP 128 -#define XCP_SP 132 -#define XCP_S8 136 -#define XCP_FP 136 -#define XCP_RA 140 -#define XCP_MDLO 144 -#define XCP_MDHI 148 -#define XCP_COUNT 152 -#define XCP_COMPARE 156 -#define XCP_PREV 160 -#define XCP_CLASS 164 - - -#endif /* XCPT_ASM_H */ diff --git a/lib/CPUs/MIPS/dist/gpl-3.0.txt b/lib/CPUs/MIPS/dist/gpl-3.0.txt deleted file mode 100644 index 94a9ed0..0000000 --- a/lib/CPUs/MIPS/dist/gpl-3.0.txt +++ /dev/null @@ -1,674 +0,0 @@ - GNU GENERAL PUBLIC LICENSE - Version 3, 29 June 2007 - - Copyright (C) 2007 Free Software Foundation, Inc. - Everyone is permitted to copy and distribute verbatim copies - of this license document, but changing it is not allowed. - - Preamble - - The GNU General Public License is a free, copyleft license for -software and other kinds of works. - - The licenses for most software and other practical works are designed -to take away your freedom to share and change the works. By contrast, -the GNU General Public License is intended to guarantee your freedom to -share and change all versions of a program--to make sure it remains free -software for all its users. We, the Free Software Foundation, use the -GNU General Public License for most of our software; it applies also to -any other work released this way by its authors. You can apply it to -your programs, too. - - When we speak of free software, we are referring to freedom, not -price. Our General Public Licenses are designed to make sure that you -have the freedom to distribute copies of free software (and charge for -them if you wish), that you receive source code or can get it if you -want it, that you can change the software or use pieces of it in new -free programs, and that you know you can do these things. - - To protect your rights, we need to prevent others from denying you -these rights or asking you to surrender the rights. Therefore, you have -certain responsibilities if you distribute copies of the software, or if -you modify it: responsibilities to respect the freedom of others. - - For example, if you distribute copies of such a program, whether -gratis or for a fee, you must pass on to the recipients the same -freedoms that you received. You must make sure that they, too, receive -or can get the source code. And you must show them these terms so they -know their rights. - - Developers that use the GNU GPL protect your rights with two steps: -(1) assert copyright on the software, and (2) offer you this License -giving you legal permission to copy, distribute and/or modify it. - - For the developers' and authors' protection, the GPL clearly explains -that there is no warranty for this free software. For both users' and -authors' sake, the GPL requires that modified versions be marked as -changed, so that their problems will not be attributed erroneously to -authors of previous versions. - - Some devices are designed to deny users access to install or run -modified versions of the software inside them, although the manufacturer -can do so. This is fundamentally incompatible with the aim of -protecting users' freedom to change the software. The systematic -pattern of such abuse occurs in the area of products for individuals to -use, which is precisely where it is most unacceptable. Therefore, we -have designed this version of the GPL to prohibit the practice for those -products. If such problems arise substantially in other domains, we -stand ready to extend this provision to those domains in future versions -of the GPL, as needed to protect the freedom of users. - - Finally, every program is threatened constantly by software patents. -States should not allow patents to restrict development and use of -software on general-purpose computers, but in those that do, we wish to -avoid the special danger that patents applied to a free program could -make it effectively proprietary. To prevent this, the GPL assures that -patents cannot be used to render the program non-free. - - The precise terms and conditions for copying, distribution and -modification follow. - - TERMS AND CONDITIONS - - 0. Definitions. - - "This License" refers to version 3 of the GNU General Public License. - - "Copyright" also means copyright-like laws that apply to other kinds of -works, such as semiconductor masks. - - "The Program" refers to any copyrightable work licensed under this -License. Each licensee is addressed as "you". "Licensees" and -"recipients" may be individuals or organizations. - - To "modify" a work means to copy from or adapt all or part of the work -in a fashion requiring copyright permission, other than the making of an -exact copy. The resulting work is called a "modified version" of the -earlier work or a work "based on" the earlier work. - - A "covered work" means either the unmodified Program or a work based -on the Program. - - To "propagate" a work means to do anything with it that, without -permission, would make you directly or secondarily liable for -infringement under applicable copyright law, except executing it on a -computer or modifying a private copy. Propagation includes copying, -distribution (with or without modification), making available to the -public, and in some countries other activities as well. - - To "convey" a work means any kind of propagation that enables other -parties to make or receive copies. Mere interaction with a user through -a computer network, with no transfer of a copy, is not conveying. - - An interactive user interface displays "Appropriate Legal Notices" -to the extent that it includes a convenient and prominently visible -feature that (1) displays an appropriate copyright notice, and (2) -tells the user that there is no warranty for the work (except to the -extent that warranties are provided), that licensees may convey the -work under this License, and how to view a copy of this License. If -the interface presents a list of user commands or options, such as a -menu, a prominent item in the list meets this criterion. - - 1. Source Code. - - The "source code" for a work means the preferred form of the work -for making modifications to it. "Object code" means any non-source -form of a work. - - A "Standard Interface" means an interface that either is an official -standard defined by a recognized standards body, or, in the case of -interfaces specified for a particular programming language, one that -is widely used among developers working in that language. - - The "System Libraries" of an executable work include anything, other -than the work as a whole, that (a) is included in the normal form of -packaging a Major Component, but which is not part of that Major -Component, and (b) serves only to enable use of the work with that -Major Component, or to implement a Standard Interface for which an -implementation is available to the public in source code form. A -"Major Component", in this context, means a major essential component -(kernel, window system, and so on) of the specific operating system -(if any) on which the executable work runs, or a compiler used to -produce the work, or an object code interpreter used to run it. - - The "Corresponding Source" for a work in object code form means all -the source code needed to generate, install, and (for an executable -work) run the object code and to modify the work, including scripts to -control those activities. However, it does not include the work's -System Libraries, or general-purpose tools or generally available free -programs which are used unmodified in performing those activities but -which are not part of the work. For example, Corresponding Source -includes interface definition files associated with source files for -the work, and the source code for shared libraries and dynamically -linked subprograms that the work is specifically designed to require, -such as by intimate data communication or control flow between those -subprograms and other parts of the work. - - The Corresponding Source need not include anything that users -can regenerate automatically from other parts of the Corresponding -Source. - - The Corresponding Source for a work in source code form is that -same work. - - 2. Basic Permissions. - - All rights granted under this License are granted for the term of -copyright on the Program, and are irrevocable provided the stated -conditions are met. This License explicitly affirms your unlimited -permission to run the unmodified Program. The output from running a -covered work is covered by this License only if the output, given its -content, constitutes a covered work. This License acknowledges your -rights of fair use or other equivalent, as provided by copyright law. - - You may make, run and propagate covered works that you do not -convey, without conditions so long as your license otherwise remains -in force. You may convey covered works to others for the sole purpose -of having them make modifications exclusively for you, or provide you -with facilities for running those works, provided that you comply with -the terms of this License in conveying all material for which you do -not control copyright. Those thus making or running the covered works -for you must do so exclusively on your behalf, under your direction -and control, on terms that prohibit them from making any copies of -your copyrighted material outside their relationship with you. - - Conveying under any other circumstances is permitted solely under -the conditions stated below. Sublicensing is not allowed; section 10 -makes it unnecessary. - - 3. Protecting Users' Legal Rights From Anti-Circumvention Law. - - No covered work shall be deemed part of an effective technological -measure under any applicable law fulfilling obligations under article -11 of the WIPO copyright treaty adopted on 20 December 1996, or -similar laws prohibiting or restricting circumvention of such -measures. - - When you convey a covered work, you waive any legal power to forbid -circumvention of technological measures to the extent such circumvention -is effected by exercising rights under this License with respect to -the covered work, and you disclaim any intention to limit operation or -modification of the work as a means of enforcing, against the work's -users, your or third parties' legal rights to forbid circumvention of -technological measures. - - 4. Conveying Verbatim Copies. - - You may convey verbatim copies of the Program's source code as you -receive it, in any medium, provided that you conspicuously and -appropriately publish on each copy an appropriate copyright notice; -keep intact all notices stating that this License and any -non-permissive terms added in accord with section 7 apply to the code; -keep intact all notices of the absence of any warranty; and give all -recipients a copy of this License along with the Program. - - You may charge any price or no price for each copy that you convey, -and you may offer support or warranty protection for a fee. - - 5. Conveying Modified Source Versions. - - You may convey a work based on the Program, or the modifications to -produce it from the Program, in the form of source code under the -terms of section 4, provided that you also meet all of these conditions: - - a) The work must carry prominent notices stating that you modified - it, and giving a relevant date. - - b) The work must carry prominent notices stating that it is - released under this License and any conditions added under section - 7. This requirement modifies the requirement in section 4 to - "keep intact all notices". - - c) You must license the entire work, as a whole, under this - License to anyone who comes into possession of a copy. This - License will therefore apply, along with any applicable section 7 - additional terms, to the whole of the work, and all its parts, - regardless of how they are packaged. This License gives no - permission to license the work in any other way, but it does not - invalidate such permission if you have separately received it. - - d) If the work has interactive user interfaces, each must display - Appropriate Legal Notices; however, if the Program has interactive - interfaces that do not display Appropriate Legal Notices, your - work need not make them do so. - - A compilation of a covered work with other separate and independent -works, which are not by their nature extensions of the covered work, -and which are not combined with it such as to form a larger program, -in or on a volume of a storage or distribution medium, is called an -"aggregate" if the compilation and its resulting copyright are not -used to limit the access or legal rights of the compilation's users -beyond what the individual works permit. Inclusion of a covered work -in an aggregate does not cause this License to apply to the other -parts of the aggregate. - - 6. Conveying Non-Source Forms. - - You may convey a covered work in object code form under the terms -of sections 4 and 5, provided that you also convey the -machine-readable Corresponding Source under the terms of this License, -in one of these ways: - - a) Convey the object code in, or embodied in, a physical product - (including a physical distribution medium), accompanied by the - Corresponding Source fixed on a durable physical medium - customarily used for software interchange. - - b) Convey the object code in, or embodied in, a physical product - (including a physical distribution medium), accompanied by a - written offer, valid for at least three years and valid for as - long as you offer spare parts or customer support for that product - model, to give anyone who possesses the object code either (1) a - copy of the Corresponding Source for all the software in the - product that is covered by this License, on a durable physical - medium customarily used for software interchange, for a price no - more than your reasonable cost of physically performing this - conveying of source, or (2) access to copy the - Corresponding Source from a network server at no charge. - - c) Convey individual copies of the object code with a copy of the - written offer to provide the Corresponding Source. This - alternative is allowed only occasionally and noncommercially, and - only if you received the object code with such an offer, in accord - with subsection 6b. - - d) Convey the object code by offering access from a designated - place (gratis or for a charge), and offer equivalent access to the - Corresponding Source in the same way through the same place at no - further charge. You need not require recipients to copy the - Corresponding Source along with the object code. If the place to - copy the object code is a network server, the Corresponding Source - may be on a different server (operated by you or a third party) - that supports equivalent copying facilities, provided you maintain - clear directions next to the object code saying where to find the - Corresponding Source. Regardless of what server hosts the - Corresponding Source, you remain obligated to ensure that it is - available for as long as needed to satisfy these requirements. - - e) Convey the object code using peer-to-peer transmission, provided - you inform other peers where the object code and Corresponding - Source of the work are being offered to the general public at no - charge under subsection 6d. - - A separable portion of the object code, whose source code is excluded -from the Corresponding Source as a System Library, need not be -included in conveying the object code work. - - A "User Product" is either (1) a "consumer product", which means any -tangible personal property which is normally used for personal, family, -or household purposes, or (2) anything designed or sold for incorporation -into a dwelling. In determining whether a product is a consumer product, -doubtful cases shall be resolved in favor of coverage. For a particular -product received by a particular user, "normally used" refers to a -typical or common use of that class of product, regardless of the status -of the particular user or of the way in which the particular user -actually uses, or expects or is expected to use, the product. A product -is a consumer product regardless of whether the product has substantial -commercial, industrial or non-consumer uses, unless such uses represent -the only significant mode of use of the product. - - "Installation Information" for a User Product means any methods, -procedures, authorization keys, or other information required to install -and execute modified versions of a covered work in that User Product from -a modified version of its Corresponding Source. The information must -suffice to ensure that the continued functioning of the modified object -code is in no case prevented or interfered with solely because -modification has been made. - - If you convey an object code work under this section in, or with, or -specifically for use in, a User Product, and the conveying occurs as -part of a transaction in which the right of possession and use of the -User Product is transferred to the recipient in perpetuity or for a -fixed term (regardless of how the transaction is characterized), the -Corresponding Source conveyed under this section must be accompanied -by the Installation Information. But this requirement does not apply -if neither you nor any third party retains the ability to install -modified object code on the User Product (for example, the work has -been installed in ROM). - - The requirement to provide Installation Information does not include a -requirement to continue to provide support service, warranty, or updates -for a work that has been modified or installed by the recipient, or for -the User Product in which it has been modified or installed. Access to a -network may be denied when the modification itself materially and -adversely affects the operation of the network or violates the rules and -protocols for communication across the network. - - Corresponding Source conveyed, and Installation Information provided, -in accord with this section must be in a format that is publicly -documented (and with an implementation available to the public in -source code form), and must require no special password or key for -unpacking, reading or copying. - - 7. Additional Terms. - - "Additional permissions" are terms that supplement the terms of this -License by making exceptions from one or more of its conditions. -Additional permissions that are applicable to the entire Program shall -be treated as though they were included in this License, to the extent -that they are valid under applicable law. If additional permissions -apply only to part of the Program, that part may be used separately -under those permissions, but the entire Program remains governed by -this License without regard to the additional permissions. - - When you convey a copy of a covered work, you may at your option -remove any additional permissions from that copy, or from any part of -it. (Additional permissions may be written to require their own -removal in certain cases when you modify the work.) You may place -additional permissions on material, added by you to a covered work, -for which you have or can give appropriate copyright permission. - - Notwithstanding any other provision of this License, for material you -add to a covered work, you may (if authorized by the copyright holders of -that material) supplement the terms of this License with terms: - - a) Disclaiming warranty or limiting liability differently from the - terms of sections 15 and 16 of this License; or - - b) Requiring preservation of specified reasonable legal notices or - author attributions in that material or in the Appropriate Legal - Notices displayed by works containing it; or - - c) Prohibiting misrepresentation of the origin of that material, or - requiring that modified versions of such material be marked in - reasonable ways as different from the original version; or - - d) Limiting the use for publicity purposes of names of licensors or - authors of the material; or - - e) Declining to grant rights under trademark law for use of some - trade names, trademarks, or service marks; or - - f) Requiring indemnification of licensors and authors of that - material by anyone who conveys the material (or modified versions of - it) with contractual assumptions of liability to the recipient, for - any liability that these contractual assumptions directly impose on - those licensors and authors. - - All other non-permissive additional terms are considered "further -restrictions" within the meaning of section 10. If the Program as you -received it, or any part of it, contains a notice stating that it is -governed by this License along with a term that is a further -restriction, you may remove that term. If a license document contains -a further restriction but permits relicensing or conveying under this -License, you may add to a covered work material governed by the terms -of that license document, provided that the further restriction does -not survive such relicensing or conveying. - - If you add terms to a covered work in accord with this section, you -must place, in the relevant source files, a statement of the -additional terms that apply to those files, or a notice indicating -where to find the applicable terms. - - Additional terms, permissive or non-permissive, may be stated in the -form of a separately written license, or stated as exceptions; -the above requirements apply either way. - - 8. Termination. - - You may not propagate or modify a covered work except as expressly -provided under this License. Any attempt otherwise to propagate or -modify it is void, and will automatically terminate your rights under -this License (including any patent licenses granted under the third -paragraph of section 11). - - However, if you cease all violation of this License, then your -license from a particular copyright holder is reinstated (a) -provisionally, unless and until the copyright holder explicitly and -finally terminates your license, and (b) permanently, if the copyright -holder fails to notify you of the violation by some reasonable means -prior to 60 days after the cessation. - - Moreover, your license from a particular copyright holder is -reinstated permanently if the copyright holder notifies you of the -violation by some reasonable means, this is the first time you have -received notice of violation of this License (for any work) from that -copyright holder, and you cure the violation prior to 30 days after -your receipt of the notice. - - Termination of your rights under this section does not terminate the -licenses of parties who have received copies or rights from you under -this License. If your rights have been terminated and not permanently -reinstated, you do not qualify to receive new licenses for the same -material under section 10. - - 9. Acceptance Not Required for Having Copies. - - You are not required to accept this License in order to receive or -run a copy of the Program. Ancillary propagation of a covered work -occurring solely as a consequence of using peer-to-peer transmission -to receive a copy likewise does not require acceptance. However, -nothing other than this License grants you permission to propagate or -modify any covered work. These actions infringe copyright if you do -not accept this License. Therefore, by modifying or propagating a -covered work, you indicate your acceptance of this License to do so. - - 10. Automatic Licensing of Downstream Recipients. - - Each time you convey a covered work, the recipient automatically -receives a license from the original licensors, to run, modify and -propagate that work, subject to this License. You are not responsible -for enforcing compliance by third parties with this License. - - An "entity transaction" is a transaction transferring control of an -organization, or substantially all assets of one, or subdividing an -organization, or merging organizations. If propagation of a covered -work results from an entity transaction, each party to that -transaction who receives a copy of the work also receives whatever -licenses to the work the party's predecessor in interest had or could -give under the previous paragraph, plus a right to possession of the -Corresponding Source of the work from the predecessor in interest, if -the predecessor has it or can get it with reasonable efforts. - - You may not impose any further restrictions on the exercise of the -rights granted or affirmed under this License. For example, you may -not impose a license fee, royalty, or other charge for exercise of -rights granted under this License, and you may not initiate litigation -(including a cross-claim or counterclaim in a lawsuit) alleging that -any patent claim is infringed by making, using, selling, offering for -sale, or importing the Program or any portion of it. - - 11. Patents. - - A "contributor" is a copyright holder who authorizes use under this -License of the Program or a work on which the Program is based. The -work thus licensed is called the contributor's "contributor version". - - A contributor's "essential patent claims" are all patent claims -owned or controlled by the contributor, whether already acquired or -hereafter acquired, that would be infringed by some manner, permitted -by this License, of making, using, or selling its contributor version, -but do not include claims that would be infringed only as a -consequence of further modification of the contributor version. For -purposes of this definition, "control" includes the right to grant -patent sublicenses in a manner consistent with the requirements of -this License. - - Each contributor grants you a non-exclusive, worldwide, royalty-free -patent license under the contributor's essential patent claims, to -make, use, sell, offer for sale, import and otherwise run, modify and -propagate the contents of its contributor version. - - In the following three paragraphs, a "patent license" is any express -agreement or commitment, however denominated, not to enforce a patent -(such as an express permission to practice a patent or covenant not to -sue for patent infringement). To "grant" such a patent license to a -party means to make such an agreement or commitment not to enforce a -patent against the party. - - If you convey a covered work, knowingly relying on a patent license, -and the Corresponding Source of the work is not available for anyone -to copy, free of charge and under the terms of this License, through a -publicly available network server or other readily accessible means, -then you must either (1) cause the Corresponding Source to be so -available, or (2) arrange to deprive yourself of the benefit of the -patent license for this particular work, or (3) arrange, in a manner -consistent with the requirements of this License, to extend the patent -license to downstream recipients. "Knowingly relying" means you have -actual knowledge that, but for the patent license, your conveying the -covered work in a country, or your recipient's use of the covered work -in a country, would infringe one or more identifiable patents in that -country that you have reason to believe are valid. - - If, pursuant to or in connection with a single transaction or -arrangement, you convey, or propagate by procuring conveyance of, a -covered work, and grant a patent license to some of the parties -receiving the covered work authorizing them to use, propagate, modify -or convey a specific copy of the covered work, then the patent license -you grant is automatically extended to all recipients of the covered -work and works based on it. - - A patent license is "discriminatory" if it does not include within -the scope of its coverage, prohibits the exercise of, or is -conditioned on the non-exercise of one or more of the rights that are -specifically granted under this License. You may not convey a covered -work if you are a party to an arrangement with a third party that is -in the business of distributing software, under which you make payment -to the third party based on the extent of your activity of conveying -the work, and under which the third party grants, to any of the -parties who would receive the covered work from you, a discriminatory -patent license (a) in connection with copies of the covered work -conveyed by you (or copies made from those copies), or (b) primarily -for and in connection with specific products or compilations that -contain the covered work, unless you entered into that arrangement, -or that patent license was granted, prior to 28 March 2007. - - Nothing in this License shall be construed as excluding or limiting -any implied license or other defenses to infringement that may -otherwise be available to you under applicable patent law. - - 12. No Surrender of Others' Freedom. - - If conditions are imposed on you (whether by court order, agreement or -otherwise) that contradict the conditions of this License, they do not -excuse you from the conditions of this License. If you cannot convey a -covered work so as to satisfy simultaneously your obligations under this -License and any other pertinent obligations, then as a consequence you may -not convey it at all. For example, if you agree to terms that obligate you -to collect a royalty for further conveying from those to whom you convey -the Program, the only way you could satisfy both those terms and this -License would be to refrain entirely from conveying the Program. - - 13. Use with the GNU Affero General Public License. - - Notwithstanding any other provision of this License, you have -permission to link or combine any covered work with a work licensed -under version 3 of the GNU Affero General Public License into a single -combined work, and to convey the resulting work. The terms of this -License will continue to apply to the part which is the covered work, -but the special requirements of the GNU Affero General Public License, -section 13, concerning interaction through a network will apply to the -combination as such. - - 14. Revised Versions of this License. - - The Free Software Foundation may publish revised and/or new versions of -the GNU General Public License from time to time. Such new versions will -be similar in spirit to the present version, but may differ in detail to -address new problems or concerns. - - Each version is given a distinguishing version number. If the -Program specifies that a certain numbered version of the GNU General -Public License "or any later version" applies to it, you have the -option of following the terms and conditions either of that numbered -version or of any later version published by the Free Software -Foundation. If the Program does not specify a version number of the -GNU General Public License, you may choose any version ever published -by the Free Software Foundation. - - If the Program specifies that a proxy can decide which future -versions of the GNU General Public License can be used, that proxy's -public statement of acceptance of a version permanently authorizes you -to choose that version for the Program. - - Later license versions may give you additional or different -permissions. However, no additional obligations are imposed on any -author or copyright holder as a result of your choosing to follow a -later version. - - 15. Disclaimer of Warranty. - - THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY -APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT -HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY -OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, -THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM -IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF -ALL NECESSARY SERVICING, REPAIR OR CORRECTION. - - 16. Limitation of Liability. - - IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING -WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES AND/OR CONVEYS -THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY -GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE -USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF -DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD -PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS), -EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF -SUCH DAMAGES. - - 17. Interpretation of Sections 15 and 16. - - If the disclaimer of warranty and limitation of liability provided -above cannot be given local legal effect according to their terms, -reviewing courts shall apply local law that most closely approximates -an absolute waiver of all civil liability in connection with the -Program, unless a warranty or assumption of liability accompanies a -copy of the Program in return for a fee. - - END OF TERMS AND CONDITIONS - - How to Apply These Terms to Your New Programs - - If you develop a new program, and you want it to be of the greatest -possible use to the public, the best way to achieve this is to make it -free software which everyone can redistribute and change under these terms. - - To do so, attach the following notices to the program. It is safest -to attach them to the start of each source file to most effectively -state the exclusion of warranty; and each file should have at least -the "copyright" line and a pointer to where the full notice is found. - - - Copyright (C) - - This program is free software: you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation, either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - -Also add information on how to contact you by electronic and paper mail. - - If the program does terminal interaction, make it output a short -notice like this when it starts in an interactive mode: - - Copyright (C) - This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'. - This is free software, and you are welcome to redistribute it - under certain conditions; type `show c' for details. - -The hypothetical commands `show w' and `show c' should show the appropriate -parts of the General Public License. Of course, your program's commands -might be different; for a GUI interface, you would use an "about box". - - You should also get your employer (if you work as a programmer) or school, -if any, to sign a "copyright disclaimer" for the program, if necessary. -For more information on this, and how to apply and follow the GNU GPL, see -. - - The GNU General Public License does not permit incorporating your program -into proprietary programs. If your program is a subroutine library, you -may consider it more useful to permit linking proprietary applications with -the library. If this is what you want to do, use the GNU Lesser General -Public License instead of this License. But first, please read -. diff --git a/lib/CPUs/MIPS/dist/makedist.R12 b/lib/CPUs/MIPS/dist/makedist.R12 deleted file mode 100644 index 0d74ee1..0000000 --- a/lib/CPUs/MIPS/dist/makedist.R12 +++ /dev/null @@ -1,32 +0,0 @@ -#!/bin/sh - -USE_TAG=MIPS_R12 -PROJECT="mips_sys" -DIST_DIR="./release/mips.r12" - -echo Log for $USE_TAG >$USE_TAG.log - -# --------------------------------------------------------------- -# Export files tagged for this release -# To avoid CVS-problems with renamed files: Don't tag on per file basis. -# => Tag upper directory then delete tag from unwanted files!!! - -# Release notes -cvs export -l -d $DIST_DIR/ -r $USE_TAG VHDL/lib/CPUs/MIPS/dist >>$USE_TAG.log - -# VHDL files -cvs export -d $DIST_DIR/src/ -r $USE_TAG VHDL/lib/misc >>$USE_TAG.log -cvs export -d $DIST_DIR/src/ -r $USE_TAG VHDL/lib/uart >>$USE_TAG.log -cvs export -d $DIST_DIR/src/ -r $USE_TAG VHDL/lib/FIFO/src >>$USE_TAG.log -cvs export -l -d $DIST_DIR/src/ -r $USE_TAG VHDL/lib/CPUs/MIPS/src >>$USE_TAG.log -cvs export -l -d $DIST_DIR/src/ -r $USE_TAG VHDL/lib/CPUs/MIPS/src/core >>$USE_TAG.log - -# Simulation files -cvs export -l -d $DIST_DIR/sim/ -r $USE_TAG VHDL/lib/CPUs/MIPS/sim >>$USE_TAG.log - -# Documentation files -cvs export -d $DIST_DIR/doc/ -r $USE_TAG VHDL/lib/CPUs/MIPS/doc >>$USE_TAG.log -rm -f $DIST_DIR/doc/*.vsd - -# Tools -cvs export -d $DIST_DIR/tools/ -r $USE_TAG VHDL/lib/CPUs/MIPS/tools >>$USE_TAG.log diff --git a/lib/CPUs/MIPS/dist/makedist.R13 b/lib/CPUs/MIPS/dist/makedist.R13 deleted file mode 100644 index be6da72..0000000 --- a/lib/CPUs/MIPS/dist/makedist.R13 +++ /dev/null @@ -1,32 +0,0 @@ -#!/bin/sh - -USE_TAG=MIPS_R13 -PROJECT="mips_sys" -DIST_DIR="./release/mips.r13" - -echo Log for $USE_TAG >$USE_TAG.log - -# --------------------------------------------------------------- -# Export files tagged for this release -# To avoid CVS-problems with renamed files: Don't tag on per file basis. -# => Tag upper directory then delete tag from unwanted files!!! - -# Release notes -cvs export -l -d $DIST_DIR/ -r $USE_TAG VHDL/lib/CPUs/MIPS/dist >>$USE_TAG.log - -# VHDL files -cvs export -d $DIST_DIR/src/ -r $USE_TAG VHDL/lib/misc >>$USE_TAG.log -cvs export -d $DIST_DIR/src/ -r $USE_TAG VHDL/lib/uart >>$USE_TAG.log -cvs export -d $DIST_DIR/src/ -r $USE_TAG VHDL/lib/FIFO/src >>$USE_TAG.log -cvs export -l -d $DIST_DIR/src/ -r $USE_TAG VHDL/lib/CPUs/MIPS/src >>$USE_TAG.log -cvs export -l -d $DIST_DIR/src/ -r $USE_TAG VHDL/lib/CPUs/MIPS/src/core >>$USE_TAG.log - -# Simulation files -cvs export -l -d $DIST_DIR/sim/ -r $USE_TAG VHDL/lib/CPUs/MIPS/sim >>$USE_TAG.log - -# Documentation files -cvs export -d $DIST_DIR/doc/ -r $USE_TAG VHDL/lib/CPUs/MIPS/doc >>$USE_TAG.log -rm -f $DIST_DIR/doc/*.vsd - -# Tools -cvs export -d $DIST_DIR/tools/ -r $USE_TAG VHDL/lib/CPUs/MIPS/tools >>$USE_TAG.log diff --git a/lib/CPUs/MIPS/dist/notes.txt b/lib/CPUs/MIPS/dist/notes.txt deleted file mode 100644 index 78f7c0f..0000000 --- a/lib/CPUs/MIPS/dist/notes.txt +++ /dev/null @@ -1,100 +0,0 @@ ------------------------------------------------------------------ -Changes in release 13 ------------------------------------------------------------------ -- mips_biu.vhd: added asynchronous BUS-FIFOs to support different clocks for CPU and BUS -- mips_dcache.vhd: improved instant-RAW stall behavior (faster execution) -- uart_WB.vhd: added simulate_TX generic for plain TX output in simulation log - ------------------------------------------------------------------ -Changes in release 12 ------------------------------------------------------------------ -- reworked GCC-toolchain: Valid mips*-elf-binaries are now compiled and linked - using a single mips*-elf-gcc command. - To use: Copy $THIS_RELEASE/bsp/toolchain/specs to $MIPS_GCC_PREFIX/lib/gcc/mipsel-elf/$GCC_VERSION/, - and see bsp/examples/Makefile gcc usage - GCC-provided crt*-functions are now called without problems. - In summary: The toolchain is now more compliant to the intentional use of GCC. -- mips_biu.vhd: Addresses 0xA0000000..0xBFFFFFFF are now un-dcached for memory-mapped I/O, - which is now compliant to literature. -- gpio_wb.vhd: Timer hard-reset is now removed. This helps to keep current time in case of CPU hard-reset. -- new bsp-example source: gunzip -- updated drawing 'mips_jbus_timing.pdf' -- added drawing 'memory_map.pdf' -- moved COP0 from mips_pipeline.vhd to mips_top.vhd. Created new cop-interface for later COPz connection. -- added I/D-cache info (size and linesize) to upper 16 bits of PrID-Register. - Example of reading cache info is done in bsp/examples/testbench::PrintCPUinfo() -- simplified instruction decoder in mips_instr.vhd. Now there are less warnings during synthesis. - Removed idecode_rom.vhd from project as consequence. -- added cop0 instructions to invalidate I-cache and D-Cache -- added copz instructions lwcz and swcz -- gpio_wb.vhd: added 32 bit timer with interrupt and auto reload -- added debugger in libsys. New files are mipsdis.c/h and dbg.c/h -- exception handlers can now be registered to any exception type -- bugfix mips_pipeline/mips_cop: cop0 registers were not written during exception commit. Cop registers now behave like general registers. -- added pin 'eb' to mips_top.vhd to select CPU-endianess at reset time (eb = 0 : little-endian, eb = 1 : big-endian) -- Status register bit 'RE'= 1 (bit 25) reverses endianess in user-mode -- Status register bit 'TS' (TLB Shutdown, bit 21) is tied high to indicate the absence of an MMU. -- uart_wb.vhd: added interrupt enable -- Interrupt pending flags (IP) are not anymore masked by Interrupt mask flags (IM) in H/W. - Masking has to be done in S/W. H/W masking was removed because it isn't MIPS-compliant. -- added NMI/RST pin (more MIPS compliant). Transition Asserting/Deasserting causes exception. - Exception vector is reset (0xBFC00000). It's a soft-reset, which can help debugging. NMI/RST is not maskable. - Using NMI/RST as reset is dangerous because periphery may not be reseted. Has to be done in S/W. - Drawback of using NMI/RST: Unitialized/unreseted periphery may cause trouble (e.g. firing unwanted interrupts), but I think you know that already. -- Bootloader: Startup.S now invalidates I/D-Caches at boot. -- uart_wb.vhd: fixed crappy tx-empty interrupt, Added Tx-IRQ acknowledge. -- Bugfix in mips_pipeline: register bypass with same target register, used for unaligned loads (LWL, LWR), was incorrect. - Newlib's MIPS-optimized version of memcpy() uses this for unaligned copy which revealed the bug. - Symptom: Consecutive load instructions without nops using same target register (which is legal) like - lw $1, 0(mem) - lwl $1, 1(mem) - or - lwl $1, 0(mem) - lwr $1, 1(mem) - or similar, lead to incorrect result. Now it's fixed. -- Bugfix mips_biu: instructions uncached LW => cached LW (with cache-miss) was buggy. - Symptom: - ... - 1.: lw $a0, 32($s0) # Uncached load from memory mapped I/O - 2.: lw $a2, 4($v0) # Cached load and cache-miss. - # $a0 receives same value as $a2. - # CPU skips writing $a0 due to busy flag of D-Cache, - # which is already active in the previous cycle - ... - ------------------------------------------------------------------ -Changes in release 11 ------------------------------------------------------------------ -- bugfix in mips_pipeline: pc_is_branch is now initialized at reset - (fixes CPU unrecoverable state after reset) -- reverted "optimization" in mips_dcache, which behaved buggy during exceptions -- new example source: test_exception -- minor changes in libsys -- added async_port_timing in doc -- examples/testbench: date set now really works - ------------------------------------------------------------------ -Changes in release 10b ------------------------------------------------------------------ -- bugfix: fixed compiler bug (missing nop after lw) in bootloader, - which caused exception during boot - ------------------------------------------------------------------ -Changes in release 10a ------------------------------------------------------------------ -async_port_wb: -- added byte enable for async_port - -bootloader.c -- bugfix: fixed compiler bug (missing nop after lw) - -mips-core -- bugfix: SEL_O lines are also asserted correctly during reads - -tools/romgen -- TCL-Jtag now compatible with Chipscope 10.1 - -mips_sys.c -- use byte enable for sram and flash - - diff --git a/lib/CPUs/MIPS/doc/J-MIPS.txt b/lib/CPUs/MIPS/doc/J-MIPS.txt deleted file mode 100644 index 43448cb..0000000 --- a/lib/CPUs/MIPS/doc/J-MIPS.txt +++ /dev/null @@ -1,109 +0,0 @@ ------------------------------------------------------------------ -J-MIPS Features ------------------------------------------------------------------ - -- Synchrones Design -- Portable Beschreibung in VHDL -- Kompatible zur GNU Toolchain (Binutils, GCC, Newlib) -- Befehle kompatibel mit MIPS-1 ISA (z.B. MIPS R3000) -- 5-Stufige Pipeline und Hazardvermeidung durch Forwarding -- 64Bit Multiplier (32Bit Operanden), 12 Cycles Latenz -- 64Bit Divider (32Bit Operanden), 36 Cycles Latenz -- Coprocessor 0 (COP0) für Exceptionhandling -- Direct-mapped Instruction Cache mit variabler Größe, 8-words per Line -- Direct-mapped Data Cache mit variabler Größe, 8-words per Line -- J-Bus kompatible Bus Interface Unit (J-Bus ist im wesentlichen FIFO interface mit 'wichtigen' Signalnamen) -- 1,2 DMIPS/MHz mit 16Kbyte I/D-Cache (Dhrystone 2.1, GCC 4.3) -- Endianness umschaltbar zur Hard-reset Zeit -- Unterschiedliche Frequenzen für CPU und BUS möglich - ------------------------------------------------------------------ -Known Limitations ------------------------------------------------------------------ -- keine MMU -- keine Unterstützung für Bus exceptions IBE und DBE -- kein externes Coprocessor interface (COP1..3) für z.B. FPU -- Befehle für Cop1..3 nicht implementiert: - CFCz, CTCz, COPz, MFCz, MTCz, LWCz, SWCz - Benutzung dieser Befehle führt zur Exception 'RI' (Reserved Instruction) -- nicht alle COP0 Register/Bits vorhanden. - ------------------------------------------------------------------ -Known Bugs ------------------------------------------------------------------ -- es gibt bestimmt noch nicht entdeckte Bugs - ------------------------------------------------------------------ -Known Optimizations ------------------------------------------------------------------ -- Area: Multiplier als technologieabhängiges Primitive instanzieren -- Area: Auf Divider verzichten -- Area: Auf Multiplier verzichten -- Area vs. Speed: Bei Hazards Pipeline-stall statt Forwarding. - Durch Stalling geringerer Befehlsdurchsatz dafür weniger Logik. - Weniger Logik bedeutet vielleicht wieder auch größere Taktfrequenz. - ------------------------------------------------------------------ -Known ToDos ------------------------------------------------------------------ -- Unterstützung für Bus exceptions IBE und DBE -- Externes COP1..3 interface, fehlende COP-Befehle implementieren -- Optimierungen evaluieren und ggf. durchführen - ------------------------------------------------------------------ -Synthesis results ------------------------------------------------------------------ -Virtex-4 XC4VSX35-10 - -Config: 16Kbyte I/D-Cache - -Number of Slices 2387 15360 15% -Number of Slice Flip Flops 1784 30720 5% -Number of 4 input LUTs 3962 30720 12% -Number of FIFO16/RAMB16s 18 192 9% - -Speed: 110MHz nach Synthesis - ------------------------------------------------------------------ -Virtex-1 XCV1000-4 - -Config: 4Kbyte I/D-Cache - -Number of Slices 2045 13824 16% -Number of Slice Flip Flops 1783 27648 7% -Number of 4 input LUTs 3923 27648 15% -Number of FIFO16/RAMB16s 20 32 62% - -Speed: 30MHz nach Synthesis - ------------------------------------------------------------------ -Performance bei 100MHz -- GCC ohne Small-data section -- MIPS Rev. 9 ------------------------------------------------------------------ -I/D-Cache Dhrystone-2.1 RipeMD-160 Whetstone Stanford Queens(12x12) -1k 32 DMIPS 5 Mbit/s 345 kwhets/s 47/767 2,135s -2k 51 DMIPS 5 Mbit/s 534 kwhets/s 38/561 2,134s -4k 72 DMIPS 5 Mbit/s 623 kwhets/s 36/259 2,121s -8k 98 DMIPS 10 Mbit/s 1149 kwhets/s 31/228 1,938s -16k 115 DMIPS 17 Mbit/s 1234 kwhets/s 23/225 1,938s -32k 115 DMIPS 17 Mbit/s 1285 kwhets/s 24/218 1,938s -64k 115 DMIPS 17 Mbit/s 1285 kwhets/s 20/221 1,938s - ------------------------------------------------------------------ -Performance bei 100MHz -- GCC mit Small-data section -- MIPS Rev. 9 ------------------------------------------------------------------ -I/D-Cache Dhrystone-2.1 RipeMD-160 Whetstone Stanford Queens(12x12) -16k 117 DMIPS 17 Mbit/s 1236 kwhets/s 24/230 1,811s - ------------------------------------------------------------------ -Performance bei 100MHz -- GCC mit Small-data section -- MIPS Rev. 10 ------------------------------------------------------------------ -I/D-Cache Dhrystone-2.1 RipeMD-160 Whetstone Stanford Queens(12x12) -16k 120 DMIPS 17 Mbit/s 1242 kwhets/s 25/219 1,803s - - diff --git a/lib/CPUs/MIPS/doc/async_port_timing.pdf b/lib/CPUs/MIPS/doc/async_port_timing.pdf deleted file mode 100644 index 8e2a4d2710df8eb6d738203e8c02a5b265ded598..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 10447 zcmbVy2UwF!^RI#wkzS<-1?eOq1PCBV?^30T)KG*3NJ2-D4kAU0bdVxdiWHG9g3^&9 zO{I5f0)kYz3CDAe=X~G2|9fxpRhI?1z%tFg3Ka*UPGvel!9k3v<`iAff=u{bV}+Y75AFsgJ#`1&2G5qGYFbCb`}Ixf&CN&iu+mpo*~@-<_m@Dj7fM>v^}5eqpU!zDPC|HPTQF_`Ed!ZINfn z)RDhl*32rg7E0$8W?!b!c4+g3)8GAJXTk*DcR9T8hqQo>no`Z4<;Svt4tJE1-lj_W zYVg^*{rQnFK_AOq{glf+w;I<_injc1p=@h*E&bq$oWXxpnPIhtQzalo#p3ZBF zEaMlt{q(buQE%-K;ow2+9S3!*QIlaKDkk`I#-)X^m7};uY4hP{u+Jr1{bR0u&|}P= z*6E?He{)=!Oop{aqxX|ntd?8|uObz&oA=GH%J{D`Tk|E>y}VO8(6^&67s- zmmSs-SH~6Wfmh$BzP%aoWrnl%iSB!GnSHXw^@sK4`p82ku;q(<&1y1UHv;d0sXPON zs#T_-Nd64ilhpE=D~4PfS?Y?8bxbTJ>hI#q`2BJgMd@k6iq@m%P1S9KOs)r25fO8t z?*ps{=U)zF-!Dj}pp3G_XY3hX9m~F-v|6!-?Y2E*y|$%Y-L$uKf!#}(r8YUYSb1?% zzSc<4-3k2j5Nqpj)|s>(i+!vFL$C0YLbD7RmkRRjbe_xV`RMd2ZJh>LL3b`Y0V6IS z0Xr_OcV+6&X+_Nh6YT32?LEkSBgV7tR#`+nBihrHkXo&uTedOYm)9c5u9EcoG)%nu zqHvvOql&*$>@+qQGkEkPBmWIY*lQ}3eMvEIywrOYd0I{Stt*7JONT38h^8S;ffqu< zXZJWPzBTAS&0qccmNjs?jj)+hO129sC41Q_(@A$bZ}m}D{Gty-{Y&Q8V;T*a3qkKo!<_5Zy3eyXq9P z!c;?0I^#Egs0IhsGk zvo`yJ+j(gmCsAjPMs9r(pLd~dohhlWdd803<7d&ly72yr3>F$c329RF=~VUd^*eI? zRK2ItVk%Czk#Bkzg-DfRukY${S2Sf^wQTf-t1GU6&0UHfQFJE8lRqK5F{RL+NhENh zn;2Ge5nX)h($vU0_?*;vKGbmehU ze+UqIJ5bMhN-C6ayrD6B4~g*&b584F>iFKmZ}jTa`*Q8q?vK)C z;%&XT*rl%_7j|=1N#?y^fF!@<67QuHi_5-0RbD0C%9qnMlQt&`%1(W&TvNHznV$gY3$mjBZ6V4Q_rrt6KL&l*VINyznu6hYS@>Tj$r8V z$`G(l_MWkzY@%its}y>%mW@wlxnXY}5gD14NqVWy=VR|sznl&8s#?*7RW(&Y`xksk zt|RDo#I!GYBvU)`PCvG}T-V`3dN7Dzi4bRIsoZXi0WAPjC6@3xyT)qJo_+`SmFMkH zfc}`+tHV9CgVw}{uxLI-Hr-{|Hm3fVV1W}7jX^}7##XWhZWpLrnhRiE!^ zEKh@eL;?MJqjlJp@8+lQ*TV?ZrUHOOt4>{BBwrui)E;nIb;#KvZ~gS~jf27>VoM#= z)NFP;N;^eogQ;?AO~75ndrIT=2lMA-5w_2*YUC}5z%3Ls8QQL4IqD4^Y=H4prq1M& z6?9lJtCRFCkx;VUf}0Xk+4muX6Y|)eDGcA5tk|7nt~ShK-T1{ARab$o_ArsZpAay^}+g1{Cs z1iU_D+zMFtvuX73ZfaZ!5b?(6v;s>$ex z+-8rkjeDnA2aAQ})d@XjDKeF1ggVIA1M0lFEa7@LC)Xptv|m_!^en*YeSwI*M-lDY zGJZI!^2-l-tYO=FXERq!uC&e=X%=USnC;OBuKC&1>R(>(RWW7Kykwy7&bdFaH~#s( z56DdVXVUfhL@SpP!CkqnK&@I&Qh-@6xDf;Hm=P-y(i{#6`ApOjM&=7Z-fA@P&0j6zgtW+}GAhm}6N$=1W81l%A3++TzspD6|1IpD3fY$7%Vfssf9 zscxEPMp))WM4l{$rSDBt$M>{S*~L=H&f}bjMk1Ryt$iPl*f1N4B{814(qmTa(Vv#C zQ@6sdRAHbDTr1oOW)ITt)WF;UWOJH}%0zl`QY2oG-!(b1pC!S3CQY4or*Zo}6~p&aO;?YBPpw4wcTbbSdl_TYPgCj~0} z=xRD5M(ap0SGK=nJ&%H9{!5d2i{W5LnWENA^VK^f)(gv5>oa$%h76b=Jj>-!vQS9utX!?>nE2*WdYxP%ukHN*DJ5yM&VSKl4per@*d z%x^>>e}&24W;xy4rqWYEW+c~8A|`7eiJIT~pdg|C=rVI@=%yYbgq-QU$Ie>KBTG0I z4Nb3T5g&4Re!bIAz93dm1$bWTD8*cPpKi9s@0Ix(j|J7=r;=WPNfQ79x;<# z+U$}+E9+#GwTy(K&Zf1`;RDd+47Fa=?Up)e>wTtwK61gPtb!KOI?5S9xCM`8dF zTn>aK!_m%eC~G(xn;mJRoUQfX7*ilNe*ysY;hq?*oT4X2S?^pFEc}Ovk~3Bu{D(X? zVFJoy`&f-=04~weCBc$@*@t8KBk{s&!x{)Uw-5~gsyo=A0j4B4`*lgo09XxfIF)}J z`L_=6UpjuNkhjEGIyu|@sp~H@e$6TNPyWBnCjn|{YXZR1(!UtbSMw_^)DxDWFfIBw*%4+yGW!g67BF; zU(d}7gNtXJhp-#=XE>d^{y%)Jqo<)S`?s$J<(!>t{_XJdMd+UEJ0JSpsk2~g7kjmE~-`TK*5JQASM zFEvoyFz#i;9(6oGS)d$H9;g6R1gZlyfVx0EpgzzLXackZVqZfz$^q>Nv;o3_4nQX$ z66g$c0iu9tAO`3LbVJ&}QD|#t6ddTmd%j?7JqZp0fX`30-=Y@R|K+MbDo(!_oUk_k z9_;deR;Yx9#f7D%|Efi082A|JkI>76rNGeA3Ia>aeFG^$Gx(f<5Po8&xo?ygspQHH zj-nt$;;?c_NF!};99tz<-#r^MA|2mE%Of2>!bd6j_ej?*AB#Q=hjRU}6?5Ehh%xt| z_&(BfHnnw9)ql^YyvEP*bbpKG=@TNbKo8+^c)r>oFXQ)s+Dk0`bG)*i#V-Pl{4{q) zc=Cn4oF72g9ObUkUX$n8dCJ?`YS}#TW4?jro8gZr0tXw@anb!SV=hJhT)Pj^W==ID zaoM)E-roDIH8+Ur`9tx23Yx&eat$M%WI{J*Ii2sN?c9Qm)8`I^=EK<3_H? z5aUPBP}XS9>?ibny|ROy%zS2fkku> zu&NnogrG!RRDNMWvtipc`|K3}7A)K_HAfp2ILxO)A5`@As*2W_dMSN@MU`pMw8l*l z{p^uh%+>X{KHh=HA@wg_GG#1!+X2eubC9hjY936bp^q-4%J|-HvT-H8{qhrIXVq=m z$8l}8Lt_JtA_;v$QBSpJV+G*;wlQ?;Rw+|Rk%;KQ*8ycG5n2bpkKSp0`Vj9?iTbse zlel4yRJC~$&fR*FFzpuw9Xr9-UcPvnS9|thE=%v|Z0S8ni-G=X z(h}plYefe-!`(GtQb?5Xdj;VT4ce-7Rd_xGl5Dl4lOJr{dXm^>VU-e=tZ^eUrDs7n zLW4T~11Ds)SKO9_i}t$R5`@_(v(GMuXp$j;c7fO%(kVFH_0@*krgqV7$9e}DV(?N2 z+|K)&;q~cVq90YdMd?Ig@(;E<31aG810&zjR}`01m&|cTH_k!$Rfv^SH&f`&=8oPJ zKTMjuuiGO_Ov)$c%7B{90d|{N8XnP;zll7J*WbF^+IQc7_d+%QoynH;Ce%EtfkR8) zZ>=K`#q(pGG>Xsiq6ysZT2M<7smpr*XxUFPz)Nfa$UOFcw7h9j!m;Rl<=Vh}1V331?|K3Pp{u2dBH=vE1`)Vu95 zX{V9hk!fPnC*77fWH*P{#|qZs1nzUMt2;%xsn+l5BqOM-paCr0z@^+AYve%kWURzvyR;Sa(tB|i-{X(2HUBQc2=H?$A z-6F7LZ)p0YZC*4Sq%5@_b}t1;c)f;zdVZ3VN-rh z>Fb?xGGC_fxlWvrJ;epjO(MOFo2wrh+`P%=*%<;Clf6u}EK~fFZD_N0OSs8^nkUid zZpC<%^%qM!yiysch$<8nYV;9*p!{K9L2qkmf6XE$ zw^pw;#<({fK#@#Ny!h^+$-bHuZt}y%@onJ0a8j^4nLe@o&N|eIV^} z5hA}Mb|QJq!l;$Tocfd@eh3+S+-u^oS6Ba3jq~=srlYRMP^;lgwZ43_51ZbbJTgh2 zZ@>Q`5LQ&3LP3g|b}fG(gUS+h^Vm;&dUIuEfnr+b%dSJ(;-Hcy4~x5BfVKB{s~_Wf z9`uH+zHr14+<%GTH63CJnN;H1aj}nXafv|`>ZIU1F)PK8oPO=@e|$XB*o|B z;qu$MldXv~u4v&^eUf)65$fMNfDRSH6Ef;4<7OwhN^aQ{ZtGhsi;#o>s!OSDb9yu! zWCYFGtyRL=nAPm$i8SX-e&b6>Ns1EF?S}bb3=;rfSdY zJIkCPvq#PS*}$Q+N!5=r3wN&eK*>K3FO~8iUPLa-Oi8XNos77z@gYK}6Aed&CgcJg z9W%{airyf-S>U@blafw->q-`Tz53MoO<3&)Obd%#&u(Y-K6HXsA}1_7)bib!4X;ZZ zN`2WI9K>(a{FGLH_TV_+hM&HtZ;H@9({ovg#uuTk-@QiIUpxdvV=P%Qa?6F6PL~XM zDz0s2PB7au?HnWs?MvLO4v$MHo4dm{w~TiIKM9Y%eteWeToa7U{%KR0#J|NSO-cEf z7fr0LtGYyK$uYOve>%xsZEVihMfk#S`ba$SUf6bz-tv0}U$SgU@7Xoy>fFi;u$!^t z9dm}3@l0m^`)!}BhoU|X4~l$w92TCQ7ysS)n#GOa?>{b#y~yZ*Rj~nkWcdeDn?@;$ z$w%1li}#7`7kWgew}?FS{P27|uhibL&0u4Nc-H0?zHvE2kFt&S1^vFSbw6`M!)nOt z?E88g(|Y4&2j3=cl{!yK3|-(DK{zN&bxgxTj=YG~*SMZA32QXGwUoULEeq_P$rcp6 zbIg~Pso;2+SM%ODA;Y~pLDHj5h=NluVl(7w_kfK*TBd;Md&=T&KA8)KT)%en^#uRD zUT^q#q`9HkEgOuCYA%4r?s+WHQo2AhV(e{PN3&aXQcg}+r;(~Zp1>U~Cm{ugLK_dS zhK-GasY&<1sZ<0^(~*KnqKc^dR%qyeU0FPWwS(LvSAE4`d(rr~Ybcs%Y17RALdIgt z`sM-mw@H4hS_i!P`5oSy0*$gAN0Gq0WTsL-r)UdX7&aG`z?Z^@Ab=nviD9oFz18dH zZq_BupCV$lWDK6Lcn!#CEX`ZK(}+F^N!2T2>}nN0A~=2$wD)qc zha=BnCgL1uIwRp&u<3%!)t%tBm_J%591cE5plBCMYd98%V(d|H?9;>fUx*aw^$$#X zo|*rKNq@T%{eQuv!s5SUQhhINT0^F-(3H)m*0kL7A>T!A1oBYQI7iWOfIOeYK5Ko* z)7A^Z2#@uX62HgixX~?dsMAW;$wN&MP8?{;_lTN?_Z`0OQ)RW%*Tzw*BK2hld+XOt zkC_CZXPfNhUnTvg52aIe541%zDbf*@3n^c6WZCH)Yp=owJ$aL#DjlhCG}n!9HqF%V z$rrX49|usg-^#vVPWxM)#t*_hxhI*QT`6=9o3sT3|1|8BD))oIh7`W~2%0{m#rm4H6?M$N51>!Ae&B!C0 zAGUL8lNXF9$(5;BrU{3Y+S6TR*|aEg>RGhG@+dT394X+77|!wQ=Fpr zI4Ps^>%`qcJ+G=KL?0NnaD*^njWu-2TE!ReV#vJj)i*}?EOj(E56vAf8k{$Yb1)wAwJJPLtH$ zg1N3b8k+Ey2TE?Tt<-5vZ*FZErlx?Hu6R}p)n7U5)Q~Pdt1ELK9yR&N(QsehwacU( z&X8DpfA(N^_CS5h^XOBZ#_cAD@Q*6#TQ7H?ex-?fvB%))85}Zof&SQBW5~9V{!4mzz;7V;-q0slI%ou+myWt8ATHlA+PtF2$lkKv<> zcgL>f@oN}MYVfF-g}={v%$jeaJjva$YpO$Zv{XWa=xlb_h}MFI+kDfgxS!7~Joj|` zep<}>zOP|xEz(iobLC6anoHc}S2Ek=*XX|O5b}D+VH+=bax%W6f0c*l%L$V(tj+W!W>@J{`le|Lh z^l-Ny=3x<_?^Bus>jQIC8nTU(FNs}UQ!=zZzp6DDapb4?ctnz$}~5Nt#Jz8wul^AcNdLHlMjETI^o(Zq94A!%UyQ|K_uemvfB zt<+5pY3Zi5AIhbZJ5RIRWrB2mSk6F9J`s4O4v|zdCT8!?#h0Y@QgCO!6S?>RLe2k; zg=JTrM?rR`tt?YQa4Cf@MQPc}=2n)zpiIT5-NQ^W#FzKSsfb!8ll~`}AIraudk9R& z)$*pT9Y6QT+GhaNUNUHNG3Sk|_T($s>Kzx$YWGC2kiUg|la#R}AeEWcf3Tk*`ZOc$ zmB`Pw^hv=GDdRNV2hTTR_qJfH{K)uesl_DzXQOJ<6`oh}MJ5ZZ+OE@oh|Y+2U7c-- ze&BCh5-3p_DaH}r%z1V}ep)uxA2?sbr_vEfJYqK=^+QT*+hj4#GLi1=vajo$#I490 z&PC%>=fe8z`9wXB)w%4Y==o#T6sgUP_>+hv!YZxhj5d9_dVa+ZXU`FXe!|!G4h}nG zlU~L)aAsXT@naA)dv`H)ib!JhqC97(y!?}N?I+c0!wru#4sz{9J=C0T7;p%g?8{Pe z(p`{e54Grw{b7;jo1q1fOmp}7`GAaY>gLC2zj*-XS8kSoHg3&!>#^*)Avrdsk02Ql zwl%4-1V*u8ht~O*z!>~|IJaMD7)qCIxVHA9E{umro`Tr(;awzyQMM@>55YfCwR!Lr z-jMylLLpFqE#Mao0)=3gjQaqPf6`!L zV%VDVKWPvVQEb`rUo;5lKWHEj7z-u;#V3rbcmIn975~pUL}CA7i--smd;joHSrHKQ zKjshvgR!?4|Kx*+3jc>JMD)Mt6BEH!um344CIZFYkNio)pe(VaTom>n1_3}l2X8pm zrvU8znKSl^3L7uF0H7+;))|0{9qa{~ssg}NN)93pl2uev6joADf+{FNK*Dn3U?^Bj m6eK4Ok{6Se{+~I_a2IE2j3o+lzL7APm)iN5)jBjRtExENLUmoTMbJgBoBy&Jj|ki11=TnNNB2v z4oXEVQba@o4vI`!1-Bw97+fkcEQ%uF1}KAV-$T^-+0L(h|K#T6JKy>4J@}ISNof0tm;g2i)E9Yam&IG7+RAkzhPeB2_|i5YLkel@J#a!D5KX1Qbd+ zBuoNQ3PuExfl)MUhG#>w<{@`=TYue(=h(zjAG~CLn8oo&2KsD?0K^7Qjs1;D>u_b( z?Yx)cl*ctQ*LZYy9L{fXSV{L;*?0di{jkLjW9vNKlk!jO4RcMG8jN{#22>yF?CZ~N zu4*ueg`eIp%#6LSk-Bqx1ka8?jcWDG(f3=?aclJSt^8icOC>A5e-NAAqQ5d{@UUY) z<9U25JeUz?F#5FV04;2!c5ZOq4`E4XO#%dVIogK6`-@cWj!o4|$lcPk9bbFy8!^My zyO*xN^tpN*`YwF3EFyUhsCL!t?Gklec5$70jw#y!1}?l5(PSN@cVJab2LGk*tC%Y% zuiq%IdB6!19uawc8JN8pbE6FODs;JhjMA~rEoZNPJGrEJn7Zd{iyO=LxjLM`@Cy?g|+y5esHN6u`} z-?}H?Kk)eH60!S4lCoc>0)|-Ii{F++x3}(fWiVJ>gehFQx~j)OPWTeksI#my&BW zO5)bvNxQvkOjpIJ|H8+{|T3^|NT0zkqc6|{Z%lBLT_iVNC0B+aZ4UCaCvFZc`PROK0Ha!J776B{Iu|%*__a4{%jMc(xXCudPoH; zw?Yt{ zhpD5(!-Ko8s(ow*Bsv_sO06p|t1BjaTo>#vlsx&w@MFLg+` zYMy%NUh=+hjrnWF)bawa6aUzW*M_dkvO*0NwNdnwNMbO6*%lDq5*s`tVFCABp@g`BvXQJs4pX7NCB(lB1nNac90wvg+R(k zJmTpfJ`_q(B6&O*0TWTKU;wdfJO}xXSsc;YEZ(r){o>Oa=;lq3J~uv5i7t* z096|dM1u%}3Z?uY389_kAin3ArQisaLMfc^j_a-H|G}fW-WJ6N(*ZhK0w2r(7;hIe zfQBwU;8DOVoGny9=-yB{atS1NVZ&1KOx2k!1NabCoDw}%bT7mY6e#t_6h4r26Qq=g zgnyL;mGyr~{(=b7hkT@IVwDJzE6s;ld>f3G9*tCBgF4m?UAc>n4Tx zT@_f43ksPjPH`1WrC>NDN5C?W;z~jwER`}5LHI#3g(H(W+wc@Q6b}$UA`u|Ge?TgQ z;zj}E!Pyv*N<{7s`hc?cF$Q`iKZ;Sv$dr5(BNKj?OCS)DyZaH&js80vk^TpKv_Ggz zqapqLh>uD|dh{-)lnW(NNRIp~0`Vb|Gzi%*hzul*Oaao!U=Z&si-$q9smMh7a=}P< zI*G;bCek?G92$v5^d@mh1QL(Jp|Fto=du`N=AR>?(Q#EMg>vQ0A(M#6A=}$~2l9a5 E0P^I*t^fc4 diff --git a/lib/CPUs/MIPS/doc/memory_map.vsd b/lib/CPUs/MIPS/doc/memory_map.vsd deleted file mode 100644 index 720cf6a53c2ae71578f5d7de9d9165d1bcd851b9..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 36352 zcmeFZc~sQc+wZ$m10X74Mifmk2{@%F1Qmyr2#RBsAUGR9P;np#;?%Z5aR9XqPH5X| z5OE%&h&XppoCkt9D{T;QL=B*z&_eDm={~=A-S?h#&sq1cv(_zrirSD+sbuFFzRzb< zBG{DgKGFUq_`f{{03~RaTLH8G@_hupHrdaIH2^q#VH!8fvfT1b0N~62|M7p&8EAsX z8Uin#5}FE{8k*^vn?tjJ)(V;>wARqtKx+%l3K|LxP61#8%@&#+G<#?c&>W#TL2C!i z8CrX29iX{D>j;49yFgH#8q;U7&S^)(u*BXg#2r=G?!g zgJVBvJ)!wS3xL)OT5o85panwf3#}it{?G4_=E9kO03Xfkp5v{I5S8;f(qB02FXH+xDhs01AITgTXCdTAqzVlYb3eS&V2+ z!8j;A!RAJd-pCldGe$Lwr}6=3R1x|dD=8Ea^y(hNBjAK_U%nx!t^j*Nz+3G zhWz`+UyD!KvlPBdBAO-==27uIts}$i#RkijP`(yHu zmy1^r0MWa=sT&06k(Ck5G>cT;1e48I0A-3jB#hH-hNHpm~r6 z8RD)O;;uY2#9cMST|LCzY>2yg^$<-dR%u6f>I|CX(0%U9I~b6tt@ec;ib9Wz%0kxx ziYED-*M1pfDfWOViWM>#smKK%k!%_CL{@_w;Cc;sVckpct^+A^dqP}l%u zj)5M9fIen{$S%Wi!)3z*!<&&a$FEdQHx488&&VZM^Z3jkt*MR_ynA#m*W1p$A9aK% zr7EZOaHyO%rfXR9OhxldW%Kma<~?ZzSOIPVwT&s*cB-m2Uj~$V2k@8DT&n_ZM4~$w zYX&@mG@fk%x@a1Lydt+y1Ppu`4o}b#)5GG;k$G*gIG_$t%rZ_M<^Yf}N(Y59g;u=! zuIyu0s1bVgA$+D)Qpd+Lk5o+x-GVW|*1uo3mF>NCx}*uqFZuf}@YU>J^=I_Cn5ybk ze!jm2EGIRunSJD)z#buY$GLu^TQQ&m)14uh2~5_mGajdGQ!_M+Ns0N+ShAPNA!}1J z{WP1IeQQp~om_h}ec1TKo-7#5j$>!COW3V!Hk-$$GeE}$bCFyLBeL(-an4J-}i9A}{bS`7gYc z@SOX^fxf~>ffVKnX~HgHzi?Ji-4=vM&$mK@&|2&$;vyI(hKq4x5&KMhCDw_pIna?? zE&eVZ7B4<%>RnZB0aKn1Kt=%cm&u8gOw9&ha8g{{H)HT%h1ocxZy+d>5lxx=GgWGF zXaD2*KmP3xp!`^^o+#B+G%6&R8Ckshs!rWrq*Rp2-e@5D?(2T})pt1vjYq3$#s*H3 z|8daC@}%JS>GAWTXN$TX^OKWRtwt)G)Tt@(3LXX=dI>GRkA|V&(D`UO622(;?Yy`- zo0Y0ooe?#fI$WVpgJWno7KbUSYPk34daNzBR^8d&thKopqWD}LguTTYuuAkyM|=mi zN;xln&T2sZ>294kJ9=JRXM03~8J_B6^$+RvXm1gt z!fac`47UcK5!EiZiMqejb)eC>nvKI;%`7a+2OufR80>+Cvo(m(EXQn-gEmcwtC^+k z+4d@E>a$MHwicLut@TSV=2xfBNGqg^<=OVF&pM4@Fn`Z#BD8ydZ{xkz9xsuz?cx73 z4%Myf{_y%{36#mu-65)-wt?0uim1WJ`&#vfJXhsuH}yr0Iz<^=I~nF=YeCoZaZ*J*PYv(tMwV=lCHZI0y2C*oCoT3T`B08u6uSKbV}D%08Ah3dMsU6 z3);;Hc1zbao(JyfItAj9>4!wvFAR1{4epR0?3u1RZHsiy_Cvf5_#tz=kNY7$XZ(7A}Sg!F}5Uq-ro_d~jZLCC4@<-t9y2O-*Y-I`g5@4H|> z%^;*_y6$lf5>Or7D_xg|eCp#p2nqZioCZq6rWkKcF-{(RZi+E)iZSBQ6l2a5s1e2M1lI7~Q5A+fOmtPBErf zPBAK`7#l&_Y`sHTus&^)K5dMiG!`2pZWS9Z7aPwN8}s1cP_Z$m*tosexDgK46dRWp z8y6QFli*-xu`#CDIHA}W1_#56jX}l6z+$5g4!RT@-HMIvi;cF$#wN>RqY4&8&ybAJ zGp>VxTOZx`nh}UHbSNm*+_O|Z2Q$^dWs2thnlqDnY`y*3R?_S9#;rsw^?G?k=S??b zb*=Qz_4!OpEy2b%5M~ErD~Q?ny6NfeTjTQW3bW%b+Z~L{b33a!*Q1Fb||dDR)J11;#(kf zE1k4|bb#SZi}auE?i&HXxK**wVRlpjlk?{CM5Hn~UQwAi0Y}XA3UH~b+eHoXSJ#u8 z=Rmz#ds4F!@m-Fv(`9<7r!%8QnprBGiTmx3WpxYE7#k*kKeNrbbp=R5HfzDd=B88x z*?{C5y3TJwhfPG4hOn4v(S zTNRuK^h_8N%gkSMVaqiBA;V>WEZ&1Z$Ja1Q)`9h6`~1#?hYcJ#l%1HhE^|zXI)0;y z%CeffWT*PKZJ$)D;yN+w5tUv~pL{wy;E%iQ&h7HKd1vdQ6=xr2rKWi2Uj^yz7q8~q z+3zc|6|TB)J-FriL#d;^a1$W=xK@>G_wn#w~dKYzB4>3&nRisdcLqzXc&)y(Svk;BVS_58w=71kPoMhB*c$IRjseufr{O z;jL==gc5~|gtfv>p_#jVB=YdXnWwDG_4@PIi@$`w5UK^mBk&=@?*5ku*D?{wHQLbb z^FVYAPKS%viMY8n#BTAV2>KdE8V(z}lgTT-MB36d1`t4pOB3imWQL@nbLcj-<{JG< zs*}uR=LWyd@<163lPAdua;m&h&Xo(~8}g;l+Ngcx8S)m%-7c7*K3Ziot09$?1Jzh; z*aGyFr}#UuhT1_*IMyojjS5)jNW>lL1yxNc=&v-4;feGDZZrJ{mrCz#<>B}p3a{DlfVDGuGFbC(H*%Xtc0oUDzJ1 z>y-fVukK|}vp3o2>?gL=DgoB7s+3ZU^W_F{5!`fcJP&5^54ke2fdkTO&O;i=gAV)$ zaklhG%#>32)%@?gVsJ*!GyHwNjQ`97!B(*L5CViyVS*64*_bFS7k+FO$|kNb{K2xj^v%~`;I49l_|CCCk zcaCmm1F?PsLMwklr2To%lZd41NnQ!$0F^ z0AWjb5TT%TAFXm&f1P4bfU??X?5~XOU8kMnfA-JIwtD@kNaIFF{o9_cRt{*`+6#Oe zo8RkM+>fGHahCT###Q)%X8|>Y(%>-EC#bWbcks@r3wF7=Not_ADM;Gj1xx59k^7^O zGrCjr-!~f#F$2MLy#=yzN_?;qhLU+9<9;>h8N)Ji6Y2Ny5!ex>?xnSS1d#aUNY(US zj5pc)9r&2AmYG2YjX%!}Wkkk5V@~UH+9afx7Bu^3)*yX06xEzJn&Lvllk>*x^TruP z;{t`qrmim*n!K$hTAm#rooosUGK>m8g8~PmLhzc+KC=qjRPUmWQxI5m(8r{XBp0xE+F?Obv|I49f@68qAoxM;Py;}-#_MJMt6fYIt8 zaf~=kTquGyVvkX+K~S)*?FF$|EEhqosFLa>3pq(zgk?!PF|b^^guRf?NUO0{crw-< zueOyv2nH+?7#6KDm$R~!4bg;(3$8I2^WY8Ld3}X!2jy;Szl3SJpRvES#4jC>OiVcNi zDft)!gP16CIx~V?%N!t=lcO1MpXtwhW6H?SB%qFVU9kythUa@2HHk`~QmKtpF14b7 zYHqZ7M7^ULslV>*RvNtvw63%t9YT+#Q}=?obQ-;d-cO&Ucf1J9KK=j<%&VfCXq0hf z{1{KR7YlYX2l%VZ9sUGU4JX-K1{CnUg&cm8Fpv#rp6|lEo8kV@P z=6>f6bKv5!O7$b|9Y;!YrB3{`QD7HX9K6@o$j9*WcqiFM2CL;(sF~0P7i2B&D2%~@ z6FNd@kMF?E@Iri_a7F;P1l#x(o7b?GqMhg|_7by)iW9{-A}wB@WzPb|gIw{HmEyX^ zN9x$}OGK2mT^mQeN99285|2u?^?84rkFHm(Q`+!RDV9;H%3Q6vn9?>XrS)&Y%G3;- z(8^_R9G6&c4o(kFozS)1X0@wjRJvZt3{;!l7>I1uZ`R)rHr)s18CdB8rCyxZHB7Dj zg||Ou5;6Izw#}F9%wpPt=B2W%7o~51H!YPBB6P^-M?*t|S7hXkJwrn*`%22KV;v*4 zUBe2)yM)`AT{LzHzcv}^8ul^#&e$bA!)qr1uoJj7mUjh+{OXxm{pRxyRrUz-1$&Ku z>v1z@*_+XZ6?kd#oVAm*UHp}ItwX_X2Npen7NN)7H4AgT%7otG=M64*((7UUA9KQP z+>fso?UFy5VeOpFQoxNpXiA`6yOdBEy=G%eG2loJIDRuKIKLz*A0|*wFz^8zN--25 zW_E5jzZbI}2NRjaIL$o5kK-ZCb;g$|sbVY%7otah$BKnvA#!-g7)@lzpfTo#u)r|{ zMJy!N5IYFXF`|$tB`S%H&m3=2Wz^Tt)YG){^E{#7D_Z+9(V(x4j;J?F-6H{Cx}9^v z-fnga_6FLe?oEdI3%!*-NS~+ol>25Mtn8f!M7oAnG7gLv(>ibrUFJe=;$5kC+>@>_X{1@j_Zm8i@WVt(^W6hQvu)kiR*4hL;sn{@R z;>t^y&Eq%CL?@ zUFR?ND*=CSAq(^&Jf{H50-kegB$>0}^Q60pep=9DOkmIuemp;m|CK+9H{f8Cuw~Wq zfZYaH;i{pn@ZJF8g+T&m@Fo8+M36fLPFOsCr`?E9?ZV#LiqXp6+G?mY+KZjV-r_LP zdXktRrivbi+V>;|6XS^HLE&ReYFb#$1oP^CW%n@sgIL764tOO#oVJq)S@1AU_f?FI zaR+bXO!6~gurqiX?j~-F0{7>!Nka`2VV+MLHW<=Ku!Y>R>g_Z$#+~fKe4aj-0aMBT zOVIUgKJG%1+R7+X{Q=6* z&nUobF%K*NTMG01E2-EzT49!btFlL)T1&&8hRGWo?9kNqd~%C7u#stz7(76@&#JE{K+Yk9|@E&>E25pD?F9B_Fv`?#tooPk;M?rKA zH;o1hX=gsn`cC1k%KN3q=t3Hl(v|cGVWZH<$b&mP3Y0)PGettlh^X#euDtY2aH)G*LlSd! z5=`WK%+iPFG)SxAyKPUPH z`-1+#y=_$$;@A7&Z?Ua}Nj9>(tnincX>%64AQfS&%|#6SkRH89@e`OIz7rdZ_mjVl zlDqxhb6C5f3CZ*1q?D=i;;96U96fbvTynA|UQW=YB*!Je)D$M7v*MBx;^^6$IaF+% zX1ScXQ{E?^kv~5$)7U(!4;>CV-7QqM=3W&mCs;JK>wE0aaVGIpYJ{a}s2i+ITcy^- z75F{9=)c=MH8;-!jC*+0f6vJR|M~ZMe^Yq?+O~JI#jtJjrfYNNB?Jw@G~*pYkPyU7 zksh^brggM~lM-0?TpKqZ7RZb7#C7j4&j32t!WwdT(&WW70vvfc|7O z{^sI~BP<3GMj}S1@uNbhu~gYB`P^R#r=Nea*30_$^8%rw?J4W^u;PR9 z$;M%|x>%dHNxj-Um)f;8YQp`4TZ*UVZ7GX?O8Deyre^vcucCUM(B!C_D3k`S^xvb0 z)89mjUPf=CS2AELGbKDP>mKLE)NyCG+VCKT>BkJ=-*ZV!Tb|($FkjCxx81##92hy& z7%q2DUX-kv6E{buk``%9^?dU|q1!AQbc6HHi zFQw1T!k4ahh52laQ1%KsBpG@n8@+zTCE1i#yn%5REVJT^wxNeCk6xW{zu;=|RKQ;? zqdrq1+*r`yJT)^BX7x2nQ# z?9+a(YqC??$Ss*rjDiN{KU1Mt)huP|k0NFMn`XyRB}-zS(B{%fpsYBv4L6 z%vji{O@N)lLnuayDg^|(Db_1~qAo*`9YmiqPZ5^BcODcq!FPo-O zcd-j}tn<^TEsH5-l9OXdwZirfJH*b$Y@0P=x4R>vu)S`#-|0tdySuO#O#~z+82io3ig`|ePlUfqex&)T{0MIYQj#B`2r($l z7HqT0iouh&Og(A~wDc7?n3&vm0XsE%@i_yyV|ZbxhBAXa*_kY+hmk>(NKcA1)$`B0 zEr$ZW*?ICVDUvO^krxH}P{XOo6h$qgI%fAyUHkwB?Hl0x4O# z5~Y5N zQQ~GXNn9azLl21OMDI0sOVsyDRgWL#+f@FgZmfHv>UApJq;JbE3cbE`M$h*0Z-YI4 zrrZ<^eLvcS+$1Vh-9NSoIZF(9ojT-I`sKp=>f4*j)O(6vtHX!hBrHx!SEW6d%q$#X z68A0(RCd3z(^mbuY?-MYa9ZE2YRVSD#~Otb6q>)*8GGgbRcNlz*ePsKchui979h9Y z4nRPqxeA|cuE8tOU_7#W5|Y~JG!J*gx8VxdbPQ+(wfrAoEx6*KUANdlJLcjeGsqsK zUux8yX!rI>WPH-R6ghgfCOS4YDUL}_1~Xrk=uQlHOMIL}^j2&AQcWbmy9EK(_2+EO z#+NsPEdxGPLme8#-?nKgsSAGp$Ud|JvI;u-rx3lq=oihD^EM#H9_+bfelws)I@F?( zJzC$ts}K0D?Bk#6vlTsvo=0D}A6GxNed+QH{fIWB*3SJyfGM2{#U@~;iX>wu(1Y$* z%)^dge_|zA1@;wtgM;sQ44y!)!Z(shcmY|Ag9G>yvYDJgx={+kp6J}a$@%RQQ{p4?H+C>4U96~em9Bd#3urDK@8tb`J(dUPr(;EWd#Lam)GM4pGyXQ z}yS8)^-cGiN1szXFn$JCfdHAUT4ZLK>+U3fzf2H~%S9 zO*TOp!j>7`lYO9b33zgDjP zn!*3UpXcwM_Af8Xwx3)JqeMdO1|kG3GFP~lE*m(fzM0N%a$fY#l(9UnLOL#byYkDH z`V{3auXhYOP`6_7$>Ms)^peT7^+EZ3D~MAvF*X0v}lbvV_mWSSou@2 zN^BBQ$yEvkJ*p>R30Nv-e!--L6W;bFE&OmNG#p&U9$@wJ%_6?pp%H4_2?suSUwkA! zp}J6?vf_H!TpXm~Tk!q(S^O|@k?;yYBS8;pI1xtmBIZ+@h&e<*D)mpwo2sC$6HkdM zqNz_W(4O-&^f2fRVTM@4d_%gyWxL^sAr#;NQm8aRQkY*@a%09dQx9K5^^$g z`Ar>6y+Cu=4BW;a;xF(oI@P}hZ}|qkwa`((h0#5Zm&bX4)3wn;vanLvDjXF45RZz$ zN$iC76@ySOaT=N?P8LBo^cdO>Ek#d@H^t{-Qy-)cMLS5HB&`%Ajgh8Fy%$Prq#f|G z>pC;N8Pzc6+lY~?x6ET!G23AI1uihfOgU4_sMsXgo6VIGg@fkSnEtv+Yyz9QV`69h zwycSs2ieiaiJsS3<w=YZNH3E!=)C z#c-SZi<7u_hTgwnEOr751%4-_BB{+oY0|paN%LLTWy-MN0`79jg=G;VST1jt zLBCynjmFJEG1ufL@&_4`DWqYq!4_MB9;C9-yVN=q)KKrx%jjvU550$)OuJwfJup4? z>FK~mvD(mJXiXM&B+p{EvA-}0L-0`WvS&YX6d6U1=msOFIh2C7WUe81kjKc93*gPl z$K-qRZ?Y|gQ3H#!Q$fU){ToM9Q>hecHT65SmIga%bJ~jQO6xc$I+BAz(MZ|__9rd4 z%bZEXy-izvdI~l0Xv~~3wZ8N{nZe9BW+tpcao}9f^%>ezm&r+}G}v zuifuEewi5%jU90syflg7t z-e8}xA6bL6MN;r!_P)jSzoVJlMRW=G5`DsfJZ?YggKa`bVr}?Nyp~r4ogeg(u8^vv zCJB`f^Va_&V7Km6K{!!95Zl9?9Z2>5{*D1kSmuR%rf>ILgg7+~dFvLylo9=gg;Z z{rMjTD-vkPyUx$;MC>8+f~jT{tY#N^oV-jvAeVIuG<8{j=-HSbkmZ7cIO1;Vw60^1 zHD9}GYP14Vr&VTMtx^m9RjW&VIndH+UBsCLwzu485wzxQrEgq-6wY_&e~3#Z@J`H; zOr6%l{9R{aOb7|8_^)lpd!c0Z0Sr9dbnnrRcFyk@T=3wxovIt*|o8| zk+dHZ=YqDjrFMBvj&@Jlw`MvrI0MSXQYnsEz=Ys`Fh?1l0cY^ZG9@pQ6+hQcw1GTx zUC;NmiZ9gwB5E>Z)HHfXsEJT1^3qpTw*o1aZ@=1CRksG6oI%@mU#cNht9@UK07$F5 z%RiwuxC3pHWq$6E(&l~b&&^#N;O2GJZlGz>%SJU!9fN@E@}UDV8!nZ23BhR>RQ%Cg zll#3xYh;Hxz`Fro?=n~;zOVHF&Msw;Fl_hFo*||^=Y8*he1Uu3vuxQ@FIRtbadJVL z%z;HW@ZVWINdCz`#Y#y2(I)f{l7Ih|)l>Xr^%VcIdcV#XV#2p~KrUMT2i4Qa|Dbv? z@;|8F!f*egdMk;4QN2iX^Ck369Rex6pFTqbX zucNxV6ELxPp^(i>v#>C+d0{PVUh5bQWb=Oihs_&yu)XSFd-cHh)_VQJ<}E-}wq07-yh9Mq%W+li zcT*qLsO?geCrxbLq|O>gXX`qPj`onxgLob%Lq1P1;dumHKd@F2_Z%X39b1sQsVWcO zJ(^N?ovO9Ao1fZUXA35qxtriScb(g2>mDAyT|g^$oetM}_%49(ox3gwv~kyMh2)*P ziM;dhop2tY?z$LY?XH`78`!w(l7_%-7lX-m?z-i`-d(rmQ}t&L-;Kc09pZORpWSsi zpq;z!5O7X%*X0@Dw&y?xcin=^z{Op63v`4pOF<`h-7|o>>&{ldn#K16aCO(!mW_qm zHUf8dh~mxh=<0`f4)Q}f4~Mv&SGXVIJrVME1ylWyF0&wGmkf!#Zol{;-P8P#9&1fR z-X=dp`-dOmTd)VBd58TFzmss2p6C4#{~|vm;5OW(*L^>v_j5m_Pr)lcB(Ta4>HEbG z*$Vl)2K}uD{r7?A4mIfW8uaivr$N6Re%aWdU(=vp-k@I$2T2Y3nGO1w2K@v$2y4&} zYtRQZ=mX(E*P!pxpm%G~w}%7U2EAp2UeTa$JPgvj^l6wr%}Jkj0M$3@iH@5!}Z?ug!TE?63I|}l5p$A;YD938kL*c>+2;jBVUN-S}5Xbxp;C0u$t6MCa zWK6w2e_ZoV0MEqVeS-j=Hp(PtoqkroAIx9cITFEUVTiTfgVk`Qg+^zF2zI-gcI2U4HuRPbBCvdjgYm?Lx$lkVKQ zU?@cKaL8M1OGO%YEJNHOiU&!&u@J@MQnR_#8NAjBqIj*fW|ZDU;x&1^`aUKpIw5(s z4B6yZOUPZ&uoa6(BuxFdJZPq`;u9&8HdGh)_g&)XpIU{BZJ!y)g^+~EO_QkEu6?&G zbPwL5NT-w$S*8Zm4eA;7F%~qZ*2k)I6tq3vneI&wqf;l*33MvGiiu(rjMi5H?#_Ra z^G_1JCUOhlK_W9OL(Bikjp5fZyO`sQ#bxFJ^JZ=Lsx)_P=S+lsV8?oH*Sf}i=n|I^ z>|i3$`phT{NtjWTz-nf@j=Z|iJ@V>yRyqAz0Sj8PoR6`cH+-AwRBF#zcjkI?!w$|o zsGOc{!qKdEaX+}F{N)A8yYtIRA*HV6cr0 zg@KS+H;FD&zg7&7JG<;!YMggi9a!i-u`bsxwl2?ZPTdXRnXvrht<*;0-3*87`dAl* zdZEx}%G1O>COUB8L&UgD+$8Q5lO=~wvGr*v&`bN#S>KA#RB2eo7jz4n=!7jp`(h_e zbRb_IafL5m$Cr;0-u3*epub%Y3zKkg#g5g6mSsC>mtQ9yVP_rv8f~vbRpzW?&qu>@ z%wp;k7s|KT*O)Y!cf*j5(ONV6X>L%Gkz3fn^+lT-!Q?&mE8WZob(U)sZDY?Qh+P-CEtp$63&Mq*xAJ+aVGL1=aumSLN)z1V4It@oJQ7>}ACII{p-gY-|tDI1?%YT3C^q-Wa|cEXmW(J$*R>tz%WN7!qm*f{xP33iM390t>Jx&Kq2Qy9%rp8g(^=r2LGIhqO3<~@~9i@2c z9_0*zGcnch98gD@)6R5Px<8FG1DV6~!KSP{PM{xg=jleyiK(GMAs56S;imB>Rg_{* zJ0rcWU|I-T2{q5 za=@EwZFR5^Qynjzz|H2Cav+n-;WqR8cx&EC>dE(&fQBcfC440BDeaeRq}!5p%S?ZB zw)c9*N^lZVeT4rk@7N-Q9tN!r6)KNiR^(q(K8UWqbXQq=L(6%-uakdvi1hk`$V+aH z`f(3h)fYEdJO(qqc|IPlo-=if`j@Gb)#3NS@JBJ?JaN_2?WJ4AgAc60g%v#=Y)$Ud z%l0RD_UTPK1o0{D?06<%!xiySDMV17J@|>BynZ+iX0B4Ll&F$(mlTw=h3g$G|FVYt zu4lH$B=ZB<@6y4AV6xQ@?5T9}eK-6ZX2kb7&uQIDlZ5kxb`r3 z(ycnXTlI{d-vb-<^&JiEA`-ffNs>+e&*c7SlmCP6ugv(;@{n)=3Ss4U@}JH|O^k27 zU?H{_yS)Iz{X@jDVli5d{w6+5P;0^a*fv4Dcn>afS%q!G>M^hoPmz)h1MsbemC|{` zDjb}bmO*NCj=_s`kiFzSvf|CzK417`d5OGU&X)6J>nrjj`JLP-hwjx_qi*Prp6KA# zuOQ~uiBWf$XmMn^)#a&6(Mrvi{bBZtN6L3h3O_5-Y{^SERavg4`ksF(u&ehIx3io zq+mVYHjZ7uX0ZMGRV4OCO-S1bwupVmrVjw!wIT=-GXv(S&60mrCyOh^ts*!mo)=r`djK@p z-&PcBM4*%$BrnNX?kdk;^{d$q44jn;vAt3yhRDyQLs&Olp9QC)zdS@9FVFgWkb?lW z$h+j@@@4sf{6_vRTcVd;P!vZ^#c^C4a}@@8HjS&J=q<7+IAQhFKTiCY6Np+0HfiV0 z+aAt}TH-@VFb&t^C@fF^Hk=|&mlphq&-y!PY9%h?7DRj4 zS=IdPtisat!Y%8~#6IH386vKY37)lF2}I&27-|@hf*S@J!VMtKu)r|k*!QS}Tsi5W z;k*HuG>96*E3ytwt!WIzBGxbzd5pPD?j`3j^)Rl3_N*yWaHq^}zHqO=p{_lP`juj+ z-PB3yD)pE;cPGN8Axha4qfpLQ9?$$>{j1V-p?0eJ{r||%FzZhi&$Mp({qrEx*8NQJ z+6E#&w<3Q2uuWiL^7g%B@9){WIr+%moa9q`!B4Dz@%yAV^vws8v+qB65u0anC-d_* z5Ox6Rmo>#l7onBF3Uy~&7py8wLb?@#=DI@UN5iFeF+bf2#8`jH z%>E^FM%uPOCacL~*O~w4RH}RE{mWf}Z3ESs?nuYA`Il%j5rpwHywc)3XWRgPunvml)< z@d=6zrEdH~5Nb>WVOOp{x3aIDiH!N0D&F!d&n+3iej{YPV+*|r8|gpcu5qn?oOpuT zeJm0mK5bI3N(N>Q-|nLhYRO6Rk@`v_C9qXr2zCZvx1B4cLFs6}1n2r;`J(Jqk2?0i zhs$9&=q1m`H_3D4e$b_O;}!V3>oSyqnjD|D3kwOC|AD&<%CJBiv>WP=4nfDGvry|_ zQ3lxk`qF{ z-Cqy_W@1aQ^;kBRhy6(O*25*Oc-SNC9oC4o!8_sBgc||8>K6>oB9G(e$Q}3#@;eSn z@m#Vql}QexOj1o%(?yqo<4lxSlAnh5ZlSyunwqUUh=0+udcwk>FdTO9F_D&VZ$$eRqWGryfzt!&aM~h{UO=C;bZmjx_HB~w z8Myv#;a5V^FYec=&v6W{BWh{1AbQoO1;b9(G}G1@y-&TrKkyXLr42jv&jJ@FogvG? z-`R1MipxisKbaDyg89mTH|%#dCTmzhys(P>O&EO|92Bm>wW1>QjgQ#9f|qFBhU>&Z z*m{odYbuUQ;8Ih$ja)8Qz}?`UaVOe1RsZ0ucn#nB{-)cnlfImt^fYl`0Yr&@b054X zrr>MhnO85T^41xueXlck#pySD`P2MO{y7gm@mH+l%Wv5y*4hZ}g1-QU2;+s}Q1_0> zI`ihSTqS_N)b`5Vm+Pw{RoyjJ0qh4*H4usP?r_2^SBw zhbMCLndF?>+Vk5hdrw_jM^9k)rL(82>?eoFV`c9##nwPK=Aj!cZ;0zxs#t&R|*h!Th?e1usw*(c?n}0lt^X_(q-%v>Q4ehZRRx z1?<2}>;SU#;|_WC<+{*deAXh_46IruT&p4zzamMJ?SUJTDChIOpk_KS#_`> z(x9}<8T!A=b75F!AT|h#z;3QE%UYJ~2!-|ze;FhLLfTEbJPtEyhK)XCUsx9aa*F$@ zh2$Ctk}qNk$(ldGU)ky_m3bE#VWrhn+t~5tsV-Cx>KoI_)Ia6Y<2ry1(>7dYsWI#{ z_91ndy)1y%^c!KGP|1eVrW-wj4*Fw}iwTpsLoZUgxQ7{F5ARQpQ_f#nH7!&)e`!FO zSMOgx{Pybe!hJt10^8&D_8M_7nqk!f59Leg$rQB?E&8&Im&fH zpq$1|kwJg)Eb9SjHEa2nY{z+W6%B3iP;SDJq=S&WTDE8@WUF(yeC`_eB&XxBgC**t zrK*!+(L41$Q3m=ICPcwSg4FrC_F<4&LL9y=^|piYX^o?Ue;VchX1aSjgh{c|d?{Vp zE|qG)Q}D#2+}52Kzvj3l zr7+M;VKEwctbd@l8)N$03Rkeiy>AEU-;9|Bac-L>VTKKGHBHBWkpq#*dCk8>HtUTh zeYa~EvO4rgQl91NA)CTe_eA=qWrQp`SrCzCR~G4LeM~zmOf_|8xET^PGu(2{C1h5Z zcB=LCdEo&w0bqZ&r@L!Ci(c4vySCZezq1F@1J@9`0h)m2e8C0-kDs2iHeVa(-%+V4 zgcP6YHke^h*k8cjJltr=H53?b7@iqYKN^}1)}$NRlN?NrgZV0FJDZqBX>;- zpI;EE2~W9BN>Sk{m85d-Y9t!?FE38(ndTTHFx{j5mp7(?XR8OKf$ig|mhA2!r7@*< zbJ+LP-;~CR*3kAk+Wx}GHMY(ZXcLwIGT{QYeEJ&wg#JMPpsg67VO}18ocT6i&Ix8B znO&1oJMJrp?6`LWb2hW%-eZgsP^Xb-IcM9+<~@!vzw_Orft+*YWbSE;lef;fvnDt@ zbv(;LQh{N62`AaBtgG<}`+@zzS{;el8|Lc40aLlqQu>-I-+T_hdCh&`eq`@1%&WXv zYQ@6>c-N%2*9s!vUY*FN6~4WySja2;yhWmKmd3ogao;fpOqIIB!TMJTZ%glQ{_u$h zGH;4l@q#H}A@Z+64kNhb2>HUbJ0IH|OH(Wha{Md+(N^>j1H@1fOb};_OT|nvN6Z(0 zWY4Pp@ydRa0+Rj^?Hvo*-j~nY*7>&$(1SZ;kAEwOJW=NQ`1Qi=eJWAN8mg>c#w7rT|QQSVPS7}x6l1indCgPDw!fX;Gip>4}cC1HB>-M@X zKL7cA&hE^anKQrNoZor<&i8zW@}s&^{U|bmnn2B_ZmkXRT`nIUTFj9OZq3LH|DACe zZ7V5v-;B0WM_TrEH_7PXp*5X`b%NJW%XWl=mc1IfC3f-~u!|=KdL3N=X2i2 z+$o3fp`WmhKZb=5Eo5be6h5R);_f8UI!PY!51n^-o5b@;2U9vEk&3@&(!(|5HJO?N znsu52jbpt2q~?;QEl!xlF)o`WxqrVlK#OzySz2s5!f*xEDQ%UuL95b9_ob2L@=Mv{ z*qLnT=gN7f9F%iauj}4RQ_g)yCmX(k54n_0vX}joBag^2dWT=i-nwkb3R07^26ayY)Rw{hay;~Nu=5?LDNioeZoejWMwA)PF0ry2;QUDI~v6#-9YE23=X>M+3{*zfmA>^3f zHfPOmH1ybVd1e_pFY`Lhsx)&EL%dcNZ;JcK0IO45D*n0iLQ9L39KP7Y5_{Y^EVFFZ zIeA2L0ffjbi>Pf~H}71(pVwImEaXeeNlOdvrlkq@i4el|;+h7=9aD@blqY=OIDF!d zMT*(Q^094yT2&|maPD`2UIXx2ZCKck_kAYO;!AZJzSJ^>^s-} zWTc{@Hd)c(z$8U8_Y6f(UOt#_sCHQDkiZY_PLq+HYy905lS-Uy3);`bCgc*1Os$rZ z#@9*awIO5uoWt^KR@JE96*dcdeg-62O!?vJiAu7VzE<~ldLs2L&9%5$ozr~pZ9pls zViwW88S{-rL~BE^t?|uUdSd0pfn%gG32#pW_}T~HD~)yid~M|9?>!oh7b1QQ;A@t1-IpAY z`$ml>iQjmThH7PWS66_q{aF$-I@cN!qOK2X=S$Tiz&fQ(DK6iW&2N!JO{L~jD;pi^ zvV|gM>Ns_dx<)DKl7(*s`;Q^{5nbrM^l*ASok{DMISi?!>ogSOt-VRJ+IS{}$x>+N zYpXRMX%{g7sqW}CJM9jD?HJ=*#>DBsr_+6NFNf*jLF~3L7F{~i0KgV^OqM^QaN_YK z?uVf=sHcjDN-uA3g_YGIu9&OfZgIqg_vJ(R{+c-cbxj-9)dW(N>yw?wui>{<^_ce6 z#U4{tKkyRLW9oHYmN(zM+9#WQlH;8dShLf>!ok^`ee+4%obrX^g-pR9T+*D@ekrI< z3bDqULX#$c-R(D6_pPz}WL>Uqd1^n>9zCR;z4Un{nN6%GD~|^E(i3qh=OR58yM6la z^o|$wxQ0{u(%PLnBDS|TkXH=bsuJG+>SDsi>4vrW2^*zv8)VyexmQPQKV1-B5LiP> z%q$!z50vj3SkUAM6hoXr4>Qg);*fc!_N)YTOV%-jyicIAu)eTc)Gmg@wVaKx0k1Hd8HYb_4Rn7bUtBdoB)|e0NmCq~s z%q%M|cds5-CaFz1M*?f40t*KnYn#-)cCORUB-j#RiM5Ocu);#iD$80SYp)HABlj^!U~tZrb2qrgd<&l8!+8?JFAf_^mPIac%i!PO zHF;T^9TxB0tT@P5SvM=r^1wXVyy5H;w}3W_-4AC6GH2$HC2lcoIt8q7AO3QjFiw~$ zkUXK#=8!tXhz_YVH5){QQPC8D%2KGGW>AZ$_OnW7Z-b5#5T1NVouuxqVkX#CPN8Se zURim;bncD_vYIy0n!LiUi+2`wsi570<%M08jLa{-;p~oxK`{lr$l>h4+B0)@M9hd8 z9{)uz{RlFPS;DMkwlnq2_smaBl{U+nZOI0+T3swVmYvSR+h7*6M)qU2{j7O+zy~%M z8cQfmD@`X&Z%w==Rr9)Lv4$8mURm1{=-gA24`_-s@HXnlF5X$6tkQN*s88+)%c%y; zZ#a8ua(d1W>4&qY7~pN3nrzI`&p(&Gap8LH4(%Z=Db}{sp=Z*~D0(K3%{9){<>}Vw z`t8n_00+dbMEMtEuYP=FqT=+pYjVxjtxLA!^v+AtsZsL_zh?b6c%=ou*Z3c--_)#* z>D{w4i(XwuT5gQV3E0@QP4LE*`j7OlE}i2r;QcT3IiAJ&y?1cy6}P^ba9}MGcQlae z8TlM3oMU5zI5l_3)DwO4FK6G##zBPK``rQgl5H7&OZ`9SV~$=y63zbLSbgVnU@jxxwtS5@vu1O!Xa%-Kyp-%R5Q z%Q_=;oz|o_`S@JIwa9>J9zm1u$KZakZB)@d#NfWVR4M&_$&qz{!5vOY=j4W{_a~8% zAB>g8+s4(-yGKa2>?mzW2r#Kl15JO~tS=%{O!G|dm^PU{H^pC39~*z3gq2+}5wjc6 zYjiaST6$Q>2J;8}SLSc{9cG?aSt`ur6TX|Uj(=5%w8UA)S!P;Dp5?l*&9dKe!gA44 zZ*k&seYl|F&>mbAH;OyZb0HgPgICVu-r>k5?$xcOihD(ayf^q=vMX|(n}#3Fr}J~c zcg5q9eTCr2v=cfoO$9Q9c?}k-+TqO`1+q){S~x9S7UEeOESmBay;GS~P;sZfQCp~6 zW-6`3#&;z03{RS&~PuQQZvwaf&p08;#&gn7OK_E0|l% zSpNZiQnd>ivRFHf`B+;B{@D!e4Q-N^w7?n~yzV{0eXv_Mna#>&m$M(TpRz~UGi*?C zXX`E2MdPbUE5Z35*=IlY)rfte^;1`92zqAGG5gQ0Bh$(@BxMszbKe_nS_bE}DWuqhKOJyVnanO(fLZqUD4Oe=+OKbIi-k8_guYrGM!LkB&7b&6mtK z%}p$XwzzU_xW$&YgpVz|h1C||54&Oc&az(cqm~H$sE!1KO}dNf)LsGn^UEWHJd^*08a;q%L|L zQ^0%)!{+Dy4Oi6-bO=^ zt68p5eW>|VgDXPR)i5>HRNGL$*|ww}uzbaI1wC3Dx#w?l0~o}g5d@&^+A}okn;j$H zbkKR~$jdr(#)Rpk_3`WhW2ugm8;|N5n*#Mx{c&TA=?f#tFo`q%NgS&&>%Y=xozhq7 z!9@v>%Fc%7RXwa?hdE#*PC&?<=8BNUlLqo-wSnB>;4%6%e7Y_8>c0JCylu3HRTk3K zwSp;5uD2UWPvJF8w=>OZ<>?9O6%=N z8c@ML5=BrsQ2AC`8>(a1H=HIx-N^N}71h8UR|>qTxRkyenDa`6@~aYvb67_F2a=<|?!IUe$LSsQvhuL9qjT-4jS39;joJrv?up zkyl;|){bKRPvN5$&+1HhDIl+ z7(!sWzx&N?Ao-Bd5)v;Yr*g@@QK^%J)MOH!EFs~r6b_cG%uJpnOhFpcDWuo!8BPja zV)7*43C7e(MgdA|^=4H1JeON%DZH z6Vr&$3CNX@EkuCjfna^Ufr7X?aA>=9GGnGJ-w9m4Mi~RFwYr%SU_MNg7zr6P8c3pH z1&*0?0TsKQCF(tANk|${F<&O?moJlkMI>eh2|o^;&^KdKotkz6Qie_+k(azw0D^P# zQn_sMQaO348~}3UrD`w%gY(a7)pfP1W|LZVMXjn(t1hZlWpHpttvaPveXmv(!oe}M zYNuLNpjN#L2Mg7z`D)c`YE>c}3{tCDwd!THsu`r?pjH6~CTT5^-0pd)MhWn`hk_{U z0A6{`DhJzs&7sy>QSB^gOafa0p0WuECW;AXe|9JlTqs{El)7+TKxAb}S04#|HV!zY zdlJC~pqUCt8i*jBfy3~p9tOEYDK8P+!2|_~(9%Y!lR{x%bTzdAnHhm+@DNo&m0wjk z)=Za7Wov)MLu;$RQOPZgrb84@W z=~Yg3*3}L=m4Y<7X5G`Yabij{_c`==y2``pK5XYNrAKsUq#C5R#6wB#N#-0y6sYK5 z;coT0j+D2<9IS#M%<2Qh#YU_sa8(-S_!!= z6KWa(7b}t0mk2H3p1@vd{RRrE8RxDVKV+`@$65!Va3f|`BSBvt1X*0+1ErZ;X=nKin_q-*mph}rq3DDRG zvOyc)QsT;6TUAW4M`xqe!Bx;zi)w7&Xrc*@~i7608gT1Kj2HJ&>rpnZx@ML z(_7+~O|Ffow0f75-D`YE(d=yE$y-CqiF2SHC~kq8ZXj>H&1Mki7CsX1_@6!8kCc$SiNeEBr=1{dR_H{-XrsyUF2xj2698My4|hP`U)9BI?toLCBef~$f5qUH>7h0 zGsXg9V_vrNzc+v(VEF&-#eM?~&>qNb7Vx0up-o7OzAai6J}0JNnr2(V@KgCG1(zz_&PnoUMRz%<7}!0!l5fq>rn0{^YqWoB9vhEz?K0K0WW}${?|MM;q;&XuWPU%& z4lo|SO)=4y$6DYvAbL_n9gn_~HYjiV+J-%OyxzXGg&kBL&$->%$K1ivsDfbMykG~fgSJ`%nQr@< zhplMAJ`noDulThNyawZ;Q)GK{BO%KJA>kuX{Odi$+)Y&0cpP-W5agDq#8Bg5mjiM? zD-iCrr(=(Iye}SQ{a@>p1eu6Bbq3u)W`cU4J_lV=sYE4)AUC`0&x%e^06@}5=TlS2 zE7a*C7?7w_X`_QK7`&B;|kr&J2_=%C96=R_rjRO)%t=@jG- z>a+=T6Ls3)jQU_+VIHAg&znwIhoVlczy?K~yp?Eo2VLUiiAoIK%Kua+2b=YaKlZf# zTlF3VO0ctb0Yh#dhRH*Bko=s5jQn zqTXVk;E(A2H0mt7T#853s~B&;=27K)C6w>vzZXv3P3M>8 z+kOqkL-laCPy0B1Yn18!&7KyeSp{QV zv`ZZGiuqIHasN2?-?7W*sXSso9`zmx|DxVv|J`nLFQVRipzgK%fb4qXxMhKBocu-C z8~X+5`?B{7aLl&A_1;+RMa^$)cTjJ8yMtrz1+Mq}BQL7n*#AYn?fqZ$J1lU$=WlpX z^~UiI>TMtIpbu$*>pkDmi>fz{Z&7di_!fPf3taE{HeXb|vHeE9?d>=Es~5Q5^Hcwp z-q0KnxZSp)4;}Zh4{SBgEr% zfDONM{*Ou~yHB!Td&eJ?MfL=qE&4mebnk!muf5n$@7cfhHb1>*|Jp13^q&1|@9pD0 z+dc{tuYcT9a4)|f=4E~I&wjYAq4)Eb-q6Q=_T!iS2cP}$^u;oMuND!@dRv+Fu7}cI z>(~lE{D|p1>2fH)ldiqadGPq*@`;|rXGb29wzbm zk1j7y@BNFOpGV1Ke^2=T@4f#AJvL%G_Hz8ceE*^+t`_$YZ0;q|<3aeymJhoA$r*(5R+{wI@( vfH#|Bi<|VjYPANRFZ3qvZohj2T!14~oPByy+ueu5&XY>>-%00re*V7z1f5?D diff --git a/lib/CPUs/MIPS/doc/mips_biu.pdf b/lib/CPUs/MIPS/doc/mips_biu.pdf deleted file mode 100644 index 74f2564f18ffe9760f684ece239687a729f5ab90..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 7079 zcmahu2{@Ep+wE$QEo*2{cAnXcZIFGJec#7m#0;}oqiipw5UC_fh|0cXi9+@*LPWNT zD6&+ji2oVY_x8Tue_h`**KI!W?WE?-pjp>K(vg9%=2J6k@b~hl%s5XJnmAWBSLHKYt!WsH^;Yq zsuR>#&rCY9lr8>M(!n^|eu2Oh4%J>Rf#(UW(zi)JyDPU|n!hYIFS%N9wMA_j6OaB3 zcxBt}-)yH^6^;1scrrA25c;!JP}T7q!8 z6_^x05%o2KX%%fJGGo|dfysroa++SECS)YF{S&3B5*A0=p#WrbL zf}eWs<6iuv&k?y}cuGK%gGlOtp#ztO_N5Clwj3Fm5aOZN)~-&iwQZzhH8!d$ts8xPBgN!q|CfyE z+z0VV*T@AgKkJ5ATs~P)j}+`ssO{{!cqqd803R~RG2nBKNYdl*=)v!M43dVN72ki1 zdIamGx+g8>YB4?xyLEQpcGp8`kUTv z^#(l_^}~)!8UiMnSB($KUXDbu>z8n}LElHgb%O7lRj-SCHU4C;A!#b3N}A}{X26!F zoqy+Ly#XGE21IHJ>Z7exY2xV=j3nzin#txvX+#F5LMiGph47n?ar%CFi-A1;p z&RI-|yt8rOtHFXdMOsbpML{*oM zS2mYN3X_h$M2$PB7DUC|;M$~K>GI4JLUVGw(!nsUs}w%J=Dx3vCDXpVd+&mTjBMX_ z!t`c=NsYxJyL9wtFUHdxd!$$`TD;P`dARIxSMGF6RRTrEN=lQ87rzxgb!hh2pVo0@ zTQpU1*b^7!H=cLlZiT^y;Q=!pEf-;G#!VR=lUoD>tU!8tf59DrGi3RaOKx-N_9H=w zwnql?F4kJ3G}uGh)t(-&X3}SbTx5QFwR9`nTV#Eci!r8fCG0Yb;KravAw%t#)tD^U z8eiL;@XN1FBi(eI?`-*vsf1A zb`kaVnKtUVxa($ksss+Bkk@pOiJv8MLtLGcLo8a_T9vzzet06Gx3x~lowauT9t67- zfZ2$>mgF_Woq|43(Mma>Vx$mBCwA2B;zGyBo(HLn6YlTqv~%uDIUd#;4P!d~mtz>S z8kYWy#%zt(skc$jHAdz1F6X|gg*6QY!fu}nlJN4(jypJc{&;i%%v;b_IA=_Q%HXc2 zZ}iB%?3#|psS@V*j;&+ng;tRYC7F?$?u!nZHo*Geqj`jA+9{8+@Vm!00}r}ve(b*T z;?la+c!f5a%o7%J@_4+r#00*r*nD7bwK-$J<#tyR(Ff*naq)*{PvvYAT-URbEp@!* zcG0mElzu!e(}pDKwj2qw7a3Z>7pI*v3y~a_n(6QARR~eCnehmTmbGnNmV6JLl642jS~U$6Gxc+=+RX;NFA`*9D-bXxkB>9`rR_8}S?t*obI@o= z6uGPgAt51MAuP$`kWP8&g|~cpNpJY_?AzNF4Vv0zD#xF-H+Q$#we+fs@XPpCnn}?5-hw_$9E_dUbEYg)-ybWX~dd)1IL6IZehhq^-M$ zL{_qt52XpMeC^s=b4zFa^m^$8`hyugj^Os|^aMw=6PI?*(!Ovx6bkYShx+?8HV^W} z0md#KIKU9+hIdgT214y%AX!FU1}cX_I6weXA_Y8~q4F@0jf5jmph()u4dQWRB9(;2 zk-;y;V5UPcfrP)*#LX$K7Tg|S0zo~K%xqnh= z;4h+@3mHfA2w++w09TYwHNkN+b)JCCkN`^<&u?y(70g#;HObwP~QC#1lL~#}HHrWc+_%GpZ|v zmin~J03-W5@o298BWL~kIhOHorH{o$_-; zqAeZp#gXttH-H3?0kW?P76(uON&pd{0#t$1NjM-FMh<(>|@-?o>lseYMk#1WwbYE-LuprxUNKoAK;fD)qXW9ENu$JCe z$a$<#Vf3h(xMVcXx4ac{{@dHzi=pem=N9ay#!$1v3EB8DA=|s1R;feWdUFlNesWUr z^CI!rW?UwS$saWbu3mdnkiTCeRU{g7s$;N-6g3h?tRp3+bBihm=J)ByJLqO+JAKbT zDaFX8qU;&2T-}lN>>2zBTmG3$=|VBquqhTn3oUAu5tqK>Ckvj?V#~Y8gY=!^Db8Ic zM{K;V=;;_-G;Wb(-kLjmEj86Ey|m-BKilVF&mryzwe&j!+!lM)u1`Wezi%Jr4tB^J z%N<_0-1PKZPS&x@wGS8`nhM>6AkAx^U4aT%;rbt3(fTBP?}}QL>V4#W#KB}o;{^mN zDAj1gO-a85d8GD`(&$JMpR2eD5yg#U_+X!W8Y8SF{UPr8wH%cE51topcKse#0puEY z&@=Dt#~!8+s9H_A;vlKeE=aLtH5GZw#eOGncTZqCK7 zA8nR=U(B3W<_eEaZ_Xi;$!kolW+<7IFgrUZ$7rOoufRhI_i{3v~BrOk3BCkRH}Ssr+)ZT?tNi( zf##hL%m=F^*2k<<&&+#Y%X8pvva!jxqW7*oUDjGRap+@JU|LCE+Io|-%dO|Lp&njF z>1Zd_DS@+Ep(|p~w7nlFjIIpA%$^V;cQ3C{oAx6`VclPoE+b?4PBXzv6Muv zB%*oa_w`E}>Z$cac&kJyF|QZ$5Ap{2tR~d;nj5CoAQ~a z9`$i@T$7Bbo~Vw_ex~kOA4L%FVyhuNcVVx8-!kGSaG`G&0sK&`nd{jOr=*!?<(*s5&olyampQ@fNoJ#qo zBSRT2f5=i`&QA9UcYJ*d-`D=ao~we7siuxgi&Zj)f_~zquQC^)qfB-ha-z@~ul2{x zJy@EQziVeI{W(H>Pzk;w{i8;GpP~+bvP%yNBaHY!7t@%VF@V0+J9}PP{H%+<%7pRy z-Z$kcV-`|$TTwG6XO2oELuCCM*W-gWLPH%dev54VF}QNdQpb^tKL-+c33~b2Hr6 z3@x22gX`-1g-%ys0(bdtW&_H3e_CLVS_osHA2 ztit`ffIKSmq_$-%ir&Az$ctUU?w^mu$@MaTgz#>lbd z=DNBWv(%*f1u0i!>1{|SCihPLRh2I_H=?m9X#e9rP`PR87h@s#j^WVV!=`lBA8mUo zQZyx9+J%9=3w19T;I6xE+@Y@p4__HDBe}bx(Ray zdR(x)ks4`~!olhk7CO1Y0omg3Rcc=x4ioRTI+TWMGwo2yzFz*`*(0&H<@3uUCw~M5 zP7a#Dj$#y-_Elu&5^XC56?yJvThOh|(Z>^&9sQ#v8oHMQ{oeYEypgQV5hkkIbyX$8 z*4OYO__Ugs*a_nhmIRAH)X}!+8s-kR^1_eW(i4f*Q}+*wMQrn)i=Bn-ElDv9h}3Ox zJyY0tHK$XEE9UD}7iPxiC7nXnOM(SDPx-?Vs*?D>MSRhziI&Gth6J~x&8yA~_izw^ ziAVf?WXrt10-E=p;a?sy)J|8_FCLmx-iHi|@r$~8SfE4M=oUn>p z@`aJKB>07z8J|7ljHzof(!td&+~~WV`siHJ_}v>)unx`JSO?<~aTaym!(^M;A{E{^ z;YP;vSb2;GY4#}@{|WhiWIK>u<_v+f4ZXvc$U-P;m)W5NxHBpe2R~pQmPYsXy_Tfr^*&GV-I87k&f=q8& zL*#0Z_sAndzKPDnN6h8*UO9H&f`%QgYyqEf)13X`9xQUrKl0xSBzq-i9-m>Z*z&*{ za_I3~LVWJ*HM1%$N3ry(iEWa+NDbR7GsE;69@Sb_xhJ}7j=e}_WF3kQgN1#4<2T0flAH72y(lSc0f&;Qi#rL-H<`$H zrU00w@RFMYmt5K>LjHk>j@S1e+a|3OuZ9+^ziDFDUQ!KX;D0yYhHN3cmpgPuphT#% z;KcqTGo&vP`^{SCVBM?s9~Li+P)5!kIoa^;$Cjg_BDc0^wxvceug|XJ#k{18fcC2$w%Au*pJ}yaah)o*Dtc$dyV~R7 zTR&FET9Vr7l}in(;<>}hA;ax*JpOj4O6?@)_+~9b##}8U-$%G&T$S>Db$xDFtIxOv zCuochwwRC^g z+86(^xDd1P@pW*E(v~uw@M&!Jl6O#t>7oji`bC&m!F&i-%mpn?|10L?&B5ZHf<>p`iRa*<;GC+v2BSSCF=vn-q)Nk z+8Oys-}_Gb0EQ(yo386s>Qt+Re2HQ6{&p96{sA_I<;nYsfopa_+!>jeFv&~m1%21X zXQv(fq=>cb?5zAJWP|iRT=7tvl2sPmx7L#3p0})&bXx5Gn%rVRW7**|8i4~oyqihR z=TnaCZ@|ImRplZ|6>j=OKObLicWx58$T+tGG;N?;1aHPVC+%}>4+pBF%3K>129C`f zjcvaEder45l>xn@bDsYADPzVfn8}(wXoO>)o?ip^o1RO0dA)D_cB)iDf|V!V%U{Ue zrrTJOXr@)6|LorUQ5%6h7B?yuM-tUGHh^k-63LXG4Faf~G#V)emVV%WCKNo8paFJk zL^Tu;Fqk|X23AQ388i|m0fURcU?L!!A<^xBaG2vM-Z)Voyf4|w6;J)GnMe}VBH?hf z1`kRa28T*PJt-7l1ppv>x)KAW-EbhIDwX01^6B9SWU>ErO9Dwacd(|1BO$Q=JW#ZZ z3{nQ_4*i8gz-7V8oAy8nzj0`kEZD*MCk_Fp^?v}`48$bhUhk?s!$;%>9@|rT52sKp=Ii!rLth}a{mYlqr hx|*B@TKRu-IM7;aWQq%kvKtIE_&`pb(mbOD`9DFw`T76= diff --git a/lib/CPUs/MIPS/doc/mips_drawings.vsd b/lib/CPUs/MIPS/doc/mips_drawings.vsd deleted file mode 100644 index 4da74c83c5d3a297b66a30463a65912dceb4bc08..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 1437184 zcmeFa2Ut{B*EYQODN{f_!_XAP89=0{FbbB~W^7;w0c%tc#Eu|E5*tLvZUQluXdFo_ zF_wr)j9mwfiWn0JMvWEhB1Q%jQG_}F+ULvwsgHTz=Y9Y0`L53^i_C$6nK}FHb+7wg zkl>nY#`Vmu)$zM zz=nc_fQ5n$0}BHS2a5n34mJX8B-kjh(O_f1-Ub^BHV$k&SR_~!*aWa>uo$q3V6kA6 zz$SxD0h7gC!Y!bPZWLwe(;9>oZyPFUYZpAj?#sEMJPx3Dx6C35qwQ=oOH)- z$&VPr^_EVH-yQ*Vqvh$3%bl2XC%B@Tp>!VQ z+PI3=CN>`Su zZbvx;(8`FZaj|@odT4B_IxK!<+=Q7v$e|sj2%!1)ed1FRr^Y7!JRSQWr*>460E(iD zM#3qWxD~F++K5t9uZ&Zb-eapKN9!u8REtZ8?Kt#wG%bBxu731vv_a=00sL!++H-({ zyo>M_z0hHY8+@tB3k@taVgCpQso@;8uql3B#h@vrCJNqi=>_W1Gdz&^S0ja@F*1iB zToKMt;keYKnd`8Z557G|uSHnb;z4B}xVoBzqG^&5bRHTf)gwAZG6FNv!>QpEyN;2p zW2Ecwr|Gzm4zXD;3qkZchGD{)qm=eRrH!hEQz6#lh!#$tVcf}u>f}Oqa+Xy$uIAG* z8cMIH*GkvZp_TCED7T)Ltz+ctnBg|-7~6GBqjgMUIB2qt;np#Vb&TCQX1j77V?SH< zfkGOJChSJ$K5887K?QrzyMjHKU=KFfLlW#EH3h2+Rrl=ETDAs%)Bkgih0Q~7)Ov@U zR#Z-_<8+Q&PpXzb;!_`0Jf-K+5NaEGfU*dso}W-uqwqqS;eH(!ozZ@vSgqQoT8H(B?dSIBnJJU{j?yD(yG~VRw5BsG$7Hm8 zS}6S5w)-zysCIVJxCR{S@XVD{?y)sI_1C8D>s*it6ALoCAxq z_QcW-o50!9J*XCA_qDq~$l7x$#^A?1z*_ z13IpdarY(tmZVqP#m?cY*2_vwHtn%gqgHlIk-V?;?r?A7v5xIi+pBHYeTE&G>FpN> zc7DIp!btUytj{AaboJ}^!zj)<>MphNn4sWRf>}vt707y+liVUI?xeiX6(&E z`l7RNQZdoI; zBC}>?Ey}tW=H``+-pU@7JuW*wdqwuy6Ng%TtJLk=IVVzO^fq=io{9`EOV?!voX)tO8N-LJkF$fl!-#@WVY#*M~3#$028@s1H4%8t%Y&R>#`j9h-xeBXSgzp-GrM^^q< z`QPPV%72)TsG^Uuw`cnoy(<}5bZEl22;JSSD^4!TDEhc)SJAPe3!`zX>qWm7@kMrJ z9%VhtY>SX<(e$$UWf^6km3>q8W7(B5SxMRJviuRA&b$xbjUU3JNPZ5#h+oS;Gum+W zoF|96j(Dq$< zG<9ZjECdbG!J!dO$P@EH#CKh$&|)=ss4`Q{vm5-&@+l|4gMqtx^surht*q*G?E+5c zE9EnC@0P#Q{e;%soizs8EbjeTXsY)%?NAAWWG~9wPU7AHZ}_;p$t#nuWUcu_gxA_o z-6fkbZSE&A%Mc}rW^ST$SQ?G;DOvP!Sw1C?R-?_Bc|H`L#r`Tqs}VDFB`QL(D^W}A z@bLK+7WFTwSR_^2pp;uB73yaugbE1oz&6iZmcf@TeEC7D%oeAv;+HW?U%pIOg<7_x zR`RT=HP?k3$Q6&}W^(D=YHky~3em4qU&@<&unfP4nE079`Pi7`sqr(_34A=9xFkPyANY|vI#!*O%qPYs$4rTx zsD7OsFGcUFCr*t^jh&ffkCNbz)kc?83~v2V-oy@kiSfu-zxChWKX^wwu=1JqQ0+4# zzwkxP1w6IH$XB%ec;l27ceO7Z80}M6+GwhJT~xckNaqByMP-tXxXRd<<@*auM59aY zr6wBI*IdD%D-tBVU5#IvFq%Kbo~+d&{OB1UR4l9(U#o2^9U{K|D{YYQ21@T&^k7SZ z*gM)`<85sqkf+*6&9l&UoMJ=ulq|q>u*A$O5yhlXQR=6Uo)v4^FEE=zKhKuWLXv1< z1$RrMf1zbXjJybYmm!*B9T8^OL5Pte7T$^-g_PSdT!m8f4AE5-OVv`CR{APz6}}2P zFq5;wli?)S5tTkz$D2u5TFaZCM=ES=gVRxzwog2t@NVMN$x~nny!-g5+rRZzXI?!* zh*SFT@reoXi4&5i^6@kM)aqU{X7I6U%L=Mz$0tU|PMN^ZNRFN9hs@6AL=?p(O_`7o z%ll24k>KX>mWJ18ka;WWfQ$5~IsU{9aa+|Fc*aW%al7}t-i~(g_9r0oGsRk5WlvQp zf*w@LTH_ehC=q=L*CcChq27s&$iv;{m5HSkHmkd-X9j3 ze(G6?NR3;0vcn`zq`I9*<+e}e?c?65pXAQswrD461IO-f?eglP&GF&9(+~3iz z&`xRpskT_V!H5dc2DI5H+fmYO_JT5l8)q{Lqapi0;vHr-GwtrAz71JKxDN{5)9WlB6o z+60iV&8}`}UI=4Y#i zBVGdRPznr(w}BAb7AQ_tBQ*V)=?l0fi*^FL%qurtKvFyOW0mPI+|vTlJsrc3D*3CW zu*>qaK~?X3^|2o+(FSE2MK{$=V&p|H<-M&j@lv#eOX40q^PqeL7ezc&063l!(MbtD zs)#r#!AA|EiDwcV(@kjxQmb_jDqnIoPO|T0K@X~E)naKLus2qnPvHS}Ut*2Z5o)xH zCo|fG9qpV)$?}=iiZ4DyuFjjW{4*Du(Jr>;(az`~$_F23U|yNBvFPLWK720vxa$fm z1<|9lEqGAD&$Tp{RapF75ij^TdU0wMPFTiKR03Lhf}`jJ9xdT0MwP(x(#5`9cWx*L zSA8O<=hkswa7VZc+%37uQ`$n}K-;jy@o^d8_(bp2NH}jrhmG^T`nbw;Ra^c1xwhuH zvHAEb&3V^hCyZm~$!?`7=UmgaI(5t$mubISZLh*c^<2KkhQY1x8goYR7bbSt@WhxS z=NJDl>6@!s)KzP^I-}E3ZJoawUgxjqSEl6Z@_SW+zXEqv1pcZE_$wU}m+!DvSC#(N z#~O51s|#(@`Xdc0>A~jpV7p8B!`jgEy}}}1SGm2?+Ec`Btp#@ljtl(N0xT(rhOcd; z3oz~|F)Pz7?(5OBRB&Ghi2FJ&PXp)y%t6<1rNwoD=ejAnu2Pc}MO0zIbJ0l2Ace2! zxh#$=-RilBA9HF?O~_W??!et-YY z4gV;0xw+!KhgJS^w@V(~(NKSrN0GUzX~?0LK!ffLKQ_nhT(H|-hmMCgG`;_hkNY?N zJtwu-6_gYucQp)ssMkiRzyEN?zYEmuWh7FVlcqY9Y9#1s1nd z6+R9CgXizS)d4Z&vs<+i6vTsD+A~Orx0V4REhlcNH;*n1QQ|eW=rxJ~zl3zCQFc!y zuIhtuFyrtz1icJr+H^xTLzTPnt3GHv_@p*yA|Il}BSE`zC$I76p-#OodCuzu$h@k3 z9TeJ@0^rQdEfOLga3w*!5b!{}(;Hlg1a{fO=N=R|l7YSwt0w_RQVrpbCEBU7coKvP z>pcll->vf`vY>=|PXdmlR|8K1jznJXNr)raRp&{-k)(;91RTi@t0w_RQi_5hS^`gk zY%nU-Sv^UIdQZX&o@C+6#bv2_wAhwnI8z(Wq-6Q#GTw`Oi$jCBaa=t29`_Nqojb_o zamClUUpby@B(=fdKvXa59f)|Y4(1s{D=SL0;62RXKJp(etH?RYe{VFcE4bM0^1%{q zfg`Q0fXHTkW|e8f;0H$U7v=nh=f>h0oj&=YXwpUPr-LiY3ypj*iE#=Uv=+ipF~$La zDg*ux#2KQSDx@dw0$wvs@b)@bpEf00U*>8D_Ek5wz3g!4-IpH3JNQV=tK*4dpNC;N z=83_l7}gw)dI8rGIEK$LdohLnQXY>aQ4rT;6aR3Tmfd9JCvM_VB(9l`@FxsQyhA1C zF}2G~(PoM>Yi_?juHnUVo!zrY&%a7x-i*+WT{Bf64e+1DTmDMu;fictzqfkr7D z;X!jSH!v^7wo!_93fx|~%$^3&ecD4wqfeY6mYv%N$G*TSw3ksUAmAM*J?gLs+2kph z1hhkm@)95#mQ1A_I;a)1UYT0rR#YqIK_#!#pN!HpZS>;07GDIHv>P0a??DP5$F=5) z(gWzFb6SxQ4VKCMS2Xv#+s-$tEz{e-g_lirNkvXO-$NuU4ZnZqUH|6Zugw)#+PV2e z_GG*IJCszI4$!09DXzBO<^SCOM}IB$Z=?0}f#XE~iQ0AE@3mzoO80w~`|OjuxgYb| zfKKC)8_=p}nuuqb7SA-|j;D3Ww63;0tz&@5*I*G83dJB6Vnrc{O%;P!L_1o8*cuYV zl4T~Vd=S9Ek1El&Wv)7Fb%Xt=S3TGO)Ss>@(GG(M)&WszD4B|45lAv+u&e+IIGNs+ z+Js7xn-C}K!E5|-XX%c>Z86)y6IrI(P9 zcDMwVo<+E+l4`2lPB&FTfNQIuIVDRuDsgjVZ-s}Vx55X^><_z*2sgoL7U5=+?4={R zkKT4Rli;?*ycB|4XCWHpNjOTPQJ#dOBpR&^ULr)j3Geb^)a%`c7o%SF2wseO;}dx? z>W!bti&1Z^nir#9^=t@o z84A0666|_1EtC`*3Bhh>HSXp?byJ_7>@>M41iEKnr?KX+C^f!Bgre1r%jrg z?yXor0^Je*7*B;jce8(j+ZS$wy-xX0nc`Dy4Rq7g({s$NG}ya6&Z$z2T#1UiY4&&1 zEbFF88!N()pTbkJ+#2XMfiU+ZigBAGo8jXt=_e`4Yl}{zcsTZzKlPfYW!?(+PT#Jb z?0!u9qjpdGd)ihZ)-X2-!rUZXrz9PCz($sf3rMU1A`S|%WhQeuU4j@4p)O%aQ!0QV z*+UTAz=5RsQEhetON#QN4)qFo{>zak#WBS5~ADbO=}0e7Ll1;L4IZqEgI=ml68pC}JGpWW$mS z2fh9mj>Sm&%9J_*o4YCS1k}qemI@+)M5q&nlhO{If!%GS@D*vI-FjV)=RjuP04Cab zT$s6{=mh<)G5|L1LKLo3`>|tGSKzAO-PAn8c_mtfR-yPAsC%9qOt4ccx5=cT|ENzpNl`1;~7dwj*NRjuz7z5Qsp^7MrXvEAoC+n;u5ZE z`5+RfK$yZ4bSB_jdxD@d0cZbEQH>zryv>5nA~H?c+)@s0 z;C6GzxqR+6_l#pz&Mr09h(Cj;tr5R?3i&+a9^nj@781|~%wGJ6C!qbk@nw&+ox9&{ z_p^4QBYjYkV0P65<0x}^Vu?|~#{p;)%uWm1`qPxa^V)w6+Ytn|i#61$waQ1S)qR zv>RWV2Rrou4d~ovP}+j8?m1sS#+uNN51;Eat=rMpoS7F!@39#R6~~`A58gi9-|f-? zNQCNa-LE>>`FnVe@pr%9(X9>L2Mz4)Pk2OW(@FkXxqr<{|90LR5Q(ve@42f^zN_wj zR}CzNZc&f8#3@Qdr^p<6Wg@Z>LEI@P1lfonu8#jj*j{;BUUyu$I0~z@y8C`)fj+&{ znYtt5ZlQLVS;So`nJOZsCD22|Tix$#&IbGSLq@q|v-+Uq} zJ$iPWVN?FvNm}4{BxVTwg5z$gTnqSH2fsFezYXB`CBa_{{PKG(d6V0^NwPZl-2vi~ z0KXei6fdelep7f+4bo_;kU4noze99NvxrVMwzmL(E%3`1U=e<+0(F;^m7)%P&D}H> z^d0D@An3bMl$j9GnF#)#1N@x?G7~P$YfJF=oNUrt1b-0$;D-2X1^^airdz~K6ttL_3I!62;V1h z^zNnt2=fGmNdz<(Ee8~~fUqxGDkyWCPqu;p;ZH!=VS^kmFLOeu!UDofs1nb01`wVp zf^b_xflCAm90(x%SODR%!<41Cv=167fbeT{Iv(|IiqIwjgwgW|CBBsnr5Q5>6yC;< zR^owBozVeG7v7j5gQEx%=)-?J4r{D9?EXg_2DuGLG6-z2Hn$v^h1^1u6OFm!i+mXd zIB}qqM_SGb!6E_|3lMB;LEk^pW&W^HJa2XA8@Zcb(3}WvHCFW9k5#I?UjS=X%&!Sm6a50>qxOuB*kfj6u`n_WUFAg7GYPbCU0d&kcv?ueUs@QqV zz*6ORrUI2MBbXXZgU53fxoj$y(eE+CDZ$;936!?>$u@~7XWS)- zN_-u-x?6R`LsTia z3mF!mw7igE0ZRMYY^AikC6VLJTM{{H-jc|P=Pikxc;1r8iRCSc95ruA+lnuZ-Ad@Og(;H zk?IreLZxay3w~bN*Z@BrYPLyct3(EyCV(fwPR<39nIDSpd&_*^uO#BA{p6>_{b^+6RpW^vp)5(3*I3st-yK!IPPw z#2vETpcGG}uzai%XL*n+$2S7cdlnK~6%^XK9sY|{)nbyWs?(R(kYswDzWiKBr;GY> znKe^|wp%GIVX(RNnJU@s2AL}L!rx@77-hpu)rTmeL8fZ7GjGXMF+=M!RYEr2sxLzs zTj?MxboTfobm~*9mLNSxNdPBDns}3w#H5zb44&in~@iYG1} zwC2_?%C7=%ttG@Yg^0~O5Z6u8CbyLFkgG}tu{qO~ek~GL5Sz^}${|Ok0N%DAtJp=L}yWRju1p=tLD6xh|U6QZDmjGl(ts3x2nyQfT4o{ zLk9zd4pyig;Y)KcHwCcP1p5@ay%N-BL1b286k`>c9}6n8bSuHru3y#B*OquKsLYKm zBJ-Xa4;J!R0(QmUzoW%R1&#T8gaj;o4JlxsM+Z=`b5utvuUtiYuLVi0z|n13NA|I* zABb%rBFoziYwhko!#~KIYS#9ukAFA6Z}GBr1wPySbDsLOM-!!ux_!&Y-9rxXB(?N& zch;P?0Y%^qsKs=PjGUxNPSP~%o}_WKTV?f#Zzdv(*GyiSRu|RUpDdjZ5ZdmjZ)XZ} zivj3qfBLFLMurr%=p%0lRSyF6t_3=4Gfxi4>q(n{ae$Z%Nim`&YsDNRagu*WG6?XF z6U1auOCBzY$s(Ec6;(hBnJu=8$pV?>iI_~Zk61y$ladyqCG#_8h!qrka;#WE0TQ)HX5TdnVzNMHc_Jng zGFwE%WP!|931YHPI3bG30`T?|#bk??+*TBmEo64MC?<=*tF(&ABAZRG6O%eQiHNGJnh@1w3!S|xve`K@B+}V>HfySrlYz}b>SD8% z%{Kmra`L=7Hk~;Z- zBc?+-_wznzIG}MGbZl2Vdff*d05!P{n#ad0@mJ6%FuCT1X$2meti(;*fJm-+BPbSA zOhiw%B+>rE_2mDRWG`sP;@K*FV9}2At=e&`4r!aamSsO6`QGbVU(k+)d@pFnr_JS( zXU1ZlBzysa)y*Y~YE9?fAmh8g0d)n^wCtpjWIG>_q%Wic^&P1ffWe>}KYU;jjuADm z0T4qjz7B|)hoC=NlD|XifjCNH32i|)t`>ke0lYRlvkr(W@h-^zT7j5_G_b^y{H5e@ zU}L6i%~T`6X5hE|f!_{P4*xB`O#p002>{LsASovRHYWf!!#BL(K|8Pju(uSM2?{Md z=%>H~l!xr;Bg2(=xP=9CKw|4s!^4T_Ti(-*8#Ok8x44U&m$PHUi+o8IAj~52q zR<~s^t!_YqOD!aLR;vNr>Q)0z9YEe*Js{otc(B*9k?w`#d?B%tPckdB{0DhoI1mtb zJy$)>zeCAR|3!YacYg5wMaU)ZEV~Uq-gnOZ!4JOs!?wCtG}8|9F3fc={lQJvLo!ec z1=$Dasah=qIJrjKsY?&ZHUA4*vv&{47JtNqob@j0p5W6xr%0y0S?feBf_ze+I!ITx?!xerL1S*uI$OwD>B%H0o0 zc)*i1GYJo>gfue|BlikvW--ewMh2EF^FN3TT*b(ss)Dm?W@i<-Uzs2*_^*rHK*;}G zj^m{B$?|~?oWjzb6t-4OKV&JVZk^^GFw&dT1YaB zD)-vDxB$WeZz#0{ZIp+TfjoU)U^WcgCI=&(RksNa%fzFmEqxh4yu0#83k zGc%D_l(@AJ6+C|z9(skN5k%omJB7y1QR4aGP_PQDd@csj{Kqor4~$w$oke4Ly%PID zhoA;1dS%;^3h1+8N4It2SDuOX(s_K?KeCl_xkguNYFtuLWs6$aL2W99=$3!`T;=bd zt0}3Ve)o5aEPvM?je|mVTh!7KHGO8H-BIP=Jh?F%=lD;a?DS8b?EJ=0c0l8r{`Sd# zbK<7_{$%{kbEp1;=T7?v&z=4cp8Lh`pZhoK@dX;U^S37go($z_zqx{}E1ic@&!g{4 zDr}M35oyU~^!JN>0ge0N4}bixE~6jOxcuKd`E_@wZn1|lNT`h5KiVFb2SUw#+Z%lC zGpMh1ebrG$o6Bpa+v5S%UZ`DjCOO_7&py#vHh7jj-r8Aqp)AQB7X-^w?eR~wotgQZ zg3~7<-%cmIrK{et$0K&gCYHTxj~DKcjh$`QS# z71A_kwym;%jbo~0Hw^YT6IC(oy`gfCE2(IO{?B}5IdT2Si90qGK5G{^aW-(`DlWk3 zdKD#Q%;kOIY)w1iC2Ij^E7?o7iJYwkUb5t5_^8XgWNqOTt^PvFE#sOqW0TM(FIgZt zTc1ys&$Y+%_j$?m^X>5wFInaOi|DkMY}EpLeEi3e@>TZum(KExDtmm#OV)j}J;qN` znK#I}h1ON2>e^CJ>HZ&Al?q|2wJJ5G*wV&R*r1IkUnpqql%a@>XdO3394mGm&@ic64b7sMH(g7my_A!GNC!@ zxlY}h7fKZ&aJ&T|FH|XB)qbbb`LSA>)G8j<&L=uN2(DJ` zNnICfZ(7UNWoQS8?jNJ;h*YhgC=zPONY#2JBbKN`)|ycLA|$l1B%#omNJ-UIk$I3R zG9RcS^CMMcU7(8WAk=(`#pw74=@`4HP-$3h{pmpQ5$RRmO#Mb-f8KOL@K6|S~&f4PE_K-VVeFj;^^lpoegiW~g~<68MDG7{HgNf~0{6cG+&@=9`8CUd`=9GWiphZP*GQlNvfGq5 z6WT>~pQknZO2s0v6J~3XSg3P-k=VoMVL}PFsIY^6Syv(^Lk&7X>Po~wU;p3h1WEbX zvQy4B*ePPen{;973aHzYroMc+DiyhKZMmLYC>PBob4$37IkVhGXmaDRwem|m9i@kj zq~NQ@7`Z!5OgXo7q@QWWyD|Dj2ZG;M&MS|*kU0lRu?Y1#mNJiPwuFTzDm zgqf3^Q=CwiT?H!BGe{&ulbO(}LAo>2^iWUsveLkaqR~(ovu=)6 zN_?;k=2JYh2xEIbP~y!!U~}{nH^)7)IqnLZ;|Xkzd&1_>XTavT-v{*+Hpgjy2zotc zqn>Z1eMJfDlm}f7y0)yaKVEmY7EwliR#!yXzplkW*dGIgW-03q;YkLAWT3_i4V_{J zY7TU9T8k)K2+dN~B1%8fEM+aC^cI_?tVNW)gl4I_BFakAEF~6EmXU@~Ap@0cX$Td1 zrFw{9f>M66?2zyNutRKDr7}|3AI-QnTn{dUo4`Fv;udquk>q`xny}&(T1DB|5Co|& zj}*_!$isjj&qQ^LH>L@=apG;`c)*PXu1usO!xz9-Av>iury~<3RAfl6zTsARB^Dv4 z!}&J~X4_CHpo|yy0vVVy_Pa$Quwq- zEJGHXnHEDg697n}T~Fy4mCb5UhR@RPy29lj?fm31Ajs~fS8h7Nj;X78dTp(Fn$?PQ zAEk#mY9;S|-}2G3JG+|sYdN=F;f7WwiM}&cB{|j zl2oo|T`rfTa%-)-kG74RXWFuX)bRCkW!%Ax|7gD)OYbuxdLn_x+pL!i9xFD(C7A;OS0_dbBEcR%U zP?ef0?b2vTDkTj_SQ5gGq7$SLp*2S1xixfmt{r!Vb&jt4(sJDX+oa@_0vhjGb^P;k^l=78xZfeQ) z<4EtJSciNW+Dsd?54|j}6`O}pe{6;#S7do@h}Fn~MUr|bSzBs<2R1M7-Mv0lc`x+qAqc zN7xsn0P1p=HBkdRc6_ge%eg0WG)NlCe?DZ|yK%P9jAm%+bc5(Pr4b*MViU#Oi-xWq zX-ea$6x%rrPp8}I%n&@!C*A2zfH?0lJyV!;rOs^k%JdHMO+oZLEcq70G?4d@IfoG| zqoQs?WfTMxS0Lp+pS~sfMFV9<&tF-t5RIBDKeKnX zm&i6Nob7kGLc;e4`!Ai{?4MqQDOd&v!PmYr{fK8YBW1uh*I0T!Cg5>qXEnqou5OgO zdRefviS!p35+ogOw;JK%b<&<(&vuD+VQp5TP)j36t%8;!{r||atZ3BIe|Z=F|G#As z>T-o;InKg*2#S2(ydarnRbH7QgDt5!YiptOtaJp+Z+vkL9o+ zupXqbW`PJ(2Y-J43V0(AO|37*u2$%)L1%f?>SHBt(FZ{3R{^C^Uw)$!%lpCrFtdnK z7t$cGixZ-~pF_~hY5}Fjexk(jyZWHFg)}G>^qzm*2So~L&^4QtM(h)W(E6oJGM@#I z7mQHm8`2~Tgz-TZ2&+qi-W20O0%89l?XD@WEy3Wge+&losrYrma)Mu2y3AK)o8Tv3 z;(?ZGxdHf6!U*|N540p0n(8mdF$)uBGSUUM1n3d~;1;iLBFzQB+tJ7c69}w1(Z~`u z)^n@BKs5J1AledwXsUk?qILgEL<5Nk5N)}LXb&nq5Ol@<*E?#y#8+Tc%Vk=A9|sBp zKc?dxl)Y;R`ps=?YNoh7w2H@CGvDdYc z&_t8ua0SYc-V>{kd;~Zbb1kAAeq@#9i z>$ex83N(&Xu%Cjc;yod%_~~dMdicC2vm2s{6=@duvZr`UR1w8nq6%cRMin$~i7M!x zbx}nMqpFK4Qb1Rzk1BGQ-?1$cRnR@_qKX<+Sr=7U+DZiYV&Scd{uSP;=wEl{X%xQ7 zZGp%u(C%=V7J>{R#_)&KGFcN6S?nNDh8<+lBkifMF#CYplA#J%sA0DyZceN zut9(U3v|>HV88;wWC|;sod7(uz?rQjz7XMT9K;te=I=uccxGx4U|1v$f@ib{XoVKu z)zg8+Ffis%Iz<6PJ-}R7G1x1fbV2 z4(7RzoN}JfGIGj!VKNLz9A#u~mB7lJL|SHHWexSe013=#u<9FTnbF!LDqUaSB+9n5 z>KlZWEp5;wifrrj4I*z0Y|tc{&xAH?5*_VQYi$x;-L0-kv?V5aLa|Box*`ikIG{Yz z>+ee~r@kmx*!z3>{|&@}RE~d5Z~}<3Z?rg-DH2#(n$056hkKtL3&b8_92#5#gMA|Bz_d!Bak*mP}#}sF)L~NR}fcXg*c4SUhC)wsKPY|2-UTqfba;KMoG_T-Qb7SnEfb) z-T;Fi#J17}P)Z$0gvIITAaos)Uh$h0WhcEwl~9)vdWx>#S9mA&6kSC06^gw{;T1P2 zx`cw6K{kpiguP#byiO~yFi2trzADXt!7K9UAO!&3EeeqC7py`XnL8+jRPH2^dfWFD z^M!U%P(od)?N+2CKo^JB3rHvLv6W)+PN``NAe{(wCO|q#iR!fz32&<)yal8Kpt~X> zU54U+7U*68MFYA8el&$|6h#9=Ly}rjvXEjMmC|_g9G396cTfsq?##o|1r@NX(W(macwRLMb5(7NNVcVMo3Lr)<$l2u(N6_ zgsu_NAKsw>(iI)HB3&fuZz4zs%Og@Z5$U#5fOMBENEcKtBP(QCAjYynBoZMD1hW!E zCjH7(1xz}ZsFrI$#33KyBYXyPvoSg*A{tW0g zWh-%ZZD=EC1c#s+vd4|SR^olb>VfVF0Xp|E0(7K;)k6TfZvg08S%EGYfG#Z@4e3k@ zSeXOx^b6r4(49U64Jhzg-W=%2c`ky92xL@INxk;?28pi!bAj%>2y~?bt$JklKj@LP zwY7xwkX4D6my5T^z+;e?kR^^9S(~CCnPsHg(lX$VAWJV_%hMtKHCG7797_oH&jD&^~ zc-8s=Mjlt8mX&mq2+br7Cm2-=-6Uqx7BZZqyI}ahYKmG-U7}Z0%xWZo0#z#TOA4|h z2UtpWggQe-e1NhMvl7u66kbc|ije^oqpe^&5&n|ePJc<^!xUprpP{h#8R{B5nYDnR zpg{{b2@`TGHL^YJc7R9j*GwFcB+fFKX)jB0_*I@_hdwz%#o*ZFy?||PA3m3m5uGW} zOd=!wB+A2z6q~~eAPO#IZjm?<;rl&k))9F2ESQK8NVk`ikYHTC--mPscou|*tO1pP4}qxXfncRroX~V=2770RZKcakiW9c z0yh|ekWJ={Nj1q*O?MZm2HG{PBM?9q{ud>oCJ-)p>(rsn!qlOwAO?0vXJF`%&@Dom zMQSZWhp6NtOGlll!R&+AyTGrJ&U87H^5c2S>8($~SPu4k3jahEFp8^)Q4}G37qIX+UGm#GGJ*E8ZVt8bZgzh%YRE?sVjVR!my8;M zSqEIwpN$$4XC3^vM-An|sG%VWTbs@bD*g3fT`7zjI*qsTC=^Bwd0{fw#!h_=&p3;R zKNMyi6jDGz+8}cqHTL(Q{MBzeMZev&(MI$TbyKkB2$-qaT=BLrY6z-8S0|}yMv+KH z4Gr|iXdH|hTJ1m4ZIheM>wy1QpZ!0RQA1?dK@yp%*;IpDz^I{8VWy_PX1~8?nZL$5 zQ`1f@Sv_AIcJN%%QQPQh@$t5IVcNkKS+F;BHK~LtGRM_-(MUJ%Im}qMc^%~?6^|C8 zP)@O>$4(66hdM|3FfoGB=^=(%LZrnL(o52YJFTG>L|VGEba8@ape!va(B*yTHV>3m zS=lPP9;pLHDKC-`3%^a+>edZ$cDEz#hXaaFN>@IJgm}x9u+=&cKSL9?dX}<+`0v=N z2;v<3XKYo*NuW*+qAU@_4@tKXwhHkb=;0I4iZU`iRZw65%d4^P(zI{Ke0dp2y0{#} zPWKS>1aUe39nlpGB*DyoC%O`sqxM9gOk9qeupXA>5JD<(Ic8cys{9LacEfKF{lKyu zi(x(LmjkjBzlo{-kev{g<1exkkAj5-5!b^VqAD?{64qlrSrBnOI6)3SN91rZsM^#i z1aAM)P(6@~bEfo1mH6XY7}01As_q?E;tiu9sDcTOWXfYr21H3P<*_pwKt0LMP-1b; zV_>#XN#;C;gMeUegYIpWD_PTgdhG}Q5LsgAq>(r!6@PPIW&j+nmf&1<{oj?T%+a=v{{@p z3sWMk8Q;1%Yj9=7za!2PQ<02NnkTai!?w;5glag;Fzh!&^y384fd|1L?A738J3?8K zI11Yg#7IQxqh!beupt5j1)&mnP7UYI6rX8galrg9|+?E zjl%puGBlfqso6ryCl6Dzg_chqre>?jtOY*a((=i})NG;UlZUCCX_fe2SB~%@$CHgrf-R&ItH5fVwa%`xVR&WMF8to^esIOGHKnn)ImBy^w3%@7vdHY z(5HWAcG$(9k7}_yD(ymlE!lvY9>p8lYXI=GbqR^tx=z_pEf$KKD9E&L+q*AA!Yrj- zqI28$Wk2W|Xz1K5B`Je1D6zRVs@}Qn`B91a38BVT=>Lr#EC1i%v7qymdtXBH+{co6+ zt=ianw^ef)I;|%`OlFy!@;nQqFvrPOx8)?bt--%Q;exZ(ZSA*-N7KU5awU4U4DK~> z=am8)DfyOg$E~q$N?deD4!0;PHRU0`H=3b>TMF3hfcve%{Q_`}GkTZI9i8pZY;uRv zhAKydR{Jw!c@HI?=ZetU1^!HnR!V%h)mZ8L8`A3+&~7VcR! zwl)0j@y-ZsC^hvpe*`@mO8lY=e1wd6)?11DcCUi_ruj4TeBjMYfTF?VNY+<567TGN zOnU4J3iU(tKQOXwl-MowiPYG=trFXed?KwmAyq_1A(Z9MTqtU%#NA^rNN4!vEAg|b z$LL-v3h^}5CbHzl3S^eQEfo9~HHH9#YYg|w!^++;$?f<57|S;ps1Bl^nAo?=%I{P| z4T>w0J$lZjpZ|`gZtz6mdh~n;fA=Nd8~Pwh%SUz{%Uf>QmBf$jJ9YBZgZqmc#*tj(`BkzYdOsc}nD(gZG1>&*Pq2bD@3M8<=I?nUbU%1nc4Uk+KOhErr}_#U|3R*p(9x=&Wq!>R zPzDXx`%b%B?CmD8Q66?-4!f|2otr6p$y5#%irZ+u^HVIxzGrL>yVxFf&QNvqG->+^e5Zf_^=E7mw3q0B)9*>3(_h{s0b5w*;SE3?S$@?k_z@~H~OGEJM_33B)so@ zZX?Nz*3Z?=TieS$LApamBR&W{BdaGP8s;8SlOf`Zurr`hdwuZ;W)W@AJn)ly1fwdy=gQNBak$OzjqJ^Y%Y!tM6*r7oBwE zel@{R7A*~G9rU$E;u=EvhwP8l^a~jovQ04~WI@QMgER-Vc^$q{uNjoLbx5A_tM;~q zA@@S|zpJSZX%wlOuW^eEh%81&Lh?FrGb2}@3s5YLJl8(<4w{K?jI(+4tQn~Uj-Ibs zeQua?vF6+`cOUrTd!rkC?SLF|!@{8LF*j@sa;}PKo*NdK2wXO})HLU9O`>AL!gzSr z3gnU-=Ce9U;~nFj8@6#Sd@FBD8hqWg6uulmH{0cgokD)OVdv3J|J<-bq{$7thHiGr z4XZ|P<%ZedxUTu(xO-7J?wK+1EA7MZRccch9wLpwU$*gz!NU$t9IlPQzm5ow!6S3S zzQ&^tgv8)6kui8|dX)#pH?EG+Qc5c`}YHn`$bt+vI zLoJJpp;jKKilIKq4W~nL!@9mrN5#ib6ST>b_?YX|{GxDr!NYKR{pG4~dQ))n=G?Gp z^siac82Z!PusQUW1F9JMi{Kb~=am@x*Ms@t%%R*c7e;n1H~H|DaOPM@5_5cJZdh;T zyWkk+YHrxUh0IM=4AbLE4D)NR_!#CLF8UhN{wWvzH5151A7T2y!&6KW7hT9~o#w1> z;;jF%Du!9oSwCFvtPgV5XNTxdgy_HAz{fDl)AXxC^dFB&(-%mSm~L76pHgE=nfz>h zVQv`3UObQ%!~UEf&R)t*V&g7f31^3njA14|)W^+?jA7y@$1p}tKm1gP{&brDOqTv^ zwtjf7QGYI1pO>#ce?>n$JWJm@O&^h^kImL!T4dC(FzP?#qLu9M&#&lrlc(SOfH zkL!+5xW^_Il?S_J%fwjk^^b z!xmkMVT(gzuCupC#;|uHW7xZwC&#d18T;?W$FTQjSH-Xoxah}hi4^|IiKNy@H-OH4)KlDP7R;gX7wB*`-_`e1L#3ssV&stmsUvMOBi zDmPqGoso21@>&`rsmV%`)LyPilFSP^ZC1rd_?ccY5`?=%OK|+D)GZP!{?slB4G+JT zF!863NLYAyN+O9rbzUNchlLVZ{HbdaIXt{0v57zRSYitgDaAZJmV zoJAfvi<;*w+G3xx$Tr8E<67YBTHwCRwZO%-KJ5 zT&8baraK(C#APbuGHv2AskqGWY8pOH@nb{r9YgW(Ylh-NL-Bb-@hLbsVkrLFP`t}f zyaf(68j4pNidPtl7sA0DLvf;^c$%R&8V<%7io*=W0}aK!;h?LbxPzhC*HG*Z2QG$U zrJ>lyP)r$$!>g&51+J#YuBJP#rs3CIO@*$e^RA{-aB#%c^tG#Lm#b+D9Bgzot#&o7 za5XK2gE_9IL|4-^S5q_`jBz!Exta#LntH=QS65R9SCg-+$sG<{Tun+>lZ~s1ay5ll zWB5F##|G0K1H6vGRA?}rH<(Vr!4ZS$YlCT*!L$VqHX2N;4W<R>SW8cgnR;9@W-4JI3di88?JAox7!u`9acis190LRWO& z6`g{EBd+LcSG3C&ZGnT0u4uI@TH%To!oeI@l<114xuR$|7~_hP6ig*q8 zgG%wvc3kGs<&fjc*2mj`Nay5s!y9?Jt#?1^xXt6d<71Eej$gYM99ADu=etdHXWR7D zqm+C*4KqIU7MkJFJ_GXY%QBsRLOUG$Zw`yVNO$6t<9_d}X|F~LH(}b<+I&p?DE<+t z9Xoc-ceg(@!H#OI>HD~`M$=f+!XrwGmivy@NY<*o4@UU?YCpH_+4J@#+VhS}?3dVK zw0%|$W*leB^o3FzUP)KC zzH4^+exGe$J`i#`Tg`UkLn$4vp(VW}l(rXcqO;Wv?Cb3B!AUgB3FZ%1#mPM%1u*i6a+vUb;Bx^tcuC+9(z!ZnRsy5WB}if6DXE#ww|=Bhl%|%aJYO zt0S+aZ=I=*?-2iK-?)v6k?~XGKkF*X?)cT~QEfkra?$CA?r3+hLg%H+oY*v7+nAJCK+ouuq+gWj&Yv#@R zyl2?X2;a2>RkTjGyl-)@6N;l-ncH2CY`b@-%lj^uvmRwtXTgoST4rmqduK;vPs-lZ zXWM55aUM~H?`Ip*aOT7st$BW~kYb!7L-TU0`>wr&JQkek>apWee-HG-<-lQ4g_Rd0 zFAfNMQ4}={MHRZ;#Sf=m^m@E1a&zRqNc6e!kkM?sVYG=}`XiI?l<(bl`ZK#NSU$12 zWMtN${J<>jPWxM5C-T}))}OaWN2laDpNQX|e>VS@{Kxq<`KU>ex~M}@-=dF$y-YJ& zg;47FBERRK@Az4ldUE^TgiqFEhjo`O@6of!gFDd8eI48v+t|8%nmU9UN)HIT&%rwi zp%nHe=_uOCWnkIZvYBNly=-;aFJ%YHY@%nIZNpQKl&w5=Vw>*80xKnL5554L0)ep<7XUiKo?qr6tT^ttHgC{uf5Cru|!P4Awb zzitiolysosp3t0{a}E#nEToxbmA`%_NosBAjn!eyOZVe!XYg_PXrvvr9^FEbj?4C* z+Z~ser3K&i@i5OmT{alkulxRfV(oX$bl>0bvwQF7sa?Bj5!{k;)Fw^eO&ZN6O^aPV zInozONh^)F-E+UDjojaIUG}U*yR6dDqf>dX6wT^5Z0U!(rv0}koFn(8oiqKH?WV{I zmg3*jsTCb{I?|bUe0(S_Rf1}v>YVCxRoPdghCcd1RivU`2RnmA zz{=6fUbDWEw>H`PPlyf-K9>H%u-aLtTb6bv!92a+eqlm)MMteP`7oDqN4x97lWeOBOV7sqWjaF$JQrM5uSc0rD`i6h&Ex!PfF%R0`~7UpVq2v@_xt(AJd2YY?q zzkhyzcwL;UKlC!secaX^w}(&2jOF8E`6jFM9LkLBpP7QtgDD2Rn?p6tdgB89wcba^ z9puFs+mcHc9JhTMG_s{*gUcI-?uAoc9pq_&hCzG5Q5;CnKFEtSwi#Wqhqtsw&1_n4 zL!jC#?v@v&!l9Xa=2e(QL;M}CcgQif<2F-y1##FB*E`SkPeM%03^fH%S2&*!y#G;% z-AIrh?VIkT$ov@xWO2XUKMHY!ahg7V+<-4>&k2pAc^8fBaktHw)*MIfD#q<&5#k4l z8HtNi#497NG9?Qmbq9qE;ZXUpy@`oe<;9_HMt&dJZVKKwCp3Gw1U ze9v?z_%`m+q3KSD!6oC^pgd2j6kueFgOX>22GGJiB;r+!SGmbgvsW>`_g#&yOnG@( zr9RmMOx0x77_nB5)vRz$Z}WD1^Mg1Wg38G;g5imR8$z{|vEOh!>m2JQ>mlm}3w&nv zvhZwuwu^=&&qw7=RiElvq`R(Bw#-;GOQQs7K*;Y1__k|4Z>l_+L0k1OekG!<`=%kuU1{G6<+L{d>pk5m0`n7{#e}rZ2Gc8@pox&v zIoD^6%mR%V?~tkgw}>{W+7&v~tI*^~mme%4fv zXuL;y-p}pD-K!gVeYyJ)3QW7-pqCYYQEhFjFAqlkBg$T)EMgfNMf~~hBpAD0m0VMm ze5xwh@9s9W8(30Dtci_@&Yq-|up51)3y2uBpL-ETBj zaGD0mctbBv6QG^u50Y_%82?GTjsvt?f=7av`wisLh8c3f;DMi0v_+JYI=@MVWZN?a zE+Q2t;#vhq!B*yqLjK>tZc=~`7? z{4z4{NV2R=sTEl_QeoaP%~nBQWEhM%GV8EQW1(}~wL_crr-j5Z)0sDzpp5yPsoq=X z^}gm+5N7mX0X>#EYaz>uy_7ve&2XE805q^R2#Q#T1-k4XEN4NjAcHRWCU9l1XMfVx z{WWC`({&BiC1SU-%cW0vtQNdKIuE>+e3y(#bYMT&7IrB_o@i`_cf-QRdiCu0>>l=y zg7IJP@^+W#LeOPId2nNA94Wq1Jb7wyc6eEP7oc-}7vJby*`C)KV^`K0$pr_c>D(LK zER3eyE_+lH*$+N(6J})SZdk-C+ksr$u5>m5;v94jCaGzVU>R_LcD?VcdOth6@d=eyb~5 z<(iy}=6kdu#-CzVDRVMDyIe~;TMFn>N2#wgR7ykbQ9rbG5p@gcQB4A^P8y=Csd7tR zHLj_Xp$o~erDg;xiPxv!#V*b=w-*^h(5h_x1=(+_%vZK&8BEMVNId8lpM(jo)a|h8 zm#&3Pzc^chI&+3C@O+&>TV@w;%5GZDymCE(2Ey$;7M?NPy=0!zDO##5(+KeB zCt0E6>kV+eYvznYI0IkJwH9TdyfJPp9$dUSczb)!aMFM7>OZkb=$U)P33iivs@KtV z`Rt*^CxL%JA8_ddj6PsA1ZJzRi{A+%3HpwKJ^3D=-0qg#+|r;~@o~*NhrpYUH`{YJ z245Ti7l#-Ze_3NDjOl@17~``xUFHD{Q%aMZ)kUn^MdjH|{)ZmAa$DsW*E1ogx|7i= zzx5&1ysRVi;)kx`wM!Tq^!@yMc9LP*#zQ;F$byaj#`B%>JiWoyeq5lJQ>{b5t3{3M zR4>IgQg=vZsu#Pu^ZkZjn^eAedBlNfI~0c%BE^q_0@(uQWY@{pNw{kWJ_Xm1o)~@# z{ix7NbaOUL0P~vf8U$upCb-bo(cRFUbnxbEBkxhon^+;5ie{t5DClO+W4$0QP@}Qz zSsTPVE&$7fBjQWM=qdNbUg9S4GI8Uu_&u=)ixkqi6~5A?j_w*jqYS$&rQn17ab7d0 zzvih1kyYF?yr;Wgzs?P9RQuswp5A^ol3W*@9Yn6jPBJqF527YCs(~JdL#-P*jEyX&zRG9 zY^ZVKhj#WG<_x9AGF(rX(n_qFQGt4}ME3`A-(!w*m81%kFpjTv3o*BNb(9mfBSO=;|^9Gh~6 z$PYa0fPkBSR<;r2-nxVab3^bUuV+Od2a(f=`lqROOuM zuIXIwc>u*iYObMq=rG!XcA*YzO`?%D&V5TpQ)Io(`@Pl1)tO^4LswK2juVQMie1wW zKQ;0`1xF=&P|pnc;@+XVHaWfbKjPc&zca4K9~`h7@~>bvG4G!EVf&T2&ikvkOzibu zXyl%u4ragjE6)qU8~>G;2jMBF{>tlv@YKKZmY`V>A)SyNqVt6gK?I+cAY4n(*O;kx54E?1)NdBn8r^?jF^>1;6Re(~!X3D5uxildgfA|1!VxE2 z6yi7gCGU2aw{dJVB{rHG8y&Y~9*EoNg}Kf$c=eI%X`mq@n_QhaQ^HA~Rmm}W$(fz) zb*(l8%-N#0Z6SNny^z4RO5goml~;WC7nudx%*y)WsQ=hk+K)GJ zgwJuR+k8|T-^Agc9Y5%uw9D&@@6k2tw|NADb?S;Avp_jm>w8z^+g+^i|z%X`*Ui^1i@_!&RMXDAtz{Mo)opHlSSQofqZzWUTfD<}8N zjx9GsLZ+Tt8n4`$X5^46uO59C_+*x*l`Jv)VL zbBR~Zk$WT=`-!%R_KBdk3d+de@gqp8C|gu4(x?}`PwX~r{~;O|5yd9w0OP^@H1(>* z;#J};Vy^h87^I1F#3kYe@dq(ZQZLn&K&F!X*^CD(C7UE)O^o>x5HC3=xhZ)lc_H~M z>6PH&B>hMA9FHW54eSj2!_d*2p5~Eo9E|mO_+!E^{8!qWdiXuu1Dl-F{xUxebjUGS zL%Kw|TDn!rlg3KHS!u4cRQg$(gZ`2NB!4zZ`-=s#2>EJ4VIhG?6ao^E^T;ja5%Lm2 z5dB9pc~p<2ErGfUQ^mp4)a@OYQLp91NJX6D!?BlNX>g7Llqeb$Cg-*U&QGf(4=7Yo zFb!4i_G?f!8i~fC=_q)F#?qgopHPQ;&^iqw=RSD7*MaCx+(6txJWLc3uM-y)5NnCE z^W1?+20NcUhJjqzoQ$EUMFeBWPQQPHy`Bo!kZZXOj63XcR&#adZs6|V9_EU;me)CD zj2j%2J3+M8pl42Yc+=LPHYdDUYmnT@8E@Vi^vekedg7#7<8%x6%xQ`*q0I@`=0vcT zJK^L`gkMg$UrrQ3hmFAbuoWYAmk(hT&M#09b&z%`+VoPi*`;W2^Gkxef+x|mr##bc zplT-Jm^TSJ1j7O*b7m~GYr}s>cWqdj_zXhSOg!U39TQJUu}nIy=4Nj=-OY`H513&R zO6dyhIMdA$8Fz03w**K0Kht~Z_^4po6lTTlxl9wT7c++)xZtwjo&XlS7PJe%kYJWbF8NQiTtxolnG!5g zi4l3Hn4S_{6Xl7jL@gp=muOU^DK--KeUM|{#SHxWV|D31DgHN8gW=F?zk0+I;^tp- zDr@y7s=)sP==MoYNUlikOF)IBNir&d5e;}ItQenDsR6-0@cc@%2>2j;8WzLg0bC8Y z!rkz1_?6Z#?7QI1|NWJkObeGDke-r)YtrG+gT@Wg57InimA+a%@S$HDp&&MhGvbeg zA^Q<<61j>^(;l8B1$1lP@GrXQan<;R3M6lsTS4` z8HBB|_?iWTUtWv-<%UB9%I{CQy*39QZ$+_GC~P!-^ofpnD}MfAaIS_vQfs7{`t|A$ zS*L4byC)a+v1Y5@MK6iMEEny#CT|+x;7I#AYCT{?SR)H^WTPbg|wD%hm2pRde&eFhx`vfcY`nhJ$AJt-Wz&IByv-o zMn@*ROz3X2tNV_wI_W|^@d3!?*d1M{tYrru$IoD^Xc*QbM%|^hx8Y8A@&z-`5l@tBL`_Rfr;kW72RR4NtVE9 zAsKSBaY%AucrzIgV}-B1duWiIS7?w8e!~(RA#C9d8*wv@GoC1kTAS#hj%)(ut}>$$6k&NqOGeE!OR=xPpB+kE{o zd$%raNaepF8E?^ukxrr^Rk;bm5Y+^N3OQBsfYqaVaiLGkn6BnR8!Wog7MBoYrS<-0~=@Uj0EIFTk+$OwPLb}FAl(dxx!rH5^=fs)y3`N9`Uxl7?L{n64bl| zr(OcTtxw&Q5vk3tIuWB3o-aSxF^OcMmojZk-6fO6H>!&?sykYFSN93IP?$$f&Cz;p z<<&wNXN^)cO%Ldr-*t8XcEhi)Eu)9B_p*<(FSGBl0n9!mIwQI->b0!Mm@xaAPcq>e zG3PH*E57IKpjPC|)Cgs$74hs$QtgAQ;+6(WL6*bU{PWe_1?9FEq|G*8^QqOeyI@*kV1{DJtBN_uw|BPr)6&MTVBLG5ibTal#T~_Cg;XK@q8Rx008E&@ zBkQ13q_{Eq`VqB%^Yu^5A$KXx$_IPo*SNLBnYxM#yX;9lNflk$_t%T?@%67G=ib70m1J>E5sN&?OAckH`smxi)l0|bSiLGg9@F@z3Xh|v8B%R z4Y&s;!gXw?Dx5#7TGKyzVC!$fl^rABuxm}lfT3kkcd4L(fJQzuuwpPGQ zVHO^q*TDS19785Xvc6y-0EPh=8=FsupiemChT!QlfTv;&>;Juf$&^fr3c`9y!5`qf ziqGVKrBKm1WJp#Tx_nq(8frC1!!@onWE+bAx@Ql4e;@{)X7aB`U7{@#Juu1S2gf-l zf;&+WCyLn^N=f|6{=b52g4vg!3&Jr`_bxzuVba6 zFQS1Hlnfkh-`=sKndhq{*5^Mpy0s%K%ZwEjh|o!K7ulw$ zf!pA(FsIsw9vVh^_{wR#{=S|wdFg#RcdtQwx= z>kucTNgoW#KI;GN-!2J94j`wHYY0eIWGbdAf`|;oF{0;4CK2!yTg#fTkLv?#i|9f3QrSvMq81%-Voe}y)Qqz2W*kkcns2No_dD0-(*;^h|9A43Pwe`HaI zIVtPeqvRpIYfl?OhYbh*MhV*uPWtv3T=X3>_};LVYGiwbYMVg|rs3@}Xk3~SM3pH z##reR1ATRiyXQKG4eX24&)elE-_NkaAgLMu>H7dBBxM7r<93Xc28I%nlG^kg4^q6h z(*-Z>ibfh3xG#2fywbrkkSo-lieXZ7RBmslt0iq)sJ@7T1Lqc2tYckUxD{ICc7z4Z zP-0S1B$p@>BZ_3?nyjiGr@zyNaYpY|%Bj>_3#RJVMXzaKzF(Q)z?}Y@bz8Cs%!B;q zLC`#CuJt@<`aDQQO7@60IlRrs&rW?4Q@k_#n(HAAbAK+o|KhoN2D|^(&AQYFeix_B zYgo8sY_ZI~=l1a+_}7v{$Ab{Or?GW}ZJwbcn1jd7gYpwh0v;t@VQqyTts@oqZG~R5 z@1^Iie7H)b2yzFt_P1u*mrxogAB?Fa$|N2;KvAVnqbFOkD|a zVEzH@BW^vP;1tZq1@k9I3M&Vx+3^KZ`WI_^1s%sE+1qPw<}IMCaIj%I+pg!WT7a{^ z6||ALlX--xRErie@o(4Lzh+h+?OstM{EK~oNed4K=I>yw6dz=rW&ttl0jrwT%IapB zu(jB;*?`V=Wc&IB^R}$>h}+3N!UoCgOm-prDf{7x&aE}V-&;YAP(QlW+v zPe?n6Gz16}S0H8-&u_aC5|WCHNgIoi5Xv4((hPE0xXT(8;{zN+Lik`P!XSQG$04k^ z*iOSnh#*;cOk+{ik3OGMB=x{9;|FI=^KGhm+KYx1C}CFbRCHV7xco?L%C9|21Ow`2 z9;^PsTV&M5K?;8Vwtq7h@d``4_58+9V%6F&Z@o-@RVX7~{v~Fi|I?Ug-Jdy#P06#X z2rX?BeTKU$Oa=`Gl~eLP-TkjMIR?E1qdqmfe;>}Q*QA#-xKg@FdQjTiH5~C5XP1<++shmkg+Rf|3DWZCq)8#eTvD^~wQ(X2;By}J;6>L;{0-W4yIfN?eg<<7PIiOlVrRB6&(w1XmS3Xt zSOpJ?>xl1&KZrJz3L?cs_m%MiiU(!mEDvyfiI9>?$)*U?l70AZGL5(jcpDCc1 zf~V`#E$EBrp7hQ1-E>H~Y5MVILzik?eN;EN4;xm`hBmk>wJ_=r0*v09Z*(=TX8SLQ z!V5PLcZ$;^VUHRl@$4nPCVoorWw^g`c+3Q#c4{#1=ej=IqMZm#sd8;6}BPU zl6|WF5$94(J0DSnia-2(B{PHcplSG+jcx|~O@lGU)hgpL=hy_DV=M9Pe7`t(6ky~1 zMSF1Vd|@0Xu_x--34SIq-jJgmiVZN+xxkvcj2p}4a7}bIk0@!_OzkzxQWUSaMLm|a zo$kvx{)#>&h}m6e_ja_q@JI5WuF0d{1n(A2)LpPautRWIAQFJ29&MzY+erb-cPFdyQ*$eqTb`^sn3i~1t?X<0NKwH#t#8q_ zy5^rcTatG=w1?)DOWpMQ6)}Ywu(qYp*rNtgiWR5_<^(ZWCoLL>Yr9 zGnyq+pHJ!72`qQl%oo+%I{9UdtivegVA|o7jQy-TG^58$X(;yACgV?SJ-Rrqv?r)1%0tI5t_PD$dp^zp;kFF#ZSyMB zf6yq)r}kia>oHj8*+PKZabsE~csTN&=vp^Se2C7Z%$>ceQdo1Jb$jSO2yuOczC;l;%Oc75p1B6`|E@dOZ@rgsA$zwih$WsS z=3?fy+7RBS+Pa@Vv2mt}m`nk^!smdxK^aS~fqex9F@LmR?;i9Lu`tuWM)D zrm}ST=Nk|7=ibd{1Q7%~-e&Gajw9f5vkEIR+`jecyJW5smG{#4$^L4paOix0b)zEo|w|HEzXkuMpHh%;Xp5moHbFVVkc(Cy!{xvHZ{y2JX~RuO2}ZcW#H z*v0pRknPEi;q(LaQ}p~`KXh^rz<5|e#AFPG#p_zYsDLe+pT5S(EYpOsthovJ`R~4w zn94QB4O?@z+kh_Kh3ucPhnXVgb!GvxmI+E&4J%PMk-TVofCpGz13(o46#$VBHk`7i$gF zk;z!=ErkT(34R>Gx6ZIe7*ZHeDC8>htXEWGh*O>cf&D=3!UJ4bUPxY6p-?P(AbKr| zP;buIqw+Uj_5YmWJ^L8exp+;Dvl#ZG024-JVhL8k5DafMhKMB(0t9ohHZT*y^$gUI zipb6PmekB|-q=8ZrsS`#iOnN4U4PK{H~&w8uG;B}KLzJr;{N8BS6`{?RjICe_G6cR zijvFk#>o678NAmRn{STu3_a@?YIhd5R6I{o!My*s|3I+`{6f6`(@7BH6`4y|&T$9M z!9MX-4|aMxzvD!+H)oz+_jbaewdmcXGG;au_7v(c-}OCG_NSTp^J`tg#|>XwgQWQ1 zZOL)xZgx%>jpn)BtO}RoZ@J#Aik9O;WQ1@z?nJnp5G}_=%O?){2gff3Wi!rV)BUPI zOt!r~$E7i2eW2@$jyPbY`CjG{NdC0VwzTQTu9iQou<19gea>|pS76mJBf6s!r{?7{ zjrTOFNTa9TW7iiyLYR-5%iYFDuhlA$zkE_+sY9#&)GpYf^KYyDBmXM{WZ7WOK+{(J zd5svI;oJ_WS4=;qyz0fqdh3?Hz9GH>830WK)g`o7y|}IcYQ@t+fL5TVro`XjIR)Qd z$+b(iLoRT@mEldqtdR>5al~S7J@xgi8m|k=n}st6Gg5JPc*|7-^xs}5nqA;j7?Mi$FL2lu=69w%gtb&2 zVvCvE{r7HP%aK=zxA}u_tr$Z~$JExO(YKpbevOzyvlQV+KbkLY?=*K;5QZ&mgXQiw zt2W!>J+S{DTR(w(vn_73Eg{?%7jA2LS#eJRe{*l?@W7V7?T!inyk6|hN1s*6$=k>-5AIEA+uSA>HgmeIu{+bs z<1(vui9s3ma3O8q`KNK$E@j=Vi5<1#l?$zS*ys=sv%X0T{+`==aU zHBhVdZ=d`0bS0ecSN)_QvkLf2%diJwHK(q=;MlWHDHxGXK~yEvBwHj)CBaQy_br1Z zF_Of4t1_u70YQ@M8DYV@Dkb-HRVpF1=*NYxoVK0Pb)8Dqw_y+KjJx-6QB$$Rf~# zzo(%WQN1@x!Q4%+nwwsyZhHA8$vI!zDy*#{O%0*dnN+oapu{gLS3jkNadDnd<&C_Op-=M4CQQ#ZlDEv5 zEt&;E(Va1VcubtALL!wB-sP{EmU>OqqMCX`b*WvR>Y{=&)d^dVN6tRdl<*5JRyoxRP}S6LI@?|6{716av)8BnN5au(R1y~kMla)fk-T;0x@h=55B|>r zsKy4B+3PP}MzFned)VZ?izjYQh5Dd{Y2l_7L}4Iha|&LI!%2n##ZntZChx~XK;9yZ5=m5qE+Z|>p<|&v8Z$+@;p%BbsRK(Mq{(nd< zs6?C5<-^+-9A^ch_gHIC@S1fCqZ`k&X0YQ}%h{jMK?RD_*0J|cV&_9n7HZ2FL|bf* zB4WUKrRNl2`^{f_VS>$c###&mXF|*edcV-gH5UU81+SFCtp%3y7(5KXv(}Ei$C$s` z{6a0N!Isc*!nV*wg)f+&nY~Or3p{ufF~L;! zZ2{Q5tyZv#y=CLD;DTVLs9YdhA^N93e~))t@6t|nv><*^VG{8{I8Q%K)^rX5W6@(=edU3-(tN->b=_Bb&DIx_if-sQ*GN;Ms+PDB? zjX!*!qB@1X--FYLNu@J2QdMT+c*OTAs!(|SL}=0B6=G@kz<&t#YlV@@#u<V|%OB+3_aSctx!A5%RExSdv;{?ZA%j`7I+8Gqfxuh$nXcbijxF4rzFRE~TsU~>M zw^f9tGah2AE=8#4_!N*3kGeZE79mBHI?B7*qoMkJ6awAL&_Wi_>ig6|gW8t&wjt5v zZNvOe4bf&54It5^qQU3oDw^|0{mvKIzubJ$;3K_dQh1*#yieWv>^^nTL$mrSi$@zA zcTS54+dZA(J)NsuASaewQ7UZgXHwK5sA9*8X#=s$R=z@5DG! zy6DE~sb5B2q8y`Nus^eV*?8`BhEIcH^n>E3Vq>$?b?$=FFz9I7RJAyDj2&Rs?&L%* zaC~Zug7XVegIjhQ=4Tq<(0wR&+3gB?A0-~DBAL51&_1KRD8Li-i5A4^6l+Sio2~_e z2}+56%xvO5CZN10u3%O$Gpv~%OnZtO<;H1p#EgIHQErS9J#tGYN0whUKI=MVhi^6I zZ7b&J-`ITV<<`JCm^@2~V_`5B@VYS5BIMj$y2}XaT3(>x4+?^P(s$C2(39zz^g_C2 z2B?Beq8ohP(!bNk=sHX)6OdVEtoA(@;9Ja9+%4g6ncx6-jM>J7xK-S_+%7JIrSHVL zbyDj?z`D9bAuE*z@=|R*@SNbspTIln5 z@j3BL@k8+o@n^A+4e*kDwngS6-u&$L*d>zHk~cVL^*kRdbl-u;#H|?Tt4hTs#AQ!U z2jvC0gsrC5>6_!c&ON@~9t-xR$>W+b_lv(_57}w)=Rr^0?MwgfU88cz0^w0Ot(25> zllusM2_rDb@vnyP6@qtb@f`y27n1+xV+DK3)iDiktzM%^i_y2SZDFI?J*G+6%S%*_ z`733MM4qC}BCuN|6#Y|-)Qg@D-_B@k8f?n%7Y%*U?C?_!!V-|NA-(HHk_$X3h=aOr z^r#M5rxC95)j-(M6ciIODT@c`?Tc;}05mQHiqcHB|JibY1KPGa>J%!5$~rcX3C zTd^JgRJH~;KWp7;3YuGYveRKD2KpF&N{w#>O@k-plOj5{4p#;7M1Yy#%!1~&enmdl z5WU7-f`UKX7A`x2=6ugqkr2SI4q6M`?R%JfXVQfc(kOawj2?)3&i6#D#-mMvNot*o8jc6ko zFJAN1g(i9xbFlGOH|d@ob~tS|3|NjIx%(q3|i0@f7@4#tXk=PO6s{8n*q( zoC;l9c$b^Jy$EN#Bt6$gY-4Gc;X2jyvI9Wv@?E1-k2#GvCpe!-9c5KqPdVmf>PuKJ za<;dA>CS zJqVa1p&F`gS%r#I9mzuvcZS+O3pBFJ>NF#RMD2*+i}hmlKyU_5?qip@fn@{DcfEyt2F_ zyt0BLUfWH1coeGur?}U+c~}K#!79KgSEwm?R`f&ITBw(4CvX+u;x8?u-6mb3 z|7j%-FwRXi-I#MKO_*C8sh4>(3y`y(^KVJy*h5QJ;SHlK@cy=rh$^xbxro+@u80nZ zDwZ@Yxt1v^6g?Ha6@g88J)#K_Nz5ux?6FDFHNNI*1VI_AcUx8ah(U;Wk2pzuNqkrQ zMBFHri-m*YBj4ZWo$0_g(IoZ~+!kn4)S$alM8W>fmpkh|pHtz=?50OBo9U;S>KN7a@3?Fi<5U;pvER>iN(3#xQ~StJ zDbFP;8bsWa{VD#kY~rqx@!&HjRTGt~8K-D|>rC89>UM4uR-Cgd`K~ss0BSKcG&Q1=qro4z;>$ApJZLJR#_6~HcV@LQlY{1DQd)d$&qQCkj{yl%MspFFP zDxg!QilNoYB*drmQYJK&VyydME!Ku9>u0k+7{Qw<+P;@2)IH`T%8XEY`nnh{T?|GS!{}j- zOnulM!*>fh=0{Vay?3msAY%)|vZ|?t3n1VA?HU=5B@8Gh<B%r@Gm$3CQF-{oyX?uy{`FC}w!Xw&>81X)G%bHwUN4@}+BQYW-GjKYuo_#of7YTsjuSurqENXoeXE zZCa1ikn12_^9>qgI43>kZK}&h=w_`5Lww26ix|5PEpPcOl*$a^N6AJpRtrETL~1r2ig;( z60>KF&;TPdIbT!Z_8*{JWTV*uyn|etwPXn(^VehgQ)Y8R`B} zwzW&$aE^@u&Ze1cC^(oE!%AG;^G@gfXCFRRkK;2TOZ{(Vr5-Xn{bwH7*feR~hd;3t zEF2r?vCY{F*_$c5DQ74>H&Ym6f3nN|=SF8@ftXByAKiA@W^=usF@!1QW$H5;Lnpqd z{ZAuLee7jU8FsS^ww^)ISO-BSgk&3UYME21vs#5Wi(P>aEOR>GyK#M$vk>dO>`8l4 z*tYkWUnh=Bpbyc@xX%M+D^Ae+xt=PALsA)pbIhA72+Q|HbAsBvOG{!gZ&7hv)g=z~ zR5gN*0!-7dp8m|H)pS`Eb^Zl=wS9`bPgVVwg0Ps9sf)=n*=c znEe|h-3-6?C;fHjz;UP&Yi{mXLc;yq0*NUjz?9+dV#;8cGK}a9bwSNEtmt$P&i77@ zIPGRo8Zs0b92OV~BGEw&9bS?L*p@>qAvO@tM2z4eNEWG-@DU)FbJwmG+`Bl9a-x`& z2F@1gWL+&9MSh8aB%ZQe0DNR?^8z~js~%F6v}i8{JP?hD)R;VrtHtHgvviphSfeV) zM>+?6CS8pbOL<7|KZ1Z<>byI2pJVhoCQ+Tg;v6ncNWJAQ%V~Tx9wkEuA9pKv zC1~R`Y@~d6y;pO?G#r>^Oyd1qO%|$yOJ*3oIS1o6o088{ahK`$Xn>d*Z(gjo$-vWR zIjzTZnJM7-{G{*oUXHQaqjTI$jhFOl^|;XX6zs{vVOZrXFc^fI6!pY713)*v7~Sm*X?9jk7JG>!Qe1q0e>7)^$czLeJ^~Qb6%?u*Fp;>zIG3^WAmdOqf0` zzF>v#1g({AV8iqQ!Ls!pzCdj|;3)5+?_nk}FEM3IrzgybP*yv0h^abzI}08SgrnfK zt0$2n)dj(jPnheqb5PXfb5CGUpW^4*7`!k>Cku)hh4E})B%Lp{W-rO;<3QP?{17SF zBTbTCl16e%xOvFTHfRrEi&h|UB5UM^=orF5c8MT`XoE;k{1AD8eEu}U)&q6j7aYpN zf_Ty0)IFiW(Ofn+I9r90u2CgA_NEOn8bRo8uMZJ*O z*H3t|qP$<#x)Te%NVB!#4%%nX#)f9;F)*lyIyShegKThiV3q+W^ffbBNANWKX7UNo z*ZW8S6SOFbfz2oUHN7L#x(L}b!A}LM&_zvA2lODi0exvpQqfUTv+8She-r-|YfC0( znEq=$CJG4Ze~42#Uh?LrmRfy7`4oxKr8G^ zJFJ*?!&X?C_ip@+V+P+W_1|q;>A!!02XiA6?3X|DU%YIm?JxfU{z0$5(WU&LoTYnB zu-u3$`_K4i3z9y$e{esZeaF$`#^Z27_@s@a({3d?S?RGtf3tmiAy>yMK*!5P$BXe@ z$IED@m%8vQR_HN5&HQ6Nb+e!OGaaf2YWv=BL8OzP#;fTbAct4nOL&OBm>`r|YD|z? zV=)8K^r?pE z5Aj5#=0~exN zcU!(vd|CHSY;+pW?|fn0flGB*Y=rzHN!405y}yStLHWg$vFz#4&c3E2F|1wmoWH`_ zDbnAS9y@s@=y|~hv^O=u2~~B6rQI&WaqMC3erK$l2Hat!P#O@hSF$X67%f zzFu%!zDRmmH#0xD8aUV8DTsI$T=9(Zky0aW6Ki}G&zDSzkB+inY@k;(d$!UpL z^11r!F%>*rnZNPGE2;BvW(%%Met*#auS6TBz)F)5@Q1_T{qRZnE#9wDrgBK0_W*to z`@minYeeo&{4s0jz_Scfs15!DFK7f0JAL%X7p-0#lIso}Y>y`cGJ09}kbL>T?2&|a z=Ra4)n6E>r7HyHvL`J2qw5-pi$_y3%JMJLLzY)vXaQ>3u9Yymx&2H&`Xfgh_cxWdE z7VLR6*P8UOtHZqC4C*sKNKkp_6;EgY3+{%r$s<(T6%X(S)P|blRVR$Noaogj$ltJw z&?m@4czh@DCrln(BMjkjL-^>OA5MpsRoP=S@aewnI~mfU=u=cfT+AB%IA5T-iBxMt zw%ud97~i;U{GjSH|G>Rbzp%q(WerY#p?#RV^B0IruCd`C`38LtJ)@dDrgZ_vv02%X=?+cwxTc69rTif4s*Z-1@fn zdg^{(DEmKVn>idhqsq;7x_9xcI>g9zx)rNhmb$?8;#F#?oXwg8jAv0ROo4j>5CCWQN2rlo{d`+n=v=>wiYNbt(wl~pn>r_wV> zD+>Gw^9|NLunkqB-b&CL45Cfwtjx%*f6%E!e@U3c6zrwrExi}v_WI%nnYVB>;p+7* z@iE7$GZvvnw$S8q&wL$@$=8J} zMMG7wg{oo;Rj?+6qS!)LYzbWu4OI|<+#UFxxp%(#{#crK#&H~hcRzbQt02WusEjB{ z)Q>3CA4$|$6e|A$tnEobIfg`9Y1V+}q<2)YgJ0Yl?wBozlf z<50l9!$HfyF?W*6v2|FgYG-u%q5T-$st}>1Xb8qglsB6xqmD|d@GU_qxy;veMO!+cr&$XE6tWQy2rgV zBTsnY_bmEYcnp6IZ|QdI?$?47dAi5T<~v5Gmo`mMFGV_ZUzspYbnxPi5p>5DBE z2(XqW_*PIq|5&DJkpw@4_w_P&@-uhZh>XQJ#$r4h)d)Kq*OO>O#4#UIV*Mer3w4nY z>Bb=J%~ri467edV+h*t4q9Fy_Kg?aVMtYWejk|@sgBIKZ4%&Ktd1x8@ZQ-X(q3nd0cqsF%!*m9wc1p!jwFLDpj zz7St&o87VBP6Vlouv#>iuIqM^NFTALn|?9&@shK1vbDNqa`V{Xw5mEKy_5c%uEYR~;Cf^IzO7*M?nrgHhw&PMLW@+552A4u9*AcgkJptD z;KAYmz@-0^48Cb1WV7pk$~5vb4k5-5stW>MX-%NG81OkDQr(=$)))-1ASs1Js)HTG zwM)-w1ek`s!DgPrG5yb6)|XG$U}VE7lsa-7>mch4tBRG)5)=IHsJ>!-V)e78S>V(* z=%Uz#Tu`wG)n6DgkLka~>koP){ndP!^z?W~JS39$#>bY1mYuD9j7xl!+{THWZ-OXY z$q%fEbAFakOQzu6@vAKq+E)^GuO=9_mPwa0|c-A4Qg6IAemtV=iFX=8Edh9~_u_1O0E`SdIFsiknSeo#`? zcTkdeP~y31B_#Jo5nHX*EytaF38Ac@u!w_@;_FYFTDxLK(ya3`HpJfVnYSd}o^H3s zT+!1mxMwh}f5?I+I2}SRm#3?gdmJd;_6oNGjt=q-@3nXG9YOiWw8J9?5`G}`qceuj zm-VfB5VYFrQBYYi;0Hm%Ey$R&Ip`nJP?P)#@tE|6 zRL5cqISBIYg8MhUIjhM3u5q~sSla;RQ3HB+5=-A`0Anh9U1;9&@m^^b0&deGy995t zEO?d0Q7D~WLr4S3j@lq*rCZ(cO39wKCLqq!->JuVA2~gjJh;PDbRG$#hCk&aRQW*o5JnnCTXLwZMJin^a-pFl9b1FFYP0*;Z zgH|W4henNUD=f`~nHpc2)#^?MQV%7wIs_bO(^$GYMh~9j9fJIjU-k3+l#VE%wOg@CszjTZbTli z=DF~;@(%EhYgN|8X#QxQl>40!l+AhW`F}l46?&lwOVndHtROk7(%GunIH|dD2>e{U zQ8v%Wa&&jcn$hL@Kia|7;l2)g{cEzVdOzB0hHs52jdZ-7h$XSF=p&HwHaQyIB8$8$0AU&u7=o-a6+i{53VHzqW-CzMYdnyKaW#ok4 zy>}$xtfJz-SQG*nFZhlZ*$m)L@0h>r;aNqf`W<6Cj5_*$mwQepn)cSED(54>?0|4odR9845tB;lr3|Nj!U;!Bdkp3Aq#%H_ zO3sWSBLyVeuepX!xhP9(`XG|2b~Je8fW6Nj)PCxbq056n)1K>~;c$N_lUg~bY5&Fn zch6;sL;XgnEb6kq2IY$1mLGL7piUheE&auYS1YVDHW9lY`>Alv`ebYlHmY=vE3K|t z49LBo2`e$OX!*4RGGctKnRRY{5*w^tuN7$8`_HvQ zGK6Cc$$W0G{vaxSqw?Obxx|P(kGVl7hJkg&p1|!#E)V_+hz|Q1cz+1QuqxpLFN||^ zEU@$hk7+ux5v?ouq&~NgNVlc~7y1SI0s5yxt-~qwTzV-M3R-jp(BJyT{hM2p2hFPR z+fJ`!X)`({{gA1}W~<$T;#Lz2TXVk^gC2kSYnGzYzNi{LPN@OGdfe)vSXT7k*b~F( z^gV$%N3918K7$phu=G+r7fQGuoQk|lTE=_8 zA|yHyJd@*Q-sLxA)f8uRTf*{u5b?kRbk)!BuUg=~Me19v@g&HW){2$3m2geQfg@RJsTAw-=NB2Eg`#6+=*b!(D+Q_4p1j!*X&9~GOPZH)~V zq+I=$bYI*fSl|NUN}t5Zjp~2%WbojCx7ii&l`MZX!;nHCG4?QyGtM(^Fc{nl2FT*haaO=B za5U4OV$4%}I?&RZ8i3H&SD0^r3E)CW!e0~n1u1pSQn_r{egPz3u=2DX7bgcTR`e-D zv|H*86VwGGR;ZbNBk><1NDply-48L-ml4HFZHSoFbZBM)mV-x7e_3E2N1cb}J8-zef&T#A>?L7OEz7YR|9&8nb@jp4&$l3`K>LoP$MkFP`W|_l~+1~&7^w7c>{3SfN zga41xl^b2UgV_pxr^WN1o3-k2l+{|NPFHV7bB_HaQcz$UI|~ZMj2!LQdjjW^-=) zDd7jm%NJLz(OU9Xm1GnKn~r% zae&ZmI5a7m89y0z>722Jxs@W60%$M{88$EoV>^S8YO&}{6eErCcHQ}}2b}sx&=& zH`=|^h6Hcj+m+zZLMl~G)2s6gcq@6XJf&?sxm^|ME3hzNH)Qf&6!8!gxD@}GxfF79 zcTXGs>)m$0v{}Cr{i69e9W{0Pk{i20tAo`Dy7cEuh48_yL$Bv-qe~x{&76=&PAH3d z_$iitx8Gw$dLk>4lL%bcDjGQ;I{nsI%}K6H@PSjyoP<}K)nz-h!KGosvCrIDicwu` zAU0nqb`@_E9~7gIE&~<@b#vk`8RTMCCN3_LFpvJ) zF#tV4z3?=hO+o8`74X=qui-9+lGB6SdaYB2 zPpcSDgfsbJPpZwI2=nh5K6qSWm_dF#sacB)CnNph0AaPQf|ww8n|A5-dk^skh+d$B zc*=W7JU~Q@5vz4A^b6L5Ed%^W1bCAHW3GJ*v_;Tun(|^PuFSyCoc`q9vO@E|y-7N& z35x6W(ZErq)tvKoFYBK9j9!`)c|OmqCg+(+P0o9ggvbItq@{LKX2uk?^~MxKvJKgB z19|)U-xfB$%e zyrqCcrCV5d572FW{LFj2wHX^fEIc1gIe*Rk?Pi6Ol-Lkg1Ga6DgZDEV)kC#0PE7lq zt=IgC2d^>&ff@IJ=Wz<0 z=VE61`l4GrXm(v+^fVNCkBKtng(7&NsHdTbr=j$}zs!lypIqw+r(V}PYR3lpw9cY@F9K=t*sF%;;(i@SHmnxptmB$T!HGsFOf*EFm+D@kU{^~N! zX;_{I+;{!R*2ps^>g0_!8s>c;);G(Wj!jS_z6?o=Q_syVMqSElD9A?Kb0kC}|AarR zr$=&AQw?u@=PkcYA?(BP*E4900DrSsv$nJ+2Y+mSB82>jQTCAf_Jq_Rzr)c2^HQ5z z?7bAj`$GRnTxm{eZX^y-kPlWqczB@ZX>PuxFgJfC@1wt0+My)BLrI&u_TF(OOt7Q1 zcnKbR{SSq+2!ufYgMnrm?5s4pv4^aPb96#f+F&GHbcg-$Msw9)cH!@RvmuF{YlSfE z3v|oIW&c@m-LbosDDi?&G_T86EndT}4)CziT%9g;QR6k7>)78@-UyQV!tlBI$@m<+ zT;Dp6MEQZA(rkIJMOsQ)wam371li@Bj0hc}D$up*ru4ORv_0?3(&Phl93pa;8c5#- zTch%Q*PTD)Rzt75`wxGN4wM;-83L>ge*-^|5y6OO5Gok=7;Et`7W}YlX=bO>-ei~x zRr;2_D+_JB=uVqo`{*}?K8@ll(B(V3x<)`5fuR^c8G(4a_>h<-P8R31Uc(8Bnkw~Q zh_luAC*OuqHvHL0^lBmZ%) z>{pKe%K_A2U%8Hdh<`X~6WVQJw|9k##cKh~MPWhj7amHAB|Dd&3g?y6c4PG$N~ ziu5mOCy7Ct)zy`mWSTLHn!KanFh@dkeE51MB4Sp2yD$@$JBKSuS(LQc(3~5wqA+kP zc3Zo5)Q@PdXl8pqC%%pC9kn2JES?^{V=k=6IsZoHJ~gRn$z6;<2CoN$IO}t1F-wRCavrj76U!d_U6rZd^2c2Z)9rlVvox zD3WVg!G0Xcds|*lYGB@~IJt3z@HXmTo+wN-+LNrnxplYU`;yF}Ce0#@&tbSMQfH#S zmC|2sb9EXi2K3^|&`f&y?6PR8D_=#f3OKgb?nSOGF~$94X640@tIKl2eF!?xJMo9FmIxF zDWkS19JZ7Vfi%?ga9u+>wx?b;BtT^<0wq+9iiXskyPNAI^^x9?Qcg-e?2V>#q@~iA zKd+NmBYjejQ^tW2^5cp>vqEJD3KzOiD3plzfS6eOQ4NXu^~_ziTlQZzGMLRJ_&1>t zw>73!UlrSOl!Ku7*9GjVqfn+I$F=15qYpotMsNX@3m>o-Kfy6+zfa*5!O9hKC-iI; zf|WVKh72}XzKtSSyAw^UlaQ_Y30B}Ev994Pxu?EWzr-rdrkz;zWcAhqIElVfmelfp zT?o@qEP%xWJ-ikEINk?uLjh)|@f`fzajpsv-1sQ1!cR(fyp{bgK9o{P@r!>q-}7YV zl_SQp?{W0=<)rl_KqCc^!bx$YE2O)yRPNt|W3MP%V+LTTd{-zHF}_zYh*R^J8R`*! zyX#cF9>ySoQXEu*He19anT=m5J{B$kPODJBnX$q0Y5jov$v~+`UBf8`y9Ykp4vgRP z$K%2NujCs{$1Ew$Dbt$?sRrZkh+nFBx%~D7)t7p)ZNV-j7B!jr^5;$6TN1k#hb)Uu z$!4c~^tNhNQK=b)MVZZv)}$%PXW@i!_LV#0h{&+-5ul4Vb_ZrV(~(75v5j>5kCJTW zf|C3w;!}hr^d{eHCOJA*IdV=@WNhRP*q+qnpj@ond>Z9R!$T;X>_9DF zUvX7aYy0NP<&|>wH6rs_aKX!{xg7*%*nhT^QH(=#U#W;JleA7j+?wJ z0qJ367W(hy zVah1(D0c(vpi>|V7r}~W!Qg=nnYGkMyq}xiRegv!P>QVjqc(LW1TQ_tyRL0=-_CvW zAcCyRH|N{Kq~~D%G5$He;5z>ye`GwR?taXZb`0g^5>*oFEvUh{sh>604}Q~SDMFgO zMs;;3A;FXOWy6m|BQ-M|WhNr^67<9Z8{~9NiI)?$s!oJA&qZ_w#lKIq%#Y11IoC3wE8BQ*SPp zxx+5+j;EY=enk5ypTO7TTBg}&9^cvG zyJ~cy-(aM=G_ysq&@W)=Pxz=3XasUaf~Scw%D9&3yIPjDfjFwJxXFBT-z~ykJfUKhm>pi7^?z~N%5`WV6ryMk$ zw+ivnKkNTZC;{?_5;m!_^mNkulDzDE()y<)1O@Wx1vo*5ESB;L&Ic=?*w3XZ?N{fg zJP!xG!I#Ov#Hv3}H)k|&=}=zw>f+oS5Gq{5KU-1f4C3B zALc076gnfzP);bY-Lf1TYT=CRKvgPIQN1dl1MHMCq><88X`Zx9irq_$Q9~Jihr_f~~b{Y2iEnFS$PVTtA z7nY)Aqh5Lfi%wLvT7^<8vnd?c-)A*O1hvThXjmk-s*QCWoyN7n zo!lUpN4zTrIEirK-?Uj<2qQMG+A#&|k_tR3DFwcJAM6hyHK zHNef8cF^eP%IZMt$*wD>%Cdhwliv-%f0qMwx&i$&>FS-#BYt;sZ-$oeP6uG#=3xTC z^s~CMFG4?EPN$pxP$uE|?y1}#t%%P@78Qf8h~ZW>woT#9P^;)0VYNuGf)fZI=+Wf( z+hIZHIDC-BFXn$C|01uTs#E6)s}C#57oe(B_ZiL?{bK@k+eR)Py0ig}F_hc04#e8; z1nrqXHNG}UkMd#*H??`g$~1Pb>xFbcO1+f6sF<7XxI@l2dboqi^hnm#JG7)bxjxz9 z+uvo+Zi%l%iqCptekXg=Fb0d0Dx%&+z2PW*YHzz&#ew1;R;V`LmF9@!bT%Z)HkkS?Qgi>&;LAhP{ zDzUP`*4X#;Z-x>JEMhHZt!L3#^LXJbGVfv|VV&S|Q&7VLmScs=CA$rEV{lZbHpuO^ zi0K4DbWL=PvK9N)@)gn5I8y4{*3H%v4yZRDN)SN}0NJs-u@;Gv?uZO(FzZn5DL>q} zqA!61m1Q^BrpT;>p$8m3hsVp}k8%v{aEb3%^3Aw{B@fq&Xrcg-PJYKDyTfIAPbn8u z3Ms7Fj7{v@y~xAEvOH0lNS>SfQzR1s`I5t0>>}T);VB>9F`=Ox z+2y7i33iW_v;>VVUjdt{raOX0+r_T5=NR)y7i1?KZc$EAUDzG)LEcnFLxK5=e5CuN zC#4spTxplIQkrRCe|Y+bbV|BwGmo*6H-4HL!p(AN*gr46lGO(9jlWDJi~%y#I-1z0 z2{zG)0EVk=TyH4Ra4}S&>cV402-KFPdSm68MrjKgF zF1k)vH+>CRg`vaHH}mJobJjd}^XQC_0RI9vZXh>;``}=4Yq38<`$qa+qlcH?It#cB z$;ClR5)G6dpb;}sf`0x3W=kr#NJNo|!_ea*OohyQ)ZeB=>-!r4yHk@K}@U*7U zfK{c%=A^>ezPK-LflH$a(0W+c*sB$u3d%1Chi+Z*2ul%wFlwxeU4%qqV?=+dM?^6d z$g@&=seh@X1T=G7?wlxqr(4h+=w9?abh$nRZdpB!gmV7SFLAo)PdIjvz+tmFNbW(7 z5m(OONS{~CS`*jJcH@3NXHy8l!Y9(%#&!W$;)#9j(HDR0@iHC^(bL93G8i}%wEJ<&RNf) zaRNA=ToBA{_IA7#$RFXv^Cg^ne6SX}azpsT(0{%_#N-hz9o(4CTQtncDnr&jzsr8H}fUh#E54bpA( ziRDHg*Hq7}+{WO}jS?;w5X2hZ@!WCS>q;Y&lGRuXf^S)_$VbLCOEfsmc@9^amkWlo znx}O}2_=(Ag?0~Q=_FFU9f_2n6xy{A3hgNMc7%Gn&0h`cC6A3u;27tpwwjWy)mx%7 z(5qIuA11-5XdaU+D}+s3mfj8PeqLz~mltgn&ykeMd$v?;)ev|5N`}m(m4DYLNdEOi z84M|GtlL_zuuGh)lD%Q9d`FHs>9Da2B;6OSeW>}@{7Hry5eI{1{8kfMLEhcW22$o*1{{2U0 zHx|E24{KK|FWQO>$==P#S})x6n?AN+UTw@t!oO3kxd`O@JnS1pM&B7hhMgcom;_~j z`|AeKp$)DJ+B}g8`cBB-or=>^KQ&Y1Tsw@{se8@m59(*^b=`DOKRti1(_;^j3Ysw@xr*Brj1-7IIT8;==K>f=uv z+8sG%#InvD`y0QIf`|#rwf@kW#9VyDqkwrdeP(@Q#gY>jFv6|FQW@1t{%bk^mSB&i zu0ybun!;jAu$94P#2(9y4yG<_rWI`?@9kmB<;-C7eht5&c{^|E&HJf zT4oOm^8TJuKfA_J|2#nu6ZNotnc}l69x6(-Q~T{p3Cds@;yDSXVUmVP81e$L30bg) zyqS!O-9S@~2?@YZmO{7wMrI<-pw{Hb;LhWtrl}=rm*S^vi4d z7rK09sLn88tYiRJ#x}-S_FtwfmzZ*dj8>n#u;RKU46lGwwG^)C%*hGRnzR630TSze z*vGtF;hPRVG}^^>HSSO6=7gm$vL~j1@>Km)bNk0!7dv7~XKK~u^5v<0S8Z4^;L|0F zKJuz-pD$}a>l91K%47kz%#9acvRYZIwqK}LzSQfQxkd6X9m`?R6)KGrJRkl2{PVIO zteh&}!G$4)T|?={tBTu^w~e)nNs*jXP98_zOvV1p`N@%S)VO__MrrCo%(PM2tV-Po zK`|-|yS}vaL*w%5uEx!^;O=#GVRWThrMZ2K$i+@w2zZs8my0V)U-Ja3S({k4Jg||s zgLjxWvU$~uEM771$7#%yehC_>zN$@4L$gieLg$9$rLpKUUde9BudK48jRl)ZTQPl2 z4IeO%!QuHw5&H&i2edYyY>YJ&22y@Bhg7y=>iHdfp}&G^cjhR6hwb$`qqLlM%!}#& z1>h{n5;u%set-H+JLCCdP_=$x!ve9AiFnPYJrczCGROM94=OSc`oT!nC*COAF?Fo| zDOO!3Nt50BV=t?ct)B_NaR*iIAkiIouJ)c8zZ&zfOl|id^6dDf&wg7!wN`b;hbt$F z4uEHo0~PJ(+iv?QdhSwGM;BSA6N8ZXfk^nxUPcXJU8Z zg+VA?h<@0&revh$J8H0HZl|N7N&mV9-&-&z8^xHoZr~-|BdrYhj&bfk-i=cWu#{u~ zqqHRTq8}FqA?v(R)cNh>{DhE%J7ccJzlSMzdNH51OHV{n#t66p${&gm`v3>3JZcc8 z4R|7qI3xl`A}}Wcoz*l&vt?*#QfSIG%SFz6P@~Y%OWxG=0L4Q*1rZ@Mw37IhD|q&U z*EGe$KC3$8H6P;@V{ekRv|weyrU7+jw*`MKDUM zwZt6$x)hT7QGQD)UzZ|%QwdJh-waPSc32Ao(Hjt`k(DfAt>tQmS61o5HB`aK>n&m{t(FN<4Nf+nZ1}$Nf|JUlARF$IQ@K*RYIC1aB3Z9LsC;wl#!J; z(ncud`%^oom2IhVX`5Ro@Im0oFgBO$McxBFujk1Co-|~YYBJ3zZBKwD*O5Dg_(7hv zL!Jc#YTgGPctN4N(|7Ms>JRtYmVD&td0K(*^675`7+CNfQckzma}~#o zPe+g4-qnP7_JsalFp4I_hyiRF8yQ!=o3XX3yi<-a78E{Kxv+0_5`3>;_EVG126J*2 zLzO^bMC|(NusG+c)O0W&c0Jv;<7iE&Fg%te^iBc8sa~n7p(EV;72YZM9NA?WJ=O3o zKGX9|doa^<|1reS5mo~0Doet8!Sbj-ebKy&HO5lrEam_{iDSnZ-%Ytia&rqjYk4aNvh_YAuhfUUx}B;y-@z( z=a80=NF+Ow$5O#Ak^z&%G7y|2U5^9+L_tJD#6ZMC#6iSEBtV>nI0tbaA`#*O#6<`W zL=r?YL<$5fY6fW#=@6G7E<;>_$bh&CaSh@+#0`j>5L}2%h%5+L^#j>404>P?Q@*^3cxdn=MXO- zU?3C_KvX~oAu1uNAgUp1AYMYef~bXf4eHp!MhS+hLMd$xGrs3a&+xY*OiI%UTQT1nqqM$sAxpZe4p1yy{^Qf>It`y>?|<&01>$f47HIGjXl8P=q?? zGLQ^(?Ta0jIH-n}P<66&?Zpm&@3PdPYvXK2>Tc2z5_m?sN)m-StrwD-NK!FEiUO5d z-KrMG9dol(*RAcXM~9mqQ%b-+84SR|L5T8WgyMUsYenFR0@rncF`dx^Y|i(>g$UDN z@TFr#P+#D>ps!>pdAw(bKN~^)_evLSYg&K6qQ7TSkUV*YhPIoSH1Zp1^P9G4_c{sO zTDZfgF*=&Dt-ud4Vsp&RYL5r&mJeXCtQe`RywmsHPL)-%f>_KR=-HmbVQz)YN%25) zRq;S#@qlLq%+L6-0`cB!o_O3LJoM#3uul=qwAhr7TPlP388h)2Srt16R6?8l-_sNe zhBBp^_&pD+0Y3T(z;%jAHnc`=z6Aw60RU`X#p&3Lm9h zuuk(yf$B(w@GoN?3(vA(!J-g0--T0nM7hRT+|1e}2Dq1d#abNc@hjrh^0rcOokZ-# z*~2-0R#iOi>~qb)j)^5M1U0ZRf`j2AJC<-~qFuI9 ztSz!+@+7<>xQ5R8_qnTEH{m zskirhJDMeLF>UYZ8OG1Feq7V)=*lQonv3zS{6`tJM4?&z{ZJqZyc_0a@5X+ydq2cM zF%&-x!z_v+D7c)@H|A@LRiwN4ggE!nUzy@7{O*5V-j+U=PQH<{rY`^T3?4m4FRwUDOVdH33Rd@8i%A_*&XA3sfH~d{ldA49?_(jc~AL0B$ zldjQi=v}F}3V|9k;@RKPUuSij$je?&24C#%Kyr73O(Bu7TAoP^zF>c00SqEDz{k1! zh&SWY==gijUPaFwq(L$y*^oAnwv!H#SR{~4 z>Iv9Jsj7-{FC+Qew--(a)8u3vjJ`u^!eEx9pOUEpU97p1j{@+ieC_Fm-D=lS5ak}} z!OI5Pj6_6~yF(yx&v}mx`yKqif8VTM$wVrGdZ9V9N85;MOTGK_bgVLSpDPN~Zl@li zvZyZtjV_HF{!4lGLVc)3`$|~5kP4cp-PCca3SEb8Mwiby?A`Rqj1A1Hs*tE;dJY`{ zevw}JjFVJsEmn@x&DVrP0fkg%G%s6`n}`UBvP@OK3{FJbUQHpNVI(oK86}Jf2Kys} zS#;$LV5zeVSSwk;@O30kVM}OT#cOi5PuSh7ixoP`3+|;y3!{wSHT%&_g_=q_(@&+^ zQ>8jSM^BKHqu5GzJM!aAR74&!=S*IbcV&FuNOV%(bUoqfVqDQHL3Ue_LJ?x{U{d7W zpHbJ74x|W1cO1EAUv(0O64WFTY5^rbvNyqyTM~X_v57G9U<%3=iz+UUooIjbXH}IM&;r6eF>` zmv{GF#V1aiBT#%(GkvN*>3W9=Z~<>3amz5kHWJ;R^k%bUBd@78CH%<8xYD%7x{OUS z66Dh5GGMaY^G7j!?nty+ag#}IeC*uZPJVjoO%(f|W@OIFW(O3xc_iAk8Md~+8F=eu z`Je&$&dc)d;|64Y9qK^?;z0wd{c!{0afAQKKdDfccX5H7Ps&pZkyNF>^~{k>B)?PZ zjLs57FD%MaFMeb>CER|alhV*?LKbPYm%S;fd*{j=C^p-c43~mMbs^WPhHfXLb0iPy zHiat;3P8O=E=GL#RC!#fTT9iw2zz@DnTtgGrc-1toW9{Jh0&-I+4V_nyO# zU&#{rH~9sHA^N#`?C+z)-Ab?8`rCafhWkT?d|o?Z?UiA1d!#^%5-C`I;niL>$>X}{ z`3*Na6!WBcI=SCRKN_6yX!`s@9k#Y#b8q&#|3V%1rRPsziu}LALZsEse@sXEeM9-S zFk{#^RJ>_IcOs?0Z_p4dC_+REBGY}(UFnt?I2T~%r%j=q3!WIy8y|dvo`aSRxPtc^ znP~Ku(8-GT=}Bnu&*aOIaZXeHm*%tf$lv4eyPM9FkK7fyx1Fd3Po49fwH*FmDH2go zdW&e->#^L>GtPqJz`^xIf4=+Fsn<=x*XXo+H;xwT`BmROtNW{HLCLpB8TutNZGr1E zN9O`#D{6tU?SsASto>cICl!y~pa_Zf1W*1W%jZ8WdSCIvRm*aQOnL3a;*;f*&_asKhxGYhwlx%0rTDCJ+wTu zQ$PZplsw zt5A79A!5SF=Xg)hjPwk#+Jw*@w2>a=rx4p6jg18((cMAFlvklUqhE$;r|jYYQu3?N zv(fwF>%%zbzR(YG0gJ23ATWX%j*Qk6*^7e=?K2Dwo*@s^OUcEI+PPCzL?>AJ07HfSr=GbRw1iS&7G4ZF(}K%yt%A( zo?jgRyDKPfF5d?mEG!6wn78R$J?irw5{L2;sPOG@{4;xHdGjH}FB%=?E&=DG2}OnfmfgQv3fAA!Wcs{t7L+It!KXmdP$PkQt8-L?X1 zqE|yrqh}){>ZLd?68?#y#)c2O8pl7K=5zS+y&I*P|KY`{_pmcWlys;u%g+h(V}4_3 z+aG+bAEtKi)GLp!;u+nV3<~>aG){B_xNXREHS~2gv|Th@I6xeRyz_#^=Ns5cqgy@H zMjsLvjYfD7N2fK#wy7P)FEZIbLoqD)T4@3UI; z8}!Qb#tyDh!*1=3BBzmWS%kN?m7L#v+!DUp*E>eNwQ2mYa*>61`|{uA@wnw>es67L zvgZI%p{zJBvi7#%IU?iFJBVddt>72B5PmNFvv}T5OdkC7CGXENc#Fs|h7H(WnTfcA zi8$Lt9Quo-{`_seROLgmr2cj?pf^;9(n)Xx$UnvJZtdXTI?PcQyg!fae8f$nE;!0N_;ob(N{ zM4%3kPg`z_?A6b-`c7m-fh=+ye0Xbh-)4x|u)5^@spp_zVutH|$)0EWCSehBRvD8j zWrs+q6r7p7iBfKS0GMVW4qc<(swUDn64|<>=~u|xAaqqa%fj6RdW&XK_Hc${6pDF_ zI*fLsF_94@k5NBc54fC;OGB`o$Ctnjh>_R2Xp&b+BhJ=KzTCP}ui)_A`JP z{URgt&}}=%JuhHkN;{)`6GMS@U<14$ID@J_XOQR&JfF#BV1E#`P7fB&ES+Ge^;Pup z;zYPtg`w6DL#wp`CP3t7PEq+4LQG6*F%vc6-QPBco-qxXHKV8w^g!cYIBgz*UExQC zAs)ZGt}Kr3PJac~|AmcDq+rr9lKc&MlMV!=I(kv|TjrD8ktjGQtyg@$oHCakha=L| zr7&N*ety-LM#mI-5EiU1WKV3u@s*X=?iAspzLyOOxUz zOrH;a${o|r$5_1yqnR9n&-gqKN;L>!>!Z)QmK53 zvNne*W-630X)iDy%~4vg6mUiIZCE%bj&p@`m-CD>_dQ3#K_PEt`Zm2ULUAV^WT_x` zLplmf59_G6-*&K&y8uA@Z6oWmO&xhx8s}D@^7y9~fuh>nuy_ySI^Go*S;ADHTKK@J zWW4-Poc{XIJZOfQb;In3ZkTPkqYp!QF)_TSKR@2)J?6dPsWkTTXR6Yz4Sdh2>$)#o zU@U4>R^=1;mV8+0=FQ*BKf#|l;rU-p2<*CkgFEeC`BJ|6vk!A?rk}USCAPYpWyY@7 z&zr49NSG`*)_vU)+<{>ow>u()>t(eTciQ(2gAHSa9gK-`(QDDH5r*vyoiIDHMc+1w zcZn}OXsv6b4nuaYb2v&TYCh#OMS}o!dW$JGp1^vmt%nPJ>$b}n>~JRLln2PioTDF* z${q1gJR;c!i3tOLb-6KK?u-8wa*)!Yh0oqaXi_fg=HJ))1ow?@JQmPm$!N zr3vO~Y?yWcEZeZqvrT5@uu54kLqA1|Q^hKIUp{g$S4>ifG*Kgwwqlg0$X6X{P!{|Z z&yxbY)I#bY^^&T?yM-hEi|rIlqUiW!Bhoh#&)Wc_Dz+1L_=5E* zj}#}gM!7RsJ;<<^I2?9}5Vlc+<)7zz^t&8$P~Vm!gNLuq?SY5G@boQ{)yf{@1@}lY znT_}&U0!euKG(@Ja}JWDJ<>Cg|G?XR0ltdT_oCr#ok1MZHBgI3t{}@}1;@zBRIr%( z50y-Hqkcd8hc*_Y7mC1WiqzuCK}Mp_G@lwrA@I-edaD$%2Z3Jbi?EwV zO~a~ASkvMEGabl-$1CYsbQeZ7{R92dgNiQ`^tlXOhIMp1LLpiTMMIr`Iw_r@*vIf@ zch3A{%S3eZM=)EZoW&?+R5Ly>dKroGTQ3TEk6mBVn1Y#n_F*t?wg5~|@3&NG!s551 z@aI?>e1+eQJi=~FX-JI_I`M)B8&d!?hj#l*>XExWtUr)kSi)hGI1wBV&L7TE&RGug z>(_?+Y!vJmzKF^f1Iqu(#5OWxEtM^s>vD?!OfSeTnbKaP1q_Rqao2IFTz_sDHOl}IT+|p-NgY}&4jzmZIyVBN4;L#peR8f#m)({<&Z-^1D$!#fF=p;__=9?Tf0*wecx` zpk_Mepr#;-O>aJx0bhvcQ(h=d+ldO{D#Db8{>&0oY@o?kUe$qpX^ z%BZm6+)x$l(~$5XYm}BEI6b^ZC4(pbp3W1OiKoQiv-oGjwO=TymUO9fmGnFgY?1m& zLt*TVcxI05Lc859w)0pgu6LLfaf9ny%gjJ2d1iLEsj)A706SHk{KP!lLo> z@e0OxAel`y=31pV8+QGTrQBF@%&}H(PysN39S;pEcq~beWJPi!QM8VmQVhb~-Q@+q zh+r2GIe(9H)#M(h5vxe8kHo^Q;P0fndyj{kM{ekM`qL11cc2kC?6cit;r`8JI$6#Y z!Ta}TNEZEUIKHKgJWR$=ofl9++kMVDYF(mIN-0Yo(h8FiF8U%|AH3KbR`vJ>Rqj)2 zq*7od4^^4InEnr)3@g-_buDRjQU3Igkt+A9FaZlymPHi_j~RF!E&A&ESmI3uSZhodnuf0S5j4(zl z)Hvibe%0glo~eUp=H}<^vkD=j*wnJmXWMo#yBC&TlY$4*MAl7K0bDmWvAS8~EF~3= z4#$jx{F{_eMJ%Fm06a|MZEs~6+1|=Xw9R`>LLkpRsY@gl35xZLmp4@KfkQp9sK5Aa z+4AC{Cstf1F7V;*`q#E ze9IvoiBs|p zb%~hv><)nLP_fLB;`}k~?>ip$sCIy+J}uEw(JIluqMf1~QKTsI$=(*SJk@FFQs*}T zn%yoOt@u$1{72uN)$?{j_iwMetZ}<>QQZOx<&1BLN-S(xDA<|z{hUTJMHSVcg@Ka| zGBlj++j!r7a`fgf2J?|fQN=WSEWlKWTf{d96)Y48-^ISh{DEMD8YISH(_J8*>EGJq zF9y4|`O8aLmyFUzM%d>D%!k$vt(I+)?V30TS?bRp_6*Kb{0E;twgEp6dk7C$ORfzP z7u>*;@fG-G_%8f3{SO>);F6-MZ#^M#J;8G{c*dEIjF{u(y1^an8yOL7vs*siFISFX zyw2%Y=i)k%4`Ey3vNjBHDWyvQGlx25io{U6F&GFP%!D3_*{FVbMgUcQ8xh%z5$8@D zB3jL{4{2S7H-~>2zVsL~RM@B7OWy2$hu}p!hV^wr23ca{%G!t6YlIKjUM%>ForlNc z<%zXknqx-usep%HO`TrqO_jpN%tWdgl_JBtLrbwd&lVkKI{r$wc>~RZz}&}_1s#N$ zKZLMwng5=kFoLnU?P=)evotqfWpc0n+GWt73{Q@PsKpaBJ3~qnKNu6Z1T1f?UAPiVIFM1p zUN?s)y&SDDK}j8#_(9V;>)AcOqrw7^`QLv>u>z0`KU7!%;#?T4{|Z2`0!H7Y56jz_ zKCghBiSGYl?LDBH*xr8OJxSs#wv%Y_Up43o+1y`TO3TBllM zbx?1cVdSySPp`t_!EMdfp!ZIYO6}s$MN55uep3kt6Tg&xEB?48sO=M|6j}Ztb&Q!? zf;PN!8u?=IllPWje=BNJiRw*3`2y7^!uuAPYOij62{2k=q}r+)J|U7G+^q$U)&euluSsf?{nxrgE@n?f zI$e!#Z~9e{aHx{^d4F!qlKuXgQuXw7Cqa4-njXUngyfu=VjAx2oe-SeSRNLwwg#g# zWPb^WjW7-uSyrcyS&2GYR;OOn4!>QLnr^+We)BYc?fo4azkV%|4{nS7T9S(ECXPAQ zl{+@R!3jy2DIVRsXzb6+l67%UjxpRzkFFOBja6>!e|&&eCie0M?L)hwhKKLQ)1g&r z^FYAy=fATh~ER7k}&-1SaW>$qUpXVK5= zJQv;qT46kCSB|^$&%&hU(dE()pf=y5w5H&Clc(azhuZuNrMDJTyerrY;jh!WJrpV| zk_ZPvjsJ@eB}AP`f36+opC)7jpD&IrS@8MOy`sm$r}kgJ1cW*k?VQ&LH?>a2jq@8n zm<-w&sp?L&QG)_Aibd|PsYx?b_tuT8NvgYf100o~lY4L%O^VP;=iaX?rew^ns-(Fz z)oI-bRlJ?>KEX>8c**;v;ei%$$H7mlk4;q2&g93 zfr&;ctj(WYB59HA+1tNB(+Zj7)Y7h(#e+fy^gtR9r!5V6O;zd(al+M%o)<}mH&jNl z3X1-TT@lGaocuculsDy-w|qM)Y1=66Du4V_JFxWL**U(ON!dytG)%o$^fpqk8q$dh zXb8ZD*hJ`HE(vl$PP}SU- zA>dfm$Q9{(ZXYweF>Xx_(Mo`yga&;S-JZ^)FQA9g75RO3tQ|D}Va}9%m@`GUru55v zr#KFmS}{mk&$vh%2-E+}1tJ^uhx;dLv7@YXn@>)B#sx)q+ zI&$ls{FgKIyje#JZhZG<2Lqcca&fUZHZfm%D%~CBt;)+$9jQe$`#%x^sjK;=7OnjXSjuc>!GfpfhC2a^~G)> zjiE&=!Q9Y~5hoP?ST*!KXGAQo=C|<8?7z=>>AYZ^-@fI=&VNPK(>~-JrAi#{fX_MU zFAp~7z1%E5*m}mQC64u|?nlh=Xd*^eNoDMTVHElzhi1FoV?~v>Zb$B*743=@e2FDx zS?J(=7Xv)J<;S{@f)CjVk+xB+Nl_CpPi)b)1TkW=GI#?x{>oY^+3Y4&ldP0(J)OEi zT>b5|lqW4dDU^PYF5OHy{l*T%OSZ^HJLferQ$OlXG{fMhndo?sg}YBf5BgZ0Y*~Bi$Ve@w;F=|3c}$ zicbaC9&2o{9U16J1x<#S4Q34W73gxTSx5DORGNmF*>~K*raZ;oWAqvr?tU8l&OmMh ziLS&_GHFjqU0BVNIzVD?=i~<@rzNXL?yhRO4h}XAMYBVoO$DEWkCK7i(r)ENsS%MX zolbO0pGd_BOpE%aJWp83Cd+)T>Wo}+RTQ(4RN0aF=$XcXPJ7N{*#bMqV5^-3Y30-n z=K(?t$>HiWV{{IB>uGh+RR_-Pcvzw$S{qwJ3#%E(860(|xiRvLxf%ctY(zdxGPJRv0*EME z*DlcQ+va$gvCVPFB4TU5A6i!dsfCng1?W|@ zDqj)fab3rnk!y%hT>A%KT?o4N;K%VxxUn+>z7=I>RGw+g>od%pVvk#_~F9? zOL-86UG!(-0%0K``4uM=vxPZAy0B8%OQ_N3UDO?{z94Xc&EFN#PT?@8Pa}}B;oe^( zW5U;8yyykGZ)K=}P?uEN4?*|b43%VB$QqU3GS%0NLei0A)6%<+v|BA!pK6!2)q##s z1pO7-`>NM(YW(}~beN;9NEzk zZr!>ug?bd}4vp-E8m=&ho93j5D{{kYm*qho>NV$R*E5z!LN#1wP)c5~>J8CF?OTjO z%BHou`X{z_hJSpS5|5zpmi*S=u8#;{)zJ+Zz^|PnoF0l{)$usapz{btSr-o;#fN!4 z6sIB$@tWbDppkWNF7!=Lf9Zbdz30BpKsD7ih!!UAT_A0FwKyqv*)r^8CyBq=2D#e? z1vuIUnPHA<-q~yI#OPt?(Jo(ov-i}T7oDyg1g=?!>id&(mk&tUXVdM1{z_LuYfw9z zBx9Q-58C4pZ_$Q3=lJnz3niBtu4FR`W2rF*+N#sf^H8*ZB8`19Gv{{7<(zcg9S`?T z`?>#Z!q-bjDDw8i*dr8tAaRUsI5$@(8N75wY?8iOnJ?YcZ01BJ@M11zlIZFoe%zf-ez_^b-TES7c zD1e`W3}G40VA;?p)2F0&sdQJgt>`K5GBCoqJ1KhOs4VLs^YkuF>hbOv3$YgcAUv2v zHB`&&o}me*gVP@@p?}YFyb%|7;Zu}`N)MRGHCMS@2|n~iDHD{(l<8DBDa*)Nxph@h zaZ?wg;?r`y@=whz8mS2B)ein+)=sP=Fe1~VkIuO2KG{MAg=mrp!YAC;Rd?UL4_4R4 zy{#Gu%HpxE_(&bdD4J|BiET!?$Z`yLafP@-8@VDq$akB`+&Wu@}%N5r{RnaVuRyv=;Ve8*HW{|4c&I+i@FbA7H@ zmKi%fuf1dlbNAv@wNEbVkK#;?8fEVYy>K=;!g-GG2McKq*;n`RrSgTrzCaDBb4~E8 zbu**v7COW4L9Sm?;Cr_lOG4K+xQ@@QMR$(R9k#-G&;YG0wRod>99|61k5@s@@DT0i zot&xYtjN&)QX7n`iiYic`)A zFUp}Kx698dlE!8~*z zSga?T27AQM_eV&+N*1gnSMX~|53eO1yq4s@{0!-8iChiWwKXRGo*~1}Ls!cZ$BMie zml_!IVKcO2N%xX2irb?KHb{chQjb~X9Zj^&chYA3VK9q$6U@|iJ}o3^vM9@!@rT7g z&gzmRN?&Ay+P7PJSwHJP>6^PD@_%eBBl)}du^2dvUBlqpODcKzHM51^So}+~wX!N> zsB8UOHA9V(GqgMeLaZE|pF28A<7qDo$vGU#Eu2u}cbn>VLzM!)X6`Tel4V9olsh9| zGYbnMQ*ZWW-Mw=Whil)1Dizz3*Ik;tF(S6aK==99~vK2H}QBi+W zN%fKUqUi=-9m?dx=IFi*lVi^L>S*-FcGE2zqw9ekw!ZXvcXQe9(ywKTb5|g3R2Grn zTed#-?A9aQ=Za4C+&W$TX8Vp}Nbmi*@x3jvXa9?jH*k&jN?JW*%grYIv1YU?>ZS)y!^Z} zi#^UOCO>C`gVT!W)$|tn54t*YKGTlL3J>`@#-F)@dF&Z+hMCKJ(|+ppukb$uZ*=U? zX4J@VLXg5zCisv4f-%RI17>jMbAmWzgYX#V0;g!ph0W;mjZ$BgdL!cp9$Qpq2qC?P zXEp71!0LjM0N~Br4-eb4yqpy-I;{gV352sK-I!Ot~9#v=_mx^sV%`q^6EM;_?o z&ElK!|57{<`SQc~slkmGA0;`GvbenP@T@Wh%^F>RU0f;+NUyRP8i0bcdSUP-e0^psZ0$x75mx%6v~%X+0) z$%{gcD=C*gAhwbD%0v8@${RsHng-(6Mh^GRSH(oq2VM1VtJnmr$VsNw&*BYoyM|-*tK9u zi}d&TsW5!XIUQp=?``qFFZvmggLsvS1} zEs2SCAR{We)o3JV+ZzZa|y%IGk%~WcaQmn$2Ix7}RP4!9^S|rm+9~UOe_6M%L z=QzlcW-D$e9w~+mC&V0W3%rb=Qr(<{s<2X9vW(`2`eKQ+<#70gB&~>U5z|9@Y1uUv{9jA9%dvwY{G_Ts}+bKxZ*G zDpC1$+xfTXxynEC5end%+rd_J@Vpc*!KBU3-H^O7D4gV@qKkM##KNY%$4#P<>V1z| zBZhf&$^0xnDCAf0>-k^!18%N)e`R$=!4?$h9x=fbjMzGRAtNTXmb&|BC?jTz5TQ=n z`{is`RA_u>^pol^2{6j*iju^O_Wp@ZO&qCYDS?5=S~OLJiT)B9V{xJ*qLPwtYEML@ zBvE(nw);HNqh>T3HX%kGgiUbtPEpLqg0Lto0Xv2{Ucl~P3nsUX&?*%&D{jT19cHX3OMz0kI=rjxAUp* z!s?h^UvYRD3#*Nqf4&mdjQ$)UCxk#pG-O~Rua>U~+420h+*n(Y0~2U~My=t|ozy!O@ADqr@yybaQa}E|c;BJHDfobEez*MbW31r##LX?co8pxqRmowxn6CMG zfd0PiJbeuTp3vWoX!*e9AE6sCtxZbl%RHEu+Tgg1a(o!&*n2R_(f`*+vPSx?+RI2g zKGfxqkY=&v6D|}VOaG@p`o_2?FmrUJXd|B*)xH`IMluYJx_3FfcGM&*c0a|kaJ}LT zJ43Be;`cAIL5cFP;veHB(s#*G8-GtY;tV>KGKytQvvK2w@;h}l)oI~eE2rMb0Cp6jeR8=y*GB^imf9fAy3ln<1w{rn~+nP+d@ zrL{xqz{xl(#oR&y>=IV88lQ2MwCdxF{qPp)59xUhX{-(2ag-c{2Uk1Z$E}(IYZ{ju zqT(5N?1j60= zdT3pQJwH|+zz3vtpPYZ1zeq?TVrx&o&?bd9oMq|)+XHrxUE(z_oK)HHp~?nz-K-V= zGiniGGo%Hg-3R}*@6#!yio^z@^b7YQt!XX0e0gC`n!kB8)u#zVm7+Xt9JEWiJtb)z zm@S$wm=|_(f_W;GCa;^33Uu;YcEufOj{nTvC4Cy)va9jxkwa$z1Ab)X`Q4H*-li#gTXPa8v08FY^28amvRgcA^SQQaP@ccEw5;GW zcbVd8aC!dTQn0c@QE=$-ODPGsYs<#SK$y%`cA2k@le+M3zHwLa$op8Hj3cDfY?;Jj zaLD5Na|Vj_66M+rHQg5k_B(~c8J=K?e65_!m(P@6mmjLKrkyBkQu!@MH*cNDPJW`( zN=84Ooknf^Sj#PJ0%N{kjvY|C#lqj>?)XCd z$`1NrJOl5~$1A&s+8}qABstz{YJt9rnZJ52tUXLEQWuOwnly^kmB3VKr<|n}C_|JR zm3x%Ol^s*2@POxpmAWeESpjpXw}-dAYTK;>+FQ05jG>zTm{Ib&wUG*cP|IDZ`&w^> z-e+z-^J(x(T|i^E7)9!7+HNNf5mF+L5SPL}aT{@nu0wvA$>bLbF0Dk zO+vCgYaXxC)pLQeo7&Wit101trYq?P6X-Fmn3I`4%saO`SrfxdToD!f$;-p-Cx7^w zIVx?%j1rJ(V%%@yn&@Wiwyxv=|7kEValPSo%*(><-fS2p$XUPvp_~}bT~0cO$0Mb! zS9YlANHb_ZEHs=5_Pt<@nLS_g9_P?Xh74Q$YT9=)YF-M?s(8PvyVd2_RQ1OX))M3W z#bB-Tm!`&mU4Aun(@VPoQk)ro0$%ez^L8yzHCWNltKau1OVE~ZDMUqc#^E4}_$J)s z6&2&)c`?NZB8y0Xprm%aK;M_e@`Wh{Lf0khgAnE9ISW8%pboY*&>rg)LKW5yY=Ky9 za~#ITaxgkpiMcI4ARk5+EyM@6S&02tza(d|O?3lC+EeBR&gIMvBz##RTO)&`qf5bR zRmW{FjPtanGOUF|?$_JI_x43zcodQn94}DYx@Yi5gesT^)S&W+P>0eZ4X_Mgnow7y1!_Axh&nI=>WW5!fh+A@vj7FCEGEd+IAk)) z#)eYn9MLZw@E0}U>qY{C4j9ll(gYBuU=%O|qX97nFaZmg1HuBZfhDj4#8_YrY`{1` z*n;uE4%h?20dRmLZ~_DuID-iQMj1~6lfe`)6=2g~w_^sF+1){)zy-JhH$Zp*Pv8ya z0wNTIgB4J@MVy1Otx_nX8YpY)LBMQy=@XA71LNL~Ghkp@dzayVxo+!!uA4<(HxIZ& z@X`kmv%wrNAMgPo0KUKv_yb}g2n373Vn8efe*qx~0nHN$ux)>X} zmDc2yEP)@yDzF+55nv5i3)TT*JrIFNumKQJAR250F@V?vHiIpYS4eCF+kqIw!B}jl zpG$z+IbshK&h3MuIU*5)(FdVgjyMdZa!F7oN2EZF+)=2HBaT6F+;K>g|9JwO{MK(QD6m|Em@27-a4_AclD>s8JJ3qSx^4v4U!i;V!p@WrkN1bMO1@uOij<^8TbeEu#j<^D4bl0GSj>v`jxqPUdBd$Z?+zlw2BW^*(+#RTv zBkn<|+yf|+!;7FsuB5$73k-;3hVEg)|MPZN{O`AWMthe!`9}VJVE_9E{|E}~oSoz$dPrmijW7TN0cxgzPWLYz9Uc7y=-~bRSQ?>W*pSaU105v3f9#zC zJil}x{?r42^`(QN?3hcnr2{3Pf>mCKKa^vhqI~N1)TLUZo&=n0hNc?AGik{1^uYk{ zpo-j+OrPcmY_fT0R8djO&S5;S^g~U*OnYHRB3?mT2V(KF4Is=Hg>QPPI zi>9=TrYaYWOmx*VnEFkO4`7|qcSNJpR5RqFsn$g!jA>=n!JA@lVQ(XNq4fc|XbS&b zFu2{Jp?APq6Huc8qJ#lLy0(lMN|3)N(%z+#X-++Fp>maFtr9~m8216FE*r}-{A|Kd z|7NLSr2_@MgbcX}b+9SmG;Jj~KnZ^f)+0gBqaiBpeT&WJ>Vg~%Hka!I?3}4=u4#jo zqotDtP-Sy%L5!O71Wh(~8qi{MH@gCDHg`4{!RFrfZ3LE1O8}kC4Y>;#Y;FY5VRNGz zIPf>O0X;T%7iiUIa}&RHSURNu!|!bF31GzLLdll{n|leEu(|nO@THsYfKhC22{3~v ze+)*mxz%6{Joy_Bc=FG{oXzcO;KP^w1`hGgi2aQx&IqT*8F6%WXWp3OjIjNj5ld%h zWSv#0GctCKGh(ydc?~j-?QVO-8L>O*{1)M6IU^GaoRLWjOJVbUyu11V_xLpQd_35d zhvvFO<)IOm^3aexbV(lSn}^PZ2d;VOv^HSgr1lsxn|h&O_6 z2y`?aG!39{2GHtD1L)%cv}6FiGl1s91Nbj<06j5)roitK2hd#u=(Yhg3LZoZpdkb3 zk^$5g9?TvQ~p0PY8i1OGrrA;9dwLRcRJnxn)bSRyQjMZ&<+ z$&P=)8X*WsCxKuv`7yn@&wI}WbAJlo(HrUOoQqJsSAr7O3r)&f5TVl7KpC`$eS0$S z@dv>p8wik7A%cW}_!%LF=xpoX^FmeqSHe^zcYhhQA(q!u%?CjYp&b;X8ANLdAt*pC zW<*eo*8F{8RI$!C$_-;fQ%0;LEIv%Eiw^4e0RKHf@j=wYVAaxKBqeByB=HlQcCo%4sCWqy%$i6u858?{-*QD<^gG7nrZnjMWGM|CI%g1#eQ(x$D0(^l#u zB;RY=%AKP@Wf&AnAQ5cV^zbe0$e3)s|-s29vDVyvQ7A4Xb5Kig4^jE(A! zuG!3q{)2r1=)t~}A@>}w524!-ums+~3@_@?e8_Q#A!-NK%fldTsByC7cYN~8Kx4rTp3QXh3#ChpkKmvTER{XCK- zzho9?K{4O=2Ij@U4P2T8?%(17^UNv9HA&H-^2i!VtHesQ)6RTovu9?N1l&anMbo5n zrOTzHqtsC;7>=E7keWgNhVfD5QD7qGg)QD*b0cz7&5d2LHHDOPjAHZVc5HccdDQ*V z`X~^DcWfw+I#9FbRYhs?8#4*$k&zMV%jGlV`y_*Sl)NNCPD_(tg!XE-Y=Mo6z7!ac z1`UI9hQdMtCMY}=ixd%xSOwWBFx?7PHICbu)TJgfk!5|FbS~$ky7!fwR-ugY{Wo?c zsmqEAB;EB!hf5sh^BbD>z>JRDe%7sdmVfVDsW=cZ= zLiP%(l*6q8U`*H&Gl=;_5D`U~ZgpUQaT^y}kXx|T#*@yiG4#GdTVwE(pj@{#(q3rs zg&n{K^-*6r9UB%}7&-s67P3cA1KVJL(HVL!Y|E4BV2Qj0G9646c3hZ#%>8<%JW~C* z%9!+K1;?2GJu(H1Z9_79UIJi!8^bEfmVLaOHdwc3-C7a(0jZSJeE=*s^T^A)OsBe+AprQ3&m|q&B!@P zo&CE9XrW`sCC}aB>S*Iva0o}$i(}dy7%_04_E(r#LTh}snXZ2mI-dcK&S!q4V|8~jK7H~h7-LH_J< zSBe%}I@DIf$*;9Kd4f=EMYBBH@^bJ~#gc{X${lv$s%mep3rG}qLW`hrc$ zHw$X3&o;-ky{kF@Sv6S2QESylBhfe!McyM9iX1nH^oUf^c@faemfn!|Ka%d(8})l>&7-VQ>H|4gh3413~$_AD0go*;}k$j~e zku#XbBoml#}QVTJgV?m#2~%J1)MV}+QU7oLA9EeA*szMaG67PF(zz16fn$K z14EQG-WE-P;A(bY$PONm@XqoIcxAks{7Swv|A7bu@|#3%d{s;e`*}}A^RbLuqA09} z4;k+BwB0K`%;y;hq2ZSBOv;D_!cbvzpZ~Et=EBOTt`Iz`v7!29}SRVc>!k#hyy-uny@yECjnD6;F|6N|(v*Vb8Ij{6`gm z=B@;$BVkKIEJjY3%##=kC2BQW3i^2m15X}2zDImqoGod#4k~;U|8nu0-R+=RLLw9< z((%#=CwA_VFko8(jmD)LrF*2urHQgrGN5|ptTBH>Zub$Z>;xGZCkg1D0|Oc*CL8SLt&43wnv(eVrb;YpWm^sXwkna7K31&yUbzBnGH^App>abVQUJQ^kVBPG? zN%jx(GwZQ07#NPe){|OEB@z>PfdtHyOC`bbKax6$HC&?gJ5QA>WFTyVd)eSG7H? zISkEwq^AKa5Q$v;EHw>$MA~wW{x0mxMxZHCmz?%|TIRHu9~8-Q`T#U!6HF?nzRBdUde%fI$Vl?z)0oCs$N;Vi_`|yMNQxk#X|2Ob$t_?x%53LBM=tH!DueO+bcprqtYoB!31 z`^g#jI4BD?mc6MeR^&zB4iA@dew8~8W*BNUtA`gKwcAkZj3 zFKU+Gm#>3>;$jg?4>MAXQ%qNcRdC75F(FoQF2#5l=0~D275O{FWLT%SX0hRJfC)(- z5SW1i2ke(6^^u@3yK$GA$V5aAH@?UP1Af?jk(cy?XpQulNFp7F0V)w%p&li&Jgcbf#=cbZR?EFcPs!QH0V?qxq8 zHt+g9li#VJ;$j0BG&B`&W-1909*2+WAWMOdvi2h+3s((V->ArqB_VYZkAX2t9u! z2PAWuG6^V_d|5Ky@sB^(RVhKFdQxB|y$t95>9QPYI=@nSAA;M`4}2Zj7wLKaIN=fg zJfYY_7ARXSJAxgONo9FgM|arqX7L2P>3*<8PNsTWzN{La!~^yU!U5@P z@i}@U((lM^-hw9w+H}QJQqMxh?)^}|R9Wck)IrcDe$qB_@}do`dQU!nZM5Hx!5k&n z*N*dy3WP~Y^Ed4a-m4ZUp(4O1ZM1AbnpFmCkB97Zcl|USpA7L!4>j)xkZAxUyyt#Fj<^RF^2blSze65 zKlMTLh9FSUY^C_5bEWlcXkqL9(27(;x@VNM@URc<3;Cc;QZ&d4Hn$PGyqP zAYKmbG3pM)YxXi(qqiPdEt&l ze_~AYOeUXcxeF{_A!3r{k7VWf)pwcCm;ff9GpU@R>@$w=AN%`1{2b0rPQVM3;1?WP zGshy>;x|W|H-@)}=gNz05w75E;U&(3>9S{dHo3eK-i15t{zP^MkHQ~xNV_>?k7Nj+ z^r2Xp*;GB$_vpiRzauY|8&A9pS08A`!*}p0Z7b6Gm-%qyD)^+#-TB<76?d_5!s$Zs zJfTpyL6{S|UwBe@Etn1Rg}+y{UHG(iT>kI1e}tzcVy4JR^n%_@C#g`vZS#EEsqE6AK z_@w|^_-Nei*Sh^vn=JdSlofOzW$aSr zpF?nz`i6;>HYv(%<-rJ>ho5b#l`YCaeJ>319HF<47mE5ehKH8+R0V~VfzVRhjygSO zBGl!Mfpv7L0T6cA85EX2H8|Hv?(?z;1l%AV5w>*i7f%hPoEjrwpi#kbrhCw1{yLzu zhQ5PNNzt)6N`G(o^Yv4+sZHKx@sD8E^|3E@nFQb zho8qCWS(Kpswg0aELb#A^rv#uU7sRYXD$NI#_V-#VJ19|@vx5G>0tszyn8%JdFEoy z8qN-mgah1O?)6+EEaSZ5z^)=^1drkFMh0Qda~U_Em+txVHP}0MYE$~$G~Nu+UEVX^ z^x_d(m%RmULtAye=ZP}gho5b|_>1|oDn=b5hB`SYx@*i`T`12)mzF(^UtI)dMfX%a zjlaM@RBRWspnGBryd_>Sg{8A%wi6VgzA%pfQ-pPd+sj#-bR-^|4K$`o#218jgl$&` zf`@YIH`v0MK*6S;uV=+hZ4$)3(^5(tzwO^C8pV7S<6}ROaYbbF0I~@O@7O*3Y)9_Y z2WM5x9xkKcSQ_?}plYE>8;yT?McWbyk3XiWFX&dL3JJ>3W9PBk*b@xA!;}~zaeLW! z?1_vd6^NHg)=4l);gK}SMahF?J5VIiJooc;->IohnpfV@uga&`Lj}|VDV(TQNViD! z6Qwsk+duqle+$y7ezeJlU8O4-V%owkZlw3KG5MuZ{*2!lW$+JQEUV>H^2$5-(X!nz zK|**@Hd|=DC%=3*E*7Q;#RhUx#3w3UAP<#qDYggO{UFkh2YI#TN1RTC+(0V8>bneRC+JHP66Cdi)B4p?66)B z8D;Gc5G=FDd3c&E6u&F8-g8G4p!7}|Rj$B4;N7@wx0aGNTIt;BFhPm^c)M?1|L7Dk z)?X^OV4hVLD7Bu2Ci$KXd#n7WB$VT4bEeMb^w|?UVvUy$X`)Un>gS=Op?j3the*TS z{4~CVxQiNCfh*l(tO&(N{(GW>@WS=!U=6;H9wyu*EWjZNlAcXxRW1IgQ%-+P|E9xH z(npDaJxqR%RlemdWv*kU!%#?@bIe=J4{IDdA{^V8znFs!X+w!N-&i1|FP3T{M$W}j z&)u5MdF%zQ5I$Gmd%Psbw0dp&YsdqjTkm=AnI|N(g4}rvd8}2ulWt;O3NPEm@glFo z6TIE`e(va$j=58qM?{8v8~#W!b7f%ET>f%?B>&V25ALNC+%qsQxgqWTGY>*MH10J} zDmoXRe?0mJ-{R7qn9hf^q>bZ+l(bEx?FH$20VL4&f-&j%rZtjR!gk>wAv!|D6a_?2 z7Ws&lZ{P-rz@<&8w~oiEx?YOCD4GW=>W#RlK3V(T7PthdV(P}2Ew=FSgs{gI$xE?y z*tF{jbI!xOqS1%83@vW=u$kvxVPxvv2nkaHNKdf<$qf2@dJz4zL?%ItB{dSFt|INH zg#B%TDcnvl^_cURAyS%x>~(aA1j)>&()ZF4gOixQCoyDCEo2LRCc0;LR--MQ1Zl&f zg`%r~je}+lkCXPhuS}AK)NO?GhsMh!&J)=?Svd!hf93$jB+Zxaa2AitTPMfl$#OeM(JYDt`{&od64oIG?|CYJt{zgybq%Xt}dTK+$r~jg-RuDe@7d;(-@aZsmx*ax;|3**SA$@aezkX$uLT{)3)Afbi+x=&2ti=wI~o zG=xw8K~FD`@acchQ{p5TMo%Fvga%RN0~DVj{M4?5^_uD(O7pgK%3`s(G%ZIvX9$_5 znF2L7*WxI{(#iHNAYoM!I(5DKAL!J#VHi3c0!`nMs4388bGLyQl_L{|fK!N@-u?$T zg}CY6zkySTn?CsuaC!&4`v*9E4Bq_%oW228Og6V^2t6fn)6KsDM0Y8O<#^}2h!wG9Ch`SM4BzN)L564|TV{5$%jPY=>wogm>Q}j`7Zj z(*b9MdjsOC&RGyry$sJXk;GN+LRhsF0_s7~F@7Z) zFN6nyXgnW{_d?@&X#9oA=rnZE&Rtjt@ z1s0V8)6bOx-AaLGrGN(9L{J>+4PjO)-*MmHIO_<&$_YzM=L=AyW;J8yxS4+MV)Pevlu(rAh_ayAD^ zh9GBl-uSC5VQc?B3pI_MPDDfG3PFdMKmw3y0gqdNM=3oCM4j&sqsy`2O`h3E$juU zpH?fyM=V2A&Es@qN#ZIWgEr(AT1g~4tecsu6^ZS_SVysQ*ez_2q+ti;+osEz;7?3J z&{mm1VtY8~_%m6O1Vro~fZIcJ`4!0nNtL8YGQeo=^C7c>SD|Xj&PgMo10h#xXP)4b zy4(Oj>{jpcs(WE)#O9^jrEASq%eJuTW#^?-z$!15)=Ar>zoc5(oq2{?psK`N<}4d- zDpbgPrYa&2#;LH6M;Tp=cVG$a9hH>7L2M6>r`U0a?Zw$AWdHQ(r*^Vmv8Yxu=m1n-| zp4}4uH7>lZn;0@OhHH{=$R2rq(%hS2J-Aw$-Y*|(vUMvY(}v~YY;%r)i1{1lCqn*) z`A2J2>%-RV!jj`w`m9dF@Q!-@XZmF8_NvZ3L^J3agIcSjN*Q5}G%)HJ#+F&;-VAN5 zam>aE7Pi<1BEH9QyFPYp*!w_7&^11R@*7<4B8kqc2NM~)4fA|cOwk0RqnSxnjoKb! zLnkX|wkkToqSD+;=LLt)t{I0sW`R>3{r1m7b{hniUbFfXYCUxvRX$doahiwj_5yc1 zeW+@J(%z%4Dz!aG10nuS+#9*5Wc80@%sBe3nFq!LfvF+&Mu)crW52R*8S|<#om)+s z`4IChP?VI_tHI{LB58!QPpJr+;{k1q{XN(O3_2ke6Ke?M8W@Qt_Zav>gAJmXs38vX z)N6TV^idkB-!@(IokXwaK{-r^>;@edj+IkI$->w4s?YR(`bZ|r%)lCYRm%PB`2qf# zF8XSpe3<6^b!L5T9Z}hlsJuTOWxv?_WIBpJ!OnhSkg0!h|co77Bm@V%| z1#tTN_*<=pxa7CKo!Ms#MmYJYhKxuBfyF>$&!C^X{#Jk95RJp!*Xt3Rc0cM~wCepR z+#*!+!+h&umKIkck+@FVeTq++v&X4hKhtxGlcR9TN9e%FTPGAh5ki2>iM3N*^p!U_ zQ@v`KwqSoGS7x=RR1VqVFnvATodV7nukf6X&BKJ)21qYY#lU&26eE+M6MkkTCHFkZ z>{KDs9PATGa!H`Ewqe_GyvUc?mWCjQ-Lwk>OWRW~xs54w>UP=dQP^nyBy(-S<1E$3 z=3t#%+v!Q>@q#TkYqQSWQAz;W>$8%sk@`q~<#wGBNfY9vgEKWqT=S9i&8d;#d25%H zCNq@T$fn8W%9hJmk+NN~qcRfWqQn#>_W-D1lzo-KWV`&k1r^m`Bcr$e4bL<>2!5O^XxWot|szxvAjm!D*q{;sTieT*el*C7brp%TALL6 z6ekq-UNp~*hr3eUPjv!dzVlf36zsbK;JUaaJ_!fj_!4|Az7tnp;?-g7FQR}e_ygQd zvdHz&kD$VXKadtmrVn!P$0fI*8@F9QsWzGe5zK#EPu-cX!_;;XQD*1?Govk3SJUAT z$Vw%hK))$ZGmZ@osgeh@y@|dh#9AV27}VYVWyBRLxL2P2nA`r#ddn(yyR6U1-klCd zvW8TrjCe(~6A&&NL1)sP=x+1?`brfO7BKdA;qIg-(KEH$k2M|%XA#3dwHnGs^Mfpr z7Wdmo;-pJ%;ON9#Zl@<|>$-58oKfeU`JkCMRmX)p((U`?+0Od2!ud3L-zkt>}PS$ZJ? zUI>r2k@qcy&kbx2ddMq&0C58Dm1Li94U5AVm^Phyh?=nt?etSR=BQBL=M_Z7iwgGjya zd5E5I1Q&Z7{qhOZqrJCVbCf*JL1xp1UiB*Hwwzgcs+>I;lqcu*go^8OMutc-41;nc zCc#VcRX&k1Na0k_3SF&n74R)}(WQs_K_F8*Q}g0QZ~W@g^FPjHDzC>Qk>Z@9`*ZV9dSdbI1Gymv=klCC}t-onnFLwxzl|$&~-m2QPQGY}vXnG*Cy7QKbFb#?|xvIco_BrN_|s($nde>G$ayoty<=J5O|-8IsPs z%)38<$(%0G7_q>`FGyw0hoy{#hFce!CN&#v4n#mjFf(LKXq+lDCO|Kx#v+AV43&SeK4t0X)?8-I^NE6;Y;`_5=vmM(vH=)eh4Bj;!NPrf+%aYrYXOd@RggjOz zw*OQuXLqU#FaSmPXCIr(?s__<6WFnqqi%#50LJ~ij?u+GQe5vp?bz_(bsJC@NGrb; zmQatYp6RIz?o@&^)dPhUkC`JV9fd@}-l~{bV{|V?k)wDyX!KByBR#mPW3PIIsnq}Bjsbm z(~h2o*4VU~j}ppJ$G~2{yT=W783A6RmmUi?^@P ze-F!F9rc874Wt=r;Q4Wtdbc`BeMbEWS{r(c@F%IHJavT{Ylsi1yHM~4;?ag^NvJvf zI_g2MMWLvsOFu>*pcT+H$i`$_-HCd$N5iUYF&U$C;$wA;;jTz7BG2rD2^z(E)FP`^}bBRa6 z<$C3AWs>rYaz2L(bv)2{b3ebgC_7?E>6(1WeQ9!&+0)YXMuk-N%`oa=8pdh= zvzZ%EQM!(@yY8FtM+*560o{3|B0B;sh|7x1tniSOmS;z7kMlVIu0`%jdZ+rS(nj8M zns_Y4v{w9N+ZNs~#XmmH_m5M4$5K6 z#}gbrF+C;qgjL+x6AVt6$e#n&b0i|a)}_+kqJYdZoa-D=#;N5zml()C@_Yl&p1h*~ zJ9({&5FSx^k9V5)Sg}|sFHwXmdwE2G(bh4uwOtPQ^A^q$EE231#OjRi{+CvJ<|=gY zKr6$T4B0iAQugB9!TaF9)AR|GT+7l7z{1*pQ^OTk6)=H82~3oE$b4lzVyhfL5|wz>vQWk9OmI^LsKQhUXC`{uiQUadOH}7o zg(~pkTvY!E0UZONCrkn}yBF8b$1g)RA^Q<*o)BQ2l`-lZvV-~&d6N1o8SGX2s|(39 zXfpD0+I4lAn*CPUeY;OhLdT-pHcxa$wP55QnsBDAYDOY@8qI}c5NEbqVF0-ie%$`0 z(3!Eg-oarB`7cBU9H6Dq2(&cT6xv;uKCO)f1klxVk!8b4VJ+ccxY!BRw9{d3%iZ47 zF!G!0)-97pOmhimqAJ$`Y|`@_z3$AqfNFX({WBd5(#fopXc~8M{p1iAhP zZEiJp>~xtsc8r*hV|AMiO)vXb5kNctRRrb;N1ehHfviq1Qpb={Q|mc{WK0lPIi%Oo zqr*?85YqHW8nt@3^OSRx7K1|deRb0=Cg$YbG&mTQblEZk&OYGLYUm|3{rDz7keve8p8!yFRF94$1e zO&u+2rsHOqcmJ?xoHF0yk1ZB!_W?o?mjb&U0(fPGbLvlBNb>xSq6J@+Es^m4rE}AaCk3ZE4zQVRdcc>id?qG*L^u} z;bZc_M{o*RBgqn~0yKvS-9ugpBj((RzuD}qrm$Zzp6%<@i9h$#sk2vTY#c)a|FtTf z5;nR#OCE zM=gO(!oiL)LV??ygebS*#6B~FBA6heQ51pKwoj5&o3V=`isMckD2%+FM6)sS(Wpw9tmCx93~8WcQu@o$aOC;ggv_2E?@0QyW3L!VMPA} zValQaQJ83t2>aL`hC}kEA4K?v$x=$ytxOV-;MlWtj3nnU5|WX0&M}=|7k6t!j6Px| zIK-1|KLm`5ADG|DTv=F}^~QXavd@ftEAv2M*p14pqqk`G4EU_cst)M*P0H77GO* z&7<);mB3atLm=bTB9*)!h=OOL2BQS;c&$i?`YDpAW(j-*vy(=TN!j4ywkS?;LO{GI z7}A}RBFm9EObG7X+4k?Lc`O?&bAKzPkTga=DRU5ElxX0fa90E>HYg?{bcBOUodTA1 zJ6nqJj})&nS6cRG@~j3-j?76s_ha~s0kgc${G6opC_C2=>Ryvz042_-+DweM(H9Zk znA_6CeQ*(=KV$46!b%gGy))j@`5PusR3gP{ZB>#z<>HXH+ErCK&l=OIqEI0DV^sWw zb`yP!zCpjCfLul;Taul~USx=CfgA?lVA|ro!a+iwWqv`!jaf_v|6JNV`LzbjEW61m z(V;E94OTc1+?F%vP>CF0y%i30H$e7W%bejI4Sm^}v?AIsn!JhDMazU(8&kT?x-!D| zne=_n2}f0c9q-z3zDa6u>0#^dvcYH$yiVS+6|VF{LINN|_CdW{XXV0xUKM^tAp9{y z12D8G`<1(c3#%}jt;@Zetsk-%If9&fx$H7hhV@+`4Dm}|xL-F3OxIEH3An2vxD`Qr z1;Afz_i^Q#=YmxAwogNXBZ4Ax(e90-w8JBC3O*hgcFrPoZP>mq&Clrn;kaJ=SyH z47k91D?W05ai+rQ1X2I~!GW~J~kitXEqQS^1(6%%Sd3`ND;)QdIrAFz2z(kK>Hrr{81KH&dZ+ zh0Rd}pa19jPQ^im`SfX56a#k^D#ebD;n^@6=K1YhbYgGE%!9-|?`Itt>n>ry5*4dZ z!AOaEU0J5wUlT{nZXala!S&1xETr7|_XMif>0xeZ${|YG%h1#V?>i%9cmmsEpfk9# zqQQ!q-M*j?WOdA;dZ4~~+3nl=e12Z*0K0zurR%sO=16Tf<;mM&d97voXr2VI=M6RW z4GXwS&2jAa7gq+3D%l$NPu6~3*m25XQo7%VoJ%}{P6^gX1s{2b)qajk!D`0stbWDlGEoEA#oB8nDCMVX>OgD_*) z0Ke%Am-2Klf&E#yT@-RNnA|Ta(T95}x!c0r>vUNu@xl}yv({Pi0|8p$E{ zP;WbDTaU9V8147f)5T4H#Sht4^d5ShCf22YN4If#^S$WP$Xi#D^T#wl|*3*|ea+NbG4AWxp=PgRw3& zb<$ODt`HxS;``8>vF>a#HR58VUL*+Wy(HS!Lyf45EZj9dvU#tLlaKkFWv@oe0{J{X zW)@f=!7?%c<1>#q$UFb$J8j#C3nSG$5C||>5QfIVc9O4xSX6+|6E_q!C7X#}o*%s_ z+(4r&m9))eg1Oj}_~Al|NB+m`O(JB>(S3{@AgE|c7G}Ln3F_Uc*w)jOEI*$WbFnSu zVy=^q?HuTm#ta1Zl3mb05GK)w#9E`X&`-bt#NycXxO;Km*YvC(P25EWY>qX8`R}ak zF0#E6pVoe2y?Obp@I}p&x>CGSL;OhVcJYGBjTZtlpB0-1SGF`@MlV|v@oib!M|O1H zMVONjO4~_0IF_4213wko$^`n9>CZ~OsC?-Z1k~S{h9uLoZB`*eDlyWfT9u91+Q4&g zvuRbcX~2rK7Okb*C3Y4yP)D*D6&fVYBjSPb4p|>D+!xnderarg^k@9RQC2@ z3(_4wJQ<+&VFm574avRRZl?rig6Cq2x; z0i|S=+=_TN9yGd0--bYZ&k96MFF~Y8F?}ZMJbfkWV;AxV8S~Y|*V=9IB9yn#)H(## z#H_Vj1Zy|jFx0NZK zSP(O&LV<~NT=Xoq;SRPhhaOCiq=N+dDLUj|!oiP=JR25NoeWuO-ged^Rxxj;;5=`o z0OYW4upYr6jjt?}rN^=0xC+{4j6h;?zwEoystFNTWopc12eVyJV1iCV=c8QoAI=VR zDlfLIY*zT|)Zo}$^bY!b;94Lu9CY0}u+Wl*P4P|aMNRZ%33$j&%1hjy865i~jvsd* z6a18%J0Bcto`OHMDb6}QfecQOFO$=FhXn|^hkQb2NUNAabDGV;EI)@*5Vh#%@4;x; zbiSJpnWs78gPe5ERnD9XZ&Sd6oCeMZjHTWQJ;t;87nDM=+2S!DhT-gvUA@jwueiO#Y&9Wt@Cnj zx5Y(t4$aHKY$$NtmwPiI;mXQ)jd2}`mk3+lgK7AQ?FAhZI$ZIE>gBkJ?ci<4y$_Q+ zI=dFhR?A=+r)2x6a%4ATJ}9OWJO5DCYau3YzHeJ#xUG{NeOEd6{5UpyabBkOWwy&t z9l}4Wo5pUe)dns-*!WO(KQY>@NaG2SB#Fro z`=cY>H8%T16rL2z$uvTLmc|DFGlTR#8^gvp2gA-d9H}=Jbl}DM?S!iK7#i((2mY!) z_sG~UgaQ-I9$Vdkc4HJ^rxC0?`(i-8!&0|AW>q_fLpz@Du-6T&@Vvzo zd;k47_`vQB{WZJEE`T0JSD&4oL=VS$H*Id;Fa`9KnBq)1bB}kC*J!*EA+yX_fXQ0G z3Sx~EMlx0q7lg)(LdsaRtWK7jr6&011hhHhz3#7Tj5A&ctw|vhB0==ps`iN@+Hp~c zSETi>gKNRky;+6%2zj`wPsAw{$_j`sO5F?{>ER;7jOk2MDY8Pl~}uINixi06BLB8 zM*0>T#5fIbXPcWr(g|YR4x>RqUznl|EJ^N4S)5YU{#o|AZAmih{{J`?m@*-Eq}zE> z^i{-uBHAV2aSSpPC07RLPL>QfOS~mfSUG=riq6Wa zYRk&5$1DZ#QDEA|ZAF^miXsS6DJt3&^G3$57u6LsbFlcnr>5VSI@vr>!fTheG>`Do zF%KIY@IsV5N`k6|P+r4L{nQSRJ#$qBVGc%`?~_hyzH>96t{;cfcz;?&Sp9R{cKH3o zzKKB30akDsVP&MXPwrrw}pW;U^`DhxQI*JZt1 zx1iBKZczO#O7wvp>~y!4-=K;u_*2UC6K%n3^ec*@dgLJZ=5I57JBEQx0(M+eQT&Oi z_=~tpX9+X5UmQ)msYN^z@OCH^9z19;k5*TKMKpY8cwMXbbc4laU#ob;y5iVuR5+uQ z#e65$(T}P~p8@7Fvu4=2U7f+uFP;InbsB!Iy@tvuo%Z&lio#6|b^V8QN!N=#tb%_f z!XRf*Xf`|)ecOtA#GfdCZvM)=iLTW}|6^;-#vL6?vcEF(2?sD|e&AeT!HetaS@z|g zb9k*S93JlxCyqCWRRhCA(Qmj%-f;cT86{%ys;F{{{4qnhTE6gHvIo`#7l1{+<0YN{ zRTEq;cjfLc*R)+fbP}ZM#5>rSi`i>f;jCCzjvtDNqj1cNJv;b7(cC;NLCaab7T12C z^>Ws+b#s{^3I8zV>!6Kr9A_$&@;DshG9NyCD=v$OJI zaBvHw1i+7&0M09JVHAHApaMM+un^4<={#R7omAzQi3tP%QwS8I^O8czM9D3Miv+w? zOqbx5hu}Hqp~72Pq^Q}Z#3*!MS5tbAF5E`ZmW`J|MQW2PrsZvy4W$-(j+moiAF&W^ z7!ie|AHe_5gZDqme#tQQ97ECc4Y-zl>0DSl!g@Td$W;Ig)o2W5;ki&2wuZ7Wh*z#r z{*{GqDjzFNzOL5mJ<1Vk$uM9+h1+Jg5lMK@Q&S2JD<`P`YQp!Qi~ffud|?up)qTr= z{eNr17s(Eg-8M98n7_&j*JeNkNW?G?+m*~7ypIt47*1y{{!C{ zc8~rXf$u=~=-CnY&aiv5>o0rLq(D0YT1YXh&i@a=qXrb<`MG-&(EpYJ{iH^ipL8sQ z?!*FP2;l+a;A13XhR}2jx3en~mqnGu;o`MOQL$U+HThohQR# zHjcS1!@(8jv=7=t<1l;ZVQ3Fcf%Z`Nnl|C)K+h{~?#U}m+`J5j*!`w=9B^A*Dw#Of zCrq4M9lX0cG?6aoVB$PVJ~MHi&_wEG;qdr1ZXv-9=RL{|w+J(k25x5JgCd#ut;_Z? z@yp|w_!WnlukkBWnD|v0Zur$DS#J0>SD1KSA-oI!HWMFQ$;5{|VUEYItz+UtUo-U> zoer<@>pwH`VHpk;_^q3M!#fh(@Y_bYy~Ydl-SFYip}M`q!VMoW)eRrXbR%rtF_lRW zx-khm7cp-Wc4au26ZWoT61MJJ%OvdI%p^obGG7y-_b~~gI3__{a+pboNnsLVGvL3B z%W@;cUttmw3gKN6Z!-x8G8~c#ElC*;>4c+oOu{i}nJujMS{;*k9ljQ#qJv4y`wZ`r-^U~t{B|Q2!q-A98s$bT)^{V8z}G^&Vc|x+nc?v3 zHSspnjdW)!lXQ2d8BA(2Z1k8{Va^l1Zw6!X!1+F;|irUo%OI-Qt&IxLqMF z^^51MjOP|INdZ2a<9#FJ{r1KC$Hf;19FBkW+l};QlpASli@qD_?RYm*oLU?d2WoNB z$2e&PP8x6vCoRB9b8*s4xJbuIlX21{oHQ0L_Tr=wIO!&wGz2bI;H17dsW(pQ3Kz3+ zQU{#W7AG}_3lp4_ij(T#q#DG^m{8}IWV;_D6T-@^E7x?gVefXJhk?zA!_TeY_@MC@W zIeUHh5pWX^4)NiyfZzA^;d}e=U48ho;lcqXDf;luefTDDLG|J5`0(*Q{9l*xJEcN- zmr&j=l)uUq%4>!4$3l69P<{(83WRd_HB%^0hkqms`mz(#)=joSI`{g?Qa(q909sqxyye?s0yD;xnt}w4wnDva3w0WE=;Br?eTT zA;(e%&{T-5JOQbaEhmG@PJx`9vMbKCjl?%V1Desn znwPDJ|I3e!el?d(wbh4=4+obW?(aUF>r!^OnUUlJAzKU$9nCW9pG9`fq_$s68iVQs z7n4xb+#ZiU#*ao;L9W6}n5rcM+O7!jN7f^uHmY~9X@KM*6;OeL=aB(ql6r#LP7T@7 zUk^qSF)S2nYk#X1*F+e=roZf84(sfM4Z4l$kLq9QP@At1iWObs@ecM?odDNF#17#0FFSi^*mx0n6L~-R7#W1x{4|7VbL1xSi07AWO7oz( z(*kK5Xue;GhiU$2Y2%5+j&KtCnDmJD=QYj#We`@eufXXI(I|9t`tIh#GrZ_4=wJ&y znl7bdLtn4xP4q6h`yaaRR}zh7&l*o8b%fv7Kp$(YW(ipKFK>^GqEg`i7^{Q@b~n=k z-mtzw773MO$#LSay*S%ATR71iDaZG#Mj^-lK4&~pqa$1sEh8$aVaf>C`Ocv|$a zZ5X_BCjeu=^z2q^vDwJ{nlT3^YO`kr-QQB`&D-5vxGvnU_0GCzzvRH9YrHp40E9w< zw#?T(0ynBu58ud*AP_f~#hmqp5ZvoIfy)%jX9t1}vjdx!S>EPZZ6jLnsk1aax6KZ; zjryi(QAU_vyZcgYa-}V4_R^Vtmi-2))LnupzzxFH#|uo!jQ*AQ;~xx-8};D9zoEN z`EE$YX{{1%i@qoVZw@pqTXO8C2>&=r%X3>xV$?VDa-AbBiMW`cqz!3vV>YCnl&v`! zoN67O7@R6Ttc{l8l}34nHMh?HS(My5I?(#ZcXr;$TUEW>H3 zOzz{ukBPmeRInh>NHG{H!&*fzVXMeX=DKec zl=E=$pbK|aDqVBVhX9Q57XnfbpK8&R$stE?Tn#RG9iY9yTh@dsa6q0H1Cnp7V1)ZE zDfzBow{)*Mo9F);B2=dHC)kIO2tuh>5Brh=&QM(G?^k2-N_Y8iROGAcb7;J&;NM(j z$APAc_CJ??*42)=De@g|bbrqc1|ztl|MJ1*Mal=omug-V)wGi)1-TEY8~m_rNN+=U zICN3hEd(Ja? zXQ~8_Y7g}?^(OUx^)a$MHn=ZMK`b0nP?~m1|C6vpojilTQ-` z{#AyQS(UH0TUQ$XAprX32f0)*!{V}jLWL9kOnELf*urHBDAW(L%|p3+Fom!eC6dM7 zWNUJ(=_mnq08D$MTd`}CE;cV&exTz*#B3T2DE2dbE%_=zC1O2kM^3n3<_wH(_Wa2h zU74?~D^B4P;pDnflpq5gbZn0OnGBI_W?-lVym6K;O<}K?8f&|7Zj9|hb|}X-&I#Uh zS|~m|de^2GqZ0&Ctnvf*zMb!<0J-x>vUy%$7t2UAhGSy77;o!JAZPe44T+QiKaNN= z5+#3)6UlueBGz+^vqpdAFnM}Go}uP}V$aYc@ZpzkoEx)rqxkTcZY(M5iQG&V+X2JTOQm)68g0+5%b-Z6j?Tt@S9a^5&877ez&} zBz6ZnY=DH`oB+!@p;h;b<2SgI>vjNqRhf%*xjNS9iCW_HpeYzwms=$-eqtrta=$2c zc}ig%3^HFKJ5yd1n~<{Z)ZMtl>A+54y~uUrchxQWQ~F!FC5w$`QRT0rty!~Kr(4KJ zMFTQXzUYcyHzu?5l(0Q|@8|i%OAH)%6Wx;4x97vkk)9O5hFV8(CTAs&3XaMDyeKLu zAhDOh9bi=PiWhQaLrzageGb0LbO+ZhRsVU9(&>Ti%Bm?9VDXbFD&G?&kg{J~2;ZhE z5PQ6&;6PuTX4JoPO6bA zA4&{2k+;f)SWtRFH<*3ZH@5smz7EP}51;h&Q0Q#Z!eYN=)sf+ zKj*Hz`6Jot)u#st=fh9d*8q5s5z5`%*E{k2KbsCcs`~1 z{e)RHZvbuwprt(z&yiJfPc0CQbN4EE`XoPGix0 zXlrT0NuFSV{_$7(!}Gxni?2H1M%N;p$PeV(@^Le;(#C=P(ICS&%>i$i;hW>&AJU%Y zfJ<{AV__Z&z**!)q`C= z`lHZ^=$}yi*T8TN3YMTLKR-BT|M=i2M&1217J@(@jfF+<=C4_SKEGyV)7cLO`W%~n z^f^u-+u;l(mvH)@&E3gYY4>O~w07D#vQ{1(3$~r6-$`bK1zIoI3bvcs^LNw#PJZkk zhck>>lTOR#mGB<&Uh%%ufCk-|ZZ4Q>w?IG_VDWC?r~u31suZm4#zqW^u5{0ct$xvx z*DQvY^5qCNqug%Ia7gnVXW!X*XU=PM8-cjuGhNmgrIKQ31C*K(?co0lI-~8ip>AM ze=!9wXt$k&E&1as2|audLu*8V-I659Fp^bLE9sQ{kN_PmvN74+Q4N-L*V_9Wj@X`Q#LcvlJTSI?~c z{Mb<;|KzK{9IxVois#VsdQY(vX;*w#7=Ii#F5a;YPJp950@#-r6@7}WD{>%iy=m83 zwM{8jCM&a*B}(v6i6KidG^TT{T{i)Z7{CYkw z-@fLdYrb2#_p}#X_Dx23FdyL}A;=}TiLM9qZ&wlGJ>m;S|6f^rT1p$gJFF zo;Vmqhrci#bA^SrMNe`bUF*D#`D+Vsdy2kAn=PJ9H5+jG=CFDNup^J8ZRC;am2276UB%wk(jYo>jsb$h0FGJ;Zd zeMxLS1HqCvM^82uvw0Xli{fafA8bkS^yU8c@tRKPLeA?bznx*$-4I$^1$TILTu?Hq0EnKhjCLwedX2xB|5?_I4+*2=@OEJn$?db8~9qT6x zcG4D4e$V7A-~>VY0Ox-Y24P1R{|^WMo*$GtCU*R?$?xfbc*j5byzdKR{Z}uN>w$QrHqL!j2j)-lMIR^TIa{aB5}$CW8>Z>X$XK(jEVh(WJK(BenPUn0FE~Y zK!(LN!C}E!L6odqP$#f!062fr=MZAg`r7iOp{*qHZenQo{DKt~gD7CLhvSWu@VLm1 zEuZM~{wF*uF3Ssbc*I)al-)Q#roEd{)b@OS!~Pt|kOK0`raL?nb+ZJ(fDUH&X@!+Fi(2Znh|q{mF` zZNR39`TCS)yI5a3RZjOAOs(2JC8HjF;B+6aTc8mcJ_HO;jC1hp;7|MnsdA$gPv_}R z?+JIFDmUep^V9NdP31YLwweOhGYfER+K2P34u{!=bBO9 zS?vJMFDlKIj!F-uv&vglR00k(UQjnFAFHdB-_)k6UrKS2+6k4bSD^l?^{U;^$dhop zF<1L3)n(Of75kYAQOzO`&lA6$Gz&4se8;q_yKC%BC(clKD!^rA^K}&|Uh(f}g&O=b z=@1xgDWxt|^VL{pDmbY=h^C`O%AYiAbUfVv1uS|v>Wz}<2k1StEA(vCxdh#6vlg?~ zu*$H0*c-tG)=iepD^Kvw^c90>6W+!&1*0zk_6Md;29fBYJ259ohM5ee%@jvBYMskY z#)=+?1-l}%+0nvSK@cUvcXfZ%uTbc}No3x|xQc<8}=7qJ#^F2?sne3KIh?;;Fw z?;;325xAa+o;g#46CC@*CN{}-vEx&wr&>G}<2_<=(DLaUizCkNke2HD!yM#@`56n;Yrd{DL&B6Agp&w~m+2tU~ zJ(GWwZ=Lo_JS9CdH7Xo*AND<@bKLik$*J@WNBJIy#5%`44owsc#M!~WwmX!jhEh

LXlI$bJG;?YmWq`_Q9&lz zw}+yFxFhvYT%Xe4ts_aiKPvnK6QR$=0RtQEj#Dn)8$5Q(aXY+%A1>P|$M3!TD?OWV zENeLBO6^0ON7CTJf+$(nzrr9e_5?1EA1lN8Pt7sAgj>d+5X#pycCaGognPYZJU^?6 z$a-Ym1cjkuiegq4RvKx-+Q{S5F43n8TNKGx0p#~xP0TJ`K05rtG6M01#yp53)veL4@v6tb%~hPlu>-ry zTs!5pBzCHIPPOl4|IOj|9u(Bt>hHZ%jT;o>LAa?6_qQf!t{*;Z)AusjLya}KSIC!! z1NiXANBO^A=(T@rCd5dxJ7mf~Y z_c*jaSyp2hi<1qXxu^3-`#?Ua5#BH$m04}=ivxB%Q-Q;_8xgd|2P!4c5_XsC`0LgY zw76bD;=QVYBdT+%yeBKLstMO#rD{}Rk!-riBT&#|Y=ZZYcswqT|BSb3{+bi)g z22fWV-ZS=CKq%khB-duT*At7GY~Z#eb5E&NNo0kU(Cvv;+~QT7@Xv}rD?tuA)qfaI)k69&%Urfd#w><9* ztQHy`9$LR$m(9kcO>~T=8JqpSXSZya6XZXW=k|NZ@e&qz06_@ABl~|1PD2kr`7k-7 z7H(8TXI~Nn<&6JW6ti?Qs{@SncQSD?jKGJCZ2%?Pfmh(rV$VquB_^j?vKMWNd&j6Q8x5kP_(9?(Ey_H`6bu9lYXgYlDxu_Fa&R->6L!%4b3tt;*;< z?iK9|4GhuTp+2~t&s&P=gIlJTPr=+~GdNq;D$56>hhZW?3*PdV+D8J6R++)M#!+%! za5^~s9H7Y?$2+0Z&d(w0#9}5*;^vjKofF~$XggC^(S+q|fq#NAQ+VjfDxKIXaoTb4 zrCgP4YtxB+8F%A=eq2kEodApsSLO;13Y?|((bokAWr8i!t)ondQwn|sOD$^FwEfyz zptrP`xM0DayCN+4aWtF#q{l7r%0ccEdJBC|s`#fh=sA&+^6P{#%hvg^=#6O5G)80c zg|DLN%Zj8q#M_yqH@~+y#z64ABO@LdB4$-TY#wkIxc`HnA~m&79_ACLi{!Z0UBq&b z%@WJzDwmcf&J0!Vye&O0HolPz_r?;XDJ*6E)36Ze8;q(Oj3YM~{^zz%#@rQyX4LIt zhCVp^uG?;E58V}6rqu0oPfo?C^NSn;Vk?S|GT^9B%!4&2aQF}$aI{a&rzY6vOKpl} z)v{*UpF(rmaG=bM8q8M!CMgD{e7*0g@K>x?V5xTCjN*h&URe(DM(tw-W|ag$NmUY6 zMk=v#k~&-Iss>W!di59O1LZXJb+s`x1yW2^4k~w5;1h?Dyz}}DRld|V{{fL4ZVMji z9;Mekzw_hW*Gekgt^Qnn=TmZ3!AJb8Po#nJ_A%E(Ea}q7#Gu#MPi?Hb~kRrlpx*L$a zNIEioSrz5a9RDxoBsNAqyYl+0y4!M;mES4uiAZn5sf=$#ei}~5&ZtQMWeasj0EN0xy)_#l2vpeQQP!e>Y zPDuwfxU-rkzhUHmKvv_><+8M3eY=zDWLfRj^V9NG7*o;O?UsSL#($I$ocW-NjF=&E z?&}3nZk-FjVq^_cNRLHQk$)qEZXX&&L+=9`KrYUA#X$@J#?jn*>_2V}fb2y#lTbGz#(r zMi7REm)()+h$e{ec2PQ;wL(=RiK|!3+w3w#*F;KDdkQRgupsL(Z$;fAyu`K{sB)|& zvn4Q6T@o&dmE^tx$?{wEX$2$3HO#j*JYl(B22@EhOVv)9mkQL%uFA%!q_F5LQb91Q zLTszpqRB^>DK;tgD=ziWyRq5i8;Vzz*u|ZIkI^)3QgkW)C`^K?8-S_OLFujxg!TAd zC1RUY1Jsts+p+Pgr%E^*scct)@6Z@LppI2dK)0#bD0Bp8t2EGqXs`MzI;5f?b|O=@ z=--{I#j^(-dGX7;jaVJdfEjzF`WFV&@xg0Hl-^lm3C z_&({m0Pd&$liO$4z0!}HC680KkA>Bq1<~O+UO2Ii^zjYpbY1!j#))tTuswYq@ng*( zyS$^m$pJVfjeEtwC5>Z)deY*lFwb$lS?0K%Q)*@x>K7WUH!Hh7?m6mjaT5OZ$#H2Q z2v&RdThlI5(l$|opy-vswm)2hm((7@!+<-SMjCn0zObq0drkj44Y<3*YHvjRvirHy z@wVMh^xtZ)uUxs5z_NX#+YC{d^^4)GGAiw^WkB_-Y35#++FAy_an=t< zLKoBerfAae2c2}I^%N}m?sit(fB)7BmtDtxOUE6U5#@~21`~1(fo6(3BZKW=Ghef8 z4r>Vun@osfonR*E(uTFLOy@fC0uS(z^= zt8<#`Mn5FKB7Y&94r!CuQE8SmCu7I_T1ki-enx(6M#wU%Bm^f3Ng!l|;4(sX&=U1B zsrXHqRKj&C{yLQ~JHIxuI|Mf;zxGc^DeZ}gBel(7MjNfq1VYgC>E@OsW&&k~J>89d zXi7_H`ee`&x|8m2@n_?6vp*Yi;VsY&Z+34?=iRaX6#9Jfr%(eb%hKM_#+ljXJDZis z5f^bDaGE%&EbIhg3Q_5=Sd&jJUN+}!n9mgHHlCPAN#-icV@*&?fuQ0E-$W0vp=VuOlFweV_+UZ?Ef}kW` zKJh1;ZMm@+bBj&cd0V@!erq0%sK4_5RpXA(`$OX+VBVpb=5GMxmBUr=qP@)Y3Ia?8 zt}qHR*E;vYyJBIbMs3-`%Gb{}nu2pRxVpA#ze>$l4>mtHJ!CT6V1n1}x7};*wGm+M z+JkqgEf?|4?KnjJ0__+Y*Z!y^T)8S7z0d+XNroDP($;dXe$#(jLbsDV$Z-6)XcGT_ zq0(EFY9&skud-5^&QxVk7T>q*UH*Pf%8YsP5~}qR^U3 z%U(sFMc;=CkcSSHTlT*0yZv)|U)wKR1e_fA7xGhuWFke#!7XGgipY5oA**}NSPumi zkKlAhdF-fW>zaqG{b*@W6{?28EeF-<>i^~vwQ8XAA2os{RYO!LxhXNtZIzCRu`_EJ zGNHTU(U~&o#qtHXnU>cd;hgCO_wl&!rQ6HO1?JbE2(RSc_17~tSb%dD4V@QM7J zJbD7RKbhr3bKep~16VWVDDA%oaIm1FiLs;#_>Q)o}J-$XVxGqbnU-H)8U@O~tgAPm-Wgq#DM5mYorite8G z_!WOi6(06^{>pB~%l^u4wriL{{*-yK9#iK@)=!>y>U(7D^(P=w^87wN_F^0^?nA{T z34Cq%*t)pF1Eb=alYa4ZVkp6Yl3XXA5KKw75@1x*l>+g3fkmks6$8TvTD$>c7?i+ws>a4K0yqR~m&yz(k-w&?!+X6c8%Sba?Mkx&fUU=^_Iy90X`e(3H#Qaq_E<;(GT-@r>2 z*na%`M@v`*07?CY?u!Mc)kBntk55;{0PuZ$;J7hnf#W7kIXBQJ^&Tf4W9B{19Q~s| zA#IG=gtRmTrumF(P19qfT_^Kl70@i5-*S3h@*KQ|3mJE{#V63iniTvW!ggu6b$g8IPT+O1P z?2uu_#`ki+|I~x*k`P;n<|Q4aAD*{79trV2j0iR*;#87&!wB(VLs4dNcF4j=khS)9 zfw!nOKO0V%1?;-E7VO(Qq`Vru-)0c!O~v9!z!KFwH64vpohW~@rb>NB<@)rjOB4^A zfh=4#g;orn@cu;=2}Z6gl$C<5@XB&rfR7ey7F|fzD%@axp?bZw{cSri7`pHtXp`yg zPA(jqX&yCBkzIHp87#`mNx5CHSW%mQA$eC;&_$p~iOM}Ex_*4w*g$HI^nnO8iMm98 zM6ME3iGzfy43rQzNM4n@((&;zCu6>-Jc|E3?$LP*p_}l0W~dRawOCTy?AW9#oLfVI zyV%RS#ka`#=OqV`jj~}<-ErA_AkO<(f1u(!0yN-J)m9Cl?94`U->XW%H`Q}B6}hE$ zLX6OE^&gcu8u_ToL@_ZnnDg3~dIFZVZ!a$VvGiR;IXqLF0i6f^ z_J=5L!>J6)hjpTnK#WmUO3M78puN4Cf>kYH>O&OwD78d= zUOiMrfJYzfD&>iN#!WOtm zdrW&n`&D{*0iJF^pG*fZ2avvsernSe_QlXh-y}Nti^Qv9HL}>OS3D5P8sc$T=7OuN zMAk>%CIP7D9TT*&dRY{;xf-)|)q8PPa6Gnp5EH~6z;hHJ9ga`rTzYq>U>!Q*;L>7? z*cY&jk%>3i#43*)`%CLN^c}d093iieeO;*KHz9EBO8GTKrdNvVdZ$>NcX_63EPBux5DxSxX*k>?q~jlpM1^VA;d_EHJ-G?E;7RWXqCrA z|GjSeUB-HV?X(@c(~s($bPQ)Kl)E09By~w*b8kjXNEvWCWOv-@(6Efqb>4T&Mz-h1 zy`DgK0Aoa?Ck)SrYfn(HukYmFj8>(nM9L7Yq2jwIeu(hTPf{h8lDV-<@N;7c3sYQI zWa5@ei2P$|67c-gv4gC0xsp3ak9*F#t~&YQnCCwd)yWvJFnz^kyW=Y^A5?Hp`(=lm z^!Lk-$nc7h;7c(1O{Ot4n%ywqD*<A%X_ys)YP5o|~9-vPc zJw>K|)?pxa+l~!LWGDV3G7!nV!RdbI6oEd6MxqpQ_m=8HXr$8L48o&FR*7?eTO6Uul+de zCHhtd@1o$Q;Qrmbo~7M_nQ|*W;z~uk)CS1UGd24`cRE(6CR{2+NvS=;BSJP?m@K?1 z3|w}xD`H8*Fku8C-PqjKk4mv*p%&}Ir_rXq9D18{5Xilol+J0DxBob%?$GtoLj)Rz zZE^J@p`x9{3#|>q$8l^o*{36{S+(yLC%WC}Z*7tJ`uYcEI`~WC31yw+agfcQE+qQ4 z?ULk{WKbQ z_ZYZD{W*jG@Oe6{oy3Rwf?blInA}@B$b_Z2%u3O-$OUb(3bJIA479Lmd#h_Z`hh`+3}g%Zv)P5p0G^aEa#BDS)IY4tY?57jCjhu zx}8Xfqmw-vS_#MMYQ_ty8tnyh?f&d7wG6O_*~Qq(#51olBbZMZJD7D)iF>~N_`+8uDc1N7m z7pL1wu*9sH{4ON=iiPISdR|y-LKFd3|9lHVQcw3JI5 zu!&E>{gZx@&d3J3nAqF1*m1SO%OLO&(^I z?|xFjeZYOq9pJL{`HK9iy4%IZ{4M;1?>n*nJpAEYcFrE!c=P(e6FWa#=fO>SPS0)F z2lV4u!IsE20=t^_#G2XOX$clRSdEQrAE!A8G#INHCj~$-XxP#`x~>OpojA?7$N*)+ zabXE_!T!h&o@5iVNdlHb5HgPG&McPbOD{?srJwIGpD{li-X`(e>JudOSxxBrZ}=#gaoFQH*{^>{|L4dQ4)`DOKYZ-)>Rr

6MfAIey~kQyD<5h8qC#Hhq5F#m z`=q1yuh-xto%7B4(JN#tZu;#G?B|d3X9+X}V6^}dd>4BQND^D81Ax0EGg*Zzcp5lo z&h7gVN`%>-bHY_*UMNqUuLAi6Fn>t&>uY7?rB5H#da5blcoY}_^q-}>d zolyHsXMuDkwG2Vl7;%NF z&P}9ZfpK(ejX-v_;GFOtU6DS0#fSS{it5+%X6B>CBz+RFAUTrulfp=+D}w`4DlSL06SS_%SBJ&5m#o#;Q^dP- z3|@F=2Lr71|5lLOV`eVA3<&s(*ckW@#$q)C_Rz!6|S*M}ejFm!r&6E=6x> zu;ALmXZGO~+l>6^qZiegO52zF1Hp_yIb*3h28+t*AHeFW0m?*TV}zU%Rg0?i-r*Q4 zp2Z=8JSnPp)P?EvEF>Lrxy#cM^;t7iMo*pGM01`>C025-AkbS9Z2N zsa&IV1s)k7yWCc5x$r>Jl`{0mxK>Wy{bad9e%V^zhNPB@i zy2-+Lqhl!l4F3{@*P}b<&Z@53(JOjWC&z7L`F+j@KUi3SnqaA5tzesAkKl;Foh?W_ zLvP8c2xyLD%kNV~!*?$}tpZwSJ`OmLlRwI)ys-Nj-CK)$Az7CW!g_Ec zp}n?RcMw<8KR2Zlb{5uz+JqLRcHTM`Gw)Xx>+mE3$@OsJFgV%=hrLYWb z0y_pUJ3onr!elc^K(>Me!iX@GYLN`)!aO<34bn%Vx$aDEE0~W!!M+e}%8u)bB+)?PPy0Rr5$)796WaPlHiq!JL`(<5bg(;BWZt(x++q2$AZyzeXFGTjbZ#R4|<^2kU^1?To(CRVH&a1fY`J3KO(*9clodWbXKwP`WO z^>Zo!+X5lklcqywNN9i~_^JNL^b>6XWi~^&W*GxoMvV1b7{6gn;YS*maglP9GI3vT z<)uucRi4L!q(_6vp=d3D^eEXM4Gs*F9t#Ne@g{p77m$yl7lCbyi{gp(E?|}&*w>aq z&CRzvCvXx(r?fn%k5sJT0d7Z>Ole2zoTm=AdQbbv zPWsjC^1!u3Y;wF0S=RT9?96)L3i}6djMJ^g>H6bz4ZOSTYB_IMK-joswXHl5qi zXS}b?z179G#r4E`jO#AuA!dYc6|bqJoSno3dCW>?fviUC8|GK$BojtMYO;)2n^^~0 z{;ZR%^DOQuJJ%9c1FJRI)wad$#QGt(A1uI$@I|vHWn29eX72T7|B|%-l|ucH^9JhS zl_ohvt|r$g+s%sW%xw*x>t@@s>%{t9QQTB+gfDfbQ2K>_4HrD+zULOmT2-PAraJsJ zd|<;z1E*8?Nqn??&?wt(7fNll2JfyJ3KuAi@{5^~hH4Ql4ocZ1#WM4AKNM zg`G1f^fIB6j&P08Mrf41`;ag~2>%beL-hBYSik3nuvQr1i!H&a%p^2N)*Sk%Ck7kD zwqk}jP#i5zgPwyL@#&}H_hQNWJwT!&X${^p5Td_#1;A5e_JY|hh~%05_ikrGt^C-( zMZE+Bxz3sfm*tR1S*(geO@<`01`uQ|GUo{gLrUBOYOV>q)|vh>-7HZ{QCc z{yGwgy=hfkvBfeCHyqz@J09P^RcBmI8Z?Cu7|c7qH+5=HeE*Y(y&$l2N!ZvN;G;f7 z?j&c+A6L3OtH(61e=t-vN&bv-(lmwKo>gpdC`5l>)5Jc|s(==Qj}h)y8;mJoW#!ye z6_;x-CqA=(>@#1-!j6d5TY8wtA|_$6Nmx~!`?sD-EleTtuHq=s9Oy068NaxgK$^E` zU+UD7~kb7UmAIJL8Trzqg<)iODURPyyTvG@sj5Y^BGNpSmS<)D$cnJ_at!# z*7dXQy6#3h*mi_AVZeaow_78%{lPy*H3TYN~?7+y!)H+$&GbPZ+ z)3V?FoYEnWWTmN6Dh8~7hrlx!0K&cAi(C54Y3C0Q4j?%P;i|a&#GuAmBkK zbr8l&Y+u`R+W_6D1pD|f9+J7iJcS7_8+!~EgPiomS{)ri)B0I3tsf100ccwPSK1_v z=r-oQ*l|(R7~$2!AhTm^gseoB!^1$lLuSD=M?f_wa@fW8+U?5mvkTKgVnM97O>C|G zqNwZ98qp&ALJs(1wYO}^H-HdAPg)BJrwKZq5> zN@rbX-C==etQi7b#aWoR*zs4c4q^7S0JCEX1tHtwPM5J2^6&L3SH?LkQ$FV4c@76` z1=Y^Ka-+(B=85d11z+sIuiWDD3%5ae#hpn`w){dam?`1QfI8Myb&HEHabs?AKOXi( z%TMRiDvkcFYaxQ$D$xdg&wcn3X*7Nj8~AOMNigl3rUSrt0<%w zw6uxrLnUAAT1C0NQJ>znf$IZvnQvNgn&O_^E-psgGp!4nFI+AR5bhM-^ca6ZM%(*7 z9^TvaVBBkf^p|u%aoHz>&3iT@GSQ|8SWYpc?4*49>90LB7D_oo!M92zAALl_u~@Va z!cYp(MhLVJ;>I8p#L zOFq~s!RuW2PhC(=%S21pYVBo=5So7wv?QVJAOG=!iI5lUst_x=zSCdqh=U681&rzS zVyted)@A`Z4E*}D7+DUqtO$KXWshFZ3!50x&dUtI;nHAx+SgzP^CQmwx&zh$!0&Aa zw;N~w(xJjd!Qt&L0NXB?B;b?ueo5q|3#F^1?4wdUsfT+PB}|$i?LV}CaK-`ZZ-jzd zYg|_<{dt8bt=PHpD6p_GU9kr`LfJG_%UDHYKcb=G&GVz)yOU!GQG|QQmpatYsu`v= z9YK~v4kPq6Dk&v9s{cSZ>-r;g`$D2KHBN`ul$G(We?FNLXj_9g*#puq2 zNyeN=?lO?Ag=haqrJ+n(SCaS2h(hLFX4X?{;Jfzb@Uy_@%D!OEOH!YT4*rL_LJ2rv zSo6E#bBok{y1fonJ^d@zSO$f;w7Dzut{UYVQNU)+1^K7FwDYZTEAtO)o8;S0ohM`c zpq-`Ee?Y~)AQyXH^I|UMVlJ*A*A7#VJ9hA+vT+DFJW#g3Hy3wgpiGjBV-Bcn`ICzY z7*LTdyRKDJyd-Jry1ltFJI$}4?xV8*PQ!|5FbgRu)l|W%n;Q-!hp$?hZ<22?&-aJY zTz^N?&-*sjyDsQ03{;lsEkwYo{QSFr3I(Nq3W4x8bAxP+pj5WThkL7BQn*J@Dk;nY zylSOG)k?*;RUsi$Q0Mo-&o}v7vdl0S8{XoZwyB_QN=FCEF;MO8sKM5j#=DkVQRyua z^&+_*^;~aq(~x&Rt#O)<*-Q?8h;{eXtva2!q6HJ2go75~q!le#${X5C+<;}9F3pN? zk_?#`Z1IwYs-Vz@al)zymfX=ixW3|*!A1e?_5sw=IcvM|f$xKd(8&9q+opIhQe}!43T~C#$O}qs zn{}SPc|{g!d=Y~Y5`i+0qDPtG4FW0P?2lAR1f`ntgwjd* zK><{@3bm{Rrh_tZCu1zmD)&Xqi-L32pFfjJ=~JPD8q+4amX}6hPb}*;huN!JjMf5I z)&W*H>jI0%Dq}UVI#^wwSrcI=5xJN=cp&^6{1304$%%%|`P0kiEHdwJgB50PUWLA~zk}4`40{N_uXrNNUl~ z#Qc~G&^A{um{=LleN2-p;@;y5FKyjfcZ$ZL<P1pclC!f@b9(D&}0}fHbY<< z_%lv2&NH}nP5}jur=rSS#wltUATE0S#b~CaFoy{tW#%g;vWWGEIfvEEHDFn?n9i(GSgaAQTe2A? zDQ*vi$vt;L6kZI!#NSyPk=OJ;0fAs1M~}0CW6NQ1GTbP<0>>$rG6M2^KkTyjV=8;} z`gBAQ?ymfEw=p{KxRR7uA?yDSCP^^c2ODq=^N+`)G9Y{KkzkpROWEIY=W@hzQUF{$ zT*`DC)qf&Y>}gIfU&0g79NMH#ddIJ))huLhwVC#nkL&sPXqr1pXq?mcLk zsIMA|e$vx^@0mo;%MF@1dR==FPpQPk!>woe$gE$$vsZt@PUz8nQrQxFbHOS2uL#km zf#1Sc!Y{(d(mCP=k~q*%Y$bLUpHV&A{NZvSzG=ji_)K8 zQu;Aw(=8d0BpVf@%w64biJ2tR)d&;51qisnNq^-)yZ*XokK zbQSL1bdsPd6b!~ZQ;|LRjI_*Ww+hhSr3w&F48_G`x5`Rwg=OBVhRcD2)Jxfa$X{zE zIm5$WD?$nqrMc1yX!&?8?N5qQluBciiJI?&W&|e(6edB#<|tw+v4B`jd_wGm7cLo) zrZrontt708et{!>uf>7+#|k3Ur(*6_7gvBxi@Ze_Y0c{Myk1zmS=2%UdR}`iunv1H z5l?K_8iEO?^y_^gY0y^FIt*kA_an5R(`(%O*fE=e2s_P| z2SC{3HZ&{gLy3KC5_TRmE2TNn4|x}t-Jp{z?8_LiWPBGk0Apk=wga)g`K&p<^{iOt zN7k=Xsvhi1p>sL6S?f4?ti7C9ZZN%iS~pR}K6j#u?MN;_braPd6Fvrt^tGs2iPi@E zcj)^V7`yEGU-*T5y$1WXhb%tbJK!?ie+cR!4jc;Hub=mdYQzn3Fwr-1Nrw2v&h!BX z6YTCFnFf7`U(E6wwl>rcUd!CZ+{0u=|4sf!l~MEY9Pt%T}L*)u_jr-k-hZ*ItyV*#hR7op(v$f280KeCiS za7!FBlR3eyJ+!#JjcLLM)_gbqLH^bsuj}^oiAC9bz~|4DH@p&j5#TsmBp_69K;k91 zAQ3=AsH3DqQis66j}ZYu_>exf1e5_*FP5JaWhz zdst<*j(CmOMttYU5kjySKawLD{CO&?`lHB)LPX zkbEF1Ne3iXN$jPRMA9}2+6gsJcw*e1h!z2ykzSJCk_x0u$V*jKU$G!H!V(2tgd;`65j&R*Hg_s9^~oNqAs%^|?u=>uYChfibqgAr=^2!~&U3@-Vib z2Zq_7vhY6O5bk(F*pOy{IVo)D$g#lSU6g8et4)C{C_&1l{^2hB1aNdmoqxO-ylj)?z}}A;(cL;Iqt;RY-j#eu%8^9_nU8mkHU0fQKg3 z-8nXHb~!e{-{p(0zIz({AkF3w#oA%~6ns1dA#NyNDfUu=RI!{pezp6{NA*#*lWRGm^V+m-Dg}?KSf^zy&*u4i-+eX@idd;L9_~Dx;jVF^*)x4p z-1OYExSkAkETORZhTQCK4OOg9eHUvsyJH{wPkiylz4!Vb-;$FO>RZ~a*5IYy>V%P! zTNxO~6Fvccm}_K>a4gs4i2x%QC#H|eS*nSe|{o-8{Fbg$0f@be%JufxOW@i*i)V}VM(2)8glB(dDi3?oVY zk%Ey4<^4!u-)f?7P%6layVfA+ddv0n}e5eZM z6p78GM6UJ~9Z8?dRitdccUDbHzd{G+qO`RDdCYmoQG=-!XQ!$R#Ax;78ZNNm?&com zvbaf542SwLz#Hzn)|`@_mya8!GCx(R6o5~a+6Bjyu`k!$k`cS{+X4KIkle=&j%|+` z&*eIa^K!uB26mhKD^X+ITOmKk<~tuq`N{%qfxp07;3iO(oDwYO2*ULMuAnNs6FEzL zvbh^)CwC6_Q7s1>>8AD%Z=^&+@qX8iNG#?}gxr(fIFLMNXkGQkDqLOt$0pp9k0OOU zutymML%q~bM{!cmcJ}X;;`Qtwe*!Y`$apDz+PpfhXUtaZNx$O0 z@R!J`TtS5(J$!6@FJXHm7ODYCrUVA};F8aGE}}svo8qtPeYmM;Ki0ptq%?1!B{UXp z5xNQw2*ZUJggjwanQ$PP2%a^qQ6cElr2pEIz|cI0pZ{RI4WTUw+^}c`*6LH+Wn&(w zs2@YN%a$o6o^76(Lq^68cMu4ck#mjPa{s|4tAmi-H7c)FO;yk3z9Hr1tWoL0Yxm7V zRA((e7zs^D*cToBsMz(d*g`^<7ao5bCq*qMMS zVkqhxg%DAL^-bb^B4{E02W{6r=_WsGBFkHBA-R$cEL?0F6*YIUDM-;+Y*MG~u-UjR z*yf3byal*nDQ9^uw}_UPBX7}RS!E4WEIYTYqEIPz6fa64w4d_U(DgUnq6jDlzq7)- z@a&MF-l$_tIdUKvv;ulyEY;6e|ibJLGN>3#CPDz|M`{(CDr(}oUPV=NndgEw- zceav@&i-%IzRXAE^k+?XJP8vkjm%ND?C}Wl&){Tnt?FvcVQ#k zG2%52k$F-U0}4WqgVTnQ2#Xf zkgeQWs#x?InvrOz8_B+Tw(P&nlTjD}Ksat%u8 z>7cqZ*3f>N^nKLCy9A*ylb1I(=zX__6XR`It*i{?{%;m6Hi}-mg zb3TXV!~e&yw%?ImQxjDaQ;|R? z(6b_}vU#E^QZBVpB$v>b&~&>66Z^Pa$Y?wMI6ScR_~U5}QC~9QPzgP%hcZf$F?%LD zgqa+01=CQYo)k*lf@&bT#hR|Gu*dkwO{nw^*{p?jq}Z>r(2lf+dW6cRqH$TEit5Wf z&duT$Wj3~~SNqzthJZM^V|FRaB+mLMMd3&ESiFm@oYe=9MLGR|pTt&Kuw)cH6&cfZ zB+WsLjufmJ-rArzmT5U}tia-HPsj)u=&iK~mA09G?a3X9`Zd}+czvS#Phd;T6BKTp z2MY9hGp-vmqquSQS`7)5vUm=Zo=|~76;{#< z-*D>Ol?UDu!f~LNVBPqQ;KnVMoZ@o09TFgeWCI1Ot18WKe?iUWU=h)as4O^H@J(hm zh0CYFZIw-E;+s#-)*f2k9s&mQ;8#OaGoX&!U_Jnn|xnUr2vQXi>^ZzAOWrr>uZ> zZ5pGU!l%q-WH87W#$ARybs=@t##yCXy*NrU=8vMt*o)Mg)ce$km$(_d{I3!qrVdeY zv=tdIe3sGH(YDjTUK-lqQ+P4Sy(Tp?h))Ccv^LsD+ArD{=>PU%NLkj`LwSM}%=p{4jh= zguz$yYHF`qLpAc}R;2E8<>`yyMjYnM>zC1M-J|d4s>}wuT1|$D4Z-h4&F`9nGg7jW z;y1UP0fA;swx5Ofkoum~SHs}Un+0zMF=yT&psjiP*PJ)Nr#t7(u}{K@vbM69KHaz8 zbUhb1^rpS>=}vnCr@6ZztBD6+TD3v^jSqt_FM`tviP#ItSgV-2lzN#=;oqUM%$AJG ziM|JQqp8!=+%<@Tt-5_|^zN$L^#4iZv2ENm@b1~`x(rm63=?^RO5ijX|Dr>qx}!n?2?DDiqY~(*oEN5IKOs{$<1>gU|OoPAOqcb<$7UB|D;sHf# zwYvDn321M{)B~Rxb(|V_D4bp#9xLi7i?zijum3q)l6*l6d#)t;qLzzj`2{V^1ufh~ zEzCu&qhiO{)*KNwM})g2!rl@Y;gU*{C0dx|lH@;Hsny~qZ_mDdd9F)5{5C-j-7hrz z5)>K?B$kph{h)J6R)6P`V-knnKYBjhfAl~he3ZaPiCz}z?&r@-=+FB!dR^0k4QDQj|N#k~9+DNOfGc&tJcHzw%N#@;})of%4}yq6q-2zhT()(+)02oj{I zg+V^~1{|#%dcW1a)^oJhwo!8`@c&gNR|NIt%1d$^^tWVGOsV_w%7P1m+1k8Y%0Z>G z+zSG5w*qCb{ehUufUOc3U?1K`GBHdU$YazzcB@!w8|u@ ziP&-_a2BK9;r}8&Uy4D$*edGP;Eot6R^js^$mamsZKFOPkRRm(Hh(uG`Syd1@&J{S z--AfPXesupDpaxcN9B_yBc)ihs#y+JHG^LgS>?-`y;}C$w529eYbo1J%9Wmya->X3 zxwKiDH27LNApI+yv_$X1UqfN)3+1lEd3+f}-ZcGmjXJ1AJL3PRB3Vf6CYEeG^M<@5 z24g`$R7Hxn<}Q>AGgCL1r?)tP?5t*HvH7bR&8Po|dmf9iD6j;U{ZZFw zU@{V8A+jv9o@M!Z+i#M*IUs5h?M28!`12BqDP=1x!=dmXDt)eAcN5xA_B9)mj6z*g z6eY8T9cU&UKod~V0F)W~;S(wzWrMKq=sRL?K}uT}cHoz6(fgL**taRj#ui~6+yd@J z2M4iiLs-IST+sES*rV{%RLGi)#09-PS`n&n^z8}ohc-KqsHq(FGGHP6c_{;|Wo%>Y zVdO$9V=^O%Q^jz8!~iLsbV8RszTY|ZVd=EvoA>&qd4YjWzL0Vw7}n#EsHUpnhHmUbQlRlL*=v$yuC@XH>%do;#shXnh<4E z$&mwPw!YLi0s1VL%8(Komi5#!!-GgQD%7KhC~2g=!^r+wb4hLkEet;$8!N3SW!%$3j$Wvfj(mq z7~vA&ED!f{J{o>jSOCHwToOO$3&b`2Uh!OrvcYtp6_PYDO=2V1EjTO~b4giEe$#cK z%4}?RL77v}pPtIHsy`p+wZdIPja=7UY4Dn!wpxe??S)tsulTtH?ev)?)8{8R$VHQc z(CYBH;-3ff1_4%0A8RRgf{h@@#b?E*B!DCNEzTe=lH4WAOT>z!HjfD!7*YtH6T1!7gW`NoF#4iq`8z{0qwZ5CtWkHZ{59yqhu6Bj0iimNB-=3N? z6esU}$-vpEHk#pdJf(H%vlWx46rxJARH8oF8%ANUBlb}9`I;T+Xk5I<)YU3J&cqra zuiavt!L;_FVQ%mceIBCmf-PIygP+!XKImJ$#J+8BfJwS(Dn;8sGXn%BR$#)mAHKUk zzr>V1;wE$--W83|{r5ii`s60|_~e%L6|DVckKLoc6=YsmuqzWNEN7T8w)<2F(7N{a z`Fma6+5Y?3N7;;Ei`{8Qj$LD5TUa5DjCRH+d+aBB+(j$bpxIFvDMR_lHkcU@szmi0 zJOUj^hcgEv*ddumI^B|w_wU9-<67bYi1#`8JQ`Q6U}R8#4~MnqqcT^ zh$c(_n1TR>u<(70>tw~p=C~i5-3AdX6XjwpoNW4(`og-msrO%`PJ56~m_zZ*i$q*| zl8j;w=6xb~oA}RF^pI1aE`Mc{xaQ@7z+6J{sLc7y1&aHJ_5=rT(%^n}0txts{x^bs z<6qPYRgYfdVT$iuA6@^S5qAyWTF|E8;~cXS`v^4H14Sfn2;^X zwQirt+j{3K>+i?i(&N+87|ikPV~CRhDvi;Jl}}ao4KT!nQ2l5pc9v)b45nvrWocvg z;7xyX3js&h->Sr(?xDKm*zlv;qkrVL9~r9s=8T+963^N1x_U=uKsguux1r79qY0~) z{4OW{QrYcwM);%fnzdzILrpsu>V76S|KAN1hYTh+R&OesW5fSwCfg+qeE zE+tbYs@X7mb_s1@3lL6Kc}*K3&frH7BtAL4eyK@l4-J*T6nzRFd3_RQ1N;|<0|NeQ zV^o4|jK*SQi`Z36GSwMeVQh;fc>IzdO>Xx5Il=45)$$zUYm4xWR2He31fpr*O?NIm3_IJBsFT!6DsZD2(N4lgU#ceU zJlt|8N^KQiZ-ph=4BGIEEyjmxKbfN`a1Y^;KfLAn=GiWKAo75*fj;@H3wLOWR zZA7w%l#05u)n@D+Z9|!|L3q}?23a?(4#-|AT`N7pt@66F=YC=mB${Z;i|sI-nZg@F zK;I*1fYK2jOdD^Kc1Y3aG_-cK>kDQ7bs9bRYN#gx(d_utf{je3+on4?6mE1(r$fBh zF5NNzsyX+`%QDZJqB7>2f~qGk!DmlN(Pt*HG8C3;g?Qb z^02mx4Z2)nt{fW#!|?>*2x%XcPP%+?-f6=tFIn5I&}pvMy_lO3olK9;jCH>ed&LX4 zp3l!Yr6aCP#C@(Le`p)3{Bthw6gwgZQ3-D-!r|G8kuj;o=h9ty)uGwfu3R6yUGa!M zd=GP@g{R-b)9B>MZi$*XrZcTp-zwYlJYcBmMhqj`BNEnz6Ds7xZZ;29Mc#;6r;>0q zAsBdcCBk2B2%X!)AN#e2KW0orQ*p_Mv<4UP^6v1!>~cY~;AXSpWe<3<^jBYTmj5O% z1i4pP+P~WMh1qO$?DcO_2yfuDVR8|b)Sh@@mJoZzne10En^Rj?B>X7+^-P&}^v4xv z%?~^yc)hxaKj`tl_hxAxnAP%B9BNM@hsT{Wb&9c&qV@oF zNRQ0Qid4MdzT-wzbsV2P=>X<`UMczFB90z)+SEAd6_!3F?ne@t zs|x?RJo`N9Jo?48g{NaR`9tPh;>6>;qdz8{mur5=+sVGl-*xpKL&%uwc7ew}jCh&{ zh8cLKI@9zEmHCv@D7U*G(vSc{(ImnF$z_mxfYbvOjYI?UiqnI0PGUer3Cccf?H&WURZ|7m z&|_PBzQPdwS^*I^(Oak8K)#m0wYRepeimzR->af6KysN;V^VpRg|V>29Hyi;ex^RW zRPOTx1h$~`!?LCQXk#UXag5=>IIF2tQ+$GPj&Wu0wP_I&KjJ~-405TJ2>!QT1C?t) z2cEqEMurInWzAZo#@;<3M*v^byT>~^tB!a4s6F0}B?z%E26Ucz_Yg+Bdb2EmjI_ku zyT@Qe`PbpzH4~?W;G*!R@V*c)?h%d(uS(~OXDt_B-`IjT7df^LMDxtAJHAg%0w#EF z{^#rY8s>_#m51mkhm}6cw#x+D39ot`2|?VLOq4CAxJSycWvnGbYZZaic&-Ye)2Z`9 zH(Y8iB*uWf;-qA_(`2R7xmVfoDv^U{ho>3ii8lbsaX(cJO>y5!(@EF=>B_iI0xb&% zhJxmOBVB++5+_K;l;UF4^q|aZQs$jIq0DpS!i~llL-Clv8z{ctYVLKAYzTD&u?XJ4 z%=sNqqM*D(r&i@y$!d?|vhS9TPlupgNSd3Pl59{!FC@Y})QAX>eM?#$%j3THn4qpV@0z~@sHh$z--V;uz9(Jx}H$GBldp;_};Lb1m#XV z))-u_0YTK~j%N)?X|H;9(+Z64n5I^4*ifvIRpKcR;Xh2}P5C5jZ88pT5)k=hU2w5^ zi0iRmi(L>hUDMfPjbr>a4knhZAIl!oSk)qHAi_gK89_JCarO78%h{f$UdG$nR_|yn z0)h7&!_;oY6aW!j7Sv{C^6p+_?)NZF&l@kvx}H;#HGO5x+7NU|%)Yr1mehN6;>!Ng zBR6|YgJ_ihOQuNIb$XQx96y`kW3Jhhzoy?VZhy?H5kD0J=s^%;B&w1+<{HT`b9cY) z1kblmtASv8d!>2hnyPw3^NL4(Ybsy$n!!w3in{x-L>(e;7(%wk&mU;Py${QUQ!eE- z582%R#`-3mn!MGUaBFaggX7N4$nS;yB_Y(A$UHPS5bwZ!)-Tu5x8P$0H<6orDXaKi za&8Zf|3_5ZgJD17zU6-7PH~m^T6|;vEjd(A;&=7dQGP5xBRBU8xSo^yrJA3fSN!FA zPVtv-MfJsh_;Um#!M-+o0~jC)Nt)%TiMv~q+;wf|fi>P$&@V=W=<{fk-Ap4oKr7Kj zf&B9Vn{gJ2-Xf|)*n=fdwP&m(5$Ay zRRyZ5f(9O`qh3wrscO-@MXI260al#*g)E+tgneW^333vYOQoL)4$XPgw%_=*BrFrvzda-25P}dw-5G#7;SNfyySD%dFxaV>EPW z39v^*VY3y(BJL?*&nrLE z%+poJE};Mv*1AABMA<=~y9w2AH8j01c}RIfQ6}0u^anZBsO$e@qLgsi<8R-m!JRJs zy&Jl`t4h_1t!2AUC?ZsQsy8)+dYTGmn4}ge=J+GJQt+TBH00SX>6z_5O!SFZqGB=I zy`Si81y`O6iS2|!dV^l@UI?KiVywmb?d|^ zspOBSC#bd#s8Mto>lr&B-W9-5XQncO3m8rBOM4Safx<`e-(TY8u~3`{L*^u~w0GZn zrB`1kWvPh!k{?6S8zcv#>^}l=tY`1%*nr-l*a*o0t>?IT`Mu=uB12rnj~P?!7b==TR(Q>LVSBi>#dJIetB-=QwhM`y?+st1~A&>swJ-``e+iUU4Hw z_7h4{%EC6v{?pnL6N$CtXF;7lH(27x9kvcn=Hy{2z+6#kSv+Jp-%BJg{ZLg(9^uyT z)=L-gI~>Z4_{aI+%y4SW#i7(15jWxb`HIU0G3P5j{3%D9KEF~{Mi1NzUf2!yjRrMj zaz%txIiP-y!A}c0&9=Gyj&h0aSTzf#BXd6!gfSCf;$bmNJQOkI{t?w_jCfDLjrNYZ z;UsT<2X(q^$?qe3emhjW-{GCIFzGSfZX$8slFJ4*!TviBN;2n8h`7DK+s+38p5$ua zgy?B+(I;GQ>p-vo#N7?gQe(_u|m?2g56{LecD(!|%Gc?$JT$o%HkCPZx0cU32HY$c*E{weTkJr}ock9WuL}O)&Ig?)T@Cz;EmuvM zM^FVd3tCvIH9uH}QdHt~S&E#H8j`gY(WNf=d}aG!4&ho{&q!+Ew@E_pb^Kp@uukg^ zOnP|t-KxIib6k{hyL{E8c88WgnQc=2RcEUJ`**2#Z7mW1g1Av%hHNS(_O2}^k9ZGP z8WO($&Cy43&*GpGC``z&_<5^}4tketw$LQ6(9)x9px7=yu8+ZpWSuqtF4LgJEL%(a zO94>yZ=0a0Vto!O7E5RgXnS7LcA_n`lO;`)C1d9%OB`#a2ZYfLrPx-*@8jl{+ZnGQ z$qH@i+e+4#%ARx%DoyRqMQxGSO4spL-ge^MWP~t{^o?GiJ8-k}z{qB- z$WX=uz#Vvbcdm62xhgNA>M{Qve`k9nLoS!nSY}2NaJhx z6!Y5uX3_1LiqxN$(Mz;MAK8@(Jy+aco6hl$!HCzx>=<`q5HW_BPP|TJ-yw!lKM;Ss zQD;xS+>}g^B5^aU@T^^@**|j^?22FAH$`{o0mqXqz8>d#c3<-JNV^@qCl*AjY)XEd zvN0t~iW&&nkk69xly zJV(onFhM$=paFAt?yy3G1Fm-N@caf`pGVCXZFUW`8Ju9lxt6f}30hU1 zyU(|JHVFP$-{1)c)x;61X)KXBn`ywgj8{UN&ER zTl`r3PW)XQ9sOVSl)`7QQNZsvl(>F#kobJt(RWe;&P%wGQVA?cku=t!%hQC}S>5eu zi$?e+F=`q7>&F&|x2-QxNGf}I==6D9Q^aZDaW{ig$hpgT&JlCaF{ExTcNw?Da1*FD z-mgMHSkrwPFk)GbHQlGttq>&}6_k1)Ej33a?otlvY$`-457cKSy;6zG!gY`mlEH(d z{VKDyeN^8iD^P~vGgzZNZy8f{`5$JfY5gp> zwMJmfKfB3n*M@(?q7{-Wm$8qO%Fa%|urd&GCX~7YJHs4ZDgF-wHoOdks@o9f^p_~iaUq1q`Sr|JGg zV%;U-E#XK5*j9*d-B#Eo9By=mPtJuvO+4J_2_HQR<2b{On+oap)=h=s;tQ<;^R@S_ zlfhN7f^@M|Uuq$R`B^Yx3Y+lvzLn(M!>aL|=dDBM>tKK`N`opA$wWi>y7%|Ngaimx zgiC~`LPzO-X_yp52rp0N2+s$jHQz-<_vlzv_K<@%0>g?Vi!v88l&t3UIW!v(&N&z(rhW#Q)%l#s{}2<_`brqZ9jJx zs)4?rb(YOqDZ)MgY8vZJW6z*5%Q z2s30yu%-Qs;|N?})l#vvs~knn4Td4-1p_SR3^Pt}968mD^~|e`eN0fysr$EyXu60f zD`)FHcQjwX_1*a4G)FNc#PaQ5b``_yf*B;J=t?*Om8b~YH~Q$*|6%Jrz>;d?zw!GV zhO5He4ivW)%gQFCmdyuqv7es-xp1-5Oy zUHJLG*2nz64*9~(^LBH6U@z#|`1xSRAq_twEXk4uzvK-Wv-JzDxFv48!^XR3#@8i1 zIf?;y4w=x`#|*}th^~49*3`QZ7txp(40=(e(CY=5^*p&Iw)%lhjR% zjk4yAV|!10q>Hzo;LqNE0Q#stZoVN*V1vtS8T;|^Wf_g^Z)~z?6bFzvOHbmZ`M*Zy zd2@75I^YQBkmQBr3QwQ6M?RT%UJl0a?#uVUE?f*Wa^EF)P<+YaK_8u+qn1ZP;^utP z7oP4dI!Qp?{dk%H>nT|EZbZo^zqIGg`vk`Y;EF)!PEaRk7xW1XMRFOamUYU!52IE2 zznogPiw=r_D1q6Kd5GCibevhQ5M^e7i*2goPOZ<|9NU(oFI4krLZ{Z>ZLdEw+6KRE zoBgXgZi2tqHyI0hb!j(2^3qib-5~g&wnfq{0Z)weWMgH{vXJhjtomiLjWWQO6?xj? zPRlakeW6GBP6j$;2c5pCPuQr?Vd)a^mT%SG(r#7M$X613<@<=BRepsyPccRjNNk7i zKtl>YL=mSrtC;i}HjD}s#>3nuO32f%T3sx{D=Ha|YZq4?fdO*F*fMU8wJsKQ4FOaL zt)@NccA7R^XB9(QGGXb-kEDgZ-{~5HG0~a`TwpS)&Ij){(VN{!3}=H1;srK|(of{F zTiMIlcn!6}=qzMD zWiCDW&I@qj+5-BSBiNJJRJI%2g##9Ha@b1*b?jY&Qg)(X0tfW6R}0<>JOmoSaQD3V z5a&E6n{%J@tI`uZ`}N-Yl0R0$eFm9(i*bZH@?Y$f*R!viIk^6B|L}Q1R!Qj&XO?Zb z7#DLm%WOAuKiBF^TCLL=P0)m9?sH6lC=q>u3CO;fh$e_JqC`ZLh)KPeh+Iq@*Cg?G z`Nk!`IGfm*h_N}F_%RXl5+15fL|$P61`-i0f&hR*U?8v%I0!t19)v!G0fZrh5yS|H zkr1OG2oS~)kcSRTAcVhO}jh-DDVA^w42LwG@~fbfR!f$)X!gIEc% z3Su?H8i=(J>mb%cY=GDZ!GYjH_(KFhY=Q`c2!hxQu?1o)L@>lQi0u$NAa+9Rg5W{$ zA$CKAK!ifLhlqfPgxCwQ4+6Hw!2yUUh(WDZD}Y~x5VMTZI4{DPRCD29iml)U-zUs4-bNq`eu<*TwE` z%3*cZX-l7D8lNS$#Na=R?B7*c$1~2BYCHq~M{=|6b;a#_+Zv%#nV@ryJy3Td+v$?M z_<=FBjfcjuv1*-A`PszGQ)*JFPN;16q@t5lirQ3qRA4l&4~LCovG?ZU4ERuRL)cT! z8XZ2lV5M4=<#f10j;s^8l>gVs8G& zs~?p^M1|N+L$1@+X3VV?{O1;=usOdObbUO-yUKgQ`=n>x+=X4zbse%2>H93iYlA;| zzr03(LZ6LoJDU;kXnaH!zfS1HkNt%J!4M6Rr4gzTBu;y_Yj42LoWjUN`N)_yOAhUGAxaFoARTA}Kx z>aFUBN~1E?T5Dajq|dYg(BWcZy{1p@Zn3i$xLHK?9y31Hb<8+%(4TT!3yyN#EULR~ zVAvj+{JATK0yLdAFm3Oi{S+9s=R_Dt28#%52|EZ;gbIRgX0U^~9tLEO^aP6fV~REr z=n?5%vEIBw$&f6Nth&VC9=Jzx=xh}x;FKF$jS0xQ?3S5$$_+W?hPmv9JiY8zE~z`k zI-B^`4Kp8JKHJ?eHJE@dH>B1J6QFT}x4`Tw`}AsxEOmaif-Uox@zWLB(rPf|hmqR8 z_;yPB;tE-68qmOpn#FzaVHbSVwOF{GnVR+%K76~FD-X%7LL-V4ZS*5@wE|U|EA5oV zt@2-Tykgfog@eK&;zA>sd$6F|k$+$LN(mXdN~{Vkt*qX=>x1II9vE;{E>W&mjuQw! z%oW%R`~@IX5HC0Jb2v5e?_t?-%HzasXR5ovveegUOVd7g zHOe%d%Th7B3yd6s~4oVIE+fWS*AiF~1RNhlWy%C2M{-=w`Uvv8ACM778 zrIva;s_wF@$*r}m{oDoel$uVvn)kIOuPL={Zzs#)UwPPtObBCdbWxK>cBynxlXY6T ziK6>JpT=Opu+^F=j9zKhsc`i)B-V$a=w73*tc{=TyZ<(Cg_R~j7sk{TC{UbIq$xmw z;$M=rf}kW?H#QI0+W_?cnLKW6Z*75>)*ou!fu=D#OE5+_d=$7KF{amM0m zWc(_UpPNO`owg-7zWa6q1hWo*-5Q`N7;Sf%bt*ylwi=)>F*o%LFtvtHqp3znymNcI zuF1Lv_6JzdR=CAplddXMb(GYN#E!( zOduTX!t5iiW^S8%$i(mIQD(C<^CpwctY%(20{6MuCgKVc@o^Keuc{D#72coy=1(mf z^>mT99A+aiKya+@oT#qv!&;(>5~70G zrL)hmG1VT0(>mR3S3YKh9V9W%D}`e_=nUwk7xI;9_{(F&z=Aj9DO*9?0#`ElvEWo~ z&w@v3ngs!rJ(NQfaGtUtJ(I;wzv->Bg82yj&0z09SHgu)?^$ThyTAmlya7*N-dpDF znQ=TjI1ZPZ!g=^O_GI?F#rF6w%e9NWd`L^CxP`%C-Jal`!MnC-Ne;AWQ>l!p96FUc z({bHG7yNfksN2kwZLTNVo;nB?o(Mbd>G+)gR_6rK-+iEQWKZ)jwGHywZo&N)eAyEfU4y$){WcX$=XMR>bpPk+m1AECImZFe=F6$3l z;Xu)ih1gX$`u7B4!H;-Xa!>rJT21_;G`%yIQP32#Ea`1*KDu1;wz?@MGO2m>xsS0? z7xo<>HphWN)bYz>J>pm*j`y3#CW>0T(38h`M~EFI?{4#PMIm3Yx$LS)oB|S}?s0}X z$s0^ zS31s>d=m!{xtTm&HAB8wE}gms+_nL`O!v!A$R+Yz`Dg7E!V?9cDe8%Sia*5piiwoV ziU@_UjTl5x5RX!-6>W;1mm?=-^g)|Jwx!YmwxEZ?q_#43VN#iIwH83D1+{X}>G55y zRu5=_nt4^L;{aYZWZ?yHQ$-y!k)_dgwD-ut!tZLt7n1-;-_@u}y$s_-04jh1TRjn9 z0RCP=zjQAo!&6afdX&UkxMs4Y7S7J?SqsHaM8&I9IgoLsvQz9k`{C4B+&3Ldu- z3cWu6LcVo6j#>=%;WaG)iN$vyU(w_6Gv*9lqYsoQJ^%;CnCJy81+cilUV;CEn=<+d zAd#%_i-=Zuef{QnNEpVOSf@YM7zB`Fh^9!g$sl5dH#EIA4hw<1HhQe7KGD3@xCQv` z9NmE!bdEE;HqPkU=w$+;t*x5rI%SH3SGAE%3vz87{K&FU8<-{7|Avlep#T90_Ohvy zaTv;7h1iY~9Sd+BWV$K9lj-AtUI>|PecITD<^&AL^t*Hl)rK|; z7?J62_rM4;eF+#zrhBJ10~^{}BWfIjK&A)W1IA?fHef=ghrDCL!}kF*GCc--GAGlI z{Z!k~5`iUr{tI9E&PonI7>BOd`|Y0wVmbtqb7u ze*;!zI=t{s9PeRGruPH#E;1cOY@8X0?QBL9V&~34?3XeShe96);<%21IBjAeCC=L! z$YkIdMnm3H_Pco_^jHSMC`@7?E*BZdv@`~?b8amInb*WXrr(24GUFiwaedA}W)@%f zn6=+68)5Eu%WFd1zB3T_ZU*8J{+EF)Ak%9QPb2pxWRaOWvUt2Zvb2!ljxKa|N0yL% zmo+*wb^%{H>bH)8t}NWdKv#z{(6zA)bmzJx2D<(t16{t~?ansTE7l$L+3&XYI=W%I z@5WGHP8vLfd!2#$=QGfNdyMhuriTnP@HxYTT1Rg}H#afREo}^RYvFeW8r;o5xBZ33 zZ^!tcJ239(PWa=XyUg5C-gxMASLp1H?q;}SLYx_xouRWCm_6m(%D9QXW!zH#m@@9ZGHys2*Kb=HH=vBWwv6iy7fYZXq>MYOj7x_Lr!uZ} z8FyS6*R+f~&9ID%mT~)0x{xOJ`$iMD(!_6R;u^SkMiZCQ#Kkmm9$aM8#Hlp#1)4Y! zE{@T}F*NZ$nm7b5w$a1^H1S%R*c&dE(8O*u@hqB{4i`=|u{BLRjwUvxiKiLT#3)VN zkI;p=@cZP7TXV&4bHz1q@hn$do+~cS73aZ4cCI)zS9~E?oCp`ka>X&Z;(fW|5V+Wu zD-OsNugw*E!^M(Zv0JWqR<4*17f!ii>s;};T(M~`{64v2G*{dY;O`@azmK$)CVdOj zU*X~zOrjn$(mg9W0F*HCw5 zQ>eUPDt|XMtQoAxK1KCoQa2*3Km*o+{srLRSXLCU1p>_~Y6@@$+reZN2nCea)LGCl z88AT>SPrgf){(M-54a9E-@%P@)SD{lEfA!IJBQ662W+_xa)UvhT$-D}e2N95ohI128|sU`iZavmtCa&Q@xF8NF?Tbfh8E~oX+qAV-2 zFP2T6PJ4?O&7}TA@I#EKNHAXNU>h?5QH|(jvdocxuG+%g0~8Zg2GWfxnIB8;_S{)d zslF3Q&U{y(0fnQ#bWbQHp)n=7=%Vs6(t}*za(`A_HZA9(5fwF{?l7bIMZl&|Jq`hS zAMczXwckd-$2)a;ODKp8ri4>VN+-yvdd0yxSR*R*?aoi1+WZFB(*LQj{q{1PR*NKo z-CN+_IMRXgsn>Yx$m+#Usa43LN|sl9iF#_SZzZeRcSyGGn7pOj&>x)-(2IGnEwl`? zxw@QGZJ1aUjK5ejwpu$ZSnp(BWnKEm6lu*_)}HsKZ?Qv5?d7LKVhWiqO!E!KN(26X zawz_pplee6L<`4Qjx#<0-5Nd)bto1C-*L^On=zAG@T*!7yJjxAIpAZORdMz8Db36h zvNWpo>Ey(guav)J)*)n=W_R&T{Up(`lgO`z*GMJxz{i7acve)as^xA?Uq^D=pRb6z zxzxSNdT_h-^G}iFx=)(%ts208hm5Cg?S{&DiY}-#pbN8AyRWOS`7gD~b4c~B(@e6! z<}zJ_B4pR2(-BV>!ycRFz4|KR5866&y)+Y)2#ZNw+nndL*ST4V9jQ)gUb5FYVIAq% zAL_F*jDM-sA{rHzOv<7rhbQ&#+qAIChJ2gN`D5R-<|t|rR@ZMu!$5Lfg}L<8H2JvUD7}%!IeHy!t4&v#;a8jD zx?T~%gwBtXXkGopKsB$ksngabB>WFzN7>hd@^S7qV1sq|-wl+rTDOP3l~FaTj16!1 zd@Jd*G~m9_e$cA5!s!HaLNURWu!OLFBy=Z;+ zwx~A0-TVjq+@O&QO`cw#X7j>&bSZj&`be`+1)7b-eZ-j2rTFIQ3B=3hz9tWHkxDGz zB+LyLKVl6F6>eB|z7uW_bGCkMLhRL0$OQ3_fbZea*mAMLjgewuhq9661G;-1Y~Cp{zl9Q@Q!0z95^I z%`Y7!w)A`(d`aHk5QJQk7awBHd3FWbGnM6YfI)=xsc^*y=*IanZfSa_Vfdd{I8&nr zu|>UMc=Wo4E2OAU!zclAg@go&5<>F@0gXrUZT2+e+ayoSIa0e7!K-!7!grJ}^L2E0 z)vh}xtk^ZzFyi_DagRS#+l~Nh>$v#`$e{xWm@C`YW#nd;aUe;Vv#}fBsgFrLnTDp})h!|! zy%UoPiqkG!9g$X=eL)+2v`G7c0zOb)u}eAT%%{yxSA03knBUfq)O#nyG#}D~g!C7@ zrt;M$59*IU8Wrq9)N!fol#S}g-3`E2@NI^oesSpE0z>zf`Z3Ga)44{u2#CHCek3b` zHC|b{CCF7$D#!J_R(@3uTQLfC=VCBC7x$_XRF{7mWZhDgs_1bBjY7l1 zV#7XN$MMUZBRcw(-UJkSBf4l8YQMVP!T}xIQ>0DN>IAv3wS!vY;Y9AsKMmaoz65%l zg<+%6sIb^bNJu1nxg+o%^4`Z45Wo|{8v>=$%~ne=A(DyHh`^J$hPa)0iYOwc5c7$b ze`bveZXr%dFlrQzC@dbq*M&2ExwG7=daM3o3Rp+kNug9WOiQBZbhecg&_vPMTi7zm z%xO$d=H;I&Mr?!qGUSEezL+5{ zK)bm~o$L{}Z>D zp3Rz8rq>s~V*crqF^(9pttPscW#qY0=qS1x3*+{d#=vd8+o6p3Fmy!#eybSn>rcj5 zcs2@0U6?g0i&@M(@LHhTZB7yyy=MXy^9+YlSrmVdqjU1uzy>-ek0kb8_8oR5yNM0| zh@&)YV~&;YsJtA)1u70phjzWx6QW1ezf;2Md!G88vE1%Gz+~+Z40X_KST%>yjW_PL zi71uJG7OUZGAez1ozL1`n$Ud7p-XB!kn$3JpNcVYP5hdQSlsxK+LMa0&dG`91{ND` z-Mo6yIlY?0$>(bi?LKegD|v7QdtcnSn9zKs_Rv(94+OCL!yfVSl9}OE-TV*y_t&a( zkoVVEUP}&M2E}|#M_PvrgDd@m7%2Xx4e_R(0s`U|RvAzALWPHB`y9o5;4j#KrXPum znP)X=zvxMk@E4OsJX(Hio%ElBiC?duORmU1@1-5el7Khz{)$?wvEm_LuitRmutTWx z^|}{kRIkgEdg_gNJTqKl87zEPQ3dm)pqHSDQ&W?9Y!m^Szwfnhiheq=cUjyuAUZ3`1UC z%f&NJ4S9Jn&zv4pbkHA(;R*K$4n-Lzc0Ep3mJ zF`{mRq9J>Tby7j2uGJQ$N_pD9r(2o-v{gUoSE1gG`ZbZ2xYbrY zBXBvY#jy^+e(LM*vOy;6?v9?@t5WJm;)8#~X-ZX9^*;YY*pSz6ki&!~n2%+ejs*|U z*G&%yzw4KyT~Ksr+zPr0_ASfNNoE=-I1E?OtVbSQ>|nJ3|U6SuuTotI>#@Q%efU!4wtD-M=yvAw7o1t!|d+L zp3An3HGAQj2o3zkyC#mLBUpVH$Wd~O2*T`lpYM9GL2k_}F>SsQZZ~G5=?!_f9TGiI zj4;g@R%Jio=h;lLB7e)+mfS64lWm0apO~q2(m}o=^P!GELvfv8$~ykKJ;-*>bTrTX zcRu9Xsx-HntZ?EZ*_vV<)&jk#;v1yz`iBH+ijEemeW3qw)v^o{(NGAJ@M;^_@@F&;`$DM0@p- z+xc3)Tl1x*OAp1hQ^fg_ei<7MHyI9nU%@=yAD#Nh59Smq$q(OMbeIA@@o zv;ZWE?***XnBiME=QlWgBkb(OWiWURHRIuZYhOl1)2AA?u3bRzzLtUYJ(Edtqf z;p`;?lh^j_=ispD!DyM6EsIrZ>piEhG5sXz<-$=@JbeG^S^bfJV5`|E$DCuw5xR1A z)f|(a^y(EXi4M=h_34WoMA5^!Si~XWRNd#bomXo+$_q8DeHSNi2xUi8Mk`L`qhl)(`xchsTFv)@!rEU2tcv;!!iRRWT}XT9v7a0w;Yl zO`oW0<)8ASkX|UagN@b(X$;bPNAIzn_Osca}3Fy-Kwc>*s%fZ)kH^jD!*bN!j{ z>x|!3&_OB!ysQs<@!R|Qw9kTIqLFB#2%I7w@mfzk>AT6zM-(KA5P_qjcNA-;L}GCE z`t)b)DH71Z9xE~Bgh|+vMkrjWU{^(Pu1W4mUS1|7>+c9+`v(T^`Ystf@8=wV6c93< zgGe&EY$I=_Z0j}iXQYT!$v;l3m&37rIhAzBdai8F~q!%#sq5ls=G z&_wE^LtX*#2@$?(gN4J|zCT>eVBs*4mdrwI2McC1wiV3pPPmKNUkGMfJLHw++vkUN zmCL=$pbGkD{>wYG{O;oIm(nN&lqWEaTGTHZq!5@q1%tVOxfeY(UKj9E@NV*>`d)4t z0bVs(3uMDdvfzYFmn8d8RxkT3`y(@wgNa2SO7DHdx9TPWZ_LIwY~5BkzTv=~@i$BP zrZ(a~daK02twZKCfxim5`tqU80wtu6NuN)dKD4~Uv61-D(D5Yi})z{2Nm|Cd5ckag3`&W%u z19+bHqB#5_6V|ld^HZJh;~SiCB-F;w;$gQFE?I>+KKcRFwwM-}8JVrHE+l@-9bwvH zR#i6I!tC=nOGVtw(#rtnN_nc8t0&2iRF1Y>yKL@6oepH6hBvczI7`RT z=o&R`+Omq6uX(Ok3{vj&iGmL_!nAKplr(*n04NB$K%d_P1LGRfW{)>?@K8`M_$>G% z@TQ!n5F`#Ofz@;t`?4sIeN=RW{YfMj3IAbNv1hS=!L!6!@?(SXsKNETus!~gP)WSx zoJ4v}(!hBsQA)1tnDj}FIr+7B5-|Kj>gv|~#k_UQIzFTR=1QCDQLOQ-;2!@pJL0sN z)2Y*;Tl1W`8?jSE{DX4I+k$q@-2G<%T=^fBUZQ<#ulmNpijOkxJe7m~4J0}f_iMHE_4Bo&3 z-l{Fb!VkoFD{tt02<{2X<5loL1MfdNp@+at;4ARhEQmZvJSw;-$lgO76h9)_ZX-Pr zyb-M0LNq4o^4?4b1fyW$FSrtX^vpuhklT&uq(~|Pd7?&9g9ru}iXsn&+Sy8+(xOOB zrB=4vtaK)-hO4&3Iiu!K1}C{Kxe^Q}7W{AZ+d>&>hisedfb66!@}QOOZGS9#k5yBt z^(XCbE#@6I%Iw3pA))dlDnjKiFRvgx^-^vn>?0f}lnxsQCNbLykC+%#xTnf?j%nu69#HPhNI);@2Yu4-)&UaIkL zoBuhZcFQ;a=8;oBptOMw3S~Zp#wK$jC>J}8AHFJL=TPbf$-1-=gAqNG$Kq}U1nC&7 z&fbobsHHAw%`E+tZe01hr^GJ`7?`S@q@*eVOf^t$Rz@n1DZSMM^L=RZb!CZCQ7h^# zDTVieqDfT$&5oa-lZcg?-}{B82bv)9?mwr;Mu5B{fDV*L&knZ#u@9YMwioln6ig+4 zFxiK$F`GF$7Q-1QUf&mumaaH$`tLa``C*CXsLEA!s&QIYpX!})iblt>E}vrKqpb+i zCciMh_J}aOUd$pP#*=0$7aF|szCWas*8&5=c)}FIu+L2$eKm>t&P7N+O5j-Ga4Dk# zsiWc9yN!;&Ppf-<#g65_`HF3yau(@|?MNa9cmjHhknZR%V0gAVu~(W1=`26@X`V+J z>y|8dd7-64(u{LW`=XJlo)F&gM0 zA$^qdGfXE`^xP;jD|+f$cxL_GMRNGIi}kbhDSmVyUtE~*AclC&@r~5)`$(@cVdP_$xi&pT`Tc^|_BbkY93?IALuJ=#E_z>)HBCw9;g4 z3^7T27;K8Qy%5E|q`IZL&3?=t!D;@+9z{u)kT`VCB4CfUNO4P7vO*V{EIF7-lRo~H z!#~#5(Oso$8f{<&=fJuwopd)Q#Ib975htzn7Du?QXn6)uC9TXjkk83buOBCxEK-XR zd`#wC5l`P(8tXDT?-O$WpS^#jx@z})j;`9Z4eU)T^jeVqK8F>Zcp@=Da#^x%%Ji@Bznfztmgbf*l1HpCZS%fp z0Xi{fakg%erWkUB*@7-C1xz>H=DB%pY+v5 zoS+#73=)4@tIytPYR=|U2$_4t*5JsD;9LqgHe&?)$KA*oS34TIxqB^ecAn)tlev_+VaD<+(U@7Ihh1+=*Zf^j#01Zn!x2HIY#a6x z_9FI?wd@`2sO8SOgpjg8=L;LECa(Zk@Z4%#%H%XKQo;5)Jtt$tf{c&aA%_UqHZPfZ zDaH!Am-0ex+e7oxQa{P2^vs~C9B_knBFKPoHpr}764Z&w3VN=Y5N14OP0h#wX)OVUJp+CsjSSopO&=Wi>TpPps2RR_ua2)98it4FN|6zes|zf^s}3oARfE z-Qylrd^x{?RaWX7X#IrmvN~cj30b+91*Ab^62Pv#^ypoC-43sJ5`+r&(4$ND?LEsO z#RkBC4%nLvBA^NV(j3_2X%S{;b=KWuOd^xrJuvou87gp z_aC37Y6W0B9`O-pGc6=hI$k+W!-wORL7`G~eMMqh^C-n3rx_W1> zWPmME)anf9kGdk-UFRh{lg!hS;!DsP{gUw3>Gu+qDk;lM`>$nwv_wYgsdw^)|F$nlp|ZpvseP}-TWAoAA{K! zf^Oayf|B0{K45OMz0bFpz@bBD6sPLF9M% zTE*r=*DBmZfE0Vbk{*4(GF(K8eF`6eroXWrq&LXO?QWhWUnbuu=gYA%@_E;2?j7r8n^lpjV=8b- zRVaHZdn@~>(%jP1cB+80cCMDK_1A`K0pmetD^+#tjjJNMViAd zo!Xo*-SRU)@dEQub2x5Wr!o0sWylRR#_ThR$LE_MF~$Pp2j+bwY{*mlW<6@3j?=*}1%62O_=sa9L z%^b;Q*xMQ~sJ75c!9vY{u^Tq?c98$`QrK*biQ7SmvbH40Sd&u77GylQLb4!Voia^m zO?pYbX-_1pYn>)FeW~)>r@K^rhECM2tbHrsOs*b@@jHD@PtP3= zU@nnO9CnG;HID8P!Aqi&*h$1tw(!T;s@-fI489T;%(VMK@K{1wPcrmFx7cD5Y!-X% zo3fa5iL7=5`+ZdI`PK(G&#csLSA7nz0)O0ZuI;4+>@{cFF{Os zV{M*=z_#KDT|Lbj>|@!pbd1f{Nv%oAOFqtw})5!9(HEaFpOL1=JnIDNbLWp`-CXSG<4m6A%{kDD;$LmCni`rxGP8 zR2i>4r@RK!P*I_JtPLv*ec$-)Y-dAvk|vWvz75(?%b%YJt|}W)hr4W@g#w1zRZPCM z3-Os%7RoVWj@Hk`1dY3;n$eVZ!SuQ6y$b035j?fF+8J6Eah-Oj)(E&ptFiH2=Q~e! z7h63&Klm>9*EFm~{VuVvY2b0^r>dDlEhLRvyljYl@MZ?&_GVjGGP7)oNS1lzyG+Xr z;oojM?{l_bCRu80W_Hci3X^B6^V~pZTH#;VB@jL>T1)Eo@TdR5B@ZkZ6839;f|ODv z$T5NDKR8fi;U%)Mig{`L+O(di|C#t_oGlfJ(nGDX?4L3L)&3(hi=xjSw|u(QgBh;u z=C{oC?8i(YyMHXK3w88`iZ`s|Z&|t*^2&=k>z@_iFja2+E|+#tJu_OJfs60L22n2e;bJL3%Yx|+y1~{UQ(`|n z*)nL)aY*rLD5umpiu}G%5LCJn%d}+b>}Z!UGoTX3>*by`0sq&O7G$&Uv+Wk9tSsd% zVSnUJX9ImfBCJ4O@w^1Zygh=)>|ao&w|wNqK3yhIm)=U3C-+G!{`22+UP+Aifc|@@ zwjK7*Ra;(VE*D9|p#9!%-Dqm-A!!&|93Frlsk0tv%JWRUB%HO*`mf3Q6|*||xVjU+ zp4`J;?;Rns^>Wba__@&YGi312c`K66irr1{Z>&zfE!q*A-Vq{E!0wu1T)?uf^g)=WIloTF{$a%)4$xV# zcYDxp#5^wPi2ohG=VZ6IbC$n&4%ltryZp=fgRHWAo8nfGkv#5xGm-(-J*xOE*GrN? zbV^C`sjGS4UM0Oc9i38{+SpLzMaL8 ze&*<^n(jN(t$ya9op((tFt~^B9e#CT=i&rh*d|&WA6R~3^Ph~T#_O}B5!t8YNHu@L zZna+6FRI}|^&F1}dMo8y<@@Bv9_QHO~8xJ_>G0;{lmAsoCtSus!H zr3g^$Q5;f$__@()e0^0Vaez*W*?ohF*Bd;}9Gz11*xY1nuN7Kh-Fp$ierVaoI}kJ(K@P_T zhDz^P>I$X{f*S%biQUJXC8*TSRsGb)2-XV#nea%PDEO+~PIwB%gumE5PI@anMu_N; zVouO;%$-*nSj_QR^an@t^quK;XfSE5Xp<;RbZM;b**GTHzSpZ`x4BdAh$D-=4F<&X z)=^N^fPm5vD;rY7BK-{20@W&2@K?13lp3f&iYj0ANcCFfJ1gHf(52WK3^$N;0%Q>( zgB^Law$w|i5EO)hCp4)ZXDr8=GnaEo$V@%P?9+u! ze6bjEX2ERLZxcZ!j$~|d`+_NwKo}u-o|Wph*&Cgo>c$H34o%$b-6uVMD#RNJ@y>!- zd8bMe(UL?=Wg@z{G7+;V)$NHlvN+Yvq1L-j(td$8aC-iLWK_1pYD*|0xy8(?nm;5- zO}~2Ew;=Pj?IsT@L}zm-^|xp(o)~AnWeta$2gbe0XHf|ZhrC- zg+kGy=vK(&WpZq-eD*tLk9;scd8AgZ z{L5s?-|rewvwBzqy4#xmwE@@ji_(4+M0%f2{MBPn^f~11TVV#xwqV_N71n)wSfSk= z`+84fZ=XZy$dJ_HA2(~a-Xc#~GV|a|Sl-QBh#A#NS_IttB_m{$WYil>8=cJKsID&# zf@S+<|GO_P)HTMtT53!GeEeHOEwaXrtM@3h9arZk_aIq(3MoJ^XK(v9$Cvo3uIB%( zIn)OFYaiqtR@LYJt;uUk{EThG7JWk$?t8s|woXz|6>bXPtGJ+m#$XCJ?JY&A;urW* zulTH}OmLW*0hs_iNWZ}^y~8s8<7QCjdVZk0;=g!wpvy=9&*JBn<4yH}5*z60$AS^x zC}|Ma*@qvZ)C+&Gmfs1@iOL1EQReY?kr4#q(E^me+T>jBLeuzrU?DN1pdQ_4R)=|z zx1U&_3+mBKvqPglU~Y`F-x;-{z}&c*eb8gqhqwQ1WImUA zFmEn(;zVH1W?J&v7PzE(+qm8Jc6`@=dB zx-%#IUJv*RKJechhV{$4FtDkGZ?Neuj%hVbI4OzN+Tjzo3d=Yrg}r$0FKw%16<_h449gzUBweP9!?Nw zIWj@nL2zP4P=rzt4bzNv3hYHI*68|P?c$1d@$q)?T;Gbvy6T43f~mf2_{_lx1V8n{ zRC{Quml?w`FT5PHb(iCIKD9;f*`dTVe^eT197?nF`aFN88Q7M73R|`4h21|UBP8L4 ziB!gvL|8}IoDH{i1!vmb;Dx%_D;ra7UcKx{yPLr+FHbawguQM3#7fRl*nXa`ePn=b z_xsix(#J96P2f%448HXQ=HENBoX6qq=Ed^P@W9nwVd6&Yfz*2|U`ApnBb1=Cs-G)h zLs6iQ2n31F2|mfX1qSlbqABv(y0oTlS(scYONK#-(V`^Ll7|JfTZiUUIzNu_W0s#P zs5!)Z)E0}Fh5U}CxrK-q={_Q%cl;7C290of`P#(xl%P+I|^Y=Hm|CgIKE2BoNt<1R1Zeg zcK5`DrTSRw`k}{4+Jn+9rR#QtSP#Nwo;HyB%(Q4gRW3IAqRiS*4t`hI3D` zPA=j|rYzp25Gt^Viu4zDy|%jaY-mZM09fU)4rZBhcv2OOda4_-JT$$r$F8Ws9>p$Y zPW8w}-@m^>&?>*H!9`rSDG%+(?82OM`%B1}&*GtWX86&On91Y9REyi)fWN6uxvCSc zj?(IAWMc}6I{Fw`lE*m$=Ri@Z-7Z7-xSUe(duS>&Wy?leCeK1fx+_a2g6l+ud?r)?sfd4>JPMHwGUNieANx16Kt7&*nf+Z3 z2IU0BO*oUP7PX1|9}S9FVO=!;ru8$CoE zIRv1j2s&~;C9?#qqaCSFZQc}#nW>ra>+S2pNwG;<*q%W4B$GC1Z&fqBTy{)&NpO<= zk(X=hwCz2|&wyU7K4BbTGE}&@hy~Isyk9XXq*Po^Q2+7B>d$XJfAS(6X@I`5k}tO* z{o#9+<014$oRD~WB#>Ew9hsVX7RP$)A+U9$wH^HaUxqr6m(*7G${R+SkWz_hcv5Ov ziZSCWLd_S?xKtfRL*5+Oc1}vvOUTYX-=&W5#0}7 zIRi6>4==f@WqCw*e`ugrXql|jyTg_gjQz8&^AIEc<^I4}2Ned#!X!qf#Fwbbz>*v3 zd$|d`(bp^a8Z-22;g_y)&qA@J_JY^`xB!eNU#o3?_~tBC4ckh*&9BS1_Ffyfb!z(Y z*{`!kuQ^!;P;GeadJyKt&KT{Ta_R1Np!$P6n+*%|RycFcgEz7^vYc5bT!DciQ zSUzxWevD*-a7MFT2cx+WWb8U(01A1iCs;mBi~$+`OJ-UvPa)yvpJtE8g!Bg0Imds_ zNxh}U$4>Lt2*s=+(b`a_Io3|vnx6T|Zwr_iEwMfENk%^V$tTl>=G{yp%ciCOX`P>0 zv<(lE^NG!E1osIy{N)RM8iBw-L_$S=Ao*nKRYwQ&}4jL&qIvD!;(v~-r z0LiDUPw8$+9;cRXSMTZkXWIGYF`QO>kZR4Pi&j%(^FEboy#BBI!O;jy?7gEAFmRMO z6gYb8oa5oF_97f6quEWDQT5F0avU%o8yZ3icZ}bY>nK8e?Qs+JkwD=DzEIE7#)2B| z#je!o>9Q@hCkaZQ=z1={$(lau~@iss%xryKlkKF zY*_?b8F`Ft+$_2eh3eJw*e@g@agNDgGD!9TV;hlnX5w(4?$TS> zsPhCq^_Hp?K74;w&m_6D&B5H9bw&kr28YkTy!88^T9v9*jn{fi(K5Bx6Qzk>D())3 zuFS&$=o-JSqyY3F7n2xKZ#2EVS>0AypG zUsp!}BDVT7W)B@%vVL&Y9h)_GD2MxfUQ>L(QVM_h9Otglo1SCB1T&`l(i(yTAwF=t z86CmGKw3vIoIf&J;Xk$pC*N}Sf-{5tF4E_~_scX1%x$?eV&`pEhPM_5QJv{xvf$*j zZoYMTM$0?b%(QAvhwCsI^cQkpCMlEDo^gEqQPL~Xmmzo;-a?*_EGT_K3RM`#9dJ!q zoroK{ama_-!nY&h<(#2hor~f-5pn)VRa@{G`}~kIn(;Go6haycx`*95Ys50z$H+>= z+>(?gHo|AXwk54f!k4FflwfmLClb=Os?PZ*S!CmTq|Gy2rK2&;GeRi7@zyI-J90R2 z;2m;#O=170LV&m3BR^DH*bUOe8mbDGAjPhs2-rgr#To=bP$73N zIQ#7LzW2)=V}D>d7{k4@vu1hz<#&YYn&xL=C3F;)xY>jx)HBssqXU)g@hjdi>FJ}f zigoNW1t6p}l7CWoS$IcSFYFNh6appDB+)F<649z-x&o4rwKEMo6jfy+vC_F!nJAYjOjDj{A+9DM;Lh=@($`tbsyl0z)`0%>_tNp_ zmQ|CR)Q(L@An4k5=MSy+DNQ}>BVL-6q9_!BN|8kI?&!+iAAN3p{pr05 zF#g=iUIW7LFP}bRwFNI1h|v|VePt05r~ybcj6ef&#-V7~`MGhjqq2P27a8_Y_Virj z_Z}H4SGw&ty<5XeZa ztD|4FPFi;~%O@BUfU((u65>)-(st?sziJ1T4=aGNlZ7TY`XBY2)xMC?-NcZF>C=KoU$S<{rYYWJnyf>=2Q0r9ob^<0Vh*to%a^17^U7sE69(@ zZ`D{9h}%Y(n&_B;GPL!kF*;~)O7A{JgFiSwf}zdGVgP74d#9Ru2`b#w+BoXLII8zq zoe%g)Un8K(L+$G7Nf4bH8MVZJDq!IUeV+}UC==wC_$8wds_clX?HcLuaAv`>ug-M!S7ezmkK70j-5&uC~i!?u@~d-(E)Zd616@| zo-zxTaF|;A+M*^iJbZ2O(yCXCS1dj)&h-S>RK7sI;>(x72O6ssqvRG?Pab_ECZTF; znz`&#A@V6`V`b65Kz~;V51c z()c%Ciw`TZ(T#=QBgI$9ee^CyC;90)b<2Ib82S{Y+iNpv=V=u*_z_$ib>V0u*h|_M z8nnSJ7|O&uLVz>9nTKZ@EFaxUJ8M&u11{2U(Vx-V=u1TLq5%e*0cJ_|Gge8sj0njS zMge1igkLE!fv*E#X+kjI$VRJdJ6Opd!ir%Xp|0y>lNvt;67P!?VWch*z<$B8u@(0X z9V4A2pMAv{TyZ9J+0BDNkN6K18=yN&(2(-lAZj>^Lxf5CINZ30?q=r^Z2}UULNlnkN<$T zSN4@Beu;pyHZwIzO_=bJry|YEmBhyscv~~9g!EBzh2Eld{Ecx!5E?H8@!M07AWB61 z>YSB2uvHwm5|6~s)GX67(>fntPPr3@&D3nus?xL4`Y`3QaQ$E}m}->AR}<-r=8AOX zDvDr{I)i*teo}P#%mx&O&P>VZg7KBp6aJ-W@W(J3ZRB1uzU89WYwCpk1p5V(Y!lq{ zZq82xEbSGBOB}-uFvd|zK)n})TgMUX4?Ca^=i`NpJMd>}rNc>=@eWlhRB0Oqd;9Hy zDGh%W*3oikd|Enf1#9Is+5;M3-Ojpmm*v%CN9s0d5p`$!SWbyBT%^f?SqL{u<77#)vJS8n>1(+u3hu-)Vqe+xb!c zOMwRy=vdK9GG6HIslNJ-{&^=`-X2&v-o9%j;x1TC-$LI@7t(QmOC7zH-u8+9XWmop zy}bT-66U>u()fvviM11MTiDa!u3w_PADI`VlsRcdE;)0j2FjfrF3?z+j)qSrxQU`Q zQ|9H=sJA3eDvV45kbjG(8&;NLRea?>8$yzy{xq?>g?>*l6Y1I>xp^5 zGhQ3-ckdoETap)^ccSAm#`_2ZJA^%fx=53V%{f1iJIHjh1yPSz3E4s%`;jFq6jlnW zo(SIwuQi^}zVlpKLc*>j`85vEznRkEqKJ?v=*1g2m@zk%QGi@9z3p#jG zQ$KJOuhD-zXKmFD|MP)hJcL(ocwpI_${PhdsAIqV5H@N1V3R(lC&D`9L$d?t2>Ppq z#o7AD>{Z?O+Mt7jy@C!T4t^avPHwJLf!2ip=;Zs=`a103zF(Yd)xFn?;7zr~W?!K5 zjiff(ZZ+`vk0}5f3RwNPa`gr%`U(~$E$N$R;t|u&Es0*wX*HO3CeZ&P^*=v zr>pg7N;BjT4)uw~6wPqRUT~l?Z6-pOlkCLX;14~7&jU%pK&?`yg8r;hS33CHW%`G4 z32ymtY)60thQB^!?*{RA)hxqzeX2Gfz`5_#>HxrZ+-lz$93 ze?QDSP(0Y?KiK9t_+9A%H)q1m;O*P>6K(bdmoP)ns#zh=Xl=CK8Ew}{bUiwlNw?hC zR{rnEh<~150r@U(>2f;4&~gtcG-22>7Dt6V;)Z&!2ptS$L@|12OvNV}1pmLs7#A2f z84DMhgtRk2AA`iwW6fkOX1TK>S>dc?0V|WG<+Q_Pn8btQGoF^a$HtYs4ZK(08}qWm zyjN(19pIhj_0BN*m4BDl!~26kZKr*cu3=$A-UOcT!$C)33q zVlDSgQQ}1LEALHe1@)Uh^pLK$^z{{M3=ij%CaMr)iztD|j@Y-T%?^t{V*f$$BC%#y z)r8v`{6!0*>MSK_!aes}Psv0XSwvO3aIc4qPMTk(uHCz=ku>txsD8B9J)jMS{<7Z> z6nUvumFu822!osfxWF$W?he zuv=vV{lP@yJ#q@$@<&1`EK6RYv<`x!cpHsG|o4W@r%}T38yO-B$+>_ZE62-O_}kH^sG4 z7Njnwz$#%52Bw&QmMixJca$qLJ#I{6K@!RPCDTd`W2paiGVSw&6=XPr(LAaZs#ay1 z1ntlf-9c~6I%-DLXmNlq3RSBaT*BONrH$bTV#~GWMnpAI-cyJ)o7NjSY`f==BH&)v zVE+kv0n0yyyoVM{3DnQ%*o{xYNYMv}*U?&p_t7I$W2oHkEgn#@q6+>|tfs^hs6wlF zL*1Eyb2J`BJd9NGGzmMJcjF@aBN!qzs~` za+ndaoyMj|EYn7p?{MwmC}^fqu55oCYci?tqhI8GZ?GwyeGt(n!%n1Ynk150lUAZxbqY!BgADbq zpQm71ls=C-+7kcQ0xqr5&j--GEzF17mLO79GG;^VM~DPr}ps+NbpgcRj85-j;>0s*1b2YBk2aboGO=LQ?Rs&5L!T zi>kipK8^-XWqz?=Dz8I}h$gw0`s@~b0J z<@u3XZXr_>{)*=%f&(0;KsE4IkV??T_}iR)aj=xXJLthi&7kj_tI3hK<6Dd)2xjeI zunRT-lM+4>i7zDxk(XfoNQsY*JdioCVghB83UUf5{Huhp=U+IlJrUaLF{$EY6akmHt@<#iyRm zVftr%+^|JG{uI4#N>ls^0`uM`bhrd$)%-1e7I;kB6);>OU3s44R+wr;tI;rrpeP2P`A)k^Ali-q;nO2gaW@?J+yg3ncOJqHz^<6(JJ1)|0(Vo#j8x1E#4$#@Q=m$duw3#?5xb#hmC-ee3 zO;N0vs;F;P00#7ZyOZa+ZXF8}!m*31Pdtj0hdRfTVi+lma`F|1WVyCs{WE*y`HGk_ z**)0{+3!Dn2~&-fAkbi}kWzZm#k>GLEnE!k8#m^jl;C%tKf&hevOI_u>e zIe?8T@_e}xo2Y))WSr4MId~1}t_rz^f!cplfT?aG zv6Z+=)=0KW@R18OM^YxaM|mL`q@aG-_~0I%Cq6w`vK4O<=)2U+RQC?WYxa^>o!1HG zWHj9MIW8iAM&I;mp68^XeO`stlQ~@hfamELWU?{YYsKa-(qY&)3Jhg|G;g|}Y?JIE z2QRvCaRobJHwa_=L38~C1v~|fVvq?~{aFawsb)N9d|(VRfEo*Sudpx{-ZZb2HIEB< zpX=ifv$9zhH4!_mRr{1h>}c|vx~_`L&1NhAy=qYv4|hwL(AR?$o**Jx ziDMHExa;HB2@0zI2d)<4CHA>*cQ45%Ur&ZPI81+YQR|-g<^Mt2A+%2fbpOZ(P;Ss9InM<9l?|WPaNH>-WDtNNF7>Z<`s@ zN?m6o|M~#N_XHM>0*ht~frY-%LfM|U6>{`e66e}920o2#nQF5J%{Dla`F2;R@}YS zvtI3eB7Y}e*Sb<;fj**%lenfUa$g=Mxhd8wz!>p7UvXXWR)I@Gjta%zZ+nf%He~Vp zy;j`1eV%IjaB|VQ*024fT^sAQGRf!373AEPM$-YFoc%XA8%|Lls}bJ&ZQnJ@1B&>) z&psHEkcHP9?%tpOk)gOxVBM#K8LWltNeypZ{8&Sb-K;LgIuYyP zL%6k4Eo!M2{RgQQ-cwret@UR^@dZouu;Vbn6fA<#PO!-{`+}v-oxss9BA?}f<#_|t zAxmY~&@+Y^vFS67!RD)W_7+#p(_=Ujn_*GODcD0~ksf;AcjS!yXpjkH9*9kMvEuTV zh*yc%>>=*kyf1!K-mbIIs+#`Xd~#F;POrT$1~0|1VnR%o7)tCJP7;q4@R-fs-xm=f zfyS|e65Fgq-j`7kTJKpo7)TlCK9K5?Fh0F6;-H{65*Vc)5-vQ_7jZ*yJn3)boda_N zq;R!QKK(sWdRz)#FdngQ67K}>67M!o%4_HGFQkQ*HRPZ|ZK0{)LspS*Z`!G+br#eA zbbWM9Oqlw|f?JV2InAo<$Ugx_S`lI`0Zt{l_WI>Q8QUTCma>nGJlicjB>jBij9`}qai6UKjAIT^ zLVI%!^XC;!@AsZd-IBS&jOxxbnv5-(0lxmV;xcIc^I!Gv>Fey*ad?nvnl|^PBq_&e z3yKhD6=HFh9dimz{Yz#pHKh_3EH!;?W}+}#Ml`ipx-eYO@_ngk{WJjxpBt=lh;)}+ zYQg+Cr>lfZ;1Yj-EJC)Zj>Z_(uG+8cP~Tr9t(Nw1X7rK18Bc%O1J^rSp1Ew93@~MZ zvM5=i?6~Zr?3OIX8KkHS9E*)U$a=-5f_u6R8bGh)p6>MPzpd`+?CI;94nG_1g*$E) z8?CS|GCmvcM!!-Fij8(y`_8X4-m|D#-X|o904~V{DeM#>(m!;(saVeyB%JLb*oMi))AZ8rE%z}21k5#<*_qXD99yTb>`_*#M!*iU=BN+T=#t8e73 za}@)EU;aEBV3!^9^WQd zXO${~{{!0NuN}=g_E~W2q=^1eJ|qXt^g7mc&NzlwugYO}juRu^&poM<_k?#S^s-fI;n6{YxBFltq$&icN~cyYLVL?y2!G1= zbig_88aT&YXSG%uX(=s9tO>o(d{KJv(Q5J*Rj|jRzRUuJZK&0BZLz6%t9XUjvyVA8 z!}W7dKHEdMTyQ=as9ja8Xe5+OI=D}@d8}^hbM}0=BfsvMiuwI~<_vm!{QLe4lF7GP z*-iJG7ZP0Sn_b9z5o8yT)g>QRMO9>=y){Vguu0mQt5V-G>#?f;3*h*CqSAiwNtNl| zRq?C7MSWWG$)1$>S3gqHWI3|3R{Yqee5qNtPKI}i>8X151G3yu{vVUHe7F3ZT>U@P zwr?r;*k`i#yp%HT0o@)V$SMxEJAVL7FjZ`7B);D%s10=d0329+84WEdAdw3C z|IaZ+W@RwXs7D$gtBG(mC6_iegxK7vO537&MU!x3i)LtrCLz5jqD~VzS`^XJpotKREGkZV zkANc~PtJYj8a1bC_H1f6c=4~cz@$fT+Eeqz2dnHdwC&6QNkLNnb>MSg_(}b!Zuu~F zSC4qJ8rWQ!e7g#{G8qHENSxWAZgPrY-Q*K9N*}dowP>dpRy9oirid}FfPY*uc`VGB zgBueTSX`7?KG*C?Ei6264OPm!MSgO*Uf!>wTcxS}U)w)9`S(fdn}*5%wf!5F2F_B9 z{|m}<$87(EQQQB4Ufo&s{T8_G|IhsO4gD7A(89@%gb5D+6K2d{!Z71W@9G?144L;y zK_;GD#z0uggcDp<*RO2%rOF%VV~LQz1$0xvKc@e>1q0+T=Pz`Pl@Q;vl23B9VL0R6 zdyGAd!>eGJ@z6!JLpR8e$Ztqr!P3lcWW3yMxYa6T9>s-XwR+OwqKJ|}R9F;oC(wJh zW=SAY5=gich};P*gh4coI!&}rlhB}vhBjytvWg0Qpogl?fYv)t=BV}ibA!X-n7A7+rAN9j@ zd=#vOvpif_h#VpYuBX>AS{a`he;C*4Di7(e=??1-4bzt&2`oTiS+W+3d^T(lxkBMJLxlaqW!OV?pAXQyyM#P$*A|^i z(|RW~*ijYu=;jB^3M$6L3=HFijT#=?_ZR-oC~ZKF?_erNGh3C1mvDm&k^1QI3U>4u z;em=}nK_9pqn{@#?q|{ROsBCNu$ZSw!KPn@vss*S!6~W%_O;v9$t3RnCVXN4IpXgsO z!NKyi-aj_?)5l>+2g~3rdtV*9DX9)NlOgq7V?#J39I2@pyZ2aY-mWIpNSmv5cNy)h z8mvLL)+qH?ZLJx3dXT!a%A~1^*t(+z9;wIC`In~vM1-@U&yb25eh~cNobY9T2Dq+F zXp4arqiOX>0LW@kMNid_lOWpE2~}421Rhm+yT zoF#+)lFgDmw^rd(z#pD=>0f8lGk=KwphZZ)2ZxpIT#+!mz=m7mW11`^D@ds=3Q5 zCU24Ll>wpbob00vU*Cjeyfe`wohrAIYhO0oRqoCXe65NdzlVKa5;zVc@|0b*{vgN0 zwq!%yyH*ZbASoIM2%B?jtB4J0X;G(&0;Mjev<8aZ$qy=p3#C=KCqq||q z8k0*y$Xc3Ga~;YJ5AVF2ZglBSIt{=Cfzdrdgr(m1ruvsA0^k!d%r)W+V ztFOk`^MMyI@=|Mj$TDm&_WbGf+|S$#{9ZGaKHI}7PB~)70T=pe=+A~?Y|W?`dz8~k z|3ufx=t)!hnNCu2)@aajk5+Q+_TH8YFu%}_#^j5^coC<@UF-?X+Dt^ zbaa~&e{=5M-bK*|`W&K9+r^=7J5D?JMB~G(({@T#oE=K6zz4%@ZY?pMbeV&D-F5kw z={kp$q1Rn+`N{AZiKp!?5<5PI6TgP*xOH>k5os9f&K~u;gY~lSIRs$utHiX5;>Q|s z*}DQqamkw>KvvX{i`Nmin47}rW356r-X9^DaOT3f;-uN4r$UCPLKrE!dS(+mDOnZO zS`{7KWmV+;)fT@X?ftQ6ww;=;D>S=nb7$KPI~r`ohmQ*ni$?htR%uJ(l=E~8K8B-T zqt+#4SOqTh0-JlzG22}AoasK|9XU=G);n|Hafw^7Bit2aS_Q&SQi*$Uww<=Y)?}+d zRr{h$^sfaG*lXF1<4tw44sh#IC0a%As~NK6dGSJcF+0IXeku>YGvUHp7mxjje>a<3 z`=CTQ9BOU?o&Z&bKKB$TzFiTDM8zV|DYTT*MLyCX(N1ZSC_n`0(!0{x(k?0NwGzoh zIZpYOzq6L;xM}A2q&AipPAf=lrsX2b3N7zsXZ8H0Ph>dCeLFdjn*3|WO`WBa(%_tW z1`Mi3cdK;13t~hwKoa8w;}YXGL&|7p9FUM$J+~?<>R0@1?;v3VyX5%rV1*ep5VN4x zC(?79dnncf==W}#t*d5jr%5s(S($}0%6OL8Np2*(Gdfs?=**mGor^vr6Y4*f4 zfcbDBfHzO@{LOiXTS_H^4h69-5>%(aJhc@JpL93G^&DZqU7k2=*x zH#MD&E45yEy3qJPJZ@@67<|iPhUxV{VogAD#o{vZp7yXA|GlNlm!*CTj@Jvazg&l5wtW^k1><6nBmS~ zF~Ttr!dBkDHA2A1WSob6ppO{<$F(l>Eembpt!Mq>!P)CnVLqG_xATI8PkBkgm#m*( zSi|clTvfp{p}&7;*$~BegI~A{9JNm?u*#&LpShxdIs0R%m?Mr8qbU(eRCS$^tUMQS z+R5!!wQ-z){FB5qQZ|u#ig-t9{O^H$?-or2!zz6hqh-GE{5RI-3(tS5{Co3|+&q>1 z=8e|x?MwLb%$3%InW_#*zKxbz{>Uf&aID4V^u9Kwm546FJaBsatAO%4)G%-~iWkAj^RPYm;@?AnA= z*XoyQoK`LqRI=*@Cvm`=Qm_>!Nzc84KE4{`+v@LGWTQ zn^;SIey#pghRVtGyXi{zMK{LRUrNv_s2ZvN*Wvt0CBNpTVK+PpQgFVTWTMu#O0~;- zl(WwfMr$n;>cS|LeR8N*0piae@1+1@_d*uscEd%A_j&){ot%``SGZ@ z>g*lk>t0hiH=^$6Ns){1`T9M4mNFE{R4oABU=Wf z`fv1PGvBB`r^~1wve7yi*@<^9=i9EGusnlT=;qA((*IPWQ5_75)WrJYPxF`dV`5Kn zaN*>$8CJJ@QBj7~!`{T4S+{$U+r5N`y~xAf9IUsC9--9!N+#4pXmvzW~%9P~Q(&tj*2kEM>XH;a~ zGj?@vnv>bi_o3n?L{;)e`FnZxOA*MQc1QMr@{016GD4XopCt!N4H2){}%OY)1nl-7wGi`Iyt_ zluh?Y57v9k5$Os_@#za{N%t9<>cQsDEmj7@;F;Ihsc*V9Y`%p^B2V3flAQs>SkD+Q zCBTmHQr&i}D3)7A3nFif^P0Drdb%9;(ZaD>J+cR+!JXCZJ8~{MW1LG_1X9W4L!0s8 zpMk%e&obPE&$p#&uTT4tK*->_8drHTf*Dae7|CvYtf%$Mgfom0F#|Bq+OHPRBxH0w zV!UB|htzi5%Lr^)uB>&T*{*?F-vg5)ATXL{^N7}ur*g)e!#fNfn#2|yx54p_^=P))4o0)NvJ2BDO@a! z^c*B+@Afu_)-8C*{{^+YbN<+9XZFM-hn_sYN6coA$RoiaWp7p^p^`Qqlnd#S-#yNh zyjgoj^4G__q@i?nDbNXQl$ZyYmkgJ_y*{s$@Cf@c-26icZ6$jg>8oYx|M{%QEW0bI*+WsM}lQS=a6fL>(7z!!+}V*W8Y#&N-brfzRdU0bp*2 zqEq&9ekbX-snoWesR1<6xGA2}U^v)IhS9OhQsy1$Sw)BRr!?;mm8dYnrZr5o)(@EW zmZ{+zO^mfxfKmF`r15enQC0diKveN=Y~?VD^VY1V`}+|VP}zhEdTcX4+M1di??k%k zwTg7p1NBup-=xka;nVw@9!k5EH00a-AE3DjfIW!ts#J0E##>ml6df zyL%FP1&T}s@%-;5c+vUz#?n`L2ZcWaq*Hv!aO!UG{>N6m4>0h+Rii~w=F$p>;0bOi z)?B+3JGd0{p1NZcFP2~ijN&HrWeyS-ONXu%R-$~cw0DZ5DcghFF zl)VLbPOWx2eg2XI;n56w0Db#O%9nzQ?XU892O)Y86w#~c&*>lNgLE~9bIL1bw$FYv zV!rFj7B}a^YrmWU3GbIiaNX&!2x1?5ZuHA|fJPjOL?Y$!hk0-8(1?mi^%F7UA|<<2 zSOrUae@0Aaf%&ZE&=z@aR7_qjENA)NXMyvtnWPCQQHxyp%b#RP2G~(&v;{U)U1X4) z2p=}6I1#`vegt{H@{fcp!taDU0wEKWkn1=tt?IYxehIy3*B+Y^eP&?R6QZ7TUjN zDosEi9jO))%asUW!`@3tF1TwLCBrNJ9R@joOc5n00jw^Iu)HphJocI%7jX@~6RIrV zt2L4?Tg8{ez;1)7Z{f{kU^O-S?wpq0fwnFEcZrkio`}A`%Y^CMt_*k`0UC+;X8Bh< zQSyXRKshZ2Z)F}*ME+iUM?7EtQub4vJuKtN@zUQM+M04xNA2yB29vs%=5?P;*1aAu zCN0dn=6Y2Uq-c~R4J<`g4VA(h#A`mYSX=F{PBINu9j0D@%?%KkIYK8)oj9r)Bbcjn zjdZJ2ph6`5e^`!FSKRN>)P9D7e;Z!L3SPhk8IEDslmCz{mY<{OkUs~CVbF`})dcV+qGIw-B(v;h7 z5%$Wu!9HyD9(tW0e!a(m>tH7*m2-w8=HNZG#pGXMH&QJ~QKj(pfzYc@*XdY$zbQrZ57zrfdgF1a9eQyjKVr2p zY;CJO3BhXo4hFr!`fdF;k7F1x0F7bC@M458aLxV{qx|TNrR+NyA<&q0RUNGPb!C7a zzj5+-C4ur?wtC#gkB&Q{?T-pVKoB80`d!e~9flqu5iOCyk-*lomFEs0P(eq`_DGcj zU?(e;b%rHo-DN3rx>%_k6;;ku&YW#mmT{PzKu*+FAalAP#6O|CoF+~eBowk$c~g0F zc(_zWK;?W87NwUH6+160d53Ie_U=i(;5tultzJ%Yu5PZaXNuU}1L){!FVQE~xXcLWf}GV;qjK z(@tUQl7Sg{5&7-4!pM*1LF8!iI}tcRzC<2+cCIKas<67@#~jKMy4G?nJaFwr384UE zXz1NdyF$^BsnX`j=Fq@unFj>dQ{d=j92~tQ(9Dj}F3|etS=O2^Q9bp>%%{BDynN6E zQCVPF+hZplHE*5H>FBmhRt6HhjUD^cIIplVCgMZ;g6__iz6JK5C`XrlIy&IjzD>jv zfg_?^5o~1>t&@Hc9hTlB4W4KVi@MuO!sh6vUWe`&tPtyX**4KBsnz03n_FZ5n#)ra zRX4dee%8Zjm>%JuYA+3x0QAT+QA3Zry(kdkephh}9(k!fBl))Sn*R-;-oK$((IPxG#cuPx8Tf+WwG_k|D`Bslk0v zq(hV1Nxh^86*1Bj>8VE`Qavncm(g|UL+NYjH)$UkETjeo(R>|4&2>E{bB6eo+$u`p24&pw_wQka?(-e3?+#Lvd1eH2S z{O-W-ZI5*;9YD`p3jEs(oeCq1oyf+OP6jl*=@od=SEX2)N zj?T8xsULBfINM`cTfi}TFptm=W#VL9G2-nY^hcvYPbE{_gq7AY&!v=Gak&1X2 zP(1622*D5tX+)N_Y3r1FpDkJ!P)5iQU~PhIPd#`m9PemV6Ct}oN^qT+aK7_Gdr1jj z?MUg#?&&3U5lWAFcfQsahfYcuu4-`{19dkUKbCi2IeHU;O+NI|q^d-_uY6O_grrkP z$MMg1;#aw)+BtBl&n_8C9B*-0B^yrlC!S|$sAQuT$LF3b?2ymNB~WwC6gQ?pD=ECr z%}s5C_qns))djxd5N11QKfdSKWfAh3tv|r_QO+u}2*b))XO+W6WdhNQ(yBiiORkdH z>nWqT)~=$eGicfHC1h}H;J-=n;)K#+{-gvjqtziz>B6Fm6tQK2b#S8Nd5@~#ME}t) zVpNhXb^!~^D|STNl>_oa-s?TXwTo^|X$LYV>Xup{^R4RaZ@Ds74y92_^i`g3O8^hp!Pbu8$KLoGf?6YZX^!ls~G{ zZ@6}{8!6YT=89g3|6wAlj6#twm#d4ZAI%F5+rXl$hHb0F*CY=l`^8@+g%^u7X?G0UusjL=Uc8bN%10`0L}_}e*WI|!Q;#CH@4yOm zc>l=}T&M+J(h%u%VM?_h$x-Ml3=>j!2@eX-ChCK|)QaKSyK(0#y&?=WYvadhk~B1t z0~(qH15Lz0Gj-~^05hvND6_}2H3>JpBDQLlBDcIEVxiu2k~!pi*4ql{Jyb!+s5Fq} z7@WL;x2UbmxPjDHjsxLFjz#Z>!8TRjj*lo zVe8}*s|s*2=@Rwwx$H2ERKYraV4Jxfv@3=dgEkC%)I9T&L&A-VT>6ZrEqa;pjEz9YH?++W^zzIc!79NqzHKI|_{ zLa&F?>;U99lmClp8!RC=kgt;zXiShQdJ|F0!KN!E&vPOm2S~l{416~DoqQxO4HI*Sc>;r~b2=Q>> zp&%t)?x7&c-c!^pz;}wA9&;?nZP(MO!PG5N03EjVKwZNI`y3}8MZ5cC?76S}{U!!= zjbcc{0Gijs(OX<|7BV$$F54@VA7yy~oe)~ada>91+}GVOImz^6>fe07KUe)0*vJ~) z*4OzdjR{Wxj?-9Vjv>dI18d1Sn>hBnIVi?I5*(I(ChUtp2`vtl`xC1}#o^~NTDIkj zz#yl*DkD=TA}qb{=*FY7Bfw9QeRxnZg|`jRC+#aVOdRU75dTA)4Ywu`8KfeA#h6tNyP_DSX-&hh@@ZFmn32_==wW3< zHE#LKo%i^u4yRDR@^-38%VZGwlJrB_$8s{o=fxElhl&u;tQ=(-c0F18!X-}{CV3zQ zubvK^+joBuHV)~_5~Y~zYUKrZUGrkrdNB{~@?v^hCgKD4Q^+7U&Vact(Jpf5_8`R^ zE+-<28WExh2p$7Y%QjNg%(gbxZ`!V)E~Q$UQ@PQSF$h9ez4c9Vs;mLpn7Zn%UYgg} z%jzRT`Wj|}{!PQ$=4(=M)b=QD`qOV>)l zHYrOME)&T9p{9eBqCbiiG8364xk<4`_Dj*WlRPT1%kI61iP$8F3Tb}+_64Esi)>g% zMXYd38)Tlh|A$oU3K~X9#qGb1)R3HS3i?0QF__=dnu{C#H7c+-u=T@r6jn_0M*j;d z{yB^6ij1L(PY>g$VhAWstyAED;(wvVaHKDTJqV+yVrRvFP{s6||3wu~%vkz0{(+420{O#ikBhW|3MW~H0}NuReWKJ>i?pOx9QFLA5<}qVmkd_ zRB=0!{=cYVwLkx$iZxgLiz?1BjQ%gGxO8UD|DuXjNB%(-1H~w+7-F1fq>izQ*Hu$r z5DZ;|h$fb!tm1JN=GJdX|HTz|DI5P6R}9I;|Kf^c?Ei}^uJCMwWh-mI|DRQi1Bm}0 zS;dV1i&bm@slYg}_}D9)SllrREPgynEcS!H`y0G9{x7Zgnu9fB>IP}WUJyTQwieQg zgCMOK!f%n;k&srr+Zvez;kU@#RBMEG6#k0EDQmmusg1@rhHDnfdS|f|Tz+YM1XN@fRV~s4eB{(3<#yP;rgTo%`HGO-;&e#F5hn(VV z4iH%EINKU^aygb(RM%mYKr_#x&l_z*F~+&sh#9Ad7451vEJ6+=w>A?70Z zU^T>?HN-R;Von)i_G=C?)rOcv-~#3^LLocVo8V{RiZ~AbScwoOSWLBPRwBFxjhjit zH|QMd{&R@733Sq?jJgIC@FoMj@5df1x?p4#N0GMXduluk>1Yf=FtCnxePgU~bx5Ap zw5&d}N z(Z_ojHwFPda913 zf)}3^{A>k3Ok$xAQgX&wC~>fMWILkMIk-YG$KJIdOyOHfBw`=Q8{u~$5NV3kM>+?W z&v6I{3Jbv&gN4A}|vza3eZ02ae>=5znai5w`MWSugMRl>p z4t3~j5yAT&9?ZdWIeVhO^t(xs#6}i*!%a&9=m->Rv6`bQv~Zwp_MWRsqK}>M2BnM6edUEW0DCmjxWq z>fcMYlY^5fSICRup$g9i;L(6N6T2(DSI+Vv-I70(tF+0X;$A~mQA|;oE2__e+d6)V zO^V%$Lkf{1Vqc6pNQ~NN)S&28^edFflVKWwI7DWsk_-~{tTvPPkPnkVHu*EzmEJ<$ zO8-s6Z3xt{8D3#`xRz2ZZP!--`5uE6aVQOOg=+Mwb>B=@3TEBp?VwLkbmQ(kkkYq;%et)52 znCG_(1#w!~iYJA7BEd`!3yWhNUF#bi!inMd5R}^r?BnB+RF1z;nbTSCx+>bI*uA>Z zJZxY>gj^|%w^(m|RD;v`DeWVV6HB1s_|(%$fBlj_2oKDy?9NHG`#$9}GfBiL=G1I+ z^@q+Fo+i&^_t(ohD}C#x&_~l@#2BZ~{@tgY(-XOS3>)w|OvQgJML;r^ES#7}*uvL1 zP)$fr9MRQa?$OCp%^N*xpO3qw##YTHsGn0>ehvYXvURe(^Xho5yidFvzxJp7jWfBN zL$cTn!}hZFUHj?aND>O(PVn_o3Y-vl1ncN^td>7GekVNN6T#4jS;#M~_WabEN10NG zzWn`$#*?qV_WTtx zEg^$=CV{penJ>%~o`kxf6spd6lTh zH^T?(POXo-o4`WYD>GIrqbbE}WmF2}rqTscH8<&cDMuRj1Y!QnKOwy&{ig*L!&^;f z%Ek&WQS}}WXR-jr8)IaJz5{&)zWwTtWGYnO{*N+3p7OHd1t@q*m{0I3c}Ct0ABG4o zm4O{Wp|(!GUCx)M%U{6aJmv%WRtnynH_iql>GZ}Crw*(sc5_cQWHBo3af@X4Xvlpx z0jtV@)dp;Kbm85jUfj9H6?xA5tE&cpW|{tUsl)W?Zyn}N|D{kRqvSPw$gfdpQD5r) z)@V74xR$lek2yn#m%?8Vj^75Rn>y0xbHeE6GxpOr3sW{#mC=3aFX;C4zjPaD3-X21@LpT)iF3{KabtIX|XR{ znOoo-l(txXQXHJPhj|1mQ@JtpW`+iwxDSn{?RuPl%vK6)06Lj^@h%g3#^au(Ka_ob zLDxqkw3DflF&aQt)g(F|Ui1HIZWil>yjezL&J6W=*~Ia=LWuQ&&8z9OJQ`kjf%0cE zRrUjmz^}9snmQe?Q88sKV1OLkSl?rud-R)}61t2tkpa5t`J5TNBOEv0XcfKtQq355 zM~0900mf+t7%QZw2?rP|tSRd@fI>VQGXM8aUS0V{PhGf4kA?OcRMz*$45n!}#tu%J zLxEsH!=XiShZWFVR-&j?v?#h2?^)x?x}3ax>IS4JH$UBlygzP2XbOY9iS#P3GBI8o z#&=}YDn!uSh>zgbI5Kz_P?Zr)L^5(n|-;{5dOxy)7PuO5xM zXrwV~#-t8w3UHz%b9V7|Qx56H43c?e6#GR_C*p0oIl?V{Q)=UpNq2=!!Y<)2p{i)A zXbv>^h&)6=B0Mh;`qHf^`ZxzGNj|8$L};F4q>LFCW=lj;vO1il_nJ zIU2Gp=OU|@H0ihQsj+_rj)^ab@pno~@_1gu$VJ_yRLfyR@W6mSXUFvR{D#j%Gn?V^T6b`#YAc^o#Vj?;zV=6 z37Jfm%FD40`;erV%)6ujB%V|ez+24AROpf86pP8-c#m+X`*^ECrt>QBj@QE*ja&#P zQ&tGq3GJt>Q=cL?moJkSlpc>YLMB($g~(&%|A(vhj%s52zrRlkRdMJdmWd#Uh=wZa zRVOq73lpkX6F>y91SxhMq=_|15%uZ~MZ_KiL9h^tU_%4JE*h!|sG*2m=68l%zn}X& zYxzg!%363KIpUzQ2JeB_UbJIb_tH$sTKC?jkRd56BS0(niB@dvrc( zyh4Xc!Wb7RIa3U+J2hG7wU0pqbqq{`Vn_v5E4{7!_k?jzGbvdtn&V(d~z4g5q5h~vz2m9oA z*yR{yuRMkrl&dLnbi>i@=s{H5cc|al7^Q4S%2l}MwM$Vz;R=$?i$dySX zy^x*pPeSC`jQ#Pu*g`hQVHdL*geP$iv%~s?OE6#{a=~VaMA$Zr6z&oA2pjT6O;{)P zb?%6hDPAtX5VwFSZ;S9%c)U0s&%omY$LS>!M~Sn9w(o;Y4}Ny)-id_$;shbILgskb z$G>>76)gs>kspc7cUmPniKDOf)}SRo=>$O;K}1$IWN*F=o)szmASmRPI?(}s6fK=6 zjTQw-qVDKw4 zFUYN5mBD@c)oWm+rZmXparny?0q7U7r4!{A#OzHQq}QauM10IngGO3>UNA4x(%cJCpa&T0BR(@Ungd*RdP1(iyPKFZ{)(U5Zw(s^Y z#DFtfgTqOj6#QjGAmO6&c05mVOmSX8m3u7;(69I#y@WnQWr5b57QaBB6hG3@Rn0`D zDtGHQSu_HII^({bB60pv|79Vkzt{f)fj%F7m-rqG{=~}*3iKHh0=_Q^@b^5)VhR)tn=;xcX zNpDUpp%yTRV15p@ z9#%J!9)lRim|G&Ls8uv=C&5+P8)*Fh#r)82;)3{=SSo&}9bf73`MhjE3{)iEDR=8a zlke8fk;LfSyG>szVHm#a_C7De+Rrt8=m#8yVbFQmy7q!Vf zv!!notEBOfQsWNf3!;u5aJgS~&dhICq?e^Zt*?BRQLQgc3X?v^Bn@uTJ3L6}WetKu z=mz-}vulmzat%TS4OtX+u)na?G4Sx$lu#SY z1@p(k;PIz*7_@UICUys3z$kOyR%`$Ro%mNg2=^wE@K|CKew+XgAuGv)JkUbO15wUU z+n3hm1}4n&ok z7LJkDcHO0amJM~^9rhBK_#G(r0J$z43eJ#w$d}3g5rEzD20?SaZR)$z%W})*58m`^ zM5-j4Y&d2FnIkr(8QqvwXnd94!4hOX9mvi{+pEqouAGU5@}k_Yc}w%W+rEjzTbJdU z7IPWbLh`0u&uFzg{=O|=0j?>W340;bfxqjzdyguSigRP?dqLU(M zS}Br=D6;^dE;bfhiRX#4pMlCtk1b?M_xXakb=ha;))ifxTT8zurXPOUbh@f)tr%(NmeVGCC;BDXa|on9~y|ZpIeQ<65_3U ztum(;XnuJ*pg%|mjtCUe;e?)fqaL;RFrV~)7mOgr6Kn!_DKZppLNPH1X(ITDgaC=i zSm7YC0I5f2AiW4KGzt=$@w$!Xd!-BWh1Z0fd%{=3M<^-O5hYu(qza=}#em`s&o zs%Q&x3^T?n6R~;tY;+O23Z3ETv6dF|Kk$AWuM185i9TL2ktWrXnn|r(b~7aM^(@{L zTpA>emO>k$Ea^Gv4e3LvT>6I1kZVI)H-h_dby_gh(jO`)2w-KODF`UKSm2)}r+WW=PmO88%cH?xTmB9S+O8~yc48ZGR*WK9@ra-fdlTx``z++;EQRjr z)NM@)p>CThv~g;KUa@6w0{!q_puglT?_Upf0p$S&Rtq)@xCJxgR-Wdk27agW(lv^PM4#Zplst_B zur{52URgL?CxGw`!P=j__b^jvDD1suI!m}v_+#b44~)U#8+@v>!KGu|hbAv71O1D^ zc2=(Ns;~}5s&)&12}g+lOJpl@6$NCe7EXOUy;>mpwdWtU^1|Or)4z0V{iBq}A+@yV z_T#OmKs)@`Os}q~nO5^mc3b+Xku$woQ6s(MSTlIvC&y&TS=vjbjmksu1+ik2e}y{b zbXf6mlA2_UWU9ol62pO)aiEiubwhUi`MM~c{PXbO^glet*rXowr^md9U!^; z$q(?MWFYhF@Aex%fRWr%PF?I7@M7;JED%@fVmEsTE98|2-&?xv9?=RXf*j7y%}FQx zOXCXDzF=#vbu-?^9WtNaak|>Sq|UTke%1TxLJTg4JtgsV)NU~>ehjOj(KX@(}TYVZA#L9}z0M?guUY_z!UfqEg$ z<4X=*G4yKYze9^(E1h`e0j^~9ff3&a1?*QdhldtT2R^M_&@p<1uQi+oj_CzMZ7kZ` ziM0Dc#J|Hp5oa)4#0f9(m`(Elt>)=SKGG+*a(OrKorGclXpy}2776tMJz5;jHT7|A zqLelE{q~Caia!LjEGfT671Ryw=FN_oP0@nL*-Gz!`l&LiLHiV9w%1Y&al8 zdxc~FY7py2i(ciBSF_ix-0sr+$|}Hde&T|;Ah}QR4^a z?dj*Kh^Z@v+#Bc;9$3qp%f_coTeFC`x+I*i5`crm5L!RwCbU{>Ar=r!;pI8|;8sk< z`nHPo!4oRhei}3FX(?46HrhjWGpXjB7vPi*)=snbu(7w9y)$ky4^S$Z%W*e1}c>-0z4r3+E-l+$KQfEqqP>zE0KhXjF0!92oR zn8@2+xPz!AZt)UE=1h_E`gjb%J;rvPLlHVWBiNa`x5;iT*!$E&uq@23_DS)a+O-32 zwID?>R(uiGdM@I=mM?`T^}+Az&jJedwInu6Zb~>p5Mb_Bw_5&)NReMBF3JsspqGe( zJoqZPk%DR_Hy+X&weZ*yKPtnyNO)VwdMX@L{1A>5L8Fp=QGCpaMIa9T*^m>N2kmv5i@Zc^K^W3Z+`;BZ1?zmD=22mjhy zBUWNNWTxA3R-}t-l`Yjq0gk-I!~lJ5aiuKR`1Rytu3sF$lVZ79iHo}1Y`f|6yK|~+ zL4Zr8-8<(c_>fbTZM;jcJGgI`vcOs5Cs`w*inEgvRy*hYbSw0+7RyWy}xx{TlfywyLvQEr~75!KB^Wr!+;~^i7m%AU<7sq%fnu*jpK3OuihKnfVE)< z&dSZ>>20}&h}X3X(-%Gpb;VbCgJ$mD;N%c8cRWEj?G5&b1{PaVL%g>CksD3saa4Hc zA}_C^@|E7+f>Jj1C|)A(=!!tG|7Bh!PsRhvg2Px~B~Ws7^cVr%EN=Pf#c5Q;)Pb{c z>yjU>S(hXisKu>I`Xyk1@~rNh#c6Hni_*#5b`jwO7N?EM`;--su76$`aTHfTd?X$a zuZcZknov(Ty;o@mHLZR>yj<00j-$Is{iWB)ZI5h9K$`S3sV_1@ERhe7da}V|&|kCy zp;SX@$U5;A@mUm9%a=-Lpu40dXpVF@8i>Y)NxL8trX`0FxaiaI$f&FySmXXcN3tid zt=TMR_9yuo_ExszFZKuVkl0FFVsdlRk*5>EOvwTXSRvV15#PC2a$Isja!VqWfH|Y) zv~Za&{mL4|Q3{vS)C}{Q^gQ`W`iO)Jg?`dh{##l`&PGm?tB@t~&uisR$7>&aMRB#@ zlw2&Yk~hgavjMEIKCFG)9%P#MkkAZ}Od(H@2a$gepsxDb@E6+(VPQsyD;9$QFGLeN zh<#xfVrP--NWIqhk(?Cxkx*t`a?DUi^f100-GEN}U}G*Un<-o%d};?LF?D>6udwBn z218@MvL}jmu!&GsGiU#5X7CEp zMiF=zW)g6ytu9!BO$^A-pl_pri2={s7l!Wg-Lyu2gc*E11TaEAr=1Xt$YBQ8hUAB7 zg@6YUj$%*oa`7j23wA_o9;rQbRSb4dY;ed{h~}Wh=nt#tp)o$j9FEZ;l=6I0e}#TT zNfc}>l*jIgejjVep2L2?WejoH5Y=x zC22K$cwSR>hgI|D{wD#Tb{TZhXORant6^S6iYO7slf06Al#r6S10@aG^FP0CqXzY0<(;2T7uBWwe6nJ7+CAEj zr}Gjv-(vvJuSbJkw?z#!w_ga3CaZ(M>$ZOec7J`_e)e0_7M!Bfl$v1RH?wlr|`5QMwl#2oW28qW0T@_%Y^rZ z)E@CC>4X5Lc%!HbO%rLccZ+P;FGb+0=qtL7-Hx7Oj}o)Q6L4US|5*#3p(a=2#3r%K zeFn8S%SMVux~ld>+8g^+LS;Sj2?66^-sWg@3i=ni80Db@tL|9?wbc#IN6w}egbirL^0+YL(EZFoJrckJ(MTd`{6Gp>^*HV5;YjJ%k5c3%7k#rP;q5UpaKsM-^(>0Yhp7rXV=DnePljrNNrh6iw4nHy`tj-+Lb z#H3J{LrK@7k0zb12J_-yCCp7o>~9wS-8U~@EuH&ruX}>li93Ck_21f_lc1Zl;28^8 z$oj_6-D2KSq&olgOv-omrFImL%nED;4yOEXpY!QJmNhawUJm zhljS%D z(jk)#6GUabbsXQ)-rCiYgO$CtdnAl`?|`6BCJSqCY)b48SNsiMgY@?3cdwd`cYl#6 zrR|)k;jl$jk}@uueL)&XZJ@?p^tCLb>3o%fVQ1E1S*TKt2WROQlTk6dEgtoQ9E#I z@53?XS@9BtTwX9QX2sk@9-t1v4OSELZuZJ}ROtY2SdGp^1vUZ~0i{y-c^NduAy=QL zQ69-ki)28luyFztM-w4p989+tq>^j((OW- z`eN6ka@6?1y4OVjoS3Z#d(M2X9Us z@4jJWH8>2`BXSC?-#d!m@Hg{g|2q-*E*c>oFJ7a#sIZfq68j;bO1u@hBtD5~NZQ50 zNC#5s1!s_RCAdUS7+vP+1*l_Pd8)rfsZ+f=W(9{b?-@Z(*W+3YReHlg{_c4qspQ=N z99MWiB^j9WEy2{amrDkJ-DFnVzTFJO4Kx%Ln$XL#zL?{Y8#KScom+ z3V&3n2U?_>V4e%PggUGm0o~XH^czx$+2SX$0Ne+)UyW`aKjN>u0Zx?hV_Z4<0DXW^pfz991f@^dtl}Le-o6g?hU^5XG>s-H*C8meJTAQ z9g+^RN1DhdV+{Hp?yHP*!As;rYvuoH@)^ouiB6`7=qL9e#whAb~S7cyu$@oFVgUE(e#`tZ;(~r)* zlqvlgUSl+M?2^NB6(~w0D6D|PNs$My{j&M)(S)}tkG@NO@xUknOQ4*zDFaM750AOW zy~+@zl?kA>G{F9yO0ecuSz>ZW-&Qra*@Iew>)3ZJux`Gk)OFafaHKmyLon zz|7m2u8^sSRa*sV)_K|mU~Bq}^XWuBagDeKy$e4QtRvY+59lzzveBU$+^?~(QOF)hRa+gZztlXv1LoEIy1!JsPP|Jj6hDE6o~$JeD=H{I zxu+jp9pHU=dMSHlQ$kkKcJoCGox9@Zd^2g^XMUO;-lyGJ&8CBiZ{M)LN$AjamL=`( zZE66$pI^2uz*b-zu{g|EejM&w@FG={w@&0FJe1VN_mN;d^vA);M)EJn#bo0}_>axw zwJpj#sfHZ1;D0t7Pmo2tRlI7`>28nZZ{^?QV;R?$iK&_J$vE9xtQ?XH>02XMmraH% z?D#I2~Q z!tH#`9kVL5pvw4#PBiK9H)K9Q1ZO*#XEgTh~ zIhM~*p&13!>fGP*3^0Yo9k00A0)LD>D?;#%cUaJ|bVTXn!YJBUJ{aoY(|)`UqKS?S zPm(Tx=NGNBFItBe&Yb-#0x9P^MFm6NCn?G`&V7{R0B$R3@!j{f)U8r3sX7_Q8mX$Q z-O_R@B`LZ=EOc->AOWW&RE{m>gKo#ukcRT&!ZK$>MrEvuca;W6H*GD8x$73a`R*2N zE5o1X_#9z%bZk-6$)xi&xArkEB?FMV3Z6MD6Pl|(3kRxJ#RD{*+#8l)b^^wL%3b8o zp>SESO&*t;v^z?0MgIH3ztk=t^bJ$Hzev!FDIJ6M=yFyQw#Q*|xi)8r{PcE^KaA}9 zF%JA6vTKO|1q4%-(C*KZf1q6wzD zUud_B{y%6}PX7b#E(HI9cJF}yLAx#UX#atB<5AuJLc6->jQw#GmUQo9tCyTy{Ca&3V&1Zigj9aCFp3d&t@ z1L&FB`T%`X+hxrkdnefh14C2W2=IEescjT6GPT_fI>(sW##2=8elYfvscjkX!Bm#h0w5eyPd2Lwlt>! z`1Q_^+jW81u4^gecHQ(`X!FNHT-P0PyB?6+^|W(&MPC59-Gwf8^hKo$UFeG;x9hds zj=lj8v7>X>+0nhD?Z(o5cG%H<6YMsEgSM~e{^@q~fWPhNOG@+X=z$mP=u3;?*Dt$a zM_*oJM_=&(62L2)?C7gr+0l8c+93uEs=K(?ySV4yd!O&(=5}#UbaB(*tNmTv_%81D zE^ZWji0I-5cX5|>aed&!f-bIe7k73S*A_llc0sRHu5lMvx4Vn0*~O)IL4Y{n{C@!A zgxq0(xSQ+EzwXU1I`7Sge{#L~C%pM-@YQ~Ae!Mq-yEi`yK16u)gT497y!k%xVSzW_ z*_%Jxn{NvrEWPBR`^%AKb`a)(F2(BY#07-?@=LyAgh$M!sbu z-=vXm+{oAc(a6_q-7)> zj7?l%3Iu(aFAf9Mth7c=2pIp%7aI)i2Gm@fv!{xrmNjtsSWYVA31DOaf0$=|ff+xK zX={nShpk}OZrN&@-4J_P??r5pURx|h7$;yV&U@-Dy!Q+f#+*Nh@sapp!k8RJj3Hs% z^Dkly3FCj1h_NIF62_N@5#twewATrA``2+w#CVu6o~1;LfePC?kCjBTOrt&D@=d6z zqAOCN4Lv6oiB_G;IPz)lPB`7Tnl1X5F@}iolc6uEv>!(xV+`OyKFk=qFzPXT^7Xdi)6~-NQ&CW<%SVYZy zIk$yRh3|#)MR!FLj?bLMFLT|$Uq7uIJ2a8B(FptMWjea4AU;pFLqy- zJ)b8pO2k@+`OZ&H z>n(gzr04f!$l^51hIw}42gT*j!CEiEi>U^L1m z(i&weE_C<3Zd9w68MoOn)azyDZ49jnnQdFq+lE9z3ro-bhnj@Phteg!QIvR|KHN!fb_KQ^?aU z46L%|6?%lXoi5oSru2a(+iwOUKtAt>#^tedb-q zL53I{2XU8r*I(+L>3XTRqV=w+b$NsPY4xSKI@&8Eb>$Hk$}G%QzFF|Be3Ac~aZoVh z-8e#j!VrL}M+QT-^0pgT!iZrkr2Q;uQv@({fTzZYD{g?clA&@9X4ys;9^Z2HJW-nR zSpB4wMk5Dvvt@{}+DkCm{0DM5Wel{DzEkOXr_$Q;PUSd>wc4xO>z}mv!3lBWuWw^i zE&II4q3^+H#P`hOqqUFwwj4iaeZ7yF34H)n+_LGOryB;;-ajMtY&M*2_&x--+)%&~ z!z&I8cDs|g7Pmd8j54|EIeBCA&;*^h;grydA-V-$8ENc8pGg^stGr!!WU7h3_!VVI$ii46I#>BR4%4>#H z`VWGCb$Oqm*^GmZJeOfTf5_0J@TY5q0=ms`hIF=7L0z7L!}#K)%J!xWallW`Y`@=P zh<-?%u0?RXt`4R7C}H7NHU$eW{z`Xj2`_pFVd2|Vbz8hG^a)sxz(#KL-B|Jf9Ewv5 z=MvgZIZYZcG`1}}^3#eOD6}3K0+o6YA=_@J8q63em=HYC@MqhRJ!w8id{yW1kN5)j z4O+eJjUMa&_Kl7(diA4aXiT>W)aHGrosv>K@uQZlSD0X-EY z9Us91<9Te}pCmo!()E!oURN{Xb9lwP+Q3f(-^J9z@>yVfG3S{}k5(7&agHoWEtENR zHPA^l-k>9z6Os|{lAfO68w^}U5kVR8f^=7@@nNV zzN6(C@MSLikGbWWNzF4lS1)~DBsQ!VSW-CJo~E`VduPs5a^~D`q$V;BVNORl8XAj{ z8;v2OZa&?m4mw^cozm^_*9bMcSJy+~?0$krQ=y?Fr>Ox2GqKO8>Tq{3hwa7YTY;Mm zcjw(~NS=PPp?4nfV-&8sy>v}lC|G@#Dc3z{EvXA<3bE$uFQLa;{B z6*I$PPzvS+9X1(bcgWN?*cgj|uUT$(W{z2=3uhk_X{A@k**>x07D0RHG;Z(B{Y7EiO-0vIyN}GI89oq+u_{ar z@5Iase7jR1w}r3TflwwF4kMqR%*l7^n;;zVB8lKmSS;l9F*$d`jzoVxi-YTUJ^lvo z#pyhKo;hzOkF|i8vd=j(D={KorEqe}X1DTl)w;=BJ|vP;XnQvU_2NTGhQ-Cnnn4k8 z8oV|E_@^}sXTS%w^mlus;WSvE_DEb_gi*;tCFc=e3vM_+Li82fU<8|EKIQYoVp=#T+y}^ zaFz`t`BJoI{9r#iFs|rOF&JC?G5)Y*M$ovT^5Wyy%!+~Jy0u6-1>P#EfKU|ISxiw; z){AupQ<<}51{!}g=;T+bm?C;DTZ3}>Pwq~y&C@H=4lFX!0mTOUrhH9A#i|Ek3tB>m?1jor3v$g~ul+g^B1BH7K{p+TRDX6=GvlO}&_Q-{b z97S=Pg`PG&(rNmY>W*83wL`VnYpz#K)&ZOT=0`exQ}q0-b9sSnw>{EyA+A_hvTRZSAg z-QK$)F_->ZrSvO2>)}yfZZI>uZ1BV2_T3yk4qkF?@KVA}l?}zOH5d<7fq`uoe`8v2bdl@`U1nvxJ~j|qAE3###u@urC!pzB$eQ6y;v`sQXhpbaxmHEbm_1B z{pj!ok{&m2(Ec~A{5)}!P(`SP>Kw!iiKEgP5|LH=tXLZo{cKexavErRoTJPS1RRK- z#Jvha9WEtAnKk)W`d+YoyYdnS)IT2Qc9;G%HpT`ba^}FcfJZ7G&;`tMp!GZWqgJAp zFC(z=7?X`TVRTjQhQ#T?SJW2;fY2F_kQQ|{!;MA4St{eE2Ln;aw2+VS*#dQ^>A?>| zE`$Nckj4lK?_L8FxcB1?IO{U*$CKe5c*iLNHQpGW`c&S`fzTP(4<||Ae0T@BH09)v z%JggIec}N@oUTCkT3O^0`ib>{NW_#5b*?`&{h>vq}I`ghULS%ZOxejWn}EGH4gX4SL9S7pxk08vzR}z zJh=~r^oZ;w_Gv{bXA0VwTOA6{7`gfduP(^<%)3~^bZ&ZB&bU?j$~LWtQFEjinCUX5 z>P~4z>>A|G-^C91!5?$wPa=Du`K%#`Oe7NtyR)-zXd~X|1 zA*M<6BxVwpqr_9PT(UtzNa*7lme{Miw&j!sKkZrUAN-_FGE@nIpA0afPdY@UA;h8X?^&JuJFh0>gyod^3*!eoQ7y*u`RNquyX3#aNDRCy&q;UHmOhoE%0D)0sm%sj>3- z64r6x$7XTZtb8jr%ZSZ#)j7%Fj&UB}z?dkvd*jVhVmll1K?w1)E^ z{a-}Yo@QuoYgK!`IhmF**gwT2EPL#D`DmU~v%1Ef1WWR&QXa@z$Y}|YDJsu;CCC$> z(+uB;p(nqbiiPTy|B_eU;jt9od1Pef)yZip)+D9gqr`i!!IiIcEv?BRs==LFI%z8Y zM-r#NV_i-m^_=9%rOVJ^EO|?3!_*C#%xvF=DU97mue420yPa;H4(_zoir%zNPU}r? z$g)oVa^jOFnF!j@UQ1fisEMDMpnobkmkbe92{_SYQ&p>XIMrXFKZfAUP=v#^+0Ij?}$wIrD z20#1zZ4?p2p^zXK`98Tb@n+Weo*DFzewxlZ8&aLH@X-B~L;?>Y+_QvqAzzTIiOoa` z;e2At+J*W`-Q*OP7K>!P8DQv)`)lJf&nOZT@=W8S>f(@ z0{}n!c3mT>rF2;qcnkmk-vZ*KXV1yMJ-d$8x9i54w&{VVX?xhxs&?IrrUxf~&?~Y8 zKOqZ5&6y{X1Q{mZCZB18QCN-#KyS+*A)nvNXC#c?k~R+FFLY-gLv4kL!d`J8^`*m3 zJJ9aHQ*2V4M>7=#iXW>^S%XolPdh7xQ3w=1g8x3KfJ8DfsS5&FQqZ_DmIGebxQU zopw!`$u*!kbA?`K=3;_JP~aB*HaL_z@^(h*fR-drGAN{ic&28#O`LUP+Q_Hs-1+;Cm>d;ki+)`f80u{s4#%R6 zePz|4MI4cjXtijw2n3XYR#T;g-{U!O>W{z;-PjE28EKi6 zd&XIlndk(;gT^qcSSdCuv>|k8 zk5(g;GzciQLH!EmFa(eqOq;|ZDO9U|eG-{Po+E({@sO00eIykjHyO!V032BbuJdgD zkuYQ%asWAnsQ*NEp-mc-<^?>ng(M3KbkRxZMpPYNhFam*u~Zb~qQjyM*xV?48|RcX zv%{hV>>|`o~?T^)_;olFY#A4(7?uG2X?c$qL>-MR5mha6PAEwLWxE! z-lSnRBN<48=SV1D%P7ej91v$EU=mRzNWo9w7x4-lQbP4K^O8`#y|1r!zx_cjBV1 zu7Q~l*Wgg*?Ga7>nnH%=hAXOPuFzr&qYAHF%@tN&6+RZuQEScieymabpF7|NpgEm^ zm%zw$)rG-Y14Sy1Rcn_P#hMMR5BN8?_5g<_=Fz z>UovwH5VV!{+zCmwuXAX2$8v85y*BqByQ-!sV^; z50crEcF~5{2YLW^=NX1kst2$DN|V}+R)5Y$pv1fWM|XiaYBdd>%$_#tY@Bl^#vI^v zG3G(_x2EoXaBIr3`kpqBGSJ;#R=tmuR`s-99mx0!KDS^0@#k!$&TtlWIL<IRzE@X*(+)04Mv0x>T0KoI7o*cwL*S zdQg3v$}*B}XL+ptp>BjJsMjm2UI!26hq^~iH&1@52ToePCKV(N(L>CTb%-Ytxg5%( zDDO%SV0i`sR9Xt_U=Q*ep`uQQMZ8N;iex{8iqI>lRT$W7J!`et8D^lMbMBZY<8{D1 zIjCN6VD|&TzGL-b=S9BYvP)U@VxF{0?7Y=Ca7md9*u9MM<7;ORvemG~kkyWyi~Z(N z>MIX0H3e%qfnA&v73{ysDB6U>At-+zSfxI8ppmcVHP2jrP#rhMt?+r!dl{z^#FO!3 zcu)LV{y<{Ok*EqhGWdz7b~Xg9q|oS#bt(K_xy_x)nOoIo5J$PR^FUbxTtT8nsME< z9C~nd5u}fgB-tcdPlMVPQMjm?L5z^dpIMLDD>^Q^Ai8xNB-b{I+C|Fle5&|OH}I^? zh~diqzz#WLbyB=X^6cESjx$}delb%53?&wlD2cIRm1LfxUY;T0Q|hbx5}5RRW03&5 zj8HZs_R>V_=~US7Myc-hladRy$La!e9~BIgOVw*dnS-5D#+fhw$4k1L#(Ohj0_aLV zD^{kwK(30YtWByM&6E8# zoxV<4!?)(Ksra@tF2BnPg4-|-ysJgjUCnv#S6ImbxwTyZ%#cUy51YFDpVjpHgCC|p z{l5<|Lk%$tY&NzC11_g8ax-FzgJZB{>=z5-6>vl`FLAErK;0RoB| z0tW^E2;8$7sf$l*=2E&^@K*3mpb5pDql9cjpQD?^;3SbLP9e(09Yh5|zS^?4B+KGA!%74=)R8S2-eP)P z@BdD}{EdJ1r-Cc4k&umj8MWYp>8aYD?|z};S}MV0DgydMICDwmQsycd)hp~nSX8s% zD+!gfYuNUxewBeC6`bf5TcYRhkAa+8xM!TF;+cGdLX1|SO=u^oKeRX{z=>sHXES}t zbQ{~V-geAX`U+{=njw1JU6cOQ`vI1jC>#gVI9OKUTTc2A&EwzgO4s+tS046GT)=`i zxqR4*MZHojRzZcl=Y573`R#9?XFWAs#y$V}pU=u`{9vmlA11nK=J%<->7!lhJ>T2) zSzBId0%ao09mn)8WjfLSzt_0HkPfuAH>suvYvB{q?-*s)X4IiKgm?P6Ob+dtl;*Kp z^@r)}dyG`oyS)sfz7*|BCpw3r+5|X^W-VHr6P>QtrnZ2gZaks>1vim|_A5#=meDN- z8kwM*mi{Dzi7z=Lqfxd&2S0r@nf25ojPzEV8h@a&u&0xe+>qlju5v6njl_OFZ}pGg zy&w%*B>SH8nnv9<^8jP1aC`XP*@jkPVa zJLWjau44A1sVH=D=4iX?L9^XDE*gx+px05T6V`E_o+5$6y7uu7)K+2MFN-0sL1m|) z2Je-n9`+oM9lr-$Y4`SgyZ>O=I-E@fH-ks)7Ir_IiCqrP=ajB~=)>Y7!N_!rp81?~ zjV^Z_TYmxcxDAap<3ws4Z21aTR_@fwYQ$)`vT_P$K!7#4i3T3}>

*eGl!dNZLc6 zvmqcQ?5XeN2(>6*tGKayp1X*?(WQNnvVa1xO;Y5e;1MOn`iqE578U;tAi z#t>6sXM_`jL^PqFL}cx946I~cj1p9p5L`4LsY-ZcZJrQqYq;hcEpo@;_AgiR?no^J zP}P+V!Uu0NuH;jqDLZ+oaLHq^G&|@qzv$n1Uik}=2P)1~^t^EV_VjxZ?Gg&i#I2Ip zma~_~O8-{Gb}f{0UPuJeYYL@_xYpxvOgSXknC;oO%RcKQWijJFU8Yg%Q^`D{HtlJ0 zVMXemoN9x_P~6gR~Z#aabD08Fsot*g?<`D>!W`J`$OT;Ue4 z5@W2BDm3822QHC1r&_{-%60wM(#lYz8 zQ-jHS^=|)V8Ar~F%Z)Ty50_3V4d;)2Dizg|&&ct}PqI)8sb$+BE(n;t1TbQjBO69B z;>CdTw%zTP*X>+r?p=O{-meD5je~B4-35?hcTWtSwQg`g>^3{F(g}yJj1&hj7sXKr zNhn(9XKmf!=ji-@ReT|o)@MmSmTS!ZQQF{4+wJ%dzEbLV7ZCIMVW^S#o(ZoIpU*3o zzJDNnEmcVMABV%!mawp~nLeFm&27y2YYF0l)e~WJ0*>p_z?rlA0h8ac&&|w|u6z&zwZZngWUOJ26ws}sPanyn6 zG0`wL;UMAHXB>4cI%|t*^sVjCU!*{k%Fbn{!L8MEHb^JLNO?xsmc_86S1=4`PSwyNJSMXVH2` zDScQ>Qj-#DT?HryyFViS$gbUmETZE~^()b-Pid7ZKQeBVzV>e419$S*uO%zTpI;Wo z-Y98rSN~AkrKk0R@w;wv|Cwr+CXinZ*cu;0_~*% zBes1La-Bd#df{X5Tu1D~81%A=wcT7@Sj9Ei8(voZoFVqk++^Yoy4Hp|J>lA)XoiOk zIUH&Q9m|<+z$`~C+3-+rZ9~+=Pu`Ukl_82)Snr;v8D^jI+E&nCx!Dc^;VqAfG!&)p zf9c8ZDqePV8&u4qX+*^QGSDQ)k<&?PdIIjHR#eV*y=tP=yImwf1zCtxBiaGK498+z z1jE1_Bm_GKH&|1!3zz})pWxObZ;)QC=S#VrT)Qr=nvLz0QBV$Ki@Ksr>-fQRIv*@r82l+e2iwWGRTNpTK&cVf?KKj1Z)zV!ZHQ>uyO(D#3UFYpb_f?X2ckL zD*mHaOK)7bU?a@nD-&g0iF=yoWqW_j_p)KTetf z!qUbFrV8c?a6yoO%Dn^Iut%Z+LBFVU?hT;(Ads6ka3|PPnnJyUi*N z%Q^&aBAN;2Ct^>gYI8Lea%L-3;4qBYIVg@E8b38|L*hQhn8K}x==)M6Mdx!Uc7C`< z=L~xT!j_q1%31W;ApeX?&39%2>)MYgCKD@^vzm2$CcjE;MP=*=&h5#tzO#Pp_SUem z(*1VDU$=+RnerTn&iqx$aIR9_QAJx&3EV4_Z^P*!1(ao#7Djx2^rl*c!yWhd=d~NJ zNk|-hWN|pA8-HJg7S`q2kw$yteyV}dkEtqy!=|!?^&4o=B0$Fa9Z!35$yf79XeFcM zidMGko9fp!s%siv*9czI-c*Ckrr2liYW{w?`(|hL#w!i7dC{rECf5Gi8AsTZiS^0M z4DM)g8jV&Wf{x6W74a+Un9})T+3b%8(83S-3?UrUG`b9{?QTAw>3`xONrj@1hI)se z&N+%oCWlkCOEluw_{J(`!JCdNLlf@yT2Z5{E}8_I9!veDVbX2V1JYB{N->NVBm+}h zu1zX~i3{%*7c_NiH?^R`JHG}Bn_HA+*-%r9(t4c%bQ-3c+#CFqARGLZ@M`dqFX$Ky zm6i2RVO$&7A+to%8sp0P{TU8wRRha4cir^UP8QaQoVoM4pY`=#>FVY8rwEotYP4(M+|ujEFzzNr;GC#LWP!X9jj2g@ z>WoN`;-rtkfyiWJ0rI!Z-t=JWxe3O%PIoxnpt=#ne6gxzVyTN143>_TPLuYOTh9v$ zS4y`_#jp)=!-fVYN6CosTA> z+t8$gaOYZsmZ94eUr`|z5(q~3!dPXKq`AsB2J>g{dqrdMSRS$)`+o*KX6yrBqZjXT zN{+x|aj(P^?y}Xwq5-m1r*Q82ZJ!6QU?$KjWnEc;D&tWHmC?QA}n6yDpcmu zo>t5wS!J$}6=yk-lleblEQY6zIg}>gCA<}{TYj$g!qsV6kdn*5;W1dvDw@f#N(L~h zk{7PYsYFBT-l0y%?sj(1g`L-a_iwsb=l*C;a>yN9j^s`)@0)w#oOoT&e7B^KW%-A5 zIMbdz;uhxR@c52t8$iP&?jCRk49eOv;La41!vRjmYt`<@8?!q<5MSA~2bKk<4L=(+ z{H*8jvy*$?NHZ_ZFe}OKyCjXPsTow2Av}cS_RZz5G+VKG3|L_ur>XV0fSj&$M(>p! zJ$m%m11;z9$-WnZHC=OR&!6>FKRp@keN0|(KJVnMb9pC!QM1xQB)PLD{ZqIPoS3fJ zHC>YxJzX@t>K1>`PbJ(MuoV0RL_88uwY z?_FAI``*yw`I5A_dFP-49CR}T^fRoR`L5+~e(A)u)h=(IIF=ipxN$*t8TOhiFHH{9 zzu1snw(hlN#+#Gn8ydHsDm;5A&xJD-4&wDXXv<~W6d;`33;Ptms&D_xGK3nI9T{tK z2K?r*lyJ!(@`9T%RUEOe?~!+3{=IXzxvu)o?o0NfZ8MJCX`=Z$RuLZf>Bd7SL!2&I zH@n|j_$Kb;aMe16jb+g1oj?#{w4AtI^A#>9jc`g)IbZ*_S~b(4Y3WkKb%hEAb-ipm zz2o&n#I@k;h8*rBIBZgy9FDwz*OEW%X2D^Tlb3JKJ`L50a%stz6GNsmJj+LtLhUL zsJ`TG(Q{X_{JvWcJ~AXmlpvZZG5h46x)J6Yef`7MOPrH@?Lxh~N-UE-(>(>D>4r=% z%R`<5!jqTcz2DQKM&+%^^W5W;=XumCvu!8fCLM?D=7L^@M|!wraIHYVz}=V5^&TVn zXlt~Ud_ydpU-j-H4ff_FT6Iqnu9F<{Tq5TcdLHt`B~PTuulg5!>@&$dL>h(#dvh~} zjp8MmPwUO^<=&4Y;1Bam1ZI=^4#3=|y)He3RROE6l6cM%Ir!B*GK@2A5(kuH_2YZ@ zZu@~*&jcV1bmAD(oa5fc@<9$~MbY$vdHjKLO{(vNmH*6dnPhQIGiLvG7o8@^v+&#{ z$6L^r-{64BGasgnTW1guP5jO7kqL33vS}n8emae;U>}$#2 zXWhDBZ3qaEhGG)8EelQ%m#_y!+5+&F&`jtyqnoOT7@_)`h*q8H*$>8q!_VFv4t0Bn zpN+h+o0Sombi{Y}x!Yj(*NHGNEcn!?;{4e!s%@o~hiT)7D<&v#MRE$!-eQ>6 zvm;4ZRFZW^@m%pi@k;^3gbR`Rd{f%d$A9IpWouyi)^1ZBRGF#1s6A9rD%L?Yf{Is- zS8=IS>XTY>g8Ey*xif<0RvR)cxHp6wEV0pPb`RN~Js|7c2G*%t= z!n|VUf8cT=++td}yeV!mk$l@0?+t>wBI|}NO?|lz45#7EaAc)0NGx-hhn#U@XJV!s zf~FfhJ*FFaE|Zwg`Lgs4xEHZu(CcKX*W3Elf^DuloF_s#l?`87t3PfwYcixuBp)m! zb3Ry9Omi%&weHP#6iept9sd+PogO{-ac9?7i!jNYR*OVwFGGmSlS$_8v-VAbqwEFc zlB9A;?$UCJZ@J{O&5IrY^C;JFUAf$sw|F1LjSuU&KkoExbME;WPP$DLYoT*q8@+&c z$??gT6bFAT_U{S<2w+YX-Lmjr~8v zpmB{S?@uqYi(Z^fo*>1uc<^@JA-LF0KWmZ%CH(3h@O$1`&(2#*`@o3gQ%gCVw|-=R zZe9mV4%`iMEG||tP@?5!Z@Ik7nOHuIC?|)-UAHm+3DyL)2b62OLQkI{=fEkm07V&? z6TH5BaqxjKTjz!w-2)s0IcB%yj)C+9S4o4WCGg1@gKOZA(1x~mo!Igf0jI9nq3aCs zY_l3Zl!p zc+#XRFMlqdBZtv0tQaD&DJqg{`mCFB!?kUgcBaq&%x-p|VJ@Jzq1F}p9_A+hR(uHy zO6VEi5A$Vi#2dbr!A;fB0I&J~6Rlf%E?6%vvtA)5xn8l+<-({{%gfg(c}rH82K0FQfuc;uMko{;6qyQ;tGEb>NL7lD z3P$m7#lJ~$X~({1^e09Vu#|m0;B`;A$Fap=u0KQ=K;l)`C8J4h|J>;E!MR|0`N-V$ z<)d>;1HNW#KiZNBsseVXoBY3KTs*qxIForT517Hp2oKc=)kM`URlF)MT-@t0TRX3t z70yCbyN(!JVgAHxevxC@b?|C-p1iPU5EaIM(?qV^~eRyOmDxe%vYz0NP^za=N4{AVAmTuPt6y9yj4x zWy#9t)vydu=pWWOB!UNS38=1AKRDzfpFo|O^zC{AwTaq$E#f5AdWC9M)s@4Fd1$U6 zJTSZ9eJQ&+pKjHU2E*wIG)}Le+X;#EWjfA2Aga3jW-?3@u6f6Dvl|SfaaGap2YL|6ol(ulYvXGc>c0!zoh7mL{Fm3MfFZH2u>avT zEwBEk!w$Q<=z|YtI-qno8JJ?PJi5c4B?gy%-eC5iA(jz^3>KH)9PT2xy7EIG3A+R} zAue?dY&3>Wf;g`l33nH7+RFk41xF&6i3Kx&fcWgojFJN|*Nu z18h2SNV){I9;q6A2KPll8NPeWCp-}iALgXc-~ozDr}6oU$86!|qUX)Li=I0!dPd&% z9bE3y<=2}N!P5f!diC=|J5Nx|1B<^6e(Ga%*lIhr>xr_Bbu^`do}~GegC5(5>HoDir$L^>P~FaA58tN6FFXRS)Xsq z&QqVmN+uTO0#@;Oql#5Lrv8n~F24!Z>>*APSBUfv zTi~Ob=iBpYc0IvTZhNQ(s*+IEBozy1_NMl!=22WgYd3!RR-4{x-;n#&zP?E%49~W& zFK-^x@?~OE!;gs!FcW;MO>X}BdPYVH>7=^BZU`_gH^)cZgr}ks+PV=M4$9J3pj-jA=Y|36V$6@C=QN z3D`t|y;L3~%~eUA(K33(tvnxa7mKDpV&{fh;Mw%ryTkCLDr^>h8{2?a(=gkq?9|z& zB4li&r*0fv_L;Ba-*H}F#z}?%NLI@&J)SdzUDN;a!oyH)@mYMtr=20Y_=1zXT<-kA zzIASACKkwn{|EEF64#F-TVq4*IIHY1;D!wi9Um|jyO?@1`bO&6ct()gF6U5#un~ip zoN|5+5y*=X&y0@8QiF1j9Qa%n|7l;`CeZz>fy>!AXh#qq47lVzjfELhAHxgrArGF3 zPej8B35P97JkG{s&bI{-s&P2*yVJV-xN1AT_ULI>f8& zb>-IFnF=ss<)ZV^5IVc?L{)tHjglu`545xLqIqFw6o(IgF?@eI;FaKGkEZV}V8gy4 zUD!z?l3lKiHVS;oKY)=>zU^^U_I~2mJn)H&tIrbugLSU z?{wLBx(;y6SLuF?{OOae%h%o1!Lii)cDD?VyFBE!v(t}9=*289KbSe7=am{ZZ=7$- z;e5j^n2AWs*t{WIkO&5(U%rHlMqVHaW&@MStlM*W(U(Yt0(Rt*T}roTZY8@NSkyV- z<}gXZ{4vGTJn=2$e)2Rq$ZkssW7_qTcPAjPn8g*(puii_NE-V@^7upG?yP!~2<(OE zyGawTOJajcz1y)@H`MH~U^2p&Mo6iCLxh_(B_GFEA#>w3t4ONiofKE91$+7vN;a zHxqmTvKIyh*h0?HZ}dXwn=hQk&mHK6v78jMPn-_)0`p4<+R+QMyV;n-U9EP#wC|rd zf`MIU1D&N;=U0w8}<(Tt8dsND=4&P;lZ)+5V{#G?B4hJ{|l{gy;kwe zy#>~uf>k`bVXV;FRdKOMcgR>oU^bC94hY_0IXaC z!K_Xx-l4!c#T%-+6{dOv(RLXSXUf1in*%aTe#{%#rFbX523=0cJ{nTJGJpdlF@UaD zWT0CK{3XZxvZ?aN-k?X747}`_;(ZTRM4^z|ETy#f!rzQA);YgiHsWsF%2^cA*W#`FM>PEDuTOgiEAKld5Vm;0gq4-&-Q% z?}L8}|L-3%L0*qQ!9RuD0|jSNWCHbenPAzu12TcEe*}MsEaDV@x-21jT*91)gqXY; z33KNr%v+KWyE0*Z-nxVZDG3X=CoC$5|LNi?8Gk7+g1^ivqKdDui{Qugh~V#^;u^s} zP?B))e!`*GvMRyh_c8(5EE8lu&rCSN3l!v71qzNnwF?v+JCKm;8YnnEB_&XB;%LIj zQwgWeC;W3dQzkfjB_aPP{ENHE>+0{S9lRi1Xt~LUAK!6P(3251RB=}!HxbAg5pA1grMZL z%ll9{*h zBC5=PT1A-uvWqZhmiLG-2b|vF=A81JHBIK+@|^GHJb1|!^2>89g#vhKD>N(5=`J*f zmo7qKd5(wB0$zFxEz5KKgjVn}K-j4~Csb$+FT;hM%X6ZHB6t}i6qn~L7TUnec%f~1 z&RU@zyi68$DbLv^w1<}&LWlC4{lc#BGDq00JSR`+2ru)6-OF=|g#CJ)ud?u(ao(cF zDo|KkXcs7a-6K#~=Nc$nR-Y0mY}g(se3K%p629Fo6TZuo2^$L!$b|2Y%7h=Tz+d@z zN+$etKTxQLAD_^0MJD`QA`>o>G&e)a-|c45en9Qj@IItc8borDm~G z6Qk5b!9%!G6ROk%C^dfY;H}hnC^arhO?RaRN+D`2l^U*6^W8jht;VQnG-_&%n&(FN zI!4Vsqo&xXDT0T5qbAR&$uVm7!$Srv_8B$FM$KAyh&O5$8#OUTO%yzY8#SRuO@LA3 z2M^vxjfYX=V$^gu!q+isER7njQS;plzK&AcsMOXfwa=AW_sSQwS{ouh{sr685U6k7HN-cap zT1%yttJHoMuOJ)Or}TE=Fy4BYYjB*3ziu8nxf~?E9&1R94q2 ztDh^Y;rpq+r>rhkRu{oTzOp(`S)HS--VYBM%Ia;(>SSg0T6l<8Rxego$0)0#;2~UD z9jdGjP*(fFgSWEULs{*jtnRL?&azcjTPmx$%IbM#G<+%IN)-5HwR6y{$4jxiWffB?Qe>MlY_6j;V}}s)V4K%IMI_=zz*- zze)(2sf_lhjCQGv?p_IjHkHwqmC@YF=(QrP9Dv8oqPj>lh7RMMn5KMg#oGF&g$8;p-R;+l+=} zqhYNPzK+qb*l36`8lsHwb&Q5kqana(@H4{KF&aFK1{b5DyAi&Q(O_vbaE*rVfPFup zQ3-05;JFf%!NWZzC{}_ZCCG;d_>-dq`;{OAUTsr?WF=Uu1o7~&SP5d3AW8|s;UQEB z0+hf{3B2LKLkV1zpt};-epdoZCEx>u^L>UeMCcXC$K@bY+!X-E(v}x0HnX|j&y7D` zyin@D#?$kN?Ozh6z5W&c8T}#OJwkjka-dw!Tx!Sg)S`@BKpu#o4zQJ{z{TJ6rd#<;IrBj*OF9Z9FZ!54 z9Nc~9F7Ce^di)TZm^^%t3iq2i8-Z?)=Tfh4PMoDHP0F8MUEIXxUUI1Xxki%9S?9`K zC&`m?FgbTDuo-Uc$r(7@*Pk<1Zeuyrzn}b`gcI6zw^SzM7#hX-(om#P+BVSJYeye# zcl3mG6uPUQl^0v28VcJ-yF592y*M_K|Fl0(d1jyTT&RX1+pRgXBxZGXO~14MY|MZ7e7E7wiaGA(1$MdG z4$G9+aDQ)5*uhLk1cx2J%aL#d(i$h$su?Yz7+oxPs2eDUVz`icPSe2bt~?<$=ErJH5@WVF=AoipOZ;g@L8|e z4!6wm6*m=66>k;a72HkakPmR&uYF{tdU7rsP!^6q3#nRV6(=y8)}(dd-qkvv8qFcaPb>>Ar~^fG!M9d+E_^DWAvyq&Q06T%T#>qIOXqa$F)o?XA`LSX6GQ7p;v zpH+7;P=$TO7|aHD#eqj$TvZ)dlROEZi?6~rzyTl`S_-sOXd9tzg0>mj7HC_cZG*NQ+74)cLE8yU1uYF)I71}ju*P&6+G|*rl9~46? zfp!yGDYRSAZbQ2R?Jl%?(C$Nf0PP{Pf1%OPw9ptqxi}v<7HzpuL6m4q79$_s~8-`v~n5G(9u}w9n9* zpfyAL0<8twS7_g$wL&vO`wr~~v^Hozp)u^g3|u?n!q-rLSIhNIm&e+J`T8JgoBkl& z+t%pI8as(WaHO5fCp}K6T*n2n59rOA&ucFfJJPD3m|BA-1-776Iq~$Xds$& zMf%@*>_m4T$z{=f5sO2LP3&ZiAV`}RlI_aUQ;vjjoJ`vcPM7}(-jAF{z;#56)FNMy zvPRfrP8|~tT%@LvFP5pgQ<^R1FGp`md8m9;R;L)2JOWts$O3evA_ASG(BoTC$pQ2q zIKue|O`bC3Bg&vc8_X5kcf#7#l6V|JJcZz~f2K%MF$lLkfjM11x2k=O2x{^HR+O)- zF(K|u!MbF&F9BGAv%@$maP}C_fv8pvZ)IG3sXU{HVxWRm^#lhLE6B}?EYg)UF|mcs z3IS2LX|OW^M>UD5MDfFl&afjv>?4GkIbnjnx8%-jAK(R1G`2n$a8-$V6P$0Rs;u!u zHmI#r=d&XcXH*(hnW|1D{;Cp^PocUVuk!5QEeXZoJTr$}NxoxfG8f85-ldbK(w|A5 znr%A_Q#TgMBpuLwPB#%NWZL#nJ)&e8L?h2X&vCg#+#|$P(OAcNAF7KAs!1=U{-n~V zoT3+6hu*Ji!F5VYb+BpRHY&}x)J4<0D(!Q(6HOSIMT6t?Mv|wiWc2h;W;^4ilbAHP zm+73odb9W+;XgV`HzY*-Qm5B(^l{C^u%4Y^=-?{R0~Y37GT`<3 z;?T&hF6{m_U@7c=%y?!t6UU4a?P54Qk+^g03zv%wOJe!RfT1F5)K%n#Qqt*g@$?Uo zP$fDd3U~LqCZa_(qGnO?qC^`T#1$EW9CPJ!kqvT**ew#7k0c^s%DWB0hmo^LG4dE` zKw1%yQxqisGj&|JyVO_8Ht^)jr6!f#c=V2x7bph-S>l-Y(w|Zh>WnTy{S`1|iiJ;@ zzfclAhnB!N;&fxm49cQYmYaBT29E_x!1HS z3oyy-nhUGS0#cnyUE^U5vgS-30a^`r}v2gi~JMZh@nvLbO!OL!cIxFvOLI6 zneDqWywdNcak(k)-shUZ>6_o(^=Q@8#xvOsb>KpNhY}DAh5W7(b|RmXo+R&|?7Wt> z#StWcLpbDCvYb3cQzQ-5qO&`eGcDFzIbV`V4CqqzpXxL<-?0m;_t09d4k!r|w}*|O z`FQ4Nv%=ib-KZ~XB=s8s=F{$hZu$X6Gto2gr_OM20pIHD7t*Olsg$J(>8lTg2=nP9)>FkbAV z2gCH^^i9gi_8r|e7(3n9kBaIho*0R^un6|wl6WSa++fiGc=L4?+s4+pu(4Au^MwJU zME0nMXc&51YKon@?G~L7MY($qGX+nnKSawC9oXP$By!rd4sD;Twweh+03ZozQf>?W z8~LB$2}t9&O^_$2MuwY$r=)pOQ}A?Jx)#;Kq2=-N(OHf$Z1B_-?T4;JL8t;pmn+)v zj^K&^64ej&H3d(e*wGU;UD@C%9;=Cf%A+FKHx#Fbu-HNk2ClEJ!X{Ft;Asecq6j3% zT`Jg`{9o`SxrWnt4X#!Q6ub>_>r27JjIA^qJW=!s1wrmofTN@r#FDoMPf*T8Kh%Gy zDRhb@Dk{3A5Us3cu|p;d8Tnk^23t04Yb4r~UvgpS^bs?KPK#A98!u*mtOM8c|L@RA z=s?zyek89j`&>&(abHDy=rmjLk}RO_k`?rPTHX;ljZy1|`pi>{SF5+E_p7bDIbKrV zQ@>FE8duUDGQR8rAr{sYLbWOT)dy2ksYMi6NBu>Sl&!}HtxNCb+J_X-QJ>*A&z|l> z52MG?jykS_=DpW8xLs;8vFyPe+E(|D`9)j9TVSwmv`#!tw^+Acryn}RBsY;t>jFZ$ zn?|scnkS;|TQ6N%?GO;DZ&S{;U#s7tKde8iFV=&{`Y}OGJwJ=S02N42BRb5z8%K zlUUQk1!2{gFSx>Zk-I|d$cCv~kv3&!uo{73D!bAN2PUQKw@s1nNCmUP|92XAR4Tk6 zO+hQAyvg#gESDGGLrvuVv<`py9<8_?!xoB z#%(MGQ#0D6>{N_5J=uD+MUn*z1#Va#B!phqSp?h^)PXkKr-8d z1zwmF4aG>Ci35&5a~)N{l=iV`u7*ZU_SZUaJHI3CW3xVMQiwowZ6L{`vWr@F6wfDr zOMN!Lw6Bb;fok{i4yjMLVr%ZTOf4qV>FT3uhi*d1-@yXlQ|x;A0Y~q8 zQ`QGksom5Gs)t95wtw%o+NTuwFYOC}S)YpzB+}CjpWJUWv5t$PAJL$Pu8A?%Il#}} zl=TT$>Ne_HhkACPjf%&GASO=9)@C+V7=6~6T{4-a_q)8n9;E2MVjaUAVNo7p5FP2| zV#WNI^oiFnTbZe%e;8graqrl#F2GB{daebEFqrg>5RF5VDy1wlj&)o`qNVO${=?X` z?}x}5NlKLTM_So6x9hI$!2<8R3+pp85WmX@gD)Wl=gKv zF5z|Q4zyOvn=PN7)jvkd0M>Jvi8i7$6)Vsr`1#9CX&-c4C})gsCrs>wd13+Bg%i%K z<4VPTHAnmo7Qj*L0(KkoyZmUCDeD8S_z-*yUR1Oz?q0!xvoiPwH7EOAiJAq<%uN4gG*M z-83M@Y0B$iRE_`e`l;uG>Te+&-sFZ3-4Ku7zqGA`dkdO$XWMyKytS$Cs2}-VTTJpf zl2LRReTMeby&2&8&HY{z5TJ$h9eTLml==_MFx|Myq@JQYMlPDHV`(AVb)5#Scsn*Y z?$px}7b+_>VQjm63nHY zqI8?|p!AGXBi)JC!N=xwc}$jjj5*4RIgUg(!z!0zCAv;wp*V?NK_8+zl>ZrhBAhG2 zoG}>|jNQuSxX*wa$prQ(qWea6LxB} zwGUd(HnFt^aDl!}+vsYTpR_=f$;foTRBTwM{{KQvcQUwdq%{`=+zdCpNF6 z+L2M#ecxVoFK)7x4}UYqj=Ru4QZKaJfZ50ExzP?L-BSQ%Ui6+4Td}6V(S?Q604K(i z31A|b`Ai}+T6B=H;n|44yS;MZM0Y(c?IHr7TIVgc_Qs<(H7Bu(P;~} z?UfTG%#5KDcH?#y1TBnRo)8-!&#a0|kW84fa*2Px+ah*y?WbsCoQECK$_nlM?aD^( zZx~jGhvh?EF@>^q!PAO+FZQ?N5xfp5Sw z@m%~OF1ZU~V;}J=3L6D)Q(S5(h{zbM7_FG5SPXY~Q^{;a(h1UsG*wzV5l-u^%)Tdv z2Y1|`HQGl5wh;S?)9Za5>!*02EDHED%HE++JQRQXIoDp*N5$$F&r-=1s#lE#*`MmJ zsn~~>z(NNr5if2=1z1GRfG<7bM>;;t7|Chx`b;M6(z7q7;faK6Gp!Io-;1UK=a=hj=- zGyYJRRMEgsg`Rw;uu~r)5yFcIB!rWR1w_9PFNkYspY1IEBfyIlAp1sa%B=g0u$!z_ zCIRF96(k<3ieMVj=yLXFUB6;BuVn>p!GE0NZR9ld#h)CnJ6}7Ou|u3} zHD!Vtpt@n|xw_A^LcKwqsm@jNFRJ^6c(T)LMzs~yEB}$VD>Z}~bJcT!eWVA@eot)X zUn-Q8aheh@-FUsGFoPKVPa8udjOG5}z$)9vuY3GBtdBDje zhu&Y;`yZX1uQ%c|ip$Zw=_CU2y73h^K1GZ2bvtysAx#7n>r8@5mhWuD1z+9uVqblz zex}~(oXkY_`eep~xq(FMD3=RITjJK zilhWmx^^&&_9{VsdCMG4^Kabwm#!9na*Tk?#YXeVu-3@!HifklAKZAGs_iNmMn?IAQaq!=* z$Ht2T2yU{1*AgdwQkJ(uU}&&LzhX(}{&kh(8GP4_1q|gkz_OG!trD zQSAe#ij&N~SgVjNVaMy)JjMJ-m{Z|f6NUpX1k-TSJ@`QNO11R6>)8kEzjzc2Qe)_Z zQjT2PnQYgY+t+(inh^*#MeO2RRnI2l$Yipb^B5 z&WCj>(Kg+AQIfw%qce4>gnI4Qu$17Dd4%asyyfp3XSx;Ld2nwq`Ygw}P!CA~`k?8* z?AanRFjbMGn43{I#E&EIxPbreK+_EkoiZ^E3{I?#nMoX zi7dzZJj5q(f+PW9w}tZ%r~F}Tfv>FrStVQkyXGm7c9r&%9=beXGA5lP1uLZ{MMc9l zaTwUuH3oFFL=n^r4MZoS;svM@9fRc`8dkEqE#@i;;4U88gpR-l5`D2rgiax!jm2Tf z*e>jEY*E*!5={IAW1q=R`F?DFY6$-8=3HM>)e}VG^YKLd(B*?0O*Lfj7;nH^@m}}v zq=7f*XSgeXuOd{zF0CXfG8D%Yg$g0mEG3wSe&VO&a;%761Yj#I+llq+HAJ?0koq4& zOA(KV*F?+u&ShI7*7ygq=vg0Ch-z8w@Mu*l>+Bp6OkAmhKN&#wPcSj%(|;r2`jb>HAMakPfFudIdu=5;;fs|Ko$}?bgbtF7Xc<`o zf?LLwOl+~poZ4bqtgk*q-{{R$-|ub46{LGw+jQfmqw_1i-RUOy{5hTb>9dut*Aub3 zc3?S=2i$#h>=XQw&QG7?Ycb-CPdS$};oA`rqpPd{6MwacQ2pJLZpeAjSY(F&EtG}O zr|VtgTRjs!nLs~DM8ceeRm@6>i6chD#!LD}g!e0Gm=tvVT_Si`Gug?dwBplSC$~|& zd>gOG)L~$;+&oMkKGqBYv!yj%WJxZ^A!|eD5Nc%>$j!1e4<9o#Y2;a|`0P#RyVUm) zlRbkc!vMlzJ5%}{mEVDbw7d~cr&QNe2%RzMqZ@qhU){#h)+D5TF|Qf3a$V^9-<4NTwv zGHlVVx|myN1=@(RVC>%!sx7_{ z5383_#cCd{eInr1)~mrcwFT7!;?)N0CsEV%4Lb0j;CKzi4r-@%rRf>|?N4|5et9I- zE~a6#?oJ`szP9PFJLj8s+&WJ0NI%lTEv32nUu)=QTA=Hy>!$++p7RV{jxFI%(3x<9 zauzpuS$AKzPp{YU<{J2a27B6a^1uBOEztYFJ^u@YBggd{^ji=I#1wlbebh608^)Cx z!a!N})_}LM3@iw>1)*8+k<7Huq{}&6roGSsm+Rf_YhC0!Z&$n8zHxiZfF0@ox-~UF zb1N^Yc4Ngv0jnlDMO5IKF6nY?ulHIJfU@O0yX-RWBiY~O~?m>?u#UB zb8iAdBZm_M@>Z{a6UVwfD7Fjne_K5$6MKw+Gss=o9bwZYHVPfk?`Jo@Z@`>+Q|8QL z=EcwO8Zu~*r~fP#?7(*U<`@Dqq~c@Jt<0SPf84rS@N3ZA`wXx|d-~kJKPYxM3_);o z1qxEo&e^)KF2@>T*visjQ4))oF%>M$@mUy8_$sU-_f$M*-~uJ_1oM9j1}%R`*yDPP zr%ET>@S!*ui_gFZNJmLc&Ut$4kswn@dS}3*w2a>1mDC^&Q*;>>o;48tOF=3CE6p+R zRi`xn$96d_3UdOm7_pHMBQ}RvN%*Vw5FDOWnxMWSCkZZSzak1T;HR>n+*JdqE9!Rb zEmcy6>X@ofbw~AF^+7e|M{u1riKLmil0{M=?}E0ctb*p|zteXVXnQFjp>TNx!{>2#HguSnj_EA~zkfgDkR=$5EL)F^5bbw;{K zg`bc#|Jvt|igW92PDA=-RSnODI2HLTa3(WG`!W@qA;vbn~Y2G zN7&;doRIDfFXB7E_Z~Q~Ryp8aDvIc!eal(BT2tYu|NXH)@m7(-S#fM-dz`?laW&yV z&fi^|wM_vID$Xc0iZVr=LiT)QTHs?4l*5)TeTWbuidahgNl4O&-LODptFo^d+r6Pz zK6p?3gz~e_kfAk^nyQM2^CHw=s{f6k7qU)p>5tG+WEdGk)*mI>BLuPA1`?9bl6D_{ zTJjIs_W4RFxKF-3^t802ueX*D{?w%MHSxqBDuS9~6AETH%&r|k zjiSP+n4+hpNqTUDI&k@{eiUR)yrlFLhnCyXZuC%kEIotH8#IofwdtDj&wJ@NZk`6W z^`j72XKC(HOtXbkFl1O;ODEk+(o@H(LCx2BUhty~rGsyA1*zX-<-jv5QE9q_$+5%3r?LBwV~DI!+N>FZ+fQDThGo*;Az>L;8QyAB2a^_Pd{^@tvGY_>~0jCyPa$ERCk zTabXktE^XWa~=)Es-K9tAtCOO7@Gw>#irr5mpBug3ia`Ku;=zb-1Bq%d9;7NG z7US#jop?6>eQI0hoeSZ9>8h2<+9^TLr|*h;hyTE%)_7U2yg95}^u(TUMa&kxxRP1g z9z46q8Ts6Hp3neb(oW`R_hy}(dnD_k0(7i>C%l@Gw&ih5j%j8Pc8kVgCP`%eMpYHT zi%N^G@00&OV^n{trcsMk>nTerTLtn}tN>v?eiMI+vuRNA**0t@xtvTQ^+$8U5O!eV*P|UqLleZB%DkLQA}9Rswe+{c1qiHu@mlc82ct8md>r zMgYg{A+4i7(@*w&X=#5r57(I<%WwQH8e)%K=K@l9PFJFPqI;t=-G}`5dVf8y&~PO< z#de;4wH|EI@7LGq3lOco0!|>9F`ygc!Hi%gGSN&tlgjL7iaRZxWI~0Gvm4eEX&;mL z!B~qB5qPrCWk|4Ss;Hw42<+F^OJa|G@O~)Li9U;Xh}<6OgA7B)A&yc7!mE>j&#TS_ zWFW^77M5fyt;N7E#0=ks{Wm!yVMk~3r8lK(AA~nZTcvH5s4}oUIh?|g^h4Q)>XUt8 zu`AJyDAgAL3?4o0jb&m%>P-_gqys$uQGPVFyV*D}qA&h4m-S2`fUW1ikfK`;2 z<6_kSe6XsRh`|9woZ+TAkEzU4%wHPOMd7aSRUBXGV2QAkKTcB>ixle=@Xh|2bwqJq zQK~Ri%)#V5|Fqa+Avqm^pPU`fV>>mgRQCy(c@ z0`JM6q)6?omZ{%)Dm0mo!RoT9YPQVwml{^t)FtXIPt->#qnfu|Gqrv=e6(J>ZJ}R5 zjk|RH-&y)|Fuw+wdS|^!Z222yLHD4=18J0=M4vKFj-!+5UGRI~eTeCM-{Uj7iIgYp zKitx+qrn2N=Pf_!nnNuueRQx_qpO~!yU0IexWPZh<~$p13c2Yj-I20Ffr`VO6w|#4 z-hAcadll|ab&|Kb@49I)y-w^lIn`l>E$B(HM6mFpmX=IJr@#CzsRVXa-XK5pCh6?X z*WsEP>jA>Q24&AQI*6Are=sl1y@d0I1&E`k9A?fkyXawdXSb#^EJLgf_NJ_K`oDHJ z?K!-Ax3#DwUEF<0f1c}*VHQn|=Ob5*C1>Pwh+68@k4O#rKz0@-^GX4 zPmaDw0BcMW;O^Wp(e5m-`X;$!`K{7i1>mUd)Nbmb>dekbn&bSqL>I{{x-%nkDEsyN~83=pe*nB5|Xph&#Z14iwhfjYe*4jCFWT^C@KY|> ztvjJB(ml|<(iwDIeHXpBJM%@qTc7J6HK##sJLm!^O8W!3sh@Sdx9}0dXI|-nxikyu z=sNbGmw)jOV!i1Jrigi9n4x7_*%HzkyY@P`IUHDLrCfYPKkiHz0%nO6q79-PeSG*i==_ldZfp>8FLzdA)sR%ag@{<_mF~Myc~=E z{Y*bGpd>6gX0#`(tHDmyKQPREYlFI?i3h_jl)@ZW#Lga>pmX2vg1=(_o2_U?C*;Y) zqGuhO8t;zzVt*ZVoD}raX3!kiBY-Uevb{%uhaNoR%w0F$&y-+W<0`z%CCFnAB`@qi(DmP(g1^DLa#haG10>_PM0&=S(89PEvLzQL;`tc8AFl;xH=NnNG@@=KFeG<2vX4`ThQa zZZtig&)4($c-$ZDcFb@&FvsUMCM0_}6@j03yA-`;hNb!3)e7*_-v!B5&M&roejC<9 zyT+eyuZLr3`sbqe0?2LD@B|zPTZ?E6-7ea;l`>jR%4&YFbO@IwW{Y6iTA#Z&l=jm1 zQ?*c=D-qWo?UZ)wc@f$A%?7SNE)FRQirR)4A-DBfM--hlMWI>Is98+dd z&t0_n+FtgS2gqxn!(z6~%3!^`TSkQAdV`yR)&WkApj!Ulpp6*Cwy(Nb(KiK^fhCTo zl)n_1<5{8jsg8uJ+Jm@&Pf!cBi~0P&>aTL}@HQ5xch%=Aj1_eVYmT{LHGWw0zjs&^ z={7D1vbF*Xf0E>lPUk=yMf)!u>^?4bgnt*@0w|u0$KZ+hW_&;X8=<>_>j$~_No*dB zF6T`N;0n)@1Lz6FEcy$TOk@xsm$*V?sJW^paP%T|2HoT#lt;sbuQKo&A7K3?+*3tUfD6lMNXgqpXqi1y{y@Uhn>0KPbU8ala zH}rSOw;9-zttA-Z}sBzQ-yPEcfVj9{`9L%X~gREdpfh| zGzrk{yp9I3Q_t#Tx0$5q{HRQvTgKxDKU!!YgXAF*$qF# zYh1B7T?D+*5vnCE@mm|aqXVP^IzZNQn4&$b2OYC&1;6m1zVMT9!M9^kKS7hyg0;d9 z0c-s_e@*N^x6zCVtZ{rOjjx3?TeQ)?$}ek{TMCu5;&Jg3jOvzNC^cezb&I0Sm=2NB zLTU77uOCN8setsEsy(NdmRV0%-DHy-EQ1Ta6YS>8mIz!Kt=K`pU>vN8b#(-aqtZd? zp_m3LUD3A%pk?SA$BW8+<(2Xcq79q~;Gvp`oA`8f0hH+OPz5!9^k&b$ z)F*0%s>9+UBPxs-+U*=`0;PiM>p-dC6bFeZVUn?=9^f!$WN%?*ST$A$U$`*D9scC; z{@(Zid@Mc-UxIVEVHbW3Uq;-=^&{PfCmMsnc&-7_mRQd%Bu3EFh&bA;r!`5&ZQ>a* zdb5X7dsO!%52Q{DC8v`$3&@xKEKE71 za{I3ET+nXI-9(e<5G)#{d7^$%{<~)9O1FsMpmHuvGWwKD=Z& zD*Y)HNrQZ5XnVzOE6U(CFr=`RB~fFXeA9P|oms9TGvr+PiVPmg!w0*9NdZ4QqHwIP zin)&xq=YN6$_gb!J)r2poeJmBN=Jg0m4B27dYB5@6Ta#Iq6pXc7@4Z=2{p2L&pYsZ z{YkBhEsZRh*%9-_hG3_fz-EJ?w>{d(|AGBl3^sco$C731(q{QWFwT8L>}3Dm_;6f< zI~yV089#-uBA(#-vF@W2fot#$r3v9e=+$M!XnHmQ7SVO--9!#?nJ6aS5Zn9r?O_%B z97~-wp8Sk9Ht+jc@+y`25C*q>ikr#QEbEMCVM8^Fit?B~c|5NuQ?| zotb63Hg{aS&EM1AxHa_DF^}g!o!B)xW87h`7k7($L4Tp$>N7tvHuK$kP3s*vYCUB3GdWC$WmajUHXi(1{3+!n3E(Kj2D2!6@9o2nbHCpK=hL;D z(?j+xiyqSs&RhlbB_ND=f9h^nK;!cRW=tofd`eW~n;E6SRyn8W*Vax`8 zF4M+gw#F)|9e&IzZG=lj!C7!v(4}agfQ~%?iMZ1RW9#?%?oF$27Yaa2v1%zI*V}N> zNzz4&`gi$N%}$l3h6+|$r(%y=;WBe zf?W0rt8Epdlz1gbb>5@s+X1)G_l`DEb zhe2x4_?~dpJkhBBkO9T1PzDqfF=y(GI&-FXLJGbQY9_xntb}Qgd1C{x+$QNkZuLGT zwex(C*XK!|SEyWPq3s^;#j@^1k5m~F%P}1en&Qb(Gu%^Sqx@}^=8BtQhK4y@dyOX$ z4{^Oir2B+K?_iq~J@s@j@%bgl>ob~8CVbT2={7WyUl@@7B3B(T(o0fHRDUwT4lBD7 zHIrOS{y~24H=ER!F`jaO3~rI#_dksIME)VSp?;=F3XGtRAJ`FgAtNLDhhYv$Cn1lV z`c7S^+tGTkJ*;QwjQFbxva_hl1sZJSvgmW%P!3%p(Syad8zay2w4Nc$u9VE($z(AF zjK^~LQdKPiAXDm4-GX+Va>*-XBQ_H>%FNP(7MXU`5OyMqLdTyyxs?Py-+hpNjMWk% zzp)KD1I~GHDi_M>3zK?=?#KoKFzs+Vw~+qK-4vg3m7>WkYR?$Bl-%ARU|${o8L?Jw zA7lna--gQYk9@>2tNm5;xNNTr0*YwCy7xILIJE|K3cEIKRQf}j0gsYKc$E|*L@#Nz zsJAcd84B){9uhTkOIOKOg~7{iYOXR|3X@Rqa`^W8_6r|)cpsN8Ne`sgQgUQTjDy@- z?kaC9gR=>4aWD+MZ=sqll;_*0$iJ}YFoR4kV9Ma$ASR%n<4+0!H$Wp56Cw<)R<92r~j3r1m+vBDQ^=#b#nh$l4OMsMBAh4Wb?^1od40E?vf55g&>txE@kN6*x;C z@C*1aY&pJ3PxrHuB%zbvG@tnujb-$p$S6Y-NgXKhLkn*>_!Y<7ft_-eY}NV98XO3~ zqJW`}u5fvYlsQ9VTrxBnEM<Yr*+ z%`@Z5=6!uDRa*?bE4D>0=#PCyo15Y$me&QGN>*dru*2Az;#}`L82Il+oVIX*dsZwk z`)ewn_4sZ)2fvIv6ytk|@3?-xdu(E0u#o_sL;x`g?ic6L>xiwi8*M5e?hhCi31ngF!iD5IawplX;Yc`@JaTV^cDbO0TvPlyq7J-WX-5?>nJPMPIIKM5 zcr-`tqK;8!YmRC|`Vs8`OWL8Z{W%Nbb44Vscq`te!2vFxzR6ACKGF^hO1HJ`!zlB5 zYEi05jNOBhMcPTF?{e!@au#MzG-KBkgSMHy*jAL5lbXWTdkspGT0eW4{@?6p{0Y8c z`f?Z_!RenSJt+r=vqNaKk6A-I@K3}l4(OyLu`>^6Kg(^oeQw_#fAE&4F7M~CxRn1~ z#oG&U$EYEle zaVaT1BZ8aaQ?XL)Ejg-gQV;clVwxmbR*O*FIQqGFfn>NVJ(oU9b9|N{wz!{MyT8oZ z=f}#k z(3;nun4r!iKI6%1hHA)Fuc!~zwavSKRMD|6p(~aixm3%|ecU9yevsR?!gl{KdiE&B z6@ydW_pxCt@*Ci|2flY9SmJ&nHo>39=ieNiG96ugS- zK@23$aT&xyI*9-~q0>ZDE7lN=NU?ukug+v|ayS`A-b-bdlAqDjwed)+g#meJ%1N&H zeMEf`ey9i{3zGQYWaZlx8n?XiUpczoX9z6LOZscOalygZ7@VR`#6~2$dvgiC~zMin)nAO67l;2>O&}G4>A|w&BD8vMCL+IDK zRpH2{#!}5AW%dyJ!Mz_+g$Q~ENbJy7Iy|clt z6=kE(u)igj$!JfqBw!fymIs75YE4t?nTBofe!NJ%rRax(A)&3Dp>)n(ZK?h-F4L|T z6a!58VxC2O!8syR)f}M>8s$5{k>RV_0Bei6V+DI6mup~y5=hLzQ9RgJ#3s$bK$ivi z-jA?%n2KrkP;hYJa`)4*Yy79+arjDn3vN1ypM~;;5?mnc2z|UeU=yi-1>O4yGYvKp z8PKVDjrf~D7rZBM5Bt%_>!Q?`97#ry#aqrNXbI^pM!KX$`Jlz)m7bCJ9`#sw?;Q!Q z)~SwYOr3m;Ob5tF1s)&D3sW-0Xlwg4l~AaEwxG-DUbG%FgJU@f@l^_HpPj!J)9_>X z4wrl3+-I&KgEPnnY6|`Ji#m^41@j~t7AKx$K3``ZGeehKq&4~?`x>SZYh*9i?VQ=4 z1*m_w~56|(1yuZT=)IMt*g=NRALj$_bg$kGJ(naWQ0<^e0P{P&jQa|`D%#@6ar9Y%JDOZu0qXoG4`g3 zb!b418?G;I)xGLnjupt(bu!3axX!&Gc7s2X$fD+HLfx|%e}kVSFhal99jr(k6Z~C4 z&C^TGCRWp6Cvg~l0oLZ}M8;pZ+{2gD_Hw1Et1GnYu+aj^Ktn?zSxQ!sx9ZkL04?EG z3%Gr8;CvYPlyN0GojMNh8xN@0R1IZ7X5;sC0IjFOPUrj{542>x9rO$M9JoW5a^@(m zE@L&eU%2dTw8|1&JXnJ=FKeDNq06m^3{9GKtFBijlD_~HM1*A7POm>Eb$#|d9o%PM zvFH_m9s&K}@MqheU%=_jNfqS<*~s1wkiXrD{~$W>E#L>xhc_Z=LM*?6|MIE(Za#;1 zxXc&xLmk$B;_C`+gf+(yB4bQiD>SG~65#)JWKn|f3EL-}68;jN2w+6(E`^hudX^$b zi@WGAnnJ{B;(R#!jggLs`osCa#pP3}Cs8I=i;=_#$xQ{nNJHTV5F;f@+FCBYTTd@E z{?|y2y@|47a2P~g1Wb2C)4z52 zHyl<(<#)AA(bHgDXjf-&OGNkII?@U_{71ueh8ZI)CkxA3Zpw5|BRc$|oVwh|-zQ@+ zSWO~U)xqFdF^=%4R(cr~kb~F8uvJCX8tMM_QNE%^qm@cR zrr&T2IFxeVgKWoUp@XpDn001Ag>$-q4Vqg7tJh2xoqdt&e_ZSCg)^IiUZrUI|F3#E zY!D|)Cq%thVK*00naNqI*CTEm9RB-Dq3{DR{ad}HdzXDmB!jk?TjR4HT@%L2wO7il zGlRDF#Rl!M(}sUb^>R|U!7~6K5asy)sa{u918Uv$cAC$FCFZpxthVdurm$U{t*#iG@&F0JhOtgb2R?ZS;2{ZM%{8F89!?*D|sy z_0|RpJE6DFjG|GURn1#u3a8=C&~?L*{rO{#n7hO@qH=E;;=1;06}L^$gU<8Ng%)n$ zC^h3wSl#31htZaT*6-XjnffQdp!+h=74^+d^h&xelb>g^;ji4i@ejqd^bXo^txFuZ z$~9tMj{U-|btwlV?X5t)lBr4>sOqo-=MR(RZmywfCrHzIuz+97@8AXgJb#BT=RffW!t7I;q}jDdxBY3K?o_8Ec5rwz zodo_m)nqEMAOxm&F`1mAV)E;nh6U6wCi%NxPK{0w*4^*g&#<}3uU}fxz(K`V1(Zz) zR3Wn2h{BkrV@lmlW}kq%2*101pZ?4E5P{SoUh3E-rH89ar44`og8~Li`^Ka_8KAC_ zUeZg{`l@-WbVxcU6-v`)wA>X}?yk;v5AZYgn+!G45t=Akh2A-%Tfg8=O=~5?gHT3y z(fJ8u*GsMgrO>Krw9TLQ=ROrMKQCLaTRNzO_ORdnCe%KqH07e_fNk!Znh2j=gg?o5 zWfl=Mi$u`Z%A@}%1n3+dFBtpwY1XyhfM!SFyNE>wRBvVDa2vzE00-xPncmR!>M0ib zw{}TY6v~D+-c+8#JfnPd{De)jM%{1*)glTtddtO0wS+V8Oq#O@%}vz+o5J*S4Ys3# z?R!tCJI5W#dQ9!=U7g}l7`9o5H^p7?l=h@%pW0YB0OpRui^m^(X9aRNI(b~g!F{MG zys@yG>2a)gFj}hsR9dyv>l9)Nd6KZv|7_Zy_%&D?5gj4$itNG+Bq`=Gy_7@`6Z3J> zs-=cEwIQh$+JmHEq;=JUe9)Vyb^BA}z!}O4rD;w#I5j>BI2{j<51_5E{GGG`L1~hh z=d^xY)XSWX$-vsXS2JVyIA$>q>hTAevkbcJXi91aq^L0t*)jo|>&>k4?>(5G|I49m zQ3$l2{oDQBeH%T=yw2Xabusf5tGl-c*l{hmPH?9^j0=6bDsB8Tz-7l?(GL| zT`g=A4h!#{{)8oPmIfk(=oLJkkg1L=K!DnH4xTm3BEzIIm)SIwW*X0kn5BU1^JCcBQr7Ghmo-8W$d zWYve+m=4=Dt!wR)_L_d^pA)3X#;vhK$9?ln;P}$Geq-@^N5=&=KQ<-s6KkW7?XP{c z_wn%wKbb&8LWf`#Z%ni&yomwCSi&%iSV9aTcM*Cg)2NHDf&sLI5-*8gx5fq5hyK)A zzUE%cRhnkv$d%+4@*vruQPM#8)VfCgO}>W~t%4^GJ2V^C(UI1t)?_M%N~D19WK!J! z?gT;nsgY61$H&Ec(Sh`6dIoJ;ME_3n^ii5+ifDas6c}|8Pu4ck-I)1I5D%s@vAmAo z%2)y)m|=2!$_lR(tTEf3^=2Q}-T5?xoyN{*Uo7wQ6mDkqI#cRzKFtr#8{GUXyJY~l zm|4QE{z=biM%5B0uqth00+&65LkAM1i8cPo6>%@P9KJsKWS3Wikb(<@i4W$#cHYmM zr5ilh%X>oO{9|b3x9DdM8LyK4g)zcR;c;CaeX%u%1*bnPFRdaQdo+Aj2%86eEkb+< z;3p0h5!j}z_1VIS2^UJie==)LWo`RfGD-R~g(qBAS5A@QB(PH2B9%#}R7rZG{;Jx^ zVW=`8os9b2(|4w9SSPa5Vlwo_$l~d zLovf7EDDRqHrDasF{Cs|D8dHL-}M2r!&~4h+FNmiJzA!-;5ZwBPw8*QKd_qY5In?( zt?6i*n9wcQqVXrpeTX0;oIs)DA>;u#FSwf8rF;nP#>>P%#8iG52|6&oKZw2yBVVp^|a!&VkYKr@#dG zkxhyJg{J7qbPSzH8#mMY>C^OTMyB=Sqefi>Zpk+YBtg`Z@yu9$4g+AQCyy*wT4LG8 zI(>W8WwjKM><7CivY*jmqhh%gN0`QDvlrN1gKlQNMu><;oRRb70=N^e*QZ^622!*C zGn*o#pF;(Aj&I8AlhW2!Pb}!kgF*awel~xC|3li%XTvYRRLon|h8yd6_Yn+1Lbwns zyl}`!7BYlfq1NS3?WNTMXr9wugY@ONh}Jeh+uOWteW|df>5bC8A~-2t7d5dp(prCz zbb}=Q#ln1-5O z<35zvk3N}E(FzUv-4ytL?E@Y9m#O)R28C-k4txV1Av$MG%8!)%Mnr`hr@CQFRsB~` z9SSZx>zHHeMb(FChkYg*V!#Q00R1p46s~r9U#}l^4I43kPYqTDLqMH;zQL(5Ww3}G z=ca2uj-7P_TjqzfUDaH`j!1rH%84EOh|AyO-tw*Y^iJQ+w^Y= zCD$DcqugAzug>8aF^&8wbx)^Fw&AF{fv-dZzg2;*%q((=?&!Gz`0P;j{{kruh)8JxQf8!W zte#r{5Rp;?Ql>*7)yxZJh6mM2u zW#x*2lbR&<2ZNQ4M~60xEDLS+SHDTk9zuv8beJH0Rresw;1|;T|ICVz9Z~7#0#n-5 zUsNNdPF6*=FIGL_fZeo5&Nem^TkI$5Vg8Ym+I}YnV<4XKBF_`!uwSvISQ3_wHUHE; zm^x$M`%>M-?nRi}3v771X)zwNqYfHyXM93;e0O_z94<|3*Y>5k*)-4R&8GBK+MZev z7^&#M&}j(@+GH!Z4H0YZZ2}7u`UPt{^zp=Of+Y;=iQU9p2ouxyf+RzSa2uPU)9=wF z*~(|_@XibiYal;Z%uj-B)r5`A;TOg=p7}LHCMtTg6?; zpzxF6NZd7Qq4J*6ki7gUFgHp#K0iK~MsaVe=&iKz5RF8uJDDn49~BjI5&V*zqjq9? zF>ln(%p86>1CpV38eQbjo7{$N@>^dYO%xcyN)HZ4v!4^#O|0Dpi=ukgn}#D>o}{3n zdRmM4>fO2;*nihIF3a43>p<0>lQ_y_MQKYF5*4V^nIh5jN_`uo0mry5O zpP9C=I=aBdrfRQA+Qql>sXnq%D&fIc@|rZ}e*lNZSL8R65ug}-;1L++EPTCw$S0tg zWg_Yb%SK3xwf)U0!@HD$=HmLshVt&>-^03;qkatH#f>7?;Z9+z4i8ILa$C5dgUi?N zfhOqV2AeCc4J9Kkc|f~UW4X}n$ltDeD?tke8KH;G>{5PJg_o3KGvcZKglUB{Qf}0z z|4WOE8d+l;4#}&9Y4ZiNa=b1uA5=|PZ!~={)jB&?rak-cWpT$oe4Uzo;Y~hu@rHxq zxxPWoCYOzE)^K@vvmlXEz%J#Oa#1k_H8J!LY3=;)oyS%hqE1v9^%u-}gQ|Bl?5~!c zZ6>!k45^pcqSWxVHslbjLh4CgB+|xXvoRFLHK(}wik5-u{3-pIsS)G5V@U6?O5Q3z z!_LVCbE2})OUDP_+urIq$YC$D#VjzMTotIYjXABfe#616HA75`5`u$~tn4616Q;Su zaw3J;OT>}a3H@Lb*k9cud?*h{M>3wD1N%70<9}to(&(Xs-Z``6_ex0pB*D*Ref;gN_M-qfgotKfn>sp%GD19%fpT0Hz1`>~y~4Fk(8qm@TgJ2)7PPK_Wz zUeh)7HO9#3TbmbMe31-RNukVi=G?WI#Ja)*rh7f$CtTqt3EJHeW=R+K?fxsPnRf0! zIN`*7?#7uoVT0w_VpFu+gs^#u+}{I!&)Ls`)7%YC=KkUI{NJyGvSx;W(FGn5oEFMY z=e3QMgTOBl?(ljlE3ew=_D7ftC?H-AkQU}8Jb zOKjdU4_&e2#M)cr%4c;hx}Maqy>6oJ zPp(i>l>PXl-kdW*UIdeVEE zZiT0fL&p#@2jd*-cH2jSYD}tEOiqVObfnqofp;B<|Lhh_O>f?NZmW)_Afyxf(k>^) zb%Rw^wB>Oz)A0p(KD7fETAr>zFfkov2NMGZh*S?X(3h3cY#ljA);-p6k(Z zOAg54T-0Ky%>53<8SK{yS%9mWQt%5;@raO|$ZzHi`}x!G#V+&u@mVA7+-`#~45@E7 zVe!IPd5*9|HrJQYW9y3WP@RT!eZO4yC#Qe;T>EkdOQ$-3^-nK!NUcP2vUW_G6v&t^NcW_dQh)i1ytwDtl|4X& zPA3eK$ID>htMZlDUov=7d;$x^9%0D9)j(;hnEqr*WrQ+CiBo=Bc`jM`oS`fef7bu| z0EJ$L3u65*ja*)fphoPchN?*7T{7;L;hzxjzu{M~)&)7F?1g0-E zoQ>Gw*;589uvBa|RJb6M#2#$X~wZX&0;9JTP zW6K_>H=YF^0?UqN%lHKX$L?Z}v9=f4-9vh6-sKdU>(XNhDQYEI=OXLVp7P$absD}5EQMd)PVBf`fCXW% z-0NHHp&O4Yyeitt2EUUkCn~t{^IixBecf0nyR62-H>Cv5qd*9Esmluv%5e z6&bLpRt~rMovNyhF{F>x<6|*BxNEo*vC9)(l+v(ltOkQu_?Os6s3mNRyW{?N2yQzK zZ_%TBJiZY}4CHRB+FiJZzr?@dGrZEBTv%um;Yi}APyIuu5XIa|VhaHd5@!jot#yO? zZPXCl05P~xH5*ONAbV23lQw#XpgNgF;Z21C@-8`80Pd7M>qK>C^O#_2Dm9OCSVe86 zhD`Iyr8GNqL3rN9dbAVWjovY3b`Koc{heD8U5L3fX!B)Z;$}LI&?e1)XfXZSFXrDa z1SD%hi%`Zioms%FWp*&L*z=6Ow;A**s+*ogeq)26X7F18L~XIHXW)^W{hmKnrw*vw{0_7k=B)==Bq_`|#b*#~%`n%75VF?PS)1}%loLT_QXkSffP6NF^hY?QSVc!i)7k6rRG zYWMFD@mkBvD4e8blW2EG^ZVPl4bwlMzGJul>bnB&KdGaMJ1bZ(Vt+tdGAKlS7=`c@OrPL0* zvPa2Nt|`9yf8&5ylbt1U_IQ^4^Jym6DHA=~H&exB&0QS4KHx5ywBFqnJ#?0-V1rtB zYO$fo)Thp;)f=j;n*UKXYrZd52cHN(xCe&&5t*LPpkpNiYrW9J1zaYf*|gOsGLdXU zdEou<*id{r-e9O3+*q%`4G0W%2KQWb^&yV3n`>u#X^yV1KcEmNRu2uGPN48+u!9hY z^F+_BSkQot&BGM}Sj{UM4x$$Y(L?%1LG?2qg=?oA@S5ySHDHaDJ9~~nr%E?;tDNan zKYonY2;~Ol0I!r(#K~(K2yge4K1Z`G<6y|>czZB?l>NsAbZEzAi92XWfu(^Zxs{&r zSAcoZg(1l<4Cu)WV#YJG85q;b>}KY&y335dpP4K&q?<7$@d3H@BG}%-YA7&!&nF05 zSfFL&lq^ofku%DbE7lwPt^Y6_G0ek6Oy`omB6dV__!9|~Fdu6z*7mw|*$#57uRR|Wc3Ui9@DuV@Ge+c7r; z<@0&vj^eMkD2nwR43#e@(NT0e6?g5e0)e)=@axVjGqjotUOS^{P8;TsmdwE)GvL!O zeW~Gbgy8ua!snsv#K_jgpOV#>EtO1~5a*r3k>@VxMb9MMfLiAz+;`PY4RTZao0n#C zas(*bUQ)uX1Vz`<@fV~8gVE5VDGHCclJp7B6U}0^Yzmb8IZX2m@5#*TpEPOSF zIwugZK2$TdGv&)(W>DuepflkBtT-3)w>0JBOMF6tzmX!k1!LFj%13 zIq(zEXvx=E+sACs3-7ON1FkLS&h36#QaBunBcr(zl%IpWiuG%;p4-jka1%QLG3OBn zsbgGY9!aqGeFgDZc~z?mtkl|ryz#7sIVK2pf__=nVmmPWHsXK|6($M$1XkWCfZgy5 z&}hj(bQBX?^zCkej)@WCgO<0Ji+RX_()9J>mQO4BeE za?T9s4n06QHNXpT9abp`Ta|`mZlmhWx8dGQqoWr0+)xp8-@`){6rE@B=`c_unZ*L+)^* zuZQ&r{afB$XZkZ@dFD*9=!qdyFoOP#UQO4W+>j{H;5>Z?suw>&6~^Lgqs;3rfQiZf zw|Y6`Fw5CuMjvVpDsoP*fjmbjwDE+(#F0WI`y2fIo6!7Uz@q7Y>)NdIRmlZf^)g$l*K0mcXe8*t znyf^-(YKQ^Bu~789TmVTd53TaN~96#9aXOeZNwXwJbbn4HAgHcX?ah>B;j|gGXpA| zA4ITi?Dz6k(nn6KUNI7Q-Z}s2#}1b(t<}qE{-UQ* zD_;-rA*&uBMpsR1VzrlbXz(Rq`6B$jObmhFi*46=_ceQ61Ud&@fcYL{l(&2bHf=RQQV?_o-LZs&7<7+MHL6$`>`k zr?wiRhb`)$j-+W;ZF%Iq{AcG*EH`bX{r}mXm^U&rv7@BVT>%hv!JcW!ti3>+Qy@;! zWWgv+8N34GK-=qQIo~*ab?(1B z#r&$BS=XvE|NlJ25s-xpr(zaR(8FXaycuoGK| zoy1<^Fp(DLip#|VZ<{~jv+Q8rIB5$?~W}7p^^qtta5q$RPFGr5*)wU=l(V6(z6>C z$SP1zHaf}OAYZnTa;(>*f*wb8Ha1;8vDiJi`~0r8cd+IPh=rYRGiG(5R4(}ba}Z)C z2KpJ*!1+@mqGD$->Kv#Lij9k&qoNfW+Mtm}x4@u&o#55*<;75Y=Zi<)+q+y=e8IAr zYs20*rapbI=ue1Ey@p3R!v)&e=5F=v+v%F6j0hgkG3aj|@}(%cc7gr}O%}?b?!d;f zW4Ql8^T~wU2hAr|ylC(E-UT$04vi>s$s75^<tb3nNFVW~htLxzH1dhmu9L6u?aEF%Un$s-_e6`5vg5z zFreMdAt{rYp;98Vnc2^5yb0`*_FZU@j_@NYgG3Z2Zx-=vPq4mR+U_1k<*{%UMy4j)npf|QFCq5DL_%?mk zUhGbS80I2>pMS;QsSV73Q8n~7I6~%=x4l}Xt+?H~V6gDQ2T=q6@qzG_Si!ggK4Lx! z^Tj<5a<;uoDTtvEk$yiFDUMQ_atjrcgR%w^9gc|k;=~C}@~+gD8#GqnL?g=OYA$8b zDaNO$#oL}Gq^`4vrfihez45ft zSkeDpF)eVMBj~R5SH>ta;hT6Zo~8(hsc=tusUZ41qQ4AQSE1;Z6XQ!bb(eaqCbITV z^d~6Xf71|toR8pC-w0|9O{P;7-`-Z#^U{HjDhmmAFvr}xv%a3U4+b<>j2XKccG@UG zj$NKb)~j#XQn%`MN$Xy}*qcW^akMA?kL z;a~7S=9g@pC&DkbZqMJTb9idYdVNZ$S{yvUThN(QBf>~n3|XDNx9a8-&~NgT$Ov-K zoN3JXo}{{za6rWGl~tt(es@f*?8@%H{|5d;oE%8dn(RvU=@T1)UfGMt-$}re-*$Ej z!!o=rNp#1$6nd@^p8`S06aOlRknoAPnxZ|SPUqnPzRG;(cTYCl> z@6zaP-IE{0KSOLW+mTGiW2d*I#4^YDi+sI0pnlOA=0C33s(RpNeyVMeg)0`xqP3(^ zb1YOt!=L^}{sed{DV-ytjZKF5Uc9bA$AY3PQ4Er^)LrT?p^K(LTVEgUQm)zknpbvx z8oj%5t2Q#a(11RD`r4sTA*AccmXG!U-yq~p=cvV2AsfC?v*Ej|D-`|LitXj#vg3Z` zv~oj{l}_qsyqOA|hy%EG8C<4rP%~A7=7=%QdS0U&wfdAz?OeBusHu{e4+smu`wJl8p0*oSDXn$f5eV@`2 zH!5J{M%U*Z=jP9jGPj|qb&J|C0xLgS8sA~H? z^zAG-!sfHL*=OuW)`4ryz2tO#IQ^BR?d2)i+8G6GhM(Id@do!AS`PGlGahv0effOi zHi6dA`}ud@LSJ1=vb&jVdpA}0bZ3!WWvb6a@9Zv_#`WsJ4vwn<%o7*$svlSP^wrRzyUSYGu$to-FI zUHL7z!9Lmy7_$r=@?4P*B19aREq0gAw0w1?`L$A;fcqd-`6AxQ3w-icfza=(PAWK{ zm{jYGAgym*exyfOe?Mcx$bkA`!D|OiU9veK=PL8`!uinnrjS~Dv#FhT+5XC(y8G(E z%+6U^=Ogboe;R^4sM_H*4{3hyeeC3-2(Oi;2Ch( z5pBy+PFiM00{tJ{vyT^6~r2K zyLv?Zny>zR=NlYd0_VSgqf5KVu}N@j5$9OOmd0U53{5SXo3Sgl%!9;6K*>cMwi4S? z?@j(*3`JS`x0k}6>!19{9MIHpU})OTz@{;K1JTCQ5;?dAU%Yg(DJeEG_zZp%e~N=j zJVa?upqP+UqBS{irOlg>E4;%Ijr1@f5_L&1jj1Nqz=0N}*HGkSvL=Qs`r_kfga=9$ zT`19k(l(J8* zvq-(fifAL6TK`>z=BFLGE(qR3TO|71^?MK&_eY06*KrOzIme56oWA`fE$jvgm_OeA zE6a7`odQojfFH$!NPZ!|j^D{=@r@v&BL9WWyX()>ZvT)n9q4corXxU_%Kl2(EH_uO zgaV-o@l@L1`G(-$G@^UQV0k0kh`?&EjS~rVi+E7<-`wE6relh{v-+9c=y?BKj`>ZG z3^bk^ZZ7)JTPo{&s#@vyXZ3g3^zMF4khDX~o~BDGTsMLQU8z(h*~=~E&T?;gxNHcM z&&ehws^j}bt|J@+7;s*`BQKm;R2_rE(Vu2z(heIWn-rB~Z}6hxC{lcVSxhR@g%6 z7dTX6ld;j0aCg^@uKtK}22NmC;eAQ7Ju>(|xUS1|rN^`n{u*v&;Y`R2$7vOJQ*Key zX$*Qg{`MjQ2>_b)S>)lz8iOa#naa$LB7hcWlSf=5<}t|qSb(jmKv@j|Q;s`9L73~ttI--b04WMhny0%ly@7tdx#FKqU{kz~Zc4k- zoA7w(6Z#7`Bco6Tol9S#AJVT5HLtB1?+O1{=fp1dtLc3XWlmzFSP;){WcRQIH>aiDyD&TZ0Sm0#c})g# zoU`r0Z@T}_u6uq3n)MMp;#~MyQe&Qzev*)Rs6r$9)Q;^A4G|;*Glb^Hp5U+Yz$$D% zCws%7uc)sjmD7aO zy3)3BO^&yis1>IjWEFHZl8{Q_Nq?6Q(z7dyaL#T;1!^sdS|D8Nq@nFv9B%T)1Q6 z4grM{8a}YdC=poP1BEe+0SG02JcrxI>W%Jyb0aZ&DYCINmIUyt!d+}KW{&{IEs&4FJ6q@0Ipn&-*D?< z(uRi@Q4uWQO?UZvRq^>vt5)Bx*yaBH)#n_$Xx7__e~f|n&N5bg_O#XFxr${&YA zUTNWFC#9|UdEc#@Q3_PWoiwK@-INQ8wx!P!8{DkE0&gaF#PYmoC;akUr_1L*or|wF zNQu4&4WE`v=9*>HptGhChG(<<$ay=D)KsrIxPXrj0irJ zG9u$VQ~VS?I8l+{o#2S{>PW8sSOGcsRizjnY^?D5*2m7&?*f5%7JR*$0EG>oKc7^u ztB=*8P0TEs9iX1(`=@2692)iZ!ZCVlXYc-)4)p4wLGn_u1K9AecSaC0waU{Por#X! z26XLiO++DPvoY=@d_VQ-xsrN`f8N)-&m+o>06L;E%~M(&F#0ItlRI?ZN*p525rxFz z&tIZY>2oBP^*b`|@XwG!o1|SN!#C3rKVC~(Pky@9Ijmx1r|ACyB2T0kY8lj9z~`C1 zUD%n-_ZCVs&@jz7q%`;AZm~0IqlRhDrn!z@DA~~A18v6~{`|E)gYxBaW7x+QOIZDB z44BWXVW#_TOhKR?MyT&elI6A3o?4)#*pb0dWPcoaq=CTRgL+A+^l@wIoK3hYD zdvRb17b4E!=8N{Ch6;B;wg|4Hr!9|?4gL6np{d`-@H6?v{F~h?0&okMWm{?;tQ7{X z@mDUDL;5Rn=Kd^@0?4knF28H+hTF3REkVnpri#V+GQV@P#^F_pS9X+feG(%HsDt?!E>8NBZbAqX|bs(4p-9oFR>Atnqptbyo zN7meMIaYq*cfJC2jlH6?W@!FB&f#~IQrsMc|7VN1 zFxuT{#Y7EF{f;n`s5T+lth^{F?KK*@n69x@v zHZ-;N6PyCukhN?24c2mHfgg#sNWJP#kI?V};1u~6`Gg#CpmW&d43Fpr6tJctX<Oh5g*wMxb-}ijJf^E`js9Kn5KKzibT=a1N+(;z8sQR^J;$!&N?HBH zq;ch-bM|xvImUJ{N~ORm8JpI054d&j7W>SoovUtM|SFQDa_PiTDihw`Ex=7fQ6SjLQ=-XZYpq=mhK zBiOo!e}V0HZTvOr6VN1N1MzXV8?h8WU1ebB9zcB+PdET zyKCph$HdAj_dtb)`%LPa2B+^j5U-AoB;ll~?yLx~imc_4SO=}_*FC%k;7|6BHc-w~ zcd9=%hMGwM1Y?{)XH))R^z*OLz9K-mM~oOscj5Y4);=cf6@eZRQS-bW(S~=lN;hU! zUa=*ZzRXCbwjjnrZ$9P>P}0mM##EP2Im2uv|6Tp8dl;Uy{q78H^`q@yw6jnWr+d!o zCqtTix9lPc?R-FedNoJGrO$G)v1R9DS;~LlGWK{Pp^g`y5XhhYY^U8CKkn{HYN1Sf z_&gpKFjL(-7b|!T$LJ%#8)tsKP5FhkJ8sVx)(G1Lvqi-#JcIkm3u0>sNJ+`x*etyC z7m*Sti!tI^g!84pPUf4Vw3LN8!In1lT^Z&UN+kV^vWnHTiG8Xb3;?p72_@DAMG* zYW66v|Hs~&M|Vwb|G)dwQVIwJ$~>92%qWC1Pm+R^L54_C5C;N9W;Ki=2!>V*f-LK8}7=yw#}c5?9}`a?&Mkkn!Y$pb>SL~FNke5KB^-;jAkuVi4EY3 zJT9d1k@sWoO*quCxb_tf2YGQ;-{!wbn0i^iy1YSJktj1K_-vu%m{uL%9x8*hO$@O)qWF=Qi2epXAota`3O?eRy}4)4(Pb(aOa%{o}TxpJqA z(qB0+ZW{Ftgl3sEtV+?@Lmw-;T!G0gKUtWqj4X9UAw5r373Q8F@&1YvqgS#S&@?rX z-Jl0Ba^p8Oa`^l3a$fVyHGG`bR6AF7mNv+Q&$V~8a^`w-m-YjqX#da>i!R+D(EO*n zzUyv@k@}q}`dt0~D(o8ieu`+8jXEiM-e`Sp-)$Yd3$(ZKO^M~ZPZWVQ$Jhnx-Jiwo z8;4Oz8yT~EafOk&olNL!QcUYN=Eu$^({y?|yS)pvk#*@5qFKBcw_Eidp$qihUaQGv z);5G5Vb9bzT9=6;wgs>obh>?~&GGzVoz6zUgS<=o95S)AsTjPiEL1vk zomvdyPAGJN0?i^DO)l2B{dle;g-`>dLeUL6jBhTyhhxa-#u4c!I&vCaph+4u5~Ad) zLVfuwiCv(@rsE)G!tItG4>Wtg;!<>fHWZgWS^dGYl&+^d#ZNlvq zY_c7zd~l$2etYFIao5%7x6KEf}!;#kY z-iLb8FIdwMs>GPaX|1p910%)&mJ#&4@qLN4yDt>^{207zd}MrP>@t2Z7}vAN3A2G2 z`N{5#3gdEV`3SUq{N7ycWSIw?zK&zYhAbB1vY~FXXRM)CF%oFsuUCe|rr%j@FIUPP zn{|746>3#D8~?wq64l&ZCooRC4NL_gCDNoyh0% z;Z)MPn9I@v=M$%j9O0hf;kt95e~1Mi3hL_E!(=Eh}E=N5Bp;?Hf z+=+`j)2lg*98^Sfqux=E*WOqu83H z=4p6)NFmljJSkok?~1Q%fX)M_tnN9su0&ZV)cVJ!N<_(*;7Ib%R=e4ze57G{*{#a%F+Ynx+r)0E2EUN<4!yXb7VB*xHH=po>1T? zg0s7H9<>};Fp%-vpP`iNL0uVa-vc7x7@B4}yQ@Dl(h(>Q? zuyLxyrrkdk`Rdp_lsP%7L z-D+edS~pK6w0_A_tYQ==P_$JA1~Tq+S$)tjm^vKQE8DwA#7DKas~Ob$!*qMG{m4^! z`PDl87V)k9qYc#jv!kn%6XOndLXlVU?WD~yeN8&KW}EPco6FyJisC*(?964}u; ziSHsT<0GpyhVtn@b)=(<6k&V)Z85Y{Ju-JvchZgp*BhM`&y4_ zQnwcunwC84N%q-0RoMPy`_l3y<-&E=(Z$m)ERU^roS2HmPsSRNRZq1upqDYw7;EGe z*}K~*a_HDc1_Y0{$_R-la>ra-sY+(W4|7=%DlGfD+Q}>jgMbcRb0(6WsIt|-YG-*! z*hSVe>#VXZs(!OO>OgjpBL^l#oIMitn+1uPdWwr~o|9x*vftuyZxesBcw)tZm(Pe# z7rDD;SabV{=-3N`yGH#wxOddu5ohrAU<2_yt0YB0txm;b&YT&16&(B5KW+k>%n>%K z>t?5^`(yX2S394I2|XPRtNDMN{_plKeTQ%BF3}nZu;byjuhNo(d+JnhahHZWny1IQ zZ1*-c*6r3Qw%*gp-CnL=-*ETbc{aAmzT*Y4%}f90qGRdxfyENWN5_{LKTy0yQOqsU4T*)6W@SL_ZNw}BlWXG4n+|F(hTw>G2*mXlf zPr739PE8R*JjiK&Vep;izYY#1-5p#a2?`+mU5< zLfIMBs!yMu9D*+JjNC@(|8A()IvG`K^?#HThvJrak-&1YO52Y`wrmqARuJoo41ZQ8 zLM>zjw5d*!>1c<&*6vL+)S(}Q(5qcrf|flNOz0(fu7b&*L$A?uS3jHPg<+ME6Il}V zYPpWm>#OShw?h2> z_jj$GxVbRz`p?G8)Iu~+%N~ulcyncFqGetDWySX=ZakpHBX#*Rjdh5LIJcW~HB@8q zPrDwvtTyZ5Sj+Tsc80~kK*fzB)r_3_9hnr8F!3uE7_FUc#vx;M+xow*C^GFre8lEE zYd*?pa(F{RqtabnrkD~F-3JT(#5WVS&5WQi;*(nz@F^}aH{Ak8Tl%Ia7WcfKa;a~_o2j9cZTTB@~%9?7OvtF`e4p**!y5jQ@p%Yi@ zaq%{kuXpnL6b?_}GoNv7(C&B1OH7|T0xd+hCX736U;A-v_5EYI;1Kbji|V)(&(rMdkJkLlDdrX_Sv%g1tWl@E`?QZPF$5r{q`Sv_K z&6ClTWdq0Nxfnm}!tp4$(dpOx{QR81D|dfuvwNk|IgyksZfuz{iFYuc)-vt5#PjY? zxP6@3`Pcl=GZ7H`Yko$Aliwq<0oOG&yi4dA2Vch#Ki}%y|8W;bp(%9}JJ)m(TpTmA zabjop{r#Bi+HRLvFgwcZTsT^&RByGoyl7NkE}Ogh$C}VDH%fPd$wdotAhi1JqSr$a zv+>^|7Zxp0i$O%ulqjfNR)|gkxE?C99REs zQU)GLiREKLOUm94#T6|P^VIsPMb=l1T3@M3OfkOv)464G;MGdkL&a}YEwR38!XxV| zseJ9)`C_Yv4eQN&`sgD$q4ibqU+XI5pD$kSy}BhJavX$UVyH+=gEA8$26hgeXc@UO zE^=*r)W+DT2{R+VsGkExU#t^bu}Ya@fB#;qc8X6??^fqK8@mu;UND>ps|v85W1EK~F8H=dCH$$z>J zlWd!l6d*&1q3ltPD|yOorMLqSXGHLf8?%Xi8M!R0##pK?1ni_78IzP&yVZTX(O&koMw z!6PnEW&}lw0b?x?YJt5G;a7nTz&tY%(BwYYy~86?4T)j7hDZ~onG$>~ZIn!j4O6M3 zfB9#hCU8S`G-IbRVMPU!X!Yp}Te8;qRKw0w4h{kyN5JY7T!v!e3 zr!CVAZI54p>OR&eXOtz8Hzl}M-r=Um@J)`jcO!6%zb!5lDIypS ziyqyjw$xJUCcz8Rs}hS%V5tc}u?b8X!C+P3jg|JwCuPd?0Lt`W!^|NH0W5(CmZox4 zxvVhnHTaRh42cTc)$dhXy`g$gD(J4gq$wJ6ff1?_x6Qsug0{`Tw#^wjY1Bwg3BE!t z5K3eizV!x}ah18PDV6#`Rt$@!u4L7>z|V?d214*0gyrnoc1ydP9kxLx8W8+y-?up@ z&S{E+&VJ4a2i|n%IJ&dh+3TEiuHq~RUsN?*-z_-Pg+e2;O9AG8x`oT4$2gW~;60vz zUQaB?l4S%!cm5?_;Zyk!_%-}j{6QYh@yzAm;mW{!j(;Jrv^7ARv&f4H;*%nU3QZD$ z#s2LPkBfQYZLzonEFYt{#Po_wBnVQ;h!_cN<({%Ek3s1e>jdGjd_i{P&_j^{_}(jq z>VaRC`wG(*B&q$>5h}c?viv@e7Y`H`M7;Pu+7N9bsuJO2ZKH;d9qqFArxvYO(cv*Y z=uuv;0}Et9^QgfRE}*;dlA#!$-0PqLgm-j}vSv-Qx!J|+Z^9^Zs;QY7<`?EZ^R#)* z1ZEXwPEnda!+X{;%dqxX$E`ezG+4mIhlO|uo47kb+#NQMVe=Shi{nJu@dnLV4urGo zy1DRz`>LzD^W0VL7I(jU#)V(q`!2`DaZNdvR|;=(b2x?$V;N;YdATeumr1GNV}2uV z@<;j0{GWWZP(^^pgeL?^7$l4n(uEI&^#W`cz88oQ=Jo&J5k!d*_LX>0gmdEWB1KY! zL1~$=gc+iM90fdv1w1J~D--7!hzM%PzDor>(6MJ6hHzM7eHFaid6qt!rNUwLg6gOt zt(;a{YpHe9F#PIOP1Ts&X}@+x1J5PgR8P|T=_7P_Q=g-=2-}nTRsAkY7ZZ#Qh8L*} zL_nlS<;%vOMzmSQgvU&8%aCqb zAJ~c8z%Ydg&XW#f6aqmC4Trf*2oeV#C9ZHH;x2K4>F9IZTQ1vx0*yiZT;wbc4s(?I z9^%XKwfUBOHy*-sB5;uRD}SFSVG-$y`UxX2!AW4Kj=jQ3fn4MNVIF~x#f_pVdQsa| zBw(o!3@`Yhv|fVk()SYiDw+1PwG1ThVELS+{X8hcIhie<*y6mu0_X@)G{ujZg@2S% zDp5zhFiarAD*;}Qt9j~ewYUaMR!r!k2}qA!qJbwXCWY@q&xfp2w&6m3t)8V*dba)m z8fZ|+1H52(3vo6SgI^7riV+zj$t08(5KD{94u#Mc^Da)PP;ewz9jrdq5No0}(*hQt zbkw?R{b@zpRcv4k3>Ljk$?HIAtG3M$7#SEmEzZ)>T`p;KdZNTA} zET7UxDOtc$vgTQx=~~6fn+iYA4zK>=8D+Y0t5PS<```5o3)5g(jHJQRlMr zrxWc~ae-K8j9o$-=k+cy8@2DEhVJN`^`lS^a^Q&sYw}DB4lL}?TP4HQQ-*PgGjf5BES7lY6C$Ewpf*uGZ5~nm(k`&5|2D0wx%4UTWe^-^e3Ou5E+&s2U zfsav{MeCHy>Yr+~Rz*Wk!V{XLF`@Q{+WH{vrh-m;x`%)~3ZV}Z_0=>;)YspDQN~n5 zGcpWP&!K6{02ZU+r)a=?<}%YT{p@F`X0hyNf_xI=6N0{aVtj%ZhFgf4wX#&?3CMy`>0@+L-n7qP#Htf#4> z&!)R3{zpVOu-Mu?(s3zIx-Au#p_<%K7Ey~b7$?#*YNTpsmtVVYrxu z3ME2??af-M-Bfr%eN|P}dFm?l0ktd`p+YXv!WcXzXCgJzT@5^~iN{m`5)!dU#y|CF zqly8K8BZ9JG05=ZQeeCByo5sp{?7~ zmEAG!+wMY_=q^ASI9hy_<7#s)xo#YI%r^=-+0UKf;8*TG$MJD|Q$C6B$B*FQO@0oq z^PBm-{7L>QdWYZxfv#1%6^7>$reguHeQA zn6lg7IDv;S^EOUEE2rSb31+BE)CcgW!i^JnsUP0P349GV!<7N8oPrxCpp}zHwQp)9 z89*zi;Km93h+dY^3$$_yZk!;9g`$lUFcq!8ae~62j=;tVXyp{#I03DkMmbY{FCi>- zK6iFIaLl>l(2lvP`?yQ{Wpvt)cc;571mTE#$ptSRl|m3G1L2__){EQ?h_7GaiIoT* zGKG<8W4#zu%0glo9`IvOtBZ}qL=lq3m&Mn`cg2rHCbR}hZ}U>`NxlFq0fyKp-$@sx ze9Y63$sE^8eo7{s(=-|8%bq#zH@QGAqd>gUOzEsVr;JplD07t+3a~KBpOwFrk}7e# z5$nSuGiIqvRkAXJ?`3{mBRCzTXydgYLmr4B&ukzh1sknHn!Z3M>GUC;MdkvfX0ZoJq)w6-XSH0~Btf=xLi$O%BQY{zq6|KxogvyEB5o+Uiju4T z55}~71tQe)Dw)v@H=Z_tvMGGm#U%r78b#1`QP1@9P73+z#PvO7o;RZFk(i4?kbiJ(rIjn$n-PND-u6eQ-BN2i8dhk~>T zgw)O@3KEQU{UGg&ZoUfB#n{@Yn#Fp#y7?(<7b0lEDxQkEKHHXSb(L(7PG2a zk6Z1nr!DYOVm-PV+_Z`yUX22X2^%>YRl)WG`xASceaJpdfj~BQBAHWbS1y2pxx9j-cbd z_6)}I@9>NGb^O=-cl<>@pGT8ld7+NroBYsux?0#O91zY5zX=6G84=>eW@2aYIdP;o zMVu?H5Fu0iMm#0{EdDK)lt?cQzUq=hm%Al6CS8&Kl8VVy<;Ugr^3yV;$m8Yd@?x2B zkuS->+z9m)k3oT96AP42lx@lb8nOy8YAv;e+EsmCWxjb}zWE>3fToO?^~1Hv+QWok zW|S|XSJx>a7+6BEmv8=q4!JrBB|T*5Km*1a?-+{^t>+;_A;K(gdc;P;ngDT4wwjd0 zNhbDX{ zzArzVpUltZm-Cx=$mUP*Kk;|?5<+#Mk&q}rvfz`lNyQB$<1Q*z7QN7Dpv-%gddbwa z5FrJfC(|UDFRhk5j4Wxkfe8tplPMjVG~2*L+ds=*Iy7`to>7J>WYJuzQ1Cb$Q#^mk z<7#{LX%$k`@v6^@y`;iTwTQ;Tcqz?tv<7L~0__uRn|4S$uU*$bhZwz<-a_xHdvs3l z`F8gZhY)K(6Qh&S*FcuGG22*fY%(C*ApF4{ql8)AY-A>yz!KBmH9s;xGk2Lkn2>A! zVHUM~?JE$#n!ydev(Rd8L4;l2u4A{dpR!-HUqh|}%(qwDTWv}~`^_$}%Qz74c<7`l z&Rl1O1DR+k_RvX>x{Y1v=sx2Pb>DCqfMd4{$6Qa#_c+&{dzu5^x=Rr!mpBM2_DQf0 z9zOUGf1bb2g8(r?ErFuJpBG*c-V)vyV5RV-;75bUia>yZzT$9^h0bphfmw_wTdKO$ zNJ^A|!Gehu%v|H(Mfxxj|3DeW%J0aFWR~W0QO=hkLZJ{TilBH=p?qAJulONS1xgte z;?-s~0>IW}d}}QHmJ&nt9?@T@v7?P(-XK))SdQcC-j-;sWs#ahvEx)Ip3?OKKr?m7bSg zk=~NtmmrvhOi{?tL=NUDZjvEeJ|PnifZ+fV6-ZWmIO;Ct2L*DKKa`?sWwn9YPVJ=* zRAH=2SvZWJc2Uh&fnj%BX&yff2%zTi(+adQI>hVE^v*hSR+GH~GWBotQ~J;P-+D>o zQKPW|4;X<484<~c2*(UEA{H|}YB;2rTsNnYkP zq)3FlVR$IQk-<%=h+I*wC%2J%$OQg{Gpx`RNvWO{)_!Z?X<$VQKDqkw!DnBZ} zC@ei4ny8)BzN&9R1qLUjXoBh*#c4pY_OkZ6#(2sk?gsMz5h1UE-cIkO57dFY&5QJP z`q%n*`b9lo2hVZ(l<}hRnla4)miNXY2nvicCd8Y~%+BU>=17yMAS+DpsURh-N3F&d zbhOBY<)>r-#bo?t6|<|_EVLTP9z*V!4fYP301Utg4E2z}(8C$vjCRoVM1CuVvAynq z3l!wWa@<~Vi8li*n({~Y7nd=`z>lV!%`N9PagfcO;C|xna3%Qad?P-Qhh+X`J{U#~ zx%?k|QK7QXK)`4=VW0qGg?9u`<$qDg7r@8UGCFO+^n|5LmqJ290tcz7sp%rq`y&|l zAF-6g0!^NkhDk6<3STioaXEa&2utMf6(dl_RdB@!fs8A)w%SsKZff|75zeULD@O2x zB$;ap$Tn3&7xWG~TQR~+J$%IoRgCZzBdj;VSB&82NwXCr95lmMjL_c-UonCQnDthS zFv$*IF%}fRe)#ZVSi5$u3yT*o29zPWuyyNJxOnj*{Ygf6YNgMn>@mvM*TZ ztaY*+U-ku_!I;Uu^gFjtoH!Ae`_V@qfod2AT)1#ynS05T?3OEX=+GetR;*aDq{+5z z+wzlgW3YdVk6N{A70meX!w-ii z0wgt|3~LX5TyUo1@#Du~-MV$9Q)4!6+_;Q;MCi|r;=o^KvdJ3w%S^V*1U6dpCu=}( zBDTzAyG-zxnQWH{{xXwI*1#8YGc7kHC{HR(%+0ji;ETE0WDR^VH=C?MPT^?HpR9o| z=B6M3UVsF_qZP8r8u(&vHd%u>gGOuqWbKldQ2ytJW5!AgfggYTam=9u z2M%moVE$zNacIesC1Vb4F}G}i7A;!*aipqPwJM+*C(9InRM)Rx56BPv!zy_3hi1*1 z!IxitIr<6v%@diMUp)HGJMZ9PeXZTvI&2e5eveHod1&dRTi(!+PPl?d8+Ps51)VzC zogfqn?f4}+IuzYA_j*}83=1Epon7$9MQmCGJ`0{ri-18HXk5gmMc|K%*t7^(&;X&{ zZt^rO0z$p9aSVaih*GDY+?z`{q^et1S%;-VdRsHwmkqZ|sTGTwP;7;#GjT*tL zufFQS#EBE(si&U0GiPf|Y709LX3Usze*LV9^QKIhlAaqMe?R_Ca*-lMVCBlzD@W+# zR^U4;U47auoubhx+5tJHP4IF*6uXJt%goSg||FDH%hD4h8qk zH{S%57sKuH<;&kmu2G`~M1TA3w@gno%IIK$r||Oxe&8wmJb@puaMty5n4r#E&2QSv_qiH7cVK-CZ&IdTLRj9ai^U!6O>-+1GV1Y`GJnIvO> zK3^hXO=@&B9}U~LZ~qge`mJA!e&UHI)=Y0SX#VClN++{=%Ao0+V`5^~q*YC=+PffS z1l=X=+qXZmCaq=5mcMsQ88T~Djah5b@WiZC@K~W%Q$|Yf=|44lRCF{a9_N z&`m*FB?!MM_9(56E9t|0rMJR^GP{1D)&DyB?QZvSi7)WIT`%N_FTE zNq2h+vM~Ay;ca1N{MO!h3Y-}`Ew1-pakFraOD~LH;tq@07L_eqHZFN?>VaSAJXZF^ zB}XI-7*JzCT=MAAqZ^8Cwf;@=ZzjE#@VvO7DK;o@6;H5q^@GOq=g)WO4yoT{;lhPG z=AkSK`t<1&m#mCalpHa-)2E+)8kal~Z^A9lzeD$^0UW<~tbba#4CrigAPoF+L zNg9^eAnr&)^ybZ*he#htwMDY46q<~Jc9l!yS2-+Z$e%ugxA)vCX?Pc}m#t?~QWM%H zBveV8J$rV2sjUPgs3bNR@c~HT48FvfDV)KVI5UMa_!4KPa0XxE%oNT*XE2jEx7B;< zvJSq)nJJv1Fc-a0;>;AzFwY40{ev%YW(wyAsa7n`kQC1Op2V3NPz&%bM;YvQv9UE` z_uL#ga%4s}O-!MpQcv-w6EvKF;BLoJ zmI;UJt!TSq#f0Q`?b?wD5J&|`OaV`p3roasSuW6L6qMycmJ}|_1qwn7%5ve1{Hq+4 z<-!OhT$T%Wm2g=uFwBWB%Y`ahxGWdeYkmkN$#V0FpF_FTK<#TnJlQDLE&Qdzbz!_7 zgYn2>aI8Jnfbg+)gbCqe?fK?58f)+Vpmy!r3GpMwjTmu|-@XaEhKy|bZ70OfikmcP z(zZSGzux>*99|O%@k=9@E_5j)p}c)XHA_R>{C zLOdQo>Gs+mmPamMo)n)D_t)l6>>rLlg(pK?)v8s$xBofcr%z6wg!t)k*S93ZVfS$U zuHEvt{rmSP#Mi17s@2?~m_V`vT(#02(426S-e_jhTUdbYb3**pHf`E0bobuFgRFEy zJa*w#oV_l2_JGMqeHAG%8L6)#E&PB+@V<%^n2gj{kph#E`kDq{GE!ef3QR`oYZ@T< z@}h?qtdYVs4ZviizNP`F*C1M*r)d~XFRvxvUcZ4S@=WF42QUA<1^ZL@;DgWyIqoQh z94qW21VQbf23b4ce}(KLgrGQl)xC8K-O80K19sDZcH~58-n=PN@SW5)nn$oe;}y_PjqH}wAcR}0pzy}!2pP3$7@ zwVm_z7Ja)uNdM=3Y(B5ozlrVW-9>od%&mX3Y15`?mb|wsXOD3-$UH>L_l^I6C{uS6D0llDZWPWS>@oA49J?h_F^!B1fH&*_g+TN&V z9=lsUvV8f5CK*0m{d?WkVT(D#Wd1T{FPrB1%jO)Zm{b3TbW4)vSlcZ+BTLu6iH4F2 z=C2kFCcw8NFgF5hw)fg6?W^`(n;|TK7#7Tqz}yJn+Yy)>0Vqn9*%6o<0em|Gb0a`1 zN6ca$Sq#Lc52ES8w<9n&0zQ^KI|6efz#hS~BQQ6@Haz#*HQIysaeDTLdq4bekoaD+ zv#IHOva&*1Gh1A=c8j#$ph+TlqeO3#2t=Cqk_~8*IL#X+vPoi|1K8%LXXEMQ0-g!f zQ50O8h4&4hzS;tO)7;f=J$L+gjpOUL;+*7r^OoFP8GYF7fLHaTk=S{rXGdcbF$tya zy%l5N@_D!MHc8K}UcEZFW5$dDny>7~n_;7}UFm(OPMu|S(zEg5bYti*gKDC>mvvyb$?_qw`b;)V?ypm^~P#nZEM2Mx7;P;=G1Guh{VN=Vd>yC#mnL zgLL#qy|p@W_3HHOxr2u4KZxmj()K|1n9|x6oj}Tz2;3gi5RGuP01%@ws1|_HCZ(|l z)B<3Is|DbFYo!%b3jhHbAMzMcEdZPBaJ2v=I^k*o_`wNR3xFS*^tJn)d(oXnSF5iU zSl4#lx@Q+1J$m#d?qd;iCEn)9AV6p`B9kGr+w&qbD>4w%n0b+z6&ZXl@~T>yq11WR zC(m118?S?@5y|ti)mB%8>$MBgckbM|PjiGz4aL1$YjLnRrVYMMOQ+7qvCSA!7rV7T z6}KN-%I}j)4?5bvVZ%KQi?{h)e5UR7)YN(P>tCpUvJrMlsq_2w%js8Kucr5xMoIAD zhs!=p#q^`ZSEY}8Y%(`(0&I#?=f86Kl~+y*c$xRYr|*%}`E~2o-Pw6VRJ(Seb{8aG zKEp9@>^rdvy^(KXV@WAsgI|6tG&gk~UKYkGh?wa9FI+$sB4{i3&zEs6#5AFV^1`HTbdTI(DqW$d;xP!`@Hc(a$p~^f`8H77y z4?A$dah#CrBN%tH5$VT&RGvb*ubXG4(J`%czDOkg3Ecekz`bU6=$}(T%BL~vx%G4B^dKi(0vBdt=t{_-8#eKm`g7W~kFj0u&EAddDC)~m? zVGRE^-(OtIUw^3$_O??~@aw(zlBhSM3#n<-P}8X?Z-xHmSBNB}DJnr_se#l^^2t2l zOWT;T4SZ=EQ?>zd-QzPg-Pj=dU;#z~&5El$^44+{F+vmTq=hS)Og%?sIM0^_JKdbXN-QReuj98`&jnK1f?$T9! zn@nn7RLp~ew+RV>+t?sa6XUFtF8P2 z-dhXC3lP2*%oHGeE!a^6LWufn!DAwXuLV;i2ww}{lpuU9m?lH`S};a|T1pGWUkk2O zAbc&@L_Ob0?KJ^^&=-C>b}V#^VE=o#Rcan*sAp6NUl;vPIMSBS=+dQ2s5I&Brn^@h zz;WTSo7m`2+vpzGD;S@;aYlEe|Av8W2M%0z6E|Z0jTy$a1mja<%P08gIP=r-amSA@ zG}f-e!Nnx|di0L$?CfPXvE$j+p=g1-;1*s5GmF+1YuBbJ=!9b*-MDw;#R=HO18t8LzeGQxW%A>2qbKr2d^Y#lHLSic#xqoft( zG`6Emw3F=>X5W(owhtIEvuLeawf1FCF{ezS(dV^AOz<9MAbC<@Y!UHz`-+p&>8wzDfC09(M8;pTqkjOrQbL7@Q9+ z6c`y9E(k1Z_~N&66kMsB%t6{PgCi*Y)wZ$Xjy^hfx;bj%BkN`EFw3vcx$Z zal>=NihQ^EKh2xZ>4?u1D7w99(Su*(^C9)viM=OIgtT#5`rOYq^GH;g(-F_3bnU}; zE^WVbX<7EHS+h!=S~PCaq8xKhB3@i*mNm32iLzU}=nK_RdX@)4*r$6Cgi9}I3C5EK zLJ(%-UPl9bzRu|wv+?VB-6Fen+qwKFZHGbnw3`M5dq8RdA*=_)77)S}qbn^4_JH9` zZtMZ+41#dQC@v?$6{EQX=?*GJ$GQ-%7>(e-?*U)qrg8H*2v>~8^Y@zZ9jlzfqwLW~ zYdkuqBkn(6l~ieq0Uz>bjG%qCFn~5_p9S*I2JN$>$v-}Zl`GR@uxq%c|I_t0?qJemX!Wb&IFH_n$HQ+fz~#3$2MujW_7 z4?q0SO+6=XR)N6aSJk_!2TTEvnBoCbz$2!3z!V_TEyZbhz!dO^DIPEdJ}}l8Ul|7t z510ZTF~tL>fJaR6fGOY+yFFkEc*GPBm;!_C35CQI512B|?+a7Mrk5=|Wy&v=x2zT7QavbJFQN_p(lr{-?B zwP8aBf2%s4F)$H#!&7s2@7|rKT)$Nw*L+iR@#eU61F5CG>!fs;nu9;$9leEHNGN;n zy-9U4w`XRS8jB6aq(-@BZZ1A6i%-oxxBc9?NjR`PIyJZaxbo!}a?azp$(WiOjYrn+ z0zJKHU<8B3&3qT}BtJ^L%hSLJ|JO!Im82m;TWO~7WRHu@VScEiG`ssLVYWnCpIiz4 zkc!Hb+0st#B@dLx$`G!;i%=k3eK%i$aP?ih3gPOzOclb_cO5kdSKl4ezz;zu^<9b% zM8~7v3 z$Rr)p688f>0crUM`TyDF%Cz8eWyFRhwwafC`m}wTe%F&CBsBM*;jV7N3!>XkKbhxSSsnM`rm0(Q!-hExrvO-xti^hnElF>*C%J>)dYAA62MO zqe8b_ynN1Bgpvc}0lBKBz0dsEzGglkSN&;6JI`8=IFqc4f&)0fdSdI*qoJd{9eOFz zgPlZ47_=FDa^q4z2%{nv6$Ceo#G-;AjEY!P5QI_Df)Ro+Dq>MV5Jp8TDhR@;h(!g8 zSO}vP2}VUMDhR@;DCG=-Fe+kEo#*9-&*MlhDYtz2Q27z32F#i7G?uqIZ=gj0cF0HM zOR{effF8;Kg=Zx6fx7Vq0TGJGQbZ1x>X%BfVztpuoHfN#FJ|4r+;G&ShjwRP9j zPhRVdZ@wX_ctXV%5wP1hspemPW9U&7F;2weA6&dq0GkVNapMFNCQN|a*j=W6^7!MA z!;HOq_hzZxwVi6T1}@6P0NX@Raq$iP`}aS1tRN|ebQRbU-5I2H`5`F>n@iv>b6kdY zT+5k-y?^PXTs*#z68O&6JxMv2rl;nrkAIMTG za^h2SXJ%*L%}zS@?NQPyT^V=fN={mXdAOTN%Dp#hOzs@qbV0?6_bVpl;^Y#xZM(Z| z$)aBKmMvQb)!J68mXwPcBaG(Np{!BUV6v*mj4Z9L0U3s)kz=vG&J2s&Ue!M}dTzz; zC@GhE)Fq3?n!9zfJbi5fDV_4o2&=qR$7*FgWxkEiJ02DNc4z5aEyk};V-DQZbj3zVwnDQfBZfbggD6>(ZnQJd0p zpNKnloNjk$@Yb09c&&6xJ~n3kgtBGbvb3zl_e##?LDIy}zL(B-$8F>2ED7g113sCD zJMKyGmolY9Ia$6ZO_EWA);20?=SnLW# zft&|d@rG-jwtfPhFxS`2$CXLySX`TOq|`Yhj~n<&hxHTgOdm5B|AdVapjQm5Z-%68W7y3&@u(Wd(WCCFj}A2 zdwyX8qxE^c=abgMY<3UU2aML|^`3)m2=6^_+2GA2y^-X9s5Yy|{r!1re0+S8@TN9L z16_-ADI=Ig1pn?L1i36%lWWcqd6U4K5F~HXwEL15W%cP497|sx5s&MynH^Dq7ut_!GZ;;?phxDiT(P)v(G+@)9~t7ak97>|BM%m3pk8|apT6JAz=P|I(~MKsl$}s z`FuqEL4({uBq+m|2EP)c*^x|GONRY8$HAxJpfm0HH51o+!Y^@mKDZ6^pP@zF9et= zeJouQ{t>DmXL6bJq&WIn@gM04`N^m0LDn%EcfsB+eT@u6oeM(ez?Wn&MF!APB?z5E zZBO{99Eds>gw6p`=YpehAnIIjR1QR)3y#WxsB^(lIj|Hqe^d@coeM(eMn8~b&?TPJ zIT}SYH7thUO8>v%z4mFpK)Bx^?H7i*liVQf7jC=7xghNq2=^PL{X!+4jh{W*FRbOW z_#o{U2=^PL{eqXPz=?4p(SGqmWvS*K?H4GlBS`xN!uIaL;eLa(Ux;?9I6>MkeCT+&KBe!)9*yfX*9L&rOF{v$pQhVhg5Ang|j_Zy`B0^xqWY^g%|6ybh@@+n~QDWCQW zg!>KBeqq1lg-B5la*_=FE3m>ZM)gbK`>T0dE zAng|j_Zy`B0^xpxv|k|HZ;wdfpEXUyjURIZ;KBet~emLE0~PiDRbAXum+X-yrQ5SmL}-`-QrE zYd%Q(1$r3;X}{1#@WXeA_6w&4I)#1OFA(lGNc#oC{RU~jFhg1*1!=!PxZfb{7g+Fv zPx}Qw_<kY4Hb_Im{^&5x@HW2RD8(z`u3RwJ- z*FY?EAl&v*+Xa>@=hJ?HaKAy?FZAOcWG`@=xxL&;4z6-{xghNqCh{}+Ang|j_Zy`B z0^xpxv|sSzKD-AOcrPsPfdyS8+IdfvyayJXmaa)b+Ak39H%R-1+j4OwNc)8u$`U0= z`-Mt4Uk}oLVXc~_25G-QxZfb{7f8Myr2PWneuK1MAl&aGMh(NG{lY|JrV*t50^xpx zv|k|H?{<>~kw;n;EU0UFnWz+tw8jF${RU~j(8cz0wleH5?0q&6?l(yLg<%e5xB0YR zAlz?|_6sxIC2o-R3x$EFoKO1&mV58het~emLE10u=SeK*(|&<)zd_nB5bpO8v4$v! z9mGE35D_MdGsPh77ow#qQjqowg!>KBexa`1S`N~F|6kmAfv<&SQdl6|Z&0HEr0?_0 z0OSP#!u@(?0P+Gr&qA!r65F8~bVCUKq_fV=>3n=8(HW&rX6 zzzp8=V6jCS5boDA1JEK3yo^zAkp_hO^~?a|1t`>*1Zls}PZ}Y4W&rX60O5Xvv|sSU zL>cWD2=^PL{lbUJdQ?aGv|k|HZ;X;)|y%7VbiDm0^xpxv|k|HZ;KBe!`+{;Opy{ybdU-JxKe7)BH6)Nc#nrB)a9J@B?l&ka2EzRYWyRp7CwhWTAlz?IRt$vu z4a$mv#d4CYI8`UwFA(ncoc_D+>NGcMZUEtagS1~D+;5Qf3oJp*r~Sfhv$z$c{Q}{B zgS1~D+;5Qfi>9?KJ4pLQ(^@wtNc#oC{RU~j(9a#=25G-QxZfb{7YO(JF}IO3xuZCX z`;&ucz6u|t{o=ZEJ^x=@R{~pC`m|p-ErwfhVVD$d#RbCs2CcY2xZj`^7bw^;XvGD> z{RUGqfpEV;D=zFuaYayD0fhUd`G!aP1;YIXt+*KI6>h}^!u z2=^Pb;zAcI+=>gQt#B(Y5bif<#RbCs25G$H<_5W@#`+9!D++^?_G9wPk9p1W%V(~kaEvgiJte<)?unrd_P-}wj2djEI+ zp?#pO(f*x({BJt{2t@!yU`1jT!HU8viWQAj468U+39Lu3N@A75DviZqmBA{D6@yg{ zt2|Z(tcqBbuqtC!!K#W?4XZj<4Xj78c&u2gIIMWAnpm~4YGc*Gs*6<*t3Fl(tjDk( z$7+bx2ur|fjFo`Z1gj}lGpy!VEwEZ*wZdwR)ds6ARy(XGu-apZSczC2usUKriPZ@! z39BWWkG6>p86cSkGgvgP&SZ`oW!kUcrCe{?JsaS7eO~bnHy6(U8FUQB8{5${pcmBl%)2{xVfBiqdc>H(% z_3!-4x^HndvzPum|N3|S<-F>s&OC?GuKt(Izjg=aUyq(R;hrE-Jeua*j|$zk7cShm zaD%TaG>k_T1gL~9Luy%4Jc;xh3WHG^DBrz$^i%r#FYw|nz5N$>ahKly3uplr+<(Dk@lP?h|AKK6 z+B*XKFYw|nz5N$_AhWnjPk01g+@+Ux2~5)F3y;8yyYxJ|;Kf~f!XxnFE*$n z-vSTQwyD6wwB=p@#Q`FAGr%R|TS6 z_Jp(loIRWMH8Q`T^gpFbU&tk^+HiOHa45unna@2(Ah8R%^-RY8%Gxz!`-~Zz7a>mN z`^+iZr%c&1AEj>>a*K$CFt3#rthyG^5_OP8aS}`f0U_JVJZ2&Ym}jrDx7fZ20{qNl zCV~Jz^O%Vspo81T9pd^T2=FtHnFs>>%pVqc3^%w)bZPh^2=FtHnFs>P3SQ zqOr_lCV~Jz^O%Vsz|TBpA_(v^kC_MpauDtiCHo=>@H3BDkfDB|vRHGbbAklzN$pvU>73S^#_W69 zdouQrWO)1btnC|TWe-9*Uq<#=6Ul|>WY{?CxXIXD8QCq(mMzH|w{iNm?c26(T!fyK z^w)B4<>p>X%h-dsH;6`SQ(3*xptiWL4#V}y`X{d^`~n|H04%@22ND3wFYti`!14=xAOU>l>~exY0$}+CetZECkst^pfEPLD zM)S;Q!14?H_yS=01%7-1loZHz?Z+3uQi1Xd{P==yL?i2kj4`swmjg6IR<&_@I{x7Vzhm4ddkyuQ8K_Ue_Df{3gx@_{k(vo#Nq4~&uTBl6)heV6`& z?j!P{ozcq}X!wYH_|CX!v$fs>T{WO$< zE}=nfPNBD%`&(Yjc@Z`-Jk;V_@Ll=mc@|-_l7}z(Z}}g2FT$pYFs+l&SD*-+#qwLV zmnXE?j)<%jbfgVxf6={okt|6NbvY_(W0SXpD|Jx=d?b{DV(gswT?r*iE-M*IK~q?c zz_=}V>oeA!_dndM^IMFi#2{vbLe%JQ9?|MccaO#X(spLfTq4$hHjrCm@H9;6GTciyd zWCw7~A~$frNc}#jAA0aa>i0qYz)1Z*s2>=q-v{->J)yK1EBc^*m@O_BH;F!|9~i0M z2lWFZ_4}ZH@VtVaRS>?DiPZ0d`hk)9eNaFArVy#$2lc}gb*{QX^+EkmQhQWutofjR zV5EK@)DMsA%q!?w1%Z+J8K}S3+UZA+tUroQhB!m|tWTdBebyhtBX6fG8PsCl*6K z_D9h5aN5UCcpP~6#lB|~2;Sqs zg9n25IPg%yt?o8*6J3u34;~2K$AJeA1n+U+^BD-f`b0vTsOU@p z#Kl!nuXmY(q?idSu~C98Ru>gzJO|S7bfLoqysQ@Q9s)0`#k+^51y7f>?=90pcxt(F z6INDt5&TrheG(0WTAm^L7y9{q`r-Gn!^zk{%%%w|(fM>xkN#}sywVdgunWG1e4!Zgg9XTi?42xhut4x+c~P0XH8b{AhtGlr4})kC25a(a5lxn$iSQ1~4{h z*ncBR;u1OE#*XOQ`mI6e*mr?O6nF;~EKEU83b~XDo^3&s1vFP$1X6ld{Hoc73w9w$ zX<^Fz`JwqW)UU)zY9%#K6r`Ri@X`<|I^Y}mud_fD_&{MX$)0ZnNI2oYr!rIse@`W7 z;J>GqX@<5(gX3DB7W9q4V10rf^o_tRJ<16BM&NA&u`vPP2$VBxn?c_QtTMNlLEi{8 zwUVr$Zv^&QC#|4w1p3%R@LKVGBbP4QWbLiu)VzWYKnJi*?G}T?DUK#?ald>bzU&+l zVYuTZyfI`O_z7?9g#_zd#%%LmNSBC)I$XpTQd4|kT<;cxpp!90asG3!TTHjI#67xv z`TpfGC5U^JlypC-TMTiJa&tqu6{K<87>ScEaCP}439Ush@h<1T!y)KKATt86hq(U^ zhoBpQ%m@&4Baj&Zf^GydBS6rNK<{t}x)I2X0PG?D@Exwe3(BjCsxUVKnGqo9Mj$f+ z1lCG#9-#&qVq z@AY5zbM;yGe_hwJ@~$s*E!O(Yx%r;Q_wyNbrYC#R9L+w);*sSks|#D*dfl4HmPzE~ z|0a=}=G~C*%N1tq9=CgU^p5E5hKTBw?Gfv{Txs7vp#2EV+&Fbh ziTQ(8Q@^@jv6B!7r;Kt}5`$ zs)(x!cG%z9uB?i7+^xT%zpJBPjP8Z~yyXJyEitq$2cMx1!5WX zOGbfMM*WgeAha_trE97Iozm^ofKKUN(Sc6sF6vN#mQgRI`@n#y28|5`Vj1;Py7?wJ z%qR~T1;jGyrF0uDpi{c%Z6KCWFQxmz20EpClL0!V`<($|8TC@S$t)1dsF%_`(kKoe zMFz&;wYoe9#Jk+cSC#pfo(g)%f-taK9MU}o#%$ld9sd)d9s>!(exPvi3n94+#xVn9 zs#jO5lLwMy!FUO43i`kp}oM_H9 zy*v)?n2%U>EH95c=yz78rDdn}h`@_^_1LIP#PRfE7qKg9)~>yxc5D|Uajjr8YsYtpkB{wwZ(d}SAC9wT z?E>~Wt||()$h{d{-h+#K0Af({3)FxZ)ZB|Rp&mmgp^xBVj|ue{{Mci1Zw6ve^9$6# ze{m-FW*`PN_u@?M%}_C3&Aa9NpaL^243Izeyqk@oJ7yMKZ0tJEkTno<4b%~lB zzTs#!IdtY}H97pq`>xE$Z-uu7T1^f&3GloUv{zakrrF};J+x5Qw}gPIpuVf-PSg! z@)nt(`JC2vB=CCM`o+PG6>~$x-tk4e;j{T2BCpL zR|YX_q$`8a)ubzf;79V4${_fW{DjC4w=KFd2!13#A@V~FhOP{PAIVQDgWyN<6Cytx zX6ecx^yB=M!OZ%_$P1b{vsSHINOEA=i8BekCm2K3!~$p0fR8DomNI3^i!Zop+Fo=Lr+W=l*uf)_$ zbSW@5`X3O%F?OF6e-ZD9&r7`}cpG0JKarM5gw^_kbV-7nQlMO2ZYZ~vd&+Ohqh**T zC&^#Q1eJSU{#`DS;c+EGc~0r3yrz)D@InRX!|)R-(1+p8D$s}Fe`ALJH2-1v+gl!O z$41aE0)n80jWan2Y=XR?yu5V#RWXE#6A5Yv9M+JF{W!~jOV)S6`aokpidmqsAG0{1 zu^+W~ps^q8cp%m!5Bt$Z02=#|DFBWA7$5?T{m2)A#(u;}Kx03GWeAmtJI}>_ER})A zel${m#(wNnfX04wSAoWUoK=Cwehk-ukflBBN3jMp_G6X~H1?yG0W|hwodGoVqm2nP z_9N2-8v8N80vh{~Zvl<{h_hji{e`{BcCjD94A9t*r3|Dp&cus5@B(!0WhVC$I1e=TqZl0x6!v4505tZamIyTVW1R@Qkv-;NKiWv(Y#`qL0W|hwfDAPD zBVPuOS?dICKx03GRiLpSOI7fgwNB6mH1=bs1|GB4LDm9|{Wz-wjr|yI0FC`9Hh{){ z%rb$-e$=v{vDLxyupjFz@Y`OA>=k<0Z`dC8Bhv;N`!Rq48vBvY0FC{KV}Ztg1am-R zKbCSpV?P@4(2gfyMHlegk9-wq>_?miH1;D{2O9gaR0kUS(a4!t8)Qg^gZTdITE#k;#HL z_UKGK0*(F1=YYn3#PL95KY|6Iu^&qXps^o~M4+)BJ4K**YuzPq6?m=z54^EQXX^1k zM@<4W_G76DH1?yB1)c-cQGkNy0CjlN;5k4Y-ZXd)P)7j@H1?yI0UG-;iv=3{QHui_ z`>~FL-P|$G&(8-M`;p0m=KysSpg`9i@&%x=A8{hg5x)>OiMr@uKY}Hou^&q%ps^o~ zWT3GhJ7u7;AKew8u^(p@ps^prRq&tT$q^oC?8ht({AYM_ga;b?u}%jX`_aY#8vBuH z0FC_^U;>T($Tz{&YPnV|ps^ppHqh9Qr8dymk46m8*pHnI9Az#rHyE37ty(~1KhCm1 zV?Ty-Fo|=tTCPp#yX2(C@g!G7#ifyRDx*MP=;oYjEFehk-P65cmG>_@Q< zH1=bb0W|ibmI*ZWW1R^!_M?pjH1;FY0vh`du1#js2J<0*(EsB>|27 zSSJCE{b(Ztjs3`!fyRCeP=LmMo}Q7|8KIrC#@h;Fw!aMic~B?MY*orOy=ci z`5k$@JWGaU@&OM%8p2c?%HDh|MTodUa+V@kH-0Gt~jz!`d|Z>XbG zSxr<|tJ~E~70#)@sSi{}3)fm|U9|xkjL<&T7HF!r1(EfqwR{a|>_?mqbM!CtO=v90 z(l6_`^tJ-(ws?D3={u+)H5W3O@CFbx!`m^I8sCbTnOHV2uK8E-nTrf}4}VBRoo zGsJq*YGrk|V4(HB@IYfv^Z8QLZJ59bQNpV@y%HysqHZ?{I;w0OlMT?=)1@M$ihIT5 zqA3=Nj>!gS?CDMk+&X~U1^^m+dR7J+dpcYJ8hcu-0F6DJr2>sTt)&5tJzb{(jXiCn z1C2e+)PcsH4lsbmp5_}sV^8Bu@Wxl1=@p={r%NrMv8Rn}ps}YrZJ@Cq-I=od!;d}f zUY37Q*wgM@S^nWVd&=?;^h%WFA1@na`G-&_IIYjJ{KJnuEz3X3@(;VCE!eJAye$9l zV^5bVKx0oEsb%?xAA4Gsf0X4Pd`Dj32lM0jvi##eIsZ85%Rica|GoWvX{G1OFKvf9 za`|%nku8n|9Xl3^KLLWVCO?7usl4_q8g*goR&y)h;MV?#-MiV{ z#AUaMC#sk+jw_~JH=JBakFZr$B`qNc-mzmxuP*HcM>L(&Q+QJ#72szUft%oG0*QQj^!k;t^kO`^a2L|Ql$tDF#*oSeKp z2DL^DB+#WS>9TZNa)l${jUG6Y2VlyDa*$F(afKrwDekr|7^XWXw#qAy9MQzqAV^s`G6ER;}8ZjxM=6jomuw%Af{p<4z|Oy&;I%BrjiAP zr6`!7ZQI;1ZU(cIDOnMSbrgEM3C_Eoffo)pNHn7l1)K|p}!)z+Snjr+EUVCv-9riFbxVO8@8TMCZ45>=TaNoRuzO4mC!LPsmdOvO!=jb&G<~1EYeE5PQ;$CaT zbw?q}a4v*@fhVsv_q+1)vp91KefvJ>yQzfeuZWp^3a|57ybG2AzgdBRWx#J%AYuh@ z$ucfj23)d?3zh+wEaQS@z^}9-Mk{d1GA>vKT(XP{mI0S6Y892qfU#fSw(I7OJ)V&u^!I#zfQ zb+VwSxs5i%Qq&0_7e`Ph12YyB<|FN-oo4)iBlRTTHRLgTVwxg;l3bXNnQIu=^y=@k2g#G)A3l-U`)f(`s1K-``4n z!P;AE*KRqvpb%>qV3Pqj;#152;DZms)~^l00&&g_F5e^;h+g;5@K_SQmcScGAFh|} zTAj$k*ujPXhRl4lVX`eE*z8a)4z+)4THr|Ql#I4(3umUUiNuejqWvHKia2_?vC%kS zbe3b}G1>$fX3NXvjq(BcM>$XaL$07eZKa9wywY2FTN$f-qAXG1Yh{n}gK|l^sRXLk z)rM+LTeZLOrrJI$IRN`j7UFC64qA?-Q44V@6_NuHPBW&})UmNi0m%VKQyHYz%ly1` zEbcGKfx`lhs3-ndinGCuCoEU5KqhW0Yl@Nsmgk;58*uhvr|PRx@-Od?TMD-%F4lxjSVxK%YuxZn7OA90N>Ne(2}Bcc)-DL{fmPrQR=H|N%Sx>-;Z;{1vSQEUn_bv*27QK7>gf% zw6yfy4I5T$s4*4+Ev@7M*ajzS0~tWiN8nYu^xM0=d-vYAUuR^%&p!0z%%GVw|CFl9 zVKVpONO|(dGMPWdy(si#CZYl+$?GOA$$I+f_@_fpp3rU@SLJeg!6fsLX^uFvTz+m| zOxAPH1w5BNp_BZsQd4q zN3qZ|c%mr@J&CjR1VaE*WJR8%Zk5R-VVKIP(>khxI#_iqnYR~C-8*$^=t*>r_S!r# zXyU|ZWwo|lbF72lX$KwaAS}>TeT#kwe@_lW3c?J|aO^jZ{02555y27uI`SLnXbR?F zlh|(@`3)S$`hKBF>^F}51_t4(7;iaaFk}h_ZdkVE*RI19Te1Dxb*Rj+jH_KIQ!ucC z(U^4R6f<6O+)xbQ=_@M{m^flubwIw^rP+=#(zlEYGp(&ZTJxxkF&@m#JAaz1hu*0>VfAl4S z)Co;Nq)s7P3&-FiZRak+7y;Lu(3H086C<=$0(K%c;fr_9IiXlywz*4kXmaDmjqfK4 z&xk-yGq}?QJrD+nLC?sNR6ac5;0!x6mLk~<&qn39Y%L7 zZe|u>UAM@zDt3Llh5e%4-+s^j$ewS*O8Xl-!~V&>YTvahG4+_6?fIu44GaknA&urttUfoW zaxW`9q)wgKIt@_j5ndH*m~)s*h^gq>wQG3Q_uk8XZ+jJlkAznZ3)>yGoe8RkT%PfP zPX#^o)HQ}ij#9$T{6 zCpltxtH8a<&BfN(!tgj;bjAnb*<}HDkbo_9mWd$~D=fabhT74Gu z*=OSePXr`!)7X#ruUJ?w?UM+*r#Vl$L*HRMnQO?IX}2WaTut`g-7QW8 zTx^oNClbHpYboD+ll@Kdc|3z$OKI6Mw`H>V*Tul7Ysq-!IGAfTvQQJ8)53b&YSbvK z(X|vjc?`A`YjIvM;u5yAXZhpSZ|v#oq&j*n1sidvt$KCs@FF~A-mtpce_A&mwWrve zy|~k)Ns}NGR~a&xa{A86lkq3FTbUMiMIOtDyp}xduVKRiDiEMbji4GeuBFrr8EH+n zCNQh4(tb1fu{%Vdjdo5G_IWnXz8D-6fDULJHmq3jT1w9?fn8^^@HxAl-N&9l@o*7a zj;qPR(_DM*749u=441%t#;xUG7xz7Pkt^VUugX8gx8~s`{&oHXek%VdpTckBkMQs_ zf1SV2R}tz9q*B>mfcJ!tg!#fs;Ts`C_(`}bz+It|NG{^;Jsf6>%f*f20nxpOgL@Ho zTOZ)oKHSy^xU~{U2&`?CSIWVMV?zQB7`@;6MD~O4Sxt6j;+qF6l7nS%r zxQF-1n}z4Q@!GA8G08o0D+g7sd`@F^+>^g)qQ9ocJ@Ld7J@Rm!9;l-~bW^1?>nG-W z{d0SmK2fh%)u?v}SBon;Zxrfdf{gJ9(VTJwp*I!4a$$0()+_|p_z$;xv zzg!j$iKj)sTozuHhDv_9Y>t!lG}xS%g=fctuo%2vbiR&YA%(PrE6buh>Z7<0adA;; z$ivA!IeNT|*9qvC*?FET!8Jh$@B*1)Z% zN+vZ_`Y3UDvul@t0EcL$o~+DBz@Fk7J@cpK@i0^QZeGdhgxJ@W50naO^`+1=tA){4 zy{_C>MyvJJ35(|?4mxfez%w9F1f5gBer}20*UcGq8EL^gF{rYwZJpX_%TuFY% z<;n$=3yV3C+FyNJo2z`Oq?oYHte{ob8ftB|CF<8|L;d~_>eysF!ysQI`;m4Dcn|Jz z^2m{ZBe7bX?oDigGqUAPY=JYftSZ23ji@PggX z_KT|Flzqkai>l!rW<28;Rl_Z&JnI)#!*q5r>x!ynIk!$60x{Yp;G&+(qW_N2qz7~3 zxEUO=pn_k6N-U^A_aTn*(=PBgc$*KKTA@et*tFPHx`Qrim+%3-J?Ck78X)Be52UoXi*KU%izqx1p>~XVaM~jhta6jBH)(euBjm6EdvC2ug z;=x2sW9znPs}%qh~DWXbIL}Yn(O1a(vlij$1fb**otFF6)so!FbpU=UQ^k z1Q|$nyuHX?W4q#PaLrM!I2*hQ9cj>o3Kv;6YY6V@kuf}9$cMAs>@Fb$(^HIjPhLeMA)BqnwT%?pa8V8MEYdh) zWJo@qF{8L~O|fo0t#QN>ao4z!A^nvP->-5ztwUPcmL~i5?HkxIqbn3~(B^#foCXc0 zru-%DCbuh)ug(vNBvD61bsqCi>_-pgFU$8s`K=R4m-pwNC;hxe#u0tICWlmQggfSx zA?x`oSrLuHgRy1Zixatl!gOwq3}47Mcztpu;ccP0FrPmo>_ReR$B{K~vj~0toPF+G zX_}QAl$#ssJ4}LqPLUiYVGw=~{=+2Pkm$o?=^fX9n1sp-eVF{;{S$U2Y&jqHzSKKy6!9?P7gs;i9mgU207Wh{=ed~{v zD_27K@&V;1@pYNwwrNK*K}?M*#eMts4KHfnzCGmQ3e}HkSsjm>_!lx0W_TKq>Gw=GEGP>zGidb7{@_42A=9_OeRSiuK#@o)Hc@vo0=J&=$<7R;Y zW+$W1Aw0iAF>W0lui`!hGM>6ftR9*Xj5pR18B5r&t4&A`O)sgFh~YPhEAJ<>jeaB# zeATM0sJ12zzp(};^XsQUpMDyeF*^Mtv#&ACm}unV0jpJ7>n(T=suG%k4>^;ruFuUg zAHR%jn8!=mFb*)Lb1(_!%i}*7FG%<&@eN>&E!wg6bQ>1iw7wG>FtolCwllQ86S}gr zz7w2ts&`C_Y&#ksVjZ9~)7Zr^?w?>CF{s$}h&YOK2aQ952XwjT+&6%a7=$Uv;${E`a zV^oHDe)`^UZTgpQoj!SbIf7a;5pbPbP@-+juUa*|>h6MW>Py;4b@HNa-P(0)w`cNx z{7TMg!P}rf+of04_x(0i`&3KOzTGO5_gg&nY(El=uR>8fsupJGuNfna|2uGS@WH{E zmzdWX_<)(pe9ELS+n6KF&&+iO?lV=``fLmKMYccYMjx>-pIym*!)CBQu~*r2k%2sY&;uEA_*3#EH}-d?KwV%5P?7W@n}*k%y_6tgNuC)Fcc$ zmL*IT_YH`{PQ-VYMG#4bz> z#*^gV}&zcMZ3U z@}^&R4b#oVreAjr)vN}VUv~|}_v6=HLrc4>?dq;MF-qL^s(9Kq|G@XyelbFjAe84# z8)4*36!R(rLmAq84YwKEdkrMDcM5R73F!BkU(zp{$YF3V81tZJAOnrAM&mO~znFTP z|I8@FU8`SA>(~-@;lxImTlb3zOq|f5_T}2O`^BtRwmlOcA77 z`OuN{`W@=m9~yyg4l9gc^B**xZyvSs*&Eia96a_xCaxqyBSuCST|ws(1?Qcq8qqL42_WS77OI@$SQgNCVm=(V_GmY0zb3R68xm@4~iIxM-lRN7l*sg z&TL;8J~XvkGfk} zFxf&jh^xUh;z;>&ga~9L(P>{gLL;_Bm9IQ=M+|MQmTL#QfnwM)m3e)hpf!G#}CGXpW5qhG-vZGquk(mx2#P zS~!+SC^ z9%SU^Ikc$QuXbk~*^)f(83V&aH>~dMBs>q2Vj%J`_kQQWYx|nROz;?jgbjMf z1cxDb$#k6_7eBYw-@sv^+ey*U0nw@dHE0^lk@RVvy~5V)bi{oAe+!x{Hh_a_Tm!BR z=Z(g}YK}}`dDTE@$#>-k@Ln|#4)Lc;$K0GLw8ND9jiD0UPP#Jmo(eLNa}YNNye`ukm;Z*(pXTE8PwYRf{4%e+UCQec;ryZV=l3f? zpAIR!GPG7Lvlif9eP!5-FRCvRflz?j;nPyEKBgd7hSjj~D2c~&2p$(4d}UbAT-o8stTW~DeAT_?x^nX75w_3eOf0AzSW%HD^Xez zdk{GKppo`u`+L3A9^`^a``T;uUHVi5XfSCN6KF8$O1$ito<4}!gMbE;9=3>a;Jom=P$E1oMu^Xe z-Ne_#oRQ*WaiO?MOv7z&fL@C6>UaG0*KmvpFW`$$%FG+c2^t3uZgJ)LT6`JIjf_-#6V+ufH` zr~Rh+r&wWx{;}?#Vue5TM-BfJE6hR3v44v7A4D5vFt?ZGL9!&r%ZudFm*O&*8#9QJ zn0RIpLwL+(FgG{Ub~5cUm|GdlO*6GZEl97SH!6d<@${@>8O*H=<|cX*_hm4*XDt6n zUKz}-3}#;jvv(rwIHe3`|0o;Aa%>d)Dm#>oW6NOnk7{8Wr$uS6YD2X+tqf-WC?Cdi zd=&3EYsz5uW%-Ao3Ph)fHpMcSz4@`Zz*NmGSVJd1sxp}U$I=2xm9|KSq|;Kq1b<48 zk~+T}CBG^UmE&ZXBYz=pl65&tzAWFCgB1u>%3yAc&SWu{88XWEp98bMOJMd{L&!Xu z%bB`1gm9*^q+po<(1|h%2Fv5*8S+xuRYm~~ZjuzB!A-UTG`LAofd)6R8qnY-O#>R- z#OpwVn+zRt^;>#*!v!~q2GHOp%K*~ZY+$xAU1b!|;3mcb8r-B>K!ck&8=~x2?V)y@ z?JA=n%f4*iwu2d083luxaSUND5oJ_mnH^)}z`vBmNWqgFfg*Vhse@a&!wtLO1>YG4?}f-o423r5sx^?Z| zrA)3MMd`(7n#4Kw525+HYGAJ@JP?PRyS8|efAUFEcnrrm;9ar&bbd81-DP+)`_5kP+MpsJdf^Fr%nV*gs+7?!ViL5 zCxV7zTd}A3rs&p*V2AjfcwYQnbn8UWO?pilDNUB#IuV?aewFS?kI8PG2!_cM<+<{g zvRfyDJMtq+9i^$_)`_sk`?<1S*{7UPa+D&aoC;)etG)V)`j$FIO;A5mVXeAL{a(GO z7O0?A)t=Izwf2(sy7qzQ^cl8okg*v=@F9x>k(1?svg9}ilob+KWpMxwW;e4Q$`&GZ zdT1Qdb$VzVNH5$!G=4DGxMhSewJsI~EJm&p8%(%LHO%hjQ09IdGyV)=-h_m#2&s7T z=+UF&ah4q7aAgSFfkXF=50o~aalChNpo}#nQV`v3!Z9=3w0>%0J#Y0!0K!-cKCx&G zJXE)74Lp2h(;9eqj-fU1@GV1Y;Gr)|YvAD*me#<-ha9behjKivfrrm{S_2PH3A6?t zwh68VzKU31Y$3vnVt?^H@gs4*xKjK^%n;!x@v3-NtR&TwnoFIf7zy5$CP=fT<~mG6EcFOk3g7^iBX!sQAT9+>Ms9GivnuT?6h;S8O7 z7=dQK*HrSD3i}m9$wjVSd9{{G9#f&0Dyp&Sbak;xxNXPOG1=;0MrHHSuW*Wb!O4P( zTd-VKaXq4R48XDWj+(Hse*G2oE2iPpZLgF{+LaTbSFuSPi?R;r-Jy5yifKsKOV*Bk z9f#ejifJ=v&fKEGF(UE!Dnfrwcbv{JS@)dIzv}mNc+7YL8);n(r@=MXfG>^B#zEtx z@r!ZCc*Lw@LQ}Jo*~c7WerV1#KR4H#u+KbU=9oohIjg4iwAJ2%SFE?JF;;^0nYGs1 zWqohKMXSI9yQ=+^-P(T1e%*!-?5Xyrc8a~tK4SlDU$^1DU4^O7v|wIj`ZMn_A2BeW zS;>6EWH3K5SDCv^B^K(j&DqXu4EruSft}4RXJI3Ifc=rpWB*_)aJ9K69N;)S_ck|{ z`-EGI;Pq;pTFtJ~Ud_u`xeH5>#!1o&;n0iNA`MFj z#%68#xoN_E;fw$xv=HfE4rGY*F9%{I`j>MTe>&RLp{4Mmz1U(&z;=K6h24U>bqh-% zzOBCFOQa9R*+@A6#G!$VB|q{3j*v^1P9y~vY!!|POPCtFME*7oOL+J0kx|7l-gQ_m(*{^A zidJ81p}nZ}*Wf+vBW=F6Qu{{B(0#U}kGfjy9*6N#wEz0JHzld$R z!Y=u^hYl5#m$2%)t68^&!oHWWBVO2raEOxe?t54`+qp=n|4)8ukSEcL6pWQi7b$s< z{DXW+z9~bXQeA1Nv{ia4Zz`jeX$mAMUnx73@09b(?@EdCxC#;Kb80vBH5Ds*>Oysu z3Tf)M>KXM{^`82e_JsDV23@qi+AwXRHdp&n+pHbb;H378c1L?eucJ5BJL!FN7@~iu z&(uHH*X#TA6MBvgMS3}-rt!4V-gw1$%NS!og7KNL*4Sl`GAik!LRIrAv$gq>`MUXm zNuZCAVs0~!m_M7>&HH8*tG)#-tQW2R)_c}R*8JZJLMle*<5_5qwexrUW~)?;!T$d; zYbWtS{R-ZC<19DetvAkc1KxV$EH`(_dQ-$-A-JuQii8wGU_!f2GtA>Pqi_YN7_)TT z(xsKzHr0_v6T)43gC%W>iZP*~YA9&{4`OFk-`ipD-ik3TTeh6RZmk!G`)$P-QmiAD zmHn*o_;r@7Rb;6G|5`A9BvQ6}T5d1DBEKcW z7&$@yOkOMRlE0TP$^|ljQdN0MX|24Z5P->41wK_$lx@lpQOchyQ-J*~M0owXS4U2TFkTU)Me)DCFyqn4-rp;gdp>rM3M_1^m3 zxAn35Cws{X`5lj(S^O~Kb!}f9PL*fp;h`x}2Tk9uXYQ(G)H9kJosAd+-Zdr|vkiwu z`J<6%z#m2hv$om9eBSJBzHN>*4}M}UF~2tVm_L};D;p@GB17-ldG+eq^#G}V$N)06 z(tFXRufKlqb#@-Us^oBf(i>I<;YUS+4*-`Z#FU+sJLV+=gOJj--p`ZB|q ziOgK)O9nPG2bq)1FU%e05w;H7l!Z=gA9hG7+}5EufroK&C{EyEoE(Z16mTxa$)Pxb zhjDT!PT*mjoYEY47$>JR2Oh@Bp*VquadIe5&|7jbP7cKhE=exN$)PyGXxYU$Ir45O zk!gAN{e{XZ1uJ7vy?R*n@I35{BqLC4lLERzyQ*N8O1r9{mPWg(Zm!dIYiG^FDFl}k zhhKh!Jp5L}^Ga^7L9h?u`cyf*8S4t+c^O-dXq~N#-SoaYu|XD|*R*MD(<>=4`ltB_ z@ENaTwvb+sr2nk%*nLTV#HeFHQv>_(#t`E}W2W)BvEG1v#t9?GC^E{KHO;5Z_9nby zzGaRv6U@)dwdOAKdlN321twTkEka^?$$H&_4=fsE2lp)+V+ZqX8e<3bnC47pCWd*J znZV3umNT%CIl%nLFb;M~+#ZF=$aftY#I8*#wB%q{10!oV2Get-i zw~7R77%sJxx=I5i7$N-+0o^nwpgX2zuRSp7YVs-j)TvU&c*nmwb}UT8GY+Kxm7c!; zBLd#3*P&j$!Zcjai5K)@lyZ3@(pw4CBVa=hWtP4`xr`Ius*Fp<;AM$s%D@H5>kM_52g>liOt`5YQwIK$ zX{HR!Q)q$_)Ky))htmuKx-QaKgAN)^Fv7bLO)!EtbedoUzv(o=2tGDwf)PAw(gY)L z;m|I@2bXlmY8Xb>rEF!|ZQhf|va|(JwgB-2>BQ_QL>cg!Qqtz*4RK>>(@b zdK}j4&PCw;Gpj%*gczi>oQs%+eL13lkF-1d5#J#`{#*p&ss?i#p2|mzLOXlVyj#=X0CTe^O92Zk?MMXScG zT6I+a?VC-THf0sf!V~EJq?-2cdUHa2#IF&sgK3vu`*HCsi2NSWQdvbvaA_N9v@x;> z)@d+0AV^GnFwJ)sf%YbS7J=_g`YZykTl8532vgU876HQ4^`Aw6U`G9C5m?U9XAvOm zQU6&4_OSF>1bQM4*MAm)^BjE^fss6Y7J+*_eHMYa0(};NIwE}*f%W1(@r0No7K!Dg zn$pwKnD){u(p%D)_p$6+BO@5;IHRO5BtoIilE82LAi@uzAC3xT@Ebpf@MFv(WsAO3 zNuP;0gc=$77`~?~`JZ4sTct(@hBuXse5HZPeHMpUlFCV#nl@WrjOk5ff>D8dJeW39 z$9;|R6ntO?R zo%?{B%6-bEaN9UI!u`x$=k9X^f82t9kuT{PN$53r0ms8}Fa5*dWhEz@>OJFa2 zU?Ptb$9WU^d_ls$#AW&dZyQ@htCahhgunxZU`w`(X5W;^`qS&zubgyXa3z(%$MCZ} ze*8FcHp^M0-kjVCOVB6E55e!Uf%N`+@$q5t<%i&tSG4p#{=8t;yBX3?(pBlMR7tKU zH-_%Al4Yl;72L)H?Y`P{f}(R}WeHqdBWKg43)}VXc~uy z+QotR@ufH1wVc6gPe0wd(C@rs`p;=9=;XNh`);W#K)v3q-Uir67-dZNfV{H z(wEX^>7aB{f?uRN(j#&mxvAVq?jsM8;X`?*{JFed-Y1`sbL1i<5dCcyaB^HAL9Rc? z1rp@?b6nVlL9Ty60TSf;7Ze~tu75!R66E?96d*yae?b8fZymy+Ond92knC-YlF?3?akn) zl01lL-druEl1#Br*^r6wiw6-mZU=Tee?Ip7vO86oFK^);@pe%$;z>^5Lp~-H6Z%LI z#x#(RZ(ExJ&lF-bXFueR)U9&62>Bx&8G*sa@<$+zq2Ho_a7X-aQE-x_-=hA-h`4|U z0jdi0TNI=S^jp+Fcv1Mj6Y~~lWMm{35fIEQ)RH7tSYFsV;CA8UpvjZnF$toE{|B$$ zcN2>i7+)Skb}opAM6qJv1mip7MEb>x>P12rDYT7mR~=fl>Pw@hdE?HB*ebxyp$11YQ z*){E_?e;djV!vgNu@mgi?6r7Q{@(syA-%yy?f~~Am&g6VRp4v$O?Y^o@6Er>kL5q% zm+)Wndw6gc9e2$^1d<>3ab5r#_c2lg7x&?=Ip8ij?wSMcqT{YP1x;mqGfX~Gs}@$B zk?)dx1TWqFRMKWI{a(GYJ;O#-4iJh6 zQUR;ZNtv33X)goF5J_CyTqBV&ysNonBL@@%9@)qN8^JF9At}bFYCL7MHsB@Wb>jnL zs^NlS;Ai8yao?z7x}X?%&-}=oZ>}_5Pz>BPD_MjTps{*VLXuuUTLve{8a0UBC8gK=@BpPr9*%A%7LIyewxPk}Bs`LY{V1Ysd zu7HSdT)-8{>0pzJfGd=(+*X~O4)AeX8?24fW@t`M2giMlG?LT7AYIbq^+oy`-O1^| ze-kGcahPH#h9C0_l}*<4V}4{)}k*r+nmQ~(%ayqnq zIapGcN($MwWd|_T7?(;4qZpY%$pzz5N#Oy*u;FY=)}@jHP0xRngD}iBqqtW&mr4qo zFq_NbE^}@)2Y$UKiRQpP{<_f|3=)unEi4jTDk4b_b_`;CXW8Te3Si1-%qeiB+a6?%)(;BW5%} zt){wzQ!q-E)kJl*>JCo*gPSyL!fRBP?y>5jqahfB4Ubh1$MI#S(C}FGFvyh5cyp0S z2B!$C9&VVn8De>?dYED>Y=jD+L5-$st1Q5<{`wO8N)NtjK`{nheJ<{%c_T7 ztjNZ)9;+U*S;7$W5MnTjlet9BLx{lxj^V?34?!sNTg+DE>T=MGmQW`92$|`jh^iD;NR%UJ`Xn(+Hndb3iFT3LS>D1oWcscf%!*ep_xuQPQg#) zX>4>bpqD{APQlAdowyW6nY7~+yu8$jOM&F2{!!Ud+Pi;L7B<R$KRzuZiRB$YGBR14K0t%lY} zYp1=e!5~f2;x(c)+^HSaE@*H=v$YWYNxhZcT_32wuLBJ%{YwWLSUS&u6^3S{8>fsb zMzK-RtZPCulQ*Nycg*qTEOVK;!2~~%r?J(+f?k$r#ah#?#nw7&w{^?{$EsP)ZeX{u z3C12q*|MEzJ95)=_HQ;kuo)(tX~}eD1~4O-j~Q6NsEnh1&1e2(9%aGbNSnic!NMk1 zXS3ML>}@ufBhfn0I+48`9Oq1~kPG5#@I)u_G7p1ziI3+O@oV^<{89b_4@4&tB0MRy z61ocmh4%%RA}B(#u$2t*2-k$a1gI>sVx;(jNc0?&#CamD5H&GfJSAQci^YmkT?v{= zyc8|HQyN(=lQu};C-OALgF29tdaOKMUM#PZcgx3Q$d)ZRK&hsX7q=eD8w!k4WF=8q zjW2BuFAp9lj7oTUUDW~V2=!wX7O1L9RCA}*eDzQDQ4Rc!v^m-r8f?;ZElazs-PVHj zQ2iMlI_iQxSRbd)(3k3|`d%H5>!x0)2N{H;-_Cg1fI)^-`rfg|*l8R!E*Nmbu#FJ& zNwXEso(?qMH(`pYn91f=^RRi=yk`DoLS>7!BCQv!e%5enk~PnQ6_#eDTc@lmRk$GwYb$%rOSYXnO!# zjcvfTVSBJ|urP|1*+h0VyPeHs&#}L;@PK7Fq6q2A4d6y_A9JvPQ@JhNA?`Gn&;7|g z%7ed=Hi!R$hfTcS{rijn9WnnMEI3xnRAH|G#|2X;6oSMWB60t|EW#jB65~bJ{d+-# z8=@_SNUr<$eF>&Wij*w5?%%&8z5*(LIsZa`% zOHDjD?FoJ&4*~MP4cV4MlqZ!|N_S&JA+)-652sAe=U+88~IHw+kM$VQ^E+SqPn8t07P40vELrXw30V2&_9 zHo@OW`_p{Xf-sA-qO4b~p;nwV$NIv8O_pwDS(mNbR=rocNmv{(%=V?*jft z8Y!fKzmZ1fUBDdzCyg{xNP~`wpbS>VDKnI%N~*F~0W>oxg-VcGLv5tCQ(soW!OVM< zdAOn4YKZ1h=7H$Zk~NPq50!OR_ZJ3Wg|6xT!T>Zgc*9>9fc=JHkivjVnTKAcXvUfz zWgc+$A7foF)rC=(Y$aMAWgZ?_j2&)!sVKm;qtJF@fvBN z>@zHMWCeCG>nLFfTpo_IG~gQsaS|8Ld4O;5Pa+KD-{)ZpPXoT8vOojA%kq!1{G%-Y zAWbpi>MP4X{@t`?W%);0{!x~Hl;s}}iNt03M_K++mVcDxA51@HI5UZv$CRqS)0tCD zS^iO$fBYNgA2*%+qx%>#Qf-sj1e{n08E2o#KxbF^{>O6s*ix>`YI8MUMP%97W5)uH z#iPZT#M({}23`{81YzJMVNMVRUJ~X6Vc;cUP7nrO66OS9;3Z*B5C&cn<^*BjC1Fkw z23`{81Yyw9>}onmm=lD7!)78$m=lD7mxMV%7wf<0!yB6Ddp<|bp{Mq_R=25vOwCSy5nG`1bNE`fKC zw%Ea6EakeiD8>nr+l1=^nK-z44nxrzUD~!?(e^gsy3`QbbUt7oI8bU_B)-twE&6pO zwe?J_HV+)zTKMpV)KoPUaE85K&wgE>q3STz>jqy!wKNWx{%=n@MB%ba02+TE`;g=eyj_jx_}?+LdN`I zj{b%2A5H*2)`d`AAl2}&E`;g=eyj@_P5?5U;2%!7UwS)tQ7_*)sFx0k@}LtM=D!n; zSXKJh2Jke5^=@Ic!cWHp!zm;D}9BO&Mk6WMr)T z^@5@ReB;_(wMmmE7U1}7`Kvfedm@o=Vv-BG{y#_Qm6=<&k4Ne8xYe0ijf%Y2E;8dW!1~fPoXs-bc zt~b=xhJx!2CECz;#R(!f6=<&k4Ne8xYe0ijf%Y2E;8dW!1~fPoXs-cX^4h#oKum=S zyEa(^K8eW15#@n-iF*?h`yth3?!dhAJkG(Q?Y*CJNP*LetAca}<$$Ol{f$;|C*|Bh zxtnBCZo9d6BQb7f;*9LTytVOrQj?R_WCDx9$NGjrprVKEO<_N=2fRcWuC1Wr}jYbSwImG;_6;8dl(cG5woDqY%6dgIks zSG<~ z)_}%2{HOtqb9h?^#5w3o^sn_j`Vaag{iY6qMs=g1(bni`ylIR!rWufAd}Zvwx$pDF z??#F7xCs&Fb7nX5HFKmn*<5I@G9k_U);weWYTh#+v!1Y?wV;dD*BWL`wB}l0TAQtd z7M!$xvF=!p*mdltb|<@!4MXe??V0xH_Ii7teZt1c|025_Qb5r*Q)eNhrqS z(5U9vK!7-0$U_q5&!0bvgS{L*F#<31^u!2U;OU8xY3~bD1Ol&AI**JFi4WIHfimY7 z^d8z_=+KY^+oE8fYr|h0{7;{i`f@L60q6S zEarzFVt>f))?EDH4aCZXB>X?@y?eM1W&ienT6U34R-t5>D55(iitI93MRC()o4R9A zDQ=9l&}yeaA#F^SN`%QOn-qf(!q|&qSY=lj%QoFvgA!t`dEVC=S98ttJip`q-uLf0 zj_>#TJpQ=;=?^*%^SL(X`#fJKOT%^0C+b7>F^}Zv*sdSaf744Dd}~9J?r^|BlI}3j zM3U}MXd+2>7-u0Fv8-kzidgospSRzzr`YpsthRIQBliDi9q2X(2c2Yn?d3X9*8KTD z)q!%8_y74i(2KpRZ|h#2urf`;XD)T>bh=ab8q=!xp*rJf)BI_mz(V&Luf106wNc@h z;pXtiFsf}t+}jvA2l0ipLE0^ykSj=cfsw|$ z#!O?WvBlVD))zx~|;+3>mYkhAWv(8&( z?W%S?`#u{T?WgSL?APtd_UHC0d%KN8_HTA6=LY9?r@8a6)6+qw^P2O%Guv72eCr%= zPB}<%uXk&?jor5H6YfBFxQlG}6L*RGwflqni(BYk>s_kh-Th4wU*>DOh%Zy$)4y%k ztX;c;RJw_E_g-CJ)Lu$EXhCXey8MptzVJ494D$d+ViU)wc+*eX$8l2-+s7x!!w#7= zTW5y+g4B@m^hK~4lMIp!HZv^$96gH*QW zS~z(POUx}x$zG%;sdk|Byfpr^7!a3mIwW`ZNJcr+6niN&Lt zC_-Y%LNqhVX2#J>MA^(Znu#cz*;Rd3eNlZ&ou*>Gx>o&OJ*J*l%W74%dK&K2I%-d8 z&uOn~leN#aRT{QyhqT|cQu+=0?Rsn--pyQODVq9<3G8!9g zjVFwO28J8i#wW%S<7?vw;}@gQz_n%#^KP@X+0E={zHE*&@sYXETyO3&e=`3t%URVd z+-ap-ovl9B^VS>I6l=jf*Ung6x2|7A zpBcKUM~`AXhOW(A^PGDs*tOt?yrFAM+LqaCYp0uE`D-e^9lDn2r&TMieeo=jXexT0 zyo^Gmd#`(aHjnfE1Y*HY0vvIz^qQVzrv99#MZ+uhOb$cW5m%Jfij1hG?U;541Vj3T>N)gW4Ib zgkDLntvA)%={NEAF`WAhkp06K-k!sv(G%_AC=$*7}QZ|ujrrTKt=DYLf zGeq8`?Ec03_wP&INp774YcpitNp774_fB%_B)E6-1^3OR1INCJ#$jHI1-DEZ~V z4D+I29?UQ=`sKk4^P*pV=}>Eo_4YUdWE6~4zf#q)JqV^zFfvt*I5q5@<*|nPf{_Iy zUU|iTg>BAbAOG=3|3`G}*s);b%{R+8GtsiH{iZ(F#*=m{GJH+4Ie{Fzy8`@IkuzGA-@BEwhg_rjOZs&w^(TV+Dc*dn~*Ny#N zIOmq}Zt`Nk7shy#ywAMY?}f^K9lx0$`@JyBk7K;d?}dAUHo@P5*zbi+!QS8>LG1U! zqha4L0@6f&uY-}{D^0qs1nESDpLV_V5){j^=qD5~zx_?MDW z!+BCFL)Vp2x9|OG@7`9W=*K#$Ue9Jdd(P-cPuH!wujh}dLF})yUFpgjf|M?hMiuK= zGdi-`b2HqOsWh2qGGb-H#xmvDp0xF&ZnnA0ft3ME4^M zGXAIg5zOTM2=AE5`w?!olJ_Ibx03fG+-E26N7!yB??>qAB=1K!*n?IUiQX$_{dx6t@n0$KY4$6<@{>h56XacZ$Q7!!V!g+Q8(MVH=x16 zX5~kPRGd9~Ko|1v4c;hOc)BJ%qtT{K8xO=V9`VQH4VyMC)^tR8SGjRJI^J7DdRA&( z2K^*{|B0?Y|0mECi0?nq^#}3&C%XP1zW+qmAH?^c==y{B{u5n)5Z`~I>ks1lPjvl3 zeE*5AKZx%?(e(%M{U^HqAin=RV)wR(*cfepV9&8v*xT%b_8Gf`Q#eo}@D1bMFa#S( zP$<`|T)8eObPulRbaM9H=vdn+@6;t_-n?S-o+fcA#-$-D28?lOh+~*h3UhS?M0z^> zyZ6GD`|qE6f0qip z?OVNYHK8`Tq})09&N~adzw9GK&e4rmrIIYr$gkMza*hBzNWgOh;6VbOBLEK)@Eien zkbvh1z=H%lM*toq;5h>DAOX)2fCmY9jsQGJz;guPK?0s5z|(4$%7O$uM}V_xY3)Ys zFB;DgV3amdV?hF*BLEK)@EieV=wIra^&fSfBS1srLE|w3knkMA>J7$jN^n(mt0qz_eFdwX$2Wba0ya{YaFL!1N!H^**(u`V^f(ud9>Q&((t*eE$c7;e?Ea!>%EP7Z?qPy@6oO*kWG^5Dsn*BHO{Cpb<< z&T;z1o;GfJe#D3o~K_)~=CcXi+QV=DX z_y)97L6l@-8&G?rlloW#vj~?{yY{f&V`y0SnEGb(ffa`Jy8iI>*Jm^;FRyMkXU?1{ z!+N)FNx#{Z>OUIyZPvH%u-^3gsgwS*O2QYLDpahPR&iKw`VudwS8Hh+ln450MYMEn zp|)PzrGX=eIe{1)LCgun;0R()AO=Sea{@6qf|wJC@h5`#GJzNzLCgun;0R()AO=Se za{@6qf|wJC!4brK&jCje^F0T#W*zN0h&AhI&q1tNM|%!p&3fU86ksH+S82UQYZR@~ zw8qeSoz_@dZ_s*^)?2jRrZtY1Me7|}<7s8nnn3GaTJO<%pVmZLAJCdaYcj15X-%Ou zmDV&`Hm#3nO{bMZ>tkA<(3(MOCaqbtX4CqV)*M=&(fXX$Tw3#JIke`}T0mv`7qP2q7N?NOExwKZ(T0?6st#!24)7n65BdtxezNWRA))rdd z(E66vR$AL=d9=3E+CeLq)_1hNr?r#TE?T>3?V+`o)(^CPq_vOMep&};`Lqtw%A<9N z)?r#lXdR_>jMi~lKhZit>t|a3p!Ex_leF?_1+-4lI!)^gtzT*VM(ZrC-)Wtrb)MD* zT7S^GNb3@<0$PQ%LR!U&)Bgt>S?v4CZ`6t|%O?&jTC{&romARFPaJsbt%A4eq%ubF zfdk79obVq!NUXX#sa4b}RTzw=6(y*^B2@gQ%r44c5h^i31s0(a6I6w*8nG)e$rOcc zQdX}n0x5+=QYr!|g?Q|-$3Wr}{XKmu(5X?E@{$-s^Zh!hQ%f#XmrCsMR40`#)YVg$ zONB>@Glmk)CkyK^*^xbu3-^{{SH-DQrv@OAdPWKXlz2ev29B%79C?Kt4{K{HXsWbR z;$iJl1zVJTN<6H6NX6r7e>EP~?osixdP$9kwa;pJQF}`han&fRSJg#aH74ty>+!Jm z1_QSn&5d|iJKMl=<69#h);2cL)_lT@hqYgu_`&?ejEA+|EHG%K$czMoMsj8(8)zV! zXv6~zRB`TbS~!n5y`3S>Xy*fG5XaUKK&fSl$p}hx!QERbzilxZ;mlyhiBoy=+E!?h zH=`JhZ|KSHx_L9{l!r-YD5F8nNGVNC4|&et-6&g)FWe38Zuf+H(T%dzxZmsIJ>$LL zz3D~SYQ*8{CS~vS+x-|8;g!h2v5Az&ntqnwYDtY6c{Qd>v-}0SGK=CG%duK;$y~C6c8%^+@*AoyOh%A5O^s7G42}9 zA@EX&UJ-aHEV6|Wcxh>x^NjPtJhELioVn%KEn8k-fzSmD78Ewjp^6IT@;E=&`Ehoi z9YqADkPu9a-dyHlnKE?`5rhdd)EP6_&Hc}ia2Ge0nf`eZ5yV^}lbImq3R$cWVy=+M zOb~O0OlE?ZD`c@kh`B-*D@04Flf-j{ELI5KbjNaqELI3HSIA<8I4u`fDk`@rO_aYX zELI3HSIA<8sG#1WHdG%}S+0=93Nc;%LfxS5R!^uGRTe8meeHg&i}sB6g7&61m9R?Z z*J$5qd((?ROksL@1Y%Olmj{8E+K=4k6kh)~wu91eH~`80^%?3s1ijBd1ZD~A)~%~> zIZzCiC>8_7|Dru$2H7aV62)Sm7%WjN28zKF#bTfsEKw{5is_AZ6MLim87Kxz6pMjk zutc#KCQ!I*TV;_^R8(7#e~d9@@4iZNFDP!a>h|9vVh!746Apc>kke=|j( z8upt1Fh!sm`dTkpB2W#<=7TI7qEC$3#E@)0nCKvu@**V3Bm&j2SNew}0@cu0en}RA zYDhL8WGNV{e5i;(HQcEFMHPW+;AIEA>i}XEB?GEqv-aZ^&vFb@`(HfEV4h_WsD=~4 z#XtnA;f3(cPz0)>jC7ME0@W}{`b-jmYN#VOlSQB!mdW49B2W!&l)ot=Pz`&Pe<&hQ z4Sm&@R1v6#NWF-NhzzI(MpTUsuCaEopR`$L1(F>&l^rBIaArAJ<|I2S(8f)6R)7tv#m)-!^^%>}17|?Be`7$5zWPhL2voxb{c1x5s$s10p&g7c;$0@YB)y~!1UYMA7H=88ZyFru0WRKqgw8&3qP zftL^S?qRU*SP`fOUO>TtYPb+w9j1j!$bo9$<-;7P23|hQyNAKbheeR79W}7*S0Gs(}&JM4%cNQB4G@ff3b2!5ho;q~HxkR1<+}U_><$ zs0Kz<6M<^DU|wyBKs7L;ng~<_BdUo&H87%@2vh?js);}~Fru0WR0AWbi9j{PkN)V* zkND9az4^h2Y9de#jHo68)xZ+PB2W#Cs3ro{z=&!hPz{WzCIZ#Kh-xBG4UDKJ0@c8X zY9de#jHo68)$pm3w8w%G)kJ$N7*S2M$AS^nhG{WS4UDKJ0@c8XY9de#jHo68)xd~q z+!e%3K@eR*%oGGhRO7B7W(oo$s);}~?6v-3i9j_lqM8U)10$-5Ks7L;ng~<_BdUo& zH87%@2vh?js);}~Fru0WR0AWbi9j_lq8cBBvN8m*&Gy%sKy7OYz_)WRO5qC zHU|YGs_{W6n}dQ8)%YNk%|XG4YJ3pN=Ad9iwRjHkr~*b*i{}u>6)>V2AB3_wD8xZ1 zn}b3egt9p(#6c*VgMty&_#l+cK_L!8*&Gz&Ae7BPad{B>Cr}NHs3ro{P{z8+5=(i( zT6x7%Ua(ePv6L6Al~)9+ff3b2pcSc1gc%p zKX{Hbijn>s;{Y(Cng~=woFk25q+mof5vT@6RO7KxmKp^ks`1z;OO1jN)p%@_rAEPs zY9de#jHuRL0IGoz)%I&KPz{WzCIZ#Kh-xBG?VmRYUeQ0U=pR-Ll)s{XT+u&l$*Jz# z<@_gRwy)?PSM(3+?7X6XSQV|?tbg7db4CC7Q5J#nSM-l7`UeGGI8groCjH|S*FRVp zREWzspb(dFKzWaS;xv;=*r=fAdX&bC=5!E`6zAfaI|F1;a8rXpLiyJm<2wD1q!3-|V&D=4R0S9#5)#1is1WL(M-dQ35#sqJc%+xlFLA%$ z#TT2~@tuFv7n|D=H$p{)P>36$qCzOV8uCV{Xnu*f5h|KrB5s6==9h>Yp`!UE*2z2N zxVgPyjVyBN&dnq{cSEJ{$veni&1g$iskvnkL6$~!?5)gJuw408IiQ?UQq=3!T54kz zZPh2#f$DHITm3{`qJFL72lW@VP`y^Gq1~;u*1Bm+SuN=sZ73EsH}e+vmRndPb!^)& z)GxjO1&gP*p4Kv?yd5Y&h2vxdo8J0;t z&&kO-s-4qNM!)HDyG3MQfe6HBbPI?;d`7o`2*hV}3yd%)n9RSz?JE$0_{_cn5s1(1 zD-ePB%)SB8Lq5s1&YI^g~lo_m4_ z#Aj|!h(P={iWU}jIYXfs*6qG8qvPlfNbg$ctqVMT#3)n2I=y!)a(v#)Ff8Guqx;1w>j$fp+kq_9Lt|qp~L{P?z`{4jE)3? z8CHe$WM-tcK1)CF!eLcd#(?^a%V%`F_S$RbrXG@61uJg2En=q(msxM`MhayqVsCF( z6+9fyv*F<3aGnhZ4~O$?ICwamXT!n6;XE4-9uDW(aPV+A&xV7C!+ACwJRHum;o#wL zo(%^NhezS4(KeFds7elMJ58N-P7i00Gtzn2ndxAuv&Grxad@6BW8d9$ol)v9ORXLYpjl=YnTx;5GQ+*)OA zw+>mWf3r&2H`tB5o9*=Rty@oRy@PR+TH4RNo9E``F(%iJLvIy->#e8ls5^;G`XF{E zu}L4q?j$zpTg|(Zo(_yDjT$X$wByi7#(QYL>Yirz+_U2l1v1*ZUo6cctLBbF!-fr8 zu+WSMKIL{CI!-B#1#YmE%)#Y%93q0xyUfMtbjhGl?RAE#5va--{^% zc--&rzv9Of0sQP=^2-M?MF1}bZxuybc(Mf%Mj)mLApTaOPX!T1Af^Z)!U)6^0Yn&q zm?D4(BM?&r5McyjiU1;vKui%pgb|1-0*EjIF+~6oMj)mLAi@a56oKIpMu2@QciN2x zd>@k2ojK=At8|AUXi`Jt$!D`@SDwC*Oq#t6BpZ6JF_CQOnQ9{0&{Nl1s#@LM2VbWw z`}Bp?)rjHK%6fHp76bS!B$V3-EB~|CDS!s7i0KR7A2G-J>CH`>(l$+B zNS@Hm6iYv8A$+Z@{fJ%9E-~Rn`z?E#4IXIWc^2?M3(vEF2U>WZ1w7Eg^DIb)=mvU7 zhUf}CBtvxLd?Z73)dD0#bn^lvLv$@dBtvxDLL@_UJtQPUbd;e>hUi|A@s6BiFyUr} z7)%Ne(M?k@Us#F&GYfeu3nhh9p<1rdmh_edt_7^^@ zC_++-vx-5i{iTbgcBZsb%?4&f=~;fS-uR`?DdTI_r-a1|`p4a}Xlt+8fG$$gJ7&=# zTeAVtAEr|}L9N+lR$2<3lr^OTog~IQN=xzmVtyB)oB^=c9mht66O6Ne+3 zfQi$4>lmVs)<4iWR_Tn65=JGXw!yJVBMl_6N~tDpH5-`^nH;N>Vm(o)%Jh#$<$9O<`UQ_ z&HwAZeHZubtC-8)j7N$eInw4bm-0Wx4Oq>&0c~#Yx1&?1uoLJGL@jvv~3(c*E zt)5n<^_um*HQQQl;alr~b;?SyueWR2jqSEJp0Een!|iPQ6MKpMwf%!V=oh=JU)8TP zoh~5PE6OxoBQn`mPZKoDx&CV;WarFl3<~> z{F+9F}gHIkVWznj3GIR(KCfzl2-75(E*He)F38 z-J~A=Ab+I)uK#~EeGHOcM<+?ZaPq{4%U+vBkV-Z8F*Hn^{Z9Vu535-$T_nyi?}-_GgVb> zwat9}_18hoVUvBD=MJ#9M1$va9&`#ctp{;&*j8c? zxs1H^ocp>v+5OyIGn(9!_~F{`Gz> zzp>xef5IQ=W4NE~f8sCkzxIFdfAI@_TpQE~?haZ9-GY9>%fYw+9|a48^}(*-r{IsE zTu5)EJL!$oIqVZYAHESz3FrN1QP);SFY7Z#3A1c_q82S3{{AbkFlbT1;WBL*HHDZ( z9Sa&z(v)Zc#rBmEyco+gB)u4IbR@kPd-c_k7o)CymvL{Oy?gz=Oq?ia@ZER&zq_{| z?Vw%yNK!Fre0JBT+qSIMaT8^6;Bi%D=(C-EZzc?DzCD zeZ1zs@6Yy^```Kp{8N5Pfa`-=LF1rp@I){$7#?H?_#{{od>zEBW859K4n@{6)`z=7 zk#&sDQXffV9WOnlrf65)L;_p&*0+X~04pLCg@n=8brOFrUVr^r21vn*;wx5^lsm~! z%USY&tfh81XO31kB(+J4d%n8op0g>0)M?UaQMhPP(L<+rNU1|cdpY#gp+iktQ~0b& zrQOYT?|yF}U7MSzPIF||-)2lvkEyGh<*GMmzpHr2d|2zLWooZ!?`yNQxxxBk!4C8=<4k)}og&y%_IU`VTU>Ew<+^_fn-d2_MN z1%A}J7G)$5x6Vfy3B;}QQAT2T)H=`VhU-dq;r_4gzyD+|9gOu$b^5APr<1vKi>+V& zh)aA(lIKt6T3=aK{Zb?mpUh>UFznOmCBI%CPnN%^P}TO?d7=S%C0Hz%9K?_v(?($lBk9s_4 zfmq_JET#E>*^@=b-_abp!_?W8Ri{p!qd9~ktK;YE+h2I$g`+ut|NGzbyYHg=)zKWf zt}Y##(!>8~HwlSHb7~c@RcnMl!Kc!I@7MbKd>r#vd?&IW!GI)OwPB(S>V>gt!$cdb z3X|+dJS@ek4HIo}K#ElxCfZ=29IG}=v_YX9t2Ruu!8j#WZJ20-YHF<7Fwq9{)L6A) zq77PTv1-Fa8*I~J)rN^S=%L4|4HIpUugC01Ch#Fr_+o(%k-`@Xe5)gc@1R2h-%C$C zk@m#?OnO$HHCeL=qLSS>5{sy0H;%+2D%p)AvCkLxEBZH4r|!y?`!kE~zJ$j~o0+93 z%Kl7}1k#**W6zKwL%Pf%9?rJ?nT%lNOq@MpMB0e`nKV9&0v&K>uX0Mbhn#Y5Q@5Sl z!~M?y9ET5w=ow~)uZ8c2v%}@#x8Z>hr@|EJda0JwSZXUhAq|uuzJ%CAh_;U!^4)T4 znZ1PALkJ(q3+46lE}6ZA*h2_+D(OmRrH{g1LhK=g)k>~%MEPA|FCq32!Xs*Lb%;7z zWiKK25W+$Aj9Nmgq_LL}dk7(Z3GFghYx(U>+Q}GiXlHt9!oi)?c!@fq7WLTkkElgG z_WWav5qtha`=n8L-Sd|@I7@e?=eA6Jfim+u(_g&!;)@ktVd`rAuj<#|nNGj+3NQA( z*thS_bb5y1(65IMRWRQiRHV7ne!4TARG|zLMJ4RdFEJVF9|Y|Cuk!Q;e|i(K&%e`8 z_tDw!<3I1e;ZO1B`K$e0A4mM({i}j1!5u-1;E|wrfFZ%?;DcaJup-zN91P9`C=pf) zYllt4c43cjP&hKgyWz}mX}Bfa7v_hMQYG9fHIg2Z9+&z{uSoAmIT9908>KxGI||Fo zH_HuVJRo?HPvZ)P0 zP>@9sl&z@*L3vt3mPP@>cJnkwhGf$$FxD|2XR&D(80(miv)D8XjCIV%S!|jG#yaNX zEH=#oV;%Ex7Mo^)v5xsTi%qk@SjT*v#im(ctYbdTV$&?dtiR}xgE-D&haALl7Mo^4 z9A~j<7NT)h1MdN^tM{z;qKCJ7`M>$4f*XR{gW=7Chl8F$X7F0@e(=fh_086=FV?zi*REUT?}GfJ`E&!_aERTK zF0@Y08NhMH{KNvs74sA8+6Y(tvzoHu&;_YP<-!&%*$tWoZBzD3w_Hmk!+X;= z0s&W=RH~>}tO(kbtIL18wlp2OWxA%+Y+a#Rs||T3fle4-t-B0E9wASVSqJr2`8uVh zf_s!?$P}BDWXKecs>zTkj;qO#Y4nWGiyL}YcR70M7IVrYanuK z3^Oe=;`m{=nGBgC2KhxHQ^X*@C}fH;b~0p&%1$z5idjxFWI8;)`;2!#Ty(>_8*V63 zZA-A-J+SOYhRr3S%*uuDy;tnL{d5_M??OnXPA_;!rcTHD2YKpr_jV38Ir+o?7Ho2A zr!W7~wL<<5x@+Sc3B+ep*%OL^)YF1Tf2vkt`0#KzNX#XmiBCk6GG&gYwreL7(PYMq zlA#`C1b8)w!sx}ris5ZxlMu=L>gEs}>(8nFNaj~hNZ?q1PW4AJzgkB5H+D880mp4L zBmu{JH6#JYeRU-Bs~2=6^Q&VGB=f5`nn>nXKQ-}{NwyO6v{}5!zuCk(_*bjDWmqGu z32#01)KlY59{Bw8&&ONeSbN`CaB;zc3%NxAnc{~I?X|A9)9n9fNex&@jR+q=MfWyW zgb!eb`=u+w2MDD7pck8WzVHz7__=xKejiEm&UZeN=A9=43=PIy{`dBRyx`Y>PJzmy z2p>SwymOs|n$kUz2p_;=X_F+v2hd7>R2Ja_5Y0O+l}-wtRUnEPHVOap676ARP88q>tWG@NxydtzZ4SYw)4mz!R|nW51>o}>-^A<~fcPe6PhxP} z3wOPM+g`Zq1>E++Tra(X!2w1E69W-GfN1xQH*YZdfCwKzL+L?DgbyIu$#TDpF7h+7 z2p_;v`J61m2QX9_qfAobYbi>ql~oZw07f4W>GY_n-J^+gdMws9X(F8-t@KBA5k7#O z`f*)^58!Dd%MjrMIBS$PMfdXR_yC5wV_XqFfRbKiPlONPJ#UsL!Us^(zsDEh z16b^D@;2f&)`MEC$^$Y07L zd;krV2Ne-MfDJU{72yNuqCTUF@BtiEAO07Hv#yD@wKCH2a>2p_R0vRjMr0VIio_j^bZ2fy=h)H~;i@Bs|<$M_(ggb$!* zcuy$82e3FyS{~6#N?IPVQ%YJM!G&@TAHZ3;v?9U>FiM%Ii0}b0eN}`H5cKX#RfG?q zq4uCA!UwQH+pUT40d&!mLIjTLNg)D54N-{r)xdwel7zztu-MvUiSPlmvLCfY_yBg= z$88ZlfTx`-hnw$rIENjabxOM;d;nDF=Zf$FRP=81MEC$^cwc%Vd;kso2YnGfaD~F2 zq_9JvuouAx(B;n&YUCBeQS+QB!UqtKP@@Sd*a%gG58yp}mMy{uP}8}`5#a+^>}+yG z_y8DvK!gu~(Fa8M02qBhgb#qx2SoS)7=1v54}j4JMEC$0eL#c{fYAp;_y8DvK!gu~ z*O_zp0C=5wU0Ibo$WO``Dvyyx_y9^Ol@$>_fcKPHir657n(95O2p_;=b(1Q>2hd7; zR1@I?*r^@YMEC%n*0XdGzKFAWX+!L0#3*B;A$BvOqIsJsb~8eBuQT&H8d^!E85^vm z(u^*4QfbCf`W+-1Otl@=WR~dB` zB6gKgS0Q3o8FdvRc9l_A!Qv+@eNtCf^$z-zI;i7PpQL}Luhcy~Pyba%Nu#n+$7p7> zH*_Pzc-6pr#w9lk2#G<#azZFgCcX`BaW9gwk%Z`O_VT}5PximO zg;cp^v0AIsZgGGAmX9xEXKLm$?94U({Y5u&R%d{zzT>a)V;l(T25QhDh;bl@cpxzj z1Q8D;#(_ZWGhmJahefH?{v_8G7`1Mu2o?kIrRXTTf<5c>?6qX1h~U*&xU z%u#^unxT!*CTQGIfRkFNRnTwIxuXEXbW5MEf1z_n0j@D*qrP#!!5sydYBp z3Q*Tn%?{?1CU+DJUuk+~p82cE90h43Q`V)V)E`;RddPZs#1V3<cD_Dk(xgd!N0PO6Q1_zpnvdUU+_-Vyk;j)UTQ=QZ_YPUC12k&XXwNt@3R$24 zORte@ZG6o6G<)c;;e46`8xgiSo_yjvCpr1VlWubIiC^91P~QvM!K?K;R%N}V{@^3y$B%E^ZRS90_!vSZ zjL@xa$I0{8N}u%z8SVnsTGeeP#rOgcjih0NtgNgMgjWE?Q36m!RJYSkoG*Iv_L^0{d&9d9`Hq=Dr6%j;UtCDSM6*>-kp+pKNd5u+(- zf7br6=Q)bqcbiER8<<6z8%q5)I7cL#ULC1*9;Im);S=_uCXyDJk`|H{nfELtEiyH2 zBrP(FZ6qx+tsEpRGCLh4EizBLNLpmhx=31NMtMkDWGebdT4ZMUNLpkX1`x9+EP8^Z zMW#!Lq(!E#3RNv5vF}WkI#6xeSY%4dNLpmxlObAUWc?bY@E!&9_E7^s zb7Gb}R^z6d(r$XJ2063SR3_n`VtvZ9jPXs`uD^-=y!A_+8L*^RrAir<9;@+qhwLV_ zyT8!2aEp4B^_(H|VrJ%JH3(*d-NkqBzPv5A8>kJ}kga{9Ez!Q#e$al=3bku>)X?wN zTkGBQe)`M$IQ=6X3-$H-F8wF{551gG&A8J*y3yI_V?1xXVN5aR8LJKC8b^%ZjjPNm z<{f4W^AQuh%^~J!^8<5^xx(CL9yD>rEMZl$YFkaMc2*B-kcE-fyVgu=skO!0XXRV4 zk!s&+H?kkHAGiD4uh{R{$gvmM8|^*z&lHU;@7(O5f%AY9MuSl~UoI7xTB(r=RX)H7Ip>@G<4O zFe7|5eEWC$WqR}xsU6N7s{iGe7ruNuTo=_CXVLGu!kenC z46agT@0kv#TeWIcK|0T@QxCG=IbJ*b+G~U=FZb}-e*OCG8=KO)WT#G@I-D^GX4XpD zRD#lN4I6E1GKMHO9nP$(zEP^JjxIiW^yPMus(s|=WxOFzk>|;)nLkfHR>7n86AzMjOUEk4NNvZH&z+jjYGz7Mk(_K6Steq&4Z#B%dn z^MHBEOtG%FYFUjfw6&hFXe+g{txv2a*4Gw(uzs-$t!wQX_T6@CyPJ)E_RID-`y+dy zz20X2fBa#8Zy&Sobkd#9P9Nua2X8o2oO#Y_C)YXR{O(-kqKbQm+roXs?d=Y6N4p=m znB%T+x48%1Gj7kY(5?N=rCQTFoF)%7-hO+{+a1EIi^5H#HjWxqFsjX3hS;F$=T)P~ zDzIiFyNZR(na{G@W9S#X#{1PP>0iCQf3yDm+pHx5)$}tDpWU>1^X4*sC+Xe;ty_<1 zP5+r3Bk%0&v*B1VsvwZstfd_Iz5cpAS+rNTSxd+H)ZeEZSkq<=Iegdn;hqnhefVLU zwZy&2^MCc3x#XwEgZ{xQ!8<`tuqeRBU{COKa49Gs-W)av9|+Mkd^UVBd@Gz5&JWjy z--kFBo)61PRi%2;eNsp1DGAR>uS=7q&!tt;cIlAxn}kyG4f5@BbNOMpr<^IjCgXj1 zw!B>aRz4t~l2erH6+|$sCzOH8a3x#$M8Oi}Yvl*!7o||SR;{7lt)jKsO^pc=>s2HP z5uG(82@yxMeN zzu`Rc47bcS34?>|?CcEZ{7avtuW32{x#yn4gu@diG|XADqvd$IsO@X$eDyi~##?3+ z2jqigIdp>bow?jO|5?_iO`BR~6CP);142eR($aXp1IvPoQE;#Klr!lReyue_qL>?Mz0;*wHcy;*Ib^5`YrQm3i& z)v{()^O$;`v9qdb^)wDyV~jO?uC3BIWbJ>ON;$|r$79#;KL@p>83?Zrp59yjE@a&Q#;#dTcfAxHh;EH&h(Nc*OaW7lREu( z;~}Ts3q`qc%EvV6J#pf)iFM7vL+Dc8r1!Go%a&z4m))!0_$muB%|$O|5w5IBZ@R55 z$Yk)GCcOzcu)r)IyiB*kCcU%A=hChR%8ic^cRa8yPu%gqwmfmi!!G+Ln^6s_Inj;> zw&jUC9@v&A?s#BZUcBR#@KDLC?KSn~v`65XR8~r`LNYX;r z;MqVVY2jFKJ`fWwcrHvPTu@3%CS35oG+Rp1uGd&5bBlDnj9PMIStMy;iTt%JlC;oT z>86MztwFmKh6uUp9_prT(!2C+x7}9fxkkn*rIgxJ&F|N+d-v}38}#qre|TTPiGH$a zqpun@s^5TaTPK@puWDNT2KDOatM{3$+t0o@dv^T>McJ)ackF1Ty=pQ8^NiO1VBaq@ zvVMJf#mz|1B6v>y2E@*pp;f)ksNaBIbeqX*b5cY2P`ch(@1yf#c!-_5ta2A(=Ps+< zh1j{vDt94v?(Q@5O=?X~wQjW<(IfM5t3T02!JFZEF+6xPJTHd-&jV@wA(fMN`9Jw< z{c=IIe+Q&>zPb9adg<5o>(}F|W>;Nx`V3ukFZ^Cl9mJ3W-K5?nDfUt)r8M1~dP$Zv zUHU@WAnn^N<&~n;YMqpuZt`zp7vj9KbLXbbt&`HQVZ%J>o`^K~1fcm9;-Btr3OaNa9X4ms;xA4Fp^X@{r+pL;7=(726P0K-aq(BTyKA^3+^9rz zvx^_ylWyo%@Hm4OVu|KmQY-qWS)EdW9z%6fGBWZqc5bO99sH*H4tme*Yw2ryOw-)C zu}+<0b*kr9DHB8c^7r`kg07xRN9Vr12Ub;}Be8n!iWPY)s>^p>Ush>;oDy)<*Il)0 z^;}ZNPBB~TFw(6+44uO2x$LRyI1b)EmZE$c)KV_VKLpo@4HPsE+lEhs1H<8AcKAuS zB*fR@58*FiVR)@nL%LgPEuov#PkLDzCw(L>l-5hTB>W_?54xIsr<^W#mix$fUQS-N zag~z1Y~uqZdD%v7HF?>_QZ;$m#zR{2vW-1j^0JL*_2gw6=k?@e8?PJ5%QkK>lb3Cr za;DK`d#1Vc@?{&1E%E4CVj+3-w6>8vdJcK{+drf`PxV~7wOXLQrV9Qoe#0MbAAI}m zO`Hd3lm4{z{Val1-Izmss;%~F(;4r4>@eeIn`2jBJ@x9mY`QLQb$^mf6pR%?%bF|HQg3+b8}fF;)PWk!;Kr+LksoY`t=#GrTvnb#b?fZ zVfi1ydbe8mTafFboOgS8r3^Ssqwu6M-y-Mh-K;^Pj#h5v}(+aKbO z_CN6F_*mg@^AGxG{1QQ>pmxwSK)c|-b^rTM=KI=uZJIV;`{Uo~e?Py%_`&}A83Hk& zR7mk*_A6q5mJI_dIopkm#(ienp;?5|t&ll!;>0%Q>ewl`A#?25sbec-(sN~l`Hvw* z$Vo;&D|@(X*}AK0EUu72AxDoXStrc9UhCO2t!ITydd)Hqe#W?}eMXFZ`}yae&lq>c zU18D1p$9N7)&mQ#AbdlG z%&e>tSu546%?+wzHq`EaXlS#cL(8O7EW9PD=BK!9&Qjn32;W;KouZ`smTAWyB7R_* z^iiXljJn1ub06J{%B1%gVG@@WL>)Z(u*sNAbbT(9zKPHUEO^!T@k58gLtsI2LY;kA zgyJbzZfdzQ>2wvIPJc$z;!T_O)eU{W^_hN_{EPpux4-X@56cXnJt;UGF!~>E4F3|| z8)_jlAT$3lL<2JOAOBD7XV+=vYqq7MvP}B1`iJT-kq(y7R!OzBdUEs1bSEk-mMT#` zoG1XRo5+7wqE%h6pkP6qmbYR_sfYHt;7VOXnuuN~9Q zYh?*HT2H@EM@RiB{W<-0eX{8_SJvjRVFh z11aY9W-YU^+17l*9B2+Vk!^lrMmURK%tG^83pK2}t=3jdAH_mzy|v4V>7z)uJKKHi zm_CYJ`-uI!9n(kA+Zp1Fc4GP{&NwC9N^Wg8qMrwa&lp{ipz=qK$~({ z1a}}F#Ok^JIcb4^lUzNxiwYB)HED7om*xr$X?Rzd@iQIHprbkjF?T>(gNOFNGBd)RTW9ciy~tJCD)B#sevkXLEBaWM_xj48@PmotJgq8Qk(4 zjTbKDYQJh)8|9Wubhg7JLI~ptR4+7{{7eaS`eSJ?sQx=CSQm1SlaNwSWlne$ZgJN= zTPeD4eSNO1gjkb`Bq_w2R3u3u)}$gy3b7^?Nm7V4sYsGStVuX>!jDr=)E@sIDbJK7vtiqGv;_ICS_&7q}e z?mX=DbTSOQ~q0bUKH|hK=jGy1Q~5 z-PDGi>E~{n;*#RHGq?2u&wIg}>Uu8Nd-;!_&bTGKO5V}FXGq*Ge>#VL)2+grzHZ?i z{Ks*6)t=7jSHM_5r*r5Rexo<*YsUIHokJT#6sv*z?SBSf4)Kv0otR)p<_Gc|Ix@G( z2jw#|;v+LUF%ch`(TR!p$c#=*B)6mn8j@SmS`Eo9siTgkbVg90T=dOs*AMAPZb_L2 z7!f(%l2S}0x1?+{A1*yxPBXIT@UgD%oTk?n%TCpKW8|+RN1n(`88LkLa2%)GQyuGX zuM?0d02L{m$Rtr(0__5i(XIQvk=v$^JCQ+2<+&f*Q zyPe%W?(^;&?i6>PyV^yrd&K?Sy~?XX{Pq^!BOZEtL%h-62i_cSg}2Q+=-~`;O)L4e z{ic39pJ7eGxTZ7xrT!K|f#v%MkQ&??GzuOHxE2m3hKpJ_m>4c<;b3C8sD*=x;i47} zCWebzIG7kNYT;mFIM>1%{twv-6EI^f983%swQwv{`Nk9NJBT-)^Dm{3Iy7Pop?coa zigN4E7gK4NKtgjdUFvq6>>Hc4+a6&c*n;%DmaIwPop=0q=q~kL&BwQG3%6m^s8Mv| zDyWv1&Qz*}3-cD%)L+%dc6@k*EX(8a(r3<`IadEl-_W&Nvu@q;(&=Kbff6DIOB&Zb zn>nh^(=F_ySbK5p+F~PV)5a$%A>ZiISD|F*B zF(b)ieGVQBBQy{jROY1<8Yl{V;xmKKl%vXc3^tRgZE)rWPiWd1Yixx~}g{O-sv5o7!FTR$k~gGqZz==G&;fmFr4lH`)T{5NBOAxb5Kz~+ zt2rG2+v@bGT)Fb}u6rvy@PPdQY2bPF)xY1l;xK6~efo9j(~CBl@^$(UJ1DI|RJlVR zj5s8GTtjk5__K!Oknlwv$su7`1IZ!bWCO_|;q4}pL&D`Il0(9_7Lr54A1ow?g#B#9 zL&8WgM=Y5~iaC-)!YVG3L&7;O_>hpDkxVf!-|iba4zH@WBpgncH}v@nHc&KK1qO8v`UKAhqfZb4Xn*P^vZ72^z6h2b z`r?Z83?0Htq=TxC3m$UuJNbGLzO;sZIqp zGtM-w#zubyIlijRvRtTps!y zl91dpGi4!=^66S~V%UX0-d#c$}PZi`7FQ}#cl3f&T zU0|=Xc{m+uj^ea*IypR?j=7HOuyi^Pr{i8%b9=diT^>%yR@ZmQs(0Dd_g4?yJ;NK} zP4IX)9VfleD-zo-hto04xBTh;7ybr+w|~OF=;N9|4(bQ@2VH_^f)|1}156E^U`_B{ za5Oj4&jsG&~QvRDf}$N%Fqk*!e7IZQe~+Qjiu3E(xnXPRp~tfsxFhh zk+5G%wh&-|oNOULfgH6Ev{D{b`YJCecw4cR1Qr*d4mpj@pYO;yyEYA5w+m04Oo zR54d|)g9_#^{iT2yHWd#hIl0!jg?l+_h#XAw6}FT z!+zD~;dJb`1G|`Wox{WF7~sSjCkv;8rnYW%_b!)*)A6=@rPxoqOXJ~mysg>V0&Shf z!|8~N{i1L>=IX94R;z(^tBKWWVBKnBwHjErnpmxdlV)g&)oO@2s8Ki_F$XmYrz7T| zM&Wd@ZZ)x54Xj&DtX2c-Ruik$z`E7MYBjKKHL+R^tXoa2Rs-u+6RXvb7AS#Otp+9z ziPdTl#UZ8*VQc7zr^DhB52vHMWJn{V2@(&dlr_qC%2DN#2EFB~3D z2W#f6@80k7a5|>Cj?2>NJe-cYp6Ye*p7eM)9VlSvsAE)3KGNnk=2p!|CX*7)m_V{80fDX@sMltg`lZVqWfF^?D&5unUPDg<$S>&X)csLzz z7gcM<&6?nJKHjW}i zzdl*%Ih^l`mHuC~(nGY;GdLgGTe_8Dy=rkdANE^;Rm{H5=5Rg?uuXfs{jtsAd?>Ib zhtc^soDXk1wzI%l=WsY5(p<%D>2`8CoDXwp#&x+*t_aSDdp*tTE zTV0^8Q#qUuX_}(7)H-P#&WE|0tL@MZYaGspdv#6kr4QCQoDW-dUq7wK6}#w8lGO+! zuGqy%BQz?QLd7np^Km#IuCZjRzIDIF;e42CIaWk%ji9ZlYpZrdZH?f3SZRB9p8c!M z;e2TC=uU?7s>9)Y*zW{RG50!`!}&14HC+){4@RtyA+0ZYc-#9|J1N2Gd>qb)t$`n$ z4meu%uOZm0e?&MTVxT4@qcrGZpPsUCmHmRXLmw`_(`#rd_9TI3EURrZ!&tSmSU$6ljuO zUB64`a6Y`P+ePVg4(CIfp%^WVP6mhbVXomCJB-7B$~=g4o>=BV60Q1I3zyNVf66@I zbUrTgV3=*$)9qO1!8MNT)OTW;2UE$zvBrrbDyZwKZU;Axs9+_@*m-UoQ9*l8_cFXV zqJsTi;1%=ZhzbVyra#_~BPuBHrGO1kctizn2X?R^h$AXU3ze{C7)MkvH*~`tVH{Dx zy^<#NlH!O8wo1NqT8bko=q^XpWe(@VNja1&C~-su!xT#)DL~kJO(!vMoH z#tW`T6d00O-Mq`>a6Y_k+U5dtoyp;RNV62HrPayea6ZhnTx*AQ*y32o+AR{EaL4AdOXhxP$uBflDOI3M;0K~OBbF63}N3<%9|d{H5B6i!D$C`r{N z=46WCe25E)BRC&;Au)&Zfz$aooDcUZn$k-dtZ+CVc#92(^P#(Hs3X(~Du?soq#CLf zv|BU|=fg0~(xz))XdKRmYjj={5W)En*91gxKEyQv5u6Vz4bR9kel<9p5A99e%rJ{E z|K>9D8x#A@z$|86XVtXsvD#2L9h}a`;e05tB)htOm(AgPc-yw^EBc3WMgJ&*^Ig$D zOm)2avC83mC{QJ>`W5|y!}+f0A6N8`EBeP3{iCRy;Qw)yz!m-DivB_E1iYN!ivDp$ z|M)Mce+(D(k6~xX+a0lKJ|Z|x5t}B5;50>Sn#08pA09^IC_at)Us%cK**I!LS+XI3 zBWd=hFeJ?e62utnp6Ov%+A4P23~j>ouz%iGF|Dr@G$$7BBA;=oHGd*$s;^;4 zn!WBn<}|F29eoQlSopW91oPOu`yUw}J{_%eFhkrcs zo%ej^^?ALXFNUPK+|j;>B58U!4L8M*G*37i943Un{3k=wG|VF;%@L>QssrRLZJ5W9 zG&M?YKOX#&(ytBk#!`m8?_P>mzv7&n?JnKlY|jHftXQ!E%oM)VZMcc-jZ~nwW=&uB zGxrrActH7)Zh>>BUL1IA2y2t?*zsb=)ft4LAqtIOf}tS_&BZdc zvzcM^rI!j`ddTDiZ=zFNTzqT@3rGL>W5SO=nC!xfLHQqXdoHW{PVTY6ShN@7WwF>P#LHsQPmGtv z;)ED4i^T*fUKWeWa=a`S%nf|PDz>h$lkM_K9Rp7efbmuav4fI*`iZN%761JeHrVpUVoyRy+$A%DdX2eA81C0tC z9w+8ZwG7tsSS^E6(BEjASpN~bXjiSf#!sJKZ~Da93l}cDOMg{gFy<&3KwHkvX-Rgp z;sxVNa5I^iRVOc_Ov$Bgo(W*=j%b?je^`*61zMt5M*zlt^HIwcKzN2 zBF$9GXz*-<2Gz73602akz0Hp{HMf%aqC!edxn@m#{PD-P%TLpSWEl*4XscF8A=u2s zlIwvTt;W(0u8=~$&zUJzE3_oo%r==R`u>f232bJ{l$Of;+wLygnxY<^(u&(<+u7Ny zH@#uXtRH91x+ojUtTYPeji`_^X5eh)kT!Md)Wr%)bmzP4t2e4V-i{#O9>m*GUaOm+RR^P6d12*ha7!n{r|@2QR98bwCv$XSoHyN@@2&DS zdHLR9?@tfq{W^Ygzk}by&+wo0r}~rT`0x0&bvt7C*B(jQ;J8RSzj`$^qGvbR?O-Lkn=pRBic~)XV!cofSydZvDixPbF z2Nc=7R6|k=A)kZeIS}$WIG%%Sq5+?S<2jHg$E(qiuEeX+QK-bL(UGaftI?6D#jDYg zt;MU+k*vq7(UGIatI?5W#H-PfZ^Wz7kzvNG(Q(?0SEGX&c4v#6pHyVQMv~pgZez37 zSY8^7CH5M7i_KbNd1)-d)>u{=TUnU@fcW(edi?q(W+!|gbHYr5u)#UYDrZ{e6JZ9` zQ>#}$mq&z|mUK~dfePX_F~ZE=y{Gn$X19_Q?>LCD6tk%5x|pFdT6F1Lg*^XjV?es%9ZL`xf&U%ue-b9rR%?&Upu zZ0CXoEUfg?jX*2v(sUeJO%fs7GIlU=`{`YS^F- zR-qnkP{+^O1ufd34wl-RLD{?_4?bJoVB5Qe(a}gZ1{q_FX$IyQD-D+LDKvgJ%9^!I zG&9?q_m~6BOmm7k+q}#@P}5!hE|F!<nu=X+OPY!-fSLPGu8P<|+H_jR(pcIB+Vv>z?WMa+bFF z7<{vZiw%6Ug^LZzZrrPm95?P&N1DgI>cL_I-)!Mx1K(_Hv2FBs`-gm-_Ae7^3QdJu zgu8|Q!UzFb!fV1ZVJ)#;4hTg8L?nrg#5Urc;sfI2;xpnaB9@42#4X}?;?Lp*v8vQS zLWMcDgjh9}M7E13+$dkU7ev-~g73I2e3%R3=ba{|GMxG|mlUK^0%3sPTlz*4Y zDz%hmN_*uVWq<+}!kcRIz&G32NK~tb&l%Zkk9+NWAAJ$dv)sSiDLJcD*{LtW7i z4b-_0;;r$-;Ve4N4pVQ9r;mg~$1{E!xJ*B56;E8ge0lNlj1r{Go;@co>Zx`oLzzY; z;W$GPoZ}fIM~=i;I$L$0L0FmN8C!`f)7{u%9?z&!C85e>vb#}OX4-k9vRU86jb=QM zicMxbkcu8wJdlb*Ry>f35q6gSn#}^K+j$@rPCSr`SDbht6%E{YAQkVsdG6QlPwrW_ zqF2{zL2OGe-5cbM@uqq6yp`Uk9=`Mnz2CjEel5S5-`>B+#{fUmpW@G^fWmrzr+?7L zNk37jE-*-6SD~LUT)-qDTUaW5Bzz(47fuMp0_bL}|>)*d#|AG|4J)Ki-GTN!d-TG0Mn&IKvwi}cA z^1K?9;JHhET_wW%v+6GO?Z2&5Xs314qE;$w)4tcDRx0$>AJd~&D#Q!0A2INh@uCs6 zQlWx*wHdWiAzF0GtW<~>V83l4UVweGjl1jz?WmOsq#W2$D;0)1@xE)EbHbtz)^my% z+@SCJN0;@Sf><9Ovr@4P!D!ZpvBEp5My*t6=Z8h7%u0o5(JAXWoy3by8JyL?`cAD< zTeT`kq37r2iU;NSb1LmiAh66ipmkb38FZJ~77=BjgivJTXE(F~<`l z1h0%_wJ#w6k6JoPfVFTV)2jFS-6qDh!3pryu-wl z*^{4?BqlMY46Dm*>5sVWLgRw6)%NV6Z>Y&OUbUa|-;_p@csa}8N>+M=UV3h&N9d*J zR(gb9dTymh=%wdYdW2qjZly=)rRP?9gkE}XrN?h_;HB?gVx`Bk$}Ht=Wu3A^;Z}Nt zUV3h&N9d*JR(gb9dTyo1XIkK;=T>@zUV3h&N9d)$)nE@kbbGb`y77&_!QfVUgkE}X zrAJ8`*xY7*Z*nXBq|i&hj~;xSA(L(2(+nb0j-IcHt9HB7tY@sVR#D=I1d-Xcgibk= z5+csri8(K%zVO1fCGl>8Q(iBKZR(3ish#e4N$TC z)c;RKNnYzl?T@djdmJ91`d39sEau{nc3k^QWBI8~E%n=U*6vAW>g54TX4?|Rk{PXk zW=+(OTEFUljbkjC+)QH0oYR{aCxdq8zgaT5nRI%sJJK+x5lbdFGd*{UZ31*2%FV2q z`-aU?G7DyWZ*!DPZsxpa=gnhwKXQG~@1HAf5XIa~VpNQNfT3erQ!s0m^Dwc?o;MM~ z%Q(9X11%0OV>W;0@&}94*RY$|?QG62LkKV9>@tM#GR`hT)aK7z{)pQA889DFVm<@r zBTCF?zuQu4?ImT!`#e; zBj=4At{mE^k5LZkKPkW8!O$`5(gJkMDdq3iR6mA}S(g@|V}`1)_o3s?x-^E4c`hsO z| z*99##?QzDCS(irifu7_vr=a4$#z%tqfq6An*+dxG#PTRmdGfvw; zGb>8lSZ-mxwbMFiowO3|>ULwht&OgBKYO@6$NyL!(RlHg%zOEU)jN=TM>!b&zfyu;>S)Iff zG6N-}`A0n&LuPdnJ)bW(4j3};B~9-cW5~QLecy-}GOLp)<*6iS-#4YFe|6GPdO`1# zu5U~C6h+<7lQ6Y9iSQH?K71fUCUA^xztLHc1PVChXTvXvNwUdZ096m_9+Dp)b+{r3vTt%0_+T zMk7#~Fx{AMtTHwkfzpIJW^=QH*~1K!CcI;AG!uj*t&A%x9RhN28_W0M7AKRiuixq|B z<8N4YEam1`6w))^P$*K%Po6w^MIqfGg4L{2kgf86Q!I6KDg6U1H8=yPuE|)u&j_#3 zJ(;jZh%P0RwQ5<>rG(kmax1!&MzF2a)n4n-qFhl}j_z4I`LBB`ybWHiJ^w4aU_J39 z7U!&AJxQiaKOLV6>?^;}naoI#fWJDW&bUYyf}4(QkB?RJiwI=y(c&Y%;7 zlBltFED>fF=MYb3B57D(6NQTLWU4OCp+k2&x0_2}00;1q`-QvT4awB#;`Q-{c_En^ zd%a`cc`qbWV~9V_pYDfbYH&1lNTvoyQ-@?~a5QyDrp7XHt+-tb$<$~g-6=g#0(RkK zYHX3dlYW*$GBtY3kILg^E`76o1cs)L?jtajBD#-IR%K}Fa35i|x?GL!Bczy}%`xsY zcb>b_W%~$hy+`*Ey6AoM=sv<;{g@u^qxUz|J^$gnT!KAxH&|q%_=B|!PEWG({B_3G zX=JvTY`Bvq{x)&qhgowcGoFn8$}1&2nIES6^yyT>lQ~0|ymPadMD;v(5<>emiuiO8(r*B!iY5 z`?t+z7tT68LnF=c|x z^?S4yW6*?KZN#AoyKKav2@g4lLlb^=5QipAbPRw{EqU1aQ7(`hUC2K+bnzk~yM$m;bXY@>w4-AkG-as#kS?QmBR`A&qB~enlE!lW>f7qBd%O~=W zHy%24>d@^e`8_KRWPKPqT`z&ob1%!q;@y`>G6qOmt&maN@ScRb%iMi;_l%z#*1vSW z^FQPC7TgnJyu&UE-*@tyubrRhWjc1ypg|wDAd<{E2dXksc~%+fKJ9WM1h`M?oLkA` zLgh&WZgg}Ud z;6w<7NC-}ZK!}9kL+gy2L7gh&WZgh0tj zT6jTtL*PURgh&WZgg}Ud;6w<7NC-}Zz^l?*(#O&^Dd61W8aY5ha3TagkUy8dm5<8- z=N`8yy_83kr<8zmj{tNZaPIN28XzG!5dy!d0TO}}A@HmgL?Sp50wEHD6Cn^HAvh5N zArgWUArK-VI1vK(ngJ4m6Cn_Q?gP#};#$!u3vsQeL>PX{{@C7T2b_BZp!wyLLfv!a3TakBm^fyAVflNA_PJt1SdiuL_%;P1VSVPCqf`ZLU1AkLL>wy zLLfv!@M}zjNCwyLLfv!a3TakBm^fy;5X@V z`6`*21vwD{ArgWUArK-VI1vIN65^u5h!6;o5S$2s&(r`3!HEzEkr12+fe;DtKau?T zf2Oq*ArgWUArK-VI1vIN5`q&U5F#Ns5dt9+f)gPSA|W^t0wEHD6Cn^5VR0e^LL>wy zLLfv!a3TakBm^fyAVflNA_PX60TO}}AyCGuVKuSZS=}s7gutuTTh_+gy2L7d{z=+IVV&SIS~T)iUAUW6Cv=U7$6}y5dt9+f)gQ7Mh=h= zoCtvs3BidF2$2w+2*Itn%5mi{g%crgo7zj|NC-}Zz*p)Kl_McI5dsgh8x?J?_O8Z> z5D1YFoCtvs3BidF2$2w+2!S_^013f~5D1YFoCtvsiOGqW2$7hah=~x1$%&WYurU#NCJiOTVlB-{`i~!Ebb*(qGg$5ffkONAxo~V~%qoCLT6M8_yeajdu-B#KdpL<>pl; zLt=6wCPE}8Ct@N*Vsfh^c8UDk-R{;WhEvdELB+Jk6Wz;Z^S~ z?_+P9_r3S4=X=$BT;sR)@9_KjkNFdQ!(Z&<1OIdXTmQKKmtRE?g_Z(t6M6}c2-LtT zED$UqSHM@o5#fwbLA+XIX6l|I9u`N7&x@Cg(qe&#-^9zMtEB6sRH?h9N+TsaE6tML zmexr-q#q;(TE>;~werpKU2@PXjSvaJi4X{pm@g}gh=~x1$%&Y_R~<~6-3#g)Dkoy% zN9s!{r`6W3*EkUqqqOI=*R>Ve28|OjQAV$!H__Ya-E>aG#H;#S`p5b<{d=7gF>#I2 z+PK5$YdmIfA|^gCJ~ucLlM^v7KlOr*?I*W&`(bn_UTK~>0hjq@XWdH5nEY&~cb8;o6RR3^RJEi(ZfW$1- zKZuBl5Q)i&me*{R(QvE|%EtKjX0TQ!R|B(I_{bN%^|LCxNyH5<5H{ZnT zuh)CMbqYDd>QO_;4Kk(NUyvV>pCatWT=`vU2m!AM;d%&@L%=ISxE{jf5b%nSuptDY z!<|z%z$-$+h7f!k(Lhzr9>U}hylt*CcbH*A2pB5k zK`V%UerRE<73v{O4#EBQQ2S{+YzRSA4`Ff$qIw9ELlD(Nm>hzr9#Y1u;UTJrFgXNK zJ%q_2hyK<>E+i%uXIpLp4CVPBCBRQSxT3_J2G}kdocIP7|f1z!xg7 zSYfUJ8MJquZeFF8+^QAhxl{>A=Dmc4B%)j*na97oMu`Zj2!bX81XTn<69MA)&ezC@ z-#dRGBYy9En}Ybg^H&OZ!Fq7-{IH7nz4LD>;`h$aYKY%EU#TOgA_$rY5L6KaO#}$4 z2!bX8d}ACn&KY69I^y@vKbrW%EN9iWf_vx3mgF1YMPA5#b)f9^8?L|plROGp{hF8jS90>Ml331?GE0^O zt^`I+#^_5$6{lSGGipMWqJPV3TvbCTt8rBgp{&MLHH5MnSJe>8YFt%AD64T*4WX>Y zRW*dN8due*RxOa#xT=OwR^zG~_Q@;}7=l(YRC!wAvKm*_a89YDMvG<;%4%Fy`?p(& zM{rr~ktZp=zbjvF+_*8wMmt!?>-r@MihfFGRd;A&1R0pg2CKTm$Hq3}dn06^;|{a0 z`IyP1&IR*|_UziDv#8Ss%5KWkWg`~#rKB(7-Lp#^#JguxTtvHPS<)BLs4q+UA{zB& zNnb>xzAWjBXw;V_eG!fNvZODfQD2ty1&{i2hZ{4vA?k2rNnb>xzAWjBXw;V_eZiu> zbL4mAjq+~!kbGL6beU39X{y|!+^zKQzI`!Wk;)S@DZKrVVkn3Lwb|_nTB`Be6XdG# z+mk~*wTCsjb2&{}nsPMdX)4fE zq^U$xnWhR&RT_cj3Yuy(Ni@6;R*eA#p;}fAA*;)IFFN*)r6fsdNHZ+z>K$|x8+7x8a1>4B9;j|_$?AJESl#8Ie z{({Q;QYeK~APaZCk^06P`%);3dP**%fFj(TQ)q+qCfh3W_+#E(90U|lCBU%~Ayon# zD-lv9z_1dFv>a`-wpTl*o!3xVudm;zr|I|UL-cX94lrL|rEk*n^~3s~dU>Ocf#yaB zqlb}UJZVfd<{0l7*l6rF4jHG7%gmZ)Q}Y%Rcbomq5oVV8nz_teYi>7jz$`LhC0UKE zHrAci0~Q{q)a@(Q5^IgM#rn?r*}?^@s@=d&u{+zn?MLnLHeRw9+V9(Wmv9*s9n^JN zI31mIXOJ_-ndZ!Mu+sU|`O+zLes_4;GupfNxC7iwcZxgPUGA=TvC}>1o^%tv>Rw~7 zt=H8n>T{HW+xt?;3ofvl@Lt~Y-dyip58Ut;`rZC*1n_~UYL0Th#B=pH*B?t7;9j6s@z?TYFR+ui+(aq4vI(r+uycq@C3& z>Zq%?&^zks`rkJ2mHMapmwKW8yI$6)Wi&I;-nhpYU}PFojM>I=V|~EGNHnXPjm@@Z zR}=lr;pQYW+gxgXWPV}pH*vybjm=?UGk9ZjSlE1sH#Vo)JwB$hh6f5~?n$H!AeGzw zN2_!;)pI4clY6f_Qc%Bp`|XQw?@6Q_0M@V1UH=f#jdF#rggtvVY^b+kTRwqn_PG9m zF$Gn(?V&VLf$O`}(s3Bc-lJX@B8p^EN$T|D1g;AskbIdS+$NWnNw`h;GC{aa_%cDT zO&+Bm!b{>p5$}t6;@9F&;#skxR99*tp`(;84U)!4)1-OQKMK+gS1?J*R+cIsDPJi2 zl@m&_f-BTywUydM?V}D;C#W-2EK+mS&FWtDn0j8Vtku_Wqn4)Krw!4@Y16g&+A0m3 zw0!Nb_NP`}ucJ5DJLu>^XN4#AsrnrK9ety|Ti$Y$^y6G+kxj`c8Q};`^(8cd=S+ADY%xmx6;|-wS2Bvtkz2)9| zZ>M+AJLx6*sO~rR+xlJoe*SQOlArBkssEAxg}>iF;TQW?2+0Ck30;If!Z2ZiFhf`* z=lj)=Y`5*eep&yO~ifT5OJJ1U7Rnj5;uwYA~+1Jj?`T0AoY+kBs?iimF7tA zNE@Zy(jn=zgv;cba#Q&h`EI$tJVMTr@tV9$UMp{x4_vBAMkA$-a;Nfu64WGPjj~1g zPWf5kHOb9-=`1Xjo}Qk&r0!j6k9#SIb8C7tb)1Un>U?#T8UXgnYls8(=4glm_L}Nv z8DMYN3VMu5o4xm5b~r`Zzsi>F@c_m1@X52EeA1oDeAu1+y3F=vs8(9{^vU-3`n85X z0ZB$5qm5D77-B3kKD9R+*lQd!ICY3ahcLt(XHGZgo2yI?9m1bxd8>}q-0EO)=uinz z>m6&OwcFy*A=I>++PBzu+x_X6z@S5jP=`vOLuljNNlnU+JI^>AI)p9Gch1kw1*fXZ zp+o5HKI)ElUvd|^96E%MI>ezv2&qFHI)soq#Gyk7sY4t(gpfMKp+g9%LmWB;MjZ-2 zMK+6v{tnyRQ1Us}p+kptnY6mdto`h>`26$FOH#6+Q;LVaef#$4P1H8jlm2nf;=u7; z?ixO_YeSu~w4ey(x=ft~Y$(@vyMnh%>Uv%_epE&qj#67ChhGI%QEyPos1Ffo=tBb= zh%^)}Z9|+iv`s^tG}Ko|oHTS?$6tE9v<-36Pz4il($HKJEEgCpZ9}RRFKxpPD_+`$ zIB95~jW}s&sDn6Zh_W(q($EVo;-sP49yn=epcgoFvBCSBG*q0{aCIl0a&4gFLk+(u z_2lf?vsb4P8&?47GVLyTg|OI%?GJfxh|Hh4!o#=T zQ0X(TihsRy(Ywt*;^B<<6cxX%kSssfXD)r5@mX_YSlo!HO`o~+ag}(Tm@0PZ)>f}q z!{SD~uC7p{I{;0zIBg6cYjN5b?$G13F?_4XX=8ZAh||UnoG}t+Q>K4$p(u_N>*Xby zl}&oCZZPqn8E@*uFJ`={6Hi<5rp`^wmyqgp_wKd(=G=U9y_**o61Sk^9D)-LL%<<8;V=Xo zf)fryz#%x{Fa#We6Am+#DaveRxw2ltPUYYD6g_Z4J>SL7PHpmd@=V%w zb92g(=6|hrzcy5RT6suou}m_GWvpeat>@ zS9Va}xzR~;?sJAX|gFZie`G!RmR&O&eDQDMCBl7NN6`$C@ZweXX0R;Vb}712WMD5i^p#4+MDah|wR z#HZqyVxjoESXQbfHIv#)xJMcwWlB?|+0t@py|hz0a8Noa5yf?8R`>2tbw4Ftudx(; zCk=PVedWjGu$LLp6dnuVA)3NtA-qjz=u~jE+Rl*GyLvZmTCeHMEJ|?Sr7{*=(X00{ z5^y@5VAi(F$W}MqPr#KI(i@j)+<38CLZG{^P`#j{tadkc4fiH_*&dd9A9-JR`@Iuhv3G@^?4y<6#qZ+}^C$Q-{6&6_ zzjm{~*FWZyT>nCP^HI&4ANQ}SOhUv9>E(!ZP~-0d0|Iw(a9}{-E)LAacvt*HbjV%I zu0a@V>0qh^f-t?1Ua_KBkzF<1Dm|^ftQHwf38gYQnbz)sm!*%J5@um?a?hR#J?BdA zN|Xm`dQfU4C(8IvY9_amyR-|~y2zIg%YVv@IM3O-$WWeCrYdukfUS$u%4KRzwW%7g zb&;jMrY=+0ssURUNm?VVjdrINuywISTcd5!zS9D>E>iT)dT;$veZ2mXzEFQ(N1pz* z9+1%)TNeRbH(=``fa?ZqU2wQAUk_|MAi5sdc0hDJuJ}lj&St;0WK1N*y(7G9w&SaZ}xY(BFRYqIb1)gLKmcR&r8~&`6V$ zpJ|xlkC3vYqG^B8CEZh}=`4TYkG!e=5ilUiSR$f4b($jiGku;hIm>=d=lw7JIs%Aj zQXzc991u_>Kn&k7kBeXo-S7=_K?GyyhHsdcBrt|<_=c$~gE4f&H_S>IjG-I8VcIKT z4BhYzvr|F*4bx8rW9Wur=Lr>zp&N>w6Ewud&dNICV&{Avaj~^xwep*yjsPPc2<4o4{u@Pk=q5dp4W=(6$w_HVToulICDWFS`5xopeK1T z_?14>oDU@AC+;CQPK_n2R{5(y{TlRT=k{e6w@;mJ(ZXzj@4x^4a!1+3a2*Y|5U%4X zU*D-S(g{8MBlCPlI$@xbGxSM5F^^rb2egxsd5m^)sc?MfZU={))0Y}9o^d9**)Ep4 zaWW2CkuVk|<6yHFC*$BgKTgKMVLwjB!IMIqjDyR>I2i}8iE%Ox8cA_74%SF{5?frS+ znA|E=>Qxz;N390mXeJD2t<&8IQf@RJFkY>=ndAAqN}P3x=O!j z%(&w8zqh~0L+jl=ezc6q0c)7y|`06D4rA(B~+IhOKqjDQa@?9 zG)c;quvGd;`a;?-osf#9E97Ju^d^$~$iw6b@(h^~moIFV^V>0{v1QAPEgQ|IC5Yr? zH<=xE8qFR)TpZ3&ReNMnX{r1Jz(6rMJqU(^UcD~%sxpkQMO1&|4+P`n&!2D3$2Z@6 z^M@)wJ}7n2pen-&zj3QJ_VJ<)GYKI3M@CW-{eL8SY^NmzbQVAioQp$NY16cM8dhFX z>lsSA774S6Dzi+O#U*9dxZCJ&j4-kcyk;yj)*9Q514fYnGs#3FvyFMD`GEPj$$v3e zV{S3OGk-SuFDAu8XREjMs5Rbt$y#W=Z{=C|+WN^lYgM%C+AZvkcDjv0_85DbJnE~>kY-L`I5x1T%Q{ol4; zHbvG;l|pI?D_NNxJNg|#PY_+O`IW)wK>hoR{n^oGmmr7@OUVW1hvrsupBa21|GT)$ zrOy3`BvMK)C?yxDLsj;5WU8yxQgXrV-u>QC?`f~pxvw|WOUVVLLs0DY;Q!r|-~9$&JEDp_JTMN^TUxh zRgkYH)QBwil>bW>u$Jl{|A+LC;@cE3o8F>D{vz^)%qOdsxR&`&ZYO#~-!z@`XR}G6Jkf09wZNHYY6ypk-{ZIcYfnEu)*m zNy`Cf8N53;tj@(_E+;Jqpk@5!a?)}DTE>eWCoKn{WnArZ(sBS=#=AZzEeD|G%v1qA zFYi!=cr-oB7LOqNO$F4hUE2rq_E8ws2bGAjzOc2o3U3SVB~ndc&%~Z(diH!z_+Fq+ za12W*5{j!|RYI{zNxATO+1bJokl7h$+O%miqAF{oV~OO}qE>yyiWLr{*o+W*qE#!g zgktlANbSw_$F^7$_`Ustw*Wskc>`7l*$g<*keSg>`=^s)a@2h+2NX}%qW!|nl;&qQrR!~ zR<%!AUOqWFA-QMb5|LSwxFZRnC5bzd5L%MBBMG4;i8+!w3-if3U#?}#mP7NWR=dHc zlp^y7Rr#w*m6z(U0?L(TR<3OAvgk1T!aF0(KjKz8MlRaB^2hJl|JVNg6^bajg))DY zDRWmobxq<4pF($I$BsqU4PCnqElZW7L+d|3>iOrN+h4zc_%{`ji<^DOI;oc|S%M0l z{49iloGTy8(yuuD3asBbsCQ=YD{vZk z00S2$jh!}a+FkiXGpS-A)#z@h#z-S*k;e{$*T@Gg^8e3)AK5+b{^bsSM`vAwuf6u# zo}a3AT0CytxWPp%hLLA&`r1mTxM=a>g$11!mn-L%aBwcJ%FPvXLFw_!{~Yq`{(`aO zr|qMWrK;75sWUIe~=M8^oeq5+4LvtYzeXEk0sl- zZNug2&FWq1gDUTle^bSW>Q;51`pYE%^-UUX|2rJSvq1>ML8;aeN_)>A{7m*@dID?b zv>Q30%!CPp^|!5c7K;ff`tDQX8P+Ym-N@NRMWN$%eFvc?!E zY!ut^3<*L82G5WnWMJ?N2|@-2&yXNwVDJnHLIwuUkRW7W@C*q;1_sZNAY@?h3<*L8 z2G5Wn+lyyNknG1ZB*^i3hUC0oS*S1ENY&WFeZml7oG@LOFRT(a3CI@?3x5jb#X4eh zv4hw{M27gJI8~e@z9ViFcZ-L_1EtA|W*)p?exVbAy#P^+PW! z8dI; zxpK=i${V#-wLW914zy(&p;ewpFGu8pmR;E4sb#016nw3oHqNRQwYpjht)rH%VURYa z#Cf|?`&9cmWaV2pZ2f7Kx9ix=32V^9&am;MJ=LCLzhiH-ciV^T(>5-nBw|yC)%f;zMmSjx zUUMQP&2Ey5Ms6GTPWJ(ql{B-CW<*PxSw}NEd%cN%G2VO0Tj;&-<#{K+_I~otdKo<# z989lNsS;ap=P29k-|8#=KtE{v!v=qs@A{|wGC~cZiO^0!H{l^c6DA9<3U3J?3)=*I zFZ?R_LN!q$-S{f8uh{nC>h&95SFKa0P6Nd^lta(a@u#JDoA`MWfmVvIOJZ%Hl;0ci zxmcz_v!2&gqvKP8R3tU0C-}OgIdkTCEIEB$5=A`^+#o&DobpcBB{gc)uF=Rky&Gm{ zXU~$%MrY_neq9oCT$g+G)mH~g->bi>tfmOjo+4ILgtz5&@(!8z6tS8j+^pQCJgD%V zB34s`tr4}G)fD0Wh})0V6yd0PPOYTzo+4ILgt6KS+8Y}0DPlE6D5uxfuh)4`(J1}7 z{{?E>MAI-An;)2;oA}l|ZvJIfu|%t-b(_`8!XwsG){E8x;$`GoU(t%h8LNVQwS9vv z+db`v?a}t6=k2-nyY?rxV;9)J*%;feU%%^;=xFkX{l8Kz*F@YS3SLjI_`$>Z`T4A` zxoX2gve)x)BI$d0i7IwqJ*GIkn`a}NfzteHKVPQEsFVFHn z^9!V-{y86&1l~p%lo29mBMe~txL)Km{-BHy8^nML$)S+wCIwVT4uwR}Mi`V4BASC_ zF-Qb$gh3f0f;PgSj1VCel0zZ!uFBg8gEB&-YP^jwC?muUjkgg7WrTQ852%nF3W;Cz zfC|Z>ka*e%sE`Z_`D@l0%9S-Nq)!>JwC%5kXtp$2!3LrY8?0ah(S{9Huz_g9#&1?N z@6a`bFklTE_pc%LMAh0kvu4feWg8xA+E{z7ee>G!1w?JBom1B*Y)c8XMJ8+ut=|vr zGS2)O&efYJBlXnj+N(F(8#jUgF12$~KTA!m?cBff^y=EHt5o@+O0O-;moKlKQ>~g< z4YaL$IdA*#IoRR<;76-iz`9tXRV-j#EF2oinUP>!EYT_!ur8Kp6$@AwOBAmF*2NOV zD}Z&e1ZhbYmIUi!3DS}*EQug38C0==b+JUNSirhiqE#%=<(YD{iUlDwk~1U0kqzG{ zM-|SDgrs&-qg5;;Y;}+Nqk24@US73x%F&VbxO$a#oyLAXP_>a-@cUsuA9z}V9{hgT z&j-3bQxD55E7*swwm-L7nWZv?h#^(0WzlQAyYaluen%IGEIp+J=W_3Yd!Ngr<8Za9 z)h6E{Gn&gMpS)-IMp3ne^tn?lt4Wh4b$4ZT_?(KJtC@=V#O|W>nf?3sua-p*HF}z+ z^Oni_?Y=jEHGLD+ta!~S7F+R}Q?#_>HK)k6<29$~8KW>zlBd9l*PLSHC7|d!cZbVr zPLbfnYfdrKi`Sf@p&zd~#cJ9t-}r2^@Wp~oLa zPMR!*HKzs1t5R33s+QHfdGlRag%o9y8_R9wu5v$lxXc>2!7I1J#%=J*?XYnhymFf( zx^7g{RQCw7va%|qKm2gQ!?&xt@f;CZYN$=rU0FWyCP;2tgfkQZt&q-mE?a3qyrur7 zCS>g2@9qb^e=DS4cA0n?V=g6Rv@zRjYbh-BM$Lf)W2%ror_7u=FPLwbi#3}HJ-*d& zT>DFle#s%uF+QUs>~-R`P6&IQc&!t{UMF7bggD3eW(#qS@m33Qj`96A;vD0nHo{&f zUh9Og*NN{EguPCDmmutQ`o{p;qJ$JW`&LM&uM6zE^pgpGF$kM+`7Z{w#rV4jD@6X2 zVHfM`)F#q_c9Ps+;>3vw$wP-G482tvtFjNWDv~ID-hV7%UJ{Z?M$VOryrx^WY$-@4 z9it?CnvhH(G68ga{0>-4|#?cu?cjeSt=VUo>9b7idIyTIbb$fkuQ%21nNi8WG+w zcy(W(5#f51SN8=P5jL2-x-Za(5LEXC8WDo(zM#1eL3Lly+=stxUfmZo_Z@oC;njU# zIVC{wgyhbhJAdPpacj6};2ScT&rKs40b5bQa zD)!(7`3*TL_Mo?r*h`ao5x7huRhocwhzv-77R~gqCOc6v>65L@Nw@0vBgDcI3^H#53eLSli zrKJDJOEw2Mj2w6NPoq4cNIR0ol21exj}QjH)} z9Ym@TWU7NmHG)ia5UECxsSYC52r|_{q#8k{I*3#w$W#ZBY6O|;AX1GWQyoOA5oD@^ zNHu~?br7jWkf{zL)d(`xL8SUnkg0BNRjpdpXAx?!kHB2{H~DhqD&;yQRq3v%3Pvi= zDzlWgm37Jv#XF;jh0Wh&qi!!UQLf>vB3gT5I+uhgmq>GVlaL%Y|! zmG;Ys<8)$Kti3yk02c-6XXu_~#ju>59O(3k$#AbLhU<*1LAN*s>0{|BT#-Rv69wry z!DiSc&I+wa9B12hK{`Ry57g7|7)L^VLAs(OC{I{-=rf5j$%*Q4FCo?< zI((y=d5ziHNNjfVnyp=vM_9a)8E0&;V7ThvSpTFqlq>&8snS5|)t<+kz_Avy_0{N;t zx6<Uou^#?vgd-Wt}dh-cmkRwkh8$zbd{`O$FoH+@bbWA5$l)hPqfq z328`WKc_01sI}B^o7PKvM0-kmQCpx{TCRq#v?G77B({+dT}f;sA-a;-MnZ5)5nNIr zxTOfFWO(!clg#zmlD7B*yLRm&a46kE(JAqdTMoL2l9QQg42B+xs>WdGp{Q!yk)ema zl*Y?1$>;qe71G!(=bqDyN>PrUtBbxYw^Z&Ih6-no`Y#KwmfUhT{jq7&J*TrfWmlp5 zv!Xqx>9jMmDiwH~-E+Ekr}Y9M&TqZd0X?=eg-TcK*x~K~?cO~^rdjuP1u?ZQeU9uo zUA;{8>MP0)Q$~n0lyL+K!CG;4H>M zZXl<~3>1P#W%jpTD8Db~$qW>NvvNhHuF^v3sH7_l6oP5WJY}Wwsq&>#s4!3nYN^fC z_Ub+A05wx(pb#uq*Q-0#gX&2&QDdMG5T8oxrw!L8Y1tYBh2RTqzji_^)~?W#^;UWp z9ewm+`UHK3zDUo}H|u+K9MjM1m5utwjYgVrA5l*+&X{h@H&z*&jC|v;@uz|EW*xJ+ z*}?2#W|&W!Q%%e<-!V6uyUj!9Y4b9xriG@~E!N#ue`|!5WxZxCvx?Td-K$rxJ*TM< zfKW58b;>GZ*RY$|?d)zg9ec>gka&*KqutRU`pLE}&6~T;@!4meeYkt; z)^%HtZ}~Zwp2cl>okw-u)yuy>QP>G7^p!Ant1~?2thM%pavmm<_*-K{~$YysX+*u zc>^^F@d}ZfU~^%MYZdZ_C@iXR40x^q=($dR3!=kz#Z7>m}bs1SDM?MC%g43)o*sSk*D6!1)|6G#y;tld_8NPOjqmKA?F)8Qr-75= zFv>Hcm}f?L##txCJTuBOrn&4a$1%^0@{B0vnNgk*#XK|0GoqMhMtMdQ^UNsEh+>`@ z>x|!6e00FTfhDjTzr@u)$?Eyl^owaM)_`*~^I?;EGQ%4i3ZMtUagE!G8w5GM*T-ebn~t z*BSRt88m3n6VH?*f)3Fi4Z5c_at(ZC95K!q70iGQjEBw9=JV!UGhhSbH}i7qD(gBc zU<2b>YnH`sjsrF@uCz(ew(qh7HZb0_KeV^n`|N-XjGLVQnjw%83^MzOIJyp9i?r17 zhWNyoG2$2Ee({7@EM6fYS!yM9k@`r(qzTdtX_15+X|uFfIwqZ$D$Did8)c-)_sK)# zadIiR&-quueTZ^B8P*d~t|!BKBFgn-SWiT`o<)T9M3n2vu%3u=JsH*$QLZP$dLqj8 zWLQr`xt&wVdxW0T|sjSvlZ&Z<{-lq;B zKzzW5N4|Pk{ZlQk1$=m9XisWWwK-bAhsSB{GQFnWRA+qn{`v?VSvr*u>1*}v`T@O2 zhe7oBMnr$V(|Evm+<3-##lR9{jj_e}&iL85U{p05m`E`@o4w6P&GF_-=0fv*6M5#> z=1=BXv!YekYGHM>kZujK##qy=dDcqnQ|n6$h1Ty@S-Y0q%x-VrL!AJ~w5Qm!?dA4* zd#8QSK4~M-sqQp(+B#jGe$H@bl7nm~!1!{CFG7qjr}!er-R$ml8OE1Wd=X-NImH+G z-eK=gk70Z{#TOa=lm1knVSG8o7pMKpE@6B*#TQY?B4aEf3Rz@~MMNQsjIoF)WRWoz z5rr%=#v-DSMaEb}6tc(|i-VbX_>TE+AbX+9|UA1 z$&KVT@}2Sn^5gO|@+&fy$ZO;+@^|vj@&&o7(m+9q(pl-PJgSUWUQ!k+?<>etzE*xx z&MFnvx@rrxql$EOkUB=4rp{AWs-LP~swh-{SIcU(v}Rg+?H+A_hD>dWHd|Y+t=D#H z2ep$L67}kOW4*23Rqv+{*C*-7)|cuZ>0jvk^%HureuaT#qm|KxsvL$H6O0*D<$xSx zvk|RwK$>}<8Le_azIoV;RyiQUdeWL|&9Q$V5t#UXm2Tee{2nb;l5HA8k*aXCjfDkqT@gg9EO+dT|2w@WtF9Jf?1jLJg5HmCLBeZ~`5b z%cwZ*1Uf30QIX{aIx3e@k>mwBDwk2Q#0zv(E~6sF4|G&6qax1_bW|>*B3%e{R4${U zPzZEXE~6q-40Kd3qaslXbW|>*B3lY{R4$_;Sq^kmE~6qx-YoBxkICod%1V9ZMg?ig zeaaAJoHAXRudGrwDacn2D}O5G)jDc(wS(G2MTYvMI#r#czN2nbcdLg~oK`Q>YHCfj zTeQ2i{@Mr)S=wvbGHtE4T|1x^Y0#0RH`3eacj^!5kL%Cqujp8!uhF;Y;TItICt&ym z2>uBeegT4i0`f1wPt7k)6q>)AWvyCPGpoIIk2SzTrZvTyZ7sLfTRW|T)=3MA)XLM? zZfke7``N?oNj9?WrS?bm7xsSpgk5Z3;UL**<#ciSIK!L?&J1UfgB)kGv)4K1oOdd_ z_1zm?q`CLGL)>xhba%eH%H8B5-#zU9>6Z8Ec+I^IUJnl$-jm)`Z;tnlx6#|}9rAG6 zyUefYH}!))I0S`oK_47~Lb#w04nZMY&<6)z2p3d1y)PnO;nYz=yu#^A35C+{Qdzl{ z+)QpS-y;u@ktt7+XUogw_3}>npnOtBqEcOHth80SD*cq<$|MEx3a2Yn#4DT@sfbrN z-KZg6;j~FZyuzu6j(COBAsv5LI9&pTBFl(_LXl*~L7`x5*(fL!DOMa5iaaY03PoVc z4_x_Vn2v)&k?F)ip-6P&pipGHaSkyRbj3Nu$noMFV*134bBK}e$2r8v5F(&Z;gEpS zLYza4EHTa@2A3B@brD=%4An(&c`;NM!R5tJT?CgGLv;~cUJTVmaCtFQ7s2JlP+bI< z7ejRsTwV;-MR0jBR2RYJ#ZX-Ymls2I5nNsj)kSc5F;o}9<;AtucI$vuWWh#~-Nc+nOzq3K*`;C#Q$Nk1gG~#|^WE*k6F_O)=-xxV&+;5CD zEABT&z7_WyBg2mSjd9wJ`;C$1#Qnxda^rquEOFz0W2AU-zcKPW?l-RJ*Y#WY9et$x zgZwf6G=HAI(*Klz^eFUy_sa^kgl0l};T~atfJ|YEFk4tItQU3)2ZfUY62(6B}$jY1cn{Sf2|Mdl#JId_X@tnRvpQXR8pVA#21$tob1XG>6*^)00?0u91noc zrEjI<(qB>)nX^dHOMXOtN`6sZAafQ;-6Qgu_C!~ykoKos_YR+oVI}5|;?|vd_Uy^r zUd6S$lARM2yl`0cS?jdEx0fp?mILKePbJk+#@(h9H-%wS`gSeudwZ)^CD;^ zglu{R$}b(qjv6(pb=rUd1CA>f$miLA@8185y*H2Un(X?1cbUrASOx`b2`z&%89)kU zj74S(u@w|hjDTel2nC_cp~W&oEXpVlTSR6eF6Ne+`n?5|aVP}mvPv5t-e71Wjm*8EmSrx|A9g>?+ILqlQ6 zkRdR|o-zd$U?Nm~TD59eN0Nd4^S+;d4y-kM_UzkN8$E5*s2(vR!_d1!hxV)-7C~4k z{s>F)IbHU!L6~J+>$l&2%c(pzYIIauWwsL+-C+9k>0uo^m+ag*ij%n{ZY{TyJIaAK z)%XJ*ys5_5c<`ng#|hv~HTD<5n`*pF1aGSGYZ7=C7|jhN4x}7y+p)It=MAAP&&F6@tX)w6a@o;(?~TYK_K-)tTz2*U8thI+$>fM0j% zt7&)B(jK209x{Lae7J@mc7G(7Yr2bKcQ6JoA!vkqCOtg@H}YPi}%b=IzA>k7NnW9oU;S-X<0 zD|FHNYBUk>C+*Q0?VkB$D@g$j+!q*Fkbtt`$J@HJ?b4+n0hw2iHU1yP8hx}C79_+i zSg@e|F0`Z-BoI_edtFXLBTYa-0t!B#SE;ly-{ThVxPEU38ZrtJj-q2UYf*FKt)pw! z1g|L|7MuI|WUU8eujgLt0om)h*LpzqdhWFzkiDLJtp{YU=U(f<$MzW8z1D+#8yNRm z52iC;GVZk=1hBPP_gW9uus^WwwH~~|y~VlLdT@~YjdQQ{fb8|$Yds))J@;A<$X?IA z)`KG9CDFas1Jc*}0%V_v6(y)8HI>|JJ=i84lH6-O=per)Uo5>HJE)`ZaW8+p#=%;+C6L6I-wYgQgL;~f&{e25b(`6ZNK@ZAOW!` z{gls?8PgQyi@an(3SMpHT@}3A z%9$E?wUt$L@MfqH@zG;A0Tlu2_-hi?9Oo%b#Om}sH`=-BD!)j!;w*+gTHO_)W zYnipt+K12r(<-n^+EC4Y&2DYKV-K(;JKp}vhIRICJH!6dzHQrfAXA5dFs3VmG&g1% zqcF+L4hD`eXPFz!Q>GFslnI~&h_-SPJD*+6YHT|DI}2CXhio~HWbX1@6gQZI@!V`~ z1^24bMB$aFc_`Ka-YeFDFL|$62WksmvCfzugu}u``D9OYV`nAE&uJ(pdc|Q2l$C%E z!xKXOn;&6+o0Wi3u=&lRk%p3$Kxinp=9C5=2tfgeVWLc=)G7xC+-rn7rd9( z2VntO3E|_@hNRDg+>A$gq7pQ~xit*4WXTqyy6O%Wi%)#b(bGEs{ zgw5sw(=c<*yJl(Y6{~>-ZLOY`XvJDHttHlaYmWuLSUHwu`Po%$hu{n!+M{gQPO__r zD{N#{^#^ZK>8A{MlS=O~;7uz1g1zV@m7WuRu7P)1(UnkSC=mQf_7T>836=L(LIq)x z@QiK50Rncegv!M4h8OIW(4)vdX~O+tUkR;RHKb}xXfJL#H7HD8T?h65@rg1fN9;9FG*W zNP**#q82G|JW|vm1&&9GTBM+f>~(Fz0eoS(U7O$qx&5Mm7v%P#3Zqn6O;V{v3ZAKq z7UGIhhJ~7{xucYUWGTC&l!0U^J5kF1Mh&Bp0qqUJ7-)<$5)FT@2DcCY#v6wX5>4t8 z9DpyH)F(KATV|2@l0_ffho)MKtZ%JU>o@k`6~izMB4powCkTNj4(|jVH-vX`;O2MV z1%J2w4pLGMSSGjqj!i6)*aATuQct$u!BplDJ6tS$lDoYCKfVEXy4a<@v`5&L;_ajM zI(y2!Q;%okJLX7eIp$TSZt0^Xj~>mmX<-6VncRg5NM&*tCLoo`U6_DWCZ{kJXS8#W z%Mln7Wg$T;Afgw>A5+n%(hD0p|5F&al1+ZNtFeJ)Cf(XfDDUcvjA}}P% zLV|%ZfgvrE9lxb1LxEgUsix2eIe7h+wgO(irHw>6dxsiUwCkS?Eg%pr_f8uKM9aO? z1_IIY?X-_syS5i~EI=nBMzIH41o~IEe3K?kEW$Y1xeKqyq8oWwXUU@`d#C>DG32t| z$ZOFexW%+5h&w@kjWOPaw~d9y&|fDThm1AG-*#T^Lwvg2$Rlr=Yxr%JGnwBI)evwa z51}n5jJ9S^Q#Ai=0VUuDl-%ZQ4gz@}`p6+4K{CICKf)9AkwZR$W`YlW0i)||DB>7(zh)k(e^xVAM=QGG??#yU02t zPCcNCYVMlow$ag9i*b;Yi}~)wzGA#-vljc~WlZzkVT$H0N>D-f7A5#b_ZB5+WYD6t z%-CqaKH~&dm4agM1mRAA8$3a{6Y!^b+qBIrF>&I2$>T#{O?i_r`jdH!TvpD#Rd&V(*2>&MEng4(v&chV` znWFL`>RSFZe+{#8p@I-Ba6*Leo)9C%33CPbM%XIoLZ)y@xG(sNHAHA6wig9)pg2w> z#G0K-_EF`;B18gYE#`5Kl<_`70J9cnB~90-PbXzIqyL{z|NQg*(%Q9aLw3pR>{043 zVum_Y4U=T);%Zfrb|OA9Yc#$^PG%0ORjXFDl=GvKlY^5p2chdbE8)DppcHkmPl@Iu4v1ZK{p~Cr6vcXoHiZP1SMWNwbDAF|!*IOxE<%Mf*(W9OL2 zz)6(Hxz%y-F*}BJtK)#0Zyj~qMPk0)CLR)hZh{1bVjfNAAp9EhkJLvX)WS0O4733! zMS!)@c4k3Us}^MrBBn6nGCfj11(7vBqZX#*E}s`QM~7?eQ6!(L7F7)zcl2 z8<^4Df9~A5r;8KXN#%i|*hjgcYw%DgC%U0)KueEPdB8`_@uNB)Tm^#W;63`vyTZw zO=loG&P+FdH?NrR&@5-YY9WXZIemkz@fOUsR#=;@1D0XsT6e9|HoRgtu-n=_ZPAXk zXWGeJ+751y{o_62^liTR>E_Mp56+!C2Q}N)teMdqZ^?yaGMd@=#)R(OyTdg^x~4x_ z8HTTupme)cMRfG_;p;G?m_uDF_Gi9jrsD;8vh>$q=X{-B0!#9V@<)z5JCa@kp`G~n z@cZ)wLn@E2@PM!K_zDmBDvz)5fHUKxBR=p|p8xNqROQ-0rmz39L2-q>+1_sC@B0ZK z2k9m7PR!qP93La;CGh#+tV$5NXru4?JHWwe_8z0;Z}>7yFVVDV>!yAtmrXz@KUX%P zDItjd9&Ij1<80*bhY_BF;63y9;dDQJpROM{gU^oi62nUlAAZEFU>3YCJMl%8sWZPlkK4gKl#?6=N0nLRqS8 zQ1&X0r=o-kRaN(JZ;g@totnA=(I<&1J9p;n+`a~PB#9{ka#gmgPgh~TnwV0RcSt9X z)z>xzUCm5P#w)L!_NvxIo56qA1ATI%wN7jIYCo+VyKn5++*4SX(^InT>}(+4qaTmo zG}^Y)ksbg(e1NYQfe#O^q%}M5bbG4}z7bCc0dW#W^x4gv& z2qVi~j9`hq-ri#q6r^SQF;y6-$FyR)Gaq7wk(nfBEdx85qf8br%X4(@aQd<~xRiNOIBQ$8_N6P)Ms0Krtr>lu8{XW#1?yo8Y*A{-IV zx(Fk0ONSi7$TD@cwEoir2c8|sSWKQ57cM-zux>PdY!DQ*Iw)f?E;83i4@VNzNycLQ zAn!};#5jUiSd1$(KN*UtjuX4c3y>`FwY+z{Z5Re2uY!#`7a*H2GPBKCj3d20GCY*M zAU>F_ctL#dis}XNfjg$SidIj9R+<;Y2S+t8hz~x{y&yigrh7qr5NCKneBf_-L42^x z^n&={HOrxT`kiT|d>aUIvp_*IUtJapX9p)2?w zTWs32X?$gwP*L!sOy~2haO``=SN4HUZu3>%@_|mqS6;u~Z~gOqRJRVoyTTwLdycTH zJMKirSDrS_oCZjU9AA0M7QZb!k)1@*Nk9qe4nQ3!LEQnU!xU+uR0MIb+?+Kg2VQtXixY|o2DrmMSH?it&+~_6zvJ~_0_tjQ?w@_g3aI!iuQ!f z#sU0UQ?w^IPiKnu1c&WO(Vjq9&ay?(p759T%wlYc_QWmZLR+;d+H-~*8ay-HPsjR) zkHxtqkbH88OzW^w-nI=8{}282e*FNy*723!;4$w3=cc0=z3fBWIFGMf+y>#8=Kyo9 z6pr65z|es4m2ui*VX{kFP8nQ_*|2)`YCwo_!1&6@D{-LMb%HLoWV^Bb*>BlxH4tx* zf1)Ffg-&#A(4YYZJX~T4O|S;nh-=RY91P^faf#eAZX>skJHeS86mTW^YW!<_YyKU6 z059 zyae72xgmjfLoUkT-H=-{csJy-0^SWdqk?xsuBzbOkaHS%H{`ko-VM2+BYyQgJyBn# zZ^RyiM9F}6LoONM-H_V`&<%N9#cAe(KWzs~BEnIe@WhzAvs3+89PlrxjDX{v=B0D{ z$L-&r^z!H{NEBaJrf5mvJMR?pNd9??Is5c)to)5P@r|l~f;}dZ-GM)cNXaRa4Vd!l!N#NKS-DYp4q(J@U95hs zIOR7)e^c+Qhm-2G_6MY>j!zkzj5!Lw>23qt|LG_CEM_^giP`_JJkf#ju^a;%P(GGp zU<1m>atv%h`B;vD4JaSWF|YwaF1QVBK>1jXfek1h%Mow^5( z53z0o8+72_<=h4~ILTe)+y*xIm>!F1tE!EIoJ0I{~{Hn0J4u(=Iv z;3Q^H0~)W8N#Vg@y^fs>d)hyAck^A7vL zNzCvK`}gbMBxX)W8P$2AFOG8#sv>)W8M-7D>#Y1~zaKGpK$`%c@X9n;Qhw=^iyUebNSi4po#9Tw@|>Z$rq`WgMY{zR{6 z03rBvGy5Q2{z-~)u<;|BNuA^5lfKHw1IDZmGc_?HAXzy}ry-wJMk z4-kTn8{h+EQtJlzKnLkv$qn!UvWam6e1H&q+yEaS1RpoR2MEE(4e$X%@NoltfDnA# z03RR(A2-0K_&RX|e1H&q+yEaS1RpoR2MEE(4e)^?<0aD#@PS31=iK0pXQZh#LEf{z>E1BBq?2KWFW z__zT+KnOl=fDaIYj~n0vgy7=__`qm!hUfy)RLRZZh#MLlMl&m zfDd#~-c{THA2_L8RNMd`_*fmIy5q1QUj@w_hXvEMFEw`@76jCe3#&3o@4hwpjpP24AEVy8L!KN_U@`6pF$nt_sVUbP1rZf%53DhNFx>zjc*A z=LYyd2mW2&4e)`J{6*dk@PUtoF@hW51Nj1oZh#L=7rzwU03QgDYD;c_53G@XklX+t zctd_mb_0Cip!}Qc2KYcPbaRYo{v^qm|1AL%JeMxfzd|;9Gt>y;!KrOwg z?gse4HvN$92KYb+<6XlI@PU)YMZ*p7fsf5GrW@b``6gIyfDcT!zO>u`AEZgvw%q_9 zSY!WSy8%A%2J;r<2Kc~1<~PO-@PS_JC#)Ob0~gr8SvSB3MsqVbH^2vqxR-c0zy}ub z-{Q8C0(^iFeB1yZAOs&bzy}Dy#|`iSLhx||e1H&q+yEcQmq2y{e1H&q+yEb-3|9x> z1C-(F0DOQlTpfT95Q2{z-~)u<;|BNuA^5lfK0pXQZh#M_BEDp}0X{F3zW)=YuN&a= zFDQLqNE952!oS`8gYv;0fX|Eh$BX%g^kV*DI{=>-^N$zv59SZ%D)Wdb&jztC<{vNS zA6zHyeQp>xnOng9H=cjYaL+$lt~hO> zaVmH5S^B9xnBL@?m z#-fso7S)q{=^6VZI3bx*f#gfict-}}fsdD+ttMG&f_tk;taISrYLcZUxVM^QsR{0_ zCRu7i6OC*&N$Rc>x(f$1L(A3fYNhp8^agrc9eV1b9;?sPN!acl{TCf_bW8U$su=Z* zRz`Q@Ljy=wU6QfZ*l8R!vW&kBcxEtWi20`3+5Es9ZcZ^_p{bhN%^%Iv<~8#%O7y^| z(ep|4z^BpkN%X)Q^u5mpZ_xKU40waS|775~rh)ZI^uVXl^GWo;r_u9C^uVXldoIyy zCljv>rnW>5DqhW#Z^uS04bh~5jY*e~oSY1CsEmmmf6E@AA8*SQ3ar;<9C!0}X4=Mos4*SQ2D?{zML#e1DgAPZjS5-_6I zxdf`{buIxXd7Vq3OJ3&^2(s6?^lzIK_lP9L`Tv%alY>4ftZ+oHy<^;t9i`1y*=Wb_ zQ^FtREMfm!Y?5p3ooHaovf(fLnawaE%$rPShNOVO6lNi#GTWISnbXWQ<}m{m*kG1p zBiQ%Y7&eZb%fdJ8R#s;-S)bYo9Jv!!JAos2qG~5_@{lu0TytGM=2TBwF0@3GQ+K{J2D~F#^^#cS7X#Oel-ZIS*`r8fG@-*UH)B;@*1t5 z%9WH~)S_ogG2aSMb!`DU_n$3AF&ff5G%aE=YP>B{EuSq#LHDAbr%+B-pnj;0+Lp&- zEFylR%~Gx=!K~zjFnP2oJG4InoRDf*{YF zIg@}ja)o^M-4!cVbWTAPaCWfRweN@#BRZ$dn9+JhXHn{lhQ!V(yW)#Ri&ubv9ejGl zBfT2)jT-~HXBHy-rq`8^k;QYQS0xFOqhXhDOgJyRJ2)(+mo!njBZ7+X_*(+O6g-eh z#XU%u5$!>2kzu1{lGubMR==@_ZVv36++#^|@guoMQcMgR1Bmqq8$CI;f7H>lXU`5m zxYC~KJ9nBp0ht70qifb=YXZu>dTwi(?598#C2V-F*u8QmrJ>k&+|8uIgHd6lh<3Sa zSGFthKNFYml6gTdCwET9n6M?q($gY)4lxLQ@WBU#-BW^9D9(|RNiG%o-=8Um=8s%D zuuJjo@ylg~p&HP)Z{J|K^S90TX3Yp1YN2}cOBp48(7ShU{7>nKNmQ6qdgT8-Lyouk z{*MhgGu#?@`B4U+kpZY0T{3!8RKU;i=*5|4JL&Y`i>Loz&l=BfFbE+^i3uf3A{l`w zS3m#!^ZX`*Fk5Zz1pJ!AQ5-(wObiC5R$F{HP)6bhpnrAA5V>{h)I4`$a%AS@mPwaNUb+;6=8J`+4<?ov5sEp zBZ;iU^0^ty`O2+*s)xNi*igNCbwJNw_QudR267yinBebk`vVpbXwoFONn*mGLx<{d z5BX*t<1ipBF#&y@HO9`yi>z7mr3GhVuEy@Uv}aEgI+eF}K~qa%gXW3xZ=gB2mJGqT*V~iZB+Z%>l)_gP(a5<~Xe)+rX~J8RBf?@(vAZ>N{J!zy*F|GE zUA>lbO3s?F>IJR4AA>@q|2Fs3ra3n za9ey&b&{}WesT?c#3!218;>1r_N3^8QH>fk%3V5jYR=U7(fB@0OnCX_)-Q)OpB#bu z(!_+&W*Fr2-(tP<`H%9B9XkLse-oqQkWmpb2x&m;LW@?`LlHa>GeWGP8<`k}ecy0I z{?OhO%z@@OGtqQJ{%`^fL{W~Xkf5f6QB_28VSjf9XgWn#-j4Z3N4 z@et`9iP3N{>SOy?yN7hnUTTq4Kls&ppZ|y%&0M!}>stZkd8=&H=RHkjCZMq?*F>3h z?GX_vA?R2flNi0YbEy5DKe|a1yU6I50W5OK0W#iZ#9^EmeR4zu-rUKI%0l|M^z?;y z5~I-feWS;il)%Li=LaT6p?W;IW*lDBm4>WYvnH9H!Ehnmn_P{el`&TbE*7rjSE`K9 z(cG3OIzH5ydz;-O@?0i&sqwjUe&<43z7cW0Sw27Um6oLwqYh1v2;je9NLKEI);T$` zIZ1~Tqb5Y4b7Xv*F*hR)M^wgt9ln>MYG%)>wk-qOf+jD2_nqH&5-WFyryV-gW)rch&pppXt-|+5cGCY;U!r*vKU6n}67p)UaVr!`>zE zIhok9Mvc`qdY3?&(MJ8Rw9`6HanR=7yTn%|zxrw+r*Z@w6J<#DqCSW57GBsgFL>#R z6KzkN$a)zg;g{f>8#?oU8A(oOl-7d@BC&AU#w>Fxe@5SLq8RNLnOyl;-y%<4!^=F~ ztZ*F*Eev?MIa}M9o<1lfGP6vx@>c$sMp#oKPoYnJe+(jQNFNY+O8QZfR#^JwUFngT zufF>1)g!eqhLJS$e(|T~H7R3Pw;S3o8IhTb7B#~*CCt8bD>5^nWI({_Q$$#?izC5f zV_rXd)h{yheBkcgyHDFtf!SH&<7(wkOg4){$SM%GP~<5DAIx2IacQ}t%*f0qAxldm zS}i~F6tdfv1Ylw>^s%VH>fdRy1HQ>lGl}3y#82b!5{W#8&bR?m&|l}GuOMqBUfLlY zk>IR!LwYJzl3BT#{I=XjhN1E#dA___)@0IaU-=)sQu*>1*uqDi!ZNadnqn}3bgXp= zi`p()6nQEvEG#EKPYL+)A>K2$m1TA_<89+&cXg=IbMceh$V{y8g*{b8EpG6OI}!8% zC7~G@+B28bxym=nRz;uF(X6gPf9($yl~J3ID_?455EvMT1*B67A`iD}wa|$-VZwxZ zRuwgNrA&+=SQAU@0fYBr7Z6e+)DM3@diIyQFXW(3d-nvS z48&``Q%Zv0UcIaVHI2qbkH=#(-ZwryIxDwRvj3z>lL&BbtG&ZGV&oe?B_<|zNo_B##GLc_hq?qIpsQ~;NxfE zsUt^nj)auJg1GR)xN*VbI;CJeUugbiJ~RJ!+Kruhb9<_C1@LAX z)%@Zn!^vC>or@h) zKK|g$%rj@maHO;Lfi@r|sBKVCyRkU58=%eK5*HpG-fk@RTXVIb9UBg2*1)1GlR^#T z#YrEW({xbuWPOKzL_e$F(4Xp+3}6lNW%V(J8j}n{djic!H!xbd823bIPvFKq5!w^D zaZiNy1a90Dp*?{c_e5wzqpSR5IT zN9*ZM2E5kO&MbJXr>9x)T2EuRv^Z`qx9oMStnJ2*+&6OMl2H7t+l}3KY2Usj*fM8@ zqL(P3-B_&EWM*7XY9;OOE`2BgCM&laJL$(slS0N4?%blVQ>Xk+wdZ&6%`^wclFY%5 zy3OUX7%KG>kMOy7_Ht?83Pe1N{ZosMdrR)!yIr^|jM`L7sn~XL=Zkqlq(~&+)B7O} z)l0$vNz zBo(|CqH-D#543yO4x2UaupQd!-eEiZqI-w!@S))ywjcV-@D1A|&Sz!WS;gPM$&-&y zMwn7I8D^I%S*lcvjtQBgpX-mooghl|$1ud2Xw9>n1W^(o3ho3^qCeg{%f7NC8Yej| zI&RswWy{<<*q*fLc;wQNBXiLfop}d)qktA2ar}c69VwXSc!=QNvqtYfsF(4TiwY1#THaPiq}V=Xxo`D z|MZjJPX%mOt{>+RGgmjv9~+C`e&fp6pJ%V;et8|+%>xr+W8-5Nn!nWUpIMrJsnwll zpI!RwvkdNSzI$`L9s(Ly#-dtamt>Ym-|#_O`5jFM3>XkBkRR=%r+iO#@JnPid1l<1 zGYxvYpNVs*O2QaKP<8Bu?03A(8&|%zXwjlcJy!bR#S`>Wn}bnU;U)=&kSoAlp|tpl z*g$M6_C&aBtOzs3CE|K1ej1s3jzp|A~1uiM~6@Rsc+DL7$ z3hF==#;J+wGIirWyVDsZHQJpH{qAhrvu7Ju#-b7PAGE1X@dH}@oZ^>OT>Vbs1+}DO zwSCp9H6~W#+x45ZZPu)D<*i${PBMNp@-q%2ce8P29Il-V>41Zq48#B2uwko*HLi@U zTxpX#*Lq*;);$Aokkh#GD1Ou^f{r6^vVfiS@!M@;t~Cd+M@`5w$vVku+>mW*Z8G

1f`0lQo z_u6Z(h2Q3Wv@`RtXk@h9WzTqImuD*4M3>nzq;4)-l4WZ!jhKb}SIjzQUv+1>)6N`oWm;Y+q{x`*{^??~;05!@?ZXylyVepBMs`$zu1hCs>n( z0=6VqjeCu2&Ar17;3V$dFWiCG$l(~i1% zpMCaOjCx_83OGQin^(CqTbVGF1_rE2Kd9!z`hNZT)y<2Ijm>_B#0dQE>*np>pR>Q- z_joh=bC>2L`IeIJXl5uZIDrw?joXS~%w9BAW90Dq2 zh@EKcGtv+5(s%75Op2h?DKn=`NjL5qfsFr8=aX{o=H%c8!vw^31q7wyWMv>Tj!9(Z zo7t<)wZGv_8kCxrmY$YuIz2#OEuMeI*SLyEK4{%qZ4LG6)vNJx%fNXv=gsr8kh5*c z?C`7MPs785QjwPcXG@+vJKQ2_p91Q2CaOAPMo%@kH&0XVwT%x3wlTseT z$MGwG4EiNDYL3xzd=Mgo}&!%BYTO2FYk6XCs1`Smk#1{0J@-iT31GI4`U zfT9B&asUvLiGvPs$N_(cNN-Ar4j4)3Xh-qYcYjmR_J+Ajm#Rz2vm@hV(Dq6^LPK%H z(?{ApG7cNnpj2GaRx*o%e!y`Mk}NJ{@01>Xio}AT)VJS${Pun6)z8V}*T1d5e^4qu zS!zr;m{}CG9j_3;=W2EhdGOSC-+ebIb@XVz(F0{g?rH6io$(nGmul#&vO?Z0_ffu* z)=4wwD;W|$^?Xtp{g3(clDk~$(&fHB*vw48$Mm7rdCg;|C!bPUeA6T1)mPb90cV_9 zW1Fj=s)b{>*38A03itiNWw-7^S8ptOiw~@nQ*rr%v+b%0{y5t|pjzr_De#L6v1vtW z)6Hvgu|utzu(9OEjr~l5QzxwLZ@%@%M{?DKQ%Ng}eQ0BDX&sbDT8DM``2@~7bTFs9 z-dCSs&AGOC3AW(B4cv=^nIj3&YMKtm^=#d3c7XoINW*P*fSX34;Wj(KWOIS(HakFh zE68%29bl!k#d4b+prPH)cAFhwFOI$3W(VlOkg*pvJ6t@^++rNF!xhMQnvoGW3oi?} zH15)+dNqHJ#|sz#_uyOLu}qeAWLF37WgXeofxyva9of~*Fgd!cLx1-}yo&;7;eG;U z<6C5!GPB*FutiC~kNf@ic>dBCIQpuZAmby5%<@ZXCj-BjHf`EE{;#Ggdcdzt#;fKA z(lTc3n=zwm0$yE#y?Q_G-McDb;lla52%8snx5Mc(_@6#~I!c%=bk;WuQ9KOh$MbiE zK;;#Ytblup7YWY$Lm{1)`{JYMWW{K_KYI%197&3mu1tQQe5zslP%&D@i67a+9TD?i z`xM7JNlU-_>MN)xeIN}VogWoHs+LAvQ~CP`<3qV(G{N%@XRk>o_;S5#CUr@AAg$UR zhlQqMG>&kdNr#?_v05F3Y<%_k&BSHP{FWs>CvAj@mRxO~KUU{HXpHZv;CyQDQT!q* zM%NmCHNJZF;OZ5lu@&xDY>y z3yzkAcDLYYNqpUHXA>MP36+vubhIQH;<6cdu@{wlA1f=4+eZ~$X^uA$SqeeskXn+H zy6kv1;GA{Sa#EKa&jt*$C)-Zyvg6sfNO}V&bs5`$qKc&L1vK-AM_`q2HUaBO#psps zG7js=OkzpGQM~iC#r@8t5|g8@HY-ymx6GarT>@W@ z{n!s19*dAWZj`~1N>H`26{D~kObQ4H91?i4Vidko#wSeflapiT6z7RVL_CYA7)<~@ zsi}Uclb9)NYh^Y|7Td*-y3!)y2`ytIID#PxCy&8z8sls@BCk}4TpQ7Zxb&J79lkXF z{lNNxxLN4jWkkK8eB7F0k<6?gox3#Z8ZK&=B%B|JTQ39fYHS@^DrCrz^dUL2U-^>hngkk2_pIe&6992u3uT~R2s=iPmF z6$w8Rcb~mh0&k!FrVQRb`$rkPefE0_c>C;23V8eMaVmKG?EiQQ{OUjAa8g$)6qi`{ zOBA)=Lx{XM#b?O%Q$ruDlXMnXp>Ng?=uSKfNoRouMq8t&;l#6$bQaiS{9^dxSx7od z@pQISDBh8eS|j9YJoYi?q0hKJecJDBa{$-2iJ^rP%x+!Deyw%u^wtr3{pz)eIvBDm zbMaz!F@ZJt)jt{NS8qm9WY0R3TaRh8<^&yXgek@zwa%GG>==^))V%+ zRoPx(wX|n+vu7cOZIk(>y|kcBM7MF>y0y33r{P3t;2nRw*XDq)&mnD2 zd%QtlpfFBI6qX4ag?+*a!4#lCC@EGGUlUu4?}!7CcnNxx0oURDc%-s5dx(; zQkc|LavBN+cizQ=U^)i|XAn&1z=xbcFloW7eDTRAIiD2f;ruum8BO+jz>x?b`gP;L zJC&8*$`Iv$6-+V14W?+muH~hcEerGJVN;Avn}NEDtUg-YxBK_o`$_qPR;|odfFD>n z01j)mYOFpW@3V2AebzZ;X)<>B2l8Z`_K}7zM2Eq8F8e08Lg%$)eXw@h0^2HW z$a*0D{GOtiV{H>_G&X3$<(K)b30=?}ZJ&_#*g=BPl0NoH(#;sd4XU zQJFw2tYj@#lvo01P9)T4Q6>(he=jglj(8!pZE9**0``NQFGO!YibI}zsV#H6WCaGU z4!lR2!_MZb3ixA{UWeey)~t0edVAW{f`)@1#!5kzL$z)q-j>+X6tbgK`~F7#7-iz2tovZmLG@j-FvCn zbL5~e*lKTo$VEH|&8(T*WqTbPXHM9V0vVP?U{ruFDFA#?0luUF@I?jqWNqM!3h)8B z!50;BD_iBq(n0rQwnf3^wCO$svOgFj%9BZ?Ap(?R%-`w>OlpG)wSn>*seb6edd)moKxI0q^=-34?MLUzv?F=k}Vqq0IJM@mfg@e}%tjH_WGhJkZMO;WhQfdYe5c ze!7)#GJQ-NeV9IBPpw>BbKFXRJDC&o4SJUY6AC6|5>zjo*Y5qEnogh)EsfrGe*?T- z_e}%5UH4=Yyj^#B3%p(TN(;PQcS9SzUH4uayj^z>2E1MOc?Nu4cMG-)+m{`|!c^94 zG0rbl2OlW661sNn3V!$_kKo?peAGhN%IRc9%=xH=co}=4|A#2_zfQNwlUGl^m4LN- zR7z;i>20S^zmtI{BH6n}cuu!uXN^ z33z7W`2tTOo>_Qiv(S9xryg5Jh$-N#*>f7!t*zt0z7x{+{JSb&wV@( z@I1ux2+w0YPw_mnZM%^C6;BZ!8xNGie`oZ|0}09N(xuo-vC7&xi(+w7bvarleL7CK zN=t>WNH-P{#a^8{!F4W2<6TMkg-wuKXb?3eO|1b#%~hRHEhke8L@icxLbaSsEwD5{ z-3irlGPOX~pD+6LEd4M2nGQ5m%gNLN)!2^1SejY`oEc%hXVTOf(9KNql1Wo*z=^G) zsWoXNw&v+&>?kislj-PVi^kUg$*=KUO5{!gl3(Myl*pa*e@ltDyWki6@21{aXfacmbmlgPOZ5VX`#@aMtf#5R#6v<^ZiX-U}(3W>! zR$20lzhrt@ah(o7J$yK@Io|Q`-M;U>+x|XwD1J+)ww*e)NiQ5)%^jN^B9k|~uIo*@ z#9>QNZZUS|*`fZpFlr*~7WVMJ@VA8-c5$m0p)ewGbbySr0iu1#cwZ)c5jGa1`rD+x z#P>K{!;UCBG$jPf=Altyg%-1-`bYGS_&NT-0s8w}aK-L4`-Vc!V0J!%9;0N1@X2{!2RA#DpfhnsN7Xu8orDwfUHmcrJb#OK&`Hoj=pytL zMhH^{2b}~z31@`s!V{sQ=%ACJw>U(cD9#gCi4HmmE{hH=zp>8A8oMk)?E>F<9iKP%^yo4Ati z-rcYJMXu_q4!nkmv!j_3|4kv^w zLLcHRY4zbxKKTUvagjB^QmyUQ4)e4%hNPPwwVvI?npN!%nbf^Gqk{$cEemj= zIH@v@oNTf>CQ_@SNqOW;$Eq_X#4YFnoKvQKQodcadF_ziz9Jy;LeL9adF_ziz9Jy;LeL9adF_ziz9Jy;LeL9adF_z ziz9Jy;LeL9I&5&~#gVwUG0!OyAL6_8ND=(}tR>_7{gIy^xPO1-=LhcJANl!#`}aqF ze&GK7k)I!s-=8A{anM~bOr5MQP${|#9;xNEAdRBCV2-v@+oBN?q=W8)>Uu-HolenR zutDFe|Eg1T7la!%LnrK- zc4M2OyI{G!$tD^&AG!-(XWB5uy0_=(E=XgJGuaG9cL5>tj$|pi3(m1O*+Q10yTI|T zQgjzQ;>zS4 z6x{`Vr4iCpiK4sUx`YEynWDR3qC8JtB~x@4lvQdfjTMUSg5}C4WxqnLtMIzoMvYV{ zx(m|O<7&1_(Ou9@>#vQ}D7p*IX*ab(jiS3?m_Auwpi^`gJkrY>K?X&4!5m|yvBjY1 zE~sucG~1aJ-31%Wz2>hbMR!5C)x-M8qUbI-W}UZgSrpv`eeuGXYEyIjBVSzx=UGPXKF9wMe-34>RmEsnWqPw8F)KF?CQFIqE32RH^aNlf^&vDH3tku62$2FscRin;=l>Jk1>MB{;z*IAyWpI7Q!ErIx(kL$lcfa`MR&m? zsk|H{Q*;;1k!er_$%%mKN<+mL6hU$#z#SApaw5Q+0=r8EZwhP|4ZJC^XEeC3J<%%a z6x{_A^?CX#oua#-tU*Mh6x{{OjZMaWgQC0Ob+e5bX;O3-q?yOfY?Gq9pqtg-`p>O_ zfUbcYbQjEFRx(={itd8yY(uskOVM4hf!)jg%2IR}gmXSefP?OWW88V}7Dv%t(3c;< zPvt4P3$F7|_=*BWcfmwqp0G-w=q@NL))X6y6x{{O#ZBUVk)pfcb*YUMDN%G6q)Er6 zY$;#zc{`w+++Q9kQ*;-clW)p}GDUZR!|tN!E^ydg6x{_5yNjZ`pt{yjYo}3k7i`e> zYQJg}-38%#5B(#ZqPyUjeja0cDY^^#8YHEchV;U94gpaUjA2}hV()>>LfoBXh<&*Go0go zbDA#bD~=GSilpmunl895l9XN=(hC!%dD1G0hV(*Nxu)D$rXjtsT;3$_mub2fysorS zA{Cl025HK1C0oh=XSx`4Q&9!1(sVI6r`}WxRhlja!?elT0*$7N!6U7_9;DNBF_@#T z)VJs~T@0!l4UKjNO&5a=#$MxBgQkl?xY@&WM`6M-^StSf!UWV_S-vPtk}d|T)eP zaN@-%x*QyKIYpO)!!D=ja&Xw?6kQGuyPTrS!C{wEbQd`6E{ZM(hh0w5<>0W(DY_gS zb~#0tgTpST=yGsYL=;^P4!fM9%fVrn(+v?g>~e}O2Zvow(dE!h@2`*4DY_ia={NO4 zoubRZVV6^MIXp7Tn?WW;m%|)$rMbnV=yGt_IW$qRZitSY8T}D7yT)(w?Hr zp}O2qZYNW8Ic$*k%D>7KT@K+&59K3;qRZi!a$dQmP;@!;RY$1qCp%nMpQ!F9J51E( zY3?UGl-0?8gQCk}xxPu?uTyk6yl%8HBJmME#z-&-x*XDs<3_fTkA4jYT@KyM{^m%N zqRZi&dDAR3DY_hnS(B{=7DboCBdfd}WK(oGIP5NpE{Ez&L#7==(dDp#*~>VpVh3Fg z;cO4~BbK7e;TU_Ky~R>=IrQa5a8o&oF8>!C)ZnnoDY_gSb~#0tgTpST=yGt_~e}O2Zvow(dFQ<%PG1X9CkTHmxIGDr|5EU*yR*m4t;gPE~n^n zaM`9%)l_Ih?a^ z+J!bnm%}h-GP8i8=yGt_T@+mobJ&&a7M7yRp*q))YsXP^Ic(tea=&sET@K+qoxhRs z8@T6hWc&v1`5PI(fqVW&#&6)Bzmf49l$B~qFXkWCA&XcCUd%sU%s*btKVHl~SO;DH zV*YVny`@rg`HT6-i}}Zk`N!Y9vvhhf|9CO~5MRtc%slg+S;qR0=N~iN^N&?`SJ}vI zBetUWlJW5?it%?2{SGMp&Y|A{#osyfJD~VGhkgeXfA=EnQ~RHVeGb&e>29Gy(e1ss zzlXJJ*IKY_*|O4y3G(c=UdMQ*Gf1E#ZWhI`391KB=8GaJ1RxS0T9QYb#hF00S>udE zLpNcCx!I-75-b>KjkBmW3x)p$R!O^>{a=t|u`GD;ml~pjP}Sno2@{zxL~(;TpH7&_ zgu$&7Cdw=D;x8>8y!cC505ATM5y6YUR7LROFF6Uk_)A>^FaA=H!Hd5%~L99;LvuDo%rO2Ft zPzXTON#W{*!i8wsL)wDhKXR16lxGT~)>B8T-PL?$6{@*cCm;_F7NW&^xN=losHjRc z?MDSpEAMDTzSmFvOr56g)*wk+tL@P!RsuHo>bhimtf?_2g%l6_iVL0Q(W5Q#`i^l}Vaz`C^ z;7bGcIqtxh2JCa(0Z9WMrM<`d@R;CB1NPxD!IuW?!(+k?f#NYU)IZhyNgtyCtaJ+U z7Z^Yl;v{jiNCJi}KrPm}@6kd~v@n{e>Wc}KXjLekf`%59%%r3cO4?(wg7n-;I(r!T zN^PR!A`A$B^c*BgyQLWMPid|Q--v;-E@p~d<$7`}xsL=yRP4C$`^W@!39Qmgd0XkD z3{@s6^Oe=;4_494;z#QOWQ{sgHw3LQ65%$mUrF;B#VX2j0t=g%jf=%` z^0}xy{AE6k%-w(BkhPpKc6mu;DDfIUfcu?~=g#s_PT0-GFuV{faKiIifN?Eol}!67n$ z8yH4-Vc-Ua5nkATrCtma2Aku}+0HHUpQ{&-4)6v)@D91h0`~<5=5$2Y-@qryJOZx? z2h(0(7>BaYoQ~)LT6ZUZ(0x=k=5$0lWA;G%+9NdQ<#e1i%WqbO{iltp;70*WZ>Bj@ z^bte8Ka|Wd#6&rXS{%=8NecZ?m8 z!hk!*j!0p^9b-p~-4~r0yZuau3^dPMgnioYlptXLfZtjB<7mFP*zXjfv~M}`{t@Ia zSb##uey7lgl-=GikD=Gih{JK3S8~s!Q*LC$xDE!e0Htb})Z;+)PEHFx2KNxq+ zw${tmA)||l8o39?NNbn%<#TZqc!LcW+29Q}ti^yg*l-&I-eAKHEO>(rPqN?*HvE_a zZ?GYXqrAa}(|Pa)8wLpA4K`dOfH&Ci4H3M-h6hFP1{?O0z#D9MK>`wNc*|@cx0U+2`# zTPV!E_tgk(sH75+lez>NPr&=i5=NmG$^H*~I3%b_MUM(Ge~6 ziTu%agPH}@h(PDyM*b*|rneSwlW!^n2$$bs04!E$o;lG3K&a}| z@jIFTNL6W`Ig#;0M~&v06B$38(k^Sn^yt$Bz#yIGnG;O_+|g;CIne}wBMP9J0C4A- z6HNf5n7%yoKLlcJfDSCpGbfq=IBd~8bD{|Vcb+-X1YGpxnXl=I*ITg{J}?izzQR2n zdzMB<3LH3)b09bXefE1gMn=X)1~ZMU#QrGo$EH?i5HiQyXN-z@%1zJF6e4 z!__J3LL|Pb+tnY{)9N+#v06b(va&gCV;)jeHs0a+9KP8$MA2-#Q;hCHu1TQ6+0$%T zuO-`GX*u|WsbpDNfd-px$E5hGmV|cxC=Cb;rjA0gq7tcvpGOgvSsSf=mh&f0p0hv)Va{_FcH7Ti zA{@Nr-%zhUknU5!;4_a7Xt%v(p>2qX{+Rm zfq67VU#K^dNs9<^NHt78j2~2!>2YXSNo_Vhw>=-RgnxcrpZuJX|KMfG*I7Bd#Z0L8&#l?YsV@N6msn_u7N_X z9mX|yXIwXQaQ;gvIu!^zmCm@znc$sqtuTSGQ|XMWfd$?f*B%SJGp_D7cxPN$|D^~R z2W?k_`xhc$4v`3$aY~|6M`+NoRjYzlD;7VAXxI~3KM;qLrxlAaxuZ0) zGOuJ_-T-yJa9YqJ4+~{QxGH?BI0USGEb&hy6CZo6?+DLW9`qCJwhtyR3 zUP_a|E9>qigICslP6n^6dzb=~l?4iwbw5&|yc(oZS@#?jR;pW6D(kMUfmhbOK?AR> zJ6s2^toxV_URifv1H7{C>jrpb-4jjl%DT&1NcMBfx|dtv$h!X)OGs6vm+jYW@XET= zZ1BpuyD{K1)A_t~V{S5I#0N}m7Uva7gRbE<6vDp!5^{@*k_HiTAbv~Pe)ii{kx-O0 zsA+<0$#)CKNN5bpT6-#Cl$Qoi9b|u#uL+m^)bZHro4z}B{?wFPW#i&|U2*0!j%g$(YXwneQiU~5~{+5)z=MXfDhYg^RX z0=BkAtt|*@TPNMCZoUg_ZHro4z}B{?wFPW#i&|Ujz1mi9x2#zuJ16Hx&b3hlML2Tg z+L6lUBdcirbx)gn?zuJ!jZ>GjM^>d_O}2X$K5Na*;&E${lh8d2%|h^&N#8hq?F#dE z97_CY0`&%{?>Er8#~f@uX+l@?v(ge!@0;xrykfj&x3GKK)9ghyT{|J%8|dahxHoXx zfpBkNhzsG~Km`uMy@8K8SjK(F1-*erJcN4#Yk3Iw2094vitvsQ^ac(H@Qd)L5cCH6 zh%ii?BnG{Kt0GjA>PSIvV7vr#rR7r48>lHmWBE~LZ~lc0-^yP6n%;~Jm6i%Tqr9dB zy@9O?98!K$g5E$k72a0gSA*WbYu2BCsAWgfthQ03d5z9@!Np31)@%~4wT$y!@Y$+0 z_Hy?txRXg7g~xU{g=>^p?Y)sWD|P_khl!)G4h=~feg9^UU!qZ=zHfRNbcl2Q-uou__f0>84g1z36CV=6(|83IFYq*8fyE1w zrFW&VlAl3;akfh2YP>+5PjC@FLbzLSiH3uA1W*yJ3-|<{iBXBig=dkyQoSblQR&_L zOia7P;-)H5O36}(P2?NVBapEqwF;0UW@mncLUB+75fL*r8{T!tx?by> z%Ci?-D9hF0*w#19;FfS~>l^;Yx8T{<_t91SX8yT1Pw>CjMueV6R>MW;)tx*qG>D-$ zY0RLQm;(2{Mu&rF5(UJBsw@X22v=G9$PliwT$LeQWf`vk{SJaEOHCERRhBPQ z2v=EJY7nlnY}FuKW$C6vxXN-`hj5i;hymd$O9d1Bv6Vlyf^e0kkp6dy1CuD0ouA?u!|FWk}U2$ws&u?!@2cK zkVG}5;3U3o>$^{#8yq{*MV=5DhN8{rXaY#IO?b|I?zvK>U@{rI7m!v4UmfS>cD@$^cJV=Hy@@#pjyiVRJ z+wyt2i~`k_`;=D7vr2bdb)+lP6F|ty8t%CL#udT zLp(IQ0G6vnt9W3!N*UZr4t&_3Kf3@Q_UE(yfDQ3bh6mUX4`q0uoEV;6pdLItyMP8# zcy;f(+QEDxul40*3N3KR#nH#b94PE-3!`idWODIhg{rvozbuBl?~pA zHJ&ga5oz&5OTm$bvBB7FzzO4uQPHezHZ?`FGxAn}fU7KT6$rS>@>YR>t1NF72)O#R z{i@y1R_&?wLL0K}E%rg1tU{bq-)ZJRJLe_mE$2OFaw#xolLLDl0><3t)^!Cp9-m*J z2Y7<}iTjmnx_Ry~7cRL`9C-)Ya-LKO#&EN_rQAA>ez^4fLSPm0q(Tr_g*>Sc1XdwW zDg?R0e&LKjRv}L+1c~CC;!u(3(}uV~+%3Wh@rqbcsx38@M5(j%h6Jh7IBAabrIaI) z(c+>6VWY)p8Nx=3YX7XH-FsQz+J7RlfI#EpjiMmX_;_(Ep!@`d@cdB}lymNK*tiwo zozh|BR?xtG#AV}F5X_#v(KC2D;vjAXo{l((TY;w|4s675iH{Q4xD}ukP+;R$P+h!F zq_`DjqbP0#i^Vk}8@IX%PYi6tkSpz%*tiwkJlM(eWJ4w!F`SUE$Q6~qMhvOSIAx9! z*odK=dY4KIZ{J1?GfBCsZdVIbM~%>`Y0yCPXV2c~8G_lfH+qI(_Uw(G!Jj?XH3TEx zc)@^PMw&6f_{8`M^O$+YF#|3cQD!Z(iP_ftPry;&gQL1zij{6nw_vfg#@c56Y@M}S ztEzpk4bAPRY>%g}*%|gq8*=UaHj+K<$`0?4h8#6>Z#qMriOxL7b1*>QA@>{%km`Jxm|=S|h81B;zCj(?7#oe4B|iRslB*BhFf;jVNc*WK@)aj(0TIi8E&k*0FTWr|FF8$~Ab%o%B~zsFm<*TXD5aLtL}{x?N|G{2 zficQ#WvQ}G*{Rsdd8LdB)z$mdR_e2AcU4i-)#)lMR@bQ8)IfFx&9$erm$g841-V*S z2LOqBSO)+n^so*9QjM?<0LqzR9RSQU!#V(HP#T~PWLJ=ln#+S$AiIKgc31}hdu>k# zP}dQhc;^KNdO2y%1m_dyE5~&5P!`= zI(Hw}ihGvp&M90vH=TpU+!}5h_cM2vbGfSgy*xDMpW#0pOckSM$<3>78{^8`cKfHpNaAzTqEinYb2q9}G2-w+{H94F2ZzZ5BNS14W- zp`3J=bidR_>L|%l3OZAOm8Ot01sa5?$_r&+r77f00hFdNROL;jNfL!HxJ1DvFf#N~ z)6@y-C+b(KsphH2RJf!@X|=Q_ny-Wh9NuV4wRIZdO3!O$bf~W1r?eh?31aNfU^_moa#bOKiClrBscV6m`9*e3ie zoE2Q5s(7ym&Bdq0m&Lx~a8VO8(2NJUqNm2IEb$WAZy`~7QyMBwl;%l>v_aY}!3pV# zR8g)iHwibP;*Sd1XqZPL%uS;>_MYz@Q>C6MfJS(7v5l``bY z`(;)j3yDfVw%(xZR^WtkMX9LPR-3A#+F5-=g;aH%N>ZX6)lv)9iz<}U?$Ykp+Gu31 zPtiteFjM8d_eU#LU2zC}N%lRlF(>Kn}rAY~>Q zRwo;}k!fr)V6Sn?xMtjD)-?q)-h9D?US^s(!TiMh3fC)n<}nj4nNb$u?AuzBm1GUF zV2m}}T57Gcc3QS|-YR25b^AWMmHn*U-B#>$d%6va?KSo``)B*C?b=nHdmU)*JmtLX z^mT?inv>zIbRgH+@0@Y2JC$ADjdh=Jf%3u>7oO*0T-e?1!ik&nkEWdGlPH~k%;CPo z`G>_7au+!$$KS=@&$r<_^8eQJj~w0OOW&G*gtHsB<{!7_AGhWoeiY}{{G)WSb!+}{ zYyNR-{&8#macll@YyNR-{&8#macll@YyRgX3wrQ3kF=<5bF^9zTBLc-U=kxfPl9G z2{s_$tw4ee2zV=yU;_f)3MANofVTn(HXz`wK!ObjO8RI85^O-O(hB6%L!|C$alJ*0 zdsdKwPb;HoiSrvuJ|7)MN?|JvCJw_^8t?(>#7D2Gmsg4(coWmA9j9R;4kKNM4&DED zm6Qq=Q;ZNVW$9j&rkaG*6fy9I}E1B=rk+`!UxU>jJp1qWJ# zvs-YWH8{HkhyO?=0`e!ZTX3K?IJ*T0T7$D&aG*6fy9EbYgR@(3*x>AT*ey78cHeN> zEjSdq7hQG>J~D+H&G}pKgOz5PD6T~YOVxo7x)?+y15%opmIi3?t(9Cgg+%1Fqh*fWB7mf%YAJz)a7{P4H7z%bl+V8hL%Gt6Qg0~` zF+jd_T)Hd;A_hp7-<8M8frtSv$YqrpN+4o@QOXR3Dm#8-2cp%#sV&q%!~hG_RqAFn z5HUcU_N3NT3q%aCQQM=P)B+I$bkTe2gY`hf07d%mdU+!dF~C6M17nsEh!`N!ywhxG z1|kNSW-c;Un}LV{VyuU)_EsQbfGq0=Yo8T}7$CuZ(e7;rB8HM(2Qh#Q)V?hzS$nYJ zj+x@RHB#d+gS^wGu>ypDP#YWw|DZa%5dJ|Gx>ql{RmEx*d>Tn=9MVXtR%zd+ef!in zWHD9cUMj01=Yjxesc~s&?@BC>?YGppQ%EF9cfvuoS@l zp-B2&DlZ4He;6o#AkUHm*gyEGeLu7h)09QZY9)aELyY>c+FlJ{|B$8rpzc!x*gqsN zK4^mdL;lT({oVQlI>G)SS$|g_s|T=uxS*FcY8V0R|L7=VhOxw0YiwTn!V53#s#t^} z&0OQxMPGhd_sfb!7z96mq=wnZgs_ZftqEZnPX`OaGM)q0+Fz^+TyjMul2j~0(vx)l z2<6TrTuiRhBfD?VzI|t{7Y<+>t76d=>}Yq+#}7NCVKum75q9o7+r`=ed>JB z+;j-;$+CA~GJE-Mh;bfvSh4_QIi!XN$O4eyzUZ=K0myfcyDV7%lDT&|mMj1l@W)bv z56lq%!atU^S?YI#DrKTzv0%aOLA!TjzISKu}4+ zf>VexdDtgFl6ALu=KG{I4%4`rH@rl z97<`PaSBgKnUeh+KBrZhFTlEd!Ob8LP!fm@0s$p~*dP#45-11){i+w=n2+V1<_qxk z%~5@%K)GwcAMyDAz*jxQt z{ZPFVGSpLQuKLNl(VAzJgg`0j@sA*^^y{NTSm}4wuLC`9bTPbc2ZWV=HL(g7Qu=*i zLRjh7(t@zkZ!4buELQ2)&4#ej@3akJrQZ+-K6E~HRyaP=zJd#3rQgRcgq41cI0!5K z)^ZS5`gP#f2TH%?)d~yULfE=>E9}_u&5ot~{yNV+_guliS!HI;+KV|8KV|~m1x28o zi61ioKWE~{Oh)=SlU(tba_MbM!j*zd3I^6el1VAZ1jCc1Ad|hV7qwZms9@k@k3F_m zyrPyA45U|YDLZ5J>eU4UvHvrmm6Y~ebbLVy!c0;VD)f-PkVZ+B=SVgtgQq_UVSn6s z8N&X!nhJ#dabGA9_Q$nUA?%OaszTTw*G+@4Kkl>!VSn5Z9m4*&3I>GzaUUD_K4JZF z|IjB3!v45EHiZ3gS8WLU@1I;#)yPUmGnwSVpTL`wmIyDuf-9a8d|6Bw?@^c1S{bDeRDh zS@;uSK}pb14m%`awH$Uxg3mJY9g?t52|FaAw;FaRz-2Y;kc6>X*dYlu^sqw`mgr%J zB(yNX4oTQ-gdLJ2yPAwcGAFG~TH3Yf`|i8%Y~)50emBGTBly4y4X!`Gtw^}E(D*S_yKoo1W0Y1ZsoG+O2- z^Y=M$27{!D*eA&0HD@oT8G-E+P@MqSJ^|GUfbA1dodDQA0o4hh75^;X9e)|={B-CxDlQzQS<9>l09&0N6eO)d_&@6HuK1ag0Hqfa(Om_6h#`aE#|X z9OKH7_&~rFJineVLM|vo8HSOm`EfV!@@_%g4ZOTt5O)JF@8-wd4x&uZD9l0{%K0J@ zdlZFB@b-AV=zQS_bHoUmK@~3h*+k9*k}A&^-6P&}4}pHiIL8bq#CT#ybGDi7j5Bv) zM(&^GdJgRMynu5!h~TU7Y)BoZ@(X!3qz?6kW&#^hhfHCUz=qU;QtE6-9Vn&FhSY&l z>TF0ID5cJZ)Ynorh$c)mS{a_{sI7^ALlw)7Y&R3`UegaZXpHJQNH@G*n5|)p!gA92B`gG+9}e z9hwH6$wC$c2l)0b82qjIoOZ;7_sv(d8CsV40XCaYo5dP{9#`O~m%+qO>+K9e;D5i18J=`}*E^wZkNV`TZYf$~}zX33{DY9>c3 ze^Xj09Ta#)c}EGfTn7~RMfp<+v|N4Ee}Lu)jr9PxI7|ORhi~;AdZ6WMX}~kaYet~u z+G@Zd<2NJFa&=V`gN$~Yqf+-K|toVt`=#1D3vHEY&n7lMqf7qNvPW9vn1;aBbk$MN;~X1o`% zUGHUVbEHjt-rY!ved1sj{1oQhjsEn{4|YL#0Pad|eD%$RMT-`}Pd|P0QyyRY9-O-$ z?DEi{haRdWJoNxRvk?uUvCu*2B$U1PZQ*NSiqP|32%AK@i4Zoao)#f&QXL{e*rZxP zhOkNXV;RCG)kX>;cUY6^+J7PB&HxX&^YJF!mYj)>!WZ34Ym?=*R)Ixs5pfGxzr-BAcW;ibar+@_O@c&f}Dw#q;I5cPPISrBzh+LPLU8S$B$Qa#j9yJ zfISn91eW?PG;=YF|9i6gKDOdtyO{4nc=nRaL3s9ZfrIeuWfTwLL0z-}q~-KqH6IBJ z1PBl6;zS4!>NbiH9@KS_AUvomk{~>&8z@6~P#39yhu822b<-3G59(r62oLJAR0t31 z5;S;G>#ea?PViV5{-7>dFM0QqtgI}+Te(9giIn*`!*-|@exrzRQYkm{`TltY{CvKD zUI9O!@5l2;`uY4!XN{SYm2(~0EJdYcmg`53C*@|428%4AeyP5Ug+QV98jk1>i)7-2fxLFf5;Q$Z6@PG3DMThP=Fie;v%*Qu} zM{m3;Kqaw`_@MZ>*hTCq(me;}ip$0C#h=6?@pqB#InY>oRQmgfun-VoJ!Wh1+x<{9 zu$Q2(C2#e|M+5L?4STbu=&O{?itm7gd(=4fNtM{a9y%DlRyV49)RPE$_0YlaxYkAM zsSVb~YfH@KT2{L1fm#~v%{qmkmQ3yE50))kRu7PA-5)m)RcX=`%fFKd!@NJ*;Afu|`f&pMc#z(fSG4{S&R9fZadQ z`U%+m6Rn?s-9OR#3E2G;t)GD1KhgRL*!>f&pMc#z(fSG4{Zqbu+=k0`SOgAZov;WT z2pPu`<6wy!7J;vA!J!De^2UuD=X9wkR;&nkB)QaeLFY7FA`gwj3&P7BEabvXBJhtn zev=3`@!=-X`WFOB(#-5SQ&`lbTsgNKT{CcElX7UdU_J0-XP)PW#+^b!{!ZaK!CdMr z?L9OWALI#<-zN@@RT1SvAAuVJcwi2%CAw0~6(L+KOOzm7EIT1VxLB4dL%3L0PJwW- zY^DOAE8i&Fl>)_4s94rO{fiap70a?!2p7xRX%H@!?bX1)Y5Ny#2p7vP>3Ab&i)CXB z2p7w$n-DIREjA%sENgB-xLB5JLAY3!cq9$A1&bQqb=O@d8kS_l;;aQ|#F7}oi$*yR z#*5B&AdDBi&pq18eb(*nDsJk9mtJ}a8{&zHlmF<}t()u7T?P+!J-W-@y=zmE?Xc}K znhqvk=q2{*Mce0X?v<-0-`5}M5ne2aj*d=^92@)Gb9^b^WqA1qxtpx91nxyd&n@S^ z=YHa#i2I!@&)4J|^N;eK_}6(D$bZ1k;=ka(<#+H$_;Wl&3U>+(g_goI!fQf*VWa@l zghj$?VXNSuj3GvRSZptL6aAAhWQjkB`^3|te=`2pS#6IDueMLPrBSPdgants-B6`U z6}Qy%gMJt|<4!c@;mC*R9|ZpZmi|HT4`AsZ1pfe*{z32$VCf$O{{WW$LGTY?=^q6D z0G9qi@Q+*5I?tq&ss5|TQ##xKusr2|QnvJeJ%a~q29Mw$z|ub`_5>{bgJMtMk*9-w zGI-?a06YyIdD`D6pVEQI(?0!!Vo$)*KPdJDEd7IIY_QZ^hl5qy^kYxZ%6iuF=^qq( z0+#+ku_s{Z9~656mi|GpCt&Fx6nlb-Zf&=z>(M_b_5>{bgJMs>(myEn1T6i7=BmKb zKWMHBEd7J#s=(4eXs!w@{e$MJFhTr8{7N)Mf36BF{e$MJuvA(n?ZkzhKUalT^0RVx zS&?b3O7IWZhBH)lgbFV!eHC_u3M~DDMyN1Uov6|XmFOP?|A2~GZOx~D5c~t?XkThR z{e$2iaKGM0_vs%5{{WW$LGTY?=^q6D0G9qi@DCpYT1x*Q_y@4`4}yOHOaCDF2h_5g z*gpM(;2*HmUT6FC4}yO{E9Y6qr+*Oq16cY8!9Rede-QiwKPLhGgWw;)(mx3P0WAH4 z;2*%!KM4K-Ed7JvAHdQ-2>t;q{e$2iz|ubm{sAoggWw;)(m!bD4=nwIcK*Q9KmN)s z`t%Qie*jDWAovHc^bdl6089TM_y?TPu4|QbUXRtE&r^*Xuf`7n4`B(Xd z%qc|wAovHorM#z1R&*s(*`%OGMgf-oLGTY?=^q6D0G9qi@DE_=9|ZpZmi|HT4`AsZ z1pfe*{z32$VCf$O{{WW$LGTY?=^q6D0G9qi@DE_=9|ZpZmi|HT4`AsZ1pfe*{z32$ zVCf$O{{WW$LGTY?=^q6D0G9qi@DE_=AC$^~R>HFao5}!|{z0h>VCf$O|9~^%bt;q z{e$2iz|ubm{sH&9ZQPEo?54P*U4nlAOaGwF1hDiEy0XJTF1(olmi|FkcDTmhCe#%K zAztvV>@Y$2MDXb!1pk0qViVD)e-QiwSo#OSKY*ow5c~sJ`Uk;3fTe#B`~z6}2f;sJ zs4`KRrx*&+KM4K-Ed7JvAHdQ-2>t;q{e$2iz|ubm{sAoggWw;)(mx3P0WAH4;2*%! zKM4K-Ed7JZFaAWhl>R~R4`AsZ1pfe*{z32$VCf$O{{WW$LGTY?=^uZ|0)6@i1!jQg zr)*#bSo#OSKY*ow5d0Ka`YFLrfu)}k{1jOFDZx*HrJoY~6j=Hx!B2supA!5OSo$f! zPl2VM68scc`YFLrfu)}k{1jOFDZx*HrJoY~6g(4YAR>i|dTrgOpA!5O=ICGQKK+B> zr@+!r34RJJ{gmLRz|v0%ehMu8l;Eep(oboP1YvVanhjxdOO*4!9<6{sTJc4s5H`0w z#X;EIvY&%9+;z^UpA!5O!seDMJcP|H;{*tsTkaD7&IL5VPl2VM68sdx=9W`3kapIm zpA!5O!seDJ6e?XoGB+qljs?xnubLlDRWeEaexd$wV>r!Qzmt*B8WDi&lVQxT0 z1p;EZ2P`lC@*Ug;ZkvWpQ0!~pqFVotQ>`B@RlH&ZYD03=4?p~nfieQmMF8RQz#Itz z8G+{_fHrbRj7_A-qh-%U0NdpP*^wiZYDxp;5#?zGURC-jsxnnssAMZ!l!FTVs@zaG zwZ7U+ZKuAZzNJEV9eE9#ZCYJT&^#|@nucD?PqeQzQ_ItiX_vGpy_OD5^tQUBC+UOq zG5TzM>A$iUv&24kLWgP zfXC0(EA;HyGbe6jR>XX62X}-!$6bzyjQH&OXP;fWK+dRRWst+c1>odAadujV+HDyb zZU$g;7gns`SCF!FW~qb*JPS=Ap&98}Xl_bqu6}*}>#sAT7cX86d1dnQ3I)$r5+C-vm?)Ld*Fcw(Eoc) z-)U7ljLi$Q>vio)anrNAYPvOR0(R@+xQXFKY}RK-zQ6AM_p9!kGiOeAWamwtJ6E*_ z?Rh&kJL1hZ3*St!XYct1{~h~H997b0mO4^S9Z*Z@9xYm&-KCb&Jv8mllnU9Q%^lbAcs_Ez&I!8mnnJK5g6skaq1wyy#$dhO)uQ- zKL1D>R?@R05wz3FEq>#7%p+$J=h^%i_Fwo!K5;iCe^oR zTi)t&%};7hP7alh?q7YXYuBzBSz|M>oPRXpWT&O8_eMtS%tSq3oii66%)k)h&a5LF zA`J-R4ze5w;|>yB2;&a&|9=&^{}Utk{U{$_zI?0lWAcBQieEL{hP{3YgOusUnw}V& z|Fq)j)_K?wLc7RksNE2DX5oA1X=A&2wZ5tv>B9;N3ZQD6s#P0M{j2)7S?Yiv)c!+v zB_*aH5N7F!Q&d|jN=!j~NtK<$umKalulZ97oPTK2Qr=h#{-dz}(-g`1S%59hnw3pOE^G#&xr`dHT*iAl0QD%eH^`^#Tj%=*IV~w!x&||O+^sRmZ)g`@p z<&IjG`Q3LnzRQ`5-&%a>)J@JEh1Z9()4td5Fs|0fsF!jimm1pr#s2+a-@bj-jVC^f z!jIYcS-I)O8xo8e`dYHxeK;KH3%R3E<%ARJg9n!`tC4vMpNw|-x#<`QFJ8I?-@Un` zFmve8Eq>_|ED+RLJTNyMzy3=N0=vTtW*F=a$IKAe%z{By80-#Z>@e6JrrTk#JKXDp z!S1lq34`6?2{#OOhuv-%><({mUK!d4yTe5;40eand{}G;)r8QxYrAu2!On7H@ov4h#o@#DVZaVV?x+;}XRlbhLv$uqU*cySZLeU2zaFyo6HY9Y=U(w&uN9cYV5)SCU=zr=}48IKteT-qoBxAnew;|!GQOT@hK4|)FNEmO< zHJ6*;n|>P-YFcCf?qvCGNch6~*4kkmvHUh9u+?j7Uc**9YygICPS^kp0UyR|L&6X@ zYygG|T-X3S;A3tzXua7mcr<6ZJk8@sNuj!*vL^pTvukQZM9d?(F+XLbs zyrG0$V{lOkyT%|)S&PuX$JhAu8d#`>U1QKp54*--lOA@BL71|ZhrEmsWi82sK_B5&L#0y0G!+#*Jh7 zl>)6Z6N@XG*b>6be|%hYo9O7aMR+EE8ijK$Gfy6>+P09;FOL1&7JSvTEvixfh;sr| zJgWenIP!!6_qnuDZFLf33?1FW@44w0ux#13=;4PW9ww~YPJv#tZ%F4$#^C||<%F*B z7uwBlFr&{9R1aW2@@u)y~N$e zx2lJCyzWK&M(^84eR5jEPK~Z}tWKS&&Kf=^8mmuJzPf;CuN?ekUx=?&rdBQdwF`ca z{NF3@xZck@VhZv2(4mDx3nH_OABn3-UHW)?5Y#y57yXuPQ$UTW_D4o|Ahvu4e@HfyhW zeHC4uquNA8HP6E1$u*N-KMqSR^&?wYk8f(6lXNU8sV?eThHk{?wMuj9x>Fo4*WGTd zEwEnY&+Njn+2W1Qtb68}Gn=t>zj$M_GR>NKlFEzd?wM#0AXg8f2Up>#euG`?9L6jD z;*Is{)q|X@V*4J4^x6aMKF%nR z@p{FIi#OuY77mv=e0c9odDFjNeCwzm-ywJ8Ul@f?b}P*rWo;W7fnau zUH9-d?aFvO6`nttlESA@RX1LHQ15=EO5-to`}V!0_0^NcHcgMhV*(kYax8jJu6@BN zoO}0FJekg$w!F>q<%P5GsBx`m-qdkx)~xZuJn|wMKQ&eu zYZq?J956OL`l}4n|9cRy%@XA|mfC`P)GW_J9(&M5rQ%dOolLrnaOxoE%2wX-PNvIy4prNtF-(?L)Fy~ELu*UHZ#e^pEw<_APPT& zi?xfICzph9zWf^<0=uLqmxRDB>B%J_uuFP!NqEnkZ0djI%deRb*d;x=Bm{OzPc8}J zeECvjqJ{G1tsDsF%Mt(NS-QzC>B%J_uuFP!NeJi5hjI|uB|W+1$iOa{%D;C4=A z&rBXRY}inYw$&*dH8Tkh1(gRMNuQb2a!S=@{BJzI91f0(maEKo196IHc~L&0&V2n8 z9`^5lFfz44g9hhzsvbj?=5!8CUuGub9KeReNzb#%xT?EJ7M)NWb@N}E0 zk-Y5L@mKIx(yKi}$Y4vWR;`A{bQ<$^`iCE0`!G+O{v>`RV3CU$2z(mO)##WH_gO!<$~a_9ayWpz$vpD0ASz38#$^`^Vk!o9oBiDE_f3 z-hwB`;pFpZ{Za?+x;r~{#y3ozyrTBaiO=Ky?4J4K6y8zlCQOdSK@4^$YIEt2O^*Ge zup!s&w*1a%wQALx9EWGZbaDN3aj{5u`}gE+<+pEdwf#(7`TBV3-Nv~Pg?E^Wk7db^ zOZnU+c~^2pyoR@}aiJrgcnaG^W<5P7qDN<(a%i-tNWwDB&giCPnl>F1S#o~Y&E`LJ z;vW#GGWi%b|LgG&-BsoLOZZW#*lA<@tg5pFI44AkcZvfKexMBua* zwdH&FPW=`eu2aTD(l{z|nt6ET++%a+7DkphEpNjaxJ97@@?Ar(O}%=JiCk9ykon@K z2@~p07!!#X$$FN zHNw|Hl`)ZcqitXl{q9+NZKf>vm<8bIu{*Ejkj~|#WVF$ z)ozZd@eJX<(|9l{PP%}1)p_6Iw5Lka1zZkHzNra?x}3npb1!hdCKP;6sILhH-xKO< zLSZLw^W+Kr-{&_%z;E>0+`u*ks3-uwC)C%3g6|3SHKE{pLVZmr_?}Q-6AD3{+tY+X zKh>{udu{HKz9*EL0=+&g#hKw1GU-CSb@l2sD8d(buTcdqUi3+D5Pv;BKIsC@2(kuc zWnrygJbt5>W~Cv0X>k_L)0U39f|t{z3q+$BhZFv5=6id7Nl!Z8Qf%3hwt*SHJh-#v ztn?r8KjAgAm$qj7IPCAX&EMw^(LdBrTrHP>D18ck6+VR9+uVM8(gh+9p*;HVR6Xh^ z99Se>Sg|5yMFEN{QxD-Rf9GWv4?m^Cg)8_4S)7IEBT#8+g(vBx3#agFm;L>)0-UmI zfaj$#3m(fzI-lGoIeE+y9C1`fXKhJJ2_8|XM?9cyet!D5#_yj${`lib7ozZ5JZd4-w|t)YQ7ENf+?rm1F*D-Y|i) z+M2a3yeECv*cxKZa*OM%!{;aI0tONePabtBedy4kNw__Th?!6{);elku*%vs>_#@U zwx6?m*aPfQ_6&Q8z1D^w5kOaLgA?ui&1vCuaNrf^9cP5|k+Z;AH_iQ``Tq$9(@~$n)Jgvt5(gzFHeH>XfrIbiuc&y!q%B~QyzBE9@x$=d z=BC-@$`zCw{tCWFG8XjjAJPB3HfT|C`ml_q+0j$$>BSG>Y;$_*0vu-^UMxTL4qlv7 z7xd{<*r%O`ynP49b;YSf9-i4BuNoZS&Tgji^E-z!Q!}>U@%SLlP5Z6byxHCixDp-y zO8N3P$`5}9&*FHVXtlqpI%qk*--f?3e)tyLHC0x>RNvY)W5&E0sSEJPk*WUr{(?3O z7Njn~BkoM=Uh`%=a;wBJe0<#2(C18*nm?cOo0cE(r zEJ0!kn9c=e2@*?ykN@}S|FDt|%n~G)IQN8*D7?{VerLR_f=eeuQaN0~ZQ0OKGyvN| zhXG-sux(Voe&6(~nmnpLKKerkPP#a0Qpaga>eEa_ef#aV=}ob?;T60O7slZC2V9z+ z(|}$jLIi#kt1B(<>zSWYR38s8iv{sfdao76;Ay+9Sf{U;5{Ji|rg7hP9@uuuwEB2V z>Njw3=Yg$goz!n2?wnG@-7V8_TGMYJ?vnCEaK&D#{_r22yQIwRe5CV;`YPRJ@U>S? z`t(>Q{?DI$cg9nEmOqUHA@POT2xk`Fr z=Xp9?zwaXB5MMg5z0CIQ_sd?SrWQ7i9v!3KCetZBK4ENqm!>hamyN>dLuzT1hLSYE zMrkNX1G?%r`>&~#qyaWcL*oZvqcoJH0X9mrPT#2mo05Ch=xzW_2BsT}jWxzL<7eZn z0j^Qiyw_}QK4rda_BDr_pqUxwN;B8oZ=Nx)o0To#tyt>`E75w>8fs0n=2>9i31GK% z!n$Hrv}@Zx&N+noXj94Er9 z=F&0eY4=sPp9`ux)m`XjyIb6Yn1a3b2h?aAYzN*cv$1}0dORL^-l~FQ6^#M~=?PQX zZchAc&}W~$#ci*Ed+PKA;*f5`!fG7CuSf7MO`3ADwvweJe z{C)SO+&3q30e_fB_*Qzt$dj=jDmCS0d`~5kuk!>!V&fa)S0p`QR_Brg;Y8_uC!$S6 zM0x^EVX$9ZrCkE<4$>3uj$bAm7NCFKWl0NSV+7hFbQ7XQcwHQ!loe))Ux?p|JH#U* zoD(CZJEebExpKQwPl1P&1m#7gw=zWeQ2A6@p}=}2UpcN^Rw}4>s}HD;sqnm-tiG#` zRXuthOA$wlK@S#=asKhvJKe${-ap=Yr&|b)w_Xnx0zA1# zCx?4QA5ZR`Zh?jaEUXBgki5(LM9Dkd!fwew-g>87ctiG&x8CU%F3SG#);rz8XvII? zdZ$|;T9J3W^-j02P^BVl(1V3$8Xa$g9xQCqs0bVMVBrNlzycE$7>?-?_OH6%gME3) zDZGYkxKLb(`}4K^E|*MgQI5D!D~?_~dNeyfGY`R|KsJ4iPM21=xSfHT>uS~U@61|%K)Nfu&@m9fx|v50|+=wHEEwW zd^K@I|IBi^7%Bpk&-3Lr&J8& z)nzr!D;c%{-$gWRt8!y3zNLmQq3!!K^R7O#p>RTv4R}@tS|b*Ih_|GJ8*yB4hhEWm zSTEK)*qw}b?5+lc6+w|EgcU*4Ob9E2Vk`(Ng0d_KD}oYi2rGi}Z8&a+5pD3U6GpT_ zSvQPmgBflZ(FT9xN)c_`JKPBFBW?i)tGLbF0qz&>Pp%4o4T(zdlE9KlCQ8*Qu)3xi=&GJ=w*2^Vx6LAI$xL$EfwOW`kuqf4g zO&0s?*un3hs8MFZ+fxUpL}941SHfe;`^psM(>Kozo7$su!=xoCG+tL}+J_U6#R*aP zR=JcsSMdm+#$lt_05jVBn+Yw<4(2Q7JLU-UBXfbd%7o44 z0rMC0PqT`3j}>P<8_~?Jjmt8wT6s?YZ`H z`+NH*yU70ChVo8Lr?K;>)5&?=8R&fAz%1tr=UZoobHq94M7npn(9mt^KI6XT_IF3R z)7(WaP+s_u`&Cs!z0XbIKI5{uA2`^@o#y`FZs&2F%qQ?K^3agk8c>;et?Bgc@Qav9@`fDS#Y1$$UR%=_eL)vdz ziAKT2hjnPLchle2-`A(;pXpip4?67APwRi^w;T10hl~W{MFV;pLktQft}xac`NnYr zE*lk0U+R=>zH7o*^J8M>{sk}>=E`y_5ypA4V&!)_Aj<4b)uvJbag0dFv*$keC=#>_Be3Tx$0DM z>$nfPkGoymo-Pb_$Gdagy9?#Hnp|Vg;S8j;p z@8qE&-;#fZe~s_YkL0KEi+EVgZ{-j1zwssf9Rl5?fUZ(+3-2S1{4*g-_(1?x>Xab9 zC_-;>i1?xSsklO1FXoHKMYt?hknWZqkRFqsmy)G-B^WDxEG?71lXgi*r3+G78EVLl ztUaH+GMfy&>P2~ zEVdplTNP{;TMuLHk8KuP4>g=d4vVdaCC*xh#nwX$w}b0p>pyZAxT{>)>>hA`asPCy zaQAR=+>;!1<@#{LxJlf6?rUx%w}*q1+*Pg;Ux$B?f1K~a_vB$PKc1hd4z10kb+P-5fy+t%Js@w_vk&Kx5Tg5Uh^8%@G8v zBX4sAgN^Y9tKNcOb@aM9(EPxJS>_ietKNc!R!fUjZ^3GdRzHDy3)<{lGHnpe$ARvqg>>v5}#)zgB()_7~KwcPsN`pGJ?ez%~!UDIxCKWcZf zU$+O^AJ{O<{=)ti4UI?ab9SV2rvnY0md-QIYfgV>q%+M~Wt%_(v2aAVwu zU1;xibKgcwz!dj0H_QFOg?;X6_Ye1Wt{(RgM{Hc^%?;r``H%T!{CE5={wRNeFDpO|p^?y9cuwdc3=l>MGXz*7tQCI5nOLy^ zVzl@-5n6~H#8W6?h6b~gFBH~>1`XAgDr-Z7)#_H2wV^?Kt((T$&|sf-T4QZ! z&|9a4*{AvneZ77Q;V%5w2=`?1T@l8LAB)Sx@5Ei=QSpLUR)QK*BdN9YoYX@afU>(8 z5-gF{NX!&n4w2(WU(U*tdKD#|@dobsdsU6nq{ zFlCZ5U-??usO(YTq;gfMq}EX%R3BHns6AB}td3Xbs>{{y)t}TN^>-D@Yc;jT+M^m3 zN(O2lXfR9rLi<+Rp&ilAX_5M!IyBT<>d)w}>HYPQ`ZRr!4y*O8`XT){y#)IqF~-9N zv^TmLZyWC$Q;g3H%96r9oMzjE7^M2g0a@e)-vlmYuC;FBhUhp-9G{?AldyR&;pX(KLRZv+5IEX0+QW70xclf z{Uguhwy}^rvTvz&F?}4he6g4h#Ra0``cT|b^d?bpStu@e zsl_0)2t>tYp}63s7K6|tc&Wu8vw(ZtdSoT_ac`NE)SWPIM=_z1*W| z?gm$PGYQhSf4{rGGy+()DqofA4A|2EAs0Y zm%?da-7iw(aIM@+CKDY5Dmw2M1A&T;ela=2N=C$%j`8QucY$i`xRbFcj-8`kd4Ja~ zcNg~NGq8-$&!cJKCG|e7l?Kmh-5D(0Hry9zXEj%=s^6;<7Vc#o`s%}VP0!F*>V$P+1YwF;Of2H#s=F;*IYPnJfS|dRmDgjU=^;xu99*aaCZ&3BZGF< z3l{w%CtLfhOzX;yG@NLc+laf)OV&N5?U=(2a(^@<4_M{asDnOJjZ-3XS&RJg1p?N6OMz{HWWS;zmLT@c3#Y@WiUx3 z{wm%OIjO$XOu9-G!=(097p=XicI~{F5lP9?q$gf`ZQg5nG1z>cAidi11@VO!$eDQQ z!C~>Iu*$bBW<|%+gfHeAEvP*N%_F3l%|V<6fq(c5ikrw zktiTTD2W0hLm3be5XvAZbCDp>fKUbyL=r0jkwzg!n8(!JJ1=E@>zuXjIo-eCI``ar z_~TvOtJmt)tGmB>YrlJc_VX}it@Fv=y><3h&%`;_=;w;{$BYrpjTh})ZPX!*r=~0^ zZqy8iw71i7EMNO_qXV@JEdLKD(RDmq&fc1Ur^((%di;O z-_MJVx)~MKn^GXq_h#R|lfS?uELi0&tD#v-&K3phHs;aF?%z<^1dKLkn2Suq%rOs{ zh(6wuit9R;>toM7 zuEs^V-*9>2QSJ;k$wO(*b9?jsA6Oi-c=6@>xPg(#&y%jD@#g1y<1i!%FS!Uwz-4zB zZsImF&aiJ^X=}D^OFJJ~H9KwY)G03-*VJ<^ygl;mxA$CV-x9~p^EnV?(#iTZS@=dE zovd$@g$^R=WO1wTnJM^QTxr7=+w*TR{T93;y)C^j`JQ1oFO`$4$-ZY8Cdrxd=Q6zj zk0d@9R#2qU)-=Y(e(I+p9)tquEABZk-Q0i5JR6 zebEx*;>2a$K0s04U^d8~<%EPf2?ZyRG;&6HSZ%1D?`&+8_sPS?m5oesxdJe4KJANe zOax4Jmh(G}eQJRUPMLGGNcM)+g{exSc1THi^F}tVU@t58Vdv0-FzCqy(#4$%BE{FiXqnZde&xRztP`v)&8N? zzB_IrV)!kqRi~m6i<>1lAM@kR;CK7>74@BW-k}ZDvBfHW=>TJWqpQ|F7}@VKPQXT2 zeIct;R_VA?WVXX0S;Xk7I9i`=HxNj;05n7nogst2p2N0t%1pLt##GJ|F8m87+cs4H z?1{!I=BKqOdHJ7)?QMej)s%yZvQgP1a8F^fD&=6U&9!RHABQ`fDF=s-96r2?D7C=^ zPRhY>WKuK}%YMjh-Vv{D5kJMJ2M*w1j)>thGyxUi^*t#{5>*;iCriq+pQg+mId|^X z+>|`L(}qbvVujrj;bnUu47@-9M+g%i6zhqr#0=RI=kzJuo0pO|t7xwL!*`U;inp%H zi|kqoam9NmuPQKF37132!+j^E%MYm3H-1RPzVU!ek!_#P9`sxibXOOuG$uHx{-$10 zXDZ-5T7OqY$@i$AXl)v)TV^!>3CD&T?=ZrZI{G*2PL)L?$_CZVG*RoJy{cVSW@uX$ zX@&-PFQy#qcClNx8b;60arpyMaWa~65JR^;jBDlf>iTk{Y-k#e3F{RG)ACd@x7RY$ z^pEtsT`74-vT4mdw^(v%w<3Hc>DtGdveG+g6 zoRXfGw=u60*ZE!ygruZDU;g>$?`T6Ryh$U7S=?*of8ow@rQ8F2H2qPeH{Inxl{nqI&glRu2*+8PV(1WQb6if^u;MVgB56=^EotwV8f4@@bfq*Ic* z3%W%-wMdA-;G%>DvJfUcC|%3rzUe!q2VK3DMO^#A8#P-#DFac{eF??YJE;4CY{GF~ zoFeCcBCi~P*I-Ke%9TYcBUNe4k+hVw2@@tjyn0ivqWB@hLY6XoPiZ$Dw?j%((kTW? zwbbRzH?x|@(ulZy+N|u$vv;>_*>bgFXe%CS+O%!c?DTLb>pIy|XAr}xtR9vZMFny*2G7mY#2D1$ygD~&D20Rsw+3q}Rg*C4_OGu`~y4ACHh zRn@9%`5MFxA6nGs!3C?N^e7Rt82HDr=)i%b14(HZ2U%p5&&QjlXHt4*R=GT^4U*DN zV`@Fj7W45BB_b&uZ^S5Dw9$8Q7zW`da*F-(A=2GZlwx~LrwzZ-ddwN*ygWWOHY_&T zS;}WPo1OiR?Zi1?T6xw<>y$&ke%(%Uf8AkIS)P>MuHD9VlieM+a3d%wJ+gdcWRB}< zbJPd9zrgwD9M@qBYr7G^T{_&o#nFuP9-c;|5wAUraoe`fMd%c=07_X<$if?x!dV_G zVD}35fw0T|N|-n~9Iv_60s;zL*NqhaN{2B9Sh5H$gq`9`!Wr(6I9piy#EoVnlF}|T zyH9$)Ggf~|>ET!l#z_~2iug!dAwj6#X1rLVPbyZow+CS*T`(mT<2Fg@_%#J}SLpFdwr=seS0>U(@hXnJtIwRTSWrW=aQznEMR54?c6BA@_ln)?QUd zt0VcbnD^eQf~6Lz7gb{JGvq$VT8j3bM$CPN+y_Ss(;w7{xzCXMBUF91-dLWKiNC_c zsw&nafWg{1da3mxT_O11*wR+IssmMBRp)NT74A%|UJ|Re7}=u5b-ndh`1MY#8je+1 z4WqSzs@Ko^8St4g(df0*AEOsO=`7J7!7=)4-(Y#~04B~8t0M0Ol1$y9uQ^#6V$IDu z6qvT&(jqYB0%Nt&^{dh)&8SMks;2e?Yx58I2p#+Fft*biOp;Dm57^Q6Q#Q?Q{xHEC z$bWD5+4H(}$=*(ryi$9+bbTnu#5+~t?*7bQmi(PLYWFI>QZopsCd26lZoU}FKoc;#}va4JxEjl;3P z)i0tFBe8_Y597s0@RO5KE;%_YxgAebT8+=*DKWnND9?l}Be@>kUwEO;3z7Bl{yfJi za%7`$EIl&H{Sj6bC$?WirQ*{dqa3a=SCLBjXUn$HD^-ffD2LzJE=%6#KT#t@cub^3 zh9Ag)uSH5^_<;;~R-#14AZL{Gsq~e!O@bdKN@Vzf40uJRM1~*8fb%jXGWoC`Z7e0opv1 zKHfRnAq}z=>RQm_hx%L}sfDx$Ng9FdOuWnSe-(T{Wb2MFnJ;fZb)$jN*63;!Xza%h zl-KUEc%XjPNY_8sqs=xO^u2mt6Z7i@^=D<_(`2T(*!+IiD-h^Xcu<1k}StYCeh#V zReK<#9NsV2?biQj-8!uGXsy3<&U)3E?JRZHJCk-h%nI|WUFpWe?D{eF>t~e1w_n9S zevjI)O?XSV?=s%D8Rd4C-?_7rJI{^#BQtOD<+)+IaXTbxN=DePVL$#D_TymZra)~b zPk0_y0iYb7@_6tu3Kj9(gC`u%y?83&xerfeJon?Nf+qqGhvxx2k$9@&c@R%EJk{|$ zgy&&AkKn0+rzW0ScxvORgXd8^Jf6q!MB$0X^EW(o@zldpA5Q~3kK<{GrxBjUc%H!1 z1W!{u0-h)FG{e&zPYXOx;c1Dd6`t03+Tdx6=V?4Kc%H%24o`bLBA#dQ#Nv4lPX|05 z@x4~Qop5A!+;CTs8Up$F;`r+x1 z=Vd$t@C?Kw<9P*75}rYLUd8hop22ut$1?=a8+elOyoqNhp11G}!!sO@f@cJt6g+R^ z8Hr~Up3!*T!IO$-44$!g#^HGv&u#o>O~8Mgh)2aU2@l7hn4Sst-wE%_V2nDSjfEOB z!9q|gGfjY?R;GpszE-A+%U_!tnTijP__g@0*ndN%csUl*lg0d_;;E;xNm4hxL4&pp z<~(%bC(IX~5*tVmr#>hRkXmo)073+6Cs1g(x2$Ol zqPkBe5fy9|38G38;~CO0#gH}-M0LfWdGqGgPM~Ms3gxsr!D0PxXr^{hf09qjB)gz) zCd3Z!qx`1Q{Hvx$^RHVkYJJj(CvgA$b?&d7fQXPeJT=3CDdI>(HBEh3Z>Uc))p*5L zQ}puM9DTuuYhu={shxm9*|FMgw9_cKbb>9FD5HfDXB^jnH9K`9+vtGJ&eKLdHakDT zxN_|Tj?+27SoUS3@z>f&O{<-dkb|$uh9(@>&*`c;+gxgr(d3x9o!0UMIV`t*N$nmD z8>TeexcCPCGmKa!y1x!}5#`jZcEak_Ijh4g&6<-tJ+F3;9XoFCn3GH0%zN*>eQ)gq zMkC;p0ciwttUukKtbdAzmaJ{ovz&i{hE_;4G|rlEUuF@$FkHZfJUzA-)=rpGgdgw; z+#wFi@VZ!O)=p4~qKTi6pYDNQjB0$T(NT)VEYmot8xNWMy{4CC`joFNkC?^LTF8rk z!@YrO(Nu253sYrAt$-auL!s=4E--!4wfFeJ;&L9SqEZp!2$)t)7EAS~=(UC|v50EX zxJtE1w5`$RMG-tL_I|+@N`&$v%#j+1ZQFMj^QE^%irH?b1(fIIPHm&Jt3^@i&_nhJ zzl6YmkR*nENH$2 z?IrcV^(k0KCTlm}KX!~iMpfj5CF4^1SZ&_e_hwYJD13ul*QV+YU{z8rx(u_2U+ig_ zgd(UG?V$*!=`U&LEc~FMiib=*5O2svit(O7DjqWNK!M>HVdjG-sd&i5Q)Y?sf4F~| zKwQcwtA#}>9y0MjhNWXyeTPLV9y0Mj9b2$t?Vk2v+trfPA*w?hg=*3G+{>SD?>LM< z*o_C9HRGGn^Dt{}`;3Ds-0xgbpW$mdy_~oCju^ec?ejIxcITk;8)h`B2~+ICC*1b# z^B1Gj?k~aaEyTI1;4St=xwZ?d?UQbvebT;ck9P)ex`RH&J$ou$!Htw#E9MTWi2Xr` zi)$Nq|Am!Fw4KKt)lm)Ud$@vr#fVPaVg5~SyZ4fKR_NYv?b^0$<1+6r!QweyPzAsz z0wVpo@;QRSr|}>0la}!o=5{1UmrEBG9pysb?i{rj%Ni?DR5r@Z%8DmIGlzkqq~ zwAT-;jYIH2v&HqX^%qvuLq4saQ(Prd{TtS5&{+-Yp5Uk&)I9;I$Yy9>opwqC>Qaa5 zo?xmT)I9~^ig@(8;+);iQS8P9mBdqLB z_%GgSlCU<8Rw)QFQozRu`?(H6itwH=N7%kxV8YH0{F(YAMl2dpAs7D~&ItTdxiPu9 z6>^bEkbI@P67g7T>;+ZGT@#zmkLrBuIs7k<7Y6+BL!BQ|THy<>LT;n$<6=`WX(&)=v8g#*{bodQdJnwIhc(A-`vYNDa455$udw~;r^BAk#`?dW zc~NbrJv_6KhI@J4wQIZ=?!RGHN zJ7TDITi3MsCD@s{m9FBAL~Z%3nlAN=@E(S6Y(>Q5_o}x*twFeIupx@6_b^ZDmzgeJ zFeczHl)S*xj1dbAGInQt%kw<`r{iW_tmRQkK{WSU-axZ~vC$mS)h;l5+G)SyFZfnE z)GSH2zqWIY4fgN$HTymXYCBDx@2v#qAJ&bsIBMZn=5zLs&g=H!lla|t%SaX23A>eb zBE2_tsb6{J_A9s2Y4hXg(XgX=PHT6MO)H|bAzJ9Ih>8xj;@bWib)j4d-iSqRt$S0E zDR7Gxm1D)lLwMRSzm>kJ*%Wii6ncHHZ;roxd+Z6kx^AW4Q2nO zYyN2wF76iJO2={I`sP>-=8ruwt_U}JZlx1CHs>Bh8Pq6aQ^A9LaDxh#^1%%%Y`D+{ zRd1`m@Yh#9xIqOy#oz`NoD@ShsLr^BU7g9&jAxgG-AcnsWXm)%9b!V`R(jo&b?a_? z;aB|EaT?raqtunVm5yAIBFV+uMt-{iL2&uQR%op)}NbYNwP`t&$40-fgOG(I}QhsjP<^#fA%x*3oaP z`hMHhI+%Jq{&sugPqwm#G-`7~zUrIsmlCj$IA#?;n2&?cO9@!^wQ0*eXjjQZOiM|hOFdHYk7>X!cn6Jj z@;m%EJPaF)C4DMXxLx5=0@gR!cVF~n>_L285BTN#f)~oa@ItJ8+V)(zz&JtvHb1aQ zIFi=g#%@Dhav@%SDX`5CC2nw=AJVwsHb1Znw=-X4bucIJ?>&%;-_=VASazj7l!`Tb zSSB{L1_;HtG|lz@L!#c2;Aw&PL)UXmLkbJO{2591Q$rG)zB>({^I$*x z!@?eMq%gTD?%GD2jmAksJKV9IBgI%aQt?Fq%f#xy(qsRZGRcxRT%jj z)+y<1)XzVM{ai&kt!O&x_LBL1i0 z!)vsP3#rm>-^@z>$2je{0`b#nNBUFwNp+jnOU<2}ihZiH(MTxB(IRe6!aw}8(bH3I zXpif#N$sW&)JN#lX8A(jpy%(^pVTmKaW;D8%Ihoh^vYjh`3aB3JoebxXe>!v+A+qh z*d&FjCo7|izfC)h6aBN%=^6M*J#aP}FTv4{^A8M& zr44BRi&NJvb*j1jaM1?_xokOLm;0MQ>msEQ+$mbohMqA!d;WF-KO=RgL0Z0PpNDb zY{a|jEcJ2aw-Su(EK-3c+>RQidBk1tkh>mn7yi_4Yn)z1&%h5^w(b#k zp|VlO5R6#EBklrqp-m&t@QAyGjm>su13AeYx(>@ljoy^MU1*i`=EmgB$;rQ6z``|o z+q#%_>wdd{m0I$)PuHt>9TEmC*(^QzHI8rrzc%2Xzr4FaFU53PomeSYrr^3$g$^Yfe)&SswW@qutt zp8b|qs0+hTe_Lk1eKaX4sW?9u+vKa8;-%nFcOyR+hwHFfcvxJ)$B6NwEYkY_h&keN zaihpTf%Qgy?ryvubHuCS?dC_1+D8clHy}Zh!lZ_(AQ7FM%(v4d9OGev+ANsPSBWPQTgsDQP!7_hfEv z!{~=%?`ekPjQn=#{nGF{%g=rH-P`ZBn}wAoJoM1*hw^ig9fhU-?G0H|sGG59k-Z4; z8=9XRA0HOKRkO4r?cz+f7X|)>d&I)+nrSYXL$Fu@7e~2(E(y4bGt9iXSkyr(X7;u& z#_~RKN^w6dInxejVo?VzSN2QmH+!2t!bms%p%2nvlr}~CL|dtC(byOgI(~Ow=G=r4`;$XS-Ft7zI-GeU52o8? zE18a$@Py(3fNBNv`ZODO%B^VVMU_3mEP#xEl_UaFVaQIhUg(2!#)mA=JhsqOVP0o@Fcc@Gg z9rFQNMn-(DzB2Pse$0FLjeBJlH0AuYy(wxf9T-W4*0Jx^YHCkt=i6&9YJ;><8YPud z@fW%0b-ZXMT)6dX$qz~RjzR1|*wl@B43@CegbLRSLp4{F$5^IEe76ukRbLtd%{_{$ zVc|ReP6w45s2>?n*ZR(gvzUd5@I19!n&#i}@p$aQsO(?DZcQvXvJis`#v5U8WMlKF!;zw4LmMh^HJyGwXl*ad%Mmo4mqzp={} zc7eXtOfbL}cEM{Oeb2FlUGO({*}^XP8@p^_xAX}Cd%%D_@f<4&4139GEupkgDCF3vf* zF42t3Xxw-etrj*5)Cs*T0Oilw<;(8gTdjpIO|g#zBS*R;%V<Qw!QR zmm&&VU|)I=i@O7&c3mQDcPzd<<;VNy)ZAgC>S(_z+cBi-??y ze>W?P;|BTypNBt`PSEB6jv`2jrZ zXwqY44-a(Vh2D2CRG1)y-gj_Q@G319qJ$YD)q*+VU9Daj3k(Pb7Rmwxf`Nsyz<^+2 zp)4>U7+5F^3ms0MOd8M@;A%@&#%w+N2Q=VVuoRQ{$g zZV?PsCMdL?;%%pZztF_?nP7(Mw`^&j32JFg?j$|gKGU5ME*8ex|3nHqgi_e2^7DCE z#c$;;zKFlbR}>z`Q7Oa-@q&D3Xh1Uq*e4VSUY@tL*hK{P;GZon71xWq#bYA)3m$RO zOZeW0@lu9FW$zB@C+RfO{Gqa3M;7E*xu-l>PL-$0us~idn{ploEHBGsgM!9NJ4I5G zl#$A0WuCG^0V4I=iVrx4uId0)QGLKU99Ic9|qc&Kp+v_VE3QV&B4o8A2`aY((!C3NKmaKs_?8kcZ9 zWKz_b$4QaLA@wk%aFeeh5Qmg7q(g+U0x*Jpj&MjgCD0Zbc;VVtMGDEz7h#pSRirI4 z%2qrqHIyJmiZ3hSsP9PrQSkeY^H~B|XVpLXN6WGkt{!Rp&1h+me-wrq6AaDBGQKf(8dUkiO{0p*o6XD) zW^a@HqYzki!3QZYkX#SzRco|G{!v(EZN&j;k#*4u$#(hUzKu5QvkPp;CQ=?j6T9FH z+ZpDlck)~m=Yl_-+ql^k<+gCC%b)DRcsIkPox>e2tqfkrUJDmwcf$fM$nFMTRmzBk;Y_Wp0UCJ+79tMylqYBY7Q_JGtFenA$u@eW1cfzGt&B-)za#0C0Z~v(BVB} z0j=Eeb~C$!-P;~wkF{ZjP2Qj!`;dLgzG_!;pq4`p*dETS&S+<}SET$mxux7$PL#oW%_Fl-rc4S@C?zy;3^SBPN@(I3YN;qbxsy1a zs?Jw|BFCYLV~Ek>wa~;d?9;puCQBSce|?xviQ}dEdVRNkOou;pKS%YFk!-+tBg3E^ z)ehq)6{Kf^1mCsGOpvgTFW^J%($HTRhPe?I8`&)!6W~wbw!n!|qGy5xUmsnTBod*r zR7VQ*I>NR?1NGt5E}cS)CUgQx8k6^ zEGt_UEdsBr<3)>LpAn1}L4R|Y8JdX$YUzYVi(tGJj21y<+m9Bd+S6=UV6V1Ko8^AO zof-}_cGyBK?bA|o8rTv-iBsNXuvzHp4se-9cbWU0yT^s&ZrMHn_cyL3*O^P?U??|% z)3_||8*V2@tBK&PCU)Ryh%%Ok8T=yN;B)vx{3-q_UrB&kLK8t0s24I?pk4^961EDK zP$ba007=8aZ*sFf3+xjML`S5R6*R_3T_or)(N6blX{m&>Io!g6Kc(9eCr8OGf&X9FETizkF+#^(0>L`LjN~FO`sxnQ117t)W6=wVf)dN$N(;sdiT($LZ(85&e*ksK963z!LN(x}YP?Vlc&Qo|s!3LX zVCepu(sdR&2xXxIbFt-VCpAL-*9h&mPS)q?D|8?jdMFDW2!R<^huB$66z}#w?)E?K_CNmb>wjD;>wi2$gp#FZ8NqE{z2+o@ zs)8{BQWK9AUlJiXFi5T?K@&+tJc+-Z09z$XDw6!|1c=87Ps(50Tl-`PKBW39FicSu zS}k0!>{e*M4{j?#sT2esQk6BRqlG@CFbuF-3reMcKv2YiVh^d!Is_k5T@466q>dX9 zd`Jy7A^4EGi8hYFLu!Tv!9j8@8-j!6RW<|%$uSND2g&;!2o93_yR~s;;1;6RW?z`- zetxwqd4Yj&DBW6us5QdDaRdk0dVz8TXD?qx6k1j(h1^eLvi_{Q^*qLYQGl^-U6#ul z-Vn#l!uhkoc_CD�MuI zpu+*X(7s?-a6AS&40J{~=?+7D5d$5H9dN6%IWq=2_)G=HKnD+k?lI88 zgP?m1bnqbP9s?ab2)f5W2M>boG0OM8@PelSB@8c7 zcwwcyMLr-G%7o!13UA@lN;hSo@~)mf3}fCJ5$)zI*)}^}IpvlG<}e^UYwREle=Spv zDg}eO$8_&L2PL7y3zYCNsklQmX9>nH&nPVRFs7+G3en8(sw-6>5nZT<4!UUrwNMWo zT(#f&3L|>;fnGLW2VsoRT!DKct(^zaUn+=oMKxjzq1M^c8zB0F&%x1%6 zHt>wq-C{NyCbNMbtY5A3Ryo`A(80_0aC?&Ng>Zkd!ME8knGL+_%yK?+$Y#T2HgLa7 z5ETMhGMNo5bl14sU9#CQnGHO_wdY>s*xth@+)56%a0j?Tj%+qeW&_>$H>D9g*=(51 z2J-o09t5)4FqsX!B}^1P6qX3<1SYeATSA2Bu~SAV1KWDEtie@P+>oS?+W@h2=~I|k z1dOB}7+e)IhgssGXFOKc;Ht#R$`jo-7_c5(l~`GKrsy4`rDr5`E7b0gDSa+|EB#&i zMLH`%sq}yxEkA|3Wqsv0<#%P6C4VNbmA{vd$p4UU$oDJos1o!O!Wt#$CxrHD&`$`# z-$geKg1?J=4T8Umw{!^pE^g@%VKB>)Cpm)P@1nK|O-*Jw@+3zP{9Qa_LGX9+g9X9g z#mhDXe-~$M@GM89w|LWe*MZ>g;(ix`zl((~1b-J#a3kn5nk1s zE7k8O-6}@D4-7a#t0Abj{Naa1KMXj5Fcs8W-oHC$_wE5FFgALOyUM|Bj;mIae}!+) zS9_3TIpEoHJXsDdbun9xC(8lPmgC8Cz_aCevK*jQ7qaDevK;ViIi4&BJX?+@%K^`p zTsv*mcQ9Pn&8o-7ApdCZpM$#TH6<#@6j@N7ArEC)PWjwj0j&z9rKa=^3Yc(NSu zY&o7R2S}4Zwj58E1D-9%ljVSC%kgA6P;4<<4#{#}=UzN?74xsXi5~*HaZ@55BiHi} zdW@#tYsZh@IG&II$eHTBmN-*6wu5T|`MuW?XDSZ^7?N#$*JFn-W67IfbU&lB?tK46;^WKqE@ivfU{z-H-+h}S$YYfD74-04Nq?C(KuU*?^5GVsj^#p;6qasyBpc3WEeSG75exC_1noZ3L-;6Uo{t_HEgE9|z z%?ipq;F1-TdBFR2Q04*EoS@7DK6ipL4|vKA$~@qEHz@OfUR+S-0l#rUnFkOvIaKBW z6@;M71L?{^nFrJrgE9|TCkAC6&`}D?Jm9e8$vmFcx@ieA1cAsWWC#M0-&Wv#B`EVK zWI*ITt2brgcCSl?39Yx^ic1(anz4JXZ*7NbO+ZkbRE*Te5fo?RnuzDtW5|9s&V_Fy zJr=5K&b#Hb=e7FU7?XZOutZy@g}Qs7x!zF^b@xE7epnB6_dtU2ni1;mffL3hBh=jk zB<~4z_dq#|Hi7&_Ajq^nw?f@L;4$DlcMq(!zrV8qbiebc^P~gMIlY`vcMlLiB-Gu5 z`tPM9ey7QPlB zS2!&EE?g7t6Kji2#b-rG5MLAD5kC+=6~7Xn)7YLHtdRXZH_Cnh zTix;Z++dFq+;f8<^5duqLFC5}4aRE0><0vqA5(P*B0nBBfVeWDSQ#L$OlbB4h$|DC z{eWX;F#Cb)tikLD5LYHN`vKGJVD(lok{dgP+}F(LM09dn~#Kes+&V_rTBYvFILn+u3bR z7Tp6syT_t?5NQc6%kHu09uU=qwzJPzEV>7Nc8^8(z|Zd0a@z6@oYMF|2=0 z)2+hs*fHTcaJ{)9+*ob~_it9JSu+bzn$C~rDSyqHS>WfdSu+b5w8dk#I07)9GUc!T z+PC)d*Q}WZ1lVW!Yu3yHKYz`dS>WfdSu+d#{56YTgP*@<%`EWq*Q}WZe*T&@v%t?^ zvt}0f`Rkin4Xd#Qe*T)pufgkPdCe^FccWPRdJ+-sE1D0REu9#%%O=9T)XPNNOBXZM z%%8CKiz3{1ua~)IO`SET{=hX+qN)^N^wPX+T3b$-k6ZUxecgc;Fdw5=VPb*lSC~x4 z2+YUm>looNhkT5_juDuT(bq8o^D+85MqoZhU&jc{$LQ-A;XFq^MqkGW%*W^<%u0D+ zK1N^12+YUm>loolk$jBaQs^2Hn2*t03T-a|^D%l$p$8;jK1N^12+YSAqGJT*QT<-U z*D=C}$`WOr;_DcJ`51j2BQPH$(=k47KBN^tt6^uN&LI2(mByyu0g>d#YU5|({%oB= zQ>PY89h;6+gF1trd~)NHW3}&Q;-6ccLDkDwuRdSIaPV_c|z_m9NM@^n6a~rNHaT7-hP$Q1SW^KroP+ z>JzHhkNBT%T`nh96KisQpX#5qE+UyskV3U4Vth1lWp&D`b-^yZ_wHX&>J-L`2gFDAC1uG19Uf;`_p?qz^~?cGxYfY z!>vhH=<@;Y<9viPJs)6}{h1y5d;oesggzg@;}2dz{$NeF?!_|w6#l_gJeXfDFZwd} z2`e6K(qvKX2zq(eYVf@lbV@=f51(-O z@S9%FzSpQ}JYlpq2!{`&j48$^2IJuq4j)2!_=Lls6w1TD|7w^S7Dn8T$lUEN%0J4u z9qyVnjN4%*CIbFR-p*`lHf;(B@3{PJ;l;wj-WP7qCV<6N+(NkgEjFe=CHf$aX>Mm; z#fI?ZO+@jyiprVWnMCm@6O-X(8@o$gw5W{YaXT{{0Y_}>Xw?tfEFe#5sM!!cwu5Fv zsEfU>P_rSd`-^)K;XdXzccG&jG#kQUH)uA5*SMhB5H4{+vmw0C2hE01O$eF|;d3Eq zHiW0dpxF?<7lUR)=p_ZshQMYj{zwJbOvN9m0Gp|>k;(`qT`BxnVP?a_uOf6LB63%s zK7DTM<<;tH1NC1R#-2Z;g@0dBueP8J41&o3nv9;Cr4o|@krdVDx&*(WiRo2*%3U5r zT#C~;AU&rI{SetIwQC%?oP?j&-kD8zUQP-}!bVc=Um{GVrLJqRq1#&qOf)_;mKf`d zT?P}`LWKF4+1%`CdLmo!;NxEJ3p|sp*ZTs`Wb5_5z%$u;y)W=gwqEZGJd>^0`vT8o z>-E0CGue8*FYrvZUhfM$ldaeL0?%aY^}fI}*?PS%@JzN|?+c3Wm~6e?SD|OJ-GyAV zN6J6)NVUZ`6t7(lLAm@c34(I@J~9O5^1lyI@31j$_jB*CF~GgU#(>kv#yBN6egm-) zZW%WMJ6bMss;ZLk#3i8*p(8Z%*fms!ywP;_B$F{Rx(upxvr?tYnPq$oaoIAel?LPf zD$oKe+omAxQjCfokkAEmY?K8lRQ)v=rm5O&&7)BLsR2=_`~~#!Is_?Hl?@0|s1_Iy zq);_BA-I6P*@WN%dRGeuSc;WqePk`OzO(jN$1ON#xmKiIX122v?V&bIur)i&{>I*E zAGOceH*Kim@J=(QgVWm?;*51>IIzeuoE+znbIQ5uRB~&%5DZ|ia$&1$xuMb{i05Ra z=Df$v;g)k7xg8Z!k@InTAYwjp?yk(}jM@1A!GL&oWhR*P0uMy%CB1-wX#J$u-IbYO z((5iVBzR-rMTP`#Y}m&Us4tB7K)ukPAI7WvY~BO)!k_$Yo)e-32I@@~V7$Ocy*mU3 z>P5*GMKxnlZ_7Zvus~cbnqr>lfqL(*%-mg>xr+?BiwwDo3^{fe8FCjH^8Yw8Bz~O7 z8h{mQkTn2pwV*m4_Gm$MJR~CRKJ?)PXY`;t9>y9$bv%Sht_hM1jFRlL7J>W>p{zyN zXzjBYYmu=Apo<-3Ey6K7$XbMCC&*fa>rRlh2-DmkYY}R2LDnLy;DW40Xv+s#i@@Nr zK5G$tV>M&Tf^V#5!s^G+Sbc}Ji0z4!B818jlBAImFie{-tAy$@VcL938!$|pPiX^& zY4a&KM#pdMN!yBPhAVTNkVHkKN&-q>v%GyXJg8=M(swlE>ie925U$D0|ZZf2W1 zP{wPXHm{qNEl;^yracc;?gCp=Zfv)+B|FI;X~SfDo*k;(1#-WTc6orKIBCvD4lHwm z%3UD$ix(51lmLXr1Sll{p)mp4c>zXV_jg_(G$ueP0brOmf9D0}2!2d}QUXv<^kV|F z^8yUh=I^{fXiR`o0>ChB{>}?9Oq;*+0u0mUQ`*Y9T%kKJKz-KGofjbgV(88bwA4Cl zp*t_IQ#-1K?z}*6eTW{q^8%;ztGX8xpp*cNHl`Z$4WH760-%S@hB%+}C~Yvu^aMbT z8D>3b0mHQUlr~sz?Y53tKBWy%PHQLIKBWzQ3h_%2r40r3cq3nP#Z9b(97^cmqv;o7k`II(bm^Po%_HQ&~ z<#k|~HlNZ4%XGrDk>QR}+JIr&d`cTIOq)+>1BPkyDQ$4dyo#7MpV9_*1}1+|+K`A( z3QjU`GD;hem1(2xQ`&%G+I&hItam)?CZn{WG>kB9KBWy9rp>3c!C)?xV_0yL%i~UR zaG49|Yw$j$4H%})r?f$Jp@Gm=@F{JuO!!XNBlwgyXj!(V>{Hrcr+8E(XSzpegWl2* zX)I>_7D2?(-;ZFj}4}&zF5l8&p&tRvIckr48mNe$zBCgC3#kH4;Bf#i1BPkyDQ&Vjv0^pd*Z86dr+E--bepVS4<0O?WM zz%xL4NnIFh6Q<2i>H@BFAg0Yv>H@>G`AJ=1m^MGD3k=idCv|~g+We$0Fie|IX#<97 z^C@k>Fl|1i4H%})r?dgXwE2`aV3;65f@PSu3w=33OTDum`f`Gu`cXafMAQ9DBF@f6tQ&{3jK|*Fz=AlOi(e0QgcwHj9FWa&Q&}Omg7k+n|dQif>zP!$!mo zgi;3}Sqdtppx!$B1Dsm5V4Y?T3n_B=IHT!c52pR^L@(?r( zV(Om^gUNzFw}7Bwu%`&VVGv=YIJfw(c|;fY7>C)ul$987fgb92;vVtt*ZU4*_0HFu z`U@8KU-k8tp1<0@ef#8hC?^z-$=P^`_@8&t*f#i&t~oXtVgLU?V;6dluFim|I+y4n zq_}Z`G*+n7;!tUNG>%ib+1yg@8dd81%c0*AivdjN(6aU_an&lo4ElbqJU^m3PpYQQ zkDya*l?*TXKx^DuDE{99R zZkcusqd$-rQtwl_525uwc^sieNWD+xKCBS^dY{UDXe;^kK9&0rTJKZ2UuM;2jwMEA z2Br%4smw4|2~wFMwBDz3A42PWD)*tG7Nj!6MlDEXhAw)L$_&SJzuu>EA6UK5hQRZ2 zeRI-v!>ji@e|;lz$Hg5x6080Zh6!buimLUvGK6ne6I@JIqPlDmxQK^Ao7n~k$7Rth z^SDXc%rho+uU8yUGkY02df}syAAPjPOg)U>t^qZ7 zqtz>5l$rJYH6iaM5sgV0=i6$RciKe$F+6)f4dh}(Iz2aB#ne~!7vz81 zjaJTf4l2%^QqC8n=n>Nd2zbO$ zUIL7c!|D+E{>o#J<1QPa8Y7&e-cGFiRQtPHuLq$@vGe;zr{Nam!ij*4gU-_fz}+ z8WrV60j(CdX;Y_7+&jq3XsJ;o4X!%>0XV+2!I$VZ2dq7>^|cd>xVO=43E#i>{r6+- z8FoGFCTFi)Dk5YG7sUD+4gXQ*#li$|wo&LBJG7@&yKyu=dLnx4(Ub+wpB&U}y zgaXOwr3;}za(d}PD3F|9x)2H^CmuPlkEQ?81@_eSU%C(qB&U}ygaXOwr3;}za(d~4 zE@q26ME269AS8@5{aDR-v(PNm%`RmMP`4wx<_|<|`tZXKZ%d7P9Y3xgr@zrHQm>c0 zz1OWwe8NzmkdZ{_jAzlY$~3P%*y=_@=lf zLnk$AQ*MvqG+HyBrGBQCevyKLYf5oLFZG~WDYJc#FVtIVP4fw}wCOa`iD67TqQ-P| z^A;pD)fP%MropTpZzi^j`@P4mw1F8Xdd$`IFxq~Pe%iDa(qj_dt9!X$pOn++RQ%{xf$9rMG{WE_1s*X$K8dKkqKaek^ zJ^pyu!h;Lc7EX0p{Qi)SA$q!dio)_5h|jSovMKrrf92R-3BNstGDEo%g5eSL!zPNA-jXm(+W-N3=%TGia`VMSEL=_qDm& zm)a)n2klqwyjD(!YI=RWjqdNw!RPw7`rq|m^s{=Y{(uo}z*9yiqpv}jsaeKn###dy z-pQvsK`)c=PCnfUelrR0{ znXHi34&h_@i$vO~KPW`Lw6@0|=T0LrEVAE)sPy!72aX&$vcC`RcXE`hAAqaRX-%Jt zEsad9QKJT}Ta=zTfuCWRHER~EZn~?X$HXBp7&PZPatzbKC>`5#xx*Y`I_{~_J-%vH zzA7Mat|H&M+JQ*u9u=9`D(X$?T`8TfD>RBc(Bu@FF=MY}R^PQNZP)5XHHClh_sEaP zk2VoUied$~Ng>`#b%e#3a>fdOk8}D`r<0vJRciEfkM8wwulqoyMp(_n3+7`M!uE*Z z^i%!rCEEnJB-|rDA~q7A5xa}8h;NJVzBpI>Qrsl|ApR8^Ag7%R1xJH-=h5>?) zwJ)>{+Fs4WLqT1=mHxcmPxtUp;PIh6JQR3*C=U+>hmGG2MtHkmbaMteK!mqDNP~uZ z&3seE+YoSLw~bI-?`zD`7i_~%VVg>gP6%yw;P6Y2R^zxn2yN{x^i0=u!2yl%HRyS9ibhAzLOH@IRn{RHzTIx|n>SH4oC zL4(>3n&x~{`0TUK=G|E9O#02CWy{kU%0azlyVR7(fm_Wwfy(|5&j?i4gP)s9u=Mxo)dZruM1-Y z62t>D#Q!E-5$+Y~0tD{{^e#Z~Zor46$EByGZW0WXMo8(>$I=(l25GO9FF~;ca#gvm z+)934?kB$`!$kQ*d5OGE-X;Gm|ADs?uK=9@6<^KG7U$;XuCU6)lZW&?x5b^YFNB&iY3#e9%+B={noh%R%q%~1W{E*#qs|)! zIisBXapwEqpjF9F_Z)dcC6jg_8Zg? z>Jgy^HAqg9<9S4=K@A>DqJi7C3?%`f9uaC#gX>2A%>Ts3FwXN)2iV^@z|n8$vxI|3;u!N$ziD$Rp5nh8~gqeemmA zy-zA?*H_@ZJZpcS)SWwbUf+b*`F?p;<2R5WS@vZ7bnwN&gRgJ8qMyPyci6Ek{UeKz zM0>2pN|*{kti)_}yN8uHJtiHOr*219??dWhd`g`-rIJKjGOPEAiP2-=%{Sj{m-}Xq z8RCo?^kz&`B+UXc4Oz5dk7I3mFY!*s$qEUoK?7Laj`=Hc5Cwg2|_1?`l zH*cO(AM3A@>Ga2$BXkxhOfXoe{^Du80;0t6Pf|fWUzwp3*(gUJFJ2cbOHe1ED_S5G zt}fFRwNR?}!9U^c1=53ZJz3Qbivwj4L;*oLxw-A+k`GSf%f6+&;Ki3;ez|a?wm>G8 zRNlaO^X3(wp;|640b4X9&h&dbt-U_11(xw+wGGa@-IIp3#7|J-puC%Td1v}j;s40U zM;@84EPV}Mp=bI*)!F@&pOrt9TS|mV1O(`)`UnIfAi!ajArNY7O|@sW1Pxx(=#lcN z=BcgWlE%#I&*%I1F9MIjW)&$#>>WVW0H|+z~{!d#@~%! zjI&0m@qig^!c%4^v#q+Z53wl|vTVt&0)s!Ee?T>t4I2{e<1#e$gIe!zg=-{fSL9Rt94QpT^2ytl-gD={xjR>tW4yV`-aL zTr=rR;_~GM%kzqHLGDbycistm=eonDjT11-wDCgz?@?zGQ4+uLLV9{i`k8+BG}}~y zH|3dr;X{WG-RO>&+li7mz>OI8B#sPfa3i5=NhX#;3PVqgx`Stg$N8uEZu~&r!!wT9 z!0+Yja>H7V969nQeml+3kMpm{eS~31BnYc^`@+)#`+{u}ewOq9kbh{5CHk;dl`C(o zTo66IB`)p_Yt^89g9f8-l)K%^?bZ5)WWvrh z5Y!tt7NDIV2}#08VX`n!Sb_H+kO#d)C@)qQ8;EVit|AN&6){cxNL(h;Q0BM@=R{XT z!MD^>>MSKnLnW9XX;PN-jkHrbDxHyTN)Xih%#dM`Y{)sXr}wF)Kv3_qN`au>_@CS^ zJ!GCT1j@=Jfp>M=V@}5qb=0|TjL9( ztmU8JU)kqZx|bY}IevUu=D>jiiw@-Glzy>@%<$BX35{4$h5{%=k!PGVycyxYTSqP4 z`7Pco$8O*UdD2dk)K85un{n~`Uvu8Q`R==QR?Soveenpp3-l*w6befRxogePR+ z|Fdn{v?)Gy0lUWQb6PIg~=le}S} z@<(>7WPDvMdUM)IY=W%Zo3l6xUrqS~mW*A2o%n);wQJqA1PF)3#IVFVYZ@8P7~PFm zjJJ*VSHashV>5c3S_nQ+Kh`$T12uOt*5)n89Vvh0NKRQmrMx}bdiaxY+#8;(ll)b) zvaE&6_0^e3lz%|^_~YJg@7{n@26$lP0}p&W_xIUYbgW*S+Ne>ZlyO+6c2U|8EJS_{ zKVPdCH%e-=ZN&uR<9T@944Avb0Dljkt>J^ehtJmV|DR(}Qgh)kqeS?4-rBLXYlt7u z!{b~W8SsX9L%iJQQT0i+ zz1T~AU4=2~o5n{Hb(|Q@7H&yFnk~$fiDtX0cWIC0E~Py-$&=2@<&?+t;ratZjzlGQ zSyX<}A_~8d6Je3ESb>1WojK$& z5gT(j8$YMKG%DhY6#Q(pQIntFmVzJh&(yW*_v#V#AL` zcjh`@I-8syoL?O{@04?^x%J&P?hEeA?r?YeBsbIj+$EOe%)xc*>UE)V<;w4>M#tqM zb|&$;d)`fcUd47c;04@PEacT*TnDx6)*dx#(WvAXu#q~A`vzjm$HpeVFfeIt#Wi6O z;>;l~0?Gluq!5l*D$Offax|_4MM_eq^OM!CJadVIClmKl>f7J@U+lekln>{&|G&E% zji3<3T;?FCAjA+UZ3+@92!cpyF;8WPIi2b@##rWrpy(LVgwjnr=F%-%kXE|Qg6hE# zLYHo18@hh`=|`oi?!CWz?!D{&zQ23d*B|?wb=Fx~v6lKg&$IV_zh7^TsMOaqo7*9< zSY+hh$Y}1bI>EnAu|U7Gw*dr8BkjN4VPtqU!Sdz{1MQYB&U%X#&^p+n7~fD@b0 zvbk#>T-9Kwr^*Ckf4sr@Mls`JV%G4t-o+upxn}mKpMIMAW|@cs*>jDtFDcwg##Ia; z)uC?joEi1WV;`S@Hq4wklVFsd-r&1^(kcWWLeNxi+LSyyYL#lpH*5$vg<8Nb75?v% zU8WG(WvqS7F4h_6-Kg|!+xAAj6O}s#?0Swd9SOM0gJ%1iH9KAdZ|7Qp(}Si@4-pK5 zpa<6*6U~f>^Y}72*9@=OJrQQm+4D_tG!S+9RP$4(S~S49O3CCI^{?E?ycriA9UYY{ z2o;2Ljmd4pzEi&OCDNHknXOaE1pQpIQ`x#pU6lcWr@zp)9NWP3J_ z`Eo+ZJ{Az^VG#t+wjAv486XWrm3_vJ2R-=JL*6eEf(n5f1p|wn3p#hMFhc{*7cf8O zhvM}^%Ouxd#hhl+7(%-#Qo0_a^7ne1aRzOEsV1M)Ok5 zC%Bt1s`-Qvp_|~bSIls0S&Oj~?Pz4CoVCbUb+QV9)y z2>UNm0!TyhR4Zjc&096}CVEHx3w@OSiMB+C4f<~VH~q4HSI^Ol8dVH<&uC|SZVWTN zF%}x@jM{l`wQJYz=(CJVc$-^*BC~_>IL$p3cM4zqx3_dIT&$Q~3@TQvh}*lSWg8Xz zCNEB&0?eKa3}vP=5vIySGfQ)Iz~GN-9&Uj@uKBqI{Z-izd=o2G_2Myn zILDnzRPUbb)r;)~I4W4bs@>IMTF%!O2s4L-GG(jOGBsJ-tVWshG>FsAXkOtc5alTG z+&PvzNYx+cUg0Q=F{T?{;V1-{PQEX-+`(e=Co>iWqK@SbDq9V$wpLHevD`tlb;LSn z-Lf3Z-T(hOjPIo=X&(O{(qY(gG371M(TDzX9mb2rk~)OQkmk=<=aXG@dF}TRWqCwY z;V^8C)LeU!Ummf6z`Wz)0^;sTtu>)7`EgtZd<+pgi1Iusm0NPIOwH=EG zyvcYi9&32ec)!I18nS+i2OMF~u|z84SUjK`=eKx3I!82LuH@_fIG$*})-=Go32b~} z0iI)ElN*M-No+Fjz$+4LJoa+MY`5?dTEm;~;ZMo}Tz5SB5ZP5WIUvc?L?I1Xbbq9Q zH{TSrY137{b<5rLA2(ewrj?K}Nx*jJQ8OZ{n*7Qb=6ErUZ8WJ^A z^CF<3uP*6c1T;9tAjcO3VFqagU40l7Hd)g}K+C5m;`(v%c^o-~nV^|o7Ia+;c&m%$ z{d%q#R%!;WB_E~Dn-?%I6_-bq?S?k>f`MxWqh2s@bcx*<>IH)znQaU;gHbOSxMncw z1q0U%M!jI*n!%_S3|uo9^@6>Qtn~k#gCh!b{?37NzumucaLr)!pa9nlMh^;b&0zGP z0M`sgyb0DHG@$v7`SqB z>IDP8ICQT9esO3A75w7RODg!qp+hxr&0y3E297win@+u8;F`gx7Ytl881;gIYX+lU zFdz~+uR;!7GZ^)Pfole%UNCUYVAKl+t{IGa!N4_xQ7;$}iJbQh2&6IaD&)X5gVDYK zTr(K;f`MxWqh2s@&0tg^2d){6_66XY!RQ+hTr(K;f`MxWqkRFmW-!_pfNKV$eE|%Y z{ck{U&0y3E2Cf;5_61N*^}hkZHG@$v82Dow_G;jdZRntbKepkL4z3xDdcnXS+mLO5 zKel0x39cE8dcnXogHbOSxMncw1q0U%M!jI*n!%_S3|uo9^@4$G2BTguaLr)U3kI$k zjC#SqHG@$v7`SFI>IDPW3`V_R;F`gx7Ytl881;gIYX+lUFnB|9%wW_D2Cf;5dcnXo zgHbOSxMncw1q0U%M!jI*$7u9Y!H?0nt%4t;FCX_S%Nwa`DeA6&f%?D;)>n*F617wZ z<_|hPK5FB8%^!4NIFyA0E)0jVaKMG(P!^Ojw|d=2A4sgax8Bm!d%?EV#&^fk{rY49C$;uGjwi|9<~HIR5*Q zrfiZaDtO1JWQq#jF)Ep&f_IEc+-xw=o@jf?W$?%jX1wGw@Y>mkn+?2nHsWRjubqv! z*`N`s1-;}lILck%yyPLQ;Zujr0ZiJJ|Uit z?@L~rJ;X}Kq)Q%~J+zg3%3hm2oRe?KUYk7(R3<83n>{>If>p209>^x!YqJN8-PVZB zzON=}5&yLScOU`olZ|=C8bix{ashpFxlb+_Z_YMX66@ouCl}B+m;2;`<<@3vuXWP8 zYFSo*{iY4o?f2~tb{~7BE!&IjpKKuez)SXD_Dh>#Dl-ikXv_3u$o6FcL$)tR7&yn= zVzQYxSVu+$1KEk}9M+MOrsJ=g4d%*l?{JQc3LG7kBclRGN9D+!ikZI@2htC1)t>55b*kz>`r({ToV4AdrSbF?2d2h#r< zoiLG~!@J1m|1;=>*Ze^@rtmd?Pc2OFu4D)H}j7vQ6S%#V$d=y@2t0? zi+rC)tFUYoyi+ugd+UC)qVE(98qnpf7=J#=c!_Xkb|2&EhSKzFjon zPFB%?$Hju4m-zwyvfxL^^A*ewDD=%pSQ1cZYFVf`9K@f30Fp;Rz)-l>x)NNRQdVQZ zhC$UkF<#Kf>ouyw)TBtw*K5>~g4eP9dX4JL^yo+r{AmP3E%2uiWLw}*Bbb96HG7+_ z+b*FB{AmPH4EWOsnzGaj-tE8r8jGriYqRHUJTi$kR}RB&;quh*z*Efw5Mk=JWft`-N5TZ@{t z_HuBNyUJM{$rPcHBG88)$;&*+6rqtK;AV=@ND-JSED%(IWQx#85pXj_Xru_ZnIbe& z1l&v!5}X?)!G0-GGNnw3MmIN=;bXb4EXfh_Qkh1Iz#sBGnF!>oDl}3AhAUyHs9vw^ zRA{6KJXZ>qtZwbD5urcylfe8Geu~m2)LOdG*Sdk>Q{A| zDMBMfz|9n)ks{z`iqJ?Aa5F_{qzJrW5o#dG6rqtK@T0ZO(k+rHLL)_{)UW{MB2Dcf%fDI+Mb1#B=!@(b9YjO-V%{V&de%1KNnFv`-UOEb`=OP53p zP9`*K@CGLn{v~*WlL^fly4YXYUYa#{gOiC02HfCeO0xzxhLfgnf*Zq0Q#iqm;iNQc zh~}IaPMX3AZVV?~$$%Tf`Hs*6S!X~pp}dh$kSPR--bg5j5SNPHNGK>KRh7JvP_SOw zDS0EIpuXH%_C`WIjg!yFH@-#pIP9=@>>!XAxE^%<`VILl#bMOK7-hQR&7^<;^-a~A zNdb%1pHy!q1yt4=YTir=h}Mp1-b@OcKuaM8o$9$jVYFzxsIT|gg>*8Aj<%x#9Ruhp zO-=8m&(oLh&KH5c@ggtBA~IvLeoVil|D~T=b0{Gp;pNx~(ddXu&DJ?1#OP)q3DDk5 zC>9_HtUv*Cg7>E6vT2WTaNS9J^-^yNCEvLojn{rU~Dh zg^?|nh*pqHq|}zQ;BAX|W=Q4~Ibk+h;ABpbP@AfDBl{`IoLc%P(#haz(ABGb?dMk8 zn`^BD_9+`u>_~f;U5cs6G-EztzGPrDGmTlsY-08>CzvZt1_QtrXREP|+4gL2b_Dw^ z3yauDb{Ct#US#jEFW4d+RN@+NZMYuXE5aKGJ2+xAzR5l13i9RodOWn`yYd703H*2b zD*hM#5D%w$w5jmE4x1T@{%9MJ3JHj=8C^N~L(I0B8H&)D$_lul>~!4=4OM5|J5uSU44j)Y zZ8>`50ZoiKGlvl?&)m6lZDQDgs#UAzM68I2h#>UXoSB1&y$7*!FCx@iHo*l#<>!?v z&m2Z5hw~oHn-`K+HVVNOa10IYWww8*-F-fPzB!**A7>6LTGTEINT-IBl++Z0T0W85=euOg3@uO~v%p@o%+!iO77`r8vxnp=)ry%hqr!}t{gJR3t5wzG)Tej> zu3ZvKXxTL%)T}vkSn=r4&`=0Q%kJVsqx3>LG3_6Y(Z16g=xzS7&{%yeFfbr+`I2ec zyIL#lg+5k4twWmraDRV;U?IOY>lrPL`(2GTxp*N0*d|P{HEWT3n;D6JEHnV$dxnev zix2>34nt?B0byZb1tMpLE?*w7oWuZ7;~o(q{4Wlke)^!ziqP$Gh>e4&=TT7`W6#&o#Mb0`{d1U3vOZ_{iewli6 zad0pjOmN7Lb|;T47#56tt!)w~hsfRJfig^#=g4jn*CRP4Sji?2s9{AS@F24RVb*|L ztDL@Ry863Vz!+;*Q7l6V?T|Xegev+kMvU^Sa$Z@a)i~H+gRiw&8#6QlU;tyE z_PaLvns!?6ZHzcMbm-8e_?(Je2&e`x7CRR)j+_BZ7R;Ns>9kU}6XNG`Hjwc^RyIoKXNn83}TQ&6W)Ypm(|m^(4Xuf}-;nwTBUFU(P9xVgmKVD2{IH`B{F zYG=Xc)-cOu9G$n|PwSag$gXI=YqzpLvj^EQ$)0Pkwzu1d?PUA9{n&>5Oj)K5^C9yo z)1Ud8nZ>{l%ogSVbBam%f8%5U;bdK5Gg#n?bJe)U9JJ?pb0fHKxkX$gw~I^Q;39X2 zd%+dqEAb8ZHhd5M#Sp%tc7>#^z^&%Zo3}VIr9R@FatbFS&VgJ`m|${@zr?$b`hPzt zaIaMEyQj^fn~9%vBVdSeLF2~t^1K1yo@k5SH^5;6bm%VrC{6xycj&x%SLa1VA|*0* z)Vg(h*F{B6n2FBDMv<7*X2uReI73uq|LF3&rFX~SnGzLwEwr9&-T)*-M@24M7O^bE zc%V#{#YuPKI?FdKShZ?ZR3wso_sm4cd*-)@c!`Q6jHgU_vvx@~^~~J`U^!8`nftx{X)BPQ+v1>owkjZj2$~>Y$NT#x*BnK z@2@{`>e+GxP!-c3tc#2chz#pm+bpVOt!bryrX%aaYl|nYcyMj;uRgXvjb}z7v!eN~ z*~39=ntc zHSK2hC-#^2XnUHy%-)2*0Q-b}#m=ySDb7@58Z*$I>CKE_zGW6Mk<2b8fq{$69p(j7 zgssFjVB4@gSQx@iVdt}J*&S>=dzQV)mVe6TtAz&BMoS7V&d0Gg2&T8ulFN&0aNrV5 zDZmt5f++=b*Fl{IPEM@Wdk0ZC|T;xr@k^l{aHbM_!h%iN%FRT@I2oNuv6>bVo zg@R&vF^#V&zR1_9U6-z1yCM%Dwd_iL;%9+l0>|Tnj3MZkp?af5`64EWIS0BS)(Q~U z{9>}XidU3DFd$dO)QaZVQ-=^ny2$pVU_2?prWBWVNDZVE8G1-{ zvl{-bhkMS@yWyQ2cZ&3I`ukc*q~&}M+(X1uf+Ah;PX zZ3YN##!H(4f}8QuW`N*kytEl0xEU{P1_*A(OPc|Lo1wIs-S%(xWgG6=Id)N|3iBS* zj`^G!#*F@kS;%}hJvtPxgT>5?ov>;#0eg)b7cefGF&Q`K;Ga#AllUeL#V~GqB_zQN zoHmw&U${fuX)cX(Xv^T>mMLv{6!&x&zoc$*eL}EmHm+H-BtEE3$BrF`PI(d7c6$I` z%8*NzK(Z79Mw_Mu2(4S5J$p8~f8hFHJPWbk`J~Fm{%SS3NvpQ2LZd^`^NgsI_7jnR z6Wt%L!}S6@7Yg)#98z(8LGgf`A$%@EJ{38<9RjuX;-S8e`TRopVdM9;MYHx*@h$0* z3OnVH9{YqL(lue1_@y{ngm~!_rK|9@FhSTLZ|apJ!YA?yVVSf^+9Pcj`blG@(KDn8 zGAJ>V@i~=O$>6?2;P~DZm}l}q1w~X~)22-!+S@XOPV21fKtT8&<)-pfDX2nuwVv8i z?Wzt?C#c`4t5oWIQ$Nv01tXnk%J1nClxuUzw#aadB^e_xS%xDmayB!X=PFdZBhTm1gI}iOm1db+BJfGnqHEo{D&Z!?E#Qo5 z@kfw6+Lfr1TXacCh)W3L2Fr=H6DqgpvTWJjWr` z!W|x7H18;$l`eDB#pPnr_u~clx=)6XBK8pOip|8DQknqoN`zWIEw?|~BQ*#a-EQV4 z=}##m6c5Bi1$K(-(ZQcBol&T99~{cA<3;!%i+c$7;vTkMjA|Ygb-aP9B30z%>52Gu zINkucf5%ODV*1?)Fx&FG6Tr>*yv=;f4Sj4A3Ih@pz{Z;g5KszF5F#v+dagsWgl2UPQa=I`TL0$~oSkJ>R}Pc{evLUY5=H z;w{8%9dCe-Yz9$!>n5|)OFXN8y#7QS@f9eAT&jEGwaqNx*>k+Xlqq|s^kQ$7#;45j z21)5jNqgBhxyrS%by5JYyvp1ep+Ko->CKvjaO0{qtBf5%ZisM6c_%xD%avc3E^=xh z(j6ah93RD<6dlqK4D}W)r*y#=dM}w5>WXMmohgd4 zJKBS8l0T>r(j|XTA&is#L4^>c_=5^zsp1bRgsQ4Ps1SCl{-8pjFcUYZ5d6HEE;{&m zGpTxt!<%{kH@wR&z#nO11B4i6gjTFsvu0ugysa>9_CLd*8E;?6pVOl{cKW2T2=88{ zd*xwq1yhUP>txkUUm3J=kV1Npq7A1Ns}g`s;)^lH zKT5A(za9wgVraouY|5)<Z?jiro9?ex`F0v_+wKlO2xf5k36ho>q4wavm zPGH*ef!xnr4ekr}N+iGIeZ&KHiYHg=HvY_eh>Y#q;}Bo|ET1m~8ErSjliXe&2p{z? z(VZ)TDfs7#Ac_9DBKUiXFbNdNKUV}+_RkeTlXK^ae@D#&uXItqQrxI{FcgwC??%l7 z&6;tW)Qi@z5$p`a8x6t1E9IL zZtN|_h9&7FxyFgTJxs%ZUYd+`ufc)^_5uj|?Ba-1NuHG>mOtsd(iv)iW9$DjAHl zmtI`+N*VRXRIh^BFD&hiKj2F7HTh;de8PXpkLIWG%lJ+F9{vOmSNIGbgyKRqp|Q|j z=q&&t&@B=ogJOhkY_fk^q zl-v)!dUd-xp#&p&Ds}$&B|R!1GV=d{Y{s0CS@={Z_^Di0Q9y&;aU(OoPXGGrji=J$ zCM?Fi$moN`5h8mbUlMl6BeP@@wX<~T(pt&E_&Beee7XALGX2f3FJvTK#bwIKESv*8 zJ!(#6qT@*>K>p|X^Ixrk4`7J0qoPP200i^F!GNdt%J|F1i@PUlBq19fI&`?&Av+m4 zkloW_Vgh2KOz8@Fu+}KBDz!&yk?bTqr0&JnPO5@OApS3$iqyT?)f#Z?*;SZg&NtVZ zg{+F!yXh0`@CU0q7K^_T5)zV`mX(?ul$@OVo4cH04fyMjwdb^zc6(te9);tVe4*p~ z6{k(1Swo%=88Ute8NXc)x_mjz{)(w!bM|_?2d*4sPUgpJIy<>x!|aBSs>ElK@Vk!9 zJ9f-Y#(REz?d{n%p7KE8sy04H$bbWa5g3)7+%6!e)-{Y90Wzr1;eKGZum{*vYzhlm zY#y!@SCebTeZqaojpkq)w~X7w?cq*vSGWugcqq-16t|zt>p{qDRBw0HJ^XKjJKt|vne87G{8tYW~O{Ka5e$Q2`0)Ed` zTQ%JAT)m}FHjpSK0f2z$4!ig87(j?EVRmwMl1wIoxB}{+=PcEMT#WVWH?2Q@_pp+9+AKfxVQl$@ z0bMik;>Ck}&x+V4@zFN}qW9w1VL|b=1@05zYuDpz1ISiE#v7R=0(Lny`q`MZag7g7 zD2A8z_}w`RK#{aKdh}-zPxTl5_trRv zP;-ouYuch%%=lPb4Lpi(oC-D0T{G?pS%Vccz&4Pv#CWFYVb9a3b@|Onm;_zWh1=`R8O0R>1npI!wdWZR3&E(+1pP zZ6@Oq2pAU-Q1aQKOk6w!R9u+v5k8(f+!+;DD&Sbqv123CN(BtECRwZOUu-z^vLf>? z(~9|w8N^It<}$FF+0Gnhl9}twVHBYzq1ZQvf*g@(W5OQYa@vne;*8B|4&S#3pP!QmT~Jy5>FRs zllCKT&(uf?;=SbAc($Z!j9y`1zV*NHxK70dVg>z)nh|mcfoAuTaUFCxL_evm(KS6z zKXc&9m4GW7BUkAI@B*l0kcmJ_52L2uOvj;7BL1cra=@-J$QISs!;2Y=c|&h_W#5ek z=jtUL4?2E4%ouKlneQ7NjGgA_#rg&FwrQQl{^nrTseG3V!&qQf{qyqWfXkQSztlgm za*WYd1N=~6leNb>VUa)r@&Kr2Lu0$W-P;~ve`_zwT~$JYebK&SzpzQx7m4};Z`K!y z`T~;mRgf*u)?-_;UD*LFOklrbSFyjahuG6>8vBrid|YX+HunM7nd`@mIKPD7z{76-H~unzm(Ssg3RQ&n1ZXFGE|B1`g~B=^ zM)*~@e_r@gcqZiOMk2C6NghApYajv*p+%6s#lf~;IJQnjyWu-dO zhtj7~f1ERh&ys$Swn*6G@6 zO!qN3h#q^q|J>(u=Z;xLGA$bgHEJ|QrL7a;+(BWD)#__b>-0c{yj#|)2eeaKik7A2 z(M#z$_yORROzy8aX|;6{M6yWBr{xBbd|)2>w}VJZSg(ReX6ToV|6&k{^Fcs0+y6np zF5CY>fIs{#o&g&E=6(<`fc1Y6@R0R?5HN%De-KcD_kIuyo66)jh;RC&7!pmpfY*5{ zkAPsIj6n4fR2~7}3sJ&;AyIJJn3T80rs5H)`n2Pr*#2h>#k;+0ix?a?*tu68POY2t z5{G}bsxQ8hT8O#`Nn*N4bx~9n1)QV}`hyLZ9w6B&)P>$z%J#!6+Y0tXeR>yeekb89RAB4ng% zmz)n5lT{JEIvBG5i&Y8Kt*ZJ;O=0LX@mJM+Y6=2vg%G`)PS{{`bP9C?f2$)H5NeDw zDAkQZ-5}G`#gHZjBFv>Gy@V*#4T@Q$h4{$oWl^XbthaVrlX*_nhq_rtiyEC!GXROapYP`je=aFJ=b@J9 z=lj9G41c~)!k>?>Xx4$eyo2%mve-eAd^-`7JwhXKvK=6Ub9>RvaY-3=N=b6M{74Q~ z$|&zBEtH&(W{{089w9d1%p7o`25oZ@2b#Q1(Um0SLb!~ZRlu$7IR$a1#qh&$r!;#M zb-lWI5x#3eBR2yOTQj zWp{lH7-?V(nemfBWp{rW@Di`2%4S28%I>C`u)tK!X!D3kWp{5_;FsO~Xn|jL_l^x@ z4ijpRvuE1h+fnv@8xnE+l4%DqC7HLGrVRcH`Z5v|!7ODqGXG$XGk-8}kFl9zY*n@q zOP#b3#wzT3b|-t3y};gPpR-VyW4ZcVYpy#tn48Sa<6sS^adF%k?gsaSE5MiIp)Sfj zy6}`ozLMX{!$IEQQ~3vcUg0gFme5>)PJ$?m5vB{v1(GU%Qh=*MZa|k&=_MF2t2-6g8y|z=MJ?C=`3hS(1UvI5< z*9Ys9QB4J}o*?=S{fS<{C}%)jgEw-+0SzLR+G@Z-d_YjC)LSNrnSoBGh{J~I=5mvW zo=%!@)wIk2>rJb=^}f}?>SMu3OSTqUKUuNXG3ydOXMsfjx%AelHY~7Jo5VL#dg~hu zRA4wJgmLJtKQiE_x4y$d3szu5*>NnTx9(>lk;PbBHi)D2){i;JjV?tiEv2{q!NEPw z=8ExEc}i~`&O;cl@ay@V{89b_f1AgjbYX!N>Ie#AOb(V zbt(&fdg~h;RNy!+gmdVvKXR~*)43$h#XJMaI}7D0<~a(Tw0NMKd?p_xkf@BN!p8#i z6(k`-SSoB3{vjL}{t)1vU<<{>sv@Pg4i_OzRK)e-PLa}EpNmjfVx{_0Yl+fZ=Si?e z(xf=)jC4bKA{CI!$>68AZk6GnY{Izj&LMPl6dR3DUkq2NJ)^w~HSTnI^Va>++ z4r>n9T&#Im^RX6SEyPl=7GW*MT7tC{YZ=yZtQA<_WBq`&5^ELKk65d*)?ls0QnA)y zt;dSQ`Uz_T)<&#NSevna#)`t)g0&Uv7p!eq+p#pP9azy=F<3jXc45V0?Z)~C)*h_A zSo^T{V;#Uch;;}{$2yD^hZT=?1nXCm=6iSczDtunerzSV>sP zSZA=#Vx7Y}k97g-BGx6W%UFM4UBSAFbq&kJO2JCSO2bOWx{h@N>n7GMtUs}CW8J~} z3+pb{J**5Y3+p~sCRP^K1FVNwkFXwNJ;8d4m5ucb>p9j-Qnqd9;D6g#kQe_vilul} zvoKPXRj+CmUaE}dRn5WzP1U@rS*W1VU0beg*7j;AHMpu-T7dqhUR{4* z@1Xb5!EZbLONW;_V^lU88kF8U)qn+tYD61HjB~Goa-o9h56T6{N=@m#?^w{n@(1NY zqU8_Dg}xs11MxnFq8^|3#NSPlGjNyREqkQt;Dzx9V_E zH*{|x2Xrz-!yCu}q=)nda)94<`j-i0jpYsGfCZLnc>_6sjKT>@&LPQx-*);A11%VV z31!AH4oMCYeS)EnS?J43EJ4XRBssXp+N^6k9nOK@cKVzHzwLA$4{LahCn!0GBnNc` zUg#oxB{(EGI4BrGszA~nC`k@F;WCq;|Ift*ZfLPd{FOh?|H(h&3kelb7A3S2J`)BBlZ3g#YGJzohlOO}y6{-Y zFP0VSh#!jZsn}oqTAU^RAZ`&4h^ItI5wpZRQYopX)J*zB`ci_?(lm(*@=i!sqznl_ zE-qJ-8_VtG-tq|fTNxI~k@7A%LB1&8kzdF~6sV*$P}(Rxlp)F#Wxlc&m!C?!a`u%n zj|lU?tIQ+9Jn$;>h%gUw(=lHu^N27HyvjTx%mc47j|lUCL~A+9JR;14b%v|VBf>mz zG{laC7#t0;BOwMyL+nV1!O;*q5@K*P#D7bO9SyM~AqGc7>_~{g(GWWlVsJFXPuYT8 zd9EG@ExE2-u0Dxd#Sv8}cx9bL)d~Ihu{@P^?&E*wukmo74-`mbvy<2i;ldJuL^eB# z%}`XVBEBcK6P?6nSSQAaB?AhBXl0s0BAfqCYzDQsN+O$`#AaBek|_BE)k$my5}!sQo1MgF*rCO1 zB(m8_Y=)M4*W68vvx#P{-SL?jxm=nNpCphK=aNG%wIRPAZf@4kq$DQDWc!QJT{kJ*6 zaVI$D1aRC5jyVAwcft^!h|bpXu!E21&+<3tH~q{hMy(Usc}wGDXXHbiX$UbziX+kjVYL)13l zmD>=t4S3}?L~R3q%Wcr#@r}Arg>`C-`m1_g{ZoCW7SbweKn!u8X@j&$+FWh5wq1k6 zTC#Rsd#vTx%j$LX4|Vud@2`KY&(eR;x9A7-Q#z#RS$ZC$lu^@YW_)6NX~1Y>nz78- zWb83c7*~u817`%q&1z<2v%T5d9ASQI!Xh)$++`-17tK573$us?m2h|3#_C}Wv8Gt_ zt+f{Hu;Q(=)=lfFRnRVP*R!Fe-PImoPq4qU$twPk4X5oi`=OnWDb3VoK43aC(2p6* z%wSe9KQsH7-Z72t?Y z^A((U1?Xnbd<7?70n&{}MzC4Ne8+5IlHg1r#_#XVD09C_ecwQg-)~z@t&c6@`;M?+ zskPB^eBZWJ%m!loCcf|gxJTm38RkY2)JIOPf)>wixl;JVL^~144|VEPdnyS+M&T)2 znW#-}FdQ4gLO0fr^@eoTkM)LeoFD5ALA)R94NG}H)*Gq{eylg_6#Q6kXf67&-f%|r zW4+-k$&d90CrZV^dc$J#d^aL)Qowt-q20+W4$3=d!z;HW%PIS z7P_E^>M%~9sei9W>HGCW9bJez1Q{ibw~eO8$3|a6G9nCEYLKMeLn6+CGu933iB-TZXA_1*7yHUr z_Q=P0+P(}#rEJ(pTe*+!JjfH2Cr@_ZLYt5PQtT`n@-Qw5fPetNM*=_)0C-6N1OxzH z5&!`KfR_Y7Kmh0%a7h3J1OQ$V009AjmjpmS0N^D75D)-(NdN={0A3OR0Rg}(5`grL zv`|_n#Yph0bRHcq&!j>!Nuh5g1Bs!ZB+r#s%iHC{a(>94@o z$}HsvWs7n^Ii;j1SqkJ)OQ|*0X6h&Em+EMBnhML*P3j)?gnC8IP(drMK{c(h)?Vwa zjnKZ;7HN?h?9vjni`pISg;qqbq&Lu^jow2aqEFH1>udELdb|#2^_%)ry`WLvAV&GF z#?t}D1Y^cAqR=>IA3K)&!^;&NBJ&{vzXTwk!W`pA{1oVyaG!n(^DYt?g-u-L1V%xG zD057buSCcYInU3ctP4UnB)oqaDqQN8+5@Roeln&Whk8dZh`t$pB{_CMG|GLFc1J{*x!j2byQ^0Zs9qtBD!be4>>k%O z?nMz}7Yf7XLb-A;%XL3dp+W_;5}KQcCZ&7)xpSH4P!p(MjVB<9C+HiA&LOahCul?H zeu5}zwriM98-aWy?2jC>_aVc97;KGbR4BOH_6JL z#H~W;fhAA&RO-w1r1eTDk@36LQ;4` z^=Ip5@Ym5X3KNVb{#^;#CWoPvyu zk|$7Jyf_)PYB^2gqfl3msyBupA*!D*sFm01ZQC=&D1EY3DykkACwI4zaYDrDC-$E> zu`Ln>{h5)W%|k;MCnINp?3AwDGluU%j>O{RZr#joxqdjrVvLEdwYy_|z+F?Cezpm5F_%C#z?bI*Yp{UDoImWMBVY}rt zOSD%4w^^dS61dG0?Ulf7mT0d8ZnH#tC2*T1+AD$EEYV&G+-8aPO5iq2v{wSRS)#oX zxXlvnmB4M5NUwCA2jUtoE7TD_6h0ODqca$02|oy1gag7UAw|d%@`zAMtSKULK_mv^ zY2q>wHi>)06XF#yLjzNGP5G%@P$@qTtve-SZlN6`_E6afRJk+6f7{6TLmjVFRe-?Oh_WZv zpk|VslKV&+HL^u4A~3!^3$YF1C1aXJQ|Ah5NDm^&L@61A2%OuBzGx!a@b}L8_19l7 zDSLEvvi@WddOAwR%o{gv-Xpco56hMDj`e8pzv&{n)CL$ty{O|;*)Oc(={SC z+N;pK97xjAabv{_rv^}3%@4*F zNHHMG$YYi=Ynsi>Ps}gP(I!kYmzkT)J?07XikV@81;wpuR%5HZ)!Q0jeQPbU zAkx}pC0G}&JJt)Uh+WBs26h{}hdsoeV$ZkN+BI{0%|#R z{VEw1tpvkxTPm`C5sC&Y$P?udSy6M=uO%|#h7B7wDW-osqg@2LCN8Ox`~r0bKT}Y{ z-c}LHvDM+>;jy!7rPr!;Z)`i|?(7jGM!4+#F_E&fuKR&7qX-49@A?95&g156&6F-hjr8GdQPnb4XyE!8x6qLl4#&oYT2E z++>}>Ih~sW8hc+2>A7^6{nl+PsTHfEE1DJRO|VxjDFlb2>K%cW_ST=I{2Lh+SXZ zX?UO46^r!z9Boz|P6j!fdh$McEt*tAQg(CeTF4Sg|sM9 zmJ-D#<&?T}#}33-%}nW!A+yoSKTvrtVpi6Sv*XU5tvhX67aRvQl~X?crrzR;p%bL9 zWzvEMs6UDWi6HUI{_;b4Rv6rrYbvwk7gD{M_2fxP*Dyeb-S9|dmvT+HuLPSgt=nxhugs%YW4u5yVxD_NxZxwLi6IS|Pon z{;p1tEHFr)q|en?>)UmD>45hTA!i88GTcLioFU*nM93Ke-a~|(A>chk$Qc6OLxh|m z;5|gh83Nuzgq$JZJw(VEf`(l85Fuv>cn=YBhJg1FA!i794-s;PfcFrI;SV&Nh<(A{ z{&)=U<%^^@!JqLtQ5MSx$9SkL{KXSpXx~|#>JtbzVQ>F9@r<}PG$A1%p^Nxj+}m-9Tt|3} zbA0IEp_vpe6(2bkFRbFycOvW?xK9k0ul2nq-2b?q{O}|2uVPYU@ULP~Zle&$)l^fSP}in(uqe-#sM0tH1mtC*q|_*XIO zEby;l-nD^(qMTLCVH+qY%2~yH$^ZpLIjfiy2C|quY$?`R#f)ZQ8oP|$#QwdC;Zi6l z>af(d3j)B(x8=?5>l?`xtTzRZVPLQb{qf{j57 zvD~}Yuba7mgSK7Uw`X$!2SXbWBhBb*Tph6of8ZlDtF7TrJ!pa#eVCZuuUWI~W|{ok zZP4`qmG)PvRJ|3F5ZZRlHJTv_p^MO`P5JFz+IB&w&>ViYu%J~iJ_5@~JGn67f^fSY zBnXAXwfH%;6xRxc_;%gVhOY9wfIfL% zy?B&*3ba%Rfoy{Eow7>#MLDFvX(dg0sN_>itF_e+)XpmOQ^%?^)D`N_>OS>%^_mLz z)j+L;Rzqu|b=1DlMrjbPEzve;yS3l6%i3KnM}wkz75zQEU9M~98-1Y;#5VJ*e*SOQ z47_W!GCnf~8Iz2;#%g1`0f&ub}G;5jVu~AVUmFt=T>Z5X9GeCV*u8r#H4u<%s&)!sBiFmN{WBD;JwdScfGG z5?FD?aTP13J}y-l37WB4x3KT*&b>ugdl|7=NE|4c4;xSfjkRx21@|9uqkG~1KQ|yY z6CW9sh0#wc_0PM4s}n>zkRpWb5}SqmfRg!$Z6!7fF`Z>P?|EE#Sh3hlJUB|`i)oWZBKWejDN zzMfG2>j@>03FUXjD&rU9ka5~bGvJ|-&n#`$Ha{>soBhnOX7~(qh556&&-~rIX5Kf) zJ|8?Y$0?hgN?l;AZZIGBAaJ<8g>Q;(0D}3i*eeu;N4$U=(uY1DIy5$`O`A5b;`xddN7E270L^$bHX^F!cJV5# z*#r6KdcKtMNDqqKw@6LIP`Fc2xM>od?_J8@tj z_A_zCa}rW>&HEiY78w|bH{C(DCqtZQD0yTVlCntMLR^XR#WSm9;*=z{IB~Q>k;2$S zKIzR?vgy+eXanf>e?S{RxBmm$0J{Aj&<4=$|9}Xeyt*eK!Y8lp35f8?t9t?>eDdm^ zfC!(wx+lmLK6!LcK!i_T-4hVulUMfyMEK;@J^h~{lD+uGm==d)3&aU#zqc)G%~9gJ zUu&;j3#2bCJ+5@=ZSm9M&}1JQKM`lG+p-YY5E~EYQ>VT9;1LjcVQ#>wip6lSdN3{T zxmvZ5d*^M zE@%I*gI+GYTJPKs=|B9Cn3i}cG83=Ol&i_R<6`2PU7Z$ySKo`o^Z7C<10efsT~kWQ z#S8@1ub+5%NIDwF1MPaTt|X+g#3J2z79{hjs)un zKk!@l1NhDcMS`O;cxhZHZJm2OJ#R4OQ!m+Q$b<*xDo zd4dez$*bgF8d>jSub>6L|(`tT54(up&IK)R3aOWB{25*?5B zwWEj9?euiQpM``Y2?>{C67&*A*|_W1+3UnwyHam$EY?#78=2SeEqLnnS`Tj9&+WntJ-rB84<`xQH$oz22Zb}M_3HP}@40lxm;;-D7i&y#??oIg(j zI`IBH3Gkw4NuC4@75sS;kS+N0Bw&u{&y#>Ml0Q!Zq9lKw1T>ZXc@l73_UB1JFU6lH z0k;)@o&-!*oji$;^}hNO6$)tnJc*pen{rL}jT*sXZNHX?+qg_^sIxq?_dbDN?0|lCRRu53u}}W zZov|3gSFfG&AM#ewQ{VYHdL|Sv)kF9+r#W{?1lC^8)EEV?eq4Z_A|Q>Ltq`?(mE)t z16*1Mg>`^S>-gWsoB@|Pb63uhiz-k>c~5Dle6FOa-zW=}bxJtpN&l%lQwpiiG{BF% zK!FPCM=HT7ps^xYum5iwD@abH$5=r$0R{BGG1K48iIHGTEJ%+ z5N7KQ=}o!1{Jz{lKHNv9tjnL|sIe_uvMmXoKT0MVpe9e`0tyq3iX~#dKv#QDWvJqA z)%KiIZYlSsp>_Rbe_~y~r<7Ccs&u&v#EP*pH|L!$cfqkxISwjtEL4tz3LFcS_!!8`zr}mwV_-SInfJ!WKy~4L!5bd~vBELI8y^FXh01YIfn%X^ z98}!zp*_K0 zdO6*3P{DY8w!Tu|syhxU$ZNc1)H0eIj)Mva9%HX@(r_G9P~Cjr>|pjW9S0TAesBoLG zS$yrT`Cs6!@vHW#3gB1m?G(VT+G{O>U$u8e1ixzUD+&Cny$2G|ziRI*8@$O+B=`wva-SRA2Q;~lCO?tjC#cT)sn!t7`l;5?mg~t4 zH~EQ#K7cp*i2z!` zFVJl*gE#q!09wH>(EUmQm(WU4Mc@)zDWDbn0^K(?aG`&c`3HW1ZbKdX0^K7z_yxM% z4Dbtdab)cm=#DeNFVGFLz%S5UYJp#%Th#`?KzFANeu#N%2K*57GYpVU%iCxH>9o9! z7LZQM+i1aZZZqd?w16h}xs4Xk=QdioViIqo1vI(OZM1+U_c@K$85L-9pWA4mG+?&2Qgeg*z(EK(1R-z`LJmO) zXmXz$+y@Rq$RP-UgAj5ELf{~T9D)$gs<5I6`ShadzFLdYQqfrAio z2txNMLg=d!J$m$jV4MhrvQBUxoMHVhFZhb{zr5f9=YM&@bl(5+f;R>K%L{%I{4XzX z&Fl2#1+ICWzP$eT(7nN-dpj>L@RPg)OnB4uzr5fl)Bo~31xGCZ%L`odI(>P) zNVo4jCh|<458&_FZ!xtP=jev%jQ{9{H(CGD4L`B|qZ=A>{-gV~x59sP|9{}E$hI*d z+kbTb7rYffhh*;24RlE69^EN)NLGvED&yu?WzlenBf4mYZ_0hl zwdH&AFqEIlFW_BSG-UH{2o(fZ77cTRABAm#D~pCQ;yYps(UnC*l(=6^6kS;~G?hM< z`bw@W8jeeUNcRvuUQDhkHd4wGG3G~AYnF4~nv!(?S1DzaQzG!R9Y(>ae< zXR9w(sy{6wnF=v6Yz&E6tlJ<`J^j5+Ll&b!rXh>ziE7S+MY;O;W5?`VeLTuikSyj> z#RydFRQ6g#pB9e1vp6+%a_SlcS`a3B;YgW?*-@Kvj+k=_Xu+tNenXGd1bwFdlsGZo zIzXoN*MhEH+x9npeWwmb^>+-)B;U=3v3qgG#*0B0FXr{wG9XkRr_%=> zfzYuQ5KBjQix@zNEu*1@Z5y#=5T8all+9~qN*9~t&(5|NWZ`fj=f)D^gu{_BlE`$s zmK|&*y=vN!dqGt9gnL1_h95DQ;8e3F(e1)s<`$F9kemk{dv}fn;>TIf>|{vqp2Rk1 zp%WX-mEqpuT5tjv%9;4eu)gP_xcyurXL4kP4}?nBl>e9~6tf6^DG&ccUiLZF7ru&7 zd(4=5XE^B^KN9Jw){c@ zE}xQ>8w}tcCuG{F%!~!wGoOY;1TG$1mn;b@KCf6YWNuN!u71tuW-6xKQ~E5D$*+)P zC(K1HI~B7}#9d3sG!(N(D7m>5$6kHW=}KiS=YpEc=VsZLY{*<9-46?E8WuJ!Bm$-T zg|&uS&df-nphp3H%1rHjt%KG_8@Yw}G(x6rw;yU_>k>86SZ#+kn&{VREH8TwkAM~n zWs*9F(8bCPP>xnq&(JUGcl7J(WA$?t&MW9yur0r>z z8ksra60TRXlNaG0e!NKxXu;YTLpGZ%Hh(fpK3=?dadz^ZOw=_lvWSvxf=$)1K;*EF z8g`%kyA6a;zJ=*$Y+@E^4a_#?pFPacn|oL{nx^3@A1*Po?UnXcdnhxNS-_lRUiCTU z%nxBxm4Z_Yl+u zT)ARjd6k`bwMb!%PK*ypn=-|oLdL>SsnXR-z2>4=J{!gIFFy~PM#b`GZhm5?-Gc_b z9F&c!cOrU!xoul+7-a9>6?$hUqhz7ezGU_@`S6Dr0ziyHHC7Hw?bGLFpE47O+WGi# znCB87m2f2ttYknIU!7dWy$9PrrS3_c^=wwf8w!f9nr@z5TX6x$C~y`u~4F z22_ngyoE}UR@<1ac36`@o3qYx4VBtcsRvr!Y1JyR;9hOon-}3?Drdx;{6>u$*}yOi z?M8tf+B0xA=CC4*KEtHmP1Wg2I~0UxNxiMEjO9purw-3F1KL6Dlty-h2?gUqH~Z(0 z&&Q?O{6l`#@-f>}IVd;-w;6wB)ze?r`z{K|?pPQw|LWDoSI5*tRQoRdO=FOeuta&P zIn~P5=ML3=q2dcKoKIO}R{F~cD*&YxJQpQ!+l;XKSwtznX1!r!R~j>3D-OH<#PW~j{7P0yY19%_GW0on9C47sceykBm}{gMT5Lv9leybZZKIPf;)cIUy{kb8;;Z$s`d z0lW>lw}mXXA-8YZ-I9$PS8wbz6q7J_OV=FzVE+dnBp$;3V5b3}PyGDzyQNif@Fcri z`dQz!&Z5hic(;@yGX0rv#VGr<_*Bhfw9WGVfvIU#q(VsDpPG8N6hjvMM}F1itFP{s zV)(v~^6oId&OT@`Y_MRBh=uzh2?dhVDku}X%E!jV-HD5vFTFW|mhHZHwA@uVd7Rx! z?IVLI$H^1b)tax8JuOrEMP7SITq;vBAxI0mTiW$b*RE3!&0K^*K$wExwWEi~_N4%) z)Ku>)j`Y2kI!=L!t0I(s%E(3M>Jln`&ISVZmZq2PbCa+0@W0K4lDj3? zmP2B>mT+BrNuIBv|54Mmhr82w8V0jHR!Fb{)PgQ+pv zhuUNfeSEpLyVyU^Of^xicjH;H-#I9uyf@&~2B5q*;M4}7yf@&~2EaS=yPSpc-hdMu zf%4vf6B~i@-hdMuNht3PP;4ZIcZn1m*0hV-KMBqV-s=STA0BL=wxj?*wBj9&VjdoHIilbFepoC>l=q7d&F|%BVq9BpsVkE?SAEBn&y->X>MTi7+N-Emkz>`H@&*3MO+NSleRY5NW$!Pm)zeEc ze6%Zm;jD!VBdwQ|+S;2+gY+}{nKN|GX2hrLPe}<+$K`y3^wIX{(fBE70{J!u;7Nq^ zam9~6J|KUfPEs|IFu6dS+=p6q{of(t>iTuE4>Vyoc*TEFdi!< z>bn+oiGj+*HH}_o2v&xvOAJ&dK59B#Y{FuLCl{Nr*m&)uDyPH6c7>5Vx!8oo22UC%Fpl3CMxB6=0abE#bHDQ!+B|w~DBnm(NP5kme_I$Fnb|CrpWSOi#SI&3 zN^c6E8?Q^Q81sDL3u%|kicgOn<421ZxLR8UYDILG!xqIX7yo=0mgg)_PD$=4wicU9 zwWMkSw3gZm-Cv(0Ekr-WC*ow$=jwIgj#P7K3jeaa`?a=MA{JugN^&)|_s8R91h7xV z7Q)~1WXT0DYIRP0UnyIjLv|Yc@+agNnzULuEp-}MEvHJ(Z&!c&t!nO?@Z~x9?Szcn z?PyL2&MA@YsE%@14wfKJ*5-On_300;)VfuCH z*KdAXI`t2gMVHkbj_m<*D>8sLthys2*>~Bx!+r5>cZ-qPLS{Ow(Fw}r|t+$ALC=D6?eAbp^$Fu2iyp@JqH1(cJOPnhP}km`RCW^2(}nj2&cL5 z&hNeF^WF);;(Yk$`MM%6ZRTNrSPXZEpUk!AoxIb@`mYOu5GYLP-L@^;7SQ#R&415l z2(VI!ci{>~n3l^o@z(?hn(9x5 zh6>o$L$bdCy5d_S@q6@I5?-W=(<1O~dTRvUvHa2^ z@KQBSvLvDiLWuO0++R8^(iSsX{y>IF@?5!%@~up$-$dn(43!mIX(=61I;d0*#k@kG zI7N-_)*Oj7^{^BluY(hIh*kEeBemZ6W`KT(toc*fjU7veSObKt@g&v&A!|H|H9*K3 zPht(YkTo8}8X#niC$Rs8p0YcVz5^E9&S>v=Y7ijbB{*U|juiKEG{}GQPBGMu- zF$~)#V(znaK?&X&(jsImrvl!5&f0s-zXyb*g<}kA>blU6Cjt5C`hYI-KPK&_C!=(<)7ti5ECoLi;$0z4}y_rl_^=@fBn;o-nGEi)1VO6g^ zn_4rN8O`?Wv#Kq->P3u|Hsj^no$qw+yn;3AP>;bE&-)Xs%-&+xvFmvpqjut6XnKYD zjH`g)oW5KbF|t0p)1gC$ZJhnGj9)hrpHB+H_RSkyH~wWlh<$_a!47=B$r}C}MCr^% zl+HyT4&N`$+LrO%g_AXV2v68p1Ybdr^r?_ZJGC41Y1ZU~>;AG6M2lY|gq0B{7G-P!jhM<1@;qlZtAhr$%GvG^`~ zKzK>Y$M~HS2#QcaoAm0!qp*(_i5=CzVvlkdxu9-$$!laKP!Y&_ZS zE{~DnZ6#g!S}arD%rw|3mny`->#lTGKanF;AcTS!L4gnoo&*ITgn}nQ0SKYsNl*Yn zD0mVSfDj6v`DCDgvS&8xU#|QUZkwTE9c#@~gdwyEEy99AUF*#}3}+c6oj$r?=8#uj zF&TeGdH!%#c) zkhS$r@!))%7}UOp^$D9Kl2o5)RNLQ}5^zr@xa9A=$j547b5@>s{HKHmPto{0~S+b)myt!nvr$A%(2Av>{O z)WNB1xg88F;MQ`3?K6nu`jy+l?GRkGKvdqe zc*Kt7F4#4!umJ1*_h#0{v-bq5k*93hw5iY^zuA+Ngm*X}VG5U>6yr0r)0XH;`zuvS zPQv$RWX~mCmMlq5!lB4~{!M&f^E~IUaxE@IeEog!G~|#V2ObGE!~l`pU`s{nDTf^s zXG{A!;Y}$@>N46Fb!*frYsr&j0KQu2hJ0;tm~Cgoa}qiAD9}lHPVfwLQl1k$1D%xT zg!1~I)Bc0<`k&MOgYx>H)Bc0<`k&MOgYx>H)BXdeLrnF*GLyVO#ozph2X&!8_8Q94 z4pXxpPbt5&LzqP>^bd-gIc{3us-U>S+IUJWI#yU)xvD5>C^IPZ$00#k$OTthA|Rl+ z&>#6bAy=?4f&U{GCPL1kY4Mjr|Cu?Z#vkDYg|(M1y}UH!96qrM{f7_t89r5h<t}CFx@J5upxWhN%QYZP>7J!|ZtMbyB#b zKjA(c{?L2OI7_~{zy?%@J`J#u8Tiyyx4#TC5g<004P)o9S>^_IEDMfL{!3#3x6`P? zyx&Tu2{)cdZTxOmn?c&9?ROD+0y53vuvIju?G*gt##O-K$Dm-BpO?x2zIbleMO{WG z?l^Ov1+q0yXAkhl!yK?2kjT-~;|Szus>9(u4xxcR2!|LIvG#N4&SzKFnNe}Z3`hLz z8fuyKGc!BD$Zm7&p5_m&p`pMu8mH9&kZ>Y>C3V1_hDyiTNm07BSH&mvn z2HsGaof^2IG65nH^?o>VAG;1ME6~`}c0`K{p$Ok1(IeXK!pC}9Tm?_j;?MrgGva(m zv{?6Gu+PX0Y#i(v64O?1^gT{BOJd~xvi$jOY*v)S%)B~tW?Y5wf%o$9`)W|J;=^%CitP&xHr!mXHq zXD{ZH`OCB2^^v#=R3EvVi}jK7=3l>q!_RXQGMju?wmXMX|41k+>wgHfJ%HyL7Ud>P zD2c&IEJIh#73ZkBeb9namP6g^ZkHLgE;b}R`5JSFdB_}iaey(}h(}5!<5ac>G8b$I zlW0?pmb!iMZI)Y`u9j`_p*a|ipIsN&!fMOKPwY8%aaYXze|DkFH z0>5luEDBT|Nj;@|#xNV4I6f7*o!~teLOrr%A~>a5&RBJ z&FzW*ikmiN(J^`9LKI65lSW^N>qGJEIbU!-`dl>J%fFXDB7;x@bR{0a&r_!r2m+nzFO6mriaJo1P6Bt-m7k0 zg@5Q71=p9!-3X@_TgnAaG!teHEUQ`n`BqPg^UfWi_1dr z9)Eo~j)ZN}x|7N=Z=3#-;YtAR#-@qit^!;Q^r>(#WOsgSK49JRh=Yov+Gv7yDMj1* z6>fn(FQ`%DVU6p{gKOi(0dgwlZigL_O0JFwd3a$cL!dB+6V{OZiA^}iI@Z0( zY&&lG-3>bWSn(F*bIk3M4B@`F!mw~~^W;Nh#+)yx9Zoh%{6CaI7yF0IRjx71;a%Fn zwgVp1>^Al*p7beXPXSMT$`G`tfTuo%>?z=>Pa%5>c;ni3Ow~GXir&qvU3Q2yguUQF8uv>7JZCA|GXk;4*r^5_j@c^>{70n3g9Wd zBFHcv8he%F39hb3#lwg1CKV{{)O*Pdlh>4lg{s5Uk;!-gSP|4b2SzR{OI*Oy-vx0+ zyQ+D8)f(Di1-YWz@Q*nwBW0R0R-3kYXj;8w(@Zp{YNTg)N4u;QeKWh_?AggFNh`?I zM{A_482z?VPphM*>YKjL&u^T+DD&4}f31Dtq+UmdQvDLHk%(JL54c7e#2Q_7Vvgo& zmkgqt!eW(}qrV!@n4>260B2ml?(!voG1p8DRD?O)S6NK6vd}rrl?vOq+QU zZMCRRd%xINpV(&4dL=7ZnK{4$nVubmo0E0|k&EMIaph?za31#MX(y2RWPTlAo^}ET zU-qvE)GKjnC7=o!!jHmPp-6CQCBTUkcPdXifi8Oc_&|`{K0c>b0;c4QtleoRkmN*p ziCms`0$Z-h`6`6YaneqJmqFz_r9ABftQw-eu2R~G{8yhNY7Y0rr`7Vb6YyHJ_LaI> zor}yHN;`qKFs+XcjxepZ@{+PwKdxWa!P0$<=M9QKMH!TK0urVjXDICy!k#vs8sIHV zTVw(W(}+!2WIi;jTa7K?tZ?fc%bj-m*@WLrZ*M)UGjLIDJ837=$hhZnI3ww$wm-H@ zJc+Zz7$D;8L2DuYnwjB@N#Mvw!h@#{PQ39eU zc|w$cC`z6XB_N8DCqxNoSy7G@_)>y3%ucBsDbPd)q9~Ok1$M~b+PEP^DODppcy|T7 zkpia_C{SL;4)4L_5sp>F zt+cC5=u{2Cac%KtwAsZb)fRZVwn()Fp02HNjLd+iYl~D{5Xip5(x`6?-sVZQ1sUv* z>{+&meaKelNVNr?t}Rk+fv0PWR9oQb+WOCZEH2d+*@5_pzLmRiqtC|1VlQ!sh+0j| zudWy2d-14vQM@JEBIQ>*NO^BcgQSn88PXS{@nPq8D;LjXvglDZ=3m7;gZkDLW4I4Mj|3>hb zZ+M5|Alam&_4b9OT$nZO=Lacp6=(jsPW0Mb@*9 z0G>t{x*33{(S?LAkj8z-dDamignym)tRsM@(WQ;R3*c#VIe>Kp@HDzm9RWOzE;JPb zPooP7UBJ`mLP8htG`f(`1w4%|By<5!qYDXLAP1)bZlencUBJ`mazZs#@HD!R&;>k= zE+ljTPooP7UBJ`mLP8htG`f(`1+tCPhTG^uLKlcOKQJembIldzwr5Mjt+y&=Ldob!eV1ErQcA;LhZCC|_j)E2xU!jL9-LxcgRQ=(@b0fj;o&cteE2jgECggdxrJh6qE5m-inO2}af@h``oMB6O9RUJ4?@TLDAHlPZ0MtkDtRsM9S}x~>gJW7Q7cE1H z;LQsM=R7Yz&cQj)-N(5i0S&%A>j)4cd-KA9`UswN1c+9=dEt<+c=N&`PW9%6gOBFT z3&$p~H!mClb#GocWa!?!a0oZNdEt;_c=N(xxarLchZ5797Y>P*H!mFA#cy}-8`5m2 z`0eg}17RyX>j>a3e!DZR;4XfNp;%pVmqMu%3iG9vlBZS= z8o2gX8K^5DjeL(92j;R{|^HBem1y2A3odeK^^M0tq zWzPGd4&!*4Z;8p}KI{>m_z&=u_kO6uBEkEi4vj_chdOK%y&vlEn&kaZhZB6a{sI3d@pLASGhd5oNsd}?xV^!hf-`6 z6Hqo#9vlCxu@iw@Z}dUfD1>nNAYk)Z}EfqvHVQ_$(MXO zI)!MsY7=OT{&altd|J;tKJ}Ucc>B~>3*hZjZzJC3#c1&ZF>WxX2*Ji*IuX)gE+&%V z#C75>@rVdAzV)f1k{{!X!`h>WDy2zshy>n~J^ zemI^CS7s$(@(HR`VXFWJ2Y%*hZU7Y7b|wjJ)aT_$6x!e<;Z1caP7*?t*Ohz~$`!wK zU5V3x6u*MDS3Zt2WRefS^E#znN%2d3if9c!(A<2AmNM0_v&t2}%XS|=-0ATAnB~~G z$tP7s*?~jPtP_{glF}0~M|&VNE9+_2=H0Yfc>Z~x=MNZExp6$e^Nk5BjrrzRzXxRF z>JIr)dL>vQpW>m&1dGt$L60Mf;7GjlYbRxQ?E0 zue7(>pxZQDAnl36Isk87>FFE%vsvcW4=eabU2B*b~_j*Q^ZSroJUN zikr%P!NF=yDLcVizJZ_^m!iFhX!SG&Db=q;lnl zl_Q&{Cej?ptZ15-c|~wPX5qTQJQdHtSY@IMFz1fyIv~3Gpt*;ZYz>-`EjX4dVT_4RU(6u zk~$^TmZyA(h`bQ_J-O_o$plNoGvxt6JyuV1)nPF55+_la_%By{4S)HsD0`*j(nDDu zJ3?A0!**qdOkkdXaT}ESYT3gh81ua~BC_S-5GvU8DUA%of{l;*k_y?%64j}g%~jgi zMQWZiT^XhJ--4?^hzttI9}U?1(X5j10CNF~$aG=&goFAFJp!Z-SEy@uIWt97~{J2LRoil2V!y854- zZ0vmRiji>JxZx-t_m`P9iV7a%f-D!iI&fzHnKM;y;O8PTh&nm+vY(+ISEx{i+T9PV zIP0pl$Z%Xx@R}{yp4WYF*N@%p<1Bamcs=vobJR?k6hYh1En8M^>644?lNIUB^V2G( zrDb>&&;RA6m*w%&YklZY{-N`^L$f<`qd8pKB4sKlh|a(VW13G3KcC~WJJ=Xkq66Ed zxxo$pn24U)tAd5DuVaMZ1b4a#208bS3BoL7{~kZ=|KW$66ru;m53D$F;27>jB)vL+ zY~cQDJHWq*=(4}sPeHT9dFt5wT%jyIjl?*(VGKK;+jscBvslbIpIa@YEI0X?#KNGw z<=%6tX{}m4Y?W59J)7DrKi&E1r#?X&sLcZMvo^~uevi%97WQAlG3@!=2pju16uCIc zd<7BqK@v*eb_^VwJo`(1z7>G%RER1mr%Y==>b?KFUr%q*`+LeAj zXZi3@@tb!B4DcB+Jl7A`23N$};xzdZ56z|4c9lW+&q0_bJ#)==6kSb*_hu@$g@zJz zmD}2cyW83;RQ^VuQ#co^Jm+&aq}|9l8NR#X?%j8TcBd6L8>+67d&*Er*)9JfUyv`U zx%vcUuTPpXR$I?jZr^bxo`M;SKoVY+nftNC&Tf<#$es(qhJY)IMZW-run& zvx5AFIlzR`rd!|O*c+f+-{9CApj_V&YInWUHrn+!PPLIDEYO6PHBZLi2%OFAY`f)& z6PLPpKv@E+N9(iQ`^1X zJSRQv9QKID^W(?kQL&|sFcE$CB0cOhb3RX#`0oX9)~Gt~n%8x!CL@}31GYSl^`XyA z$JY*ux7$h8#-xPD;O#9volPgPNTK|alp}&}I`6d)l+EIODO!X(VrA(C={4CIuwCY8 zx!bKFZrA+e+tW8R^J`Gtc|Lw)eIhW+d#RK1!90Ab`9vfpc1onH5}qE{M|Mtzw(@Kx zMy{jmR(?>Z3Aty${LDn3a6}6?ShKd`+O<9r7qmYV6v)1pG6Wj3bVJ>wlp!NBNc(VN zv3~~ciC*hbr%oLP5N%tzbA;MY9k~n^s9oPHRV!&7UvmM&7hUq#o9@T6tHB{xOa-&t zf!Hnb`OYUIrnXPGUv{QAR!)^LhKK=+WjhbD`;Ek~$TRN%slIq}I=7(Wxo;*Xa{MfkQ+YSk0_gttjg~3!`~fvIXm` zT`rrFTc#BDiXCac`vlK1pNMP2pA4`Q?o)`mdUdlpVEcN;y_PNGT6W4jtnRswZJluT z(mU*}G88rVL>xWZ_~@-NJnhnE{<}Vt2L()1<632x!DC`X1OiL8qQN83-|Ybzqn`BX zj%kUzRhEYzKi=thAp7PI_%*M}PGQ5^uwT{hoPpnpZS2)LenV^HCH#E7$!aa5pg|D^ zL-)oP)W)b!_lFfKI6%@DD+q<>{ZCd2$F|8wp^E}nta!L$45v56KR{?+v3c_YF02h5 zz{scUU>p|$o0G3Lg(m|Y%;WoV!?<{EcB|#$b6hA7{e%Ip-Qed5hZ^^!oM3nn-urL? z*&BOE5GQHE5TTcGRJbVI5-fz-2(!e?yeuRO>x2`cEJL!qPIm1s12$lyHB~J8>|;uu z;a^RoWa;>5>_EMizTLh(N`9t2DU=#9pHz#(-05btO+lKi@*AyhPD z!ATi~)RUl|@=KSQ%3JE8#uel`a`PE`)~H**ib%tRpidIDm9kUt-LX04-)}3uCfpaB ziBpsi?Ohe_s-v_v;ul(7!;zK!$B476a>Us?SsON}8|cZBpAusfT9k)b6oeN@h%;0p z!}!r~lkNUxn3eYoZFgyKG>#ZfZVtltmyhL}ckGyb4BtIf;DZn1KFB{;Z}_4>oJHiD zey{(DA7i@SY*Y0wi|}?aNu8dDcTvAZcnM9KYB{V9@WiBjWLs)N#+pTe6%wmhJMFNLz&?M+fLDSeNhnJ zc4t(Wf_I2TLHNE)wr_LT%Rlm9F`m>LH)e0lXudqZXW|;U_X{&-_{?bFpPSf|C2MjW zezFbo?8Dmo{K>``D7+KE-FA#WMB-h*)p{{VSjxabHjgW45RU=9<=h#r2M?QyI$8sb zGNCJfgZo_@zyrCmKNAmewS-u%20s*C_k1y5Lkf`EN%w4wl2^@ZD_jzSgi7zVEyPbv zBaHnI#5-&Q|AzSk#0i^T9;tk7CqBi0%fA-0n`j}!|}Bw_xu zgEZR5HA>Ncr^Tcz$cse@ak?l!46dZ3l1;rlX2 zdP(n~!<+gb{bQXrrOtE>e$%h(kFiq68qT7$(I_MCFnVnp_%A~IZgKPZc!_D?k6+t_ zIOAJkh$UH7%@@tU+^JorPHo_i&(}aSwf@WIC9K3e&ON<=A^lZGXRG*)Ygl4>nu}lI zum+i>;SFkI(P{6YYS)XfWAxNqauZ*h40VhGt%DYlX7aK!3lAAjEb=aG!QYWgJ868^ zO`Rj-%>?j6G$bW2z@pc0zoLe0A@t^Z_oi;ipwen3t8QekC%AM~`?uSxE3RI>zVzPk zb2bS+*Ro-Rh8m)HG9ztY78OoGY= zp_wX|-DBKi;iZEW4<4M)A3@6R2P)nCkvZin^kG+WcNsEL?Pp;s_myzg*e@hnqxkhV z_HkKb`R&}7T}E=3_=1qs)W)gnOYw%E&mZRl1;18r;KzE`fL!i9;U0%if?$D=<$v;z zI#uKU?&aIBU%wgBTmgdtH99tc?ZRmBigAid6UPeU#U`y9H4I!|f%vooQ9bv%jV{~kZ{yo(zWTj- zRE3M`E!BReC3{mFq=BPKOVhs7e%5}|u4`qFH6lCX*VnENl(JsC_Tk#b`)-s_Y3KEc zufIM?Tz?zy&rh`n@9nua{F*U|u1XAH_2=u#j<)=~7WeU?v%ZvAjv^9!@K*uw7A&_AQv#A?+N zGnb#oJ8np3Ugp_u=5yA$6X|v#YQ|5UBFP|(=`vXdFY?US`uF$gUsZgb$1UoULk~-t zzj=t&-)Dn`2izn6C%HJfN4_r(7Y7Lw`Oo>U+VA6G?0x*D3nR>LxB&5&Rzad)?|1RY z3@K<>JAF)OhD?nuoH&eo1PwC|XI!&;i`AG*!UgdS0Wz7Nm~%{b`{0Z!QhjNJ1fDc> zf}w*a4V_@-hJ^bR2*YzW|u;o-E1{Eqp)7>{m~`$&F68K8_-V4C6$>xXJ;BekvC zo!*J+WObgpXL0hh=z1A=Q(Tm~a{tPeAqAM#U$my3P0ARmJWVVpSfmy$#RDr&51X~4 zw$^APKJ7c*xRFDbs*r-v418TOXj8aUs5)Cx@T9g?)@KP8sz_fPSLUu|jkCWCbJw!^ zWM*Zp&I&2OAygmzi?@7uY(n7~o2YNxIRz8&AqDv2>ZIQ$ruN01l!eE)D89+h>(Bp$ zFntD4RvI#A1K(W={rS@2{CbOM{#KBfn4S2uPTzqyf9ZIA`t-}wLke(!x$M~3vFuoC zAe`_olf!;2D?UMkB)pp5US@FSUTdySHSZ@O%EU8t%yjAE(o=`j^>6EBy%HSarZG#p*RStWztCFp=V0l9Rn2Z>2e92g zv@-4P#|b%c(h8d@6}PH{bBF_n@M!mI>4&H2frHES&zOCB-WfZS`NiH+a}I{zgToT7 z@4|{p@CJI9x%vcRGw#{YqS&YNpkn(8Q+fb7-k-3GZxu7Z`Zq`sz7b$Kzm~m*`i`Ds zlI+>sBQ@_s_5wSPy}~_t5eL$KlY;P@-YNYCN5gq^JO{DlcK&;RDEkIGpmEkoe$`hI zB{N$di;l^uP{FJKIIcX~dC3x=C6yy4XHT|%=Tj{j)iirPz;k>spHC@X}w&R6^i}p;@BuE6Q@6yHcRG*_`HhBeC3s=ue2$k zP1cGP<_dyGMP*zkq&q*EOG zZLNTklgAQq=9d%H_Vf7or}0slPPr`qE1&p-IooS*IDpT(vc{#x1qk1|*{I0bLpgSxFcoEVjXH=s6({AEU$jEtyE z`~*<~3yH9A{t&Gy=uCG5oS6QL_rft?p*1+np9K>py+itD>Lz#GhE$rl z&GlctE6z;BNygL^97HLkIy#%OC1al%mKPo0Fs)vGYBJV+Vq^a)v%&fxKckM(+z2xc z=EUm*zsfsi3|#4yo5P^`{_52?2jN4l!MRplTD967gm)4A&+{o;5Q6g_D(1ln>stj^ z%?s(alzV=+`C#D6k!fd>T{S%{<@&^9O|N!t{MpY++jO)FT_j4+%=}epL&iRz&cRmUq+C3kN`g{! zpp^$9Y${c!G1m!aS@ULzxHij;r#d}d?^10KY*t< z?xltNn%D4ke>P?HYM<4sLxb2;yqlB+G&=7q3=`a>B-khXDxfY>ct%QkFD$5X>ar?< zm|XZMVEmA>kvUG)%V)ybl(We(IZ0Iasw+=uA!iRw$A6Z1!N?ZD61{W3Ky~j1&sarE-#Z>p`%eCg`uEWBW{$U|pU0oObMD-r z0gL+6Zo&1Q!%5m+>2{IyP#Pt#h{r7j6yY>$SInaRcslMGlsm#FH4dko!}QHk{9y)ta+p&e>3={xKzMfc}Tu)4Oi&+=p|+a~Jh@)%7ZV|9ykZ z!`Y>Ai~4WKDNXdnY0O@om!stucgE{5TOWFqbcvZ6sU>N9V{#G>XID|OjC)mMa?4FVuEG7n2|2W}5-rYE80Ld)uQC zC6JO>nom28?RFizx&1W)__Qb5VCJSu^U@e*C-eWn=vS%3nv7J>+N8@8}$-%I^r-bT9n?N6JCV# z+s_4#!^_3PW4CO~T;lB-WZLLq#mwhqUa|P8xIkgADIf|a zOY@{uX{$ufmchy;=~5NB{&alw+)bJ=!Dm9Lk##V~niJ>%}AT zUD;PTFSkoIo2sEJE@0m9R#J22eKmGP-{cF? za7ZEaM0a(&I!_rd{i#my$60?v?JW&IUgJtD1&3Etubz+TF??uRPwi_h;heZitDya) zQSmxPIPVuZ0_UuC_1E?Oy13J?VK&B0I%sqCX4-TeD8`kq-_cv@j@!Ydb*ZZySC<(? zVnxt9DIk2zx$4 zFKLlfB&<;2B`H#VR~{ozm#KM?A;XXIS-D7lC|6ggc@eI_I|_|<;xM>P&5IlbJewD@ zlx4`6Qz_iJS>3Nv^P)tBidtQb7W`Dmk+eh&mT2p>@3o^EY3FV2sRS#f4*IuTj^WG` zTguQycHWWhc_O@S^fyKsQ;jbSYF=a;uuk8l-#2K2NX?6A6R3H?>h9)6z6svVi#Q9s zn-@OzZKrt=`G|&sGQEND@;JQA7l+`Hw!_lIn4V#Khx9>Yyh8eZ#Z^Lx0gz5>`O6H$ z2C}{M18qyvM%W)dPm9Yo{&?M}Il{*88{qv6WV+a6py5Q2FW%$Zu_26%V3-ju-UZYh#G>krqZ zjUtI++*yApzXG3@8^{-BxGY;pRpJ$Q)*n_Vu1gpGpqy1Cv{bvOeN<7+S4OGJ)FmS9 zRgbITtfe|xe>@vqlvmAh50H8Q&TD^ZPc=q&XZ@iQ9wLi$Rd;9o;i0}xt?YV#Iaz<0 zZ>%)78M@)l`a=V=mFap;J`H+%;45>8Nn3Dk}>B481Bp9!d&p;u9&Y0k7&r3HGPF17dUlbs4eG%Wx&SVL>_R= z#*cZ{9H-(qqKz@%)wVPLzTl8O;2XhPbPw&t9^ybTR(!&C7Uqf5L;`n-e~OPpXPFWq zK|kE?Z50fq5(9tTie}ic-tOf6XD`( zdyD;pebRAy-gJh$ z#y#L1Q7@3GmlnD6_*8x?e~^drhk)}Afbxfc^A3Q29s*)d@qKZ;2nk|}_>H(*{6)MV z-W1D3s3iqS?WG>lKq*!t>I&aZ3VY z6_NzPTE$Zm7@$Hs)s+iTiNd`KZ<~O~4V7Ts&uI;{)>=0W-quEFpJ;RNmbpbEXgB0( z1Z{BUY`yiNI!w@$^rboxbB^f*Y5*|&jiyFN<1NFX4&1z(|wV=BdV|{2%w&q!>)>i8vv2F^izpW~EeLL9hYWKBam>qA=wwK$RaLxUz zeZ>Z6WY(NlVer+x!ULA<#IY zSa6$S-J)1VU(}CuDJx)JlCNplvFq~o>$grC+48z!X zb~fv{sYy)@x7l(xHL0n=Aqws0+>Bu$qELIj2k&MK!&<)FO-*}V@N`p?ni@Ra)TE{c zPd7EGsln4t{VXR*JMs#FtDV3-!K&DNG{o3wq}ui6z2Zfg~guHxYM-`B_M zXgE*NY3TKfenF?{In;8|uzDB{EPC<(E&wZ(16Xe`PZ&QIny{`_4m+Bi#x7*nus~zE zGwe0?0b7l0#I@yskW?3s?3d%N+#&W%SvaZw=z_L2}+W(RN0{HQI08>lwt)y^;es!4l102 zB;ZbxxPv6%PLjBTB;ZbxJkYA?jr6uUbk}2?fVQ5hZ`BX#;3kgMH-e3>MqdMl8HB-E zZfr948NV7=47hDnFzcAj%`kK_zi*B=A;C;BzcF{4znB-yn`W5_wX7hkz172_rVPzo zVXc*E{bZf9{){4%r2VPAz((Sp4Ow=s{fF%e`7o`SZVV7_^b=+d^EE?I zv6BqsF{Ml;wjTR3OG}QSEKFdN*rn_Sb`N`uy~Gx?0GvPPp25-x7CdLLG=lwq@y>@+ zLV@tNP(`dSVx&^+E5a}_UYsp17dMHNy}u&DZLxw>M`|vGNj;_arSTFZNGZ}c(r)P& z>4J1qDnr_u93&%FSsp0I%Ad)LWmqd`%0J021iV~B2~eP&;-bPUpDGKKRmye+ve5JK zhjLGOPHm{RR=cV2wmL%nM4h94t!`0&P*19mr&3A?(SVi`*8z*@#h0{qE5VrsAfEVN@O<2aI~ zblEC)I}2GD-1&pO$3Dk3$v{~6Az4@t+(lca{6fFieh@XUjCq+b91jUy=q-Kyj2}#gI_9i63 z4%tmes-`qj+A7dp@g^j}DaE~EcNXm6-mtr|=5SjjLJ|RydTK<^g9METNxL;{4rn*E zG7W0!1ZE^clB-0Z1MUL!pY(J3pZX)ch7n*uJA<|eNZ~V_lm=vB$mtK`o{lxZTpa~Poyul1$Ml;ixh0GcTb}&f!We9>=jcvrXWxu zzu78WeJ+^m%Jt>Im0sqSbDOw*+^-xCV{da6cvotl@5#T5}MsoK{6o`3xJ{NsNb1peRi zkN=*3{P+Ch|Bv&J2Q>fKQAAwz9Tj)%*yiEB0g~T%x^Etk{HCys#EYYNB)8+nxzK)| zfo86>Fw)H#nIT#s>|%~E=b674!W9y&5Ik{(L@NYOTp`g4;UjJeH=kR{5w4JEg>aYi z?h?n_nW7iD7G{-XkSD~5usv4!fr;bx)HCbJ!x&VUb)xXrIDx(GdCm1L1 z=*TlEClco9F4a*vk&tYg;3g8fZJQ73nk~!@7ihcV3XEY6t%Lc237(`n0@WpWlIr4$ z|FDrzgSB*^UUi&B=zxE>05ru0haFJ9N(YA>P`*lkvYFZM$|}RxykliOfWHE8{|wx} z0w8LoC$tiXTImU`1ozLt{VM?X&w%z+^eX_OR(cYS!TmFE{|bN*$DV{^aQ_V4zXEW; z6y;nBaQ_V4zXEXo4BUicAZv^#;rIdl3_eOC9L5ghVYqM@mn&Yr{E_mNvRT=$oKQ>! zN|cH!8LdcYHAIzENK}`ol#)BDQs-f!lJL3ml16(_iWtqfapdulBa!Kt_=Br=u3nv_ zt^0;VuQK(tu`;zngYUF7+6-$;w3d1oy^p?1)ITr4tWsq9m9+dH^Ye!zkH}@a+DKF> zgb0AZ3j(F}4(Jng_*^fiXHlEyL9*eiN2X&23$DyUsD^Rcz;LPNb1s&TjRkBd`rr~3 zoGt1)qpm*Dq$Mg8o;+xjFGgk>IBOqo5&h(hw%qy!w_yqWtTL;XeZiV%BKiH!%e>=a zjk5nUKPI3b6HzYR917^f_F{*yt^>J*>)d0mCeQM2 z$R$kWzu;H%8t;Z&LRH~Kp$-1iaYHU)h48I#KrjS1;w$|yPz+JgKUMtcrw|dN z`r<5cnYa;G*rJoVaL3-V$O1#D3zvFmIPah>F6)L=e0Bt;9iw8_ty@=icBBh!(W1qZ zsF=!=TyTr&rVDNn6|;Ep>cwYABHW_#w5~HoT^%*58P4pYV#xh_7R@qF?9@q}LRIBO zrH%5v6s@3fc>E(N57%xpTn>drXwo)NrOgjlUimvE#Y~|D+zAxDstqX9-=Xx;{6sx5 zk;0xQ<}~9mj*0>P4(gjKOj4bn>Mdozny9|=x9oDh1_Yc~fT3=5zM}Hg7jr;4>Q(hM z?agntB>MTM_3qs}(!Q@&)n3$|w9&rbhIDnZiPcZdal73?T z$)1V0L61&}ie9!Xf0=`QeCbo9&Yz5m!Fs}ZP1}L|n4M8E+x6e|D;WrL$Qu;jT&J;A z-hPZn;r|+bgf8p7vR1C#yK;Ex)V-LHh)nve;%~pL#-wYu_LV^#NNAwXGAKJje{-)H z$Bl%`hGqDe)c1MGSbr|LVsdg+Oy`mf=5rSH48TcdeqznBzP6}G04{@!RmrYrzifB5 zd)t`doM0!}OKrz&aLGpX5itHtQ>G*H7BiR`%RDo8>|_ozzcVy320zw&Vhm1@vwUKV z;u`OXF&yN)C&tj1_na8NA^xM^a8Hb%={L$J#!x1>CdTh=$v7J_ASYBT8zxeM4+Eyf zA8nx0K`16!Y|8TzV8VVTM2)pw!F>!1tZFR3_X$=}vc)5B@4vc#e+IIBN@B3#0K>%> zq?S?_sgEQ|andXamPs3>z0&LAWoeW+b#RiHKul<79=XPxH)Z7Gkt5H#$XMHKOym+* zC4+a66K6wvBo?<_hCzz6p_s}ki%xmQoM2qciQL2T@6+eVS;8?N~o6wb1`5yTw(CsJ)MB(zu+o8oUVBKG<~X_FSTl9g{xP!he~y| zvHIQbLxwyZg8w}*cS@Sq)hPrt8a2uuA|fA>?o9-4V^P*j*H9IhMUeU;#AH}D}{$#b-ppr z@ork_ZOSHX<8_|;oS#*md5w3`AkM~8sOmb=AbgZYf3>TUjbE|N;;gkZ)8Gb%QhEsG z8xpu6+!UVu-Z7JMiif`9-~5F!egf^jsV1{0OAIzXeFu--!jvy2e(}X5ksF5ni^7!q zSYT;00C*?v)#b)ACx^=|^n^}2vJX=i%Q%Oh5%Cd8U-QM665P_) z!ZnnYIVAr5l`kg70+n7`p@ONo?Ri_I1o`B+D|+j%u>0aym?BBiBBj-rgR?7S_+q?y zuiQ$#EFV{EBg9JWpr~py?UhaRIE|rceW*s$dS~%^VVjIGYoZWMRe{w*T#3w4`c(Z3 zeYFmno~@tO3-$Xtf%Dto$HIs)! zrW=NK*#yh2%f1L{=palK^10(&WgcGOz2Ta$kteuje+OUHdO4R+N!Z6V6*}WQ zKU4eUO}EiCPSF1`x*mvd6C0vbh)WnBhcWtI2Zc>SH}O~DL5grw>M_K{H@MTWW2E@) zK;#>MFP4|a^hgpfiT7HLPxQsFd!hK1*i70lo)8nhQ-4Hop-PrqlN+mv9+zNsd*rFr2Ygfi<#g&OCjw>MRDJd^6xI2B3U1 z;4B8faUYhe4`Gh}wZ26!S06$><7K0>QLaAxuQ<*UJdd*;B{Lt-ocVMFChs7>3mUf` z;ooMT$rUg+_8-lW^PD;I1)ro6yd2p;B38U0KY7U5u5XkJ8HXps`3e<=KOIgo)$`1& z_3>PXY|iG!vG1~OMl+me$*qNmgJ+CpAO|ceVCx64qqzw7%h&TVF^zSO>#mjsV#g-y z>4-;(3%IxWq^BcGmLo_3C?OaW#JV^NWBBR(=57fcaWOoYZ^BO#x4wF#nLJUJH}kK) zg)Q8tBf!6QH4F;JM-2`4kBi4c4$Iz@@cBdNt2`&Bj7b+(g^7pzU<&;fCyC&TeV?bX zH@I&^KYr`GC+o#wU3A6F5i<7V@v;T;=g+S^K4G!E2PfaXrKE?Cl%?-}R`IjXHj68z z%ECtJu5eX?mj4%fZy%LKz4m<{NJ?rjLaF&WVX0}^h@~4f9l^BFbOcj(nvGyuYC3@V zf~5n#qv-^uZ8e>+&@A;7%=dHv)6$X=O$$>8Ff?t$2&MT3^Bl)Hj^{c1x~^y6&sz6d z*K=R%{^PgyUM<&NwL9ncJ6^uu&sPkR4-2~yEF;K>9)2FCOuj9BhAOYl@-xy9+*iST z>;DkF&o!^!=a+>ML@tua=7+~P&*QFn40}vYygTAB`x9Hz7#q6uuo>t}Sr>=*MS5HiQV^zv zEopq4edwufouGgn#a&{zu(?uX`|0f0TxCHx{`k}5(CT_~C9+~`I+DZq<-nI;uHnAq zy7M|$%1Jy!Fx~SKBZd!uhA+Vs>t4H1fnFPdzR;5NkyrW7!WuSmAUZB}KyOK@_{VGS zzaQ}aTU`2(umx=<58!lx)GP9?K^=uB#N`}$RbLUIweXI328+}q;?E*2PvQ2Ug~-GB zLi}3XC%h|N5a8O2eyS5WOa_0|2^Dzom5k+{d{rjZ35ia?Hd*^T*6^cpNx7-`Jl0^F ztZmf^iB7;@bwZ*O@K>FX=mh*#CnP%YTCE(_35iawJ*SiEB;hc&L?DwL4$ZD)PBydj z9r|JYC;f_kM-MiDH6o0@#xUbeBLyw~>x>eQk#C$b%8kFyp%~jjN`V(rpdh8-lg3w< z=g-RT+p}-qsKMwXxo!x*UB-61*xJzt2?aV43TB)0N=}^$I2FtYrjr{GV1YX~pgx+t z%}!Ulne(lY=I0L|vl=nyDy_edMTk}72B%NAI^8%LAHS^H4Y$T)J}~9Gk_gx&<#A)m zgJl3!>S=YF)WsyKhN%ZpbXvwFV)OF+sNTUp{_*3Fb(w(}J~(GiNMp=-EedDfWz(B) ziwHtcKsx(3_Aon&9X393eN`dCEjENAq^yPomEXxe&K0wh8r5Oub4$X5h%qo=IxfuH zG2c8DgdW7k(RC)z8HBFSo_X5_onijY;{sla9)yW_GurYy_+BH?VS0cMF`h#pUH5jk z`95500p8%Iu&)RSF&oeaG?#BAphJz;aWC+%^XP8t-bDoRLO4rw+M$F05}kJF;J-wt z9Xj|g(P@Vc{!4V)p@aVtop$KpzeJ}UI`}Wq>8S(?pmLVz^i*Oxu=}Yz_p7IRGr}c{ z+ickqu!ZJ!zG4ih8uKs4QmGodUyS{bussB-owK@sL^lhelW2GZvZyuI zWYwYR1C3ugc_{AcKjlO`yk`+!Xyd{UI4G&@fe}A2K;JGWem|I4y66X7>xybK^o4 zrIoVo7&=_rSya%N%O%@g{6t!d@=F za#PPuo5oREYreUgNjz>EW|i6VPZg70!-5cegI&zE0Y&vscWIW`+URUFFz((#TjRJM z7@hSrL*1-bs!-96FKKBdgr2cJTalTA(8$8HO2k<73dy`qp8sCV_a>#fQZ7VFYuIP} zV60&rwb*NnH(dQ^EgbUchQJ-Ux`&5*!lC=RA+Uu*KHU)5!Xd~0^_B>>aLA_{ z0$Vub(+vUn1`kR;-4NKqA)jt2&lV2Ro!4m5;ltKpukkw}As``3W$y1bRx04$ZM0QW zUAv8sqozhh9WN-Ti&sQd^=0gwv(!@`V9!}uRgL$@^=dRJS?H|y8tX%DP8wK64&dDywsGc2LsEF!U-t&}e)T z2Q+uv&RtW5w=wdLt<4y`Hxbb%RuD0Pk=BxSF4pL4*&#ABbokGsTvz9!k$!J2P|LJR zTm1XP(%GePIn9~K#b&{kBHx{tjUsfaF!xIQQIe+;%9ygRD(?bTH)b50>(?3t0z4 z4i1Oh!H~m!4modQ$id-|I}QbKEDDZ80UV2h<4^#{qTo0bz_BPe4h3*53XVge@{_SR zAf8=D-v0>2;hfl*6No{uvhDe{F(=?~PQn##al3%orI8zpo=MwKgs%71*4V|kJK027 zLb!}~;_R~7rML+R$*F_R_xhd}Jv$Xufnw!%#h+>g6V!LrWq9Z0sI(#6uik@T*{K)Z z%T@)Pn-Z{wxHDDv6Io+6wkzLoXTyf7^|XL#bEi$4n2j`!EDkI#Cd4@AR&60g9@J(} z^t|_JZ|%J=JLV*mHrtyTm$fe-tYSF+g?)SH1az=)&OwugvOw~G+n>$KI$cWt!r@2E zMjVlYY&*+;EY|TC597Oa_+;~d!Nq%)1RM-FLq7V5`*Ej(jAut|zqleWynn8t0} z49GJEo3{Fsg#2+9ykWVgm;Zq;3;setnqI;qtb2M1pRw-gB|OLV=lqT1@C|nBju4P^ zfba@Gp7$BY|5vCbiFQ5+{qYm?47A%BKML8j+F0C3sfqCykIM zNbjOYSCw+4kJ+EMm7+8K=!PjpoZZAe^QKMRUyZ~1p*T?I+j*I70N|gMRJWie= zr^{<)*oxNgBKe|B*6(J@Q)K-n-|tlAmPCWe{YoUcGMin%+vI@K@B^7xYB;=XmD#d^ z`pteE%!ix28moe=QeekU^)KbH`jdKnRqe4X>_q{6-Pf*T>OzJ3qK9a0 zS?jsG`HLwT#2+W^?8g^)-zmj9Xq+KEtXuA-JrI@tIb8 zK`RGubm^gq6HB$V>Q7iG~noA5A|UU zwd2@_b@yN&7O%E9qVzY7QhljW*MO!*V|_REVMcwET6ysA<*Ahi-SqYH)XIZsxq}$N zwA?|A2)T9#F@h~^aCX|uun}_Yv|DlD-f3^;z?L>RJMCUPZe{&~7@wb8B-2NVJA*+Y zT;^}_irkRsaIrvMk1r$XJR|_>2;Ceg@0F^mN>=fxkdQ)hD=LFk880Kq&8EZ zQh^fr;?>_h_J(7>nri#P13i=FhMrCvJUu<0@C}-VbLUZ>+R5AKxuvJ5U+xsV+qQX1 zqy*zv&kaX}D<#*kDE9AgLp25PlNI?yBTGlqPkL$3afen$UIzpX!HP;Cd%#w*5n zW2UjhpgiY11Bg9D!R55(qb(mKn7%b1ZTWznJ7>*DTR!k#^U;#9GNKReN^rX%EEClKBKYe(Z}RCPMF%`9044M0h}t({U??L|PSSw|rd<@-*{! z8CO^+s-n8U^O45}3>hA%@&sy)wf0(fjmUM922>zsYrD0hn$2?rTJZXKj*1TM*$r!e zdv@b7;NI-!-krgl;G6%s!dq$n_rDt6TH@Rp`OER;4cVNDfd{7<8!rJiU&4o%0Glu2 z!%LhS&As^qF3LA&ZrfJ6Z5+3P%jP^!-~hRDb0(H1TifBAvS)MVS?<@z@k2b`F)A=B zYAfg4X+RP`kEg^iCol|gqYn#|7(SXD4-}!qV2C!X|iT))26di*Cid$vfX45?anF~xVFF&$bdPU^FrB?XlFOq2>I zOA09U*$I`SE*N~N&vq9K{-JV&QUL!@Im(m+3VHSq6$AfJIm(m+N`0pA6bhB2Ou7Gh ztU{r3lqm;J>NADPQKlSRH-oHZ)>D=fG68n#^M1<-nE)qc!U>sxY-Trel=+3BP&vw! zgRbn0?5pe~mO|wyQx0fGe1*NkQm7nd%E7&@73XBGfD^j%pTs~ANa7D3>IzMT4nj|1 zkRT!+Z=L{@z_3^NUN|q9LV);&Jo(_VJ|dqxD zHm~qmI8}wiyc6qWr#itf;Y}e$SSqX&>{KTx7bwV}h1f~7Q=MR%xJX$>FXbqQ6gaJ1R&4PFr$(tm zRj_Y=s{AySE`LO+`)>bu&r}ci-~M#@ga7SMmp}O5{&e{x#onR$V%v;^d+<%}?ZG|x zCinK>9()y}T`+>Z{qZe-pswY+{i$GtmDVQ94r8+m#{a8@b?eIDE_vb|Rz5Cb9EaSjlc;_p;x!=UI~t;2!3n zEq9;T!et<>1$J`Za>d;5Tn)$Y;rz2a^y5b$iRE2>8L#p={2?Ar^X^^%#tH6T0Im!7 zdjT02P`Ph1bFGG#G#<3(GwA0uRsJcqCJE-ev z>gj-$zccCsXV&M8`k<}$H_gdV%g{d6z{yan(HK2ke-_sm`Uri3{;s}Ew}TMCNkV94 z*y(66&X{4O8*7bwK?nw1H-gM&=2K=bQ!wMrsU|EiKQcF)`%QZ&9B4sf3xV9Y$QW%& z7H$<#2WRcJj#|H16_#a%GAP>W%Dl+D%1mNrGYXT%>|o$9^AmH0xx-+pCmX@`Wnmcm zCY!=8W!JGDHlIDkLOJ^vTc2yeb>es~mK)2#G;R^M8h5V;INH7b!9iW#SDjID2L9Dq zfbg&YRGs<9xq^RnM#ULW9GFv`QE>)To%zSP0_C~-$GHNboBZQkVS)US>>uX}jg|I_ zf1E31E4vl{I9DKbsDGR*&}hIv&J`%n)j!Vl-v?lTF91W-lk|Bw(xBB8Dm87P=EDZG zHEa&tWJ5NH5)H(GD>i;N91I*F|KFTozH2VKr(K8B=4I1AyaH%o@2_2l>sAosuU&@) z%twsB+!z|O?OA`hF=Vs5S%0}Pklxr|ZVZRHpE!THF>+DgpV}hjnlk>CPSw3+ZdAP%4q2T6#bx&S($$W%+eEQHHtlhw?^wk9Jm7|B zjnTjj&$_088=jS_gBzaJ$N)Dy>k|Xq@T|@#Q7~UI$Kxv6hG*rO;D%=nvA_+_DzU%~ z&q`zfRSnEWW)E`@p2dP2p7j9>Zg|#X9Jt|G+c|K77nCA&kH$-{fi?%~Fv*#-h4b}*~8lpX>0g;-AYj0_@wD&cNivzcLw2uyP`WyOm zeX+hq-=ZJXPv}sl|EbqA9yK}|&l`h{F$N?X^Nm%;=LW4uiJ1&;cvh+j?u6V%n0;tH zXZaFxKe51_klUF7|AbspP=OnsHG~CsLT(8Q?u6V#4*n$}mj`!3?gu=$;aQIf;D%>y z7r+hA>LY?1o^?V5H#}>M1a9-_H3{7CtW+7?@T^7(xW#mzDBy-?bymR*&&pH54bK|l z0XICW!~<@4R-y*~0?*RH4bS>O2ZR9o!LuGSzzxsZZh#w})yD)kJnMuBZg|!h3*7Lm zYZef1-UrW0WgwIJjM>FF@T^8Gv|*oP`?C%_>k}4o*>Bi0tOL*L%t18w3OAl};8}Sb zxZzntcyPnBN_eQ|?TpbL!pp+zLZSe3g%5>|!hLv_2w~zA;=N=^agO+b2*d*>k=s@A zt{5UcCP5eJ1!=hCz_YeX;D%@Qks(fgL#7GX8rjYjfin3|xt`*{v&JZptjt$dDGogA zngVWkR;mhacvd41xZzo!c)$(M>a2kqo|UJ88=f^p2RA&cM2Bkq0mBE+N;KeK;8`ZP z;aMM;U`Inb@T|uy=wiKK4Y%I1Yivtz#6agp2r zj^J6T9At8zaXxrfBOcuFtWS7w!?QXI5G}kSj2C7KO9X;vS1+zDV2gT+h!Lx>l zkRZMzE)@SEl4`L~ED@nvd_ZaWN^c?K9FI9?3OVC#V1l$j3Z-2 zys}%y2u@avBVzx-0-Yx9&p36QhhrT8=loj|37C(au;_bEf83a39;4zOn}>j zh8}h&DY1*#Ag&n)PjS6Cfs5y+atpYRxXm2w=Zd{NhjG~W$+%*`9V6Ie%?PuvIm~?1Ofg}pxz6;M`Q|CJ-2BU|Z$S&Ilf_%H z)>vzrMbu>Y(mG)IQ%%61MyJ?SupEFLuU{P&n` z@a;iHdxxGt>kt2-Cp^x(hn}#5cMmTwS}!M*ZI)4;v*3e~~A^2*Y|U#?7D z7Wm7RsmlVdT>1XWE7k-@@_ujVS@{<#=cd&`VJ@J%c{||#3M}$KpdA7%)X9*s6oODt zP-;5+4VY@V_Ztw%xc3{df^qLR;BnTy-+&#gd%ppFIrn}8e4+C8egk}=@-`?N{@~sF z4X_iYo&84502$@}tL~gf>LZOHU+TMRiUZsV6l_bdFo0PHmQWgKCe1hZ1|hUjm3sUJybENR^CJ3r zMtER?=UvY-kLtQpxwdP?=I`eHY=?C3LvzvIu63|HMl+W39Hd7tqcpU8SoC#NQy5B@ z@%hEYnHa4Z-r6A(6t8L4%5NMlF(m|s@ zQAuBU4EYMb#^$cl%kwvE$U?o9N%dyV5!7wgcHf3x8bG;QWlkXqfwQ)uH;(~XmRl8i zag_me0qWoh#Pa|i)FVSZJVAIK#8V$n13V4!JcK70PY50cPa`~`c*5{JjOP(NjqxX^n@)^BA6RJZS3i{}MA z{qXe1^CF&?@WkL5fM+0{m+=h3GZ>G6X9%8HJaKr2;&}znFg(NYjKK4EJg?#ziDwj^ z*YJ$S^Ew_8&lo)McoOi8#q$Q9ad^h#c@xiDcqZVPh-VU>xA9EIGX;-?ClOB)o@6{z z@w|g)8lLHRX5g8LCk4+eJn!Op56>JtHMkU#@jp}X5U#YfPQmgv6m_J2bBlrOlgnPF z$DQ`=i`RIG9vT)%s1z>FTpqZ5d5xj!ubPMSY38TD1)Dq4;(bfM27O zWtwsWW^2RV+9O3BOJ5Jh9&vwiKygM8hI)@?-uyE;;285K^S|S{1?Rb4&fAb`IKyKK zF;A3g8&VDajW+e!;NNIdpAG(vHuc%y-)K{x4Q{{S6EgTH)iw|U+o5Mv3b5O2x(|#TL)Kno&%8*P11NjUPY0IFoAR87MpN znu)Ju+f|8IGfrObfqw)gdgo7C_qY~t8MW9&)`%ZaN`CWbbz%OlDtvgLAh4id-NxRf z$r<)AAd-C4&wq+=jzPNyUzvgL^5I=b??ADujafglECgx*W59aA_(MSU_ zhOYwJKf`y;z?(d@4(f-CHdvT61(Y*pA^XGImCe9cH+)w{Mn-6z%P1)9o;f{-f?_&l zh6Y5JF42g!PN;QwLTjye*7qqtC>IoBgf4HSp*pK#*Wj$d8G9_$s*~xVZeZQI0Y?U# z6n*)!c1Z_h^j2Ke?rJm%ra^G(DpX_^G6eUW|2<}H2G*-rzs|;$2R$b|8`VVfT)WNV z^HCIdt6;~DnjM46sQjEaulu}|xuF5*l%&QrvDm!)+u8ik0JP4p&Mcgmwq?tf*n-f2 z#fwW9mtUgrfJ>#rhYz>BGGc5+u+T7=6lC{s_U3-<9^B-|o00mMxYFrq zsJst0b?Mw{{qaQfLPcyyO1hO)Aw8Z*xQT#60RfYB8d-Q2E4aOn*nnO{6yPPMOif9d zFnvHV-dqtIE+ZFcuiSSgRz0;<$>g&_AcjdktE%a!SuKg!&@H1{o;f1|v+JJozL(vX zBe%e$7~`#T(I^I`a!;l1a$?LLNt>9zAp_#_r{o-2u)g#_+7Ucms^CbvmoC1Hkm4Jc z%^|Q$n6^bdVt%!B@amEhtHc{;)w{RR8}K#Xx<iv+{-9fKJRI|9kDSC zwKu0Rd6-0l*OGP(D2*=Kr4hKKX3~MVHn=1pKgl!CGr{AuQh6VFCg>D3)o^={svm!> z`f+l>;L=s4T`;wif&-&eNgt>Fp$DA3dnV^V8v1h(J&{x#V6;EcIt@$h19MMwOq-)U ziPo9n~og3ZnK zVROOe=K8R?U~_Xn5uD9us?E){GmJ;ZK6UY_r_Rrf)>B8|4ag8UZQ5`G#`j2}0-G$AG?g=^&^G0Zd^D3)_Djyp%p8}DR*2eG z$>_(zK=j8LY96aH3v&`ihk1?aDeL7Dxyx*_*{xUKi&Wx_a_Y6lC0|C$Uev_ead=aI z++A6eiqn$r1q;(q^5Tg}CabQpBXtH|t})3t+00hpo~UAZ12s||um`|on0l5qzi!5r2dgajd+I|vEZbM7D{c!qZeA?@+He|zC2 z7L)wmy!YNK=(Q!k05+$H*5OatD@q>A(Ldv4#w)>mVmaORw6G?d;MhW z_@soS9yyWYla@pkW?)3%mCQ>kA6t^NFzJTy6~-)GY)g}dz2XWXTWGK3OTTE-lIJFU zi>=DEgyvgwBg?RF32md*qysML{@CrEU(Ryy7`t z&PQN+`rbLKmRWb&*0Lf$0n9%*mg#cVmy( zGwI#(Psirx2jq{-B;WE}*^YxK>827ahEiH0A^Z;<0p>1`^#%uHJmssaMq+5>9O*T+ zvPm{pSygeU^v`ST>FZgh7+Q*F(dRM_%}>YOn7lC?Z}ih~&@O4?)*j-^qmD(Lj_r}N z@qadpJaG&+rNgX@)3Nx_PUaHVa?O-Y+~GE857^s3vNCNUcauX$U8u63OQbbNCw^?C zq9_#u66dxhMd0aJ{G#K#5EW$DT=dAFj{6p=AQf{H`0Y;#!Y$!EAM`Sr_@m}UMJ?dF z2%Guu#kzx^)-aF~3){N=U$9&#ukvsG#W9|R!)`>>#z*0G40x4YtD6vqOS1K`n3oANuyR`$hX(2R=wG*`tryGF z6XK)LxLV>!i0e)v>+J(#e4hrMF=GewsS<^f!7ix}KVAB#G(KvU@`yZMyg5^BGVKzT z7SKwwkt~g8tqWYYE~N+c1tHS=@_HHQM@M;71OnVXc0+tfd=y@|(>O|)8YtXdx4c^t zG zf5j6Cp6rNq4+)U%Q9Mw-wc+u(Pr$aH_}nL8+fRJ%6PToXeY+??w)MwA=nzNoM1m(E zbcmyPBEi$Yr_X?GKk+%%;Ct)5#~Y>P-(IWh^amGgXM`XeKy0hm3jHm#k|dC{2^J4Y3h&Q4Ct z70wBDSUcmRgkrN!wyGz-Hws_xlDe`gdJ(b%kcNWR29dj<^;ab*&?=1xH=$h-<-7*E-@_aMZPqxE36Bts}0* z++9L01X_-`_L{A(UHT`HL}Z)TQJQYmdj9khJC-grY2w^r9JBKL7mliZ-iO1*}@f zv|#f?FrDeC))Bn}&NZlC9goG*-na=9&QFMGzGB6Sy>W$w0fn{{)Ru8~XYvLzy~H=U z9J$4lJ)#;nRvQx{w?1P%vD!k=0qq{@@fgdB&hhZ+<1zG-dtGuIe(y^OJiNo#TJP~~ zn9kgK{uORHAM${J{FV&yDS_Cvm036gO-l*GCKs-YK~g7yr9F?i3Os|E|7Lehb7-m3!JQ1C+ZdQWt%(e?6knidUbYMU@x_NJ1wx6 zTE3kY*jcZ>ofc$xKJ`%6tFzMrC+pSOX@QgV>g=>2O1HCKot+jqS+CAc3*wEb#scFb z!;X42j7Z`fG_J%FJSD7oRODG}ao>{UK zNt>w1obr9WQbMt^LMi#LGmtCN_!3T4Qo;xYmmw}4f}qQmIhR(|$Imz=tatp9(dRbA zhK$1-v2od+Jym;B!fuo{DW`iW2=Bwjru9%tXm!;F$tw5aQ)!*GrVrX+M5X0 zY&tQP7`v1APoA7si}iO(*v>mUcc$H@<~oE&JSE=JhpnG1xMGc9CNS?ZUdzJOO6I*t zDU2-#q<^J^o$FZIq!o50IhP)LEa0)@?N$kovX=xqtPGB@kBC>5!2TQv^L4nOI)6#{M*aOewe5=8_tkndgO=?+b;(XMZ&as2ebQcIoVFA*j#r&~4#(aie}=?AWXuNJ(5?w+^=S zS=NphvP;tf)6yJYN7s-z1}L19lE?ZOgRL>v^z$FT9+h2+kJQ#S$MRQeHmoMQEG{rE zZZp@HwLM;MHkyHRit;)*%?ahZ_-D`xAI^(>;+4Tyk={E#0=KEGbPMjgy?rzXTa(C0iVY|CQklgNW zFr+FeP;M-@m%GbEHU>#flUK;u@^1O4{EJ*616gq&SGwMJ;DT+zB?s;m<&F}JJXtkD z?W_76xIo07Q>xE_3qBClYR{LR130JfkOkLv;QnpTHs0ofyxL{hPMLUCSYR&b64|6; zS9oOr4k(80niwt<#}(hEu3GKd?KH{6_TbvEUD>4_OAGU9-t#Ti1IG*2>?{a~jXfW` zw+xw>XYt4ii-?HWxi2^1<8AmC zuns(5Hf(2qo`5UG#R2*x&AajpC_`~ey0Sk?ff4QJt)7BUdnZxd@%f+4-FGlsiTXUGXsHEkpoa|7X!KRoby#mx;RbDVD$I#BGzDco%?eOiu zN6hju5jV)BShK8Lw! z9%EkNnl)pak#1))r$2NsJheKYV*n+j7BYWlUk{ztbJncvFs#i-qqV7aSpg**V672Z zYVBv!+u^c*E5c5%P3uhx@aj-K&#c^HRq8fXn#GRj4?FK6{ouOGK5G+6d3) zkZ*DL*bME-D>s}u)9OrDx{y|)c;ooSYq?qdvvNH*za(+SBJ5*g5R+1)w%=aXv#f0P z23*+0+UUh28p)ogM+YOnHF{-BdqPT(87G!r$_$LuI_!6{&|>a{KNRdpak9$gEHMdZel(` zF)+ibx9!yfbv@r2Wp33qz3AASD>9bpfbTlqPgos9G{Ln)k@!^NrzF3DZ$~ zfX!QP5t`#i>yq`usisZUrnDV6YBhc6Jb(T?F_>G0)gC^VY`)wOYp7{qgb(P>%wPhz zKy7x&tkB-!L5Ycpv+vv9|662X0U|ssx^3?`w{zRx{{yZE4oPm?I}DZGws-Jhd2HJ| zOjXh?Ur0!m0`8EIG!-Z$WS)|vQb-8d-eIk_Rr9yKV-SeH?R^4M+xKhI0pZnT5x$j5 ztdgkQOZok(x@4`dj~phGKKykJaFBR+W$w0M?Br4K(dx;hYOF-<4iUc9iVsF>z7TDg zquU|c1xE*%zv|tzNDTWt(D6Ke@)>n1bKu|=TKAP{_PTGCakG(LX1r}tht@T)Yu5wn zWy2Ac)}~bAzMATin|157shVY$lQyZgSs5)Zv5&udT~|%O`4<{9!ouj$Bn9f8bf%%z zwHB}OS9AZyV~7D3B3-RFE%4v*kvSLq-MM7W1%G!gnRCJ4olE9iaNclo=aM-WVz^P< zWKQ>kLaxXOJg6+<2@9FM2rO^BU>Z>hO|M@}UYV}L?`laH0 zd|8iYTBOURfy*M?c@!6{D$Om;T|L6W=Zq+O6D%Zg;DZGH_V?>oT(ENG%A7SjEfjl^ zyrHp%>R#Ma)Wv>ALR%uXp%3w>2E_~y-!jg#Lv^&vV2hVYyG%HZsam4fKDvJ20o*N) z%Y^~O(>;qlQ#=&?Ob}l9*fT}HX^hKhT{S>?2W>_loX~BXQTgh!4Lf^UJ$nMS_K>cn zr;`?SUG4)GzCu)-ZvSKZcGSM@!HqCn_Ac0NpT?hRUX|I;A1=3DrdOE2Mada!B#ngkL_TqoWaL-AeD2*@Q^xL_+n?= zbA|(1!~LD%K-O^j@saJ6oZ)-O8s2pdcDS1h&IX=6+g0{Gr2iobNe6r!HWv(E5FLF! zdcsNUd}ESJN^X_(TArLnoj~h5ty@PGa2y98U;OyvUW%GJs|W=acb6?(o`%ghcEth5 zvXmW)U1q8Zj%3}IaCG_qj@ZF0I4 zojX^04ySBezR2%UgpHUEsF^r^ut`=_R8rJx?eXt=6yaz-T(2GY!;T$00KX81Xv;CW zt+xg5^Qm9duj{tn_FjULZ#DtPv2gItCd~F`cXOZ#q~syCXtufAJZk=8LWOCWq1NM8 zSL;RVRcn$3vn|EKw#K4Cz!mF`1;Grwgn5F zSe}h#$FkGdMeJ(!OBN2WI$O&A!Pe!Pavivy91P+_E{U7Rt>iXwd%5p9IFJ1B0RCaV zE&n$@h9AYlWM1YG{Lb&Z*PK8NZp-|e6Ih1qDgWjKT8ZxF1h$Iq<^+g6<=>pZamn4B zz-ZasoIr)_Zcbn}{wwhPYVIiD@PVA>1lFnU<^=pHxzwD%0gr!k(o=&$ny3*U$iV}_ zdCk-UbYE%~Ox9(c_&^RG2pm3;LtO?3yX;Vx!Qlfrcpz~2Kn@-V96pdEp9hBz*K9D1y$7#CF2Xf@|;P8PQJPkS!Yg8L0Y zS+e^LdDjAm59Hv1!2O1-MO6De1+#+(`uD^zaK9nHaNzKP9H$I8d?3du1MW9usQ~t{ z+2@o2hY#d9W#ImD?;aiqoG2*ADFf#vQworMP8smWt`c<>YGg*SfdsZw1{^++fgC)LE%~{>p4;yM_j+!i21JMRt>=ExphC0LzZ^UexYu)cba1cdmKxw* z&$TeY9S-rO2|gf!%_D$8mK!Ju?)4lhHJz+XCo1!QbVwpNS(#2$COBD{PKymrRwlLB zWPJc9E0eqrWPJdC?*myMa8b-@Q5vzw?Wj!HiX%13%5+HO&`TF|%F1-2GQr8pbnrmn z@PQmW5IB4w2M+`eAIQN2L9oSI{>iA|s09gUw5J zERYR7;I=@n^?=hxI9&v|Es*;)a9bb;>fp9OVjP0o0y)V5w*~T!0d5QAQWM-3$QBm3 zEs$SY_Db z5BHA4hOxsab1ue9g7Y&)zRFRz@PAE_ZW7#oFh$m)RS5@SxRwdne%i2cVfJ+ZK3o`G z2cx^lG-JW3bg>C;!s7x9KC(7jKEh*T2HG>-nSqS2g1bqC$DbZVYYp&$Jb(Hg>5(cq z@FzWDCD(EWt|cc>hGNA@3pc#vlL8C-UX&R;1TuLraUgk`1$U`;g#izj&-ptgF%&eG z_jgKyje_(!CBa5PI;Gxu0c;ecQ|e6?fe_ZdQm;k?LRkAsy=4**!rE8rwUU8C@qDG; zRvFx+>Rt-COTFU?xJ$j!D!5C%3KeV=q*Ln6_JECobV|Ko?ce9#-6YeR_?>@h@@Rdj z4(oJ}p0A(M%k{r>iV#KiKX1euV~q(XQCb&L5r&I{3HMga|DW5qwcLMbvAd@;bOR3f86BilH79sg_ zaX@`sv6N8taW#=hWr#0J#mVA#!SRbQkR3H2N_km?VwICkj-?d7>sTK};(aEF|CgKT)8u zRKED0DDa0e(9;C|PzGW$fIpOhm<-?#WgsR4_(K_p$pG$(WSt29PzGW$fIpOhm<%&@ zX{Yta+o(Z=`bjO1RaH+$H){RldP(CeobclM$+i8a-HR_aX?k2W5hXSz&7u2Er)73< zb#+Dkq&7*_(&xxP|5d6z!v2bjbu>5LVcCAOf`ifAICb{y;OhEGIORDm-!O960Y`DhAHpL6VyuS16!Uv7kz92Go06bq0=$TV7vMCm$uG)5;EN zZ+M`GW=9px)jAuLRCM!ob*7PAink=RxYMFVz*&me+o*Y+pNs1!pAI~I+D;nP^p!GW z5{C8Ma{UuMSI;vD(+=(QNPWQ3GTla!&GA5_h0#2}w=--uSfvSo?gv{!ZiAFyv9-oZ z)kB!)jREL4KZ#>F<_6=RSpx5{3t9in5_o`X!ue;Gz=zyM&OfsRp5VLj{+T846@P^H z&ny87UG&c^fggoSf`4X7-UHfl#&%+i3>Y=))~JzIK*;!QlMW6dn-eF@e}FG)zpzg!?}CON$FRq z!Q>lqIVKR`O&1mxwpwg4e+K&4Ql{hHIK04{HIKvDm2n^U&#&HzW6Jso2TL#Xyl|n} zLYxL){~|<=d`#{lx15LbZHQ7_MvscDl$il(vpj9oGXPnJOd)pwDVp-r>t-SJ}azZIfCqCU58oc1? zs64L>R>mmF%Py$b)RGIzYq%>&-4v3I+KSqwIwUn|lBva^M!J!Z5 z2p5938gkUi)p#dVRaTN`1mWkmK`Ki1C|o8?`6o%K7g`EH+m@Gbp~i z_ei6hf{Jz~ui|R|*`5NCadB7MHPh?i!uI*7vGuW4@rC&P4B(&U7jl)aUjDxZ3nZ__Je zbV%Bb{9LZ{P$$5-lel}!x9C&InsXz+UfPf$))238hXe`s7)6VWj$JPOt`#V6pS+A6cMK|H?Xtuo0*7N2m>Mpk&+?7Y$?`+Ws@bpScvUqhz6n+$ z`_9iz+8U1KNR_}Kenha>e57olHQ(LSN{bIkT>b2`Nzb0wdwy7uhH~hm+n`o{M_nbq zt$d+=wSs=Kh$6eG4p-h#pYbeKkIDFS-+1-*fi>c1o`d3J(pk?56~c@kl-8c-v}n(V zo{8EX{1cuBwJF-?+&*s1FCDc9kt?Qb*DfgE8Edq6bkd%{7y8$Fp^SIQyljv_ z#9_z5G2@(3X@D0YLj)PGqHm6ABV>pm10?PXv22745oExD$2sgcXuz~&o?&c+3=w2t z4dZKtHcFj!yF@wAJG6T!vKr2Xvojt=6=3(UW5@O$o7Q|yJY~AYwc*hLjpfj*`XoK^ zG`pJ(WsOI%Q0ng0^qyzACkaromk;8ibV0_Hg+_&&n{)6r*PHu|ov!@$W&-;dzmNq7 zG`PLRnqGq=5^@sP@b8T69$FcWleN?Q&CAb^-q|uz{@VStn{wX}8ydrN@zQg-6;9@KF59IpG zYKA&Wj$olLdu3m)`hh1*iS&$@XUd2!v{9oDX%rmPs6!eB`%>$pJET!?P@@iM6dcs3 zLmCAKHR_N?VSxFXImJvh9nvVAHUDYWnvE=nG@3fmde2&J?eProP&H9*k~`pVHNH9L zwpxJ?qL}({_5S^>_6O9#D;;%S@rSD@fVrZYaJaAIZ?WVyyX8)$^%b)(0B3%Y{kRoO zMFX7JjT?!>zsR7Gt2Z()vB#Kq7%Wm}Ko3l64r5A~YUTm93HyA*+IF4Dhlzba%eGwK z$FOQSTus}X%EMLI>qd3NGA!h9HO`h+GoRA-wj~U2yNkQaO<~?+hpUaA?Hyj(J09z@ z;4WB0Ek9h1>X=}D2456C=+2-)DcwlfJ3u3!*Y4eit0{CdrOTzH!&Rtsht<|EYz30xfuaTlB2zBX%-OFGv z3OiZ&mL+j2WuJGDHi?6zkP&a-8&^6jOk65;6CqU`E}fVZCOt7}fY?Z$G8$${FUspD zUl3->b<|J9WQ?ie2B^>TH{|V7H{rKY-DDgCt)KjboT?P!J=j|LO#})goW8lY!m8_~ zZQnlrCu_(SD$Xq^`d{T#_x0Uub-%~G{-yWprZov)=s^KVAl%SdXPtqnq~kODTxi{Lvb2fwf$O7iXD~46Lu1 zXuZuWw?46^Fkdz768hfUfLx{=urMi~>lM*);ym`FdMGG|(_?$sV z&ybMvxp)tCu%2a5=qcW;U4WJPApD73yJa|tSIxW|*4?Kk; z(ek;KRS6R;@_ynl0xn~(m(^f=0CtImdzYhPFaQ&bh7JuFdSzB^_hgosofNYN?>%*! zD`8sm^eH^auHy1$@^$z}_-%Y7-#?>k*QBoL{N>2O5!jbhwT5l%e6Az&f-smF!z45F znY>lZd%}%n8%p;HzrL7~5|A=^;(GoOv4DR_C=>oZ0@esygfsld;_Y7b#1mr2(J+yJ zKw2)p&-E5wVb93FAvRljUTkMZ{$3#dEL{>KB?ysUlPEGZO!m6%FT*h$1auVN7O;SQ zv5WjN2AsRh10O5kHV-_lg4;aswF++Yz{?(Rn+MK$pwa_==7G00aGMA2YTz~xyssy& z*I#<~#_S`9vF(bFo`E0z;X(v{#7F;yYW>4U$U*fjzW#%{9MRtz`ph%NGgN0aKAD%- zDla}71yhX;l8o({fe^@t?_#~Wb+9W+I?XusBhs!$TOmUeQCq!L2>kiXv>pav*EylU zc*DGeZB1*b^H`{7yk&Mgf5Z6Bq(rr6tlB5kWaT2=J~k2MTV_KMN(CEqiMkR#4D^+e?`8h&I)wCvVlRNg@q0&N$AUZ@xSLTfqaE(iu<~ zGizT}f%(27mDUiZf%pv{EpIUf3-G9zEPNxZ z5q}ffiC^jKMfh32s=pw-E+&e@JJFODT8lr3{ve$HCgN;~O`Ls5SP+3@iQ2CFXhDLq z{mKPh$S`#fYh3)VC}r=u3-LyI3%bnB89#YId~L*nhz~zJ|6$i$9G5TXvUY9F+OE6E z67|wcX)i61K9U0Ti`u#i3nG-BiV}PbAEybs3OTkM@JUshL3i-Wr^^y(?4;>42>G?ZFDQHNe#Y`3%ZbVtFi6e zni>)ke0#u798fl{4H;gJrB)}y4l;nrmTYCzhA}sd24+k1858=L+pIk6r1dn@n;F6k z*m?6vcxAKZb#Wd6%>$b^&xl(-=!p5T6>WUSfPcW@nP&S!Ll#8fXM#G?F>`k=>;?On zADFn{cI?mWl(q!RzQ<6oDG3Xie=v}HCA!sc^DT3hc|u>s58%`v^Bo(a z9H+gZP1hFhzr^3fX#umCMOetg1B5p?;$p){@og^{+u>q^1IBi^*!bkXFRhohOAZ$s z8pti>XXHMz!^H*%jO}o-;r_Tsxi??28AR6pZ)YsH0YN~2;vBwPj3q`5%)mZrh zkv@V?;#?@cdIr9^G1WNX$qJLPoFZptx=?uNL!4H`R9Ba-SW&a0Jd>CWefsR}6TERw zU7QRbZPV7mfiOP5@c#by-yc^82dw#-A6XxL1lTS@%zk9MRHJEW+J@Xfj9yk(e1>r5 zO%tPzg%^%T7fNii=*(>LX2n$7-YjbwjhE1xXRLvN0|&-bzx7tqThsJOefpQ;qZzv4 zFYGvyqRE}*g*Rb(^yq3B>>1-(!h6kS`!{;#e+kj8yu9ztMChlodC$b`!TR41;npgq z`XBTD@sDBpq^~P;HsoAd$@k>>m}<0Z4ZGbW^fHPqBMNE$0_3T;Nv%`@M+E?20u4o`=S>KrVGmdwUwrSpK!|BB2{IE_NPA5m< z+n+!9;|)b&S!m13?>{lB$(<%m#?|rq(=KLbCq>sQ8XtgdC`0ms?(D+`CAYvWqoLWV za=kfUU!{Mp@6+K2-6q=XL0ihX-^cf>t<1k?9Af}$jtK?RizWtK$dK{%p?Z9s2ZkCQ zOkFG0{?P2Sn3A6QX7kO5&J<0Kq9XTt^`(r;s;gDa>+UmNvPN1^a(SCI-*dY@eL&Pl z!upyon6H`f7M1?b|59kdulf!BLF0Ap3GM=Otzm%&e)LRd7qe&Cf3mf$dT=jua8~`N zTB|nlBy;n*iPj?wv}0Z{%5Yv>$d~X$jfW<}lY)bdCu%(SW8;Y$5B}Kr|A)PIkIvy< z|G%$DNu4rH>J-9=7NwXbN`o?@rKM$>s6#0uX=$Tnk`yUblSEN8M%XCDNLmzSM6n$+ zkvgVj8m+UK1fi&mL=lH%p6j~D-TS_u{rrA=KWly0diJx{@9%B3d(}Ok>-2uT-}H5W zw{1Lq9pG&nPhSUIkt!tbuLHbo2`P()=Juhrb*sR;LW>vOGoIzLUtJvuGPpcJ% zXN1VanN?vI%W%-`uY8*#6FG%&TjI=war*+pYlWRH#K*Yocva#I(thI&tu!+YH)<=& z>C7=MZ&LBfvIgNE1@sbqb#M1^(gZuO{o`^&T13$ zOLAA^nv4}caVD0b`VmEUuXWI#`sVu5!G5@WcCF!R>P&8{@RencCKUu4B|vAfL#Xj> zk9ks~^LOp?+qI%RFEgpr$ncrrrNvq6+_c%~eEj|hx~jNJ3y$?i+nVr{-a>y-@1qaZ z$L>6CTs9JVm~WYJ=DTz8)D#|Z50CJPGili@W5J-scS{wWAl%9&N4S(guC11J=OQjR z>qfxjYuC%B?Aso+vTQ*%El8l$jI;vPFKrB?y-~wzWI@}To$c50@^RSMWFFo<%z^}+ z;u@~2n;D#39}ZA^j{2s`eu|0133Dd15-pTYF>bHVN`_(Yn4ntOmd=c0e`1}aqW=c( z(yJflXP3_NLq%oDc--gNK(!4g-lBabCwEG^o7yZ9?^(+`$v1w$3ft6_Cw$@m#TVl!fn=Jb5$v z*S#vITv6(&ot02^n9>t#2hRKWe6B0UM<+Bx`HGckyk8*r(H0CH3Ky*iJ{6Du66ao?< z)stFDA4>nXR^mCk$aySZmxhhQ-2`T~b?Veb{!C7nRXNw=h3o%CQc}|-KMJe%Q^*q+ zyiIY*6W4X6wIzzN?(Ryl1~SE+uG3pJS~k@(2gM?=<_(RG@u?at)K+VBj6bK{)NCzC zhiCLoIwfftDmgD_>hPm}KtH8l(;w<}4b})Z;1y$#@qs}y0!Li}9(jqQE`bm95#}s& zsp+q-HVt#O0c1JX&}w6Kv-(@2b;g7n<|1pYwbT09Dzq%i&xWV%mi9|_szrBxY$k2^ z*4}0xvd`Ez>`I$q!Wiht(4C+B0!WIM&48~IEef$sA1PV^3*J&RI`jXF1P!e+o$v*B z_5!%W7u?wk;0|AKvKRWIAWAqOtQD@I^3V|;f}=bnlLkk47nNL|QtQW05)=+D# zHPwQ77LB0$Et)_dSaob@X1`$51#XP}sXfPDZi6#4T(&(5*4dXuMU>Y}{%i^|j2f5SS zb=*9j59FKkI7zKeJA2meY#1-_;Yha0^o1dQ|AG z4pB*vN|D6b>Q5>-nH-)-4j8SSlhPH6E9Q04I~f6UhNiCWj}I1Ds3_Pb3F8nH-)-4yevFWZIxb zL4QVM5}D}?EMnF&JDH!ELdIhJ*r!=&$-cz)WrwrlSeea08+0Ha^fL%|(>6DZ>&QWG zZU`68ea5A8Dwoau#K8&fDtDi&%{S#aK8hd6!)V+%&*s13H}X1Pz+d9w4j&+dJpQ|n z#VZHQ5S9pJsB}~?g)+fkg!-ay)B>y)eWMnj6Iw5MM=gN2Ee*NSfXmcQo-41AHJMy# zphWhKT7Zd)Z`1-*S3R~gmfWV>v_P+3+21s^T3TJanf6cY=rR zbl}daCAr=#$0Fk=gWU1pzERuscE}hhxgTJ$WsSa%NIJ0_h;H~76!iYzx|dU?wYRgue~>%A)YxEW>!8cF|yp4Ovw+CJmeFK%? zl;|6%1RqGgfl6>s@(omiS+Z}S5;RoYfl96=Uy`B7^pXBT0_voy2`8|i~z$-DK9+xiNzl7QC6=YF~AJJy=iHFm-PoFN9c-fIs z;4->p65a|T{iY?!Q$N8)am%EUWdV4Sn=EgT9lxid+cJ@g^s_;>%YIC24E7t`UHM4y zSO|b)a7NY_RBY-hz$%l~x#|j)LLPrp-%;Ts_3^J$qheFC>?-aq+hn!Kz@1+1I2;?C zsp0DPUwomu0F9dqN;5EI>v77~!`xiINwkT6+W+aNOSBtmrAjkJLlrGrRfIyi?Kr3w z>E-&TI?U1QX{|Icw(BqJBaO|dC(w5o`6%_=WYD4j^_?e;2}Wo0W782EZ#Chd`KEHr zd}P+pUNCwYuUbH+DpRbltd-VgE6@7du!)pWJ?$9#eH$j(q@Dl4rjzGI`!7482GfXH zbD(Q6ik?CkaPw+6v`UT9!*n>u_&N^2N35^o06b)U9S2}8=j%8CO?Y3&0ocI%Iu1ZL z!PjvBeijM^Zw&3xa4~)u3TYAH==LPc7=-fBZPgmzlyPNDtA-hat7b%#WCib7746H% zim(6X0xcefg>4+>0xfROo!j^LL6>^ibY)&`#LbiKio8OeBJmWC%P=Dv*ZY-&r?wbf zg?|ti#WP|8P(v|7aza99#9U=rHdQi4A#`E8qQY=59k_EmrtlnX;f*BdM(f6zjfKS}AT8 z^TeLg9Jy-GLvoD7lSftdoX129Lqy9Wh0+IKQ6G&{^$Hhz(WJ6T_8b>`vBsp-tuNOl zojBolB3}7SNmqVT62-OhL^YJtdY?pP>5;hX*&R}^;xo3bT2Ll3F3?GvuGQ2O5lJd# zhPGRUqpGP=p4c_TvGzk2_>#6wCriJDN*DDF6^c>#SE&y%3MJ7Vs|Tnd z>Kl5LampwPF*u`>nQW$>bj5g~^!ki(!>B|b4M;U_qcx;$_BI{sjazlC=~lQk>oVR; z;2z!x_vVxFkW9rB37X8T0MrO9(w{abTD9$^7R*w~+sKKC`^MgAgKihtm+U)s029JI z&va)%V36%%W-#PUx|=!5fXS3G{%n1=HS75Mg2bk>3)$5u3_Zet zZ$<9#x7(3;r7F$LLZ_vsS*V$?UFJl1EL&cG`=)((pDx+5y?CLGwwo?!;bC6hH3wSI z@s5PIys{o+J{dD6GplVXp02~w+(1TV*7;u94ff*dD-)>^yO--yedLIGgpkl9$5&=P z!#nInwE3EJ{vGM|3-~aVY^h$Itxf`mqZcUWIx+t;_W%$&V3? zx=Hie#^MG2NM5h(%*@07hY#P80^|^UwJZ6KQe^L$#Pibi?PZ@QXa$CTno^G_GW4T$@Z1_}p)WBIh<)l2j~h zR30`TpLr|;Ps#~}I@yS@k@)zw$x0~=d(gg=13tKWTWv>2GMX%mKr|z2%g7_ppi5(+ zozO!#ES?o9Tn(O*k~$HzdQxyQ#^zNUg#Eyv<6APSMgPWQH-I2W--r%foaFEBlrI+C zoq|Dg&vHZgEMe8~^5_NhY@?93Fanhzi9$kaX_1gD%^r^u)xwCYSUzS;8%809!H_bo zFk(P~oC;_4x73;1*IEnXkxEAg=%qcOZ&xeu^6>IE)0Fv2LRNZPYy(#IMU~&Sv;fR9 zir3Z6efEus8fij;*;%8!u&T#s>H^mW5nZd2hkAqU z+qX5Iq%D8a$f=JC!=npwg2Mg7!$b0NnoeO~Bc7Q8DJ#jNk7#fJr;8D?+p zTaMiOq6K(QsBbX*QsH5vX6y@W9G}~c8;@$IDJ$|~#{~JH9}|1HPM#rYd~;!C)7)Mx zCdRXu*$({BS6a6&Yn{Geu(0Db!c_v0S2?=92H%M9s@4&!8Vqvyi;j^;^_Sj`h(@)< zfw93t%E#gweyTus(edKx;VnPGL`(i5#Tw0!ft6_S9VN7uMhl689z7N{Lj4NzhZ7Can?{DEo!G_?m8! zVZVGp%LP!wWz10 z8|6L)$TjI1F_xA@v)&Cp-X#81cquSnO3J+qE8ntA_7-1d>hP z^#}x5f3HVyjWNT5C6@1c1X|l&>^E#DJYb=n`9Q`J2B_0I5+S4ZhyaevH9J~xe`u33 zP#0ZT{`)7t{~nc8Edzx|b(!;Qo$?Hv7NU|+EjYE%7MME<-ZYx&dZ8Ybgss_#Y6}-O zT^N;wugQoS)tFzH$X0dJv{C*z$TgjLArne5gRdRigMEvQWB=qsrAdio{eQh#tI*`-{)vp5PHRWv{c#zvJ(a_;rLZ z>-9DMYt{rw8_>ez72zm%TYxfd35Tf&?{4Wdo_k+xz{BCElY~{`Vj)F4DbD9wiBLy6 z*nTWOm5*bd6*@>?e&kC2+9iF#x(@H}bl{=69K+|bQ>30!x$>d3k}_7ht_YSd%bn$+ za$}_(UO|fjw`Pigkx9cNFcGw_bHr_&jD$Jx{AER?lcUc_=$ zm=+v;G+IV-gY;x=mR-fGWJ^o>69oenpj30*MbsE29F3u~`cVqkNxwoSx8u-!FI7%v z4m5LVdT?ea=v8&S7@Hs}JSmftu9wWioBNiVf$E=^-kkpCoBdmKF1ub_BO|qJm;bI^ z*DR;~q~ls>xcYn@R7c@`tx;Di<;@#Ym{;vg=0|4AowVv3yKUT~HNT5eAAA`DAfvk7mLT;sy3i3=$Q8 z5vIw132mj9rGuZZ6d^&%6EC~O%FCn*u~$uqlj_L5gkPi!QqO=YDM5xwi8abd!g*GF zSsoydlHsmAimQ^_DLs_8lsJ^vz)a<9WxcXTIi@&JIW)lfNL2YqH36Tof2croWWIV{ zEmc7a)}Ga%v-Y|+O#4`yrp?!~w5=K()EsouEtUjA*u5DexT06+-i*;LGP9$(z#pgcIupFT~Il!L}jDv+^cyX^SK+-huIHhUB`6N%l-Xt6 zvc|A`n10N1_B;RYzH7t(Cp^RTW?mBFnQu&Rd0h3F#%~o43U5hm z1$ZP35a#m{;;Z6%Ymark4Xo$B7LRcW0!lAmnRqlH5voDmN(snQK* zHhP(ok1o(g$K_=zzb2E9E_^O4a;E&FOh&roqYI9aF4;7EppcL5|3nZ^t^<)%EqzG` z3ZyBaK$0}pOGr!lFcDyTqr(2luhMq!;>=kFp8T{DZoC5qW zBv0IeUMn!bf53n)$McU~&_k_iN4J=;-#oTAN&muHtk*L}ns1#V{-nEks!^}v)~%bi zp4}CdynQX<^Z*H7w%4CIo*iu0d+ls-R(vlj{gekVM(W z;@Exy<4zK-&zMEl26F`i8|=E4KkIj_?a{^v*!5uGYhxPwJ=)h7G1ctv*;aPw9(!hY z99Pb;YmJ=-{A|Q?bD4BbV+yQ=+#L&Avo5o(X0r5AVjLkXrk$;?r@5#s4KgKQKN5pP8fD2l`}vuD+wbd5TXAM)YA(j@nIC6Uo$Q zqjpNoy{0xX+T@qxoHK0W?%noom*sRqLS;gmJcq?#8`2`L?l2-yG1i9tx6oH6vL&L{aL24T&qz_YMjj=wpoQ*v+vf5fN z-=NAcZ{xxKYb+qy`c|P9^P)kqtMkkv3cq~a3T|InMnyPeWM}<#y#X>tjqP?eE(IM= z^n-$nT&ukpCv>!D`jE%Tf*r$t&-CNao+(dXZe7{wpw3^i=Mk@Hg41SYd2Fm-Y&Iu0 zj|i(-vR>FDq_G$!b(eFnLuU;S6};~n9=;R^fAg&25i#;z!^8KY?;0K=CEqnX9G1>X z-hnzWR30mP2kNB!AwQ7+4%C@j^suNXJeYiRzT=6T`0A^PdBNdT!@5w5jGH^#Nu5qk zwn=hJ(J)n$^T;jz9T7`uX(>5AJi{=_M%lx^z@Wd<-Y%;hxr}Jr2e0SeU!> z;Y5nvaj^}3`S+BG%33XVn=)Npr0)K%Sw^oij_bnB&RTF3NsF6`tw4}Ua__5}%ei)5 zE43(c$pHR^wUuT0M5hIg+k)fF=q>A8HfR$UK5yneL_s#Tn3NHhIo3uJgv{`tyY$?1 z{c{k2{u%d5ftBTmI#kaapIw!m?+0xU?CL&JPtfBIt3)X|&eK(c z7U0T*U=ye;ACsA+v!JazkVsP0yfBa$sWzjwOzOQb=D9o-ZI+J$tv=C&GluoDR!q* zM1JvAoY}{f&n~7;B%FVRugTD1!AVbqYs`OzC4U9A62)=YXh4hGEn3XJIJ=k#ibHs? zDjqW+s8`v^lZ7Ym2O|woIfh|u2C!zJ8uETYvGmFW7vS(oczETQuJ!Trj*_dACp_jD zEFu>x$KX=mq8Oa&yKr?DxR-E@*%zw?<&pGGMB5|NNlxi=Q`M-6yDByUKRg<~Te^;_qivjLh7GJHtg; z%kM1B@@-PFbtsE&3zG z9-fq;nf8KK<$^Fq8N1Y9RH&xz(DU{4dS_+6(ZT%Kz?h0UE@}QS{bN1iz$U-I@*r$Q zdMhuP@d}DE+8Eu8{)S-Dt@nT-nRszncz%uf?uP5uUze(-=9C?)Uw{{ez2!M&IXQkg zq{myK{bZI|ln4Wsve70d_p3XytgY4-+b*Fb9t`3!JJa&8(}N{T*d=tB*vmFNzrX@# zM_WU0q_^FBk@*Y9CG_iS%X;kk!13$z*!6+q*XOb8!?xrw=iqpbT_5z}hw?PeyY2eG z@$2*0^?~Ep=dtSp+KV<8-FAI{%2%;Qud}}qk+ijoU0uO1zp%g1PGyB?h$muX8$`=p2PHYu>gh!t%9GbgeyA7%05?8;SDVZ|0+Yqial)7NQeN&bc%)Jy-G8JAr zqTEyb7Ps0LlX}Yk)G0qSf$p?mOX9B7X>!6SHA($K?NE#tli3PJPEA(6RST3$%4+$N z+FlFgwcc5{11eb17*pDigm_Ym({^avl|5RihCi5Koz@qaU829Gt=INQa7@~&AJm`F zDZZqi+S~{&SD!O*?buzXcLx+B)1X)UltD2XbnjdN zahf(z8?7a4vo%^a$qE#pP}^-BOuoSoOR_BelzL4io%U|6;;80t1m&aE0zB*g?6dD& z48{`Zc#q&Ny;S@G^GDqABae6K{mvY>+G*?c`6gtUTg`*!X_Hdi=%fRln~rnR0lK_9 zHy!7s19W+JAKvMtgHk{DO~*Ou0Qnp^Hy!7s1D>0XbJ79NO~*Oufaj(&m7B+{;$RE6 zpF7F@!9C#W@Xh!a_{d)TANtrc2w3#xXYoKz|9g3|!E}uNE7}O%gx-A!MIG90=+F_p z@bN5;7}+~;WE5)jGmW{zi5`=9pu5Or!Sk#DWK%qz+$$u|UY;#wM zTtIO#tB;?+_^)eb6< zmFWAbbItof%~9c3^`iQhT0?83ja8o2252dxv;pde+G1_hw^O3JX4bROIEqkZ zHlWb33_sIhT>F~CO&Dj&W`_B#xy?Leo-uEjP-!xjlgCCK&u12-TSVjiWSy|CTKDl} z4NYy%jXP#1`ULI-)#Yq#SnbOzNdI|PO$D|@@f$*o)Kz>dh!@-;KNI5}H zlm8*Fk$1>*L|87CVjn_XN@uiY8>Ya=3LVF?l)t1+%4y}ga_h8Qt~6IWEJYv>Y+AWd z(s=-uv-YZ}I$^Z1c6lxSu<9m!TWATCfi_f&Ta9yP_?7^y>fPntN~T89T5w9craja= zkr7B}(Om0^jDUMO6$MXZ1k7?}MtCA4prP5u>}K{i-H{Qn*4%0SYmLoiERDsB)xkrB{PY9n=% zJdqKwR@y23EEP)b$Ow2zcA8pQ&X8S}kcVW-jHr~|krCizMtCA4fXKVrswXl6lGWL& zccME`r2F$)cTISl=nhLXiU#sTMnG%5i|(E14*%4T=-!F$@R~u^VV=kcIAxHluO~7B z99LgYWCT#8`~ODWS=|O_W9x~G_;>2gZ46MP`wga&Vc7pEb>|EomhkKN|1NcBqC%;R z|4!YxO$8@2!V?(*PG*EBG6Jq@j@;KB8G(|{**eAPxg#SWzz8v(H$0IMu*6tr>^6=X zrcq}2oApg-ZFVu=Fg=kG@K5uIdCv4iM!;*tHSG8(If1alWB-aES8_t%D)FZ)hD{<$Xizz{!l*D3DL#CE<<$ z0ithc9V`)jL+hZm#vDgB5KqYX|Pt?sr{^ZcJ2Qick9(Q{L?;SpR@mt9%kS*<{joEhBWwe z|2sg){x#+yQx|oF;p{8yAQnDgC!_7w3RYwHvA?k;EZk#ja!t7Q9M45_?{O13n8hvS zHgI&$BL~6ibh~SVt{?q*ktaL9MLewKck(~;g}lZ42~P_x1t3+{aABMv3mL+y=M-9y zkx_f6f6aFTYRVs~bv4JGeUJtpXpTF(rjeMi1U=5NX=|dl*WEoEI87V%Y>r0=I8B?U zX9K5c^Ym;LFPVK!;a8k_|1}t;zd7B6MW%0whL)CZiH2>KZ;6K9wr`0BcdV1UM1wcm zQ@~tez#Z%4P6mV-tZ#{i`kZfxhSi*Ji3WG9lRMQ3+_6q|1t%F0oM=E#G9Wn7fSwW! z?pP;xiH7QrW1ZY38r-o??h*|xW#1AF+hpGo4ZRiL678}D@h;Kej&<6olJov072L5- z?h*|%G~W_^tG@1(Xuxa~hQd+$>&`P?;d;k&TttoRq@h6BP6TQkq9y?Q-U8kIy8z#2 zzR&>QW`3LrzRi543BJvIy5+Lg@HF#HZSZa8H~xR6KLvM_?(WgSY0@VOvxKF>24SxN zhER--j@8A6B8o@E{vxg^6UFHwWj>N8XrTy}=qEibwUl0x`bxv4aVQRzGNf;%ZPFp> zjC4b)l)zCp_m+pq@iG}MfGT?o7iud_6(FMpZ=VGqqlHV#9fjn;Blo%ri_U##0KwsRf==08TCNlmc*Sfu|IJQwuz$0GwLjDFxuv0#7Lb zrxtih0XVh5QwqST1)fp>PA%}10&r@9rxbuw3p}L&oLb;11>n>IcPY54rZ~00DFr1n z*LGXGc48J@1xu8G`7-W?0mbr(Sx`fLQSGA+RmmNjBy6xn-LIZh|4<*Obu`)qqek*= zZH)G*HV0+8o3vaFj%$}S@+)?X+TYUAZhV41QzvQU9vu&TI+W{A7!8c)jIIXRxF;Bp zW;mvC`Nnyp6tN04Kz`OFi|S#Iv5J4c-KomENh?y^Z!?%+n!nHG%JH-f!c#?IP+smnbD8n{dVGWbqc)Z|?;ada3QSi^^Y0oHjutoh}TPKa`JYMH=0&X+eb{7;oxyk|RaZ z8a-4;XOQzc84Cv+&l+q}>V9K4_daQmz}1j6k!wNx#s$HJ{_3dk#>?-rxMp zbVY{}QTU%nhu(S|9r}n?q87H3kba-^+kNwr?9H~@M!OaRzBby+m=uqVHeM*2B=VR% zf?r^Lw&PQ?5YI?|@OIM%iG7fSaK%2OYLp>A^ZH2<^{efhlXwpu6w~ignU!g8gp2-g zl#a0{*sJV)wl>$4c}kStwU zj93C+>&Uy{(R_A~&vXZMNiU!0KX2a6@m*!yh)rHB9TtGLY}Lei!>`Nr#I{Q0tYoZ- zD@LN$EF{i_Q{W-cPl2ZuYRhg4Lt}RnZ({xv|N}HGuro z$d8Y5GsspA;>-!=O!I4Vy}8Gv41kJq^W)dj%gF2xy<@Y1jI&nSD^~)Ef$RI%uirQA zf!WiFvEH{PS@5N`%yQB!E?R$CHEd{Px3yok2iT)*@_b!vN50Hw+3&uD_vSOUd21HF zS_M_TqO!8bqz34Cct}i^YQn;PvL;Z&i-D`VRvfyAu?v<>n zCxjSH*qy?_dYGdU7AI4~f>+q3F@cSX@lG2SHz#VO@dFEM>>c(o`!BZKeu8OGvon`l z&*;bgAmyM_c8`4{MwE>Ri(45T5lcHvN*`!bZBulM>b-;)*wVO`xR?!#LxG}2+|RZa zD8Y>^$(oWnHWeFO>Io8J*-u!UBSP`C92WPehhJQ#D@LX<>xz+C!T!i+atS|j2e^lP z{|+d;ACy-$EfXaPL?KxuNP8y_ufH~Brx1m-Ck$6Y)M>|d-tch4hQf$#1oC_`dUV)= zYT+o$?v%fLQl~Mg_zEwLnG+s;DLQ&%%(9@cSTc3%FF2+!v!zo4*%0IwNFRw#>uEd} zA72?C7DtiWt5;X9KGKT{$k?&$SkeKFPFtqsia^Wa7UJ9d82;04bNJ=mZY4>}`7KiJ z2UKrm62zf~q_9O*=P0UFs5*j-Ee-s}&R8IQ=duf0#zKWyOA1A7uAbUz#aLmg0Q35H zke*Pch~%BWSsbarTO3{sQ0)BrXO8LUW35YsxN@+s6cc!UN@ZjP&M^iij2U8yhS(J)O@@dLR7E88EJ+GB?h;5l-oKAh$Z%* z#E0434%Qz}Z%XWEy={%RO28(QB@!H7MfKr|iy@ilqg6V)6ou&_S-IG1%(hI+yKe=z z_8y}uaY=g4p4YbrHaH;iOiA%;h zQq}-bq>wB)n_13Quo3L5>|pjQZd1sy5aN;w;ug0*al$?U=$8sjny^hs_K?lK!NmvX zEJn2(3SdIANayO;8D&`^S*f3-ruy+Oy@22G+7MOXEaTmsiXe4npkQl4T*iWU5L zK80Vvzx(u(ZcCPgWa0H7Oz`gsaT#%btyc6C-WA3RKkye=z;M0x7#;O|mGB(bLws|{ z`Lj_WnRqqmJ95=3zf~bwcSko9Ul8d?)~YU$HRu|lp0rZlEZ^mx^lgw5i5>ABhz3DQ*n=R%SrN6O?6in{5iWcq2ArXmz`A}tx8!R|8=o(ahc zUFH{(iA_*VrHN8sD|(N0taF}cATyKABwlrq{EUi+@}HHKs-=9cIvIEe)PKKa*+E+t z231&_SEsGMy?S+Bo!g8uIS4>U_V$0fAc3l9KhD5&T#$e>$Og&df|NUu*=a0cP&Q$N zTzK)t!WX+NK+0it+L0qokAz&nH|rYzo;lG3^1Rz%?lldw7%|Z5RtkCE{iw88dG#p! z(PejPOT5Lu9DrJ|6}Ww&aK^egnA?6fYmT@WVZUpSv~v0L$N9@V7V<$D3E1V*Wc%m8 z5Vt9mUa=}>T+gwa*T!2AZ1>;3y?%`(JHbk`{$Z`Ls&-s@3@X7jdv!{LUmEjk?OpaQ z=7Jqrj~!E4T8!;%82jE=SFzLR&b-zL%d>&fkIuc>g^gZ$#dO8j)L;DUvn++MbgZxb zR4*qe0MDnY;5vnCzY_P`I{}Sl`<8}hD`BC@qqYGi%$4;WmSAU z{CQ6J|33RSG+q7XYkd1-tHl&7Q&D+}&vIHZ~B+4 z`gTHVn}VQM@4~xhVbZa)RDzmHYd0T1-t>5QQd(NtYMoAX;C-v3QypwD@C8E~vD-#$ zt+TP=iGj!W;Q=+w?0EjV__hfH^ildUeYrW${6W8vm}BPtVO}@hq}Sv53)|3c`?KoS zkUvmb7%v(|l~uvE zup{k$l`Xh8?YQ-It8zvr*8@GDoV{bKeBeivJZ@5=8Npca$B zcc^=e{m#{ppXFgQQ^jw!PqO>DK0=-6^LhAG7{FF=n}ksQxB$#p9#EpxrI`>Z_7kUG zy%2jg_7GaS7RDtN=cBaDFSJWs=h4*?t72P;Z;KH!q*xKc+rnVsb+eTeiLCprBC(p3 zA~lG`ZUh2QQMqD#kH>zG;5K}8{2nLBFjM|oCc{U!-{Y+Y%5zFr<@H$LPVfI0 z>*th@%mP(2>uR>zetlAOT^?+|HDGv*uf^i}#IbH6@sOaWH8)xEBl?Tv2l-@g6PyfNnGbH|J) zta9UW9jl)i8Ec3Zbm)NL1SrBBWLjpdRl4C1EQWhy5F3hIWSz1KFJeKAXJ%P&)M{-v zwQP%=f$lTIZK!Fx3C?Qm$p5~oDN7ru_L>_umv-p?ZbS{9%SF*A&q^+?z&mUyuhuoZ?SmLf7zbH z{e`xaZ?Px13G6Tqp5!msk2n-OvvCMyj^%UFX13*eZa;sLFY4H?o!O2i;zG=_u`$fX zm1WcPpL=8QxhRZyP`o!f0EgXd-sJa+wavZgS1A;8zv*OF)kgS8cqD`dikZD|NP9}` z+p~cLZ;BMFkS6{^TqEuf^F=r>mWm)@IE~a;f_w*4;H)AORBvmWYs8PilY7@~x{t#1x z`ULVhK%&iFGD$~qVSPpcM)g%SJ z(4l|;QWx!&??R^(^d$hPt|n>m3Ve&iz!Hs!fo(XE752J{4U?aKmC|W;G|ib*);9`g z(b;#We1hS4y0ilaiBvB1sygEVb`0b6L;8I+_cxuM-7sU|4^^qXdR6x7OFR?~GkzN@ zl@E*=51h@~9%J6gzKBO1Fm4>~5gmLfI5;FPSpV}UEG2tp7#%SM5&idj75r3CF#B%5 z0(2@lMQJT}N*nJ@Gd7!R3}Wt|AY1J(OUzG<)#gC!$XU#&`@))292_;c%Opg7mRUuo z&AgIeqmCW34xeS{YYac!#~5miw|^I=*voGRpnE{e1~}b4tg`;FA!g$yE0j5IJYdrQxHxPhckV3P*|%4%pfN2;-2ZpVO)?Jku@CU=yq^X=xDUC0!q<8~_I-9dJ4yqh zeYbNJTreNXci{K%;O&A;Cdfbz3{GFTLm(666c>ysJ}Z)A{G^sk^`%QGs^D5yXaCNf zH}am%JQRw)n|YwUm1i?AYq=TPPg4H}n2gtooICaY_la(;Yf!>C6t7I&>(> zinCw8huscC`7Wf{B!{<@5Sdr$Bp9X6QfJ?7{s|7#>W29^wVr4}VKwVk;yZMr#XS`H zuUmj}evl~x3kRKbYT(0vAn#L`{Y1IH_+qMSyu+sBzFH-G_c#nDWzkG$J+WUosr)gW zaHQCuCj2Cs9_VU!<)s!Smwu>-|jKN2b8}&@lUlfa* z)iB>gmcEg(OoLl`&c@@~;d8r863%~t1~6#1eb#*2nrE&uFQ)e};Rh?u{M8!9d|Z2z ze%U&%!vwP*wy7(v6nn7oogH`+df6XZjqR_jB)d6t*Qke)9M*no3Pbs}&)U1}U+l;$ z%wGYE!*EU3zt*(y^UX3kXW*i(tQH~6ofe?n_$WiSerTGJ0yTGfa@%M`G9R9^nH zQhy3AK0@YHg*V&XtXXU@PA?(zKI-<-N3p@USP7pJlbV*rlq6P*U(`T*LT;S8_R`w5 zvB6{g((sqQqT7lU@nkhZ#9%@v2N|47U25<>oL)m_(qbq8U&Ih)mg+doCKzg%68qGG zOx$7@u9RJQEsY!Ztrps6b=3@fJPPN<28~Hg>Z)Gue=(L=rNYIbV=`ic@PyTrYuJ3u z3itWAm6yDC?9|bAkSyzFq%L zYo$i2&~F6-vfuPE64aT-Q`Q0lUbJY**4SugjQ^Z=4N$7TYmx}HhxV2hx3QW5r%h^Y zll044g!Ko~P*7piG7~-{H?lOHR&nr_S;HnTj?E@nQ774@Q*Yz8?0yV>&ZU#9u*HZC z#&uBXWQw^diJ=9|J2qK~|EP?%I@+_X*BBtVLxKG?(~@}!&8;qN{%A`YBFK?C~+?S7*KdLLProMh^ zXvD*ah?_~cVS{D7!}Z)O&xy`$bqyuA!`H-iO}vSDF6;}0U0sV==67&k;7yEl>9((Y zf3#By9L<8HdDewK^ULP%?L(wfAx#cQN`iYr3<^NL~04^rn;oNS@KUB5nU z4`4kCLW$ObgogGY~%LF)rFQFXQiHhO7zq^X+9KzhNYJ()L8+dm7&8&h>M@0ns8HU=B35HQ3Z+m-fV z5E5`&2YSRQh2~M+tA{VyW2kq1Lb^DPWh$B7|!Mw^0WIDwnJL5{DxigjoM`g~s%D%&;_BVQ2v6y&7h z<2`#pRBxFqHgTOC9y6~)A|837`m9XNiMsg7#f#x1)1vUpOzamrGj)6-ewvwS;}Zjg zN6m$ZK@J|(rF&(ssNM)iWiA+*or2_=;4I@(gs!nWZtvJJ=wi#!)Jq3oLFpo?l1s!i za>o@ZQp`z31Gl{k>g=vlrzH|uOi*yarGkP=Nl(cyaHV}=H;_GkY{8)TWf{3W%6eG! zt}e?M6rWQ-=`bhavQoE1)6oSt^AcQ)cdMCWl=qdh@?U?-7o?Jn3vdktS8=x*KV@by z)?+mI-k|JN3{5{SFE7B$x*RI{A_KGz8kCc-`69=5R&{+NTvnp+ZLJkRibl9w3(VRoLvtGuK zbc!ixX1ri**A8nV^@;?2j`5G5$ZN2-fA8KI#%|+C{`$lV*`*nglZ;=JJEvl0Cdm(^ z>I?NF2JPWKKxYlkbg3SkJ)9Fg0hB$F=z><9=m~JLC!FXBI&z;MXMb`Fq2cy%M~)O8 zNqj*3ZQS|ue&-XtgbzUs_zE8~86XjyTlny!5W?QNCk$d=V<$Go>I;W(S28iUT4tMA zbc&iXu^ILgZE!K=cX}fGGh4`7tRF|x_FOOdV}~!kDEOjHTySD7iO*<7yPx!O(=;=< ztK80D5`yn!pXOWgB)3E7!f~jXLx83pg_Y!YIbS1oOEm7=kMzJ;noEy!Y3?7aK0a6| zp-?OEi|8!%6xML>3uB|!lvRs@V_{>39b7&)Unu2(FBh7Y#OC3$CR|{}a50w^f<%Xp z$%rW~ZdzO!ftRbkiZ0%dNSG-U4Xl<~EsFLcVq|S82>&nR1?HO2O+qte3dWc&k)b{v z=5tAQHCjrRTFMPDF`*4pw4^=Gw^{4GCMzg22#FKHW9 zUK^(Y3HClgTgz^0e+)agqoRo@sJ!beRxbZjb)APzQ%hqI1n%$kplXzM*hsXV5*P;A|{ zsy{ZmAlWn|+SBbtHfbPbzR))8M_ANUP;cK=UQ;(s1FghKiVZI}` zhNHiJyv*TWe=rZPvYq+Y`C--}=P{0=rEu3)A^`S6D_)1tQ zY!>najD)-*R0y@iP_cv9Q;flMTXB;3rRbRP{VL*|@t0Ubx-8O)m!6X(Lhcqz-%GnB zGFBnv4jkl;ehakBSRhxeN~W4j7qaNAmGUq01^JfjSdu}c(ocC;8Ly-$3zYAa?Ft-L z&MFw_tURSolSy&|9?gv-xv6kzZZ?oHMJNAGohSpsZKn(#fwiNrhNik(VC@L=z$MJX z?bjXM(O2hs1lG#_Aw%pTF7Q7--i`;n`$O;EO?!9B!s~rHVmAMYGOvP^d991w)Kd40 z_@sBr>QNHdqZp4~b-9nM5m)+MyN3((>?D^?fg}c4W)iPl#oO$e;6BCJ=-Ge|7U0o5 zaP&o-8WJC$!>|+b=(uQo536lXYsqi;Tha@i7|x2a2L2IeeaXzUzP4Zvp1+9qbmN{d zfZb|$)xKaCv(5Rl_Ae}4VDW;))#Kc_CyeJ(IC8pk~yzFbzyF_GFphszpPj8>;L$;b%a;0cM!&u=4%5+q8~ zC2y@K_{mSp-daz{kV(_y(RxCd(oykfJ(qj|i9x+$cabdl> zNA=Feg|6D0ns+vCZocNqKGcKt&>xG6>>|L#M)W+jo4G_N9LI8iMqVNMKz+3S?}hvo zB;@~bKiN$7_@qaVBgSw05p>GVlj(wqQ%tsT%RXGXFDIzM3A#tyR5Ecx2Fch^R35{z zHSD-eTYGv?WW2p&gl%@E@h_xDk(=~*=`xO}rF(<1WOTZYjj$`IrjwOy&9=U=V56m5 zJMnf^m|tqtvx7}|*0mHEZ>QJ`?CH({wNcJ+Gmyb1v2L98zkaLSHf3IK)iJh+ zEob2g4o{Sv=dH?hzg6eC>urAjz3K0j<#@8Z#x>;ca1h`n9w)&dc#FqLFqqg+&7hT2UQkIIUa6gz_-RW85ICn?F6)ZvjSNTCQip8twWOz&95C3JR=C)*UOr4zb~R`>}q@ zc2Hp0ZM#`u2L=AyhJKJe!F2;+mfribIB#~r*mKI%tdgSFQ(EKffQ z-E0rXx7OZi!_Ri1ZP|W|vjXdj)B-b(k(mtUTV@+W7$10Zd_&lH7CvLsS(VLZ-8xEe z3n|??N}xrU_Z|#r5$3%I18JNKDh|g-Aq}WSDO4=QPkmZ#sZvM-3|GggvYMfOt8P;X;{)=<_fGAA&otjQ z6Kda-r?ZP#!uY^@kfk{m ze4TD^wSR-F-D1=s7 z+z3TLs6c2{1O!5>U_l^lS+od5R@u{*9i^cxvRInuy1pTIlDTJ|d*(UM^ZU)5!ylhB zbI#11`QxVfem>Xre!pJulek+n#bU9nL=1-361*f0!sm5TD3wh$J~$?MJwB@O!ARNb z@ll)_{+7KSAJzEa6UFQCQH>8C4b3-ttBwqKp$gxrUXL%d4fpr>Xr&JR9v^i#V4&{t zXQ{gZe*P?VH^9%IrS1j<^*kS$@TIxh)J?Cu0Z&=&EWz@+8}O60JCK0`k3Z{lH^ATH zqwWUydwev)fZ$+zA`AW=A9Xjt-{Yh12Kak?)ZGAokMG~Tih;k!N8JtZ_xR}Mg&^VJ z%?tcJKDv2>SG5LTa~C-H zo2$aJJi)E{@`O|XKU0C~THrAioVpfJU&~+D0_tn|>smm4E&oy&sITQ;3Ip}E{B(;e^9NvD94!B-i*P{cj7uWUZ0E%>U^5VK49dNz4 zjuv;K0iPI-7uVI|!lS0+#iiLKMFhd05v189I9^^95e>Q-$A1O(Ron5Of+s+A{HH)# zI!A!&_)ozTpgR6j@C2xi{}em{s^dQePk`$9Pr(zQI{s5|Ax?# zb^B7}KZTLfWJ!_Ir0*rie+qv~!4ML70#ql21dl3C2#ElNK*-5}-Q%Q+Ua81*ney6pmT00M+rI!bsZ{pgR6j_}g{`sE+>>K4Dw|s^dQe zuQ=!UPvJY3EQy{Z5!!OD0M+Tu!LOVvKz015Fpwupq9;j&KX_Mw>iAFLJ>fIK5uiH$ zQ@9`3ca8wn@t?w%;%dgxT)B+qrfF z$s_#5cZg!#d$)7#h788NcRSZ^@b2BtwHrdP_RziCxpsqh?{==;C_-`X-OjZeynDBE z?S`s?d+&Cx-QeB3oohGpEZuvzbM1y4jPsunZ-_3+{a^7cMHyU{yNhxU@GJ@C4*!B@ z`ITh@%d&uxGjR6t-rWqkYQei19Kqo09gVb%&fN@#>%qGj_~rDpj)#wo;N9$f+Q$Rc zl{@XNfCtjwzE)MiqYkTvML+2YF?MvZSTpG2`6{U zWtB?FSS4GRDC1UZy0B_!>qn2!x=z#vOQ0?X0>G)QRdJGB}Sls%2HsYwDk9@R1rY?rgHLJP-=$ zRzR?ho8yQyz<;Tye>eX+$AJg{?@~{9dXTUj`nly?>gi4owpG=B%yusIbf*W!PP4za zol8C4>49aMGA}UBrJnBepfNeje#W`f)14l8HfTNv|D~Sp^h?C2Nn$yU`|znUWy_Qq zgfM^&oO8GTmj?9iGOe2tf>5RBIYc0Q$aU$0sos*-LYEF?plsNXZAc7+{xMA`_!iqW zJg|EQm$m$k7$H0^Oc$o=qLcX`n)0^Z?B6U~ZH>zg*fzk=4nY6wTIv`^#c%76Q9PS? z27nFEo7-X&qbiTa2qHZ3_Y+SP3?}l;o}c#Y*%pfu%u4Y;w*B$PZLwIFsw90P!eWtX zd2+`H`A_kzH0nLs@uXI)JD!sN)8a>rLyAUt-9-H1=o{M7jeOS?W)GK3*{=!5fZ3bU zx|1j?fvJr9qSC`9IGA`v?xnOzn9mixt6-_JZX#x4vz^5qP4&-xIAKEMgu02CH9Vsb z`M1>!DRNBR1Vk@TMFEf=G-QcNbl1AdS^1_ahg_&NYTQb_yhJ{)#%SHY!rC*)l+wVo zW>*a+X#Lfe8f^m{gfGxPU;n59Xx88#HNX=_Yr{WkfFF&#yQ&jM(+!=?{-%G_0Kc0T zO#i3>-n1rK{!s(mulKwJS* zJj4Tk6JUjTnk{?X~59FseIONvZnd2BGw6W|eSY0ZTsKo$gx9U%?r;!OL>#(pyn>rHV3SEb-wpXtXfjKgCBtl?l zvTkBr*|@m+v)U*Jq`^wQRAyWSjHb35KmVf`>1F9;k9=gwzE>E1DCNc8nEZt8vx)=| zBQOs$Sbb7#BSQCqjg*;EszUDHw>}iy_T3@>T^t zQodCD>u1PQgX?GLuLal75X8v7sY4JWdqamHMs|h)RLt|QpCO2m{nmsaMz*B|L5%Fr z76dV}uh=&cBU|!f0?{3s@R;brs@6pOr;Hpt|JbZ813eg#Nnk!;oUz%j47g)6+5}&c z2C^kRSh=>t6=1^v|L93|wwe8>FENN5!5`*v&tfy+TXr*-Z*U*6U)HF@AC{3LaIHXtsfmR?)dzw)dyh|za}P4k`kx!eV%Ebus*8ZXQc^^%2KtO z{Eim)9A4~h(#3yr&ydGd$EpcVmL|VAtt|2b5(gx$RHk;OAXV0gc1_gdFA&Bc@sqbd z`Q(W3YZnXv)gK^_88e2wB=yCtH^ttn$zzwyM=FhaCjBlal&$PfJ zI{v2kGA;0}zCrhAT7W_={!9x{sKuXY0SdMFGc8%?%vUsoHtNzlroI!4f0)kXaO7k$m94! zmDavNLFK49Qcx@G{rRIwgCcKi0Q z?a#^gx7x?P#s3w#Q6BZIOxHC0E)M5Qe{6+?V8HBP{yJ=+7W2orYCSPz$WZA1Nc_q{ z1NfJPn}0=)7iPXho|@;|KL7l*n5IpehP5xx!7oB1E}I=cx;QF4~?;BDibWjuJ>cxM?8 z1+u%1cb4(sZR4F~Jl-JPZM?IL2X7niEaM?cdscHppR|mJ4D1<_-^PXNLUbsM=RtL0 zuP^jTna|5{Sb3gie1VrpU3ZK?7`Q|s(ym<#Ls?IYED9b{owj=5N2=2+1PG}<57{+U z1j^ZbdAY}o~lR79zBZPyr*-8QQQ>nEw*S$Lrl--#o|MZA+N}D-3r;`TzM|* zG?%_RuQyIisx+gDOB&R=BK^3Vu#$vwH(AFIW^Dy@>AFPCnb;Js&1 z1Y*8qW>ahc_mYQmt@qnv8!D%74E~O6xBfn#+BP+{ZwxkE&tSDayzv$Mj*MqdOh0xJ+s1x}-ze;2n{n`t-G=*tp(XXja?6;kr)J=FFj^SM ze8bsKcjvoz2ZX(Bjwp?)-7l&j3cvPuxL>X9xTfTCxRHn%cF~gHVuoF`B)FJi7cB`c zX4pkbf{Ph;(URa|hF!EIxR_xVEeS4W*hNc%iy3y&lHg*7UCJ={;|Wx2xa`CeHq61V zJXF9EcXXL4p46Ng$-8pC~!Cz1~aDv}>^a^mp|+8;;vfw;!6@PPZSj%4TIP z#wyJv-PWrbj~Vcs5yZvAcH<3w9u^}m8McAH!db_AniZeIFG4}RNs~5A>Wxkry#5r_ zqmELK29wN9$FQ2;;a06>=AY)3y*o2vxih^ZpdhMeB|@gvF^5>O*3)KIdsHaCSQUSj z3hH&?LoNN)og(&e`KO;sG%MQkPYiet`~O8%ZsWD4pdQ|?8Nvqiwg+CD(zGC|0$~H} z88&UutF#EO9){zIg;%;o-nOpUH|y9XcD-^W1gdQ$o9Zw0LKovC-ye2dv> zzHUOdb_1Afri}Fq6NBC6VfLbTuMTdC^@9t{3lGQgX!F7s$`R`nSJKpe;bFW?L*UHCy0kqE+U3~)r8n~ZP@PYUu<2j8P}2P$Dsgw689-bFPB{I0C$#yn_T5k ztDdxtL-_GL%;Zz~RXk}M3;An&c>xHkM8KQZg+$>)VZH#%1^m}8oD?n-FHdYB0zpY$ z6UT^C#W~{F;(8ItIRB?uDn2OHlbRzq3|^H+NbgItq@_}(v`soB!FlPn^ngs>_ZazQ zd6*1Nn`VuiE$@?0%YVt)6%|q?w^zE)*i(%3wAvvw9myqR~^+$=Q4B= z!ajsS7|#>Be!58$vk9>UtL%6NWt*X4d|_eh!YW4RZP>k^7T&_x^S*(fjuVW2x)veh zP`)?WcoTyg*@}M9(DWSrZ=?00?Ci+w(Ghs%Z*9K84mvuvjPbD1V0Us={B1l~bh$y! zl7d5*HeSFYC)_|bK*3Qg0m2M?G!~eTS!awV^5?gmKY!dlY(>{Ud+1K~bn{7TrTMir z;>f-n1JgaLFJg^uaRdUpl7<_a)z|n#N1mkB!_HQW1luqt+E>lV)oav9sxi-&&KE@{ znpx(aTkrk!-g~#M;4j1O+oRBQ8hRV=FS~#LZrflt*tCUEng7AF=At9R@OLG0A3?Z| zNbX0``6j|N+5IRw-$baUxF1C-UbVDtexuxfcuX-B^FP97K48)hqIjp6U$rPzff6NL zt*bUuJF5NEx70~0e5$$_ghb^-<*br@pSE71s?ZRvj(r9u;BDpB6&!+XKbf_rxZmDe z#rP9Ae3|-~s@}TtSKJiq%;+mo2aBrT!Z-LW6j{dQ@76{xU7r?pa18!m4=Foj$YRS< z8)}beNqS2yizeIKH{!V9)|D^+MuF*i`km}jwo4bp!j;U@mTH-+!^3LFUfPj?&5E$x z#Eg1I{UCev7D+#aK!$t$Eu8dV*)AC0&0A0(D{o0+9^PvI?-AU>_0Ghg{F zb}!z`%4Ozia6mhYV$oq$Zfk_J1Z(VI<3Tgo=<+kZNy`<57m-5rf?XCLM-}q-9Nmi_ zv4u>9{GB@^caF=%rh7SSAk)bL8i)I{`|yRm!uDtP;R&WS^Ah8FyuLxGB9q4)V_c8d zb1Zab`?KUaRM<53dv-euzq1!`Na%XJ`f~6lH<9~0lkvN?sOD{X}yg5&YRam%;D2H{uXgkT9_;zMG6v81KgbuivfvDkR)=%Cnc;u#42 zHsFMFsQ5X)F@6+*SPGX!FO&lPrC=y!>II2%)?1CH2ugTv{PD8Kk7s1277(0imb_F3 zR0PV0WKR|fG0MxzFy%hPD!wbPQI;xG2gsw|yP~Wzlc!B9SYPnDjUY;zq0i^>9*tM~ ziH90oqE`L1Li~_?lWAjokl21e1c_;dSifIJ!SS_oaP+rn{r(-4F2E1|sJ{xT!YEp^bqDI=m zeK>ir>3s(%77d?Ph#Q${>3`)>;c9GQUTVRJv`J}LfgiUozuV$1X~}8p)6)0yJX*Dk z&yB{|hHSVDhyFQ7bEY23iLkHzN@DW%YPP=o)bi!i3gc69^)sQD-Lyg+sZk^c64VN6 zanW>@*sGr!7qy!uS_2)f(y*%H)ru7-?<>uqp&0r>9YJUX{9S05K0hZ}oBQ1%Ek`}L ze$wI>501|nkycO;R?x|O!8nN2y<0m84GA6_vbjYp2ZY|dZ_TonTErXq-@Tl&?S1xX zvNJP4@0|8bFD9OOhndbSU|=P)i6QCo73My+I{PFG^z%KK9gD=Vx$H7Fi-n!+akhvB zE`ocUL%J9T12}r`%;wU$AGjUdVGb^GC0saPmv6>*N)mjo>Ka9SO=xt>vd=T>rf`MQ&vzk2{ASvZ1-_CgK1ft8wmn zefb2OTCAJ&gpIre{3gNAJYFdgkZ>z;&*aic88q*~PWYk?lgjVKU$Z2`c!$8DVafQT zxm#xBsa<7JnT)@H!{y(Vg6Ua0DMb+{F#bgwr>wN|>HJgY&SA;81jw6Hy>0dCVaa$k zBwu;w9HN+rOaoST<F09jT@@7-7Ij^9!emi8 zh4UA^qE^er+eE`<$$JO#0|(OFu>SgRwWRKs@oFO^E60H=AFZ#4?_Z16%CO`s{LLQ^ zt%hNEU;ayXfa}Cthh;{V;R4r*w+?>bI@$EVuhS!&9`v)`vL;!MPLFJQ;MeJqO%MD! zJ+kRRd8P)_h;ej!WYYt`PLFJQ(12~l(mZJlJC!Ay9;|17VUMzoPLFJQSub+0a`E-? z(po8f>Zz$y1 zI3*0~U_2^(Bq{tIOcs@R!?svPTFU6?`#XqD<@}u%~5sMmYcD}uH=VU2_Qm>Sr zzkYb8+(9}dcT{lnQTvQsb}HWYC&pJ#Dx-{jMxpO@`*HLp$gF@cj>TMAZL#vRoP)G> z-GA-pJKz2JzDkTWUSh&M7Tom^#=R`~2ZIgB)_48f;9Go!WZ$ z0uHWnURIn|+X1!5w_G*Mi}SsO7X+MsKR;jSrEV0!|I%qC&R4@<8;C!d^OEaSttC7y zpdEG*Qb6e$3sr<6jD*vSq!GdM_J;ND54@~YWm1Mv1ewJ7F zq*izZM8M_YZkwRyfu;ZnMDpCGK$X-Y`584veOZNJ>bvU4sslUPr=C`UP%O2yr?n89 zNP9;Eg6tDD-(~EB$50-tC+l-{@G+DPLMVgBP<9ymK#+ZxvER(>XhJ{pEpw9T0F83Z z116j`Z<-E1)1imMcq>Q`hw`?c9zOMkjf@7;3;@a`9|l?+*wk7llA2AsVY+Kpz|rDl zd#mjTfc|y4uatc-)Lwt})mhI);A<@^u|>5ORe#v}!w-4l8*JZ*n3}P%b}XSf5g}-o z4}GD3{yFUD&Eh~`niU@58ggEmHHrn?FxFXyQ^fJ?Og1&L9xei9w@~i%$!~7s>nZ2) zXXzAF=Mg%M_bft$L2tIDaEY_Is=PDEfegi+Wg0}f>{J|%*1JQV2bdGJZQ`m$$d;$RKR&m_fp~&hj)VB@=eMf zC11Is+^1GopH!iZ+FeEBm71*1RhOw*D(qB`t3@hkBw%QvbwS^PHcFeK&DQAVwL?3s z!9}e^3)k!F&Ge3XKm9EoCh4E*OZ2sRu6{s2tKY;wU&FDVJL=b&2BaE(^=l0i8kx_V zJ#p%hXnttUH^CB=u!9zI;f^3u)V zB_W(31b9gZ3POB$Ed=n#k4uhS`s+2^O94Ku6zZw3u&>@MEJpnzU#UD5)e)ZH6xENE zJ#yqas@7eh2zCa$J-mTO;WI2w05=rxWa78iaa-RQ%Xw5B#7SJBa7x9-0`aOyQmR`5W~*H*l>;ic zS2(>_IF-E>*Z=#%X;L|WWIP|>`4G=EJk#;az%vuiM|eKQ^9i0$@qC7779Iu9Y&Q!6j@>JugL=7FIKEdnmhTmg8Rvq2uW)=v@gwi=6^?^bp?ig6f2n1-{y({J z{MEzm=+F7j7`)NnXPnAqaIlqgTIFu39QyE1tK2P>gF^vz?VSJgfG!rGtmw4LUlIq2 zl9(idv%vHAcR&_SYL&bDJ8)a&ZmAqRwS{B0fc>(ows1=2;I_)$QaQM-a<^0t1QMlI zxmzj+w^i;Im%we6yTv7NTjg$X3AXA7^>eycTmrvOiq_fS2Z>Ut9D;$ZViVj}xjS|N ze*uNYF5oYqDE87jkd6scchyCkF7U6qXwwD$RTpi#z`yFEO&9oAU9{-}|Eh~NUEp7J z(WVRBRo7YmCSO^oEkF~YgAgkW5imF^qzbD9*dqKU6bjdb@?s6Kk@&m_J;m3>MDas$ zzPMc6DDD#Bq9LDya5|m00%Jt;t@{97T@(B5T8E8A} zU(P}u#ToVwQ{GiRRu(C+M#)xOgd-6g!H;kxf+P45jzn+-Kf;j+j!>k59-%+3x6r%j z1N2ckOwniS>AFMMzNnYz5N^~(#X?7;pYfJ4$@tWOCB|AK*EnFDHHb!E+k_@&2Q$_j zVvaXwnyKb06VO3p7Mj=0@>UJ2k@dUx$kpPW=1}}Wj*xe_>D&TtCAW!#JzPF_g}aZhjxCEee0Ls#J&fZ#P!EGT zK`n$X!T@2EfX15HLb^cRhQq=|p+taiv98!m>?rmV-x5hu2xKYD6%UAKMMq@_O{5M| ztTaR-sx-9~fZ)`H(lx2PTtjXoKQBX1`E@x_{!pGTFPAsUyJYa_uMYebJo>8xe+8ny z)>A#f$ST!ty;Y?Bs%?*0$Lt-2O1 z0Nwo`EV0&Fv;cJXf6&D4VABH7-T%QB`!|~wfbRYedNQvwv;cJXe{hny%+LbR-T#5R z0Ce|%fFpU17J#(>8^OKL!7Oemm&tA84sqwX+uQ>@)Zw4uWB8Dpl1Dcs4{P{rp44-H z@fC&8uBE-uONbX}*RnuZDQpsex&&8*`^4%Z6;8T~5Y!PJ7ojMiBN`=vrz1KnU6e{B z2$$>1&E$?U`G+UTpUOa9!Cd)(jD;$>vQk@tCQ1i|0OjMcyppP{Qecbnn?mm5@@fsW zk@~y}J=NFMMD;^;zPeo9sP0nXqTYixP02G@vto&yX`bBWxC+Z@{brC}sbAJZ5kE{+bu(Tw z(4H{Wm}7ixtVesoQR7boN-;ZC&unhKXufKWFyA+U>o6$k1?$eYcP<%&pK`WWmU9m*-zWh-tJ|`+wa)Z?FIHqdy@@&?0h?<$Yq{n+A!T2 z7|e`il9{;-W|f(p%y9;auqqnCKF+payRZY;Q7lYhXS3<-52znI%wA+mSP19bFsYLz z1usnMWJ$3F<%UU}EGc+lQYT9aUYOL$l7bf|b+V-3g-M+(DR^O0Crb)mnAFLVf)^%r zvZUaJNu4Yyv{$_S7p=d*zyG537x?#IwEhDB{)^UM;NO4I`V0K~FIs=0^vK(P(fSLT z7#$3E|3&LB*kb%<6dKoz@@5T_)?cOFj$p2xvIPv09J-nl%#X}3O$ZY9p0XfF*!ziu zbN_*5)*n)z}<%KYNBH z!rr4CH0F4YOvvLnBJ6#~!Di0j3b?CWIi3i6ZF%T{>#79)gMUQW;RGLyu)}B}7-9cU zv5kWf_J6}Reo6+?V#UdC%Whf|cFVyCI}B2S5q7ww1S9O=Ib4ab_qPgFG)IimS0lpS zCmI9^dyneSSPv2*ZW3YdU}gy4K;VnxR9iU+zNq@} z5PVUc;=$o`d6+J6I9(p53xY4I&qbg}r1zqFOoHHx>U#;C{kHp}dO-$P7U;aF_RA1_ zQN5vn!|8HgR96*nI9=|G>H`&mFRF*Me23FDP#d}o+d`2rISq5OLp9>={hOxDb2@a^ z`|E!09{jFf(EZ#!c+;3@__=#<14}M`?%qGSdBKr_cuo*-q#&LX1X|i81#!!M>umVh zK4Sa1d+-V~obhw_;2d*{@pJcJ0*ftC*5mF0f%p8}Js|L&pSuT7@U3}2cMpE#^LRgZ z??0Iu^mF&X1Az3FsMQWLq=k|zDI@M4JRǼbBDlpX#Dd@H*EkT8X)3;8XTu1biz z_bL9_*+5CIkQNflT+|57o~(SYY*z?ke)Yp+$83ki(63)uzhdPc&^#21rkDbFF@?Sy zWun0!il$672BN%BG-aaUJAO0ohN7u)4*pOyWun0!ipET|_%HW4=Set*|MrTB)r7gH&PiEAPCMV?!yjyU2suNt2=y z@HaI{-YOrI|Gy~H-TOrR*FO>OQn0v!4A_>7O0@6769AP6A$S7V6b36(ri`PCz`yQx z@@40TzhD5>pC*(oTQ({YBkO50d@tV%v-~%tr)T@<={;x9UOc;XJQ7o?2`xKN!?Sff z#-ivVkVV~y(cQ2Off>2K=}(A9ygKr!AF{TD?@!n%Y1q6iLU#e=Lsn)$uyzbHae>jleyQG^_8zvaIu zfVjU7d>}_{kJ>QG_t|A=ZCU1b^z5M(^NH-O@!-p(0#HOgi_=6EE1v51<;z z=?_ky?l1hzO%@d4R=rbypE@-!#_ixYj=^ThE$$T_hVwxJJKW-f1a|mH2ol(#rWho! z!wNA-V29RHkiZUkQjow7{pBEm9WKa00y|7Z>$IQ14wcj(fgKjAK>|B8)Pe+d*q{Xo z?9f#Y64>F09we~Ca3e@yhg(LFzz+04^uG_GrWGWx!wM@%V29RrkiZUkc96gh^g#5# z5A$8MXv6B5z}*ws49oou**-O9&WxNH*$m75XShCWC4SMP{Im$H*hjZ0jC#84(@$^U zJeeYRzFbF_3wd17qXGT-php8PU?8)Kz+$cb1tApepC|-98c<0LdNg3681!gBLn-Ld zfDKa6qXAvzphp9o#s;If{v{Z$_?xEZ6u6}XJsL>;3VJl4rWW*QzzQws(SX)^(4zr) zdeEZ*{f(eU11=arj|NOMgB}g2WCcAMu+R#6G@zj!^k@{VyN$Sx6%m+(J-*I1Z({0r zMZ`}(CH$1Yns(JP_)EN)E!ApwcRK490br_@K{8hOb7io%UX^jEbFhL5V%(uM8^pLn z9vj5CLw_!aafb_>i=A_*b1;#2v2zY}4k`&jj5{n8f*5ybC~Lz_PH_>Frj?sHU{5^Tczr0 ztn*QqyreOsp7!_17oRSD_en7c=f_6S1+82ayF&Dy)ezFSR)b67vv zYh29^J&dVMg1^eOi+9c`z;{x)eOHXrTaVAbkb4P@F+5Tu-(m80Q|}~ zG!-+=gy0RMsRh9sMveu+8%A#%h~wtnFbZsNk@4;*3Ox3eGm3)X4I_mGuh(;Lxv!;Y z|Fqm6>n!&NWnx>r$G&q|7q5S^{9dd;?&+})Kjl?V_Sidn_KDepw&2fkkA3gIpYVPs zQ(Rk=gMa1GM@t8YBV-@19}^87~_l?hD%3-0^=%@T*%Jl$hjcF z{J@-NlAX(ub3vH(kX7FzJC`Hpf)wj3Yn?@QE=SGge>j+)Ks3u{x>>R)DrD zj-AW7R6w-aM;)q?oy)mYwA!nlQZLO%a^{iDq73YDJ4J4pfJj*6K9YG3(FK#Ytjxg1 zoCSywiAu-jvklZ~#`=>3GsH@>0VtE-t6Q^|FJHX;NG3u&FRAj4siVwxD3L z4{-+N^dRC4=IKGi893fP4{-*Lx6ebIf#dD-5NB}E40Z>>@%DMzK5)E!UUv{2Z=YBF z2ZvklRsX^9_IcHRc#aKL|6zNmjpI$Zz!`ISQ!Y5e1*`usjt^G;d z!`k%3^aiV^B-vQp2kgy*jJ-sHJ1(4#CelhYOo4NF1DO2ruoc)Q#()ks=@5xjGFiEQ zHnxdzY!+4{A-%HNN_AxMQ&pIweyy%oe^HOBf2yVGgBsM+nrkm=YTL9! z+Ih`^JUpXAjQ+AtedLezMfw^&TZeu6X)GsKG-?@78|{r=2E-fh7>)>jld;FhH{gnK zpIO~}(rjaPHwT+zO-MH9n#+(mveP_n7MWl{g!Q=9!s=oTutp(gY_MjkI#!8SZ z&6So(S<+7FxKt#8TpBT%3hX%KR;aIB6%BD+$M3iI?++QZ&9bK1Rkl8zE-#Q*%9~`^ zBa^lIKBc(1k)}e{sL66mk=;QU7daAxkhb{VV zdZB(zFK^T^8X3Q2d8rJda)**)Q=n<1~0N;Mi5M)?E%@9P}LCp~CMfAyay8=^_ zakRYf5&2Hx1snYzLKR;0yQ(N-VJnYw{D zc5|j~;Emm!sT+7>xBtKvS$d2isz0Wd*^qzkL?~+re#tLo4Z$z@rK}>d;AlMfV%YAXx0{V*n}1{6;cxbg`Z- z7W^c30O0IuU*rkBHuQwvz;} zNW&#>JbO@rbJ8uz8_y1vVS@aT?2Tuy%TPh7sXV1zP+KZ-$_vUg1-?M7=ugUS#Z-!w zvT8Lo{|U9V`jSdo8~iFS{x&QVgj=d(BR8#j^->rVO{6|z+Vwt2iZ=%vLYu+8JO zLB4iHyHEFcZQuage7rUY0oy!Y8#ur=kJkouO#-%gyte$cCIQ=s*M^zr@Q>yYD%gC& zYK>qm2zrB$SrGIFk3@@>9aM}#&>Q>-13_=_qbxLLgNiW-dV||?5cCHB%0bW@JdlT= zH~0@8g5Kcw1o$lA4ZdH5pf~tSG28P7|J@6t!>7q7hktvKYpWHWJbCh#NTmblBRQCj zvQjlkmnP4;ft%5cc(OEAK$xRz2w5nVe)kp$<8b4;skJQ0fLzDO@h8fjIFTSb`=4mJ zk6e0Z3WnW?`c<+beq|iF7BtP&0Qp_F#=r6k`wH>z?#M4GE8=h9j5i~mLd+E~=hy@J zy7QE8l?_VCugczJ9Ok3A&dwmC6dXEKdu)dHyCaJnn(X3^{(%vKkz>{AINf7Th$0Wi=?VgJm`NlnIvA zpf(#UtHCNZSXP7QxnNlhc5%V78ob5_%WC<5@>Eu<)3s?du32t|$*j;LCL~@vRij1^ zVS+IFEKf`TuH%duVKbV>)Jizp<4RJ~ z=-biLh0CEafPu4KD@Xa z?uk23v>rgz#P{AaQD?VjPt%xLv%+Rw7s=4*1Y$;?mB~$sVENVqY!o(-fD9&}uBB-V z>I@nSrQ*%I$?MYAj!EyGcNhv@(+aD<@R&R{TKeMU1_kSTBha#Szn^iNoEDo{+;j5o z-6wXZ4Ms-aH}QS@vVCdYRBl$&=qpNX+(t~s>*=)kDG6tjimpr?GGs{87=(gDvHXx+ zUv4RnmSpKUrLz+9=zJzwN{+n${bdMB%^#+0Qw}N3)miEp7h_paW>J>KL4^FR6fO@3m1s@v7-B==FutmR;^D{lZ)KLv(eI*jT-}QdtM5CEi5rAjXPo^+raktRH8kHH}7g zHC^!F8_i*P?={}j?&ypG8(yS+$cv`a9c^Ji7h|w~TH80779lIm+7>ji95kj&#)K`_ zZ&smo&2q_@&=dV8iS~!~e0#aQ(cWdlN&B)*jKKy>D~5zl;5Ryv&o@Z~f4{%V2dxneQUgm~z?{Xh=i@5Aevz4%tJD~l=oi_#zDju}C zUV85>ag@0ZsWg!npAlODRdnkFfzRV8t(tG@&U*c^UATQL2`gNaLrdvx+sti%ro?iE zAx{H|(0=@};77+7`u6iEmn+>|k3!wJbSzyQo8j2yiZ<87tz@MlBpTxXnBa>jxwAtH zE&M66X@gDFa9EeP)7T~qJul)RxD~pbn6pkxxpOrJnLsDv;MuE~<5Bw1^Hn_)*!9 zKB}gfD*dDHuRNh;ZHU<%H6jT&_j%1$y}fExPP5HX_$L{uzzyYuO!rVt#=i-9q1=jB z7pm%POluv)|D6gLdS9#>Y6iFU@tEFwHb)_FzGm*eq>yO>SHYDOU7DvNb~c6o>UpPY z+e*vSiaLIaKN^iQDgRY-CDA{Vg}K5qAxjvhL#U|y9c_Q9Zazl>q8|LFomID)Q&i%8 zLR~$`n})~#u?TSL=HT_sow_-AeRHR74qo5fshfk>H+Smh;PuU&x;c1#bEj?&)Hi?L z$mNKYx&x<;2{L=8s{wv9m`0K&m#j%3-xtU8|zOB`Ur& zQpS%SU`V1${0!WUI}Jzs;RRb4Ea)21KDw0c@WkA?C*~G6Kz4oCh{VK%#2(z$x>I`N z<*l!tE%3$cE3M9QSbS}#U{1IzDmIcn@-Z@(SdbLrBhT_awU zroL`a$-Q##WobJyKF;XawqwUi{l5SH`>qj_lAvqVjTs|w?~H5b&Sa>B%IyZ+C0Ue_ zK9$c3ut^*tzArjLmanDpO6jUMsZW7<5lD(z64jvH2qjzEC!Lo58ZDEw79SlSWgZXD zN!*O#&mOs?Tv;K_2z{ehi}Z>bJ5p^Z8FIr}_{Y&TVgiEMtLEZmrJ-_DRHE6DQ~lDw z;nPVP*fnB$&IsjUB~y8j1Ec^v;e3d;DeV{LW>7|9ck=Wc#Q!pYPJ$yG-JBR6Up};^ zxvGYAeW@QSut=c_uG0hWs3t1V%c%U>bbNHpk)F{hhXDQ{0_70EA4H%W0{DXnltTc2 z5P@tDc4*z%v0JqB@)f%_gTExx(rXWx98(FUdAr#+ z8BE1Fm~TgJ+IG>&lyi7zJi&av3NHh2D`@|ESl6!K^ z--}P_R{t;dG6f_4QU=zYSU+7x~^ zKP+Veett(c!`sG+W;gKCo6-#B5O4!OhCPz2BipzFhR?1$ZNVqQIe1){A9)tNQC@SX=>r44TS+OHS6RXvVAfkNw~k)Ri88 zPCVBOZ?gxlq^5?Yo)I6CZV4@=)*;hI{tbDZFi^@EF(3hNS2l!-1Q{9O2d`j}AOrKf zyX_mV%XFW|$;31%{NQE$z+abCsh#{K1FIRm;vQzXe1+*H@0@tBc+Z|V3{y0Wk54g- zFvG#?eaS}iG_k;^{zCaHW%DFL2b@(F@UW8K#P8vMlS`%J+WgTG3M^3Th?`Uo*#b{$ z#BA}9Es&)Vv!&=C$QE#zEgrH3=t^Cpd&m}Wm@OW%1srCJhin0d+2SEvz+tw;s)y}v z>O0aDt7!QjI4+1Q#C&J%Z!F_H-tYP|S5fVEcfhgEdc;0r{rrA-F^sTZeX2B}P19NS zZ+50#@$=eo1>;ljbA%1z2X@4@YF0eJ?!e$QVzlxmlU>O!yP(uw&eW^a@A~A)ttXFW z%!=rp9nQUZdQX#b*bF$qJQivO#1-NNb}}QdDc0q;*^g|Q?ca!??&t6hkQT8g4%5fA z)7bqFrZr1xk}{qFQeezwR&rU) z7;ZMRk%RmACCZchZFUqln4irRartxk2sHD4EN*LwciXXXh5f>I#5GF6@7HD#W{7vo z=v}H;jVoBvbW1LO2Jod9S2(Hcq)7?F-^w(8tFRqwDEY(r52R@RoX~Cn4pCbj9M&x= zH3>g&?ZgS<&HmO0uQf@b>|Ir~5r%A3g=Gs1ldy)8Cq7|gx#C)WKl>SJl6_d*Hwb0V zB}3-9PM*ZO+> z7yYRIr(UYVgGN20x$&a$sxiWN-2pMVHHLX?yt#;O%`FL5p zl>3=gTeU9b;Dfio{Mp)l6p>0dtyJ?vtEo-Yp&@qoh+;)it}|D+^}~yB(VAlHC|t@# zXA@My;!31x+tsZ5nbFou=W8FbU$5};%P(JGS#ch7{97h27B8+V%6IH|qT`u}AAkJu zQf^jOLe`2h(~B?VsHz%fV_W)y&DyQl7wlWiqxMu5=CJ*%uVmk68i+$e1dME|MlWN# zb9H*GNod&6YzQbF?a^TB)X1q(F=*KAAq?b3bFE}9g%cjfzk^G;YZ6-Z4E*4zM!7fD}pH)G)U@#r<{!u@% zR@+*&F6E-GaN(730Ul&_@N3O|)`8zs?M*^?>+}#|u)vSocPR(QhCs#KR$^y6Ll`L* zSc(Yq>@URK!h{3OgpNWP=?4aOFo&6oRW1rO1f*iMY#@Rr#q)3Z;70Jg9E2M|$iOR? z!C&hJ3c-!wH6;i)fA$ zL-j9ypx>anr|Q<7r@t*uBqLPq&HA}4R0t)Q_Z$6(ox>YjRpXPl@ao&D@t#@H6EpCJ zyj$mtMa8<=9fb)=#!tV{wY;Di-h#g|&KZmH3@aP&cM~%Yq6VQ#`(?AI?~O=8hB^TuIx(I(mQ4+pj$IMCH>X|2fE3-C$5=X%f9ty?#>zqr=&QnP&JOW6{dS`0F^4g5R|lcB|fW?AWnKII8$(J01UNtn%=bj4@-v#(c*9 zSUZ(D%x+;`v&LBYQ>}i?Tr<33w;cTKw@4G%up2s4@(=DH&eo(2dkXNPQ93cRiz7OO zTiDO)%5`Qs8Lt?f%+7pvieYirg;S>^dXI=&yEbgCGq?NQjOIoBcMPm>hJOKXvjqD2 zSa{yP`+R+ePv@peZ5pD>xs_PNUK2c|%l{2OAh>=&7wG~El%Uc8o>YTMgX}ETQ5xJQ zp2RLh>l%}V$G*l#QaP@(R@x)|nP)=!J_B%6(L;Ot>t4Nbdfm~#(2krD%SnW zTcpj;DYJKqvFlWL`yA2?YVR3MwTH|_N$tmE;72&h?0jH(+vUs4rQpP%@=bp#HDrnRYFy><1?M%lyoNqf$?YGCDz zHJTc<0{As6*TPG1d(OF5q*|-27RUnI(;~8G&z_SDPi`JG$Q~5(b(}mIc5*m7!T!kp z(q3)rb~Of6wly;Yzuzy|1;!gpIrH6PR!u{;a2oYqx%3-2_gq++swOikRH)FnSt|25 zTYg1$+wAOe=~!T>&x$OLQ|>OzRvyw1v-R}Thnea8nc^!utI`FcX8QrmC}xMgi=|uB zN)E(;F=wIWlr&N;1x998=Kc zr#7V|tqF@@&*0p|{DtEDdG+uqRM^!($b|TmNuM^ zFXNQtxVYAF^VFwi<8S!t`RQEkMOyka{JCAcl5keDVppS_Jtg@{*iQa*t8w#FjRiCC z!;_LcKBded?ev{`DM`s`#6sJmTwba#(@NAep=t>kU@t78RBtN(3)8B-(PitEVx%`L zj(BnR1iS&HB;!z~(@qq<9;YD-(0pa|7L-|@P{Kc%i&N4ZZNGK~%LuSp``x%;yt2Hf zS=ZRfd~Hl6G8W~A2cQ}x_ttJ6_hk4zE2m%mtpZ;5hi<%WSF~zbPg~I5dVs0JJj3j? zoD~N+0+qzul%?{}0&B^P)_8?L>leWtZ#`!a7b6DtGJF4I{T+4d;| z8|?*r>>a{f9yMv~28*~gTsF6lJI(#YRpe{&@HF3^@5RUS@9@+41^h}L=#`PrU*Yc) zstZpFZ3O6!Klx(?cR;gKfa5}u0AhsrxY$DMA`TE?lsHA4EvAbvJPw>wa`FBr(+cyO#HXH$d@3aue@7z|tLL;R zmZ@uiBj3hMzOzD0D_<`OKV^=v90yo7kdkHj^5qubk6KDD*3=lfV0KboQHCq`E2WW% zSa$*Z;I=w4{&q%W0xDG3O_`IlCo%y)sf{C!CM;ZNlA*9$WMXV=L2N_zF*U9H*%W-f zGBh9T9pQL3i=O@*fBYg7J9g}7kyZRiB2F*ICS7SUu7UpeQ#dw?OoZg(^pv9ssVVU( z{i?+_Y$9iOkYnZM8dBjt*_XmFHWP9M<>nUTE@s+lRrd@_!RNU}Lc_>JoC)vANXNn2 zXWIVd3l@Ye$VlC{qI%e@l-S1m(gsvLhc>$24U*IF?OfVv4lNAur{ZR{GHsGxOraM% z3CuGTQB6=uEBA&D=h0t=hRlJR@zM{i@#{A8xN$K*#=PIYn&&aKGyoFUm#<~8yOf)st zzpH8t`*dMu<*Mzi4w_RUfcq539CXc`qRl)tq5vWjw(LD>y>HGk&nvf;2UM7D?XpAc z$TLJ6Y{ER~t}9R1w7<%#GZFTg+20Me$J%(UVQaBZv(TRH#m2Mmu+!NE>`HbM3wv0) zB;UtX=bq%+aNRi=%#G!exw+gjE{ogA9p|8k1AO8=&bQ#Z@B{c!JkW?Do&SN~!5`)? z@+CZk3v~s$_x2Os5+(_s3a~_2E943XgtNj;p|V(81ZRjpL>w>96zBI(Oq+p^w0Zq* z7ca@UQvCGWPd^=*SZ5rLk1rV|=+GWa^O2` z-*foYN=we`i-Q@OcmEh2A6}4{me;p-deXiWyh21v_e+t|ac?$8ykJZf zV%b(!vXv&celPp`@Ab>nnVh+|RGR(44&`|5&-WDI^t$Gp&YdGWH;%`-Oz*<#IZfhj zZY-#!zW&84=t1iAL8nfG)EVl$)D}ri;F8)}?8#a|iakfl;`m*X? z`49DuYO2H60A9MjBnak+&?EGkR#INC`#aXhF~y=*Bb8evz2y&!%PwBryD%{>!mNud z+m1T))14u5q3!@OI}kE=%|}zT?qAl?8r3i3x)6(XP_uUyG>I!;u*AS0>i(H2CDX&A zx8vO!C68f8@{Gp}m&yE%1ff3$9tq7B4fO`F3Uh!A5r#>qua^07ZwN2=_77?*bGZej<1P#i9^D5j=pR!%qYc zpy==ufo$A<88?uP+b`n=vT^%m+*8TM?En;GqPL{|^1&~^jLwV+{WQ$(e3U9)Y00-P@OkWBF-srHvrwM1MF zPYb21;M9=Jf{5OQNri|;jumRi@S^;i5<6~v?=|8~IaOXIhi{ySd+<)Vb%ql^H`{q* zz9u)DHVoHJVR=pEk;+8rZH00=lNC^u3(DWhZkbnlE4GrOWbaods-LLeY^hh=DQDBB z)|=+3(!1oxE?lC+Dm7Q7`GH=jPuo(3FJ zbrL_&{Fx*vt zY%VgZ>)GZN?KD={4CngM-s)w=Tklx-SzKVPv^H6LtbFT=b)OB@?I-Ovc6XaTg~|3@ z8;V?evNzevTy3ri*MW=WhH#h1b2GVAZWZTR1Xpvva}HnuSUwoI3&;-%umHT^1@5*Q zX#&vN*bCfc5L(?IxO+~4mkc*>muDU`M@t|}PT=kj(E%&~Bl`n)JtPpNy%N#5=*vNY zyG1RR59>|0Dy7e-q1Y4U+?thb)~vDC76VtJlA!P!PFxCI1sB2tD|Cm#<3f1gjCwysfN-> zf#;Q;%IiuYe~q87ELS!vuuD0qTvp1c533DAEmi0sjZvqnZcDX2k26nNRC+B{aB8a5 zQcYGWDz`Nt7rCTrVTB_jGRK1oeI5kzTr3y|> z)oZCzOns&$)0G*>jAmpeg@Lb_bD*rK z6jyqkq=7Jc^yuvCocjq7n=e@sxn$@Zob?aleInFK{0-iLtpvUWBl#2jREzh03tpT1 z_uRQd=ir?i3bqy$v=&E-y%UF}yzxfP8)ULvExspyHXu4WA$px?y*ecdAC{Lyctmmw z^a)Z36!@*=Qh5@%zoq&z_=Tvn1%#jFBfKHpkzFbeyrS&>U+lemoDcQ;|9`CwQB1Z7 z#k6uhjnj(6pb*7Gkz*5uQVi>`DU6jvLK8(fPAi8bChL&%>=NZTty3wCU8g9PXEXEtd_M2@_x=0be!tKA`~CLE^=Ijpc|D)c>$)C~`$G&1QT&K5RcsmH=TRkvTiLmaw9BvGu(YH z-UwISe~TLd_>Hhx`a#N({*a)6TvDzoKOwi1UzU^Qu`))(e<81zcgx4*i*i2Y0R<{5 z4U{%YcV&PwTA8LSP+*Pny+XhCT;)EsoLWzXmTKqNTKNO@Gc{fPR)s_Auj)pagjGD|5Rt^zq;F$*;`q%0LP5;Q)A`1o&_OJWv9BH~=0f0X`f650n5O4uA(r zfDZ@210}$R1K@$jV(?T9;ISAy6$5xI22aHR9*eJR#;?3SFFHeG5CrV zw#QV9!HN}lECye(0*}SuE7n*;K(QEn#R@zYgQsEukHz4r7{FsOcq#_0@mVYePsIQp zi@{SdfX8C+R1Dy;7(5jNcq|4_#Q+|Q!Ba6XVwlBZ@Kg*~giFw!@)7w$UMdFgSPY(u z0X!Cir(yt)#o(zJz+*9ZDhBXa44#SsJQjm5j)2Ev@Kg+7o1933apzfw zr(!@jY(+CQZazX zV(?T9Smd!-3@$VV9*e<+#<1Q0$v@`@LgU+=gxBtgS*_4(#jIAV#hBHqcZ^~Lwh*Nl zfg(mJMi8(O85$8ZDM~Q{$_WosjKGki6eHZZMJYyLDN%|M$ZC{g1dbY|7-1VWNPAaf zk5JxnnI{tBbHEIq=&G@=wEkjyB>2yBxmMt_wYKI;{jH;fAP+qi&?GSwVBnb&TbF>@9EaB(4tI!7Pf zRf&l>&x+eO)V19#_k{bWThJ@zK@_FB#DgeGwV@ADlCM#;i!#&JEp-cr;ORk>|(+jI9M^vG;^i7&7`Oe zxMfD8Heiw!joN^R>>z5RnmN_c-C&}AeLsB4}0oA{q{mI3A7 zQaF$UHO@TZaDq5foGk-sGI9xb$^QA~1#ynNO{MIHAJrln`YDGh6O^IaUw%rmOgS3!&hOVw^(lxe zyc!w@EFYOcBM+3ITn)Qp{zhZ64J;?N1X5TAOr7Z)_>n4jc;iv~nkX#ywU;=MPH@d#q~D;2x`q){j<} z2`9`VwrJP3pR_yLeeF{gT(gGTmYpqMkxwBP<*W?^Mx0>RFeex@4TAB)QfHInH~|+C z7#K0&B93NYM8-v|`|E_12@{}oHqKXSd!UA(3cI|c9(Z1yf4^VB=b;`Kb$_b=xxYGh z=+L2X1|2o4{rwklUG4+!WdH>Lxmmg7bU~xb?S@XuXUw2;qipM(3i)H%2=b6vHbRy! zgU*aVl`0hWnGxt6NWleC>l}plHWpxlFjH76Y!VzHTeu?R7cV|2RuLPCElS}26AGeM zq=oq1AH&581#70=9wxpTPj1gQ-iUjn#{6F5Zn5mL$Gwm5KUbz8uC!X`w9IDytK%#! ztW#p^Y;;78?pU#1cI)hUX`Lz*&TO4M`qt>t9c!YR04iUpT)A=8S&3--fHSDPEhMCT z#+_1)tDd_=qS9saTW2GnaQc_6v!Qfirz$gQ#3tJ{a>NCV^q9%2WXTpyU`*}#xFl~Q zb{9WD$#J@z`<%?}JA>+@=z7`wn#z06bWng&A9pLU=&{D60fF_6TdHh$t=XHY~kC#zBjWe&|^9yURN~J)^@f!1o z~JJZn~N{#kj}EDuoS);fn=3WqVdq^B|1D5CZ?Nv#ZtHLsdOOlp(az7!a)ZIOAG zMI5*iI#kw))AzXjto@QrrcwCV4!K6rGz#UNz%@!6WLV|U3get}+bQajX%xb)QBqU@ zbBz}E9`?w}w9~)v)CpVy<)1Ne;>5L={CHu{eB7cQWS-`wOPAtAGB3x0%s5?gP;Ca; z8?v*Tox{20!7VL(X8nQh{qMgAI;Q&hdDfqf@f|z%x9;(I(l_+>1Gy2MZhQNeMd5cL zLBOLe`&eAj587WHbTb=A&H|uJ{gU*eu)_MzfjzjGoaXQ1sxI z3&-M6W4I?D>YQ&EpH^-KVG^^l%4BW(vPX{|2e+(AZ8J4@ZyZ@aQ6Ext+Za@qPE@by zWyEg;*dhEP^cO0r>*QT>Zz)B}$o5sCg7lblP~7my^5sXDAKZeQ(%R`umiS9zu+8e# zSHic-4pT5Qmt+q#7Ip*CMzrR`kU zruWV4GibtEF=i17EMVK1QOyo!<}21mXTU<3C70Lf*Kp1pYtWt#3hTcMWKv@RsP&Az z8PWoEO^@;BT6Mb#3_QpOd7UhX4)RW0z`%nv$lK{0afaEzz=M2{SHJ-V9^`|(8O~@1 z9_-}(uyx*`x0&4r%|4m)KJd&_fKsfavX390wPDt*p6RGpX?W<9MxT7rGaY3wnP#IO zVA`M=iMbxxRap}W;cP{cCtUp58R3ohKJ&4g>36QsH8VDpD`$VtcEMQ?cI!5 z+@bD-BjrRg=$(QTJPmuMYnnFBZ}9xZ0aM>D)~Z#j#^~&9av9eHC_Ko@DWSkv?aMsI zv{JEfJ4;$CsL zoFfD6s2`AjmVTEIm-*N^1-_M;dg(r;lS;|1@Tv5YT3w7yGaAmvQ+Dlg^j4Pci5r5R z>8XQLQ%h;e%c#Ab-U-?aA}}UpwpNs$)9TCcv^>nXPp9C&87d7^VUAC#yYX&@#*!id zeNb%^jHeVH*9lCc7Q}S|<#qDG1kELYqzawv*K8iw36$5#2NN`x0Lts+g9(~THQ_p`mBO8Tmzk4*htSSsCxXAlhfSu=Q67rJ&JH|!+fpL)o zfAVsbrs9B8c$ya%;l(%moLw)lU&@yD%P*0qX_@FhfG)M7=cnN%-xk%KjU`cn+BFOK zW2LJ{7fH11?kvFoTvkt$>iKN``Pvy6CO?-q!k#1H7bU_uxx83ZS?k9XLRD(Y7r&6_ zE4$?{n~`ejJCuMOmVbHbP&1OuzOGGB?#PwYB|^NqPJ~_JCif$9RH#X6-I4{+Larw4 zIj2_F5}aq%CUPweddVB5y*1`(KS<=$%%{TxdPTi~-bU}P570;J({xy%uhGBPf7XB3 zbM^a-at72hS{j`VvRZs#e1?`bAcr#3LX|aZnaxdj!R%wcWisI)(H%ydG@H1m=x!fA z<{Dlz>pI}=1QXDnGSgnVHo5)qRDH0npE6(k0`L0aV^UC=&}7x~ z1wya#RmLp;EC2Xq^J9CSz1BXof<$tIat_%|m9AP$<mT+2{BOG5Z){|<= zou%;=uuptANq(aNIyL@O9=jJ0qOavIrO9%0;RT_Oa8jNn!&mZVc~vF!yeR2=k}*OW z(w%2L$~`Tr-o}ITkKdra`iDpAv03U@>Spx^6>`)+)B;*bt*Z8f)=qmFO>f#*ZHD%R zwqDz<9n*f5;cX-OMZq*Z`bCW{XRt4-pYg4IvqJ2^KuO=A@s~6A?p=ZMoGRAfv6-23 zGxI0o={(3d@g5~6*RN|wac5$k1Lvg5L#GDZ8_&` z^b%b32RC=Ww#zvO?7i|y=c)t8Q9ejYlg~{?x zc*T^ZQWa^X)K-FLPHva(m78qJm72;;?4KM&OViGL)fr4azqMZe9sdZK(Vsc|8QxbI z{h7m`fzzJ}{+z3gP=V8*Is6$o{h7m`k2Cu7(^l6dX#BV^wF3&Ur&mSEu0t}})rSA- zfdg|7OznUY>N}eD)~H6KMosO2WT?3nd+9|Nyn`?48YZsKvC{_LYBNRcJ4VI|XRA|4 zUuvv2ocE3#@sGsVL-p#3^$?3tV0H3dqq9hMo8qQ*H`#4!&wD>{YI{7KI_h;z7_Lv! zSD2RG-c{{E_Uy`JLSJWAvu0LZZgyW<5FgVmycGZNykv8gHD|`$eo1KfTZg2h4l;`y zIcwc-53FE6W~UkZccbp7qn(?wie_}^hPge}O8J@wB+Z-OX+E_B^Q6QrTbMo!W0Q$8 zz1MDF!IxG8XTY*!7On3;bSgT>S2=B*5mtTkq=WC2+^HQ%o`{Chf#mqPoHeyQ-qsb& zfu7Ua>}I}RAH72D-Q3TA!hr^m9jny7uI{f+j{B|q{*pyjc@K74)jhHp+;k^@UIO97 z@VNK1Thy(L?a)*EOZy`@mbxh_0~a`7`rkW{?svDz!L$DGKJQt-rEq+pKd(ZsxOT$W zg7}(&A~o9`o#%fqZ1EQeb^JG71m@lr(uHq@L&ENB9Z&}gJLkTS4fam6yvf#z&~!iQ z$bM@s4e^)~7MK+Fg2a`u_#PrDY@mb%CWR%oI8(v`lfni{SYT4vKnZ*MJvCyiRC;Y6bPiwqj3LuRo?Yd;8dQazy68l0Sc$=4G1UQydE7+qsKw z>NgU`I2nUeuq7+g90jeLMy22hSEf0tzOz-hqUP5g)QT95w8JI|O>w<6Ggj>URjmx@2{$JU_KgozyzZbj!}t5xX<&X0bRK zI|DpZkJ{3=1yS^UY1DYTmNN`ZmViD^tAn}9`FY#h)@|o~2R?K1x!*chi>J5$a?^bK z2^Y3+TI3Q!hZbAAodgeR*`>V~>?Yo?CRsHT_CT*ZYJSDkohwGU_Z5V_*|UnQ@v3{B z{O3H{o5e)0Tl}Ve2XylET9@NPWubZh(n5EkxmL>`;G)}Xn)|zR%=sbKqEVZI-2(%O zaE=IYkO=3900W6UpiGmPp#hkqAuu!mb2J2ohTAXc&!*4}K0e-!rx|?lcAGcP-Mpk6 zUTj(FgHO$EGz@!%<>*=+O=8g&^Fph1;RXi zI#GeXdD02A)Q_wEh97F?lVJe|65wN-6`S%;K)*?vSxFmybxGoqTT7PI=tocZvW?1? zT~ZFslr;v7YF2bfB3f&BQgy~^f*(jiKIGXLnzUebAZF%Va?XAgKjQbCtC=un#gfD(%C9Hh?p^Utb9b!+)Sz>USvzmH z3&+s5b73YqQ1-T^wJYpZHoAFYZ2SF9U458r(|b0UsY6L@Kf*J0_(E7O1T*z{_=J;a z1jx7QYee{7{8{{6NcGlJf{Yv!L#Yx^;Uf z-6kg$!&}OSypR>2{2?gRYx;1N)AjG*{g#w)I`L4m+!D2M-b53?qDcw(Qq5BSi;x+V z+VwS-Ns7`%8T{;#Bbi5v^(vg5tgKZEXWw(r+g<+@PdlWL%sa zKY4PE4plE*ZI)ClCvjf0>+4%@NlYphv+m$;0eNE<%(7?A0t^dDN_ef&Yp-Q*$D=hd zc~<)iNyX5)l9-IfmE+6w2UUtvE0lxwpd;JLA#-HWqGCDya3n`cP6VZ-R?dE@s`0IM zNNcKWRvMtJ8Bq}EwDBR&(bAw;PD0NTgYal>SUP?9HPoT+nUC!#(7RwqhZ2KwvTtg? z8$c7$WE@h`^C$P{cnv<)HtP)x8kQz#<+b`fGe#M;-e@o$663haka*Cg$thS znyOQ)jqcm_9sE4^5M0A&(Vt`RmJhxOrWySnqk(mfQ-vIW@VfDyne>74m#6g87Z@eS??{Tf$D|& zcW`!@lz>hmxRHK!#pM+jRumqWesnK$GQ4JU!P?Kx6E={OK6z6I^;Pwy#w0+2eEzde zOxm)nfVJSA(=PUy6}<)?*%1bKqrGV!Eb!KN-+MoM*oAxd`Q?15=eP7b`~Cb8{s;bN zepL~k5D)pk`Zs;%b!#pFwJ~oA?+bH;<@ny+CuE!yuI3qT#7Q_SgRJpmOmS^4^RMx(|_WmuI%zV-?F0J&>X}CG)Azu@rkQCib!c1wY zMEuN=$}iF>$(MYZjsnuZMwgPGl#B2CGHdgtd6{#IS2;d+C)CFW)B zOT=eJ3;82-dt%EOiw7)$^ZaI=k{(VNlz9m^9$lt&o!UI}Lf5Hyo$qOak6(vKAI0me zPAXeAyX@*M1+w?bU)9Cyw!!Mh=dIY+9@kl2rtNEA5T|Herd4c~c`0E~*Quk|WEO7A z973HRE1FgPO7-ezTfRRCyB0{nF0_9;+~;ibGoDv_tB#cY!M?17)QT1FR4mh#SzB)G zAJ=tfTN+1~yH&2-SseePza;+f;c=?pok?h((tvzM^IDU+sHVD6>!6K(RU4*#p{#FR zSl{@}-ri*F8JTdlb%Cs$W^Lr|^1v8KuJPMLaeI=rr`79Q)p)|7nO5@1+?y2l1ZV;Rasl<$TbYRlgHA$!W2MR7 zToYc+XI(c&lMR(TTC^f4YMnx6$)}$#+cI*=g%#`L*RRi?ynaP)&kokB*3TyVZjSFi zM*mn}q<<<8uz$CJCSEMqhAFIIpLNnIXCjIXryc||!}gfK5WhNH1`DKv<;Dn-!J_l) zq|0TnYy78GAZJ9_7y;yr2pc0tlQV*h5eZ3kGTUZvJh5@(I{(ZcFRehMhXLqH8ZO>1 zEZMSM#`P(7w8e!dg`%zV;Z1(0SJkw~yPUTFb4pYLk=*Bn<=4byF?X_vgMAubj9!Ra z(xavOHOuYUy#28yrHVo==_RSVFhF=!DxLU2+iaRj;^K8r#UqW5 z9BEMwZ7_SJThg4kIvuic^0w}!s*T6Sj~&}KXH*qZ);5>M$_-{TUf(_;5%nk2<*o8) zT*S)l#aG1XT@zZIOWd(_$Bq^9GfKynms5A{jN4g8)|II^iXVi}4%~?fD7O~Wh4Oin1lAD+?+7_aH{nYA5Y3M-w)p5g`Rr@&+#LHa4|cTc(3T%LY9v$T$_ z9bik@!plwhokSkk&c>ipg#;E)2bfRy`+V!a)aBl-9B=0>5b0bkIu%!|2%mZO+2R7z z=EGDWtj)jW;rqR2&7L{=N>#7!R|iz!;yICID+!2?o7se#l+>Ml{z)Hxp>R_00HOUK06=v+P~K|Q&p+*$4?kB}*8DqY4| zI!~I~BHm?GRUn!)wNC*`ntDQMr&L!-;Mq%sAZe-F`g z^{)Dx`Y8QFeZCH>^zHgj`Z@i!PHW0K20Ud1TpGgCzyYIx2!3Ic1fDdDf-skcRQM3) z(vS)t!dx0^<1aEUP0Mve4~y9g@q9n*Kr}7;k`2+c>{KU%r)58S_t|Z8=G>TrZQl_T z8bHDLf(3i0&+wQ&zmE%#n03rKF4yN@bu$8eey8ky{TlY`k^a&OJXm|D4>(oyr4`th zRuE=;**gcE^6{+)_&$Uff}6I)vaC@hx;2wO+O|Y z8dZNokXFUi-!VMk_u9|e?;2BoLp`0TzvuYLcyx@>;R`*g{)QKfsQMdD8d3Fk23u=0 z_4g?_gFnJ%3FoF0HX!RSDIrr5LLen%O2XrRNeMUO&o8%GLd>L+ojtIJZP-(Dnis<_ zY%2Pw?JWC*{ihxOJ-!BtHlzINxIAs){|wRItrK+}p`kaN3-Jf=x!HdWiZiZfJALi5 zGl*RIqK|f29FN6b2sK>IO?5wV7rNiLqsbI^-u2yLp5Tw$9$ylrE^PC0S3|Ao z(>7vPXyBhPCw|VHQrn+(tc1)-NXG1@F-D&h_Klz+ z`zI;v8$r6;Sot*0&$({|$T$-AjQ|-(!oCq8<4D*y0%ROvzLDx4`9>fCjU!>-2*j|2 zTHqT2GLD3OBM{EHBi{&wbMELF4&j_T@{K?^=Z@CR5YD+H-w1?r?r7Np;hZ~KH$yn* zj@Hc(&bcGs2!wO)$Txx`mLTVjd?OIfxucjnNcX<=!oCq`?!VxNeIvM+JL!jgBS42k z*f#=~g}cPCZv@7OAB$n%2qZ|+lLO{UtE8}R1W+0C*U5q0C>gfM2O=j2bWliG^PVzG z`3k$h9~8(@7$}#Y9FVL=PY%eZMNbYO^-S0|0_Ajma*WXF(E;iDw~>b>>+m8Hv*UKyPU9Z1dZGuJ7M1l1hP@4 z8io086mJW4yeQrlws=vzEzsaK>>Gg`KZ>`7WFd;Tg?u96Z5xPu!i9jk1!CAYLLgNs z>>Gh}>02r68-eEX3v$>u0{i5Xa@aQly_6wJ*f#=1nhpC#V2t{)8upFgA&ujikZ%M? z5)}50Kpp)lJ?t9+8a9S~Bf#|;T%G|r#vex5Hv-A#STpP!0j|&B@(h?}EkJ)iqeW1& z3V-?g?GZNlMj+k()(-ndpt-}@JaZiKjle#K){%U?{+x@m^dWB8HxiNjkZ%M*D<6Ad z-v}i5<^8a41m^pz{IG8X>Ih6ANopAa)Wa6xfN)y4E)*6SpdLDeoZSSdhaB+_v4B)k zswy!+JtRwGr5Vx}5>eI&P!BOpqufBI!2-<{V4A!@W{78oyaLX=;>astBAH(mj=X~A z>I*7&b`$an_Ngb;tLohvM_xfMZ3s#nKh-$$3NCARp|G&B&XHHZh6ZbOj=X{dqr6ey zc-kQ36>@V7m~X5ywi`d8!11H%QtPbs(?)2txPWwx=DNRXH?@29vU)8&Hl*#NGg!)UJwu0m`bnLJ zQ;Z4poB_RzA;x$kK<~k2gEk5QdJo2!ADfFzj@|q86XTdORh z51g}zF8+uOb#RPIlB~Dw$@V<^Ya6!M2kg`Kb-S?huv61%iVJv$tsZ7MUpbqd9~{VW z{%{JoCEcp-6K*^AWfzj&v2JW1>+W`G_W=342fXl<6{dO7DJzuoqf=Jg>3-{nr>wxl zBEggu_6fn1HAYkjV~vPv1YxWZsdOQXHKJWEgt11n%Y`u3h^R&o#v0Ks7s6O0+T{Wb zm;V)E%0&(G>HkES0)a4Pgh4|;NRNdv1X3rUbyQgD1kog$=Pckmpf9bB)?Vwl1<@p% zfi{e>qncz$aH5)InD4A|f+U+qTwqByul|UdN_VEa)P+s1<7T^8-2C2yUKOvA2W`Em z<{plEQO!N{_wzLO{&)Ui|2H4*_=1oq)D>C?FAA>AQwLWCdJv^59P%Ja zRp{eGl&WymhbUEHyZ}+ELJ1L~RE0$%M5zk(C5TcLwo4GDDs++|N>w;5!*#i^^030G z3d0l#x?|QHLrIl)$E-PqFH{1wajHT^4H{@|wC)YaP;eTyVIj5}tOuVwzXrsf3^0b8gsE39or?dtpx{T=xq5 zVNWHz=l^T^kBTA$-7#y9|AYPm0{sVTj^S77CTcl3RiTdzQL4gK8SYj}E7cWFRT!^8 zES5{*RD}{MR8}8XiJ>=8Wz8`}sS5RRs;h;m3fnb^QWZMs@S0A!XPl~VS_c*w#iWJ7&!>1l=)fjv+9_Fh2}b_F~#{?2cJ;3{k2=eIK6oyZUeXoT{+hhbUE{lK`&? zygO#iF$CQ)YmVVPah4d4Z-byaX3a4K-7#y9A?S`-a}3|hKg(etG<3$ik}wb&g6^0# z$MBXK1wup69kb>bl`FhEX3a6W?s#|1nqvsMW7Zr)&>gep7=rGYHOJSfJ0AN{jCv5? zty`+O)MQNOD<`R{vP7q@0|a+}-Fe5E;+PJJf#INY#<}6#H7{FzZv|M4bjZTttK2a z*)yBJvLT$=NUv;&W;PDCVH`^K!$d`E4Z}o3Af#cKXb97V#X^{92!u3jEp`+8i@G>f{9J_9;&BS+j5qCLI&=4Z>%UvPi3$I z;}r6^Z&3Cqu5w9vexvSCe^Jk?EXEI#v{o9&$Cff?Yp_lGQ9G;M z(u(M!UR!@shmLw*ofPnMbr#76r}S%jA>$#VhC!s#R}2_xkZpXa!Q;Xqzxkk9#cX7@ zHHq&0t_jo4#pXJ5mwD9m%sA_Q3o2NTS*@*ZR)0&krdpp{u-f|0I&A%B-LV8a(XRX7 zmHZ2N$-h3&dxdTOkN#Qzme2EEA%;E|CJ8+6_2Mbvnovl5NTg6ypE%xt3NAkuYK;06 z?4q9+dy6UJM3Lg5Z4t7>6XKs@L5cEKsDXx_(qL(v^og`YqIhUmf=g1oTwJasHm-GTz8>w zRb8qT@30bhK~5__1lSn>QLJef7ou3x zvo1ujro%mmVoeMA5XG9#^m7+qC*3S+weCRX4Kj%7dYrzZ`J#|i@t+UTGJ2IM+dlIW z4z^yLQKox$w>zMwb9(8qW6O-qyo}Ph>Ee&#SrKlDMI=$GEj=l9l=@1;C72}5l`JX1 zWZvE?E^Eom{dW>GZ!&X#_N0Tkr=^$W@r_Z4?$I(n^Cqemne!gk{2t|&4sC)P`P{ip zC@c-t1DK<;efv1PWr`@G0#Wjkr9hOtB&!f5FF8o2RhfZ-<1ZmfUh*`El9zNHqU0q3 zRoO;egZp=;7^VSH@{(jil)Pk{D3u74mlO-4ku(4Q*NF*3>SVc?soNHN3$dy&@p|jG$Kp zV4T)p&j@-&#IUBB(tc^Ad`&7O$14ziM$jt)!p{gA<_#P!(lk$h7+v&fb@aRd(mi$b zya3X)Iup=J-|_KeRE&=*g(fHp|HSOiTSbd5OhC5=Wcqk^q3Rk6*@X%LS~k};sdlSc zwYGIgdi;?bOFsR!cDW9<{g~e#g`5RZRC`HYEYf$FDZzeJ#?pW7Loy{bwU^-)d8j-= zo+&StH_48iEyEQ#zw)3`MQIc>;SW;aU1hpLXjCqBhWphDYB;?dC^C%O^aU+ZgSr|e z^9JeVuvI&#h11J{WTN5pa-cM5mR{c2P>h}i3^v9Y;q-E#`0^mVJk^Ac%!TGR<__~0 z^StSs#VmN#O0rm}=19x1(kxhMZL@x~&RVxDMpprbR~c?kvgg{CooT~<`;>jnF60nh zMRwXd8Lv1)oe9oNXQ{J#`>|vGv6vgHX;Zf;-5smt z`RxboDt05gSvvML*7?imI%sB}xejXtwgKV`AmAGyz5oKg0ip#^9~-ThGlctua>BzR zUjV`SybTav00HUjDfM%jM_lJm&*+r4i9Yt}UhbJ+$*hMOy^E>d1fht3<~S+;bhPpV zz9&w3*IQjgSXdFnIo27YlU9gZ#e*WJIis4CaLxo3VKir8IOjj5f^sRjn%r0hMeZpNmdDAT$V=o6 z@*Wvn`4XOt#g$4*L**HzhXR_Cs(hqS_8>+ADCZUM6=sHSrFKDL^GFp8HBDWqZc~3$ z&#Jf7A{vNVZS6^|qt;g&u1(VBYM2Ho)Kr>Z&olV*rc1;-^|d>spjYAYV$jD&$JIeocrPM z9K4P9nBIp!Hu~|$;W_A(KW{!{0evvUedpf`rUE%u_c!Tm|3sVrca^ z=YFSx^O)1x>E=LxM|Y+=pF69a@0`QVZ%#%47JT%F0|y!&$iJ^m7HaHXci%bk9UeQy z+ zWcX3(7Ca|JrCV@Zh)TDBeC-kG7EwFG(k=KW; zcv+1~x8R~0m2SakEh^oD`}C-E3qI4M(yf8D43chjO~uTV{QD;03%iT)&gc)a@@I{X zA3b`wvDjE=(1+p~5dBbe6ZnV1jGuxv@K2|pyTX0`3v_ZcbfK=tDgSKq1O;tI`Df4J z8rE^yT4K{DWUazWec;q|V*O8DfiJqb_P|f zTepZT3G^qHas#p?FtlVqmIQ{DB(kLD5m^!zdf#|EykETYp6?a&ANBtqG*ZADDY{1J z7J=|JLbnKnuMxUMAbgF`Edt?dgl-WCUn6vjK=>M=TLi+_2;CwOzDDR4f$%j#x5()5 zHS+rV6l8QtyJyHWgTcQ4xoGn^6Kzhm+ik<&-0dZXJC@GfM;?iLgoab-!8IG3irLeI z!R9#g6LX2V!6c~DC3AGV#oO%sW~0vz-a2@&%>0=98}lAhtw{^EtSFQA%P(bqX}cY7 z>Sm5*wRMi2u>fECL-!^n-AFoXiECp%@c4v;k@GuQ_nQ9#DJ#5{uJcbxSsgs4>h>s9 zZ?pGUkvYSx7pBxcs->0`j-$GBM+c>EYQ>jIA-Z8u_oz7-x!EC z^V-YX*mQP4RQK83_)9U)g=M!V>)R(%#tC|^>t!1Ee_V7b8NyT0@Obb`e1jF4cl>el zCo9>!ZS|XqU?zwB*F(*vA1_>3X5o@Cqesk}*f|uyk^;&o@daq+d zq8GeF$yNXX_KZ=_fTb*Q?rbRmstJt+Mc~}oB?4>^_6V+UNr)GVi;TQ3|=!?aqN2MgGmDELoH>8o0A*D$KAfuodxFr>lc}hfIdAJNjy0GL- zdB1#0z9y%t;L8iua8L{^RW>Q%pcrVRwnax<5EQf4Gm8Z?zBFXY3pHJx&>P6F`6}W~5>WP{r&%fu8PQ#4>&2Qf4QSiXlK1 zv-<=BR580xkmU5JA0Es>n!nNy59XjY`r^WaImi_D3*r0ZpSLAz=|Y)U4qXjN$v8FX((nmU^CJjnWjZ0k;`&Rg;0#C{vW%^e5rvmI-VL>9YQbEssOb3=X=-&-!wnyNQ zzX;GC10iRzTN%*b(H4mh{wMSV$56eat$Q~|Z}P(C>FIIlZU1VDsV9bTQ~bHwLplD} zWA|C)w_V8WfbQ)(9dP*P0P-YnBxklCGUUdPv!mLiqFWi-%Sf#=O|z}0zImP8^%sVd zSGtnVT*Z*$r=+l0LjQ{|h_?boeax$*^C~kwGjmFxT=l*@LGyo8gfavqd?sjyfP~Kk z&HpYO+~a{~AMN#fGdmz;p}6?ief#&9*`L_~J-$h?7CFx%M?ErYks;`jS&Mv}sExZM z+|P7J8+&e#UY2DMT2YY%dqwmNPNj#Z|b~b;0NA%#{&15#XZno0<*XW+RGzk zaVLCH!pxc3Gt>O77k4(RQH;n4nX$yAATSA7Vp7mq14~R|opobHc{ca`GBoYS>j1?H zt~*h*9vC||ZtUU9E!!^_kBApUYO4MxE8TnvR!IR=;(M`9V;x%-iq~sV=XM?R_R@oK z-@ep+w1Q%{<9D^PZ)IoSDTm`t$cfL%*%lk&P^g-$KoF|Nu1W|6DaEcz2=2;V>QU8G zfrqNK*1Bo^HC+Q1s`j16Le&Hv!l7yug$671aHyJOKr`ccqqjl)lG(;G!!{txIAQ#0 z6g2sJ8hV=1_cUBGOwuMeGos>mOUC3J3$mm{qEs5QxDd zRw)u6{B4!`SFKXHn|EO1Ga!kY#r+}z()4Y`)&3Azfc!T*aumLZh?_TqvknoUj(0f#9FT5fQ6($G}rC`^^2tKiq zNR-M!;=AH>aj}TWYP-avq9?{l_e+HIh1OCxslTL4Q>D+P)zWto9F~5Q?nr{1DA$!+ z$S=z9x*WY+;D*dDmuAZIN^d1afr-j&Wtn0tS;`6JPoL)5J zQ8%c2R9C&E#%sm3N*XlO@~A%AN7_Q|8x3}7zi8(*%sSH_)sysAI&{%FWqqZ-P5)7c zv-&N)h#?xa4Wg;{HDI_g$(U1?w8NLpnj3F7}>j3CJ2ww-l<}1N<5QAoi zuLI~|X;%0;fb)1Cgs%gj`yhNB0Nn@S>j3CJ2ww-l_{hO^@VAsdtS?xq{aZ=-1AV~; z8}`_)&0|wZV+2us!7mPkV^itZ2_s#@O>h1YBgq zHAcWiMqFbATx7&Y84yfAnZ^jX$cT?JfQyXyCtRWi;Vav189~J9%TT{GQy(_ zh^8)8bD^=TxZzO-L{pcZ@qo|9`Dh&YY@ClWfQyXyCtRWi;Vav1F6MqHqJ-m zvEY;Nh81YV8s4x1tysewR-hGYc*6>`VhwLtfmW>H4J*)!HN0U3TCs*VtUxQ)@P-v= z#TwqQ0}Gz^#Wfk;x2}mRn62(X_l$ePy~l$xp5!(2p7(ltDIQ^yba8J>&jE?}8%>oFW?p6&ve@FLJ% zz#hXjE*XLD0(zL5nQ8{Q3t+;FKz9L5coFC>ARKE$x{H7Q0)yZM_Mlq@0|cP0tGYp~ z%`O*?x}M8oZ65Pld)++5dh6a)kMWccCE~#yPw*4{x_%4)MgMjG9UrFnroY19>L2va z_&5A}1Slg&LNnocp|_ACOcZ7duuO;sQlvH)I$o zM}zW!^jcxL7R*(mL3vO^jRxhxCN&zA2RI>&1myt*5QXJhvC(o^uJs>q%RqXquv`nu zn9-m-pk$-4Tni}KC@j~4JytX*4|>?qpgcHlN5j!zq!SKDyX64swZd{OnCn_@Sgr*% zJlSjSz2Xh^CU`Twr5()CKOtDOBg|*c>Xq~Z$ zk_KgL$!=ypZ}+xS?1}bl8VjsIykC<#F|X2NrJvp5`;B!bW}rFBS%Lygf((>R6|%J_n)i-R;v)!$k9;^VT~Le z)ezRmkwgwjyA$=

-jSR+SAHH0;CbW}rFBS%Lygf((>R6|%JM@Kb;HF6}8gT8j4 zk)viA!WubhmVs&H=%_xv2bad~-%OIfnIvA|y84?*@;8&@Zzjp#OcH^}&+s>sp^%vw5qUtZ8#J{lm3s|IFp#Fk% zF{=K8=2BGs1^c9^`U^9#qUtZWEJxK}Fh+^0zaT*k)L*024^^12M%7K&igZ`>MOn*y6#UG2@~E`OF8* zie`+(ZVoUV6HL0H-9#NH*?MVEGTEyvszl6t$x-B>jUdE3(~D`twYwY7Gc}V z+O=$GZogpnvEQ=ax98Z)?F<|C*_1+bw^Q1w?lf_pbD)U`;JboM&O9k}e= z<&t3hahC++16>&7e(WxC*Sb61BklzkJV@}$d-c7iy{_Jy-YD-w59WKTyzSmk-Z}5K zSJZ#RhdOy#esBAe{dxY^K5X$1_^18reqrHZp{CGOz)+!Ag<-;b!Ytt{VYBdqfO%Jc z2nEEFVpZ`8v7Pv`2$beGL;M1hi*}30#ET;2lcE%1m?kZd)=1w=c>#Pf26RO!!jLWp z6ydT;Ed_XF5l<`v9$CZ_i+}<)C|`po76Fee;)zATBa2vK5$KShM=8QEUyo9Rp^g!y z2*VcRfN|QmZWJ~jHfx$qP3T}oDZ)UJYXz*5R#oc>tDW_-1<6*FA`JO#MiFjfcee-F zqivXGFR<5Ogw@aX?{=w%PGE`cOA!#*9cCvZ%W;Da$f7Xz|_F&_}K0ll?a_)a)nl-K~5;?5wk{;+V1RBJxv`%=ux?MwMCp=LP_ zqxwVzFhaRhiNdvS=1)OY%%yyoa(<(LjzqLE4@~eM z=>0D;!T)avRO#LOLWRP;di6U0GwzOaM_k2(ObTQ{JRKhObLPx3P;pwjLScLuUh90T zbLSCPDK%iFzj7sf{`u!nYjCYvH+=7h*Is*V#8vV+G|XAIZe7Ei6x5@RxQg=D^DgZ7 zqHqof7Uyhl4#DD_?akp`AqwY!`^6}n1M|uG;+*ZxAy}NVy*X@^_~M-H&Ea`D3g>_m zGGCmty*Uh4_~Lv|49)?RPacMIK(IJxdvkbH4?vs+Q4hdW3!)x?L>r(4vAos`{2j~<2l zHr#jL#2i$hPs}N5qo5oW??bmZjU4Bx)2MPx+dgK;84SxJPY5~}=2o1TgA(S6TZV1h zKY0KC>Dxazg>uO0+b^ui#DtNdJ5iMC0p0{H_E9?hQ0ITw#a&zhfP7f-Sa)IN$0~qT z5bJKNLRf{d?!mejs|Z$6ECK62tYTORSodQ+fK?o;1lEICC9z6jmBxAq>tU=iSY@$9 ztVggCvC3gRid7z~0#-$=N?4V#s$f;cs)kh^s|Hq0ED5U?R&A_0Saq@LVI^VJ$9fE_ z0ain-$FUk=J%QC2s|l8j)fB54R&%T;v7W+efz=YL71q;Ot+Co*J%jZuR$HugSPIs2 zSnaVoU_FoZ0#-+?PFOEub;jy~)fKB7R(Gr(STA9zSTAGs#Oj6h3f8Mwy|MaW^~HJ( z>vgPtSZ`pxiPax#0G5U|5Ni-tGS*us!euts2w#2SS)8tabl z`~OETZU^QqZZ{%{Bx`#LQZKT$qpl+^Jq3^atnHXl8D|e{_4S2J!mZ(bUwmH*Cf~H! zjF5@qKVL(ON{=;!r6`CYt()v!Yx5l@5b{6v!4n7>I0>1H@&9uld{~SRLEan_;{(r| z;~-=R^5$6F90YlD41^4&#p)uFkU0n$z7#i#L_+2uWO!V9Rw5EI2O$Hgw26ewLC6qI zwf#xP1o+!Bk&rnEnFX&Q37LbCfn~5YRXGS5ctkf(=ms9q%@ewTMRZf>I|Cs@5c%>5spL5m5k@G*$&XtA_(47kghSEo*PowW5^W@7rLMYe@3^BpU^8wOeq zhj+t3%i-{D7-%^h-VFmShr_$!|3!UucsKly_0^~RJbiTyLH@7w)enmQC+VvPGJW-f zWAVX$c18*Y9~K{jF+68y=o>d~1dQoEJLAl|@4j2yP)Dbxrml@WIv1guxyJ|fHq@(E z<4dH63>{y^u2O~ILI*#1R2dpHq);zW;sLxTnc28~7@v9)24_pUeHTkNg# zc6r3shB*Izzk-kH?0z?&*xE4F|J+}l2iGPX4}{^`#MXu|T$|Y1(Cq&YG#I2QE0t}^ zkIGr)mO^Z8sI5M!c8n3f81M@+)&1%z^_t4E?PM(@fNOvLYOh{Ldkr0rpr5o}YuDac zJ9Iqx8MCtPWDOmkn3xFUHBak@vh}m$-!>*2*XJ2u8}oZ&R3YTQl|TRaF%(djb1Nq& ztsgxH%g2{5Uq$C64M&Htw1ku;5G84N{|kTwp5GgjmeA<|VQC4S9uSt6(CGmz3X4fg z==6ZFw1iF%2un*ySpq!bin}u)jNhTt1Guz=yE7n)-?0!5hxi>jKFFOxrw4F*26tyb zws1wrFFq)8cLs2K26txww`Xv725@@@cV_^%XK;50j@7vLkGV5|+cUU3BZJ#B(4Eo! z$PxDlV0d(PpOYuEPgd#BuKnqr8+)Q{<-*xs?J+%e7&;Jr`qi`9-0a!2DV;MTZW!g= zysbZ>SMAuh@14F=I$?kqGrneIWT3&YVOo#mDIM|oUPXOK`}bzJ|KBV8KC(>yrXD`m zrgTb9KAODxaZS^vbecTbpG;#}9Md!`H?ix)E(r+<1P;AU4)8LaKnaoDHA*6 zwXj--&y^@}6zZx`;3(if7XgmK^I8-*3MaHEa1;jXQQ#=V8_}rZo;s5Cu6iNx4f&hbsal$9U5`j|?fMXCi1pzn)fm0CH5(eSP%J?=b z)siM~&8p&sUaDoSE46AhD|fXvrp>|`L_Ljb)3VvZg$pxEDb;_KtLyD#sLWEq|7(~41y3C z2Y^8k0^fB>q)7zhwRbr@3z0;mo%4nP3aVa5S?<1acXGY&vNCuPQgO7@i`fPC3de;D`41mH3_bz^XoLbOXc0c24>v4vB{FIjLszH{ak1z6dtOZ`#zbbkNzrT~Z0DvJ`YS@UgT=S}O&e4V0Jb%TLQeX9KI` z?eb4@(AmIK3Po?mBBf)U4IEGiR~mFS5Y2eWQQ;4@fL2lqIvW_P&CtHkg3bn_886dx zj2d5~f3F9f4Y1ZG=xpFyo+90XsGg#^4N*PCJ{zKXie3&x^%R#Ki0UcExDeG-BzVB|6#IOp zrlV*f|1%wY2rb4{>$iqaO?JjFJv zIFZ7iBx|d_4&}pwEgUSh!4?kQbifu4_B&t;2W?%jg@eEOifrK^^SRvqP zAp$D|TsI&01{YW%pm8g>e{z8p0zCf~{|+BmAz<(a`Jec}3IS1w5k3+ED+DYdU3e%2 zRtU&qy!e?ISRvqu5mEsuutGqU=1Aco4V+B15W$cJPYV$YY4EfV!H@<|3lR)y@U#%Y zkOof+5e#WiH2QWO3~BJ*u7e>B-rIFBq``Z;4u&+6`k`;v!H@>;?K&9JV43M=ct}H- zRY!+3gjscTNJE%aM~5_oS#@+sgXbs@hBOFn6E{4hfdwu!nP7nnc`dNOg{2l) z;KG|WM4RRBfORLfb-=n4QysAG#KA6Dcj5~Yab(5nA9* z9ISzLC%(|Y>813y^+4)ESaVx-U+6%64iJnc#`{Jfbph*6Y-l1Zbf7*5u)u{L7Cfs< zAa#LjQ65SlbpZ=p$m@UwE-ZCmI0v0@ZUiiFVZRF&xX_jZ3tUL$;BXOqI5z^%>JsEe zzycR$3h=BhL2d-$y$M~Lz_Yppxe=0vqgIz7Hv-S<668j}0vGNQR;8Rz3Fk(@0vGbC z@T@LDZUmmyCCH7yv$_Pi5m*|_j)Z4*@qr7eIy|e34_p{*z_Ysez=anEJgbWjT$pKs z1ujHeV1WypESOfXH=%12u)u|rHUXTm>_~VpVjsA0*MSEk_JIrITxc%Kjs(xK>_`|K z%Z>yKT-eXU=k@uxKCr-rQ~@k-VXz1mxbQ**3tX5ffdwu^%V2>En`E%Sg@y`P;KE4- zEO4QR3KqCCM7a-KNHxI%7Y18k z5#=u|u)u|xHdx?7v;!8nu*m@nTxjTm1umR)!2%b0aA1K8cR8@Yg>gJs;6h#jVdDxd z@q(Hz0^q`%BEdGrhyie6zX)o&2!IQ1CCE~|6aW`eC9uGS!7^Cj!V4KJaABqb7Pt_t zf(0&YQo#Zj8fu`XivYNAQUeQI=%IrJF5J~YO&0-hVVnVKx(I*^c}?)auLKsjuv7vITzFFk3tZSQg9R?MRloul zQWdbkg~2M(3Wb3SFH~?E>&F2LT!_}e0v9&vV1Ww_4Y0t4lLlDeLJt!xaN({A7Pv6Z z0t;NoYyZ9f_}}4|_a0=fSEm-xa{BG0zCNDLfT&ivhI` ztQzwV5jmv)c)rdYqQI&{wl?`ilRtQxbXfjmT^S+VRxI@%OIPajCMHI&o`nN6kA+zAe{l@t;as;9;&+~;q^yPWJ;FGU>@D+UWl@Go`Ao}vaR|rI39{37@ z=*t6NJ*g=-mpgW)wb4wMA;sk*U#Zt}gs@^nhJYfnQED#4r6F6n;xrSk!) zrO;NAi*3Y`N~(!N@5;PVw)fST@4owPb*#GAE18y6;L*tg8ZCZPJQ^)sk9St%RD7yZ zIynVko>6bAPgUgBqBZKI^Wo(1=;V|}OI6DEXB9sde>k4#zzXS=wT4=nSK%sZx*bT% z#Rc)LWoEDD{Z;4MP4plC>*`$a>s&sA7;JFqI|so|+*^r*4KDrSf(uEgJcvp&3(R9T=h0-lA?Y4)b^`t z5uwF|dLu?G9kHqw=@m?<)o%{r6RK2iv8rC7EQJc)uik0S#D*Cnr2LY56{KB8Slus* ztg1&S?3gv{#jLWMX?mu2Z@V{$cwtqo$VfMmmQYDmE&U&>Y8{v}v2N6yapT6ltk^EI zg-UE1dG)}zJ+I#3MI$$C*s!V=DM4&+HFQ+xDP=VEw)pXI^?c#c5yfc8O{g;h!}~ zS#8CXY$nmI5cyKx(uc*vhiSdJ?!=W7ULG4x6IE0TTTS?)!k)J-#*HAl=f%QCVd%X# zYxNrO?vy4ZS9?!*{@bWE(si=hv~iPEUWsV3kgv|qBvJvCGHSk6JmRe?9!#n z2en8OI$p+SGG%Et6gx@1#3E9Jf&xlerFNey!X+uP?s%z+gt^Kj?U?kwocyNey1Tbd z-XoV3(q+>VMf-0L_>X9ZPd#JN!%|gL~1#67>oK&Tra=H1;s(?zm z@E~s1mibj0y(EIp8Y4!MYW$+e?%liB7@ zYWZ2R#9jhYo=wkRsZw;M8Y9T(Z4sASh!zs*Vf+s+wO+1XH+t0=o+C?+9C@opN(H5! z>QFVA2W>H}6Xr^*q#Y7PbzsKpxx`&U3HepE7T<#J8lCu3d{rtf)sWtkPIa5oD|T;e zY{%XtDqdquuPnWKwQNPXERTvl%U5Ig%OOpueY_?42-O&I^{r##WidniLfj_qQeF;^ zC%yz~9(FgWNN=hN)7oiv5+K)#pU@T)`?L{NhRRzz}Kz$yd6;8 z8V!i~`7n6Eoq)H423kAqLoML#zyt0Cyd8AcDR3v??Z5->1iT%1z@31%0}r?p@OIz< zcLLrHJm5~i+kpq%33xm3fI9(i2Oe-I;O)Qa(qJu>mjz0Zk0jvfpzW1by9ejMcZ zdKuBXK!E}vp92R(2_DhAaN)uZ>3pQbJR_gDT`wLSh;AA|I=vCSD~Ln^OuD%-&ko#2 zznFe8hl|eQmUG*<@42(w@5m9ow+!2|ZMDUh?}xxO5ve1n>GGu%&M|S~ z#8mrjrw|zz>pID;e?CJd%8*Xvusj*Nt)S|d?GL8pV=e_`AE`fak%ukMAi&h+?=lI zW=@MG#ybPtsFkxiy6&4T#}*EEmZa;pvhUfmC!PC!q!tHu`apJ)tM`w`QXZDp@R<0aunbry-G^N~`jG|Y_0o5b>M<0Du zJg?pQGC2UxWaPRq&L(g6J*_Ra$B%1aEj#m={NC;trsv>D@`qZqI{5@meo$wF`=Rh4 zmHeR=t(RceneNQDpOhyJBXa0w%|XBs1n=-lF8g=8>V+JH9znU?2f6pFJaX`gOZ8fQ zqc_sIyvptxL5d7TtH1hc`m5LTk8zrF%be@@!6fq_X(D%s>Y1fyPm1+k&%G_|<~j?Q zkn3gM4e8_aE*8#nv;d64uJ^)dU|thiQWE9`)dJC?@*uQ4cd&{ZBJdueG8K8M?~?;iEwa~Pwrhar6WoPQX?r_cF^A$piunbrBpO^WI&6N%&D`@`81BE}!xcJS8qroS|8I_}tJ^3MpA zsLni7wRZ0z8vz;!#M5K-_z%sw_G?Zhr-9SXN&L`BaAsIh-11*;MBKXm^LIc0oVirH za_C^GQZGt%IZNGqty}Z0v1-+-w;~_euQtbAd<0$-1B!}sK=G8>FD z`@dm#J1m?RZVS(aD3L0&(M;?l4iLwPGsI;gRc7O7@rL+B%q10^!EC+yL*Nc zocIQ^*y(aMSN&YMx|}7eoR0Gkq>rTclm~<%@M5z{W)zSqKXvZsq^V4u>lgISv(F7X zckb@Wi2KCbRBB~Lr$uDn68DJo*q%38+2stGypWdmBCX?MI(JpBoL>3vfzm5(uZXx$ z>#JK2bz1at#iJjRj~*~i8CQ*6zZ==j84j7{A|ABe+qP}a9psx9@u2oEwQC==T0hTz zpSTgDa_%6V*s^PiWt(O!F`jQW+CQdyfh$*1ujJf8`jB1D7AO#1;LIMf-RW|6+kLNh zuzuxsN@^^YbKr{%9Wbse-C_M`U9|34FRj2W%--PU$n^WXPij_n`k74zl=*;@>@hPf{2XirYI;uSCEzu&xh^OzkM z?{9XAsQu-cD66DZ-D+lavR>nm?4&sloUE?@jYCg&s2c|SA%n!!)bC4c0jJ(F*}I&H6uNN@R4H3U1ZP8GutQ|iQIwG#x9&vJ)bX`XN5~5P) zFIu!HQXIM_rLmMVx)QM8@jS`$+Zx4CQ+#xmt4(L z=iej?w>J+RnnSLC9LQ^LXr@M&Z3dn zUJOHLku0W(VdyM+N<*bEbQT#TH57)v2I0OIkb8d6Kcg{Kpu$fKW4sJgequgok5_hwkkE!&H11!Jj!l;~a4qhsmTvRt{;a%FdX|NZy9 zHVhtY4+i=8%^Xv>Fkcvi`mugbPkE?ZXQEv4{Z=s}MvQ1Vag97{mrPa(lg)zd+r@N# z*tzo@_0wHsK*wWp@18lPC?Unx{$h7>Hw7XWb{4DH^;MLT-8ewA(9gte9f#s-sdE4w2dZu(`R| zyg9u=mep!&&s%E7KKc}1q{!1E*~}s)$XyLL3E8eD`46sDs}@JsYU`)OntjaDGqFdd z1mAmVq&C19W6UtH%-CWaGJZC07*C8`W^of$&BiAEH;*vCFc+H}O&l;!ncgqb`#~c3 zMS4F-1iwh{2Z`Vp>HQ!P{35*{B&adg`$c*`NR)7^x!y0*`#~c3MS4F-1iwh{2MO=C z8C*8u-8O^ECNg;H5-uau61*QIf?uTfgM@e6^e>y=YB;QItlcywc24Y^Rx#N(9jf`H zX~&G2<$BSI@xCnk_QhyLBx(@dB)-%B2ssFA5`*Ztrb$U|65VZL>Qs9wMZsQ}ICkvl zvC)c2p6qw-jBA>MT=?Rpo6=J$w;V0k5#%}ITMIXD-aJA2vT>cOIz}F9NY16WrsaC! zhPY2kCXXst>Rz01w&R+Zj2m6ZHLX`HIe$2+@w_f~mg1z}WKaZbuYNsy^;F78os`Q; zVuk{hQl1;hOT=drHkriEOpfUZopOn}a)DeXYpRyK>x{B?RIxb(Fmkf@k zPAdJC^jep)T)I@TckG-s%9C!-;+xJHNp7$edy~JBr{h(!J_EU^PUw__{QW(hxKf#| zwNqvg8n`k^*`qzzqV$q_b-kI6PWk|Sj6OqOrf<;?=|AhZp+C`c8O4pNMq?w^=wo1n z@rAM2*l2k7)ZYzcH(xU=nGMW#=7(m2ImyI)bDg=zJYilj@0pQSK?~)qI#w&IyEVj0 zwB}l?ECg51SMAbv4IA&-AJ_x!vGy!`xxLN)-o{z`SNoZr$0^}dbDBCG9Q1QWIn$ga z&SodcIqh6?@W^?^E#_8n8@cV>-tH$Zri642bkm2zTm`Nk*M{rK4do_sUy%zAw~IT* zUFI@4@cH>NJTe!|{2+cjKbv34f6FHw=FjuD`R9C;(BjiVh3rD~f>pE9)~yj+^9kXA zNEpx9XpK}-M6B3H96^@Ni^YxN0kNcz+&-Qx(6?(3YgDQfQE8m~P^?InPo5YJ;h-+f z={_$YM|UDu8iKjvYto}ITBgW?#2|a0A_`^lnIvpMZrC|nMT(J;lx}&DNYfCurp;8| zkcZZkGp%WZ$ctOv_i~Vr)OuyFQce!)Kh7PS6YEj#ZwED6 z+M>lTc2J|GEm{n7COZopuSQE-v}EBQ)M)8%17Es9jh6m45U$bE7A?XxTH2yTxJFA` zvX#Zv%u>|OU7uFFd>!`WVMerj-_@}@| zh7kUHrY&0hl==7U)o5vp79UCU{b`Z(jpS*|@leVp7m+K-gJSrHvRyf%Tu}U=7~WRjRcTVp3yN)3@tx`=#b{8BwrJre#r&Wce$oEW za_B|%%DSg5N4Q2yTeJw*XlaWUUmB~8oyJk)lHqB~@rGH`Y;JZjKQ=vWIsR$>V4gE? znSYv|wjA$R9j*S>XluIVY0L4Gb=`Vw<+NY7J#9GxZ~1ljwC&mv?Sl53_CljAT7+w~v_*?>jh41( z5w6kF7A<};{xEWwMa{})L-MH7%fv8qvbn%qZ_*kqZP6l&RmduDQE$1YEytHuP@|lCl7A<*8_r2wwwjA$pzPH@dmV<`p!r3`|#QWaz{XA{a;vt_+ z@N2ZRMT^gbdBpv)TR1Lw+Hw>S%ZjzdmSQ*2)0X2O;&$Qb<;%Un&BY~ZPDT*W4Q6TvB>zw*l*AlEgl+l%T&>l_Yt^<|THUO{7H!euAJ%s3h;_mG&GNM6c-wy0_Pphuwj6=C+|!mL@Robp zas=LT&xMP?Tkg4V5qQfz7cK&Cx#z+~;4SxDxCk69o(mW62wo<~ci|#jqoplcgln|4 zMT>BamL_5UWjaUTE%&tL2)yNv z@Robpas=LTPg{;~jh41(5w6kF7A?XxTH2yTxJFA`v2v}K)k_5XTbLFRFgbFu+bTmve>~1TS-tRJUF3=%??gTvDv{1EPu#$!19L_7ZY4| za01I8(m1gEArg0|{Gkrfoy1T0Df~iy0}qyGUrzwbvp*()<=J-?F-ROQ&K6gSKJ*bR z&wh-A8Pc*4&pwxo;&N3v;Mp&hu~9xCpOSr^eI*4Aly=I8iqEs(qu_*cMG1KJtyFYZ zhp36_T-Ap@;*R=KeN`*1`OrtOJo{%FSf2ef9ZU4hdXnxvN72_P_|!)q`iOl-vXN#y zFns7EeCp#@<{ERCdCbIRGsA?H-zsC(vRYVOEex{8TeGc|*0%4W_!gDLiE@@Y{ zo7vubCOnH~@Scg{4*Q;ojSl;si3TqFo{1AK`<{vJ9Q&S$I~@C-iLpHUo(VR`G)(}T zV=5+s%`uUzCYxibCxOi|9g}cbV&5~t=9q5FU~^1kl>f^^z3@W4fkcx8gQ!I_kZ8iQ zXa*8Zcoxk-q6yEU8AvqYSu_KQCb|nlNCrHRXyT6WQg~GiB$^m2&JvfCl(sL?L>|eb zK6a4$Nu#7`5|&7tr6ehkXrhYTNNz6&5>4!rJ?djtrLa;#si&Zg(o-3#1QJbLR{ZCc zT51cmtBOJDcy+cKNHp1>i zt{C@>K%xoHq8Ugu;aM~Ti6+Kcv#jOTHj6+XtzWHY7V_97>}qyXyMx`&9%WCnvBchN zC)ua%Yc|b&6?0IUHe-VmBAc;6cZto|;Eu#*Y%o@4GdA!nnnA_}OB6O^gDNVU zvB5r-W^5j)S+&Ai1+AWjHd;?@s5VjiN?W7t(vE4ktYv7>^Xp~wT6zn;tByhXczw3M zQvX&zte@9!>v*n586}PCMl++6K_6c+!(bm@QQTx7U$N0-A72rU1JK7;gyR78@fG1X z0DXK#I1WG`UoqBUA77EjWglM=jswugSA^pL^zjvb)X#r>g&+0vA762qXCGe?jswug zSNKss|M3-m)Xz`)!H@d+Nk8~eKR@XQKkDZv{oqIa{G=cJsGpzogCF(tlYa1{e&4HS z)nCLOt;79%Zq#wMfUvK>reTu$N-=Jfko~)`?VWWak z&p;car!mx+XnbX?F?Jcp3|uxc44C=NGG;Bah1r!n)0^YX*(Qy}95&CJw@o}ZgOJ+* zYm9{%)-r30b;$bJx?w%Ba@i1>JIP9k-Q>?(Psb(VgqAa(B2tx))vCabLQxa;3Q%+|#;QR5T_-QZSD>`g{5Z`am6H^;!CIeVhKhepdfgf2JdkQNpNZG&MRH z{ftq@Gy^pJGf8LybdOjI!&neENq<|pP9bD_Dx#6C0GOfw&tS*^lW1*@KgHdaq- zs5R00%35RXvW{7}Y-L!m^V?es*p+Pn=vXin~?a#%`?J#~tB*;VyQu(ao%=xWBvEx!1T#92#)# zxDUAmZW1@2TgUC;aDuzS-3t{H(48N`C-QUoRs0VANB$y@JN!%jRiU&{LwHa4Ko}@s ztT0PhE)X2Ma8~$LcqSl^SVF8OHWfRF{lrn?G}4R_H;YN)Y4Mu)NPI;qCZUSdNNO+j zmOhcDNDHM65@^IBO?n_@l?%%i8fCm zGG3XjtW>^L4lC!C+X|j5QEExGy4pJv4WhT>XPt+5uX z_0dLXUucUpY}5{Dr?jiu?^<^KHNBFK26{XFLp?#Cq|eva>3ejX(68wC^hl$iQO>Ai zv@+1$7-A$EbB$HT4&z7TqJcZcOXF3uv{}QXQNw{IXw-1Ixy}6EJZt`HJ~NTWDq&T# znpz#Ke%2^!nuR6SW-G~}GO<4yMr?6AO zspp`L)6*I1Omx0-);PPIV-7Am84le1ZW*_h+rsVYVvsxDo$ao4zjY70=iS>bp1V<8 zNv=BAjO)Y=;Kp#6!7byqaEG{`xf|RQE*FpDd{w?NAItaQNAO?pi+OD15Adh>tNibL zcHuRll7I$6JK;kiL6{`W7uE@T1e_4A2=|0Yv7lH^tRuD((On!O`Yq2N#fu{Dh(W>b z18JayvC=GQx#Sgwf0dp|$Rn4KtI18}4st(vlsrww5_z+nB%hYA$&ch$lwu01D2gvT7IpJR!eK4 zb=5FP8?VjQR%+jBhqd$CZ4E&z#Y?3ih^2U`6a=vpFO`BImg1#S5X4fvR0@JvikC`3 z5KHk=DWFMcFP7q^QV_&ayi^K;Sc;cQK@dyvQYi>xDPAfC``lzV&CM*JWu{UP#8SLe z3W8XQmr6kpOYu@Eps|#aLUo~;&`B5|j1e$HSSD-{4hcUCH-slbE)m7Ws$yd?h@yaI zQBH|h#oxv3(rZ#B2@Rxn(uY!lG)bB-t&{dhI3Zn;?n#kyLAjhBn?j)=4nf$ZwP}Y8fqzt_B7fFzg!lITUD*bR;<;>8ex55Ew-@HI$)i$u3Eoa)aO^pMgzN@ z{h{sq{Px&5VPCQD*^y2`r<_yAY2~216ZZLCba2Oc>AdQec0HfpKo?_~_RljHdAJf> zHLfY=`TVAFSi)`QlDN~H=kqJZgZ26Sz5n=o|H0(B|K5LWHj~W%pG(bu??3+De}pJH6|2G=DjUS&sS8sKl()AXcDX{!Z{>JV5 zp6_(3VpOkFQ_j9Tekwvcdp_k>@Rw>s2ldg?gQukiezKobG!%`D%qU zE-m8r#k7bk=~;fcwGhAkiLYCqio}eFJYzea8j~`qO*K?_|CBsG3vo+Vz84X5s$AuJ zX#d8&hOXQ0kD506yQAId?o!uqJ?kR^?W1RX#OIu^ef0bu2(*u$^$}}%U;F6sEm2$W zwU3_l5nh@#2(zNI=s&P|?`yaz(nx)@H8WUYe6@izOUhPJ?N&>YC4J- z6^;5vTf_HzV6Cy+IBujGzTX42&6Z|2bFk_AJ#fUlVE$&lFnzxVI$Lqpr`Al%_j}-` z_0-C3N87&N10(IJ_Sg0%+xL4Qhf~z4>@;+IzX!s}L>f#)dAF|H+U@Zlsa5QBkGi4M zDu?Er$G7nP9yrI{;{N3Fl6srx_dtJsG(VkR%KLr~Jmzx>uM2MqzTX3%3yXwr1e#3s z{2nMGRut=tZAIVjfwkgp@wk{O`hE}8mRd^Pq`{K!_rMY9f)rq=-j&f=j*~x?sl72% z-YDay{8Y}ZL@U1E10$8G%GV0TM5QQH!iXGdQMIy4S!KOcDq+L|b-lV*J*oPB50uyH zYOOU|t?`;Q*r^@WE@^i)-|vCudKcXTo2}5Pgc0ZTOii%i`#sR#7;Q{9mKwg_1CNcI z=IiF0rtkN_=jI~w8*{(u`#n&^s%X`>+FHKf18c3_mTzIC5=PXvTiU*bkxCeG#J*tr z7Dg&zL}w??@hyy0!ibyBQzy6USs1C`10&t3u5V$a5=MkAjFb(5u!WII7*U?D%Lg#C z)jW3cNBIC|R#QMYnMi|)I49f^0+?Ax5&gx{B260meh)krgJdENCL)|nq`^dllZiB# zh;TBILZMJQluV?-M1+%xG?<8RGLZ%oK^b;_GLZ%oF;bhV`N>2YOhh=DNP~%3ps&~W z>L+#I?}740U8A+p!|?qc2qzP1FcINoA`K=YoJ^#_M1+%xG?<8RGLZ%o@wvUo{>Ju_ zi8Ppqa59kw6A}2EJ$*9*f3v4=#u4{|`J5PJX-er&0fz9fxp?)HzS-(q`^dl zlZiB#h;TBI1`|C3!9;|Ui8Ppqa59kw6S31eYF)DKTE5={&FwDs$M!he_j}-+earsS_L7M- znD{rE_LdU%qW;^WY5&im`XQW5q`^dllZiB#h;TBI1``oZCemOc!pTG$OoZQ4^!*+P zClhHf5#eMa4JIO-Or*g?gp-Lhn22yPkp>eHPA1Y|BErc;8cakunMi|)2qzP1FcINo zA`K=YoJ^#_M65M;o5#&m)AxHIoJ^#_M1+%xG?<8RGLZ%oanpWk=XShgA`K>Dq%+m| z+VPT!G?<7SZc(?g>m?IuFcAyf_3mEROD57_BFb}hxz?PQOr*g?>?Am+OPrTXq`^cq z=ezJ9^IkHM1`~0Pzs3K_d&xu^OhkWSwBRQbX)qCwg`DE+;+vxH_rT}kBJmq>zv%lt zP(%uPgS0k?wbE|sxRfgSeh<`^Tgu&JFPTV#i8vx(kbjfCWFieFqO%gGP^_l!_rOi% zsghgul8H2!h;TBI1``oZCemOc7HI3Wy&8o;-q&a_5#{x|dTZTFCemOccIrpyq?#p2$HN7q&`*uTHmDmeh=g@iW-%ThKBF= zzyf2vvDY|h_u{F-}{T?`H-Lk0Q)c2dBzdhQX zZZEZczbPKuIi1&?Hyz(^iqD-z&Nt3}$M>6}h+EOE@3wV)zbV$byWQh%s_VEBTmh~u zhuU0At{XR)Q@J_ZKe+82j&K*afGhnjkIsA?|0zF{_qft$cu<6&NAPPRyf5?>FjAN* zd@cA~=|2SI5Q~bHMV~7@S;PWyy|`CADSBM#LK4bLb*0u)56R<7ua>Y=Ix1a~?n)k4 zx~7cgau@kynL-0SzX#6A6k?cH;gz?Pca)9_`YWTA>B>^YP!1|TDc2P|R&uJZt8c2J z8l!%s4p;HHx=8&--LG0|y82MfrlE*dQLC@D)qKAx)@r-8<65fbXc2k=y{wMfdP}{V zK3Mntrl2sR-}D!{?>9wfBhL8Lm}&TaQ`|J38oAAA)AyTVq&e06+T3LNepBSIidvPe zhL-O)#R6-+wbwdn`F>NBx9i%i?H;ybPq4qVSKHWWAGI&pcWu|s=e*(6bkN-C;(Y9k zb9}!k&N-goly~29-*G#-fA2s3&G#Rb&o{KGQSI+8$iHu#u)E2G~eb6%%ZvX`cx;($vNR8)>?1A%lrD4YI*Tnx5NW zBTX|Lu#u+XF4#!ZMi*?PsR0Kz(sY6Y8)@p!gN-!Z;lW0l#tL8~O?gDHk)|ag*ho_q z32dZkp9D72)J6syX}T;UgNZZ^Qou%i8Kvz!A6>% zyI>MnwfG~E%wMw-S-U?WX=WU!H@B{JAZ zQxyelq-mc5Hqz8a1siF)tRjPnG!4?gMw*^$@JTy9Xa_!N#|Q1eC++y49r&ajAG8CX zwBv(z;FETI&<=dkjt|-a8)+JA!zb=X2kn53G|dpeMw*I?U?WW%MX-^k1`^mv(+LS|q^Y|MHqvxQ1{-M_ ztALF(9URtCek#>02^s~Zh(z6%`m}6nu=Rs zBTXAEu#u()HrPnh2^(yrsk;L<(saiG8)+KrA`CQs=H}tRMw*szU?WXccr@bM^Syb$ z(zTCAGEd?DS%tzv1)-kMMgRfG3loK}gf+r0;h1n)K!yM@zgR}BCAJW|ii1S3m9FO^ zqNI{ib*Y)uNg5!Hk!DC>D_zB9u$8WjGT2I20|jiQ>x2Tf($!rBTj{!^f~|Co)i6t2 zu5Hu4*UoCcYR|MhI!fr(^rm_Ty`MfxpQbPQ+C6aK0HN5GLkQSNMkeNnzi0MX2g@<GT$z2sWMGq7%MB z&ll*St?h3*y+tQ{gPvc(hHudG1$r-^-liG?0)TcY$&i8r@ze<~w->lzm)qqzu*>b8 z-1DQ{xmPHd^Wed{2MawI*oy#o&v3bUP*qG5KES2G8DKP z*|#Ebvk+G7YQc5LQufG^``HPWFzw7=lEs?U394|{eW9C}?b+eOhYLN}ClYFJdU|?a z@oO<{lW27y0Z+z8$u#MlsBR-kXLwQPD%u_;t4x#5IG~w7oP=O?! ztLS^Qp*p5%OSEJ9Wzt{xUe3_V81SObUeftC_ndIgi#i8M z=QJlv9 z$+_-4{Pl1tmy*T_;1D+nyX?O627!E2geK*f=Fa^hcihEDLMUv~q;8Y_rOUk_oU^!# zV_)1P1j@c{+<8LJbwOo91cb&B^VzI9y0@T(x1kLdv>8*g6T)!Z>0!f$?V8GcgSZqz zy5l*%7>k#c9JPmh>hcWwp` zQpoW77-{5|TX{aej^9DlAC25bji|Z+r?Z?s9U%&0yx)0*Ff5cDZ7iBu3DLEPz=J(etqSdy;!J7>CbMtJ8;Z%YX8oat=| z;hi(REj{_#Of46eLdlt1-K|?e;JR4mE?Y)f(4fw}ocULpU)fho+UP;J(nA|P2v>S& zqbI7(Il_RQH{#gVR(3N*CAfcT$*MTlrG7+$|AR{S>6AxYF@N&Bc!Hvi*5?gfw5aZ) zllD)i2qu5O{nO8niDaweL<%By3A;5Dh_6!l5y>2lCfNT_1Z19+T)82hR`Rg|cy>A~+(_%rUMdjwcGFQKVP_{BsNvEsr0U-s`GJTcdV zO8E$hJ7dC_Zr!@gOCZF52L#Q&;sJs8b0F;DymKGje~@0n-F4ZWqI{U8U%!53vu_%< zY14|+hqe-V#k>SOD>bBUEa!I(^YCd2TxJt7cT_&=c$;&2UOf5R&C7qzALZb^lb+LS7z-Y1jH`R1yf#QliI4;weWpd2?bWy+M7(FxR!MozHjC(Vaj zC`q$-@95sq36m#J9zEu8uLtJP8styqgX2T)SFKt#qB?f;>SWR8jDMV@`OTR+=g8+W zBRYY6`l1tv3o9)~D&ihA2^^^%(PNQ+ffxj)ULod{%h3rFpU$2=J31jg{%QPhW%{X= zD_0`oyNHPG?h%)~0sX8Hs@Z*8NP83$n~xj`Pg1WeOQ}k1IYeU+6`eqU+r#b8oK$IN zT3XkX==dEeJDh9hh^7uJoSSzpI$j-zXr78BQBZKdyZ!Db#7D>1s>Rm=`5K=bc+vfj zC1e_3o%1U4c#m8DSIuq)smP9UFPGpe6j-oeK{WZ(jZc{8mVb3eFT#e;*$6l6Cw8v8 zi|uc@G5idEenWN0kRc$R&9Zz_0bw;?pDQZl=Hsq>^b!9N$X{x@qsu%>@Dr%>5c;wi!e}{ zq3qy(|Lu&d8V#-IpBjbQk%I|^3r7@QFZ<8P^c6YH z*Ar{IGO_DK9XYtun3xU1Q2WVvnH1j|(rZVt&x#eBD!u;w#gvN|j;*L765R^9Di*b* z?~f3;I}LG7POe<}Y2_x?Hz%l;cSrplJ60Sf$LY}r8?30bBSZ$6@7P(hia7ph^5TPp z_ny~&=ltl={Adt=#z}L!Me^2OLaeC$rM2JQY281)P>)nv@&DH7Uxi zAy#+M%%$Sbm-?&5HnE0rMZ^cjKx3Wpo|IJ?DA7hJ!j(|k2t~LON*kdFS3+qcG%=`z z?rAvie#)?vl-0_S56Qt9e~4^omuNSXf@(R{1LOb84kjts!L-a-tWs^R4Br&SQA0n=hY<${rGhKh5ue+f{I+532u4@ciMeHnZ9X@?} z>FM}GRcr4y2<@un-1mvnlqf9&LR6IJt| z#c`>^+uS%;yJuywtawM^<~c{)yUIrbh6@kfyIc`&1^2O2lUF%3>u zBtR2S9ku>iPGP!6QEZ?A?WICD>7d}D*uW;9J{Q3zo{C6d6HjZU#Bky%x>Gx`T|0U) zi4=!J&o4(XJ{G6CKE^I)HUSNmV9(2IkApv?iU9R#2=s_zPA>W3*B8Ut+U>D@onu3 zebyXu+$EQqORkZ-wY@sJeb%kp4`<(-M`?bg<{Zv)`0yrOTtcPXxr|+U+A#v_rxgBe zD~O+$qhIMB6Su7>oL*{94su7`N+R!+9M#bvk@uSBNPV#Rwce7@!Md36*sN#FPmNO6 zUb7;J&vAurG_odHQTlSNmX&B>uJr*={UnREjoLGEb-rB89s4;kwY-(TSh470rREaV z^ACr*+JiLE^80PuFTEUcb~v-$ zi_SvlihbV2d_K{Q;;xw)4(+{fQ9#BI<%U9g?=941?g@t-0^57XVxH~2!=JPK-aGaP zZ14R^E0OlzuY)KXqOM1hK{TF#)aQxci8v#&?G^Nu*!IfhKcqh!lS_Z8xkrzt9)0>A z868W_)kuQoX)AJ%Dm8c9xb$&PiTJp$Y-c5OevV%CC(F~@7k+w`d%jCP)KQWo6fYi8 z{2-IcyZ2WrZwT>#;3gSZpFWz^ms~!c43ErzYlKz@{2{>|p0{OAn2`MQ{Q}T@+Sk;|-ZZTtk)5vIHFLSWP z$t8PqxLoAAID)cD7WataKXLyj9=p=~$F2i~h{44LFY|^9%(Pxu#*UFT6TBgv|b`8lL2-WshtJbz2*>{Xin2}}1jJBDX(X|~eh}UZ0 zJDYE%{JmI=!lRLcd?t%Z??@db8ZAr=vV|S(kCL*Qr0_;Yi|ehD>nA5i&n4@Dd=@t< z2N_q(I^8TUS@!(X4in#^&l*>+*1bAfHaZXy9L*ADT<=M&UVW>RBl-DtId>o8BqNIt zdpf;zrSu|eF#(zg1IH_`G z%^l;7YZ|3Q)wA_F^iO59`OTKWdj}6ri6vj*^#}IW-@7*@mP{2iE{ACIPqUXv+X=@z zv@%Com}a$b611JL!6NVlUKA{nERxgoLBoD-m`DJMBnT4;@T238Kpv3*AGibE zFp*&BuP%MRE1WGRCT96rtl4@alNRFBzVIz~m^;tWWur&?N^Hh=;;D$6(!SOe*jRt# z#*|nhMOt0r>eh^u7-GX&U6`D9X#&E>QnJ`A--xW zu~jROJAFLKN+JkLdRfWh`L4{3A)m&&Vz+9Y-daoUBW3#$1Vu`$mPOOLh&zqG^4H>2 z`KM|l$<{I@mI!tCTS-4vD=}yJnPc+LVxyL8*WO=Sv1#Esk?DB+SaUnJTQZ_w6cjocE+-Lgk%^6hOXp>ifCw2-`@0lDEy zg^7bwidCM-KKvv>-Ze?Cq}CZp#@vccsiJ(fTzlxFUdzvvSoBB)!RfT!AfAw>sY}!~ zODi_XK{kpt)i<>5YHQ`7bonP~bR+VOtl0GHuU~v!aSA!8(4s{|i;7x*gXVMZYj11s zYMFsuTcXB~7n-*4td{ocbPu+%yg#uF6`#4dUIcMa{xE;m(zCsyDmEdjArCLA={Tw$ z*HiU3nyu7-)vg-LEgVxi7#W1;K|=+5_!B&?@b`GC?tBQhx?RU$_;bgij0ko zi2Z?k$YtaG2g{+}gXNrJMEYB?=}mG{&*A_1Dp9#5S8PfQQKQB0Y7{Hx79)nTY>0_@ z8Z&d{tnFm{L(9D_TUKm3YSgHR(%ZhYvFZWd;f;-_w(&1?UIg2a8{xu zsCn|Dz8f<`(dY2m-;hx$p1fwAI)|c*B9h+?3v`;7^Kf5_6Y^hja?48EB6;?XDCI)! z7K9(R3x7f+`?Rbx>F`&ridYrVxuj;Fq^ZhI>;bPU&_iXJ!tHS4@s2d(g!iB!L_AB08c{L6rcSa;fjZDhR%Ol|mM0gDw^vYaUsRh@G+pZHqJ7jW_QNtQy%rdB; z9Xv%l6|}=pQ!zv4LUXlA1?}J|+Nq#@r>AH?{JktUloR^ko0w~T;asu)Z32FSXPw@E zV4;;-G$yT&v-R!M$-NVMW7#(G?9`4^r-ov%l9=dhaa=OPBR4LJtft7Z<=*Xzj?2335C8g9)gR9(^6*l(Ht{S;=YILO`EtUUQ9cD>G0v^ymlWcBP!$6GP~NvPzM)jXB7+XRQvbe4B;rZd`f+sSOXTi z1*tqSWrz>ANy7yXhugdSPQrT+r-bs-piw-kOv2KW1N@7XO9Uu*h=^0pB6oC*NYaUC zbP-9U<}vX%v846%(32uoWB7!nbx2IAj9Zl->JQi7Vc zB_&9ss*mB{;q$t;s-cqkG(KHv-74ea>0nWwM9HL(A)k@1N>$|g^5-%EG?Ch5>^%7s zd7gwY)9!uZu2;()914vfl7lT3wrq({T+zB!L}kn=49jW=vWPBZuN8%e_6B8fop5`<&)znRz=>+FY5_^rQ*A~rm z8b8^ZYkh33JAk!9)z0Ve6~bvzQw&4c^KWcG+S+q*LMKnE@Em+8^p;s1ph z-LjWyUF=BrCHu`OSxN0Hv~ORL)9p-~Lgpdp<(ll=p6h4@WG$SRm!FsV2QCDUM;<#C zaV+(YE2MN^QO-^Ir-!ed;0Ro=xNFwFeTDm0mrQqOeDG!|js*(ly010Zcx6ptt4z|z zZ$Ni$L|#!&r2Qbb!ny2@ufz@G-mF@;6rXro!Ba$%e(x$TxE=iY4DuTGX|Ti{++-3{kwRGkq8IwOJTF~6H?lK5ulRz zp!k^htw4Z|F~Uq7{KhTF-IsGwAfUxh#5@u6NEw}Pu=FrLU7GQsbVB?~JR$rgVDa)o zLF0mggyc!lYxvU*V>U-XRPUS8^K!C85y&T`f=%*z=_~mU`Ep;f8SR>KQ7+(X;nljC zAFh07!TSn9V$D+s66TPvvq0x z_ydDFb>cgb8)mdV&>U@or3dNez~~DMzHr+y%GTr009VX>eZbLdnbG3g#c9{bPwhlj zRu(*mFWk1o*}0FI#UoZCcs1{#oS3`RS*KpK?sU zxon0Xd;jD2twiilFo*jG>yia^q+3>VyQ58|7lI2x{JkIn(_S#?1u*Re#os^S{);jO zg82KsxMbs)$!vR-Ny15-_@Y*_nq7tWX(cfhSZd(xR@NUNJ>U*McJ7f8^;k&uH zQK1rDe;Ked%hxY0>gV?B2V^hS(rnohaP50=0XptvlF%B`UogOf3Q(rN1sZoW%?6Ys zV7}c8<~X76-J$?~Fz49*q5uY2a|Ev__}PM>&25woL7Uq({0|3gZgU(6+T3{R+*)#C*ydL3UUQ*pz~(j(Wgr2Y+c_SBHn+*b z1!8kc8ZbKo=Ln#_@WKmZ4ZhMNNsQ84izIpk3_VAu(IewzQ7jh!<0OfOBi#a&A0;Iv zfr}MHxByfIK_I!84V6REa2$LVM~)nE@?^xxp2~X)QS4CXBQWbDb3Trz*2fK#FjBfn z#yRXmHmHpil%Md=kx5y;`oyqSr7nIaaZJ|$!r~E9M4!V#{M|OmN-->YYtf<+V|t{b zq$Ex&A2pl^4sgegsiY%Ew!BEjV#ifKuA;IIUXa#X`jiDRq4Bd@Pt{lH>(j86E{-H} zn{_(llQiIsCK}sw7tY$XA@iszI-fIahv_4z1L72cvshSlB!7D(&ru5fp~}b zr=N2Nxno`25V)|?4QBK}Yc814Q;@^ajGnSctRHXyjM50~JUGBApp2thG8n;|>RjH7 zL}^F#cM6BE<S_c)2}5gL}N(9-zTJUTzQ2;2tlx2WW7Qm)iq0xW~)w0UF%n<@Nv# z?(uSafCl$?xjjIGd%WBp@a*x_9S=0P$II;j8rv&U0+Jb3na>W&A` z9#7rz;MwD;J03iHJaxx|XOE}uc<}7;)Ey6=J)XMbVYy%kY*|EhMc~=vsXHD#dpvc= zLr;kW_jswg;MwD;J03iHJaxx|XOE|I`2XgjQDBt|o4 zwA^+4cK%W9pKsHsj&lUxItqF zcz8f+>;O^|`i&j1g9{ovpeG+Rc0fKKGPKq;x>=@PL#K2p%4g(gDH415!F5cz8fc z2LulfNa=upT2Txx_Hv8=#e@&;hFWu!4hZjZ3=c@@fZ*W)DIE|zJRqe5f`$t}>+qf`-1ZlnxlKXel0$R^L$LE*_B50l~uqQaT`Zg$xf! z>44zj0Vy32JUk$!146##SP?eC15!F5jI&ic%_ew2N(Y28n{%Qaf(N8@KuC3TC(|K# zKuQM$4-ZJ`fH;>j-CUR80Vy32#Wxa{z!5wkr2_&RO4Z>h9T0}{3LoMZ@~e4D2ZZxD zl&UFsxyA6Vpb0AlFSi(Kh`}6k@bG|?4hStJ5?t)%7Q+t7k_sg+w;0IoIZ5_%iy>bo z!Nmj*Na=tuPEnOK#mg;*GKEv4RWG*~QdM2eRK46{XsES#-*3}_Adu)^kt9M8Nc5Zm zK_Jo31_Xgbqf7__iLRLt1QN}$AP6LSzy@ztM3WMMv`>DU4s>^hIBZr#Mn!Pk`P1=N zTo42jopT`wB$~`Y5J*&+hkASqo<=3oq(mSk*FoOqOT$aqW&*SqUJ(2h7yKanD)=id z2m*)l2MhcFmiWN}KY%5Eu)q&si61QR16bk*3;Y0<_`!rvz!E>0@CjJr2MhcF zmiWPhPrwpCSl|b&5;uz^@q-0^K&;eFB8eX?@B{Wp$0U;Y!2&;kC4R8L4`7KOEbs$Z z;s*=-0G9Z{0zZHyez3p~V2K|r@B>)l2MhdwE;_TvQ+GTZ(V0D-y5s+C0Xz@^JkeLO zzz?WxF?&39$HOX%+2g4@9%5~p_`w1{V2{o0@zfm;s4sWkcIG)O@B_{`%pOnO@!%6+;p&DHKUm-gEaI3wo=kje@$ksqkuMbt!6u&B)l2MhcFmiWN}KY%5Eu)q&si66`c2Q2Y}+2DXBelQyxu*47MTL9);V1XY2 z;|2-*0G9Z{W&A`9*>JlbjO2dkEiZJ6_v3xiFWuEMYY2YdB;g9jZ@i%!EcnbZ5 zk;2=;Jb?wC!WrSJP(`dSvcOZAAkG#)64#3?@D%Qm>PnAF9V8Zb3X7yQ(pKq!!~##@ zk+4B&u*?EaVUxU1{sp&vEbtV%C}e#+Rbe6vAPU>-N;S2CN<6`WM^%MGEI-nsgY&C9^;ttn{m^qZZH#?iq&m3vKZO$`4 zF=^ljoH2>sy}tD~>uI#MBw8@Rnr(e#t+&3l4p{{jN;mJZ>)Man9qbqFSMBk3iVchG zHTG8ffPK;~vB9b3z$4C+&hyS-=M87N^P!XBz$Ry(^NaHbDvzVwhuyH*VSxL(JJn@@ zr*OnQ>t1)OaV+o@hI5m+_qk;p3p|C(TqXWN{xO~fo&sw6(a=d0Q$#QoDL`$ZsnAa7 zA+W$xSS4&0z8A=jmIj_etk_L_IV`lHfv3O{Pg&q8u*6dqcnVBKzyeR*Vq$KFAwwdD zjJOL5B$E*Eg8~UB5d5G(G6?}cD3DA-zz+%}lMwKO0?8x<{GdQG2?0MS@ZV|L1V1Q{ zOhUj93M7*d)awQ(A>aoEl1T{oL4jlv0)9{+nS{VCCpZZKe^3IMgup}L?U*+SfiJk= zBm_G0!AS`G$Ok7OFhmGWLf}uq3rZk42?f(cItek`;a?oFE$_IaIRBrC2n$U3zj`9F zUxYe$0~7umOhhiwiAdW|2}Qz1DRh`3aSp}iamH((qt3=fCPWTVTeyI>BZ6pvggbIM zrk4B9SX4gM-|lD-PDJmFsVi?!S~=1#4vXGYlxqUIwC37j>Wyu)t!0kA^{_qE8FdC_ zalJD(i(#Zg{s?D@(~gi(;@6`Iv3JJ$+?}%xlD0|1HV-48g5oJQ@nJkgyc^~}OKyTo z_|Jqi8|FWgxeMVxV|>PA8Ku*U_oF&s9M_nOtF(11zm=%)HgKo8D+Cq1+CFF$QNaawQNe#lR6=`bqQ!oIV22voz`qkkSZoT~JNs+5-_z!%pdJIs63hA6d8ox5 zT5DeFViTpTXeEf9S5ri{9?CYmXUx;!x>im1$7sX*`ZC=gqYV!lj~V_LZTQ^y#_-2z z7ql~bnBf@h?MRk5*;V^^6AB~`rZjGBHwIj+XGbkqU=tuibnLu(^=txU_@H=RC}f9- zE;e>{lO}u<0)U`nysgu?-j@753e;j#-g@t?w}x8xTTQICR%q8pCgm-}&b!w|^=X*6 zfJTYf6hu~pFgD%{9V!h+B;s#m*y!vI*jZ38-}~AhZ4J0M9fk5wzQL!PEtkB7`=(a0#Uvty0qM)MKMFnNtotZHk8N*&Km?#7N`Cy_96!XDE z88iq66J^ku8BCOcbTODH15Ko0q6}n9!9*EgGh;R~hNE&YQKo#vo8%^{UcLIscM~_3 zqBME#o6DBvEE}Papozmu{zxLHk4*`KB9Ih8K@mubprD94+v=3&of?srmKK}R)kGNx z-fa=dn<{MDl#>@5D#|&fyrd?oFhQNIex$BfS(Z4kFmaY84lGQZWr+g|6K7fC1td(I zOeSWWMr)HBwy~h&@6gc|s3b`(I#9S_!?q2%Mdb;o%S|mxIGvCXDtas_wGfr=Ibm7k~XLEKXM9Rxy?AV55Tkk@W!=PP%NU;OUkFE5RB3chd zk@AK9d69)}de_QDQz)pYVIr2S)~}+*tslAnpfV~^Ti=Dq1BD=Y5P9%Rsfdya?pK?r zOiD$RRPdRat=@eZv}mos)?3bRwYOJpt5hUGTo|go_kPpd);WaHuph;JJ$F^gO+mm! z#H`l4{>Vwzu#=qom~%ucsg{lmiPpOiA+fXdu6?1AT3ACm2O$hgTJJ)gP_`v~7*$vq zm3#5#T0P$!@=2?l@3QnT8KU*B=@q6=FV#-#(T1rvU(+kMq;(Ej0h(__XCt)UMR2FR zjA2IdhHA!B`i#enVR|jIz^HHDV|K{=)Fr9j%c^_$~SQ%k$Ib;cfh`-tnspksvH0B2sP3fUeH&BP6xBB>zsl zIEkKp`OhemMcYAbyQ$sI?qR=TziH2~7uc}M-fVwwpRoV3%kBG|7zbjVZqCcj80Q^l zzVj(HZ69-fb8b4--A3-?Zf6(zxg*`T-FfaO?nZZ~o9DtA_o`cktIz$7dzyQROXOez zH=Fy2ThD#V9pVbOiyYj;*X1AOJMb^^ukz#h6do4wYxu4F0sbUkf^ec*0z4u-DLgL> z7Tyr13m*y@!i-GT*TcFt9^43W$GwUYbZYZcx6;+&dnGqzR|Js zhIySPqo8tb2D($`iif^<98Fpi`>bzm7|V^h8R(~3C;t36xkgtSUd#bdFQR8fgkmWe za{vU><&QZ4g6ZUI6#I2l`GHGZI|P_; z4ps6~jJcnp+HB_!N;CERm=x=AHF09cj_o_9WhEw|*PwUucgpy15c%W|t?_EzrbPYv zHku5V>aH4R+&fbxcNF?Ht7_%q`=~`GcW^=Oq(16+ElPXFATHVd^ERhWT1l8JYqYJ} zfmBG;7OCCzt?C#Yk<7;tNy*}Lyetc|kR+r5S}5b%Jl$ztX4nda)oMD5P*3hlD-7Wy zUb>)3ljThgCgYE`RByIwP=!H*ip^&Fa_gZzHkw;*gX_nE(#f0(yT3hxHO7I@v7YW>}!@NPI_owcr8)$9f~g?Gbndy@UWz0Cg7 zrtogKY*%s~bRKh_awxnTW;%fE04Yl2-ZacS!`-)59-LT3f`t=iTm;%Jb za1hIN<6h>*++_s89_|?T8`4&)^Az5Fy&pf4f15W=6Y6ZQQ|Dj`@|&hKn!bJd^z%>R zleVq?vhB;36{g@*(=cO~h>s4cdGi~sA8{cv^J#JGlEM&Ch)>4Hq%Z|*tO%h*co^0E zg(-ym)lvwy=5SmHw&uVx43G1FK6pqh5aFU2oVCqJk-S;kvT?tdXw=5X?qJG^jwep! z_rj~WFy&OJAgVVKNQX39_f1U%D?}Y!fEx9NF){KCxtlzpz?jaPg(+BJW%nU?iNX|Y zT2|X(G=s{S8Wy(M`dipmC#&xey7s-Rw57o2kCUxJ$ z@0_9)>vDu1J+5ak>NxDPe?j2D zZJSZYVSw|xGu8RK!>HqM*716~KJIXL#w7QBcbQ9w3_rQYN_V@vcM~iS;=xf@FsRP?UN^CYjgA>*7og_ueYnQOMRIm2E^JOYu6qWiNw72$&tO2 z2Xn>UBikq8RWpl&ueo5k4A1hxav2Wuq+BNYSgNpq*MwlXyz`Pk%jI*@pxKgCCbdsS zbPW>IayAW3S>K6B<35Vpw~yaP%uY!uiJ|sMD#92@EjCdsI7Xs_9)D7=F5&jQ-T8~B zLQ(Npd?iH=PP?8gO6Xex$m$vga%5tWuoQW~%g;v}{?!W$lx( z94!+GGV$#{l^XJEGGN`%M8y=D{<0xYd3BB4MYr*YF zk#eN(;MUWX&&P)C6zI1*E?LU_qltJ0r)xjURi_TAFl5NkWe8$#dogvF@;YL6rSML8 z8XY=cRv|cao~c1_=v-Te;Lv%M4#A;wtO3EH^Bx0&L+5@b1c%ON%rIod8#+(0AUJfs z$A;k0d65mlq4Oh7RGZ)Ny{QrTWYX2LKT5-(5rhcV;Vv|*G8m350$lutr4SISf zRy%Pb;=~5$xwkX8DsFw3AoAcPH&~iNfg3DMVLbQ$DoulM?dkmOr^H@ygi+V6o8FDw z5OI^HCLGv);6Q3!?2yy?F!Dn_f3Eh)MoGttvCvQJ^ZfHU&nG30X`jbGE?lkm>#xgy zO`U}GPb&Y~!{Iv*yVmZnCcl@QJfdiE{}|y*{D%&9Ja{mz558y#!s$on;7hzxsw{Sr z?|=Nrr6Wgjg=Z1uJbijpS|6+#`U`J~v&3iRr&87JB58byf)6%`m8IOL$B3T@y`(Ne zHR-}L(qd`2G^s1`afO|U*lPUV<{W-uLyG%2T65Y>lx{u0FCOo)w9X~18$2ogO-7&{ z>c1Y}T=RA-d3aw+tB80wp-Y&G34;j} zs4fAJbqPS=D}HQ$`8=zbcs`+li#`Q>XW-}UKmVM10G)KdxA}7SmtQ71?>Q(E z{Rh$}w%x%^xWn(@CL*3p>XzrUv#&a|421=DundJ5Cs>9;mb1t4m!Z(v4VIw=dF~lE zqu$vYb)&=Mz&ds609ImQYF+VF>|d_u)LJ~WT2-_RLmLxcA)F@u-iAzB+H=jg(cBBw zueN{a(nAl;;!ek6m5*_omNmB;8ZcoFx^Q;vnuNvdGOpMKVxLB@XoKi#9U9{8c0-W) zbg_JFZLHP^W@7x_&SUr)eQ!o!rM8ZP3jA??GJi!p&DWD`v5W^!h!(c`vF+{lMF@NL0URZvj{c&Z92ssQ2!^=A$MGB**L zSRHmw+q6#>mGF1f?Rls14sVbUTW)B;_GIyE&jXXSKA(X}Pz_jp_MGS{`!L&9Evy*Kxc^yUG4yKmi#{G(gO zjvb2@>I+cRIzBq1G}5hos}=VTw}${^#TP4d6UdhEofeI_@ZEjgY0A?rVfpH7GWW{b${KTsT!RD!xsp$7*8L0h6(Zm_pzw&1*e}qtm64l``kM#TzcR8=ale zX=w!3w9Ok$EsR#yc5tJWfh^m@VCZcQ}I~=>31R%feaVHKVcvPhC4h~ zCIXo$!D8ui=^KfOKx)f?%niAR%tRooWY{c!FB2C(i%5WO%FD_ag^57+C~!>qO(DGq zi%5Wx>f0&-TCj+OyDVfDkpQ!`kF@m~6M@{LH>j&W`Z1R8bF(_6HPvyei4(3cIXHd= zc4|1M;Hw~+GO>yI9Jc^0M3jypD??c#4<-r%fMXA%(M*5wM_3-FK^NY*XdZNPJSNJFQ?>9t?A+$ zO=iomA1lyQcPU&gB^-=U9^+svjYJN{6~6L?*)^|EN<%PFE*W8taS4;6G9oD|Jo@O~ zi{uvQBfNj9vxD-g`3(~}9Avn3ZUJ;~;ms|84lca81<=8TH@5&BT!?MNF5&dWdF z^&Ry&84Mks|G& z#cd+6h5a}H$xrT@eYG?rqb#GwHxy`47SnYzG0h%79&wz?pSew)Bi_tC7Ey9F0w3HO zSvZ=#Q1Rl(-%o8DSx7(UXxlcwZNogA z%+-mkQ6s-belot$bt0!vkC?vqKqF+&?X!Nds#y)Jog}SjqrKBE%DswnWW534^IdqV zM?|z49ZjmHxhIZoKX$Av61N0p$GDD|zMX>QX`%h`o^#m$m7Ta*iq=d_gWSKrPUMQh z+4&tJ&S7~`b}TCb$K>Oqvk0UtxfpxLPDL=u`P9m?zH)XsM;y{%0_!k~+{E9k+$!uxZr-~|5{@6WY@F~U27Ki3Lw3e`n_t`*D^ zKN0=8R#0F1o8-^6g7wn3l0Vlf%#iixTAe%~|1uCQtog|^X0)GiRKE5Swk?B-PMBrI z%~KE_M|kl#I$X3UUwu~TIdbcXq{Pw=srW3#C7yii8Zd&m-8krRy>Iy zu;+oj4*#DMbgmoYyXmhlT#yi#fVbudz5Ihkc;ge}==J3b=IMWJ!95rpe(&(%4QNwc zsk?f^F@&jJ)p)|_YLH;~X~z6nYp|zZS=6U+_G;_2Weu`Sp&A^F4EJ*31esXT~LFtfT6rM@&pwdflLnVs%s}O|Y($ zMsYhHsgrJ_qkMa!|0CA-L-gLWOzZ(G%lm*i~DvF!-Es=ZxrX%DeWjS6O( z4a6cq9Rbu30G=a&8Uny`1W-c&^mRwL)Db`p0pK|Ts38D6M*uYhU_s0r0n`uxo+E%7 z0>E=2;wW*7_<=|b0W%Jx&6_#`T1rnm6Qip&nj!(AROY1^N;J}-V=e2;u=QNvF{ z%fzglH4>%qK_59NU4$YzC|!hPB`95lNHr*3yuLtvNnfEBlSkVP7x;v_vcsZRa6?Vd z;NyoDo&k{Tz;aQ4j z8J>^ve1c~=o)vg>JfGrOi6;ZkXLwfOS&e56p0#*B$FmO4dOTm?`4Z0tJR9*Cc)r4u zi6;xs*LXJJ$;Pu8&lWse@odBM4W8|IzQwZx&v$rCJUj8^;Ms*|H=aFs_Tt%xXFs0r z@%(`20G=Q5`~%NHJcsaDcz(i@izg4yVLV6h9K~}C&(C;%!E+qX2|T~zIf*A9&nY}M zo&r3Dc#80x#&ZTwF`lz{&f)nD&+mBt!1E`bzwn&LQ-a6Aa{*5&o{M-c;kk_G3ZAQY zuHm_k=LVjecy8gjji(GxIUW~JL}kGLp^oX~Iwaiu|Db#OZ{-W(@4x?kLg#gXaMH1a zaY>#4!8bhhyR=^bTm+_eo-f_LEJU`aU=TYD2H6nPwQGLY;usW~M0Ci`F3Zl2A>)KM z-pGGrLk!yfx_7Q#ov%(7!x5q)hA8-Gi}-^`Vqi!d3^bPFB$@~FuB1sTCHPv}EB!3} zF5Qx9$h_QIhG*se@+f(V{DHh2hnYF@_``Cs{Fz!DgWX5XL>Grsq*a4!*vuBk5a?xP ztOl;gqS9M=O_`{`9A&BUg|b7jkXV07si@9)Ky9veR7qHNk~(d|CKD5GP+ze+<^_?W zGN!183WP^itiGqFs}E@{wLf+Aj=rW%)aGbQwJ)?Cnx#RZc1f$KKcF|)JL)}kS%)P3 zJw07tt8dc@tl42}~T%wDCak`;J)wy7FTmciupW$%dgOoDlcjJcD0(_OX z#jKD1<(C`36myLmkV)VW7hzv0nS_I<4<3x>`|^WoVXNhasUSFqD9?@&gfJ20_8@-F zeW>q3pjpJ=iFGH{ERU$G?d0?LGdx`7!!5JG@?c@MK++<<6<8iD5Jp`G@kNp4!NMAm zpqEaHB_c?*q(`K7PfE{Ay^toks8g+xU0ocT0^&zNCBp`+8pqYb3_@>LR3d>4wd9~K zyCh>M&I3Bt!Xd`>m9ixt?L#yd$u7lVz}^ab_a2oiEA^BXN+;!4dFOeVfF~BdK0W^F znq*p>rkF~ua$32f5H}>WP=jtr*sccMkhfpZdZ&_NfgS!Q-(B}- z?fg%^dvG@lM7Pak+q=c1A_NKHBP0kC!mmhBS*|BjFf28&!xDL&yj}JT?9fbUue_jm z26ot@{Gj}*cm{TOP93CgJ5UF^cVz>0uzOcFPzSqbUGPLNF0zz&Qb#Tz6SAPoDTVtjz&8^g#k4jaV=PzSqbU+nDw?4E%g zsDs@zu)}l0AYrWF8Q9@x;dkMd;2GG#->;H(^*>G}YoY*kuzLn}*smN{{!}~zI}B7u ztJ74^zz)GqbA$%LPVi zlli&)$NUD~L~15Ul7z}aJ)wo*B}u{(VVyvN@NA(}s36u6p_xcRABTo}fra8~5&XRX zX$8RF3y@X-{Jj8a1;F16kX8V$$yJqyl$Of>vf>9?@%L0^H7Q)u!&-Hl`lFh!I%Dci(>Og^e?sr7!$5tsK21->y-%jTTR*D9IsJxy zuhGyDjCiB3F~We!1_91*Fia!YIBkR#IrYpIW+zj+Ly(6h<~nn`dC;`YQnP|p$AV^7 zd+P;jsHIpTYoWE;f-Tk$*00ui%e89SjqNy=Ui7Z5*(9H6uMI!jzuW$#M<7v;{-j4B znJ^EzBqOFbO2sF-Fvnf$e&OzLEw|9Uf7bF<$H|ju2t8NHP&g2xzW&TD&4cWvQOjLh2+DSqs5f!V+nnv|TzV9e#$&34x}5 z_C^H@l@r1jvY%4WT!D^CkP8JrDnTw3VA>~ch|^Ric!fXJAQuY!Wi{bK!M%Er3k4tR zK`s=uFoIkt*lsY}48{8a!*DXlH2i8Zz8}T=!B{KEg@RjFkP8JL*g-B7JmdtqQ1FEl zypT%f6(UMMFJ!n(?(ai4M79N|L2pInd&1=IK-7Ygnbf?O#0SRhFN zKef!0E(nogZ4sJ^?L->SGD9RFatKliVkHPt3ie14q!jd%fu!{L_vvs|uA=z&=`dUQ zNb&E}p|1L<>ffis8g;Ac->1Wq7|Y<_r^7z&7tOyzY!EghDF@2W}2*&iy zG$BYSsBJ-zQn1Q`Af+JIh9IS2j}1XeK|kbDI-UfcDBvMTDVX2_%Qc~tf_pd!QVJGv z5Tq15!UF@-vRD%cQVO~VFhF=+m?|(z!4U!ec^A|e*88a5L1&bLMLMj}x9TLUw?qe{ zmhnh1tT)5hWWawySTA^*2r7vHFJ6*LBA}@g3;}^4r6AUYZf-CH1cH=;ejJSC-sa|U z-XI3q>{a;sJfjp$;9)jT8N-xPaE}0Wg+~RNVMsDC7YVRN*eV|-{avDzf^fKipHeVfh9ITjvJ62=!Au2$l!DqS zumCwqDOjb#X7zjZgvuxdu^M#KUe?BFj8d>igCM1#pAIASxAl4YCwC|XXLJZs3MLpZ z+xW;>Z!k*1JtovOA2mCej8d@31QN`6z+{wyM=S`YW^A&6tSbMoSZYQW8wS{~+f!|p znsLOYS(6S+%^2?BqR~$&xa>fXQZN(qvjUWY+8hKa1*k>{QVL>u2vQ36@DQXF^b;UR zDL5lQkWw%~gdnBh9tnb!f<+PpDFu(nKw?xqO2H-)c0&A45$^nH2IMq@gQQ=ATd3CV*hB_U!>lvtBhkfcV>L03?PYMIH z*R`qI-?bImSK2P^hz4i1pq~^b=|Mj!R5F5oQdn#R{iM*;yz3`5Nw64fHorGX)L6NB zpA}=pTF}jU*&0K12^QJ<@3DXgdv03Q?MC4k#(p-8wBNSp*`I{<2YL1x8?M?_ochk+ zoTr_aoJ41W15^Y2t#imJa4tIc;2zR_)a~HD=)UTXcT?O&F0664x(D2oZV5WzYH^Qn z@Fe#?_^P5MmoTQtFs^&>+O$dq@>ev2l=D`YA{ zv3_JI0^T5-&aojueM_CCdP5N?RV!$9G;b&ZA#I_yTJwe?;K%xrp$Pb~e#FBLbSgrz zeq<;DbSmNvMWDC&nmN(*h9XdCUNS3M-cSURtoN*R%NvS-AL~bkBH+jRktII(v3_JI z0)DI?8Hzx>8(iXpAL~bkBIScB5%)c&4%$GrU{k7As)U<8vY^V%jmRBzx0NQHH27O- z(n*8Al_s4u_*-exNrS(YCY?0+TWQis16!-Hts0D#=vs|!)qt(l*j5eLT8*^Qq>~1J zD@}H1;9s7RP8vF@UMo#HY4Eqwq>~1JD@{6S@VC;WlLmh)O*(1tx6-7O27fDE*{o-R zzm+DPH27O-(n*8AmEL0I>~qnjjrLR2mg3qb=Pusy-=2=`^i9V~h7BtlHYJkyxKWDm z6%c3m4*aEtz2()byVZ$l9b-%)@-iJizXV3PQ(Qm41SrbYBe}vHZYk&ImjH{rVkB2s z%WvcT{1Rv@bPt%MfTCPIe#w8QL3q6^m;B<0)~Pb;BkP%Lng*Il$7yVu25g+hrfECb zIPIEM@xO9B2VV&|V+UUepwZ;(9rjAVJ#O%o zfJJWbm4HXM;4ASj;{3oL=SN-%IKqct388_|N_a--BfxNBlJLH;42>P%2|o!%0$dho zA`QAp#9?Bx2s6dS;^*Qw;y=Vw;sr5Mg4$A3sh!kAdPRCunjtNaFavM1^u2UK`b#R8 z?vrC=h(-I`%kmic9eKX|shlOl9{CtLhHlE}7*ZZrIxEmmA#scIluwk6%1$Lufiucg zrHWc#{hRu<`mY-9cY22Vm>t>KZZ@FZ7=KCnSC~#&Gzewh;NnUdhy>O}9RZ-13C`gj zIZfOBJ}zHfva2Ohwy?iE`_9sRJl(qY{SY;R8&VE!451jVw?6s9F=O~K#LX}QxoeX)?OmXH+qGs-&F<>S7 z&vui9Sh%)x=gvW!i2~vrDkg@SUwn&+UT)ZkfF3~@Wd3ZDK$hQ4-Xh^j(BER;H~Mvh zVkdJ7eu;Pe*Ko#6Bqnz+H~Eo8gF=`D2Sg40_#$_1ylFao_6{^>2C;5RV6 zg;_#ydJA>L;Pe(&i^1tF1eF|LOAu6YJS#&`$#GZ)`sR2~&h3fHd#|Hz6qyJ)4}`{y zT)81(QfA8N6DQmgKnyAI@os!rn$okU+cSLeE?np?1j2}@Ti31&Xl4$*IeD@>IUGIG zuU}ceh-Bh7sZ>d?M6zW%7}C5TiK9U zo`5>m2BDFYGEw2MA+bYJ%82r_2}C!IT9NA;5@#nZm_i=;#!J zU4^#%+dEQLFC}it4?ei@LD#9h))8mzL$@A!X!Wv&4I5&|yJiib5RL13-;FuA2fGpjuA=WqxR4dK$axKa%;OuDI%e6?g!HWu`Nns#3G`581 zT5ND2sEq350-^m7><`VgIOu}ymbwJ{Lvt;La-eV_ZXvgtqq!F6IUru5#(W%4b1mNG zLE~5QU-Nr;nrl%*0A6S2$onVUJ@%x zG}odh>PRGiuEp^lE{d4-fE(P_~$9t_0 zEe@T$b@JqKl2r{$E-hJdyw{US#OO2`g*3-|po1WkaSk~l$9udP!rQU@crPN}M~_9p zacQ?abnu!fy;dT;!y&a#*Qt1yS_DAXa#@en4I1zbVA7;X2j#v>p#&cOnb4o_)Ou^f zeL&5`J}aMAZ@;9@f0y8FX3Z*`m8x!0CmOp|OwcJC8J9vTq756|4TNliSD>9qf(heN z5)zUUwk_+mvf3=HeCH;XM~2X5hQXY@q342Hp&Fs-qa)XKAb;;2)pR9V3py=W5c(#) zjRC)@H`VG|o?7tMNbPNHvjKkO5a|%Xj~pT$BKVO*q(cNha)@+@5JnD#TSVF+g4ZI_ z4iUT-k#>mSwTSfX2d_n>Z$Ee~BJB`?J^t+N2d_n>Z$Ee~B7OV8YY}OO2rSE&z5PJ4 zd})hF-+o|^KYROuJ^t+NFOPkKsCiRTQY=7!Ve2PX^qw=vo&zYIZQWt`@b<$;%hO^p zW-D5q_V|VA2~i1C#cxG&x2VJvg3mF2oB5d~2_#2ux>{R88s(64XxL16y8c|eQ8*&T z9o=I^?@0+`B=}PDtFP9G@RWQJ1MKR`AQ7|1NOi`i@+tWfl~^$Hv<9O->iE$|IVq?u ztf%xHMgRagDfp`Q9=RV&fSi$N} zLYqUgHHtokrb?B`-zh&Sm6F~ZovhAOVX+!ayMv}$FzqgEhxe!5K{p-K?(}~~e?0j8 z@x;9V#J=EnF95MG_}vRLn)2;<=3bax^R$RUJ$%iMCr;{JKD!QymP7IT?aW%U>k*<* zqegZkKsorVMqRq(beSTz=r>ZjPpBLH@yGnf#9L0-db8vL63e3qU8RA~qvgF_ap&p6 z_l?mEwWH5>4Wlv>u#nm-R2I|uwLExT%n~-T7$VFSh@SJ7*j~COUmz(WE!DTW5Gcqw z)aoTk+8gMbDsSC^y!%+@x7#4u&zy+IyL6@U_3P(Q_2|@4-os$eDzZ`OWmU$Q-4!|+(nJF$Fe4U8HtGmJn^bSY{%HxD;G&Mg)^wz37k>| z^ZCMp&T-rlE??xO*3y3NXf>70x6opDv{GfX;?|S+2lvHqjyT&>C7d24!ZqYU<~UB#lFq{IJ|c?jjG6UzexKf0to}{FS^*J|dr$uglex1`3eW z<37r8Ws>r~vP}6>0dhYTDVLQ>>Vqn|QK6SQOeL2UyQ|=odO?lUYHRGSf;Y7p+5&Br zM$jGPu7YyyK0QW{)!AJI4CcXD9>8E8jO76g=D}DVz+fJX=O+0VNjL zwd_Z1#_|9L^I$BG>lEe@wr4m*R@=TQz7sCswN4_P%j1fO+!lYMx8t0*3P>5VZ(sX; zskOS*#8SPv@GF0No3sBnBBpKBsC}co&bc#aS!~j#P0PsyY*&IU;#}dnDs*=TUMJ=2 z3va#fLVtJiWh{^5FGjv9jLLMrc3FK0B-vrO?1^vX4;@hI< z_JT9wRS~1)@4CHUf;3zDNb=lXa1TD8kIEh77iH@9f<^Kgd8>RtJ}H;Tpwv=;@(?^6 z!aq+=!v&VpPz>qmb~@qQrS4k0)?Q1*)mkO+uQR8-)?l<04~@j~vO5B;`)DExN1ia^nc87%Ek&bbG_D zjrnLVM>d_!5uVzHQ(0LNS?6md3imk_s`Ro06skn{T?9%q+%A}8Z{=DQ_9|?81O4Cy z%WV=xKh|yD23l789$0`D_6_cq%R`3b4>?~88^E5&rcZA_eTw_%b!1s# ztjB{TQzP(4aK09{f*cmg8>U45apMpEQx_7sJ?=dBuS-N?zl%G7yT6&b}Y;It1As8>>)fgMq4 z5n5NaR?IrP@>D54F~#c_-deaYHIlGDKXX6(jD(Lu53@%P(u5SR|HVZ+;;XN|3Oy_I z>=_YxpmgN6Ww~dK7Y~QqG=d6Kv5O{Cr?`vZx)>|c{`N_ypj9E(CJnRjnp*{Ekw*AX zPQxoD3+w{3+QG=eDpks=Y>32L1k%!S(pE>V$(&zU&HA)LeG-O@e)CS&SnGxX_nQ8Q zu}lkgTltP@=9>54UY1#8UN+0ym57<(x;HkoM-UsjU%(HNUnBeoKZy$D#Bq$C#NGvIJ;2CY4+P$d%|5>KJ;>j zxyi0a%ZF3$1sDI_yR>|GlbgXU;5=GBlyewt%zLzaptyXGmJcMHy|dua@?oQ}Q^*rM zT0T52z9c4!9xWdT!pl$af>)*SlAquO#FpWAWx#a#LpekCX!#JOJgi_)`(0W-tWdsE zb}1e$A1E&0qvZo57cp=VP+Y!8%Lj_fr?mX1(@JtaiOGFB9W7C5Cz|Fe?&Z{sy%>8?X-a!@IEWx=w{!onMcBaDwfC(i0- z6`D0$YV0;x_8BbIztBncSyl5PGtPd%C}?hswTbF50vHaq5Ofe{JXepNe(OA zuiRa(hw_J3+%sGs&O`abcic~05$B=&p%*`lPv$+8KTwvxhw_Ivg&D#E!9)22W%+w3 zf1oUX59JSyq{pSsl85q#jd!->Y)KAJ%P+}^@&uVJ$$@Rj*^(UCmYglgp+o_dY{}V@ z{5si^FHXW)9qhccb7#7`WdZ>|k%~B5C8=n)CPd{_#%}$FO4Ddl5qPm_Fv2%anICF2 z#v$s0hFy5(u8nE~eZ2~VYdc(@q~D{Z=wv(sKk2V(f*&^iz_Zb zNCj5=d+u>w^ipLXm9(3gN@uyE|2q~U*Ku}B|ee&qF;cis+gz>X!eU2 z{Q@Nd$$s&oUx2Bqn5YV(q=%(8k{A5~OjX6AUjVs;vfn>F{yX_6xk&!2FFq~HGh8wo z4^ILS=kfahgh5nI42NJNAOYqe1n+m5C}jH%`$5Fo8sDql$~0wXs-i2!`ZfKiVh?}k z9rqm|q2MiB+AYZl;7a0W+uvT{YOtku(? zg+?N~6SPq?`h=FPyqGk;Qs&56PiNj7f$!`Ht$giF90QVV$^ zK!1QxpN`MVNNRnlb?d5Gb zU&H-s%f*Coag8v578AGUIczCXlgkqjtX)zy3+WPNi3l%)2>pJ&iH^(W*(v&>g{^d8 zku@x_20Sqs)q;U12BTUq@WfzL3kGjk)2$D!3~Q4`wP4_h!KfAtJTcf=`?_7t0Z$A@ zwP3&^Ygl3pu*e$r1_O(%VQ(<7$Qt$r1BzU9FtErP_67rstYL33 zu*e!l(LB`USuDGEqzvwQ^l1Lk_-;5I9Mt2dp9+79mljH^r7xbrNeo9AjO(Ps5>aj6 zju`TNC8CK4c~{8Hc_-2XEW9El$3m$RT;5y!ut#ra@&Ke6N;YkjS_v zB!$0RTO=mwt|{+qEN@e;_3PDtaN2hxwr?-p-g7`TbmoxpxK=7HY<0cI^bT;}Ktm7sPH{=-vq3zK#A<>**vW}ZH z+;Gvn$6_5fX}BT9T4b?~n>5_u@3=|B4H@<(n|0iz;f6L&7spS}1i~`$(=&nKGyT&+ zU~m&Q9Rvn9Vbei~t%s;yO1RWyWQ)Z#eU+eak%V) zlj6yfWRyGqG?ClN-Q^+jIQ;RG-#++${7SU) zgaTcafy!tsZ%B2Msq9wZsB%uZq1>xBR0TC&?W@8Fb+S5F{aD?gk^<(m3bcZ0p|MC> zn58Yz{E@U!M{lOL*I&?w>WUuH7wWKD-=g~?X(7&d&hSUl!d~NN!yict{moIPKav)T z&1Fy=kZ!NF{gJfL#A)mJBWZzT()uH5p{qO4^+(deQTLqd zkEDeW++@xlNefrF%Dg|47H08Fcz+}iNTzAehdjWNOd1f!@$_E(=aFjpC-{3v77mN@l<5G^A zy>L!0z!jmgSWj#rb`m8qL3~SuS>h6Low!{*DB5DFSV4k1QZuQ&#Ok?)60F8W+z-;P z(s{|1YRZjeh?Ad_2gze)f)HLQe=WmanPlI2(Ra{aA=!6c^c@r{B>T>bzJrM>$-eWV z@1UYavhTd;J4n|^_MI1f2TgR6edk5rLAFk^?>vSAbTtMVqm5}ss-YX1I8uS5#yR7L z;Z5jZggM!qYkJXl5ROZ+yy!ci(LY}F9n`U#+3jsF`VJ_j(Tl!=IEQ54dC_;U*CE+= zo^%xYyFuwF6uUv`C`{yn(ov|$2c@GxwyxgN^?m`G2tny6kTsg0p#WXQAVUF;ia~|~ zjF5s11-K#w8455<4l)#=juK=jz-lGPP=Gi!$WVa2YLKA-{k2ir6zv0Txn^iN+F=cf zwQE{c{UN=jF6v|u1{3u;Iva!)>X&q=XgpvvH#!X11%PsIJnRkl?E=It z0DijwaSMRoE;Uuc2?sM|d@6Bgw*yC=AVUFy%)iqvTycX81(=0Paz8@>g3P~#Jgnw} z3%8QkekaLWg-Jh zlHZdrq|0mNZSwAZIK!r5H5~5b$l%Bk%Kb_ch4B*S&xX-%%-KbHw(U;Ktj{664+{3QFgaa?WIPCtZ z?h^etnQ@*&neIXE(mj4xL0Gy_$~EQ*>L-tFn@&I=OwxA@@ryGppWj;W#*>K@KfjA%KsZogDrG)}k34cc8jVas^o)E%>W+HSHI}177 zqam;Oy$FZJU&L#oEk=uifFoE521z_SL{cOS?n$+!cSX2@H~zT-D~HRk$o=K_WH=_7 z(kfY#bFfm_P&z4}uc|OfxWCMc+P7<;QoRId0FHKoz736PKMJ>nJY3D4lTfG^`^`=%FdHt=on$aAi$>G zRqd)(DHs4h-~ajN?Pnu_A=Anm`SP1~qiNMqttR4jds8N=R;M$C3bU5EZ*^h5UxaZAELb*dxM{a1 zL`;PAG)f?}W3xxu-c4@T)cNzx`4|VQziD^Pnl?&VJx&eK-Mg0CVFu?W$&1t47B?-r}%0iV>#`(jEzaAKsx=qD?n2ECKCN zNFjDZ2~=rj1^z=Tnpr)dp_Rw=Tzz8o>bKJ3!YK)` zHHLbtrxPx!wA=u<8|=0QzU>AsH}?FNw=yeZQwCZM;`PtB4%{Z25b}kefq> zgrv-iMKzh@C?yG~O*Kp`uE0SQfl?cJ$?kFE9*zr1p`74XU*&vNkXe>GExc*??RYB7 z&Q|&v8x(Rnd|_-hKsWLb1b)j1GU>70#hfrxi8bFdMx4RgS4n1vkmT|4BMWfj6q2$r zqkK!ezjL)kooP1xK%v_~M{x3k>}*g9=i?8dxz)*9^eaZu%0p7Hjsa+mv1z+SauS

2^@xchM%)N3&BJ52gxGgO7;34!uS8#U`r|dyEy_zc z4#~>NGTK$Cu#w8Zr#SGruWx2_CXW%!Xd4LbbkKI*1139ygU&*4LF{>zp(?>L_M8di zs+`32;Xg1PMm>-d^+nq$1lAI!@i3n+8${@U83m60bm72PDCLxLJHA@-ejOKi7)H95 z@ND3-&juv4S-XOH^N*Io%fe$ngBSgAw^Km<%A3Mf=>s8H29MZL9w3jB9jy~= zm2+js>*Q#i9=!bVkq~muwrRt9gsUBucW32C+mFPmkcbFSX5@v+Ax50?DfXEf+(bk%A}Ta0WY-?(IqH$F-- z(oidfxs4&|2QkM{$-JDM8&a`ia>WsYBg|LL0T;IDzaON=#gKG7Zn1TEhyt$I%KC}Q zi&xBNe{#f8hs+^s2d}L+z&igqex0brzTEoZ-Zr-bnl=q+dOEXZ>}~4< zEWWPf%2~M1HR2}l4((!;mLCa2*2aZT;VFu{%-DE%OnB*#wU}A2)Q6lyL(=<3r&-2|AVQaORT3DfjLYMENtK_r`de)7f~EEwLM8#;J)oppGHg{;7=taZxv zq|)T3;vr?V27i8yg4df5G@hh1DnL*cZ(bD2+s`1{1%2$@!p0f*W@uX?U^&FdIhI-6guEJ zH#_3uo{JYJ$Kma8d&-9sKm2eqN_z2&zTBSht$iV`&yDTLs1w0suD!f~e_PJry~sWA zNv7%X-d&mShCEu4oRZHn=OIKv)*E6GZSb|X!ooUk8`+;3Z$j2 zk${!+x%Tz%n9cSZ>fe<~=yMrk@_#dYExL?8Y#PjrW&7COSTdil))5FmHtO4K1I{s@ zgPZ&I8<*`9llAGi53Q>}@vHjvS&wwJH$DmHwv#Vejv^p zZ#TT~5>o|RyWA<}aay(g8)LM;v@QF)${!i9 z&^W6jj_JL@`me@}z4Z;WmZxj=OpmqvLcZ~t2{ZJsj2*`L_bQuznNh}?gO@Q={I}Wu zPmGc?*rtzssLB`&|I)-A8f+i7j=KMWpLEOmwbgEU; z@dbrPSd)li8%t+&OB~sGCAFJt6Wol6M_H z>F2{@(qr*c7@OO(C)<;{A8W@)R6WkaS7N615r0lx!%wkmN{u9VQF7v)f4w~bnHuS_ zL3pa~|7{^Q$1=xts+x$Ol+$CdauS;xJTw~bFJW@CNpS(OIYBru8X+bQ>>+<3rpO&g zEV(Ta$0hrvpJj_QuCcjP>s_n9|@nS5tLuCz&+Ce4?Ml}l3a)w%dX zjLj|G94Ajg2p>O6Nl@o2x25WGQ@O1SQSsB%zf{6;tyX)gu{jf>qC0Ia$7&~Dicc#r zQ_E3a(W2We6;EluX*ES?BsP96Q|+L)n?6MwtKU;#lAf+(vvF@r{dfJ0+AWX{sQo(o zBYqVbz$ZYS!Wv7or~bT*Nv>$)xs`-e7&4&3xO4hXMjySKQNf(0PiSg(@cc<*&~HdY zdF2Io;iVvQQglR_@s$~8Y%;nsf13RR`}f~`JIknNmFw5d7z>75eUuj&irlTYPFTej zc*B?8>?L@^m)`6pmLNT*R#de*rq-YT{<#v<3NXfqnVRLxsoDmWd7PTymA#84GT`uY zefV5(__>eqx%JLh$f&RjPm9#FRjYQbx>hGO71P_(>-5pF&5zHb>2=!jjwW?<#0+-f z?@wYBe69AKR#NAM&M&-hIMnk>?A+KU>lEEcl6IViaLg*aWx$_84 z;ns4F|0&4})V|OwD=#bW%llt`xgnGWJZ(C+X_Jb>n6!d(L%H)4xG67TMJ6?E-@b?Y zCU?S{9Qyq(1dUF|S!in7#EAhDC-XC{CY-^)-X@=|h`2cRC)3N2Yl`XkyS;?1c!@3{ z9bRGBxvRqSV(^fQr|~*lZ|cwi;dpJ2RGTd;3lG9$e`-t?|Iu5k#Y5r*M^pI`k73|= zzFxCs1Hy5J)Ot(>Wt0T;cez@6M`$FyDD@auU(Bu|pAqg#UFB|K)8)@RYSL^Lb+L;E zPjdLzj^mSl;%L#37Yt46r2I>v?EA&jS=Qp2%PRx-HB2wrZW;WB6JU%xDp;G*BWIZ_Ul(DIa?L6bZNlS%@T)TjDFe@t(jh+7K&)ABw6JX zi;)RpQM-EkZk&#x=r%AgI--}pQ{SyYMg5}rs!`!e9lfW~Nnd8bM&k!#y)@q<>2SHx z+=Nc%zs#YguV(>A%=4yy&*H&g>xYkVNCCr!bsQFJ%`C){)2fJ7;jl0{hVeBof^BGE zN7%mR#cI2Qr+IN7e^n)!E5h&Q{~Z@OqXau|P<>DJ>Md4aRb*Afq0Wa6<&_~!XH~?E zqLiU($<)l{C6tlPzwz~Rh)s$Jj_$;iYzRHG_A<8kUOKQU94Bk_^2*y(!VYep{clKT zFSWZgICchG(ju)>4%W7k{@#(v{K%ZCG@#+a`{a7bF455Cg?-@MCz>(!sqsS`$a z$*NmF;C2hVj%-LN92$G?*u0#fu^W=AcfZJE4i;-W=U7fzdum+{xdLR!2Y+*A@fB^9UO^)TDh0Ff`Z zGDEBGXblUMHHx=vd`|sS?NF{J9UV#?qpDh~HOS(?J9tJ~nNm@$qrx!N^ISiipw3d~ zNq;#AWaMKUC7g0oJxK?mF8V_kfvAgq(8Z(2ccTL5+^#xV#|92$$rJm;F5}x;>x;_M z!-V;XYe#aYcN!*m8mREMB#7C`dS%k+)i$2C4!zhWv3Sf)h z5^g3Wl*GjqEm*Js*T9+v1Vc&0Nlr-|*7TyM+0;nK$Ec^3QWA%2ti8nt@w3s;dqzT&u$DUtZ zDQ*<7B^5o}ZwAqTvBIqsYq7Q7f{(O1tfNys!~D+NV@ltA5~s!`aoGA>nU}UB0LKF( zDwM>=yb=?0Y&A_xR`VT3S2*4%0Dt|56NZL$>z31PSMiR30r5-mf6$~!VUwck;N1v6 zR~7qkg-OgjoSjfT53fnbOXBdOT(!cEfTc@wmbPfrXWj92rQz!T?twkKswv zdiQDZ%(yc-wC0lc$Z}o}oLof4%=mT2jFPy_wbSD9mIQ}mD#+yG-ee6HPF!Bk;3Vlt z)n}OJnKln|g;PS)A>asM*GQStkJ144W$8g5Y0VoncC1q6LY2ue_(H84HwI<3j;pqL zPV>Xe$KrDFSv9t}Su+z|xV3AKi`%&I?~UCnOo^ncVO<{IIQZ5W#6MZjW0m)|xQHZP zI9M4zvqz<&@o`ECWCUhpl%%(e?Ep#Q+m3 z-Mc3r!2^*Y$W>m%wf*zruSUys>&8{lm6*~L8dX-x$L&*LUPQIn%6WsMQx4-K%D_u* zmuqF$_SdgpRDV!RyU5}NnWFWd$;P6VH`ifqp6T^tpe z7f$n*H}nw4szf zc#R%9wd~Vp6o<3A-Y#rwlgNI{t&!1q_nNRP_wcQl=pE7cMQx%adD3y!vywv_&Wl{1 z+VXzOmYeUd*e zRe0&aIjQeNy5_cTAJE?MntAinaM_~a(rMYdih_xXJ3n3M?4oED1t(5~otPen$8K-+ zi%VCdOZ(Kuc3MaZe&>S6t-!C<^tc0RwwkZPCDqOCPV#oOsH*k*d(YfN>3Y2bI-9-@D|Gc&bLMi8E1 zv-P)ouHT-Xu_84HhXw2OUv($U3BELExb=#)?nn?`il@hw_eZg@e%0teWv@Tq#Y;(V zy|W3F28}lJwQWjvoQ` zR|vu}X6?*Ay<2jlm_8g-Wb3dvzhbxQv{1OnVV8`&4(ZG`#?d-J5>Flg)H-zT)v!)O zwC-K!yK;B=EnI_F@b5ObHccTTqv{JanFJ(B@}#J5$-m5B6s`*uM5rY?iux+TcyYLp zCgRI?hxn1OQ1B}1@#Wh?I>q;qyo!48Nr;_IY4)44S3DH#mDXt0wEPVz;Ao2cC4tj<|kr=##I+FBJB zCE|MibQHcud*jq`5uSgiqX@!0&XWv(kK2yP@LOst0sNEU6b#RHlHnxh>AWm7lntd3 za8>QT)=@9?>Oel;>Y23Q^LDnb={fpI-O~n076Xme25&?g?;4NW0LO&yj3Q&7@gLd% zN&anshvz!+2*bd~V{A;h`G`dpY`kMREV67bi|jAs9{webt5sb}-X`iC|u3JS!OnoPqdA`xHY|ibgv4uoP2R;+w%HHjAZI&0nlT zr2sFMqB=`diZK@WuoO#K@`S)U{CM6Gg^(vCi-SM;a=xa}NO)0jJR$IrkfwhkWC}kD zjwb}Fdlv0c;+vx52}xQhZV|IZTB+X_E57%m{o{||v6kAkYB|!kmnbSw16kw2b<$JEYS>BpIGCgKLR zb%c0R6xYcIC(w{72v6D;aR=nThatM8I|ldf^~3rvdXm3$rvH&`H@9uOl~zBN`o2MUhV?fblN1ihNhRfD zkw)qd`swlK@X~?3F18Nfh$SBH;-0qeY4ft_KpBb22>q-PmKVxMOh#~YwR_E0b{AW) zr>fu&WqjKlXM#VJk+$97g)+WtQ}rmv03Vd`noZRs@P{(8Tx}Nop^U_2gp=GA)#R%3 z-kK5kLm8=Nl;jU(6#w-TVrCt0DUZl0qNC5DNdNFP$1xrs1W{6eG|M4o64T$qO`(Q}%i zIjG$I3hqvPPOHy#%H5YA%fg|fr%!eayH4@aOzA(IZhP^gSY+IEpKi5{nWm@flqVlG zop0%r7IvLTh4!{J&XO%;PFVj-*J+RG={nWbKeQLvs-0o)voVbQZ@Nz7>@OH6FYzn$ zxa$B((I{nji`lsupb9$uSPyeUu^iS96pRUtGff31!0^LQoFBbgOC}c+Y zr|b0pnXVJ~$7P&w?c;uvQ*Q!azsadLfv?}>)SJN9Z*uBQ;4Qg$J1*esH#r>_@b#OV zdK1*vy!|Gp;{xk6Z@fXNbBZhVp(s3g06 zv9LsT`C{io6UFU|h3$&l7Yp50w=Wh>t8QN`jBt43qDfJ4IxkjFDYh-=#)=j9kx%r<&&D@ zLKPrqiNCT0$XVjAECF(sOp@ow%Mb}fEHx;U%VeLjWT*lYloVyLvR>J#98u0IrI_kc zL)FG=I}Ah&R>!I{R9K{@tJ~BAo{>LI{K0?ZPZNK5Jo4A7>GkwBI&{-x^x^sx{S$qK zzDdv0;e<}`$I8ajMoZ&mqmKc@j09trvDEm+*lqk|Tr}W1h9PR1-Ymp;6Ozm{^DA?Q zdB{9xQqUV}T282Upyf&KT0m6OAFVTwl9BZ>Q0f_?Qw(gLz0%%dL$;l7U$QCnNL!Y! z4D@Ba#ya7>9lAFxazZfrS>2&~LjxniaPZzvDi*dHxrT%HcIe*F&5U`JxOV8? zaKbFc1XpG2Y0IH|!!V0h1xu}OEQjt5xIMHTythO5h9o=9cJSWk>_6>t8)`C*m=~EI z%s^%g^AWRIQv5Tg?snf^5wV z`hvc?8}tQ*x*PNb6O8`_^yNlt&oE(;=>~m41IrEif~}St^aZ}nv$J@H6Sf=l1;ZFO z=nJkhZqOGbv2M^8)Wjq`h4HL93-T)jDXsw0E@e8YF3+g|2o;JE#4rm1|H_Z=}Dd_s|FG zWAu;og*rH4%rlr}yQfz->KoA3h%&rb>y-xXO`U?qZNnR8hrVW+){RZ|luLu8uJ}g&P!?*-)7U#oAV~>J1Kt8cIZh*+_?Gt;0|G=JhIk3iWU{CXU zXe;^#_B5{t@4((G_J+PvoHR-DiM^pvDw8V8KCw4UkW*v|G(Hx4gA%GVR(xV_Sfr#Y z+Z3PJ8yct)>Z__x>15lWd>Z8w%|*yCUNgd&30AY1Mdoj!Y>7z=pEaBcO;7xdY z1KzNebJ|_rfH!pGWBB3x6#f%_1y6wsIKdb5fAN(CYCgU!^buf~kRZ$wXsx$f_(`}Z zWYb>HyVffK85bFVq3qrwB#OR?_^;wE5rQOVaV$u&(nM*t1fNS(Vx*4m4T)MY;9rZO zRt)&pVhDW;uPK9+_m$}wLR+hRr|eh2JJ9ydv*A5;s`{zAO4TrDO)+b9yH(Ym)mm%3 zMgZl>8horR*S^*EYTgzWJf*kLofcNSK2u+!V{^$dR(XY0(B5#2RbF8g95f1yKa7Wu zgG%t0IokZt^aYi`e>p;5AlxxoqGyR(XY0aK~>sLc5W>WUTrcTfv)Bm52L3EILa~8Ai;b4A;Ll2*n2eEH+wCfRDwd@ekQ%9Qd=?2*n2eEH*;1VVD1X ze!5?uAN*NtRM3E_!l%M2K@)NW2jL1;#b?FVA}>aZ?~0SLa{)W4fUjYmM)W{l?Em(iP*r zL7AO!^A)rAnM(m8T~-)D?VhaC(Bn24RnIOdtS6ph!<}1VFqY zdf(vm1b+;G@D_Ct0P(&wU2*^rl-foB#C^$s?+LW{bN~=1Wo#+P7ppGB92+!DK6mc# zb5)gANf=pzkbNN`OKj35zMr&YN&J$ADYKPDA0wGzs)Bm2Rr9=RCVIPpznY2Kk8oUd zzujP{=6<_DspkK78}V3Ezq@h$zD`h@(YZuWxP$Tc zALbE3K_+7bCfXXN1R+9UG}6Y_rcBFNT|=gLDlVsgm}l3l>3|V}FoV#b7mt@?1Qz(6V zh4KN{$mxf1K!#G-0ateyUA(ZO=rXQ=yN3?8F2MpGBesaY_+j3Tq96=--^gs3yfL}l z9B7qyxYja)Hn>E+{oOp!QMa#WUP%OKcBa|npRKC-<4}G(~9mF6(tu_ z(D|u-Pd$}U?p&5j;0}frrc!DKWDGx36?Ro|5GK^Nr*F*5H#+F!&C=nQ@fKLH9>Whd zft~u=jd;a~&0Ac6XDl>g0sk2bjaa~c#zG?&aLrh7#Dc8@ufEK&mlbXk5~Lr5i;;u#Fc;^+2wk8o z%h2+?@~(O0lEFj>gn4k=6Gbn%5srzbctZ?CP>(}ygdvZ!QVzKhu1U5OB0nd4$&D~w zR^+wvce0nqGjEc_df~F%ZtQdi$cl&mvT#U#>}1_ID2+p zRDRB2Wvnt|Zm4zs2c>K__C4~VPzjor7qun1kFr(CRZe~UdFRhR&x^uP(ki3}j8!_$@vSrPhfHiqhG+b?` z_0$G$E>oeg8mjeF@8M&=g8rx0D8nXyGyMSWU^J&;CVi!4tfv45q(`h+`3(LiVYaVz zZlk@Y@1H(>E0;b77dl_KFm)cDo+H%fw#pc@rULb3%zA3At#41!K=I6lEcJv6#VQSj zy8Urma})w_)o?2WV4CSx2tYM#y|%HsSuxgdixdK|!g4DFkjCS!u{kX^a1zQsjSuu< z+zJ6W$G8;&Fotz21mND|;-%BO1aD8ktMS=M6_|D}VW_Z0#Oi&hNaE>b@nKs(FaqlV zBTPjd;1d47a^qeQz`;HHXwTr_o_(}u@I5g`OU;yVafx{U>79v1hYY=38ip+bz?0^| zIO*Uh6mMbC!%p(t=d!XoX2ohP+9DVsLt^9!r^k#jo|bz}#&*Zl%-~+}Sk&*BuwEj0 z`O4=LbHgz)zgF7!!PtFc$0nodNAvgQv6&}q{cy{iZ(n;xC zMjYspkb!@|40R2stG_JXlG-9X5z8wDX?SheoWxuV2z{>s5?rjOUH62J|)Jj7i2E z17R3gE<0{Op;2a3H0zknO{ZK2zINH8a+%xWGsA*KmP4gEYhAS-SpTL=hPP*bi%%N{ z+!miK2HX~(J}eAl>+@~-g|&Z69uvPp+xnzT-Ye7q?yq0IB@7e3)YS;yo`N~!&8*4Z zU|Vs}g>$12;TY#eA;J)zP>6fjW2}QhgljyZ5T6sga`Noy2%BFkd?(;jX6)Is>RG^# z&-Ro#YzguoPMt~)J&=4mvX1zm`P-E@;N9ILz}cRLWd)QP1Qb^l-@}*EL9G(^RD0on;BD{lpT3G?O;Z7#Tk@ev7>9Su9W|=ikiFuPVK(08yBlXz$4c zzQt5S-;~W`B)F?Al;$g|@pO$*$sPoxSN69n1L>9h?aDxUWq-RekY3r}t_+9tbGpA> z83r0-41c>a{BGPc{O!u{fjQ6gw<|*x>lw@6t_;hpjg~jj>`5Otw>`uK+gl8ou+yHx z-W9I?jd$sSvP8UoTq(!(hK%$9dT0*e3$yTV^|QA1)xUUA6z@*1 zfPZ@)-*K&dwQ5DC4d&YmuL}T)_z^28!*Ay;zQM$vP2(e^Wx{c(WJ5%pPe;wgTGctUI;{Uuf&orry_f->v{ zRg$jnc{3_}q_pULx)U5kC_s+zy|gzjD=R*0x}u9W#^4RF`wCdff7AZlf{jvN`8R=f zs8HoYzbP#aX~BO=OG8@lpVHEh7W}8QG^E8qx^GHLLt5~k($bI?{HL@uqy_&eEe&bG ze@aV3TJWFJ(vTMXr?fPr1>cnRh<)CUx>g<jun{cTz3+}_)j0|_N?k}Bx z`DOAHyp>F5-)JCHJ%%#PL*+;9_~`?7R^t}qzYpJr;ljV`@0N3rEI|R^nv&OCG3CPkHAhyv6V88pFdZuAT5aSH?FNW(fZh zhIY3pElx)k>3PD7@sD)0wD59UtU3%4e(kv>GIU>PC^mP(>+`ilBD~>Du325zC@I<&yK){(JJHaQR9N~#~}}40ADB$VIc75pRZsjx{~R@hhehm zr4KvsVW?zz>BA0u7?xOG`mh5ZMiiizKJ37U3%4T`Zg&0Sf0rXrV~b6nQ37{bWaT+_ z8-L?>H-yd@Qua3)BqMZmaADzpZtldH6DKyrH&Zn8LiLLspS}6)v*VbfFH%$Y4hFa5 ztKnS2>0jZLV+eEiON{YbK#JX_6Pq@zTCGtSo?u1X-PhRZe7{QQ4Q1qGd2mD-8Fq%p zcUGs4T8DJh;ccpg=T6McE#Nx8h)>eFxd*Y`TZ8S)kBjKrw_{(NVm81b#A!}?8qV~O zVovZ22PLql_@(S(9;l4%A2Wa~!5uRI{OfbY48Y$aPB8=Uw}?~B0Q@cD6f*#Si#Wv$ zz~3THuL5LOxnlqo+i*3P?ux6wc9FxzZ!h(`6eHr&6Mq0I1BP?_mq_p%GEVD>!i%-GU7+YxOL z5{ieO?J1JsxU4X|*MUm6!=LFA8iJDzi*EO^M7&uT5~`|dQToD+DR#+(C1ne4&FfOM z7UvBi_3OnI6|KcuP)H~}$l$jw$8B2JU1uwBwVvC^0YxJG6A|z)ekkvsh(JFUMk4$Y z5ik~yQ~yK+IDJo_Y#io`ZrM20liad#*d)1S(d=n@5Np{P|!5KOE)MrV5D#Ud- zt`%xM)HgpLYahwL+r>{DKAGD5X-E7BG30r^Ny0s{D1^%lDh%H@}i-XX0q4;pZ zIgI0>gdw2`H#`!_V+*UU4;dPA8J~*VLs#cu4gYw@G<>?QGNcn38DSY6)9`Za{K=O} zCvZI5F%8ee2TRJ<=iv+wdi4tH)iDhpd8zgtb4hU`c3C^7;q54-xIC0v@x&M^@0f;P zZ@?!&@Vb1YnXSs-U3*Gc9}^y!_=NvsDf108zEXPLydpAUc1%O|z}#XoVx}^8tnJL( z)&et|hzIZ5;RKE@KYxDJ`3<31LAsH47v$*t6)VgYWOwYCHfmJ-s0*xBI6eeXIjWqT7Su^ZddQ;k-~P z_&mQbSR5<*dw$`n_(1gc{5}H3_&mQ*O|B>VJijlh4_3&VKBTdD#foZ0z+dbJw2Ht% zT)Lzt#O0mChd~g2$Wjx=rP&Q~o12IQU33b+`6gq&OHLxvO$xmMig%7I;ditw_<;AnTSgRax>$~c>#&*a}b z67d7SpbWp!SIh~5QIuJJBQ+j>y${QR%Wq(vJvz5*#__zrcR{omIHoB&_^@nF(fA9E0`SUEujI^%0DNmy&7_$|@Zb`BwlygpYJFm?FdjVw zhdzGy{cqg6VH7)!ozD_3BbPnJ{>H*xwi-ttjc!~FH=LWofkQ3L;!beI++SQ}9-ii@ z)!c_4#wYNz_@z92!}|jpn+niD=q0=(j2DuGG~p{@hX99!bHblOxlmJVB)%y25WxXJ zFBI2^nc|OPioA2Nd{3!ioJtln5kH+?G6-%u%FK^~=g?`q@LBZX{kai^m3>ki@-G1B;2%UEBn8tdt>XJ{wC zip!933kt}z$kUL_QVB09Ihtc>h|dhd&D52cc^jO>4OG_;=zTROar2kn%eelIG2Tcr z=H$=}#>USx;2a2o@FO%EL(kV@qH=H*a>*z=d?sgg4(&W)AGr+K(vXn?~`kRWd|@%GCsK$$V@8pCF7H80mC+A zUtoQ5El}AEb|34LYXQeaa{V};Tnlsr@&C&C2Z-443lj`ut7xdEgFuhAAo(mqOOCRtmtG&i*@G7gl#%k~?tG%of@G7fI zCC6Bu9i zXe_FC7hX`itKdZ9>#8%=40WHHtiw^&?No$B&Fxf#Al>a$EdP}H^nhz_N$)bX5h0NV@_4l(beiyCMM; zLwFKZ+IgOzihnjXZMmrWj;koA`fhvBaJX|TKh_90)b!hh8(bh?yX*hSbL)(FcX8tK zhP#{KW*K_uIJdwT{PIRk`KC>2-hM%BCP7DRJ^QbV;IQ!FMWY zp^BC+Z&(&ztX9{6G`;@eT_8=be|Q(V;#Sf>ybGl1^$+g?X?p#`yFm9Pe@icrrq@5b z3#94w5AVWi%N^bYFZ{!6>4hxY9o|KJraQcQJU;-50eOwCR-*f1UNBzbu2icNHX6D0 zc}!a7@pxO};;b+eVoOMp6FIlIL0q!u!Xb#+AkiR+nL-P-V%;muy z2B|BYZza6c1J9u=)uN&vMwL{c_Znyt((reMaJ6HSkm%_-`|4srvNlp^bd`~Ezunsh1rrjGzxB(`e!n@S?bRz@RH&Vjl%xN6a*(U3jI}g zXcS6RcW4wQYwpk}RMOp{QCOn8L!&@39RJWLY&YDYQRr^EL!;m(YV^argyjy6!Y#`k z8im=mJ2VQl8Fy$D)-mqTD7?hFL!+>tb%#cQ94TIzZw_~o17y3oLZknPd;byl`h`WI zL~sYCfYPG=K`EfLs5dA@VbOoYz5j@N{}K1LW_VnzyvzI}?)^vH%YMqPVl_60J;{Qz z0(+KoJRt_WVxR|$#^_~juF4i3t z++D1XHE?&ap3=eH#rj$YcNeR@0shx&x>Y0o+rNwTmI>}I)@2iXpgMYNe=xVu=N+pxjjV;{4aQ>0I%6`qMPRixoBsj~dE?9HGj$S_M@Dt{yI zmc0u>sHHSjIw;-@dKzX7l^x0<<(%Ry1RJUFqS`|psE$!TQWvUJk%k}DGwSc^Jsh(* zQx+g!pua8y4ep5#zk!Oj)3@ z+0N`~4mQV{&XfhVnFq|X=2i27=}cMRRm)NN&9|H>3!Jikv+i2e?0U8{Wr5+gcg*5U zS>P|bGV?S;#8hX>0<#!e((Pt`VlFaNk%n4qQ?>)!i+zV3&r(GizG8QBSjxe=H28O0E7O}$K0@Ip-;rfDt)JQ-g{nkv%Z-;t(@GN17_q z2*34pq^TkeUZ^Q`q^TkeUZ|;;X$oGbsh4RA1U2<`q^Tke{vBzmNP~Yznkv%Z>PY`j zP2W*WD#`-?jx<%I!M`I-6>0GANK@hh{5#TAk%q<0dggIQ8Y|Ks*QK{3O%-X_#`-$a zRFQ^PxdEKFBTW@)IK>h4*s(fLMH>7&(o~TK|Bf_Oq`|)PX&nsP(zDgX5b(A^EGG(LkgK}IcRLT?} zZ9{XllS&|ZvZldebv;_sNN857f)=VlW6jfk(8g*rv_)FF2HUg)+F9+Y_CO2P8|V=_ zys8h-N9oh_`TA;otDdXFDg8IyXE=^A0C&ciK3ZXHGCTtK6z-H?rYHyN5l{9%FxG zFSOU#nYiGv&)8JJaeTv347|yVbSb6a5_6lW!a9z~zHA%|lUR>Zignb$Wh_+WQ0c*S z;{L@AxG0I1Zr&FN7 zkIEV4cjcZ^U9GRSRijjRQyr;(pw3fQs$0~53sDDuh#O|mCC0F3}8Kd|4JrjMw-yi z9APG!bImVI>TTtj@T+;t46^E4t*kBd7 zZTQSyXMc~?z+dcZwrz(n@Er3J^BOaVd7qiikUbi{WA-yYGgp}VObwQ0!w~|^_GjN? zr#^l{Jvhl0gkrt{nl@#d61BGgw`vzyuvm9f0QPY1rU1ObJ57Pl_;oxr1>hIn-4uZL z1#eSezd%qixG&TYSutFEMeL6)fT<#UDy|YWF-JTpmWX%6suDaawU&4(T6$M%y_HT>u_3#u`yYgRLh=PY~P zRohK(8yXm^q4k2*-FnL!ZGC7hut2pktbNvL%gYD^&W^PE*(2;kn|St{ZP4vJ`&avx z9mLdSS~1}ju!VhzTzC+K%g=B|^!zC-VZcoqYr=w?G`5`uH)*Up2X4~XX%5_^u@OAD zNn^KoAd{Pa%Ng9HvDzXu6WuLm@R7!xmNPg$LSM@n9K5ryb3l~iyqr)KNAW*u$+?#h5Kd=i?zs`;Be)#KD9jU<8?(l19$FRVC}J} z41dE4#1yjY$N!lP?jQei47h*%-!b6+@xQ`?`^SIsfAaj~L5|AIqDB2y%vN~By=TuB zovon|3*-G+_+zku2m&dX`!E1AFryV!fuj=P0(%#TJEYQFEq*F51SW^Gf9VhKdHyh55(*}$O0R|Nrz@$@&@uW%M zg~HcOLNUl@>p2*M^idFIo8Oy<&0oxGrX!Mpm#o*ULDu`$bW5?;THjef=JzX>$CBbn zOG1D9J$tJCslCe9>>T@~4JEcm1jGE#o3>_q%eF(LXXhU|q936)Kg=B+$fJN5H{+x8 z$4Czve>(VrLjrhMf9@EE1fWi$#rrPl=CChre(^;?+T77ty9b#9WEi^|bWwIl1r6tp zksVUOrz7&q%SL-h1y!n)&mHL@6<|eb5GF5(%y0$!>_ze)lP;qqVeXh3NIR_1xk802 z(^6AY=f)*uz*TvmJdgTkcrQgJ;-`ri9j`4n5JB^F%h$hbE*8jL`(WmS)d%0n`lqsALuLFP!ZAzXYkKhQ>76w_ z`1bV9njU<6dS^`!N4X1}v!{2~^xz&S7VzL6D2^5iy^_=Ce!vXrgVSmEQZdbp86)#Y z3U(Hx)gv1wr8vL;KK^^kJM2xvjON@pn^+N8`v*^k1ABLH2O~%gQ?RN8iFjh|?S)P1 zxpAdEqA{5LQVbFjcIIU^O|6!LLD0QDM(!Covc&-Gpe4s;@E%~n;JI=2<4a>EV`pV9 z;R?zpCs1M;L-`D8F88MG5D&eLN=RaiRS`Q$uf97zx_b3p)d$7x&cHO|i18~Xu2>N{ z=1c}^V!{$2N?Q5u8S!_KxiEK#%piNs3NmAmh&sp{v8FyIM+odW|8r(w{1iF#1YCUlkK zX83uri;ZwBK-=2xCBgD5w8f6wa+wvATWgJp3;XtNdHeXVgG{@aX^W<+1%&c z2F|&<7gC^YvU;*xUNTnR9&|~s(*>Jy(7d_b+(Tx$aG~Rc>FQH2p^WlB865=f`bZCQpgRl=JL}W&4&b%S$PZoWp<6e(~Z9i?2jr0Iz$x zX@;3s+Ra8ZK}yr)U;!GuF@^t=Ux5kWG-1tajnBkqB@G=~ zue|b#ry8_jB%Y7Qha})nyoi0O@&5hle!92SXjHjj)Xk`<+T3f+i9c`$Gu+)95l|`! zAEtHX786=F9LasqD*HIQjVoh!vdF}3wR^X{8%P%2qJ@J?_#2CuU3hq-gF{wb#NQ6f zL|iVUh?lsl(oT`46lHuN4vD zF;+avkH+S&?LmCtu~j-c1#bcwF<28VUmk;6ObTz7hon%Z7b{g54I(()Nv^lRN|9rN z8`}8ZcDkK-n@o+4*(#;MV!kSR)FFXvBMn1I2q8qk48z zraIfJMleGoYeX+TVk6W@2*TiJ|3?YFD-7Icitr!X6;={Y^X=I#B0M34_1M9lU{-UU zadxw$dCYZgOO0Z#F~6n8nc5#t{P4pZPV9i6<}lGSB2jR){2Z5qtL5!6=QE?XMB^ng zBWB5xuqC(Rkf~EQrcVDe(U2eAi1~}Z&9-GXavupRx(8vLbKOY%-yDf8G$Coduv6%S zl^*Q)ys|pB)5K1l8jAhi#9M5L{Qq-SWTC@~#JN&8Y(G8-vtIj?J|&TnyCP=`ulpw{gdI3mj4!e1hzbD(;Xw!# zm|lFmFc7lX4Wx^msLXjW{2oym;0zw%O zmB})ZK~N|YCWAl`=DCs}pdge9gUm%DgN$XOAOS)pVUj6jqM!_+l0ZN}QUsJasr&uA zC~NO~`kp>_t$X|Sy|;UL{D-tT>%_xpQ?51WU*A>S3X%R<)qA`Y=dc zFkRRnTh^>^U$ZYESAed^>1Cn$0bwDShA(4)VbSpL+Dc|JyPvtrZ13vVzkh$M_r^9a zQsxCOaNeLw*vff>D&bY$8&nC$d2di93=+ISm2h3~235i|(Hm3=ev&t+626kWL6z{5 zOiC|@%7UCAFOxUR@Pq6Ps)V-`Z%`%ts(6DcVYKQEsswNE;aMhECgJ)i+S(tlTq(HH zs~tX)3tGPRTET0pPvU447CLig#>~~2FvmwvSZH1s%v;sPx8@D4iLL>`3WV;>-ng-7 zV^5v?tZ(&|#xMGQ<3(ms&G7I?;YW=pSIJmF`_eStT$M%{@fR_L`_gp` zNk*EJ{=_gP(u*56?tr#u>?!yOKiR*S!wOE;S!z6AeQro@a6H)pbfZ3|@{LZ+hME}% zGBQ5*!TDi*WyzEzEcvYhF;`+@nieOX@94r8QG9|SQ=1K4Ki{S${dTRNO!CUcnK|}J zY;4cE_zQsm-++KUC+E7c=KBtpQWH+&ZfG6r(;8z8+3f!znjCnWBv%NqRq!Ti!mFY; zQ4@}fp1$^;5)6{OiJEX-@+N8miEpiycgd=pCzB3KuzCeatzfh=Ntv${ex(qiW^4Mv z^B5zw=8S9E9b7#>K?hX2(_^5UV;!1 zG2lZKs;+9qwC_pl?&8IZgLdT%Od}~4lmC5G+BD3trlb?ffR7*Y4^vP+D#O~T&1&I$ z81Esn<0piQU;@FmVHlhu+C{9kRy(iWQsc{2N(<3G*cYhJriyRZom98(4ejEONO7uz ze^`GW(w6I6^gnBnENoBw*E?2Sss5?$&mb;=3V$rXbR!B#Mg^l|t&P!F{Vh-28jitDNu;tsD|}$M^e);IbD4os zMZv71VtjWGcsv$E(rySJsY4!MZZ$K^Q%|44_pM~1Lv98uhVGD?fuNf`$<6ST_GdiF z&F}@Yf$=0aLlE1B^&~d~K{tDnn}ML4J;}{L(9NFYX0X?iq>z)hHK3QMUy=ZA(Q4yv~{F|=CH$_qL%%V{0vt^~%QV`+SG#MkK{zb(& z_pFe66y8rNDw>9KOw(li(i9axz!|UUN|HwL!;6eGwa%BH$lK&Qf}Em!rySi)zN8|) zgaOMLk1B9aaqaJ>ysN}0la<};$Ef>$F*+9%6(MtU${~z{$VJ5%z8a^Czf2%&vkG59S?Ni6MN4ewK5O0n?8c458}Bmu z{Dcq2u6Ng*g*JxU6>;549KA~c>FRJ6sqIbhUZfr|!F!R~p91ei>QxH77paqJ@Lr@= zV!(Tmx|{*;Me2(zcrQ}FXW|;gYd0i%T>5`N` zcM1U$4WR_CO-&Oor|iup4V{F+aK}gb zQM@q2XEk0(a2+51b&`E#L@JQrA8Mh&_>O?VYe5#1~9gznnlr~5p{D6Gq2b9)N zMB#jMF-~q31*t@CMWG5!Y$%oCSm$4miq~=d)ehO;<>7a+L#BsuZOn z@1Sbx7<0@R_qEmBw|Vofi`={B&(|nBl?jKG55G>03(v!A{d`WvmL!XU(Az&eA3xk@ zb0;dFDnpbz6VwaxA74#WOK_vKepPrrzVT8HRZAgpv<&&{Z}%n^xoM;MXsV)?E?)-w5Kc7=e5u?Kp$0!23 z@%r|J=|eZu8>SByo5L}Rka~7>ia16QAY>5dN*+st_m%vV2Jb8R3kJNe)M^DP4ZMRssP&5ZQNNgWfGMpqo| zo!0D1vu5Q3+oW_%!a2Aicqti05EF1GTl`tvCSCbZQ51N9uZy9JaQFZ}e8#3pUkiJL zhH|;|l#(Mi;Aa2{jItYZP(HIbC3jwKZtMM|`ypz5$CQ(YPo7NL-A;OAVHEy^L{j#Q zu-Zp*P!lC=J5Cfu2ok+17Cse8oHm^H7ltW^H}2Zy+EtW1RlNGO+t9WP z|F*{}#Y2765#JFY0+Df})y3+1l@xcw&njWZJLq^At`T;;gN_G+aU#6qE_y$m$H4~X z>7K>iE(2;AgdOjokld$6*bUYAlvL`kfu26&>@1Wyh675}W z3%*Pp#uJ+i%NW9rchK?BgeB~F2OSUJu}4`?Y;pzrHoo!52i$Zg@$vF{+LaSHAZUR6 zEBX0xIMiN?CVBrA;tyQ*o4H9_A{KFfaCalzY%-(^JQoFbxu8LBrkzY0FE!^o^UJvj zTevUyx!fuq)$zEA1b>jm-`j-X2&gGN;cE(g_%MNVdyN(@%@D+oaMu)vzl)-Cb4I;0 zf9}ZLk(eH(aE8?92pVdpi~z)D@mI`16e8Y0-LOH3FL=Go`h8;N$4dJ^95M$i%8+PMC=_mB=B@!C{nfrp6&}`z5q}61uGr<@#{{0M_r=C~0~90M_}OqO-GDVC&Ecj~=?0ovWZpBKN;lxC zIBFi{RJwsdkxn;lAmXR8P0E3#`d)!D4rg5KhYq?#V%H?rgq!i(yA77uR-*qSdeLHjr=HKE6 z^Pli@c!`G;{yY9C|0{okCx0;X*a;Uzt1Jqi01=7gMmf*j;x-F}T?|eb-C`F5iJN<} zi{Xh_Q=+9XsfRQ`8ZFI`V6n7bBLC2TmP#ZNUV(Nr(Ylhm)(J?e4wyb8Be zYs`5?>!}UWVl|khEzx8xO*^ce)vjxgG^mbi31YpnomXI6uWaWP*w!oCc?Guh%649X zZN0LcS72MOZ08l&)+^h2g_@#ey|SHG;G|cq@JgXadgaIw(@iEoFo9Vc#*ZJ5v!J<{ z(7^F!V^${%SA-L|ejdp<376+sAPJXc!Xu6(T&A^M9qorZ>?y3wrm=_Fvn+TQ^N!@Q zng|^P_n$}K-eE2m?E)Ms!`L2dIR{pKtJB^JGM~niAo+Fv5l{9izzC$ib)+y&_*_^k z>=Hl~+?;m7PpmJ#EOr%v6QfbDo&PtI0CcfTBuIjnq;QEK34kyOJdp%oN&&Jbk^m$* zMYfOxH*gH8sQ|5nDLoXYUmX-BTlrZjQ64B&)rM+o6<9S=9j;FKPv*?(N&!bjQHwAPV-gYzsbdfc1siDtD?1qir2U)d(Kzao|YXyPy3VPNG0_hd>m+a9AGDIat0~~1>|IR(eHHI&3a}P!&Ylg%s&iG(T0wZK`fHxG zg7Ag5LG!E?gdn|*?pZ4cJM}}lXRRO*S6$H{N z=vgZWq*u_hRuD+9pl7Whv|_q3p0$Gi7en;G&dk`68L%@mc4P+Z%#0nGfpv;EnFLy? z-eeN6Gc$H%2Ks8=WD>A5Gj?PK?97ZEnL!?%H<<+N%#0nG0Xs8eM`mEB=}jg9J2PWP zX28zO*pV5qGc$H%2L7O}%#0nGf!WMb#RBrY7UayS6$H{N=vgZWvvqGJ1Zo)GN(iho zyp<4WWqK*X@#dXo;G+GJZ_eZpynY4+7B# zJ>@|#beG{N4}$2nRW3p}8=w2RGmyJ6$w@vq%(skn+wE^~EMp^yFa> zAIs0;m+ofGl`g;98DXcVBfLX%74l51k5LU{8z$I|YxXs)TTqbjoyUl^g1@KMy4u9)*Ao1S1 z9pJt}=phUcMhi29#lm_46d_w67HWIV0IV1(4i~403&quLpb$6|QVT)~yc8$RlL&>B zBnJwlr-t-b;`Z&^aWkRU1KjxiwP?|zE{mXP67D_zlDfzfEb8B^Q(PYWQCL`re~#hVvH2~N@Xz;#L7U(v zihD$4fMjGmBQo)XNHoRWgtLQ6^EuV!)T!t06%|Vjha+vH3n_SFU7S!J^o{ zxW9?bclVs4(o;meMeiF-e?s4`hKhe|{z2b^2Up9aF^3f97&N$;TFe|;qI)q`VGdZ0 zIpjXN#dKiaVxSKF5?zNK#KyAZf|1!Q63~oeA5dpm-#6?W(~@?N+1ecVaI@K^>~wAs zw+=0@SsdhZS2+*LEeA2&ySyjm_Q$(?C84fR64BkKZ1-+@H=xHcjwiw)2ttB@YNJuz zwBV$dOd&2G*Aub0$SgV%r@tch6#Gm-#R)U!=mtTlNduIxdd)l(?e9QDq9U>dfoJmr3HgC%^8*R_JtWN!U4BBB4n(O@QDhaJx!=e1@j-iH1f+LKPY=I< zJMPT=OZ0Uke(ro0Z5UtbnfpfjjvgKEk%htbT8}JD>2CdLmcFIPsu+FbTa>)Tsu)#k z)+ABH%{SMoYuBQSzj@~VswO6v+`%Pm9C#!@m_VXS4{%wSxu0wekE5;VubC}7R4zl5 z=bM@PuN9%Av}WoSLoWf`3$0E+cdqQ*>c`Fgnz^2Yq#j^jYUX}oxLAlA`CTyx=6JPk z%@0|tq_hsjQZO=qe^CRr24z_!CQz_6vvb&?ntRJur>#sogz<791M^hsGinXBlbUIM zVZv1UAQeTAp#5pm<#U97NZda6>$u}oSp1r~*Bz(A;#U%1I6+^eZ__`}aD$noKhJ)p zXFfg|a-ZqXK1{#SrfVWw0;DNwb^7>%-Aop-Ga!Qde-~;82wMSGvAjVIAGnn@^uky zh>v^Ks<>4H_+|Y1f#_yB(e66JWLHav`y)i!|Mo2E)aHfr;|eSS&5P8zsTHQ zIr2Jcv}sYR(=f~hO+{6-GS7YzsUn6DW(S+eYV3T;a#6w=NtenbUzzlM6Bi{oHcH~6 zJWSnLtzKN7n^re6JUkps;&dQje|I%AZhOm;VRys@`Ja}R#XDtXq2q=`)ILzVc1AJA zD4x5!pT!oYdGqE4cP~qNfDW7`d-0}#>$rkEpFS)B4G>F94xtq{t@N5&`|ttZ0|%C< z4(=0@w68TA_Zhrscc zO{6aMZ2HuMYtf~RB5Uh^qb>~j9TPREZ?8;}K zZ9_l%U+vr%IeL!6%opDH>8J3Y2ID_*+!5B{7E^`msRNfP^yhDNi@@8RB0G%&{s%6M zzR0aZ?@cr=JIa#Jg>8AVWy?4p%zVJ;E~7^eXor^PyfK$4xI+!(PjfT*XFj{3rE>>h zjO@9NZetFyyy0`hB-I=4YM%NXcZ;=!RQ`MZ82_Pwe%KMzR0^0t=0%1S3RMX3ycjCB z7vIFBB`FkID#AuFT|6S56Mq*;p->}fUt6hEZa)v5V}sjuInbrc+3~oAKiiI2UH_7u z#S}OXVC(%G?>vABD|^9{1q*s5qOl0hPdb0TNZ#>cOiWC##N(KKdTz_H=!&v7ZD@B% z>~o69_ELa2MlHkW8TVTl$YYpvR`gK^U`ROO5Gg@?6g4+GF)c7+NZ2$?Sw#*(UtX_7 zKMY?*^7FnO6|p9IciPg#JsAJ&m3Y4_Q7u_FIKNi{enZC%?3M7^q}N^>nplyESKyvd z_jU=tk~6r*i@D&^z@x*mE7X$tfxQw)&1)>bOk2WV(NYZf&d7KMEC|-SNC6!5Ft_PH z{B}siTCU7?`Wre7)GfBfsAuS?EYfpXtp2G^H0m86KAav-V#>Qh@0K)6fnEut!s?pM zpUgD=G&UF?8-;7koln{+JIxD^aG^<|t8Dvu)0c`?Daya!HMCYGB;F4mVvaRoZuwFw zh>FtwFos2J2)Rtj>q)c*|7|8^AI{Du%ifGo|A^OL&v<=C;>wz6Y+oI7(f8uT7BsdF z)?G<`N#B>VmeUQCP1H^LDIFD1qefhfv+ZJn4;A5sJtOBjT5rnfKCSSnawnJ-TFngW zl|cGG{P62|R&c}3o(|ODOKwzH<-C>A=}c{Qsd-vkclku%QT+a98n3oZWv!Ch7DGCk z@V2>|eG%DI&k!hGOV5R&k*yb|(I$3!j{CLkp=f;mxP;Lh{Kc}!M-aG7oe-$+=|Bu9 z0X)k`^22#TfCWzkEFr*xCjvG?TKw^yVpmG^-H1g(3GCnR+Mg1$B_zjwF;ZWL3$0i*+HlTZM7w0mIKEzPv*<{p_Y!a`zQQR$QDK{s^3kx6@jAp`%tvGXeNx7vS2C7LSyhbA1`+%Z z%86)q7SX9k?yp^;@$b}3*N+(I3a%NGjna~R2lnl&8HhtrQE7YM_U%(*!p*mz#AINH z&DLq?!oq(dTejRbN~JqU=TC_twyOjaeFFFQo3BalNHwU5(u7av`Iv801FMo(WsDzw z1O`y@!)B3FsXvW7bHj?&Bff!o+U`qDh_3skf*%IM^a7OrbgsPhErdl*N z&`pRn>a6f8RbK>RC9o9>B3J-vH?S0on&L}RheZ{YU8LIyzer0Tb;nz>!=gj3M-j8H z%%0r=r`XREaq|t2x_1nyh(OBI;&x%7A)z6#ND8WcA#Y7lDg7FqyKT(;>!K(YNpG#f zU>W`oZyy=Tv}Zc1>*OJ7JqBWy*f=N)#|9rMW28?J)mJF*S1Kv_65LVlOSP5lN+&gU z*HmS!nni#^sp^r%b2I8<4sHF)DR-ebasbBvIuQ@0?c0vC`zk4*$AkWJYM*LKxzfKz00`neoKV84< zd-?Lw;!$O}SpU{NyGPc==k{G<@i8N= zV_u*)W6uI&AbZf`l+o%6x{11;eo3zwT#WNNsVs&YjgHYZm_|%nraMEbvtc?uQPwf! zVQ*Du$5&xVGgdR@N8@HuWLUvH3@o#g+LFOt#OMV~ojNs+1>5stTV8%w z&w7`)*kxmdEy1;FxoWLWy&v)T3|c4DL}j{qCsh5jN4KQNFmkyp#9J-=?uLv*dAp;7 zS!{Ymm83|EZ0m>SiMWWUw{4eiGQ@HbBJF&MGuXu}96x;g_>J_`qRYE(9#s^Va+E#QHd(S4yZ-<~yyI?z>k^esnq!aSyK7ru zR9ch?a2y}wd$?El@TjwA%g=5LBprhrHzsTx%n$Eh9Jei?G%dfV1G@jh`AMf2D2E? z4~QI9%&!w3Rz?6{IuGO((J4&T+inZMTl9=T@esmy5v>9WYAjKeVEfRy!iVBbF@9Dv zF-YphPk5J)k|uw!B^zG}+XCH*lbrmFsnTbQFNjEMn=Ae(5?UKJCbQk;JA~G@Q=M5* z6Gaa{3_6`}Fk}xRR^@F9994p2)}@wQOG8oQ= zJm&Fswd6*OI}g_-Ha6)dY6iQ8be9UB*Cr0#%iqy^XJe$MQ&mII&RoOUdW!bdk%buF z%S;cQkt3fzwaItWrnJW^@!wT7JzlG;$CF;=5&8uU?_zz^&jj%lZ64Q`=(kYB#%E!$ z_=42aP^5kaQP*VyydhwW3EmJe)to>eVDpvXJMqWUHRjUIaX#6o1$D)eO;^zk)6;kc z2dFcYPL)xB2trP+Fi9=w(6p;qZ6);7=imR%z0$^z=qxYLXQuqeDrUEL?5G zxP1KZL2`qBiy6#(!pvbnVp5pzn4`?E%nkIGg{k{U^9j`nzo=)rW9{s--q|O0>lSn) zIky+@z4&5RYGEf5al4LU)VS0IVR#`?@%m-?e!&gD}#rP)xTJ-E2hd>kwAE7;t}>{h3Qc^K1NBUgW0; zU-R48w}dmDv$|wuxqR?-vrRZ9z$4)m^g0d_LWK9kk)lBdxtIqJ@u@pSJRruZrN^gZ z=-lNaVZ`$2)a~p2@$VO{F;c$RTrx?VfK&*JDL=C$IFevFK1uQUWoV0uEaG78=?b}l6{kt2TKd(CF(`lwY_D^ zbxiTO6nZ0mi%SENF;f@39VrHA$oBIa*?EI7R>}hcK>iaBO5}M(MqHEQgr9yvolzK^l@hYf+YL?nDbGLd#eVj&|-5ENqm8dUic`EeL zrtn1m-NApZGSUeRtBtGb4fWQ~%9p3;;9b7_oRMXfFBeEX{_vS!tJb4h{nAHe6U;*c zvq1xQKk9eB-+dQhI6i(TH@p{hSxZc3Q3n_f&<7XeRd>UDfqK}2!Y=wD?o`_0k3Py? zb24F3+*Ilm_~B^ZlaeW`N(@LpvehLD8*_X$)2^h4vi;3?R#tcySJ!Nn7DB1Y|+n-baqU+(n>J{(+hDEpA&PUB^LUfeA^ z`OHeCIk)|D62hy=jNbT8+F%mGTUTeu;39mQMH{}K&i0)>dn9c#ncU%4_h+nR_I<lc5gNzq9nCj z8n#^`qlN400OKw3Ik|_}LY^l6WybqaN5x;oJ;IaO$=OrGYWvo%9dYcgNK}^o(vSp^ z6tj_;YGTE;ariAEh3%z-mlBLaB7S+YZgXV6HJn+mJo&U=Ke``amHZ>Ai9Ds_rBQLs z)}y!|J8{mOfI0m(#JF;~k~%p{R*X6dZ}RW+hh*C*I9tB7bp5d;6v$#HMn}7%>nO*+ zOpaW#qOLYusiwHiMn{zWi2S(BeJtci@P$A+GDqQ1xkz27;tZLk=BroL`)U=91P{Au z@$YIe+GK5kwn`f%9y~SZz@R~CIVdR)^{Hv%cL*f~$o9?7&d{9Sz(4fk#e4SS^}O~n zi#Gs%KYJR2QAjdrd$SwNPrZ#FYKr_6>Puf61%_e3|DZGPmU!O0{&1;lNQlTV4B*o@ za{O_8JeNFP8kd&cwyoI~h;sk!w*}wsNyKz^T27ZP1znc-qacx%^ZM)Z>x7mQ?sF)G zy~ncU!`wG6h*spU&Yp=P+4N!DFJz)SO^Iowl9QLlxR%D@GdV41`t+jdOD4vQT+sSj z8LAJ+HEch2z8 zw0sU9zd=hTE{($xBCg}8hzr>Z$yzbF)SV;i6qHfC-G$$eag~P@ZFe2V*GO7Uch`{U zUAyRAfZN3tY%L}jwLU5W>j5|8YQQp8gV1Ra?dA}_Z1q?den^d{Dvhq}8Wn*9GDVt= zTeQ27-8*F_i$3QVhBT96Luu1$+;Rhuihb)bPeQ*xJ?R+NI~v}M?jC(k`RJ1z_7}Dq z`;aTlHG}y336Iw|8i3l7e~Um=`COtKl?T)C$&;3YQ(7<|RQ=PmY`oc%_^uds;R|HF^s3ga~QERv~TF?vS)>)bY~BbV?7|ulz9@_c1B${1dWz zvmdep`yHZws(v$?)V;L`!~nnzVU`$>_yFgY^Eo86I1S${9Re}2cs}PiCKmVP22R-! zvSf+51dZ_u{&Hz|jd5De_PF9$AkOZ(lH<^vaBWVb`P=dTJbstQrRKH?!w-9TOj>qS zlq)J$(a@q#oB$W4rVP+*82bTphSRwgsQ+Zh*g5IIGYLBroMtzx*lofsWt(^TVgf6yYU3T<@a~)j`k`^kw>H-6kPs5foxWy@SDC z&2~@s~Y$<}4X%maK z+|DoBl8}9)T6Eo{PX1ksODYmDr)|oxaOkj+`GduFDUd5eZ z)%4>y{SF-#WsEQq6W1qJO~>!n3id(UpS%40bJcWwho~wJm5RYyCrWz580*mk;f(D?=w2tZ^42E<768l0fZspiIDh* zjlhHl8%HH|3|JYBH_BhiohJLbMJ_1oSVki5({Rj+PR7|fM1@!S`vi1rn$LZzK5PH| zH;l1E*y*ZmjLkn9)IBXH5-;661kyg2zqD=|-eh%DM(>bcWLmLAIPH7-bTqY=jZS{- ziosgWtVO+YB2!x&(wlSdzr4zsmJxQPo+qM$DKUA{b{a|5Oo6BQkuR2%?pnA4MXcOcr*?hZ4Vr^=81>S?B( zdMT6kWnosAS+k;(@z?wp^9sAKj2py`?2I47=;Ud>)25ANEyQ(A>LNQKPQTJ=OvIr` zd^r}e6JFxxk7?6$uM7X`Z|E?Z+tVyRY#6nQ8%P~Q`guID@>Swz5}FhL_8_vV7&&q7 z`Q)Moq8n@9_!&UrCvz|LyfBxBFX?|BYd=KZB%Yk&hmpU2?J6QqiVwwV(!cMxpG+M0 zC9#1hyJUx69Up?B-zCMx5jZXwfOp}PmAKL_%?!mY_mnjxRv27-Ic`5aUA`til&dL0 z3V1uVcPem5`B5%b{!}Wf_0*Q?Ybtm;wy&`d*^2#X?${v~4ri!O)S4QtSv|wUe-!Z< zNZO4vMX(BooxWl494g360Xy_eUDKWS6m&8A8NA{24Z|t-r)D9}M@&bId6poTB(Tn8T)R15lq5Rk1#rIt=`UAQr zyNt%auEWpc>nmg8qD8Jn+34#bww|WUtIQd-v`b^uwZeTcBTbQ~TsR{#1>DyR>_L70 zJnHl148?}9Uop_rZStALE+L7&ZsU3Qg(d&NR^#k|7L4Gga-VT)I6I&Pe{z-idVEXX z4rs-H%CF?V;rH`aKx?>3ijqlB^1b%$GelYdyl&i#zOI4fCyhg{N5D@Nz&qf_iSbUr zPni%J(D+H?#sM)ni^3#x(j>Q@I}2lGZU%3q!<8z9$8>bZxJwqw+WH5C?DJ7jU@2(7p>4~4PUYyu> z8s4ib0`b)_hl3qlCZ};l+&%6&{sq1T4_)|vs5iv%^Y|6~Rz8C-JjECA2JaH8kHB9@ zMbl86Qwih9Aj4$%UCci|oPT#b_r`E{ppwNzCHj6^$E4=1^Ks?W#0fmQ_o8u&d>1W> z5F9roSk#4QZpgWF1^7~!DjpPb#X|9}SV^iY6*iYTOMRtb(%6NBn6n}f-D|OnIz}%o z8zaSgg_zc!Kz6UYez`Z>yEl+;s{9txN4%`Ezslfkl^v~sWtDXztYBqWod_#f?E)4P zpOgy(wa^w$M^{8^ZS>QX0e)yR8}Mvt-$5%K{x<5UnRjvYzcVMXQS@HzsYZUs)9|6W zA`sQRa_u3bcfF8XhTjWlbfr5hH0*Qqt|q zK1DdQW#~aYeqUOK`c{PTi814*AO57aiFQlD)9c2ZrDPwxVnz0f);>3l=4Qu7y|Yny z8`r_)%{X(Oxx!6%!iRhWb}YN7T2xc&RjL+`84ZHQL=;@vldx!87wp z^mg!!MH9UpoZ>&L_Ya)nKdbi-oZ>&L_YXYn)?~{Ao_1^Ews!MnJ!8;7a?rNjnz*h1 z+49nIH-cTwZo5su({4@NCg5qeCVDWC9JFn>CT?pWc5CNvsHzGi2kra~tyY0FRCpFt z0BNZ3ET{m|P~lln0i>bAv!DWQ>E*g-K?RV83i}^DDX4(zX0Yj5PywW&!n2?PUZ%QI z|5S~Jztw1(%=NfXA>Kceel~cZmV^! zgjwPeQ5Mt0!{S--y7)+h>Qb=8NDwRU1d&= zmM6*c<*$&k1qb9avM!g&zDgbCB_&*eKFUxOYeHNY4{8KX6iHWGV@=3Gm6tU1CBr0BA)zjDH{QTJn&=}A0+ z9cHHKNjw3R+bK`t37nz|C{N-Ed_d!DMw8iW4^66N;1*46t09c#k&R_w7PEx$B%VNZ zHkkD!p1@jm7wZsD>T}@PEkmkh-~dM?sWQ~J>+qyn2Kw+rc|y8b#&70HwG3S3Z}TQ^ zb<2>?D10I~-7=)70iFm>w+yM4fyLr_Q4tARsYE2zGSE?6OzctriaZ9llyZeqNf7|)SBO<%mbyfh)ik6!o>i}_k5s6x1#AER7Ak;UsBoAg z4XuwjsLluT1kwH;Ka!uuf6l{NeiyIudA!xoT3>*dg|4`tjus{f*4i0}w@4St1Yfa^ z_>vedLLYIcD4?WcHME`(;i70sI<}$%pGb4?eUl>DiVi%HYRXPS>kJtd%kIfi{#h=O zAIMb|XsEPSSS3;!u1rxDDytRPp=2tWQl#8do>N~?Td2@Q?Wgi;oH|ckp>9<(R5*oB z8AEkxwX~)hF+zhIDe!J+Jwbuh&`R(l7JURhp-BKGh5n8{O8<&fYA?(OMl&-QSj?gx%gUqQ=YJg;RAjgFY;~?ohR&JxW$+A6fRz05qb)QJ&b{> zC4wxZ35SKV0$~qBbun0E#0ZhBW(j*3Fgt>-`8@H8_?Jl7!|<}yRU*wmlO)SE4+kV~ z*F1Q_hly(*F3PuMQw~s?C><2S9)?epIf|sXVVDYG55p6srb??}{}bXi?9eiC>E=Wk z!A70gQARkW7wDc*M)<%OXLv>#;g;dOA%$6{=Z5r=3Dv1!$}`FcYpGq7XOt0Mrn}Of zQARjGpP@aYjL?S}%6LW@;UaUJ@r*LUC+r;7Gs*~0*qYq4C?hwTo58_iZat@P7=GeP zxCdNS9vbqkJzTG=dDy{c@)}>n-{XnvwS@p(gnq(%AN?0y2%pvDRSllc>VKp6t?PeJ z7dk_Mr^$o7s=;mYc=oI&uWImoR{tALj+(4{>tjEw$*USXpVj154J`L=zbIh>N5V4% zSPv(WSYOHkAIQJRcjVvZVF*8#pUZ#ATTcDoc(}qw}u>doLFN6)kx43Nn zMYtwB6rh?IB)WT!#1Z0D@iP(Dh&#nY;!k3+_@`J|s)wB*5^>XhBoP=WL3{#Xd|sCB zNIr6HxtZKahTigrGI38N%bVoA@{ckgY*Vg~pI1Va_R5>e`wEOvEWdENazr_&{I0-b zrH0x_ZL8WFVX#)h&PEulm9VoBhV2@0wH0c2wMu$jy}1sZ^}hNreS)5-6Q1%u9f(D~ zR0ku_c+u!+ylub`W2`aP_|ixN6Om!o?s}O#Mk!rt8tr5`C=i&>ztg=}+mE^fxr@r%%(D z={vL!Q=4hVbYh@4^C2^yiD#0TP0U{AM+Po1e=rry^K2;Fo<%zw3u9Q44&2D5vq#u- z?C&f*er7S~&h_U;anm`lbAxtl5E}5U_-_2Wd<;LCw+vqVK|Yr!%N1+40-c4v!Y~Xt zB??x+2~G-^gi-;-K=DP9&?I4qI98l1ekrDk-;2k@-$bm&dMf%$jU~iUN&}^jC73CF zA#ISpm2#wC(D(RIf@*S*+(v#~j*>^nQ{~TOSR?P056M5t#qytWWu=}1Efvok(>Dt2 zS57OJl{<=$N?c!^ROqdKsE$|T)ns*(x>x;Cg$wE*s+*#!wb$O%-q&D^Hd|Y&ZPe1W zBicFbcMTqEHS|V$TfMv9UmvAU*TD+%Wa;_(RsFtR1*KD?mC?=ZI-G1QFjg6E9&4^q zXxud_nV5z!p|jc79A-{16V2u37IPmi=*&xIsR>jd^&-`gdYghF)L3dR^(B=`eNP>u zexu+f^^~%La&OQB>5plcNq<2Tb5IWb3w@1#NJBLyh-t&T&O|XIn5oQX46I>xGKUyk zZM#?8^-#ZKUt`~4KVm1cpR&YF2m9I6th+;ptIajzI&sjO`;Z&Y#dFErCT=hHBL^1{ zI$6Oz&xi8udE&7Ew=0C-$fxs1c+v<3q!Ox;&{pU!^cO}6(*;;0tP^$%Swg;WRk$xy z5ut(DO6(@SE23RfTp+FzVY`>Y)?5NhVVfW&O3NkeL6hL5bP0{EAP34X${ppmWf&rl zmFLP|%Bk}A@-g{08E(o?Wy|>ghB8q3Sb>?!7s>|ZTO~*NMY*OtRG^v~q_$CCSEJMs z>QwbJ6|964=2$SRg1%}DcWSR`?`R)s6SYsZmD)EN?AK0fm$f^Zk6v4ErgzezxBj7y z_xp1mNrltQ7$`I|6G(0QQc+N2o0{6FLddTkwXsffcfHGFD)PtelJ$SRt#n zQg`B0mZnSSy7z{-K?B(v;s)DgZ-^T_%Wo)&%5r6kvQL4NiZ{d!hN#{UH@K;KL)>7d z<_&R!YPvVX4c6%15I1OPcthM^zu^sW1B*}ZK-_?=+dUy}FoyDmxWQw}8{!6wXm5xc zkWHm0#0|DH2bo-^kh#lLV(YTaS?J96Wrwj7*hF?YyM^7y0*T0!vcLs$FLE8Zw>cQX zjpgQYUvjD3_uMh=Hx6!cPdR_SG2f1VgCEF$%)?Cn3w{ItEuX{x!e8Sb@=#46{uB%M zIaT;ffHeZ?cKb;v7XHL&YCRD znwFhm8LVm98J5ACmYrc4?2NfREQ6gfw17|;LQbZ!h$y!{5uxBx!^rG7~r0konaZQY1tW;|5*-+ z7vj)S2qc5!S%8Ds0Pg}E*duxu;6P8wUb9Z zXZFP)pK9fqhpHCS=P5#c4w8c?KJAXpK9Iy4{6AHY^&WmYS zPb+jb{WEQmof|UHnqiqpW;ip2vEo3G$!O2=K<+pY3;kF^ZJx(k>&a6r6tD*C;%af$ zdh!Df#{Er$vS3h9Ze`YZo6-yp4a$N+0YSNYQkubgJ^8W--r33nBG}nVo6-!H2h?6q zUX=bJ3}0x4;kSO7k%YYIhyApz^4VmvH?DV}UcIv$&>xtQeD2A)bD4+S9m;6A%t&s! znV?Ag&>46ly|?z0+*_HjLnJT?bR;(2ZW3=9rXWE?y99w<58nL%{TlOklLU^4_E=Ks zT_!*ERmP>F(H7gR%BwWp;zouX4nDjKtBBW)Q~qD$ga2Q+H`v^ql==$w};|rkh28cAttec5spB`;6#!NMLL*4Dt+oC zVq%~)WjCg0!cx&9YJyd-eB^0KV#gFW!vnXCgyGRo;=kB^VE68TMD#WVq;Esg328ru zR=%xT;r}7^Gue_0z|jjVxd3y$q?%==@{MB21(@r#^#V&S07oydoofmRtY?tYhf~ zmRtaiUSP=u;OGUGTmX(r8cq&PijCgdW$V`Zb1`)j z8}oQcZfrD~>&_-Nm~-~5NvexUbFthIy}||CgyEkJKQMfFK_Vth>rb8UJAZy`OkzTV zDW$Olga9@P!QIs(&6a@Vw9};{(mCmOi6jl7k=$19E|a9;ba|1yPKMobmYgqNmG8?{ zlm<#G1?;w~1zOUh*GzcF{KzDDnU&@@=6>_E375?~Cb5GzqdHN&sSha_ zPsLNo)Fx^#^&@qG`hxlYXBbL(isRDNS-cN9c3(@APB31_MqM+e%`C6UDZY z*wBrAmyKa3vkTZ&>~{7b3%P6|dzY=m)#aLFe`#M1u)y@0K0HG37cX%S*9c#VmwS>N z9BKS5;F$MG6l@`ynon@P;sAb9|0omVrsPL^_3+iJas0A(qvE3GRH`Ib0?d6T@yGjr z*X6tKvb!Tv$;BV|SVX!5fjg9Q{@Jgi`|2ofefPjwAXv5>_)GAnAc9j*U@--rQO6ux z4s4dZDTvSky;Ffx!pc zmIF<7!t`-$Ij~1RuAkQ(TMqOz1{tx2W6OcF2Jz)Mwj3B~PBT9@9a|3kW%^O|DaV!r zc0GX|5_R+C!fD5r1C}qxvE=~4&{L3oM>%Ry+{c|H)p+s<=K0B<|bED^lzJk=%e zw)3o&z}wFAvJBpKo&z#?+j;sZ;BDu*sDQVf=Mxp?sFLc~d7h}?n5BuGXR!wBHAQnw z(hYTRl9yKS61+{)T@3IxNuM%+B+NVmX5ek-xn&|@*G+JEX6Knjfw!HfIt{@zLz5(B z0DFM_oR*%yj)F%&7Dt(!oT8jKgqU2R;{x!lRyc?Lfn7qsz(lk`Tu-j+9poTHFtb{< zX(N-?-iS1s>s!EL$tVU`J9Li=5D`{DKKwJ7|G;&lH9=Ve6r2(Y1VeC%wM1)xf)B)T zq9`VbUyIfN1-Ha&7sHz27rH6)0o9thG>cm8gYWpkZ8~&#)L}KH zRUwwtz$<})Eqtm`-@JrFp+TB+PuxX-8ATq4RReP=(sTj+=~47_+7U_NDt(`>!Z;!+ zOlGW}cUvUINDxs;9g!3)mDCYQ!BR;bkrXVI)DcO+Qb`?=6fBk05lLZ$KvYskBn3+) zbwpCIR8mJI1xqD$L{hL+Qb!~OC&9W@-YBQbi19cl|1LWsDR|o1vlPsTUsdiaRa8eL zg~{pyb(QLfq=-nWt2Nggkrb9|TeN+eBa(t$bzzI7@pje4Q=L2_>P@OwFPLVpVrH$t ze0q=ST1?#L?b|8BYFOIUD~yqUkx4C^Gnl>JD*aEjBlvo62fA+j_>y}p2(6`U1PjCuN|CNV7hXMrz+r(=O=FyQG}AQ}ufoGuH~1)h!tVpssr zD}>x2;CY3R8w5PB5ORZn=M_S3kpC{~5G;cw!Z;d?N7RATvvyU$ZXvdra$p0NZ4Kt1 zgOy(}3T~Fp$i|2F$Xw)A<<7{#YSzI9XTpXq8#c_yK|*O>>4u_9m$PSJ@AbxnT#^Pn zU+S+H8gJ^A%tc3|iXNbJ)9W%p^kJO80fCCab^KswXoDVN+OTv+4sw}#okL$b1^6rP zrCW*&)Hl4lwqTp#-L(bbrgzsC5J|>Uk%7UKch?r&puD@bU5kj+b|BjIB&x^c=Ndj@!-wpzRrVHoaHDo;LYdu6TvFZa%fkuO>}5iM3Dij zILqd9{~&=kpZi}49c0;|15z9M!V4yLnj(GYqmRswfaE8);k@i-Ec*GGe(vGw(xviC znOpGZ3-R%KJYWnwFLnC#g6VazKQ%owb>hT=iFv6Q!U#zJ_FMT|H2<%N$j?ied~fpP zu*=DL1j-;{xEss< zle%dWiMYq66TC}``v2Ce**3F-|nXs9Wy&vZgwX>16F{>$#D^i^1W;!Ufmz;2$Cz|p>NL#T-AKo9f1Q=0J8O-Fsw>y!rJPK|v~`^gomZ^v zvT|ifDu$r<$j4Vb?6|tF{B#*%i@$o{)mOtdV6W@#)EZA})abR+oy2B&cdIKg(^otq zW!5C*T+wSKN{a6A_#=6lvRU~-IiXk

1SmW3WXAKm254OT+YdUTUFH+Vj}$(#Eh zNDts76Rlt(ILSmSnD{@UIuH-NWuXVerv3fsCU0)A@Ffnt1jwV?^3YordJ7Oj6A!&* zp$7s^p3i*6Y-0{Ega{60j4xY;b+ z!p-3%4pO-9xTD;!+zsvtSCglC2;+P31NhPW41O_BIz1s9lh-Bu1HP)zP-rc%0z?YK zg(<>9VYRSB$P_dIiiCRtDHClWb`c4__+gwlPh2vUNc}&u_`N`#W{LR2^o1xB_e*Y; zvRAw`={FW(cR0k~o_Im5s3MW)A|{rzNS~zj)SmQdQBir(=7}WkRa{(F948$XS1%>o z1wWLDQzovFu1fc%D)N8X3;s{o3ksc=a|xC@<7=@)hYm-1g9n%JwX{bfX&USP0Vhp! z3o9k>3E-q@tosL?G>vutfRm=N?jLZ{G**}foHUIUrU55SV})tJNz?q-P4I8s1f2pn z`t7Q5xXlU1>i`CGBq1Sj_H_XEeL${*DO?{O?EApJ4#2(-?CSvR`@p^qz`hU2b+AI* zDnf>MN-Pkq5N%WGRSB#XVXH)Vk91su^U^J;Tyjc;Ay%FxFTrO;ntWJ3D_@u4kxW{I zof2XATp=yOPKhwoSG^-OuuVOno^hl7EwVp^Ykjn#8bSM8WPdoJUDR%C1np1A{%`3p zSpP(yqf2^<{+)hQ|5b+@`V+mT;gkr&48uE81657$NDZtuy(2Z?CRlkyY9NF1j?@52 zlY2&Lz-ke8A~jEAnQ6_fGSH$or?{gvYI97knt*0}QoZos*n9V=Eb6!I`vg?fk_k+6 zha;GlrjC%B`w2=-OGin}{e-EdsUw)0qz;h#lnF9-DHD{YmQIkGn{a?~n=*oFVd{X2 zroUu_a<9yLp4WJFUDtCz_qy-pqu1dI|NQYge?WjEoJHph7q!FUoc#iefxr8j^f)F40TlBzF=6Z`t}7w8_l;b z81`tseZkOQcW1nvh&PnDcF&9vW;hXVm}Iy!-p*DT?i%ilx6>C4OHJRt;Q#xE@eRHH zpLxUlr-Rd;&?|VW>m;s&x4KT^I(Vz=B(8(Ex=!Lcc&qCqu7kI_PU1RvtLr4LgSWa) z;yO_IuUlOw1S5E>>m;s&Q+VNV=YzMpPU1QcXwm&npl1RQLDW0+3Uvg}JAs}FuvYNA z6X=-$ZA8yIfu0GlNA$cC=$QcSd)j?XLy6>hC(ttiCdr<60zDJpuIzay&@%y+DxP-& zJrkg@>Kl56Evj$m6}oA@p;vHE?CyabM(DnwSGcPChF*bWa&MI!eEEcnO;~ICqC}vL z<%<%5J(dS0LZMgaZ~KN`y*bCOfgL6>zM)s}<_*%o4og|z&?~qncK5&z?up$!u!DPI zcMt5~p4i<3JKoUF#Qs0Mp=n_Mzc=)MiyImyalWBfxXby5USTQk8+wJtf^X;*wg|qV zSLi1ChF;-_=o@;45t47{6|PFYp;wqA`-Wbjj^Z17g|&)r=oQ+izM)sxqxv%8pugtJ zgo6^zH}ndVbl=b`+|_+Uudvkk%-Ck=Mv-yRxM>8M(Aa#=>}3jOoH@f>Xs$M4i@6Vx zR0O69uo_s;Sia3k)^~r{xG1FFDzJ&hPi-!NI1FX~vm5(BFlrxt@ob`S9zEP zbb5m~CWTIKVkqpwkB(3 z5~A3|@@Nl3T$dkC<<$d=A33gJpgG(09@F5a8EAP+&9Kl~ZF!_-(FC{q&u#vLjgQ=a zZmAhMGyNEEsTmG1fhK*6Zu1|+vTw8AQZu;Se{S<1xZQtl^B>gY9rvHx{0DCLpWFNg zZug(t{09!4#KR^5xBJg+{)1DZZx!T!Qxn9f9k;Q6)Zwwb6*)-p4Tk7j0k11k7N39TVW@YP%g1@QGLCl4d$^Ar!qF6X1O+5Xc0) zBbSu81UJdVJ=1}kWa6Ibzzt7w&vf91C%I=j@IDpjPyjc{#68o2n`Gji>A+1ganE!& z9FobxWdtIW(X~Ywt%b_JfgdLMgaFo)d#g_scAjlhjgMu-olzlRR23Ae57cocHMsm2 zf?Tz=O;kwqUk`E>sJ|ehwT7V+9AcFZ6|EvOqQXDHY!D>foutCw3H0=wGV6~^DpEV#FN1A*{B^n2D9e`*Y#9}$6 zKc!GJDmXNbcl8K;wn1}A=~P|Ti;VBqx6MTFA(XhZg0GA?gERN&KkNTJw1U4HRo6nG zud9giAq2PacQsL}SVftWQ^`KpV&;!CXNHEiMIz?dR_oWB>*>@DZp$JCfNYs#IwU8X zSD zJPg-7L!=KozQkjpQ$$2W9lmMT(nRcMtm<|zzbYFygVn*U=^{s-8AF?ZO8$8vm*)kb zToYxaCgCSe@Q>1X&dEq!?Td|eupzo{(KX>6ar=l3Q5D%uwp470TD*91=49LnT0~Ia zFaT-h1|Z`+YFwm=p#$^@2FGmZzb*p%Hs(Fd*${Y!oGsHgp z7w?emyy^X>O*afc_&99RaU+Uo=MB-PE}l9yP(mzI79M#P`P4TIKs!1EXjn_mDt4vm zfLOBMV%+%&DSRr$T`TToqvzdkEN;e-!t~KccXQUwL}+&Wxp9Mv*3HA4Z*Am*qjBqI z;&vQ2t#_Z@FrY)ctGP4a*Iyk3&G!IvQS|qJ`cdPoOis4)pmZ`Ph4T?RZ?N*PfXVtcQ3L8?*s@6uE7NTZH23La_HQAWWdjXKIGc%)HB z83k|J5GkYJO&cO*6ufCeJ(vy4Di$RpG4en(;^nFzCeR&%!=OdsfDO^;4o{-FXe0Ao z?Qz)~qH-c!o^Qml!Z#Pc`DW%KY;miJTvPl9M6*&!PO)E;CM^2F+qD~!dXQ_!0`<5L z5bh`=*_GN>_6PRtDkiT!9;F-lE?t_u)M@EH$@b!2eRkmefde;06I=g>`xrjSA>V3^ zfEqRK`VZiia}BvQTmc6Ta51G`2d*7YR@+kY+Ez0sW>+L*!9Y@2N^d@ocOemCYh{m` zF>2I?=v(n$fBkh_r0jG}PS_GHqa}(;l$Y*ZjQs-}qGu&f%p4c7D`3~I3E_*9$F`~~ zZB`<+=}Bxl`(@Kw+32LN8RLpe;PLq|A$5KPuG|-;qhc^m;A^haI=gx-a zL}#OK{%S};!NY5}<8=C*{AHO%Q$)uZb0ZzmC@Z*kNeQN`07s zv76(4!;=eV;_J(-6B3k+2YThO*{CwdW}$(ka@Z9FGskANjzZLWYFs3ab5~Q2X4i@+ z3MeXa{0|P`1#-o&m2O)HiEoOn2d0YSWyl#ZpZ}QOBrnj(GrUfP(Q>Nvxs)>%zv_=% z+3^sWsQouy^;f3I`v(@vNu_eJh8C!8O_X*@Q0S!llP1Mx5gKyi{f!%MM$+e3QlN zOz=$>x3%)Tlf~t58`03$L#RCR3SQZ3Ep9wshC$auuso9b;{EKv8#3PZ)KF8IJ{y;z zB^lT`&>-P9GS6#PQKLd2Iwc~;)w+4U?0WFMu%KFZk$73tUTo8j0dr{grqz=qX+zL#bU0oQL8Rmc2CFjS8RE5lWw~Uq zYp{q}zj@*uT+POL~f<-ND^1F>&47Pi(WU$GUYjLvXD>q4mgCSMao}!@b=C zH~I|mwa4Htsg8Wo{^2fn+Xmz;)eK3Vk(~UH<2vF`DZBNJ({WgAA=V5={~*l9F>_3B z1nzbl=Pt2~4^x3jfxQ{3O|LXkFKErHRSW%C{8`U{bl|Kv2K4L1AMi3 zM<85AmApfQ%fge={DFumdH1|{Lrh%(E^bDzk|E1g3R9uvOfK5{_C%4KTEI^%1Q%;r9C#lPAc?OhpXOMY4EiH z4%J|y_P*wwl?GoM;Cnjw+5l@9;A;b1X_WqB13XTXTAh>*@hFpAH@1+8sX696y1s&HhTsW0#G0-!Xv-m!sb zDjD{(X7^L)t+Vz-6W%x7s11s{wB;TkjkXOnR&?pIr^_5h`x9MfTl%)*(Hw-QdUo?$ zbpo-iY$x|RuBo20hOpIw<%$(O|9rRS`z!kzp{Jxjud(a6hA7OpTau(WWCwOE#H6xAETU2%oz=(8KR$L3;EA-`>6;@!k~2^GOuoddxi1_!sQ z+S=wC)2zn;KRTv^yX0`M@u%A#Ws`WQ2upBno+AhVZ$ZHSeI%NV+!g5TdGg z#tah&zddD&-;{dF3~8!B#5<-@6A{{p*Q5s+wrD~9L-H^g-jNe!Pw~TL8Hg0#OzEJ! zsKhAam01cbQPwHmR9k4Iwp9rf{-&CsE>Ksguvy)!9#hY&H&lP^Nv*X8)JHd3o2Dgc zRI0U0gTvYx?N6;*dqNM_JL!FMZM?f&WxZs~=!1jBLj7lZi=O)ZZaiwnRHgdu(#sWU zbQn{0E$nn|neLeU?}mp5gom%STN<5>e#Qvnbvtj1@RqSb{LY}E9G2}{wrorlUM?HP zwcxQw1`ot-mTuiBvcAy!o5Bfn8o?EGBleMm6Q~~qjj6&e?tv&4hM`sn$IUl%5(|$T zJtZGkvEGnXb68oi)$I0?CGksk7FQI_KZUwPV>?K=gD$yx z?AQDr{zIed7W=DX^H0&!*1mY>Hh$2V4Jou1h;=MAgVx>6s=Q#29~E@Q4+rp?w#c-p zPPO54JIDUUm}PHfDwsD?Lk2 zkEoFL%jy)`-||rPuojNr$Q9x)b9cCFB0PAb2|q>X-RoX?kg)mHTlp|iIwlT#)6yRj+>;)co68;L zXnCkSQGQ>BW%7D?yPPK%%a`O^a%~0Z#_p{QR>mpsDT|af3Sc#-QmB+FRZ0!Dq57%BNBkWtK{=J^RYc^g@JB#tXl&^!O&%ypq;{Q>9=T#Lx(KqT%wY7%B|9fa8 z5stu>DZX(lzh3^z87o(|F=zaSFz|W>hp^#s3^M#S7VqEhx4(fHzy))^YkrpfO}cru zlhwTpFT~?rmM@QAUa#QI>jjN5Ceh8RR{kW*HO3?`-2T0leBOzK)zAyg1z`8J%l-Tb z@HhA7!F>l0_P>X7TD<~lrX6By))5>5C<6vd?&x_i)}POGVt1K4n9H`z)@9)1``g(cp29TYV+l+>+Md=ve%gs>99{!G7UszB&6hm&oP)UdTRRfC^`*KF1BJhYrGvf^+pcpnCjE zP6!tS52zk!Buo%Jpn9O|)=i-y2o2B;n=XAR?UD{l1fhXy$wQ$b2u)I|?4i(9%`E9r zQc|w~f1{N$tK5lDp4&Y{aW($gK*=L?r%!LA_fVEDx?G0M)SVB`#?iZ80s53TR3+^) z+*q*(da>5kpvtOXwcpB^7}gbo=%Y&NOr>J>$9Or`E5QENW_7w3=VL8IoZeLJqfEzW zeQJ>Q&ht2**DDCbS7Wa7l6G7bv^g3CD1>dEgT|G+s;uT~;DoG)=x^yWb>dl6ynzSV zFB7uxeRDQh|9LmfR9Qtu@kPO1_9HoKS{m3PY&>ojPNd?C)*l5yNb>+S(XyW?<;@3JzHlvZ~46Jw4z2 z`InH&37I%_UO!qfIT@$R30b%~398c@$GuGR87tfT*#u-z{!(l#v2GoiWsYYqmxI4~ z$!d)e#wPYVzjx7J(M!kLwfXZ_4I>7H+nxbEdv>#4wZ>Q%&-yb@1VV3nu-(06zVRlL zWjtYr+kh2Y_8ObYUT@VrYByu2S3KOs3}%N>T}=ZXK453sud+qVQ-{NuPD~XGuEH~} zJNFtl7RzW-I9SPT;&yXKUBU$LAv`?Ici|tEa^sMf#lsH%ApaYGjeo$CdKD=EHFLZp zBnr!g4B=a$K!9I_%fcO@uGmcMAigNZh%jE9B`y)yiQkC(#S`KMG0!c9^^^uoI(|I# z_=GGJ9r{bNrKQqtPOxjbqvIM7l@i`t|G6U74$v z&XzN!@1z5h3uj^*jO`-NqcQrygshx2?1+N1XZ_9|mp@ZlDPJLNdX#iifk3rLb|Gw+ z6iZXoTN2ck-9Rnuj@h?;=3<DD$^`TT`(-_7exOS}#lXwT z?v{lbAN)l2;Ew`6`e?!~SB&;}TfNkPLAk|xp0#(+IQ>1n`<4tHUNj5#q^d4l*YAC` zKTIV2?f&ald_qZv@v_;)7;eGDtERHNC4f z;Ccwsene56%EC$excPx?Nw3*L3c zl%a)oyl;jUT-B~#8QQ$p1b2outG{W6nzTAiwSiniA zqSZ7E)aIt(TQaYKVu;j|89Fi}Zr?t8A5d3d&6;LSK%;kjR!NCp$p&PO(6t(s9@HTI-FM%OuTH3p^qV-TA~IQ3)dmT;5Q1*z^GQc5 z^A{#)PheB^A1=z=yA|;b;s;5CPbMViFU+f@Pf`6pEyx~wWZI{P53`3UCw#Xm;lN}C z<|?TxoDt#)>5THC);k948Bv^QkkCCYp+LRVZCrzRJmX?Fojn*=7>CDnY}PMW{OI&P z_D${^f2-lfg37JRj!#bKj|mtvCQh57Ez}&BA+*x!o1g9_mSpM*N`pg_Etlmxa*)yD zXNOK0l=nSe;7*RjW;L~?%2MdNLa%7f+C?2 z>kEp6&8#md61sA}pvW7CITt9hJw1N{@m2niBM&)F?|j8u9Z^bZkf7`O?pR*oOA>KU zu`#`sO%V-BXap=@etcYYQTii7+4Kp^}8Mi5J>X7%}e?Mr;I8xUQr*i;pW0NLLjd}Uym!V|b>9|=Dg>mC%j#TsH zE~l#f+N7qt);b* z@WLP!@Kv}0+n)9jO0`&BE<=X=?FR%%h*m$=vb2?Ei%ljRBChH^tvoG#>JThX4KKTu zwk{48^Qkd`_#z6mJ~ZZOhx8I1zS~T#Q69i1ID}32tH0O;hp_1ZY=Sp2gMb;}5H>x4 zO>hXC9>69zgiQ}%6CA>(2e8={i5a086R>nJmi>^mozlUde`e^~JtZz?_k>)|51Kjz zRoZRr6*gk>wP2ZKMhu!vjlusN=exBb*H~(3O&ZQk=EjQ&tqSrBGxz4Vo6)XagVvF8 z`0m&!>^{U5iK}14g~y8Ykuye)JjDfc!qE}`r69fJi0~m-!eak&!`bLknHq!h!Vun7 zX)&9dDxT!2thtVWTjeNRlpJpoiEIS|HIz2zb_>MbEy%|!H0VGi$}SHRs^iy1?V1{N zJ_=8n5e02VWDKduZgy>IlM#3Uw;8!CEfQPt4jp=!5SbP|q+h@Me)v~J9f-IURUJQn z{=@lERNaXCpt7(u?h9@w_v>(!*}8U)X)~fC4Hfu^^y>KO2}4ecmxRJhT%>Hsxs4)a zW?xF<$asH}H6v64R*Vowz2ne-N57pSPG32S78ybDc&WFFES)(iCx2R8(42!*G|kWi zQE&d`?2NdK;Od~6I91b(-t2mKW*^+^tc|H&+E9jPy_dEsI}nGPjq>;MDMeJ{GayUZ@ljjll6Xt3{VoxNAwhNF zKR&ysKW^amM6F(h_XfFzy6|1PkZw6}S=;O(Wg%tGxe@YwoA>JDX?{*IogFV}JW z_*O5_f6*`Ncl5eOGoyn6FB&n%cw?5a#8_v1W9&EJgh7w3T4p1&t=ZEYWWt+fg1Nw4 zWo|b2n#auZCfqRnttYM47LFm-Xlt4UNmjb`rM1gCY@NaPTD1ikvaQ$0fL1pnF_cIR*7Wgd) z4Zjdyh@(3}G$V!3^0EY6(2U>+B7govfmS7<(e!km8nQ^(Eu`>7p?+L|=EBqB1^yM0 zDAX}gdn1x!gf-$;q!b^Fy;oTrRUA-Ud_eq5oG0EF+eoVgXfIL2z=sm$p7uzAbRN6CaZ@agp5%-|7*HEAaHT(npq*5!x3@zVeCO zvs}5Y(7wJbeb%Hv!!V9(&#Qe@S0Bs=YMJbbFWgnZH@>h`1K;>UWBq?iBgg~lbHob^ z*Sw*%W5e-8t7CDcA!#D?J(M|bzsW3P=r;f~ixW1tNuA5g)9iLD?-h0=JB6Lke$0l~*;9ujgYMr0OLnm%N{|&#N zKfzz%|K@86&`4-2^b`gOR06y}SS7$_VHv;vg#r8@!ad<}vAGBx#b|M;I8l6GTqdp; zw~LS`7K^TfL~0_nlX_!?9u?5j=2hA%{U8-eP%6<)T_NGACBG(*m7$qBQC=x;l6T8T z<+E~y44{N4PrGPHBb6!2d<8yM@Ptz6cD|-OP=Zt}gQrtznEH;Is4iDCRQOhP>?}?n zV+Rdh)MB*p+AM8}wody-+pob1&AX3rkPdI^3A(!|lzKwphVE}XX|y)F8Uu{c#>4{^ zyZjKbHPau5EgSIKp#s0^BUO~2#N~zU!ttO1Wj9*fZ_M;VF(J2L7>|@wR9|Dq`Ogf* zF)En-m(iK^0dl^@%w(vwVmbjiwPR^TNM}1|0`uqI-~nZ6MW^jQY+^501eK$5wYC5c zY8!LLNq}z>*Lt_S0L#&#p7piW+4>$C6%OwLG7AS;Z(0dgFBo&}TIT0=QjYzTO@CNL z<+`%dei& zOu=7#Qfw`D6C zNn?ev>U5Pv)=jEo41fxB5QJz?YhAQgw2|5rt#rOd1Kkd-U<=Oo)g>|B?R$0naX>C? zT!j}+zIOlfl`GYiWYP=X8(uk@r|!74w3}OlvJatpc~^UNcQ{tZ`6>Nfi-6U-lf4T1 zbq8)dPd#$*KZr0M+f9f+JkZNJ8*dv^t3tAI%UOz9o!vot3w`o&v;b9~%L)z-rgx}K z><||Xa*|=AE9YN2Wwgk)0|yME#C~|TyZ(zgR=;DG5=V^1CG7U&}@WvP+a`NqJlX1T>IAe+q+HiUPJS<{`BWkxp~ zt~T;{sw=idsjUWmsUv)CF-|QFgqMU^0jPV!LlZ3*fVww4G|`zNEEXM-g&Sl6PWRtH z$qljqUz%tu8GLD?J7w^tiS|*zmnM2j0jIRn!@>b~X{Woh6TG{S>A?+dl7$;&0dA6o zLlfPo!}t0T-J692v?uar;lQuPRl}Qw18)ZqmW^+rq&$w-z&J}SNxtkmW@{RfD_+Grg$MG}xg*>e0xA6P; zHK7u5dhD0M0d+G*++>P{67sU_;a)Q2jW ziJsT`Xz+$M>7RYfkJ>2>u4s3)$MjI0)1&m)^$9x6)|cv^>Dy3ODAF(LH+2X!8XM0U zy$k`pbu)~G2CO!=82gOlhG|q90cHae+}-c)>UVH=zf<*lOT0RupEbgI*P3T3R;Klx zb-;pOt*h33tDeo;5%x=VtPOA5bL@}o4Yp?I+b8XE8*bZmn5Im7hG&K_bdAAc##Q*s z7)%-S7gLjkr`R@Z4|X6cvhny{{FH^S*gfpe>^at5@e40-{kc)xR8HocHxzic`ceuL z-r(IS%xs=gn1EIapA;s{7JO5f5GeYlFk!Xmo5F-=B;OP!I7YJTk~@V7{bb)1COC#n zO4&y!FDbDKysh}AFyXf1o5F;}s&5Jtp3;0%nDCY6o5BRbvU;a5fu8^Frd>*5!W)Kf z3KOmvz9~%bwfEmN!Pnlu&;oCJKe2t`8QYg60}kBRZSU{QfUmv(00X}=z9bp&wfC2^ zaGUid$$$g*b=&)E^5ARl|C9%MLwJ*9;03{#Bm)lI*TeP&>K^s39tB@}{{#tW`QV+x z1YgGCLK#-ez9bn}f3k;hxKROL#$jg_d>MxaRPbdS#%e&_qu$k{a9i`OuZ6|BQ(x;& zVS+E?@KXbP8HcS*@MRqCLqEwDFw234_Q6r1GxUV+GcdHFVqQ;Ty&JmX38ic!|MggNnHQ+p4@Bb7< zswL-+_E56te+xzGL1Ve)d$_wn3K!cN@U<0&_WL*)X2`y*Q`|qhA>WQM{?Y!~LzIG+ zsxRvlzEj<-QwKf(FKNE4Q#h&lvQB}P+1}^Ce<8W!W}W^QlRMOv2Cv(`tkY6=a;Iet z+%i>%Wl`?P6{n!w5n73CSMCS}Oxu+^Lfg=TFy>tbb4M6E!a9hlnB8_C8c@mj#(W@| z^^N&JF!urD4Mv4b&Nt=*p2A`$x(%MfVkhPUzTrOuMXrB3(w&&kgLskIO!k#do%}k@ z!3?)2!u`J@?t>>q1oILT%lz*>Dcr@y?g;n)ij$&Zb}2rD;#1J|@nEL4y3`3B`PG=3 zvI^UpI&gnjRMrIEZB10x1m0~;RMrGeTN8EvtYN6E3B22ysH_RR+nT7X2~hInLb#_n zYHOmhCh%@+qOvCNZfl~9&vds>2Ga-eDS;@!opO!&H06W$m`_tac#rus<%9Q_Pg6d4 zkNGs^1C9A^E-+2`;63Kkln>rxK27=1L-CCHH03||St&{(!k>ogFF@@TE?x4wRHOu` zo-PoO)MWJ&)zbw6-p!fR1p?m9nbZXW-p!fR1p=C$ubDRT1X{&Y$n&MeV3Qeh^Vo6ev1dnNpSfB-8|HM6$#9u`KbwCnS0RU;x6DEaWoLKR}T+9Dt7x< zAUa0ljMY|{^}O|HVsZK-CSdS%4C)HDcYnlnyY!#_h{w_4jWn<9?AWS<7BzrDPkWHP zh9RbR74r*onR)Omd##+L*d06A9q8jY+aBK*{TX!me9F?>f@FGnTimJ7wc@y^$rv8Q zBPb6qr1tpE0MA3id1t^wj^V?22lq0GpV5h;&;3IN1V@J@@L!@skUz|y;s4~T`JdRa z#uGwmUtzc~S*Xocl~bf?j^GX${v}WX8z_S9pq0O~(%7&56VQko4m2WQIwo}BPUHAR z5&m*HV2r~ce@x?qUNc*@Vp}10a7&m>&S-FWKpq?r)JGr73yKE^bcZNX`;rh#3H|~8 z{(F=k@c|mBUSHHo4eB);{SNii*Hz+W!cx^2xm(&;yP~wxgl`(hvn*SEpgDSXC@)mq zE0HV>xIHxhHLf{g%fTyF++8sttJfS{qrtox^X9dQX&jHCp?YI08pq?VYs6OSx;SMC zT5yi5>*B9Qjn--{2UC3LHZDkdB~pAyrX4rNhZ-jwLW5PXj*Q(4M~|9EDL&LIF(7~q zp!m?KkPiC$8kS!T|JrGw{7t*IrLXZ|xN$JlRhbd?FsxT1t>QlVsM|+HArtd)QN1yz zLsaU-<9LhZXQgLPJn|Xu$`C!eX2*KXs?PGm%{m3gAfFB32rylbdzA}jzSi=ve|fW`>>g{mW{tT9aM92!@v+D3 z$6WV(VPR-ts zOqM>8HcIa2d6F%4!yh`8RgaLLQsD~v6_Vw})6qDJHBG*UG*BqfIiz`cp7JZxY{J$v z5x8NFkJ+D}F~p|)6Xl6+qb2Oq6p~428kma zXCkVC+wE)DZc-IF+%{$G%gBh2L5ouE)~Pe5PK}SLNJdLZo2)}Psrg+vUzt;hvHv1h zrPOw(*mZ#hv&`4NZm2!0RjeT0y21poCK~S>%Zyj7kyZ;M(wIJ!AGC36TKo`PUZjP~ zv{*pz(8Daa*Q>2Lo~zPp7*$KD9rVTk-L;ne6;EK09~F`u$f@3xO(|UTV+IY(!d*$W zeaP@L>zhDy^?{~n1{+PS5@R+~xU&L{dD-dlLuSwRo4wPb>M0BTi8k9z|+Q!)wwR@C3$Jig=C~vbK}`v2K9#iX<+hiy^1v!pAbpAdFWUj zu%05?08ev-ej^JWrIJna*i07b#8*8I3;&5_8h*&*tb z#Vc3luZ&3V?l&lSZ&760$&>a;a3V$L`o*?IkN%NJN%E88(jHRDjw=UF3`n;m$Z8V-!s877T_T0B`z18il>&4f) zVf5=rT1hjJ=$> zXO6deUq9P0f7*3)Wgdyl%k#^dii@`>gdttGY-^yLN4NA}%n18Ob4(TGoQ_1IRjZ9H z-uOD;>#ytN3}b(=gLL{r;br|%Ve^L&VV_oqGe?=T7=8d2F!;cBVLf|Y z+@$Sb53;|p*VqRvmCmg1n;#a2=V~49r51QQXkp=K=ZoSb4wAV~IPaD z2@A)vk`*&WLt6Vthd-s<_?Jjf)Je0*U3UeK=t=SmkK^|9PSly`%3X1;WD$>xE>s@k z=jVvke|&(OE1-$>+^qR>BPDBIy7Zc|Yif5HmYWIUVC91J+FR6~ebfXeNYP!rqt(?< zC>N9mHJIuNI5lHYir@YSIjqIK_!PBNU8Ve~Vp#aKw@%A1YWHMUH}+TL&dMB_wQXGf zIOBa4|Fiw1QmCg|?W7kd$F$OA>a*s=J<~F$4Iy{V-JGy6yr(AUKkBFSq>mI*fo>|C z(OK*_`ga~jR2-s03wl@Pb>})-7p%d?UgPkgS+hcCg@xlCb)fKIJc2%&haEJ~@o7A5 z_BDr_<4)ym7Z;etV_c2Q$J?}tZ!@PjL%Z?olqplT*-+n_pc208Gqsy^#T+An!0bdm zTOH+JR(nOW!fbfn_U-wDA8p^BzdNrp!CXt+<>H9uD(l3%F^;MD%ryY|lNoO<gB{Mj+xV=1xoDXy^a}zIsT=qhRpZFD8;Dxr%uW{+{ky?uKm0BjtdhR+hU~Su#QkGcMR&S)W)$YjK)zUY$ z0rCP3Z5cey+7)yBaUhsijCV0ZJ_M%^u)<=!UF(ujh`l6xLDGlS602y*~s`nTE4J1or~by+7O? zprRcO+u*@E)#-e=*F3GZ_9!Cm#eBuw&||}fHpTdW=#QGhe+&|tPBg2VscnkzCsST=1qbhvYqcM` z#LPz#r}Z0{w?5W1t((o?I2myAK1r037A^c*Y}vlaFPvSk z4%?Z?mVUh$O<)VzuN!rbh)EtEFnstt=2tc|$e(?ZZOxW;ZCb&!;Kp&&pTWtjS)1a6 z!8p^b;8s7Km|57S2<44E4Vza61>FrASZk98E|2t7?k{d0MsiV5eR>@`6umZ$dvhJd ztc6F}Z}|%L2@b-!PMo{)oJ=%@`*)%VZHVyE%dfv4|9Y=w{%vNZ;a%INSVsE?HO|ab zNmLt@#XlitF=x5H;+I-!cX6(GUOTLB#aC@?vq`c#7-z^WBVFE|S`r1;dP+{MOwXsP zyRX1;A22%M@_H{#q(d;iJDIjO36FC@a*`A&H+xz3-+&LPHpOF$wr-KBbO8eh5o+E= zH7bZ2r_al;d@*ul=*Tw3C=c8f>nj^%+|z|Bqm(V%Bc)@^plx;K>CI#^tlnCR8sSb2 znyM>ASx6JU5TaN?oq%S8-IN}$i*}I?{EIJ~9s^FZp{LjooMuB$v0)xH8#Xc9nTefO z#T!PvF==mB+${Qa>?!I--_?@8;RD6Ov1eKgaA*l9dx|y6q{(DN{{yW6J=giHP@LP2%&ipiSwY}K3 zZLV$(pH+l2S#|kkS0t%*YXh~HqESUgr;*5Y$^K#kM!$=QLJO*&--Fn29l9OcRO&eQ?+H_U!!&3!~8 zbc$!p;W*B1th!e7HeS&;tMHKuu0$4ktKkaX-B;`S2jjEQAU*Ob)9=a5OcoPLAAQum z)_LXz1OA~^_BU+9dh3`!rD6cl4+q**3fTm5mwGH8&bkJBn zZ#qw(eqV0);`FH>d~oiA-Ndm=udO@1S4i{PvwV+e53rTD3~fNr|Uy8C`4}#CN5eqKu?}_)f~7 z9AsaTA|H+wr;90Lnw^$jBlCAXb%y-Ul60+IU(U6)H5oE|E1zaA$&1*hg#pTPB}0L4 z6*6mIR_-Wu)n;l36<$!v(ox7LFPx2sb4fb-8q1IN!=bAr{a(}{s01kN?COL(x63?io-zOYeR>x5?KHHXzKw67lJxh2;+9#L z>P^HGGpx!cg$PwKxQ&NOSQQ@KAR}ysl*T#B;C%VG_ylwA#jM~nLps0t z!unZoyJJY^u##)ydMQW$Nk6@(VqzuAx09+cjTV$vj2in?VV^KZQqhYp1c(hpXRo}I zKg3sDJ&#Ft$y16IaM~%FsO{9=>R@%83h$|l)HUi>^#`?39WPX=XD_J@x1p#Ok)rEE@T_qg(37z9tO+z3w^Et+(gWT^D^ksk`;G-Nk;zuEjQD$Hq3i z->~6^Xj1YwUPO4%g$vmkQFy-J=)A0M$-$x~epEXYhzjJ*;*6+_AtUWSZ5V6sunt;Z zzI)AlfPY?Jrp0h3`oJLWO)i1!dY~#JDiGz;_A&Gg1+gty2x3|=#nvV3mi6+X=x!6s znqA(L6N(R@O8=Co91KaY+wJk}EOrS?k>bUyKZ74J45k|5JLFED&p&NJ7Yl#)HMPV{EH6s~kq z65?j#akX?D#+Ty9K~C;|>4bDaa@XNOPkE61rko(V>+s;1d|tjG`zut3_X9UTnch>G zw&I@O(l`{V$0*=lG`k%s;I^cYBjt589CqEO&e8Ri_#;jWuUs35vdPt)9O=^Pim=MH zdBe(5{ceRF%un^Jo7t~lXuksmC_F43R}ghD-^TG3Xoa#E@pg4KWkp=}TNgp0tjbk; zEAd%0lS@@MW4h^Kdga>a;JqL2-Mhm7VE!%ck~VAO>3ye9NB9$eX%#Li7-a5ZvF*GR@>RHgSU;1S8IYN|A-va~^oTCmXLb%Nl1UTCS9{6+vs)u3 zk}6cPcl&nL6>gdk-fL&`facBPvJRHGX00Pt8c>_?dVPEDxZDou5yl)(>0vKSKx2$&+_a;x&h(Ax6^fhle*fji*191eBCyn=e_h z7F8LHvY?OghLL7{VePbD_^rTt{4d$nsr14N?ai)NU{LV>2=w3+E*Ho_F~OQ`wK02` z1I_XghQoHcDR;FnqQx|{rBS)5v z+{m1)u{CaK96m~t)^e}%ThtlK!bJ&1OXFq)%$O0zQmX~cI-jtxlRd;X(4Nt{ZKr2+ zFYR$X5OogDlGIXY#@BVIrHPIOs3{s_FrakJGfMi)PC4)cYm15f6nLd zKk=veKX|yuKQ1_H9A}FI?lsPQ={++hdsjZ}^*btf#Oi4xcz`F4SPdTF35nGqY}e1F zbOfG|R1@8NC+wB(NF=;g4VDKk>M9 z$3^u+QT0wQgBW(y#+tb>blv z=^Jr^Tbqtb6Qp4^N`LK;c2g78yV`9P!gN8WMwNy7Np*$3PX~83O1`<8t8;LB<{=d9 zw&Vr+Z~t6fQs>S`VK4yGb@m^%yntd!v&1 zg7s6dQ*q+0qOz#jI3mocmL#bx8ZKzZ>|yxjowmt;|DKY!-5kvvw0^VFne_p`|K9EQ zdXc^N;O}NCcanit#tTM&qbb{-eN64l{>4B|{QRh1Aea5fJi`9P0#PU1a6PzzoXC+@ z2cL3ZaeKI*xpSPw`SJDnJ4M1pA*u@{n+6388WhF9%VVE0Pg*k^KwKpeS?dW-ndSjA(TevDT9Zmi$*8q!;$~q!6MH`2=i{pPVYe$J_*6w3@o3)#9`t^ypK#z^A zklM-6TOKTrli!mGl($v>K?Wz*3yT}dEtE**Zwb2V?GFdH8jt7RPoxF!Vu!=%(RW8j@gF@w9>UjVy!KjhRn`GK5qj~>1b%4o( zKcT+h0e}NN^n36dd9iDTLCfbn_x5>-THL=*9ltt#L~rP`4+?(uFxKQq&itIovWwnpX-~11K*)<@xeCTB%K_euE~LE zA)CzI<}^NuKfiOEzHJ*t(vGJj*-lanTJ~t!@<=f*bkFG@7+9vRU`oKL@FDLwgqoZg zWxj3(+b!*-<~|!fHFa}@?$nTOG4ZbJWeFDf7TjofIBvNhPPQ8j4{kQR3k_c#nZG`~ z?7~g_D392G-N=}ckx_QBGFic)CFTjpcOuBg<)Xd^gr(3NQYR!}D79 z;@^GyhW3q%#LU$7>H-#?3q*x`DeL~S;9ZoxoQ8F$V14=(wjTd|qg!Dp%H8CWJkW4N zl-D@ZLDkOu4vwQ^)LWtllKZYs7eBomuOZc`QBAyYz1Yh#IdNmZE6}yYC ziS&|(6mg}vN!%?S70-$lB1jM-JuUf*yM?yW6luQnv6Pf0?T|>~BGO!~nJyTA@7}#} zsrsIc8%}~AKp@gUYs#<7L!{aAQW-vzx5>I(Bwv(o%7IE_M3O4K6hVnoa3WAvD_a!U zr?`R6j;jnfevIn4%7}q`M7{C5N(7Ob-D!8Q7%#w@+6!7}L3r6)J#c-x9erPZ{Lk#2 zb8L?15sc_Hy)c_@&1$zl2@D$zvzR zPvH8l-trR$Jo}4x7lra+YG&1?(^EW%dqRmxE?p2ku2Kh8xe#;+AmhIQWL!&z;~daDQ{P_(ptN z9(wYF_&50kegVIV-^}mj;TV6Ozrp(pPYSJtuEGFRu7znrl8`QZDeMvs3n*p(DO3wj zh~Z)oQ%hcm@0lQx`q9FB0MfNmpV$((oj4_-j|k1uwL3O<#(9`f$ zIN_M#RybRmUCjX|j5ep4NhoEyFhi)yz@KKd`GjkN>1z$QCR;GqO0_<>a?odb+9IDR zJZ}5?Okut4>obLRjN>yUPayeB;RnXoX9};ezCKep%li6EVG8H#Gld77ug?^g^KPH1 z!()SHf-jE^z7c$RY|vBm<*~sr(U->tqa|M+8#r2tM=AkFEAdDr@VL@k>8M02LzRgx zVFcXDh+7x|w=&`uMu3!&QngC0p^?F-`~O$$Uhro3ZnpMXK+fPBmcRX^-P-PI53pgh zJh8OTxvEom@9w*Y$F=5KM=e@&_ua#K zZM#N=_wK%XXs7qq2kQj>azMB6!+*42182V$V!He8!CiRo?z@KvW{}mwinJVMG!Yqz zuD1!PqL-~ZR$UvK*(9FE*yHV4_7Z!Y4d2-N?GrYcTWT?ln6~KWWd<>CG6~EAW)-uU z*~`E&h860j;hvx|Fc;skpL03fPuywl5AGfZ zkMqs>j(jvfl%L4I&oAR)J-;0Z;>G+W{uWRADzp=N3xkDm!h6CZVU4g=08;o%g({(j z=v?aH-0Gf79h_U8F7+EaDB24?u!|vUh+Tb@VL?3=x9V6Lk-8?2kVXPMxH^etXoEHvxy1q%--f;bDT*K ztu^LW6MirY%~G?KhLBhEV7-O#5X(_tYuioG&1DmRa-991P0-1$HaO~46`B+q zGS4#I(M-aOWu`MJ%t~exvzs}}fMZzm_|?Dxk$C)S@PG~CT5yrv%iJ)I;3Ke{^Uy~K zK9WcD5jQBJ9AE{n@=oU0iTpyS;Avi^$S-UY$WP%kuTta}yqi}k@(agBUr#ZNL0QDx zQw*NWuM_!&d9orCyT;wY0-nsT6Zv&@qvR`O+;t+q&|c-$A?jP|Ox20}Lau74W$IsQ zP0fk?!az;b;t;W z*|Uv;71Zbj+wj>|WIE3_mqhtre74!Y+u+IkI+0(P$0!WBJ`ONWL>X>w1x*_??Ps*)jpmGpm#3jk;@|W^184k;5YN9t(>T;wa2jH}V=P<5gTj@c9q!)md5Nxh{)ZH>5YjuZ7g4ec#!w5{3?TA@~| zRcWMD!?SvK{WX28j>ckrrM^jr-TG1etX`pm;R1FV@QN|gm}1N~J~pz99mYWeelxBa z4~!smqPljRCcI-Nn#;`$^INmP{KdR%!X48M?1-_(TeB=!Vy&~jvB)BG!TQ_6P^LGJ zgK!+M+1_g(v(MYaJSI612-@l9aS)CJ4l_;}hnv|6!`aEKH?tG|V2P*Joa@L%V=2x= z4hY)m&Fln%c6u{AVGX~P_hxp&vjUY^xS5@s1aR1F6#|GM;?rUm5ga0ws{};cAs!Tg zx;7q&K~f7TQhHe$Cc*#1-rI-yP`~~E=Mo|eigL52UAbAsSRpqt?G};Nv|AKnT6cvQ zyIMkwT_LyADn!;;xd}1tRw8LEmJrjfR;`=Hu9lD;OYV1fzUTR#oo3$G-S_wV{=UEK zy8gKScpV={$I;Q})8{=i=j(YspO5ET(p0oTkrqQ$0p}$M7MLf=;1`(xma8i8h|*el zTIr{}p^!;rnF60H-zhG@_#w503Z2y#)YsMV>P&Tsx=!7$!jGzBpRc2ZYvlce*R(O( zd)i`cjh3nH*G_0a0Kb}gQ@x!Yt-qp=(&1fwKJ6y-J$kPGhkjFs`;A7%6Gjh%n8Jwh zHBi^tY&3%s{22Z{-diWYpM3B-0p1ndbwaK{x*WK=+)Lsx@f~rF2o7=V zn0QvaCf+ACkOD%Mrss^5%o2b37Ez{t0E!YkO!E)|)9fIZD zUIzGG5u|_sNg#d=ip9`lw0RfUg{0a#C zDc%+R3J8z{;#WWrz1&FlDH(xz&D z1q4lrHFUoM0wjU>6%csDAd{D;fPiE2@)Qst3B<2}K){&dQ$T5z-we=Jbc#C)H^jso6 z+(t{QUjYFJN$)8j@Q6q)Tb=>}pNrp#egy0wjU>6%Zf^#IJzByDSBjwy}HI zT=oz4CJXm-jX1vo0-tad#$@gqM+ykE;wiP{DIh=+h+p)^I+a0!D|(Xxf}Flff?ojv zq=kxpw*z3Wn&i11CQ0ytv{LdbAn=HcAYPxv0X~<%ll>M4APK~;fIx89PcIdMyM9in z@TYoL^(!C{-1T!)gZuSHx?cf-PxQ^YUjczuMpwh{Foqq*VZ*P0KyP!9=~qB-J4;3u zPXY05XB`CuNCNRIAV3m`UjYGP{_kObmaK!79=zXAdzf%p{=APK~;fB;D#egyw0RfUg{0azodksec0dKG2C?G%*h+hE#XRq;J-JqibNg#d&1V{q$D`0g^!c3J8z{;#WYxji6%csM9Ao+w5FiP}uYdqaAbte|NCNRIAV3m`UjYGP{_ zkObmaK){RaISL3kkv&fV`S&)0aq!LuFDw|I8o*@@>nJiG9Gk7qZYAMogS_Tb6Fvlq`kJp1uv z<2iumAf6xb9Kv%L&k;O7;W>)u7#;)9&vp7v7Eb}5LOkd2{DG$k&v`r-@cfDABA!clF5~$N&lNnycq}|u@s!}XhUYq- zzwz9_a}&=kJh$=O!E+B!nQhyp^q+Xj@z{9aeh3&HusRa$StrKH2)v*&<1521V4NgR zs{AhEoovE~IQSn5bfZh@`w;ml8PJ#)nz(~U{~V^!yU1hZ9VC|3orM03(8TX~hd;7Z zJ|e>z*^)yP4^08%6j@1C2u*QN$yY8bP^K_ym`beYSJlz#H0%>bV^xN_Pt8-wH~4@C zp&F+}X)kLdwaMB%?Nbf5q92RUr8l%{dPDtj9lGm+9uo|IuQ)5(7g#>k$x>Vh$?o^McXH-jt5bZ&&IT|LY z0ehS#Yv=%U8nE-V%NiA6qXY0sof@!5>(lf=*ItHBsa~fbj|#9M%6QorX*dnoTMgX+ z0>cm&rlI+`+1(UOh{tl++2(R{lj-DqfZF!zTP-c80ZOs}bD5UYwnyY}+d`K{GrObh zlEW1n((SM8Z2MRHqJ7V<#jp%GBr0l;T)?C;8UtC(ai)m5#Z+g>&&RV6%MNFg*tzTq zb_=_kHCQM>L!aNz2X2eB>*oV9^fl+7;`{J}`Ek7b^eyCI^o*legH5m@OwWK#AO*uA@K zcl}`$_-fXSZAM}4Eb+KlG_-hBELxAVI$_MOJS4iJ`nPM;gi3eXqp>ASl6mMU5rF4{ zbVqtX&XD#=XCtuZq)50WRC(qi)Vx=-Y)ah1g%+%6yyD92q1Z?=I8NRng6r9Fw|fvg z+x{j&a69B%G6c6n-j*S_9r6POg4-b2l%XXwS&y&Kzqpw!*yj>c<}!SLgRIV%Si3J^al#_9bALG9)W8ci@*_9uteZca5ka z{EyLNweh8~*Z9RaZ;;9Xewl+*j(=6s{C{BdIP1zBPgKSp(Bfob8${H`haLZj?5l`M z7*;TdRvy7jyMM|QbqYmprc@mh@&xa&C9uc#KDmPLu)fA^(z3RNkn^?E^-i6(GRz|Z z91XZ*Dxaag|+_+0Q!JwK`0BB2xsqei7>1^-J;la~H59;*sln@L%q$ZO!)Nc|J|aX5R!7;c8yNG`dH zmy$nYaC+(wE9d26vh(TL_GPU496Wfd{or3VW}lJxc^mZ5(0kY{^TY#bp=qyG-oO9P zy4GN;A+zW4nofbxek=FlzJ2ze7bz zHE14%`)y=r{sBllD4&;0!L2n|yE;Xm^>w9!dBi+elv{gV4(26$>brEREGSMpiAlhM zOzMF>q(A&4jt2#qIXP)LXHFn`p}z6_{y08>UU;;p@vCKHjZZnm$6p5m-ETDrdQTWY z)%cz!biDcgxuUR9NTaKkUjc>#X0QSb6c2XuIivuCV}kP(U~o)uo&pSx3C>f1!7;&k z3NW-_gB4(KOmLn8486Eu1sEI?oTmVTV}kP(U~o)uo&pSx3C>f1!S8G*1sMF!cAApG zF~NBXFu2ZkR{@3ra&U(_Q2C>ON`^^FaECfnRf9X!%a^PmP6Xz0Ex<%+K_=b_Y;YP| zPnV}I!#oc@*d6{Jow-CU8l8!uPq=`w-MnSRsV;0FPi5Anr`rM80O}S6=K^=L?X}Y} zC!+u+_aZj`o_093<;0dPM{nqwg%R5vb;7Hk_b~QrhtrdjujcKo_Qe;M%M8Y>t{*h= zjkCXM7qxpDF`7~RurEN9Cik$<4&N2O{@S5Jjr{9XC^MKdt<-(_vmzNDlT+b*THPVSPvX3d#3MUyb7&}FSC-VsM? zgEP}8D9Hfg9Ezq=gHPh@W2woADrloz{&3>Nw27(I=sIt6YVwB@kx4LPz-;0X$fc|r zv8D)vmbZa#+LS&jUwkzbcMs|qwUypNCD#bKbMO8&{bI<>a(Ls7>rkZrkCec9(ZGKx zCGe2Sf5sDYAfLa?m+_1MVZxI_PvKQzv@lIrB&Y&p2>XOQ;ert8))hGsqQsZQk>X@= zp7^P_Rn*0qIpR6-hFDE%C_OH9AK$@7)Dl4*4o*CHu)8$&ZG4fWrq~$r0gR2oWWCwaH$7ja(+0~~{DrNpN zhGkC7%uH9tjzGLD{(bmq0b~#?8g>DTP-hQIO-8cCj;#5Yk_W`&Yb!Ew12O>!+Y4i` z!8K45*XmrWR(Yccj*y-GXVX3t%218F@3Zadm-5WL@=W!-{Gq&7ZlZ)I7oID`{=QDh z;YtzuYhJqn4?IxTT^XyubVX6pm9La+Mgap)>wl!8n4A_!?h%BuC_wkq5+a$wF2$BRz-hU$6j|GVsueY&}ZpO^^N*Y{fG`{ zbW0C09yFXZ=wJiJ8M2XTP+Jte5-%G-@5eBcI@n(|N1M}3SY%R%8C95FFz=WTSP*J) zR+RO!MfvD?)~6N_@HWRfXWg)>*$wT-v0L62Y|3cQwwK$R>|Hh-wN1OkuFTYDS~6Xj zzW9(b5|hk)#H?q&Wr*elR~VbA%Qj;>vd^;v*|988RbD##6`Rfe%3fseu|Sy1NbXs# zKjOWna0@s{<1{XdJI)nxx47zjV;YsqiL->%7x4PA_~J06&7`8wG&?$-$C_=#?Oq&K&{HN{1jg*Mh4OpPRn%}=P^nU- zf?fzrrVGdn55t z4(l}KZd6}s-{5JjPC1o|oHRViUGKX@=|7QfsPj)=wigWiAt>X}58KG2;?zyDw5 z?h+NBOq7bJ4Ey@)OC5)O{`uv%r%0c^k(~Vc@Lzv@TKfOxiw(ssL0*1erAIJR|fXA6#P-P_rMV_Wxjw&2*-y`3#Mwsmi33k0+9 z>ssL0*1erAIJR|fXA4Al@#|VZ{0UdrBG)=Nwsmi3yT`Gu)6Vv0={LE4~cI-l%uDWhtgc>!<@J$hKThiQ; zG{9=`Kuelik_K)|np=_vZcCb5k_K)|np=_vyzI23xg}}fwxqcwY2db`xg}}fwxqcw zY2db`xg}|c7Ia$D+>$gC21(`I4x;zNgB8LgxxGiaJNgB8< zX>LgxxGiaJNgB8LgxxGiZFC28e0tv_fjV&k2IluWpVlVtsN&F~w+R-(BeE%3S9 z<9zRm*jr8dgiuI5l9|ZNX5227nkI9x>g?HnG;72^#5S#O4ey>7sDDp)OhH4YE6zyYegXTB_p;!aGp8lBLNp~E9Fhl=PU#owuAJ82~ zAk;PpjsBc5z;GOa5UiCqF`=#bj2UN+_=kXc_6PH4lPrOEb1?93Lm*~dx2{cnoFs4u zDlYDrPg*^Z$$NXWHO-oL3GXg|gD@Xe=j6OgII%KBCYxs+v8c%DY>4d?IYr&X7ruo; z*Wc-9Z^6;)M=wO-1chYRn>B}ATa0P@chRZx3VKJ&&)PrzbOEn9e`A+P<9qlf`1--B z8|wb{+xKi!rX3T_yutu6Wacxgm~G6z-}D-s?D&tHUa5o=3&Dev9dLjTPIkZmAvoCq z=Y`;82TT%!lO0f13Ql&wGATIO0WIXhcc0dC?IN1Tj7xyPSppy}t>;PiC_>&zlzzj}yz&6Ie=|VLw$|*^Y(Mr5Hj#ZF!8GjW?04)> z?CvI90q!O0HjBnKxu-~a-&{mBj(pads7{w+{XaIzx^)I-UR z0I0{G?D&5H>T%f?0Z@-W*#QpR!ed*21Gn&!9pJz%ykrM7u!EBwu)z*ac0ea4IN1RQ znBZgwIB*Lu*#QpR!b^651Gn&!9pJz%ykrN`r-PFn;J_`sWCu8K3oqFL4&1^^cEAZS zIN1RX+`>zCfCIPik{#gEnA~IsIB*Lu*#QpR!b^651Gn&!9dJMmPIkZmEjZZ$4&1^^ zc7Ox7@RA)+)d)^@fQ#>SlO5o|Excq0R3JzHNp^q(xA2l3;J__Bwgrr`gOeR_(+*B{ zfCIPi*cQ-$4Ni8z1~xd^0d9$!o9uuCTyU}j2Jpej4shTWUa|uw3Bkz@s4500J7Ad@ zoa}%WQgE^ZwoAdu4)Ak8X^aDx1L}@(Gaa~v%eE-8iPGjY4HDE2?LG{ZgXSp@sI*NqKMIkwlQ08Tl!d+jrMaLTdWYo8>5Q;zLk`)pxm(6w*q z4|bp?6I(LTY&TupBD%H(s3HYdp~F%sxC*_z`HYI1P=|Eba|*VER;{QB4asSa-cc`S z{okcq`8IVcPu%aemnImW8sy;nr`gSQ@R5NJ{0=@c@PXgKM+QFdJNU@J2Yv@18Ti2O z;3ESc^k+N=9~t<-@8BZ?ANU=7WZ?VX6ZydB;KS0{&-mLUySJGUD8{VZp@Y|@*jE6r zGTr%Az!f1_3@DyH6ou}diD>b&1GR%#aAwnEOTA$>ic2-gMaoc9$8_L1xzACsN zEVo_}2!vHv^WfKes7NSXBlz`^HJv-NoynAXC?JJ{qlJ4?I5=9kCxru%5s3!tO5xyW z;hq!@ju!4o;oxZDo)iv_7Vb&m;Ar8V6b_CS?n&X`XyKj|4vrS?N#WpV;hq$}$I-$A zQh3|>^F!w^jYHyTBuBtTn8gJH8zIQxi9e4C&Q>O;6TXC(#$74L-TzCTF?y=j{9G0TT)PvT##O22A*QSdUZQb4M=CsRA;&|XJhUzwuz0l zuo_w?Y#_2Uz2Ka3LD`PSok}cooq>)l7X0B-g?>o2*jMeD?oy>bJD81V@jma=hHkC5 zt*%YRU&3VHLNDj;2Cu&QDjYMkfPa{a!S+@m zN_0Vvv^orc9G?=Wi%&^?q`|lgfybo+?m9P8`c=%w;`cKWFmjmuq})?}RUR$3RJ*L4 zjAD9NRg~kW$goTPMw%!cmEF2${1_dTBxR)7j9ITx?K_-Ot|+!rS9R;2VXQh`Rn&CV zt$RkqcrA_9A~hF84*uSEs(pvXdK;bBV|BOg8Mf%Vb+`AOYTu!o5o3thFEPtlYEbPv z95K!qmO=e_%}uI(FCA=-Jb~qH=wIn}KP2a&Ln0=;-y+%Rzzj=1QJ$PrVcahrm@*1c zlw{n$)v8siO()5?@77-SQOXC;biMkUPF8sJ6Ip4UliYop@|0K{1 zx#=VpLsm3H?mBiXITxEDV-_#c7cIiY1H0*DEuLyXr%#UwPtG}r3;9UvlvQ-T2ew%{ zWtO=ixkc84_963>dByzH+G>Gr1ws_%xpe=%vf6|%%@cMzrbk$E&RUN6QKcW)17=fQ zXye9ZjjPw7cD)T7%s^dea&BH;NnRwguQV~1Fo(BrrJsBPcW+P)MYEA9hpTV9LHR5o zV8&4PG1gJ{cd*dHUSnt4`|Wz%pY~n5CId|w%4NNBs|GisS#(&>x(9L58_ykSbvFbJ zqe)I{wap&ly7A*UkhxgfiFMEqxFPmC@@``@_5VznkZXGBBF%iIH+&YNcJs#tBI}#!% z<3=g0@q#!^1}J3uiitZJd3fBod*jB%ILQEe zT}3kB`tIFz+rJRotXVUdj8@_FG3fETv;7t(0=n#_SIh-82i>XEJ`3{z6C&hYdW`(( zegtdA#Mu?Sk8lgErP*=R`zTZW18(?3X4Kvsj|PyKxbl$gAziaBph){o+}>EsHgwLm zJ~FzTL=#e0Tuf{=^q6(Qh)|gEq|wuW>qZsxVJEopduwxz0RyI!0(4mVz?#GoC2hiQ z=GxKYiwd*w)mRW$`&b69aI^4#T1;$iR+ITwlMA@u%^J2jXIp&0#*7}vw5o73eoR3l z`D1HFLux?Ev@!m_dfZTBf{}8l0YmIW@WT_E7@e5gz0vD4p)$1~SLLf#1*{d?Y8xCB zv?XO|hH;x&%#xxDe=rVY(b0a;{o~>jA7M9Jf#mpW(pq7{En;3a$|oeBBNarD_A^TS ziJy-d89+Av4gOv`G~VpWZ;!jjA?;h~ty)n4EWgw0ZmU-^u#X z_0}K6vdN_Ada?D=Klvo}lceZDQT4Qhiz`Sj@|(J}&oyA3sPXKYq70}GOk<1N~J1i=vA(H2{s*I3(&wnd^H;YMM- zSeyE0$PiHthmIRoOSVf>;<=)P`n`3&LaVM})?si{;vid3*bWr|D%rmng@H``m%?4{ z$6o`AN8(P3+8<-?XKUX9Lbe{Ody{F!o$s=^q&-*sI){@|Y#fqv&u%&~tfY0w)cT9_ z5EFiS=ZT>a=ot--ZrnJe@#wpgVhAMI731`)86XTDMd=^9zHM}i)I3m)l!H**%%^LhTBBBw2$GdlM_u%sG2}eYl^;HK)G-fsp zdl%3I+t51tD4GMxN2lP+f|frU)X z)k_bjP0FC&-zT3;crr=d^7V!c+;fgI%Vm>lzR;+!^T!DAV^nBeSYjWcC4)f}$DXls_<-%_n9*5ekrl7MVU5&GcL#nyZFeEla58XX;v z%K70H#6)aix5C|5K8bHc+Mqg-Os4qz%IMPwX^%amXtaFkC8}w}0X6tqtbI#sspW*~RuLAFp0zm#7bM<5?hp<^6&yu5ai5 zi?B(hB(4`x2N&EzliHa|;o;#Rlgx$>Zu5GJXJp}v07EA4^{7h$i{|xkMSWCyR$kR7 zv2_xLEBeS2-~FK52Ol)Ahcih>PL)>;Y~4Bu@A>KSukY^ewtIK=)_Bd&mLE_Q>Iprn zekymLv$68Vjny|?s@t`0x%rOLT82-Q&5Q2JKPgQY%?}WYp`Efpe!b;QX@uHndMEW2 z=Inr-KPW${O_d$XafWPiRITJ37@P!^OKaJSpV)8f;r5-hYRj(+wj7W31-rt0|`U-u4IbA(&6dA|Ou*DG0PS~>7 zY-OD{@fR!2#Li1=ojJhzTBGpXN(SuGdSzn@=p|UMUTD4M_3+COxDRZTF_A>y=o=_0xT+gv!AHTi9;64IDKx~L(L77q&kTDdSjNNOi@C$i85gR zIaw*+vXGqOSksB@!dr54@hNeWLUHuI7z$QTi8)eVd4;+~#oLYy>t&J$rin+@ZrbjZ zDe?H<1NE&ajGT8gx~Y(i)gMLTF6?ICqBYbXkfE0TIF@2Ri;?rbTB?3ZMU|;g&yl~< zyXY;Aj>=>d^%gfmB4-cdZzWo!I~h!D z39PP_t)i^Vv$BCpV0G~$;1XC}D;u~3Ru@0A$0e{5egs?CNTR^cQ~$jOvEVE@cTQwt z$Gp6f-RYkW?X6@e9(8tz8yPuUP{C*@()q#)}^hRJ|4gHyM@co{A@dg zk}$g4=+Rf^MS2`wqeW6p-4C&a8H!*>fq#O~U<3#jeNzsSO=8?!Qq4n40yEIeJ zJZ3)dC0naSi!hny5B#>(;>w?YEFG=6m?kdG%j^|KHoMlXFSd?vQIGp0BpfHC+Uw_| zo`EH|kBtfIm2X$nWWojf6mH_o$3#)wQTO*_+(SHm`t$lVp4hnYdhX$N_@Udn_7-Yg z^}FH>MHcRA**~Oo@5HU+2ep}56^$*eyD#Hw3WM5oN^LN)L4ySD+g4~Ezr(__d?+Ug zQ{-;%9pG09mylZgeCx0=!q4B14?8AZRX1l`AWctv^%X38!~eVR+uX+7C{SHC>=acY zLwJ)*5EgLFrF+;iEcw%=k8=}9MV~Tk+dRC1Wk&}}4Dr5NBmpO1S$s|GAUBXY^DE^J z5)k)vZ=k;7HeZfn0Gh5kC`+Vu(stW_EW(-&27-TL+Gt1MZ* zJY;#9!m2~GXVqHja&El_=u$*idiMBb+DrO1?j0Q*C~9xht@{P1@7IHI!3HB3#s$>( z`+qx%wS%Hq;Z;xt z%92qTL(z~=)x&+_P(N5-qe|*rjE;Wi)@dWH{Ae`p6 z$LwY3Ls4snKv-Au{yfCPHf|4>%e~L67QPhbC)G$QPl+OA1B!+W8jrg~D09W0a>d># zmAx*~$F`67Fv3ctZhS52WhqiRDC7&51t=33v4GnZ&}esS)l|sqN@{;fLo$`nPjzO~ zf!pLgGI4mXrL|8#GV#cfAm4cO8TQ zi^XUo86%SwMtY<%WnP;OaiVqDy5o3(nmp`4^ueX*yAXYFDf%u#4qS@9i;x4irP}?~ z!pBDNuNGX2zKf6pm!j_?lyMe*1#^phVPc$h1X^$uDF)EEcq5DQ*NZ-s15;HE})9xTMbYnu2qho=*dG8F^Z7Ar2Ieu zKJtL#>aih-_(jfAzxuO%dpl5&iQgSNP>>0I`-b)%l86d~L24DIipHi2Y0QKvq)la^LJv$+lnwH>-g9)@7?yZa+gDSQQHKGcVUMzIx#)J}j zGcoNXM;bxUq*PHZFm%Z8VMD`)B#bKgojd*Hs_@wP9dWdr*M5FvZspwE_1w2ycl)xP z&&y7xDS@5EE@j^o$es;h{F8i7{#AZ7KUf$ybgcki3k}pa?N;r8Zj)M_gz!Eo* zc4GuIuKmIyRI*n{``(_Ed@T6_$8iIPRo#khp0`Wb%1_Ksrv1$${3DOhNS?R)yMY1U z&02B4*w22$ULv%UAX?f#)+x&QMI~T8Y>-%!;iccieG?n#Ud%7c&pSrn?#Re4nDp+Kgzw8d z3QTeTN$`cyqqc(DOQ{1sO!xC+7vsAIfbSPa^XLy!IS2-#kn1?Xbj3A)_pZ=t`t*Xj_4a+um_d^2zw^`7({VxJk;k zCQuwou~*#0uuoWGHB9<^6IUZPJfTI&F{?B67_GX8z>`I}Q|{Dm5QW#Ai_zf;?F&}g z#U1XU!jUixx8|Ko4m1cGkc_i%ml}=2s^PtrHf0x$dq%nqA2HeXG;@*Jl3i*sb{JM@ z**)!7?a}r$J1vlfntAT6?ffqf7AB;GOfAS|iwu(0!xF!Vec*vE4}>L#C*Y;4jA8Iw zf=!o^oUrOxUsYm|{6GuF}w2q8K73)UF{o`Qt{y zIx}FNq6~6Z$zfchgVCwma3Rm&P@X+2AUKp~&k6_*<=L|WLU2v?Gb#kvWdE!JmG=2N z`@mahIQxvVmGp=77J7$o!|S5pQ97L;tW%*RWbez)PRJapFVvT0_yRj2xv9FYXJ;Oc z+MF>UI!5ST2)?IGuVc4w#lR$mD!HW z^SB>wX+alDVnbPu9mo)V>J*0Vm~$*O{0(Fu=Vps9b1mmU#I8E68K1U-6f8>)X9=(z-6c+Dyq3=Dk$Oe7`V@VEo~CPh7Bvu$WNzuzjmAbB zgE!jPz}rd2Tw{f?#n_EMk^yth(tYJZq+#UzyqFujWPb zo>>dazKuwW%4^?5`E!AlhJEGMChNFWWL-XsH);m(l2j%7l0}Abc-p3qM50Yy0Av^k zrwd@aRcbqiaqzkT3i)>CNe2F6${Du{fDGf0wBXUP!|CCpQ#IgLfzmw z#vQ{r{H2zw)CF)K(>7oj2d4{w8de;`_)Mn@puP5-HcD^DRj*vVIwh1GOx&kB+|eH} zh!f{v;shP$`CMiYH9Y z<53H!o^hHU)q1|(!R}?hW@8TdJ$rG*0{n#ir`>e}n^cmC->~{jW2lC!sXI20RuH;N zzyo$NvxV8s$oe7XI#Y#(huH|W8ymxlY=}CGJ;T68b|-s;J;PdT2=^e@oP(#hKHOk# z94B+B+-KZ39315GxyxJ`$MDV+1T+RsN6P3Fazrs^>;sfETw?T|K&z zX7ygZLV8tK8>R%i*Sj?od^GT)*D<=G4b*Q_^jiIzu2qS4Vj@l5kX<=D zJI&`0fe0hmAA)r;!TyjYeayk9ae6>{=Bma2nlI5gz?Zm;f^DC*W31ZmoI`6xthF59 z6}v3#@*HlKSe3EMb0PwE`r1KVo&)7m7N?1@NL0lPai5qcQXKjL2`{3Y6onVjkFmtE5Xg z(mCmdR84LuKQ2ReS&*qc)BR-t{WSc)44|JzvhtDQ7=lhI5NrqOiHw4{NA=nVK zK!Y^Y>$0@tT9HPEpvF1`8-ljz5NrtQWVFI6JV<%x}ztX1;mZgff${ z!Yn6RM#(Z*gp08ZYoC>8U9j$057-cDb9R*dvQ6#f^XyM;*oy0{9Q&M&wWv%(=5YqP zGXfLuiy^{M#$-yE%4~fWSG#Oq7KX4A#tuJX*R$WUhgci|uCR7s1n9^;&kf|p(g@(M zV!g)!j+22AfUGk#0zeujoXPuD#NXnp3ylS6BY57g6~Yz)c4K~-ykAwshs6l7n+P!| z)Fu4m{X&`cjA)4=(t}cS$?<-{I7yaLrO%{qq=QnvbXkHj$?yG|Cc`3Gl{4gha-Mua zzJr@92vs;GN_klssZ3VpDW58^Rne6k<(zUusirnmA6Egp#MO9pqB>h$u5MCysc=*^ z)e^O`7U*Kv`f4ylleA>*BW=C*twwd(a0Tzkb@gU?NBwzypgvZI>AIq)>tE^F`mg#$ z{hkiB4AzJ=o;CU#ZyHmK1qP%UnvrGDzUh`x-E3?^8 zzzd5QmC0cCF?q}d<__}!3pCnAu@w!x?58YjWpy@(J;&Z)t8opv$2sWE30yokk(I5^6gTnSg1ug|yS$+ZVVc!^KuKjPQ(-|~m}Q#@SZZN9G1Oz0>)FANmM3NT$z zgmmF6AzS!WxG3Bcpq9vrk>ax=t(T^V3q(j0H8H>e6>o{vrN$Dpk$5Rq8ZISCbEOs1 z772DshD0iN75QN~LhdF*j4a9t@+^6&yiwjMANd~&@qZ5rF&q{Cp%9B*#J(a75hXEM z{776cek&dlPl<3vw8gqoGpVEWyfjc6E5US0k7sN`f?6^wN6OF2{bh&w z3k3c3Gk<}gzkcQ~5cJp2`~`yk`kB8#&|g3E7YO?6XZ`{~fBno~An323`3v4K=P-Z4 zjSRTVUm)nOpZN<%P1E!zktwR^fh{*p7I-=P)Q)y5QC`ZRX2F&kp_CE{f{)z zGwpw*fu3pqBMtOS`yXkbXWIWr13lCJM;hpv_JhT7Yc^Q%gT;Z!;(o9=5Lw(076&4W z`@!NsWN|-O9EdF5UH8D^un9SHM|D##(JLDS76&4W`@!PiT;M&hI5@X84=fJOZOsFV zgL7N+z~WHdZfyI(;;_QrV*A135P^1XKUf@gGDjFcSRDGGRof312O^7mU~%Cwo7T1z z{6K&}hZt@e=Rn56ql`O{aquYP4rClW%6NBNvd0VHQO2Fe8v>N^!1L`q-rzmo&f^W< z^X)v|;62~Y;|<>P?L6KP%=C^`AeiZ0pg=IwJ3)nDrgw-2!62?w4T728VLAjey)$$O zW_m{%5X|(>F(8=f9dAM~)4K$HP(e)ZWDA0s-pB(8W_qK}7tHjIWM)3gc!{7b_s^e< ze(0dW+w>Nf!Gk1GqH#~*v3rg4j zjNRbO-DSAUamH?N=5BB7250W}#%^%tZg1=cXYTgKZt!ko&e#ntl`iPk@W$@5WW;xT z_{fH||ETCE2>mj<60Si*R3e6)9;}XAO$`N0wr^(x`G;}1Y0FTrQqRBz^~Ort8e!5R zgR+Hi5ar1mYD?|tk^=|I4&*JN_(efMRzXBXQRmT>Sy^nL`e3%UOFOC^JM}rPYSynk zvGmlbtW)_FpM^!+va>_8^Om3jcXUa#KH;lsnCGaq_J#D#8dU&-+W|;`B&q;}e>wn- zdbn{vW&m{nexfbbDJXuQx!nNj0DMnxWWH$DGf$h7RCvRzXORKh4T{4|H3jA9LFU(i zpm?Q{^73>y)e#aH?iW}&)?_=|l4!UeY^PNW_sRAVGcepYWE9MOIE)e4X)m|_<#5j+ zcB^8zH|p3#9wN7~jEV$-(T=k4k-6TK*ht2i_NQ~;O#6i1y2w=|JxK6#r~NcH>ETZM zZ3JJ^gQor6Zqmb@_G3f{p7zg(fux5w?T?cnc-k+M&brgS{scPpOiCv}!jxLI>_9vL zf%RwhB_v`%A$C&d&T1h46)SIi#|=EJpWy}`5~g~Ahi=D?B_v|tVZB^UIa?7>d#5l2 zujv-KbtC5BzD6NjM_zah<;P|V^@R(OCfhV(ejOfpAGof&vUaM1X$)MiMWjrecxNIq znp*`z8~4J(BIXAo8|M}*7^!13!D@6qDC8C^N{pB{J~?V)R8&#D)@eyeN#jyFw^lz; zm#x6hZpq>n$)&jo%hH@QNa+0$b8vy!J!P3%s!m3MI3fjq++{0arHp>l>4CuQqI%jI z4V;zdX=Rx9j@E154+{LO6e@o!Rn_G5tKX3>lTA{l^*d2!&x8D5L zghS@@=1${C;DZ`#ZLxr^uVuKMAStuJxNe{}Bii#&M=8UV2iRK#(eiD5xxo%NinUV$rLx#|^$ zJRJGTRj&1mMt(%=~W)nfVPo>6<&ou6N4PSY+nhqXZHaPDZ6*FwvQnqFG zFnR}$99cGUTnf6l$VO8zWK4~O_I0D<(QSEptHQm5QH_hEwr(}I0!oiL!v+mX9+Y>j zeL+|D9rxLt zcFcej&mQ*07hiO&imdM9i<5A@mv;@N$I^>SY9y0E@`)!xo){^=tmH74#d!)NB}gz! zS}MJXxA3pD*~)Tdqy+R0sBDpB<9s^6#J4`a^zr3R9Q3@EodZ7pG_;22U8|Zf85ioc z)?zYs>E0%zLgGSD9CM)R;8cJF5~<^H`ek21qu=KW)o@?^ zT{&%zvEDg{uTBVaOh~wsu++BO;j$J&_JxE*nbe2Va>w%Jq00vrV!k0%c=egz z)2m^=VUwu|wS>7sq)_^7?|}tmc|3Wt?BqB7=%do2MOKUEnR5#E#j&b>Kv1{R_{0P?Tr z=jVvGUc!47OvZ|vfrS{`$dYg061zzJ8@Pjmn!9S&j3`8xT&>?<-1Xv%>4o?b>ppCF z<>A8@71oIFF|q;vlTu2cht$L#WKkL78}|+irv)e$_DKEYnkpGoHj8y+2$x?s62MtPO>PiuxCQ2PHZP~DcsnMVA?HkQ=y*A0Hx;BLE76I%-D2O1$}B7Ejn8( zujz;*`dQnoUDYyiYq?lmqrz&TrmEmPZJx%93+6SaT2y|KqQoZU7fBWq)~jT;Xg zLqk)>-pv;QLtqP9=p*nq`-T~Aw6oy_<8`B{PW$d(%u3cn7C4mj*R4Rt%vxu`cI!v$ zr1h6oZq>2F?G853UctXs0NN{1utert5gz|-BHemcE9B0bZ?*LIgH5*O)wx!svsZO~-1s*G>>A_nlv zGB<=3PAn{JE)0Jgom85@Kmk&o&ruK=i5>};X~=J_=yBf zrSGM}k+fWW4^ffC-O+wP~@{(9Sai-=ckFRT(z}8Yx$m9vA{_p-!0A4}XD>JH3&-P)(7( zR2wKe)JiJ6sMOHjR?o}NXg9eLS~&um#Y);k+5nNtk{62ewI+|~;osn(va?6@&Pq8@ zDIe)B(`Kk2>uc2=`gk47QK=PRl3J>-)!P|^4Dh#`Q*;{q?dF8Q0)M+XMW>;O)z*5( za@x%)I*s;TuigAV+GslM=7hl7<83rIhvep_~YLlkux~ryd#r z@Q*l?-KmFuEBqtgBknZ7n@07_+9xw`TZ9_R6DPEpkIU#7#IJUh`Ym8J_a*m3#8lxd zR~%7Xw|d5VL&J)>B1+U%&%A}7&ssh3YYa9zw(?2~m_G2+Bz8Z) zl6{*$jK;b7JgnmD9oo*nA)MsjdX{S0A)4DGjN;xB`r!{JQTR=o*+azM$c~x9d*X?h z7WLn&{N8&#afw#Mnqqa16(CYL{$2~VxAa12x$vG8F22`9$i&zPF3ghWK#z>v^c49o zsnh7qViWnU0FTLwr8UE=226IJON}IW;?42mS^0$UwcK8=sSJ>j<=tM{BX^ZPR$gFN zDZ_a9n;)Qnx|v_7bW(cbina7@b?OTIWkT1kUAj(DKm8bI>4D$%6XCh1!k36?*zrp);0Gwge*88nVV(OZ&uc^OqVuTD zs0KDHw3n2ePtH_!*fZ?Yc31n@i?>iLDX`g^Z3*m&wy{Gt%fwct4_*8cOjO2Jl5wX& zZ~cLB<#8eO{lY9=lZat)Rd9fdUy{yz#T<)I#WzqaV?5HJ0owrZdzTa7AlEh?!|TVQ z&2vId)NR1BMS!81_$ATo+YigsrG+1$(G4b}pDAJq4p{L^sOd6EOw#ZiLs4-BuD4 zhVCcS`uo0qmw#JqDvS_+7q0e&p(4dTK};0xYk7e0CP7=irZit1A#D?H3-i$#2a}|~ zq_y_n(s%5O+&0XFK(6$Mgg->76S9S<<)rqtq*q>fC1dqwe$9ieC3sfpC;ctAkax)E z5@7VeHzJT`M1B| z+mr^u&ZF^ubnyhLJk@2!nvjQ}$W(Lr2j~OoVwIn&iID_EfWCGtp%C9P5xDt*8TV$) z*qMmqE&Rr#TL~{k5%o4-ynu7q^m;v#FcR5hXX4@l{O*@o)&3rzaBOD+PDGom$N$dH z56$11h?%R1fSIhc zyj_iFD>KOoFOwU%v=;OHeRRcO*$_6&dY)-(>x0AcX}MU2ik{rw zn0Hs+R%R$}PwsCDTvAGv+N#@=`<4n*)rIP6)$Pf>twIg0iPlzgdvZTO_pSDY_5)6T zh1%a*Rs9hif_rj5*UPu>tOz+6gw^^+KlSxXFLin8j=;ZxL5LeRv;QE@Rka2k)}Jv% zT*btTZyIe3$+)OL^;QTU5<>3MRO870$!O-SI}E=>4G+r%vc&=VkWoJC4{|2qP*r|r z6fthmwNzYo7;TnQ+M^<|s_a06931qk8}grSUW0z_lkwJGcNorN$>v$=gOYFGjlCQD z*=L_Akd~GfmD?bvZv2vcOO|Z151L2q#%K5J3Efkd=<5xwm#rLW)j6rlD0B_qF&h8a zt#Y?+v@}gKDogbx#>Or8!*)jT4_0UNxjkyOH!FB7hwXO^%B7rSXFkJpwMH;M*gxBa zWrZb=@lJMRHlyDsS7b*bufa8AA=4ngT>py+KU$S}lsy|~Jjc#qpJ2L4xlr zIygO)74F+twr^e|Clta~BM<02)^4&5?{Qpi^{MPj+-kNCH;4QA0VGZ=~}!bkJ)mvxDMSLh_YFAS1i!HjA} zps$g5n!hxzlJJlK_|6n6i3`Q=#GgbW>p~^zA<2(q11II-A=&WS(n0nk*}#w1C4~s0 zl~)u$k_~bd53NgNT^Oc%Xk8-f?zpDjr`2AMBJ1erH!8pJMt_l6^Fw6M^&3J*M@`0y zVy$gBLX3`{j6sN68}P0;I{E?zA=+rn8vKAl&kaBD`_W0&LBo6R#+1nNV*G^ROa-C) zLPH~?QzD9UMn{bu8!~qG&^fWkqDDt;PM;I|UDQGRpk`~czMPQ}9v&KAw1HeX(KQMN z=xKlCpTKuqvVLlZ+08WZpF4SSzFy5Z+t8?Hbvc|8wk!%itrI%-YHv(1+Fr!h>*(lP zc*{&UK+%u6_&!T8b{Sp7m%o@haqe8);;$q2kp@&ZOA7d#W?(b_y94z+<3R-BXMJ%1 z>-h|NDnB&V8Z#fV=;}0S{r1T5R`0I@&l666J$2K9(ci^sBeY4{`&vEwb8V>A`3pP6 z8gUPM9adcWz2qRi{yR2p`^~5<3?olnfg)~TD|9p0{=-IGAXSRDx;Mjo#j0^8*Fs&O ztMwMU3}33>F(YhzS$$xyw!gHuX-&8T#%pF(7T#rRn?$UC&WuLJ!(t4zbD07T(N{XL zR8T#E$L6wU#6jHKTw9j7y)${JCp;!}66gj@$_Z6uqU4^d$N8w-Ukt8VFqFiS>bVUA#ruNhgGK`_Cl*3sj`zBsDC5V z#@ql7 zHd+OfkDWbhp9NCInm4zdT*$(O>_WOdl+-({)%mu(b~@foX%Z~X3ddkXb5!Rui!Zjo zw`18_%v31!>CR3WkXoJ|c+ufCggS3=|E<-*31-(1`kyUnia{(cA#Gp($mL{11MNj) zgHgu_H(pbVjX$-ScQxnUb}efI{)=okt6jVLxi^zfMAnYX3Zu7h-uw+16)WtLsq9za z#3Dyc{vH<_XN}^pCN**zPGmxzj4F5GgLo1bzu_-jHZzJyo^6V^7l zUEPD3qK2k!O*nf8$QAfT94^!T;;-)SDg};tH0A@afcIwIMxgU~+1H z>l|7Z;H7*qF89E|`w_#law90vkoC@mG%wJwUlB%-eX)^9sfLJ%tasX{m2MS-7j7b_ zs7DoBIhUh|m2jmMvAJZ)q>@X<%t@_6`_4(~-Vergj#x6jeOj}OZ72Ko&Fb4GdfS-> zvk#}DzzY?w)t`gcAJzxgufJr%jfe$F4YYH!w0S8gQ8%RT+?ls?uJ(-v1SwPTX^m#o ztwxhSw3O%#X}Cc?uT|6^p7|;^l?6L0$1WLz?;yvg#_EGV8H-!5y#5%4*pR*~GUk2) zuJz(7#70zmP_0_|38CaffuDXFsB3DP`rvJpJfBV}XS`G~UEiW->ObpO_0OQH)>vaN z{8YX?$bj*Np|&waJzi(X|9NY-;Ualwdb!k?tyKzCsgk;2OjL2RpjK{fq#A#qyjvpHmg`-iNW$)dvA!5VY%n4Z+tdcfmSSDLQAMqz`V!krf z1=Gz%<~h59!-9zAh+xsoVo!O;9HPwuVV!@*?{P=xj{dhZ)xG!jA9LLGx88pHZD?Ge zapSJ$Ad^|QDqX2|Y( z2_Kf`c0;{4CBq@OV`KS|{LRF|11~kdbZK-KOdZtdUs$R1nsRIgj;x20J1Y~FCN!n3 z8;CiI+gw1<`aH_;-C9IB)I5b{fF zoYjc+17-AWN>TMyy@yU)(|J0q(3h&y^(uNj9T)#!Hb{bZ5|*YEH<}pzl|DuYTD`zn zD3hEYu20ePjgs4opysV=c(oGnlrhZw)Vyv`t%PdcHh~JpYgyzZO0Y&+X(oJau0rG$Nr7Y_p%z|0&CMt8%sn z4}Q~zeo{C*_@W07ZXJ)8l7q0iq7ljXdAJ!T4|=`u@d^oaJs-qB+kxGNsLQ(VLB=fZ z2ckpwA@zFAP=CVT6sOE};E0_hF<|K2kTnb=9dU}KP}lc=C(=PhPfhjzr%1;c@=UUYoIdiWXpDv4b$w8 z?bY^9`-pwscI*gbfjI0g?ClJ5R43Je&z-H#LFbI~heI!*F~QK+TvvBDxv0Wd5 z+!9=6PT=A=c!L|rjpb%@pK=>GlRM7AWsVv`%Ja2&;w>idFp{6af5H=Q@hETeIXn~) z$_mwmra}iH(R>4&kKrR>rO@3dX8$Vu6>2_)XT=xAwqj3ls7TGn%bR8Qk4KrB7>f&Z z7jQfS3@5tucS~>JZm9GGwTniP)#c4H;}c_gJm}FQrvX7HJDRu+!r3t~Hng0^Z^TYn zN1L}?OQQ1REBGgJNH8Q|<;he7S5aOfRhJ=Ho=gy8$dYf#K?pG?*p4=Bp zogrABOx?*4EKjEHWT-EHsd?qe{|<9{tcuKOvbBAq{llE5p0ybUD^Ct%PA3|7ttdk= z|9{Jz-a*XiwUM|)O4z)5+UnJ7xyO#8Dv4q!05Pl-j~nrSYbo17ma@DG=!H4Dpbb*? zLeanCE_-W4{ ztB)g3im)SON2-lOT*BtF1nz2aJ!@9wYuOEEU&_|Gm!S9o!!IPZ<$13j8OX z$sdYU)OzZF+?jkruB{PG9m=VrG~y(z(_YfLXcx7AuQT~Ot=sH(G!H8WB@O1i@Y3es z#m&96Ie2k%FKrH9+}ul>gBLgV(&li^%C-P)LSEV&ytuiSHU}?m{y1&!z=zIf&PIp& zYFS+^_cs z7S?NfG|whO%VTJvch-Z;V?+vE(1Xik@Z0ZL`5pM}cWikK6U}*MaCr=V`yE>zgWrC~ zmdD_?-?8#L@Z0ZL`5pM}cdYyl{PsImeh2U3yTp7q-Svn;;30!NVi0)9AOt~hRDK7Q z_`3W{d>7s$27!kR@`yp;A%i?(5O~NSj~E1m44NV?5Wf(&iQkK7am6L(i)Ex(siE|$ z)I%B~!9;1Ev_c|k&nfA5>AnOdWxt+ooIFQ{W%5_@UipOln|wzu8hUn8S}Ct9{gqM5 z`^sWvodUa+W6DJ(S1G8LQ=eCxsnAgkZekB3?j&pz+e?G+P3#Q~!Z)!KbO_(X7B?V# z6T8%a@J(z@6Iz&^&9_Vf^(->in7d5)!MtE1uF-nZs%AB@+FQ`a8g2zEf`K}MgB8I* z9l^nhU|<*?pTdJ!sIQ!0MKCZ7k5AzNhT-ukJU|`6!HQsD7#_bO7^ovSSP=}=5ge=t z2G(!y*V{uSv91`b2nP18_UrAT1wKRuD}vz%i7hanl&i^2{%|D;{w8yocEEt|BvN@)p~*7 z>ve}K%2(i_Hs6YWo$t?&!i6@~dckh~7=Mw^W0s<05B{B{V31>6>9 z3m{Uj7pwJxcg4vfK>)Uhtkw%2ilrsu!FxD(_)sEJ4CA>H4jwAWb>)}jF0zM%hxPIv z`A7MZ?BU>{h0klTj1unY$eebnLV6m@~>;ow7aUKx!@F$@O}6SaBT z3XPUf3KePw?-$11Po0RtE8CXgZ zN}xayv|Vh{Y%NEloIW7f{hz6ha{91cKcxSvv!Fh;KtNlgr!n;LR7XP{1gE-}&8{Xe zs~-#M(@+O~P(R+Hp$>vUeIi2R%8^ZV`?MsRhB^pNbu`ogZ8*KDj)po2PIW}`0EY5l zQymR;5S;30sDt2CM?)P1r#c$yAUM_0PzP+PqtPctprH=73x@=6s-vL}{HZQYB8Ppy!ak?`8}5J`C0)lzvspGz{~G>@jbYr z-c^ff6*Vuu2kb@WOU;Y#K_Q(PcD?u>e5|k5cj`xU7T+5yLsg@((az{?c=0{hY8*7q z7_>HK@jYl`b~h8v_d+`withn?Yw%eNFwkQ8JukioUVhJu@BN=>{JHtK@#i7V&!FNX zJ8el~(y5vw&!rX4f9;R`9{Xdbhi7mpnnB5oYdCg)i#!Gl$k?HPOxeO0E@WNE;n{}( zjvPrkQVL_c5!G<-QZ`a$iI=SL!d_O9p2wGXE;{1!<%r8!!c!s@rq>AN@%K&>zcQVc@wE5WH}obW*w|hCHfOVcH

k%8Fh`?8vG0^q3O!zbufbWZwob3tb!kx0 z7wfQ2->rM^UG(Y*&5VwQ*9)7zwn}P#bOh0-sM4s0@ul&tao5N)ZW$EU2fx6B^>;v) zdCM$hQGo~JGh9eKfMh;ML9%kv*+lCTYk4M`8&WchU_xlQ-6Ytvjji*5q?VW zm%WsKA&QDQaFG@=aFli0IyO**dP~ujJ5-FL9SE%yh8k)*ZMz{Y9BO;X&Z>;zW zAG6zCJsXvh0qy@8^4W|JU0f>GnB^{YpLafUzrU58l7X(C{dbx)X=35Oq`2R``}g$e z=clJ+Qa0-T(WCZJTInU;D31Fb%vn&(Lhp+G)6W(&hR*leKN4?Xy5@1brun{oDVZ3r zIeDjF#KSx8GLEH3@}5t`$8CK3httTr>ib!!eB@S@Dv39?<=~?z9K^qd<;8Efl`8h> zqlcdn~TP^;a!tNd>uyr%M#(5bT3abT2yHo z3gk2|S~T%0dY4B>u9D$9`F>Z7XP~u>3O476sd;*s)^vZ2)&5nUP;wAvbVA~e%x{V^tMk%n&}Xz;?4 zl&p$zkqFnawpmwT(XB;`4oywG9&(T3)tXYbxXwyGV6qxM(f&u?qB0VBi*mJp$6Exu z%V?efHTfOVlXL;*ggy^-_qbPR0(j{#g_giHkgwHeo{32{W8C zE6|smW8K|b1ig@39o=Hg1Mr~-?DZFJ*(nx20V{u~X_lmI%JpIt371rSl_$5-napF2 zvT!dQSGr#kMQqNbSBnUb*fbwBXlo{xe2nL|E7>{Om=ZaYj$Ss0z>D8r!aw&N@m*pQ zTGP8}&oR9p^zMBoJrtLD@a31^UJAu!Mh+afVQOitTgqzc?6~C=(?;IIkWAA%8y;-f zus@TMg}n;&>UAdlMBLOG@3@QIb#7<~r`pGYE_Qw1jV)9JedAj*&!jC)ise>taLN7K zr8V1C?#=gTM+3dwqI|5=(CLDvqXqn%4oncqz_Fg+#r?od);kIzg6dR(RllY?TO4eR zUEh`lw&Y@$c>L|wfeJ!xp_%%+yiFV>zc05CcXSrt633LqkJ_+U+Qpwq4t27Kq1a9B zmIAUj;#*Uxw+D#6BSKNBwfcL9sod}AkUJ+05n-Y@Pb|vjbn&e>j>YAVNuoX#TKdkO z$Ci3;$~VxRbc}~tG|deSb^mr+s;$@ZdyOW$Ain&JD0a54TF`7X8rQ+YV#i{(DXBHS z8kRjV7JYTYV(}57s|qaOzZ|vUb@hQ-N&{Z2uf42w)dnHvn{Yeeb9svC#2mU=aeiie z`=s{zau_`WDG%s{5%ZBJ=|=3XW;WU8ac9F zYNI$t;)43AXsxj5&dD*J+K8rH8!%K-f5D6y5i|0Xr_7#v%3(y4Hh2*3|Ex!GAhPB4 zkS6dWtk0BpuZ_j;R{aI|dcX46HMA$yU$FEqv_{>lzu;{Bvog5>(nFme#~n^?bN18b zNR3~B&fQXW+aD_(j*rd3NAyRBcV)b4+teqrwElw0ld~qLTA$bn%8{RuDLA73f@2wn zZ8(jVs;vmNxAW{0PG!6;&e&wII5*ZFe-+>I>n~{3D56nL7wl3FJyQ2`MmW$4-IojO zFYGSv6nC;U--2E4ET=HH(K^MW6BB>3K>f56xHVi&eIs{)Tjl`moboOFiQ2Rrtii^o9~ zsUcnhO_a^zYhnd%y@D0uKT52f`Z>9k`L}d4x*fgw4*3}U3NRL*7YAnID{h;9W6>f! z=>&?cO)@-21oeAWenp|qX(0OMXUaw;Q~6n;&S@yF`u!a=Xj5i>cJfMf%X_`zlU49x zgp5T9K8%pD2%Fr~@VomdisjkK^WvA)Jw7`LRX};Y?fe5H4;*+gHa!llnQiokBNr#f zVW!iX5o5eyv@xK&k!ZYU%r$hQjxOq3g`1y9dBy|j zQ95aYnJ5*Kq!+g2X5=2NDk4r6O(bQNp*s#@<3|m9khpwTty+1t`kMQ8;|o7*YrbvU z&dq3eN@LYD)n!L4SYnU;`I7mIUD(=Umv$~1kZ=EDMRJ3k zXtSY1UAgcM`X%O^zvGNk=cu*aZZ^w<{MyT0=uZB&i~GF`Rn9NK)KRbN2b|j64d-=k zN`Gz?*FgBtS;v*+Vy_<*Ln)g*NlxXPaB9<6+%wJv^jYq*X`co+?N!_kE>~RqR9*We zI~zYrd^zrKz8SZLuYi8HRzm)$>Y)fwix#DmV)5_4P;6&&ult#cWeCNE71*C$P;P}4 zF`fB~uZYQfJ#&%1aW#JNI6yN=xT_%^o`|?FrjZHP*=#0tk`6}Kj5kv4#ymVFQq#-kvloi_@tqKHh4(P0fnWU{)9*fqMn zUR3OL9UmF9y1)xX7o*8<4>18!EF>i?(_>k9fp^<6Uv#;*#Y|~N^jS-{=@I@NtUZ7-K zroCRjYX7LOvVqb>zgzdMjRz~(Q=C>dyy?(-^?j~|bIf_m8DpI*dN(owz0Q>v#K!Wm zh6mF4ou}q0%?mKP~*RcSa__9Zzz|B;< zNc0Gn9(@AGtdn*JF3lqt8rx=9#nwkGro1 z%x^w_{^%2En7+*`&x}Q5*XR?dzY_#_OkJvbK=@mr8gHm6`aRxM;|;sSAH)mdO_7|! zR7sw{D2Gy)i2QcQ!xPgU=aJG)TjQ4~Mw%vlEUlJcr*uR*FF8_#{De%LO=u^3piSaz z9uZu!aRA;+5BGPAO{Kx)+_|K4`+GHrh^DJ@zYIKrzKaN5l_#_WI{G?n_ z?kdI9ifSDdM3qtd2D$C{FVzivC0)&$jNjw5rM+UB#!;pwORYGIc6;>MOF3Iy8=>W^ zgSGV8$GTKSd3ap4H0V98ckfMy`^_N6OVhXm1r8j@&~9lRLkj{`zj;NIwXOO=jIVXX zhzr?D@b1n&v;folOy`vb@~sXT$|XWrhPZ2oG& zB6Gb}+J45q;4HMN**mN~$BZjf##uhPLh}k0j&8;nPS4nWHa_ueK1sK4O|&CZ&IHOi z@7m2YYBPV$X>S)b;J9@v6a%Z-p@jDJuEuk##|=3)F-=d zI@Qb%`6}i)ckdAFII8B<$t_Gixd}1Yj8J-DGLCi2 zIYl}tToWKqC?PU{4CBYZZ1Gc(0c03I=3IG+e+fr`)YwCZb{PGuETM}N<%9V{Co@T5BM7;zI1kKEK2_x z?_iMST%J;E6pH^PL#WdvHJ0p(D^^6T=&24E)qhiJ%+f;l`*v2Fe4!?*wFh8)r-u6L zDD`oCXM=LjRLW}nbiB!-fQf-r|yM=O6K+4bS^+tti`eTuL^XlS5!uAnvqw-u+famu3G-B=CdVjVXc zpB&cfnfQ2B(0s=nXEw6`G$xy6%xcTChezOLUNs%%H%D=ul;V-r^ZHd2?wOg|eB-Ki zPop=I{?6m)vahs~pT^?%^i}i6y+>m0QTD6$mGaTWi#IKv5PAO)CWal$p9g#X3Y#F;MU1ZuA|azkD-{PniNF29*KX?Ny0@UP;US2kx;ZT0q^%q*Myd$ zBzn#1uvYv=JSy5^j>xzWm1^j<-o_|MORKw6RkH0p`h z^7Y6YSwj-t$5kaz1pjOjl|ST73a6Zrp}@I(W#JpI%01*Eeam4$30h0fE6tRG4mm8w z$ZJ$sDu?nSL%V6ea5uOQHHeh^D8rQ|-M2~KX=kO48rsEw)^b(!*Uqk{QNLp8anmq~ zJX=4a&o*6aM7%ygAFsB32^l7nrWU~kMk%AaF-aY;qLl&j@maOD+Dd(0B`68*0q%W1 zM_H!aF?y&KG>YL(xj87i(`0kLd1Kgxr0i5&r&&jLp~LxPX5lEfr2S|X)_*hVT1CyX z>f093xU$Xo**v@9hOqluWG9z4c9e`Og5LV7hYRyh^AogjIJUW?Y-X33@7}SCI#9u> z?NB#ie`l2QzO&eYbTFvUqwXlJYJby?GBhQ3R&)a#~m=s zo$t82NS3=pg*zXQ%RxI+_My^f{g2DtzI}W4p~83z#pU8R=jI`f2%2{(xCz(LP~DT4 z%i!7;DvKhP26$8whX)4LC9^McWi?4rr@a!FgI~*d;cII|3jR=6N`E|~>v~-7H5?vJ zT7Nu)x7>)h+)L8mQn#k4MdNZ0Vz#uhsQle6iiF^>`&d@e_t>RPbJ9x3<=}mrR<~77 zx0cZ_7Qqj1*Ji_G;&P&ouM(U77Ih*n2S?R3;p^u|kcy}#HF=r14`S(|4N>ULl|pdG zddFIk4{)d2z24!&l@FIafn#P@@ntmf;j2-7srT+~@?vqFxLX`TORz=4L}?XTJgO+) z3x`EGCuWQ6W%w(lp4-}m-!Sn`4P^5hmlmH^8{h&$rF~d?1%HBxla={OrF7-o8@MdI ztvst`=@+}3#PG#U^6NNWWuNSii^e+daQB&TeWcs}}YDw$k(n>=G zvW;Ji8yiAdz2&X>C+*T>cA{WE**`g{n>*Nr{`NTqi<3;sgXWtTZFtq{VGXe+TJx+G z)@JKF3r<-iKug-x1=iYr)4oUo?XdEkwdy2JWlUw^rU5pXtL-Z`WgaRzbsW)wcxQk! z+L`GrK~m1Qj^$j;a&9@~A&u_dz-4X&RBAs z;)oxLh(^K(k72RhqVksAuMtg~x@v9o_%x)BgpTlC&XdiSb z&_WcMN^_%&N8ty3xjpph(lIbK=2X-oY#J<$JEG{a{e)#Bgw4xwCH3uz$!V(|tXkDH zmRLDOM6?_u!{~a2J^ZpC`Ag+7+Ozzt)=k?NXx~0H_5k;$KrJ_O1Ss>=I`PRTm?Ppl z@f{Iva%{6Ts%-_ncEy?kdYy)dvM~Y917x*8gG5jpPpA2M3dk#}p z-$}%6s3yVd${2-w3al-(QJcHC?2c-U>tVQtdgM%(;!(61pP~G!L?ve{pmtH|kE0Ao zw0e%jvRRRyX^}cqRw9t`(04!M>uIgEo9_-fHF{lqq(*t8h)s36tV?1@lEo-6U~t>_ zrP@!8ks9i+E+2wX{k;vorD)i(k8h;aiJvqnY0?H83F4=4N~_alCXOFR_3A6~lj_8$ z6i7+&ysZgeP5v*qn@0R#l2a@4DBAOLHWxvSame=Q<`Dj(cH5d##4aDAn=>FL&^B~= z|D_3I>}5YyNzKkr#a;H2Q}`h{ma`e#8kg9=+Hl6j@JT3pQsBacZ}k!m)mFqgZ#Xc} z8SBh;s7~BO;Mry8;%#S|{m5Bu$K1h40Y`5KF?VjHl#W`Inq52D`kp(>#b-@LRWP@>%2Gc+ujFoq z{QU*nCs8vARqJ-;KP^)wV@%GeBv{IC3@zZUa_`=X6z&y)&fHtv9sU_%LY?+5l}4iF z@^Do|{okF;&F2maKk{&ie@^T#{$}1W>AO6bhY9>f@vwW&&AuI)8C&kXFO(E7i4Db9 z#q}L5E5e#BS`xJ>kT-jhkgq+D-&(*gW9dhYP~PR7xF9u@hjfMZavwD3H4)kieL~J5 z$bCc|0h{^X<>3OQ11>(T-gjxa)@K0bATJi{vPv&Ha$Zv1INDq=G%#_T&F3!&)9=DD zflQg-$*1I^>Mp&gHl5s%q+#n(;I0fAB%X2TAy`|5#hC z?VNW?E2u*`-D?45)-IrY8daHj)~zr2Uot$#<_~(>kzVLmcgi1q_=EdL#uB5g|KH_N5;(Ni4sbcec~xVCOze0<*ItmYtzo5m4V^ker4zAA6o zp+R&QuVMwr=loW_u>tK2!is+59(7+3DmwzkT7{>C8p08$CqI-wDSX8LGYS4BQ5V2L z0VlyH#w8!`Cs6mp3h|T(1*LiT0@6%+$W0JmbEZnL5Cy^x=>SLlrJ+_*+M7}H^1Cwq zveM;HM{_;?l>HE45e1bh(#?8OH|0rff^r3eot2lIkH!yshJ+~YRYmZZdOmtV!epiP z$X+wR>y?R~R97W483f&A6dHn{n{1+XjQ{&0zgfEy*PozwMey%$lHmctp_U#F1fTMa z?gPP}U31CBeq9Q0zI^NDmtzcRJ)sn?;a|=52Ax;p#i`LQB_=aAsk3nftw0A4CN#i@ z5f1RHlBmoyC^zyi`0yzVA1)Yc%{PpJ>*|UazegU#Nt3f6N_h&~>APEr)_c}mi<1#F zw9h(eU9r8g$JM^A( z!1=|28_q+AR+BYv-#0tD{ahH~R?KSSqX+ z7Fn>yx+Ji@7F%nfl{i_PF4A6$t+jydwW>+;-MS(7@ZKrX0_h8>zp}+R(PraDcOz{= zk#HMPN8lF)a zDC|XmJqX-nF9K&124E|EsPYNdX)kh>il|XzkTRCn|CH83h0f|*xD1%CE>hR1yVM_4 zxS&!w=#v_ol=^6uhHDdNqFm4GkKsx!d(8)^9P|3)5BA*3IaAY6Nayu$-rQ~eI8fux zejKQYcy(oT=BBH0dphMM!d?C&HB6!jy?$|gsR5Z+Q3GoF#Pf^7%UbyE16z-*H_dhywqH8`sH2lv{ln;VRg3NvXZUoR_GsPm-T~n!MbTh z+LVd}R*5y-o?>?~zOc91@V!kU7cD{2?IqsMnEAG3Ym^dmLTwdi(#<PQNm>8+I52 zUUThw4WEPtt~rl};E?f1`CNsq>OmFjr&Y>BQ5*`|Xx+6d%6l3vZAZPDl%3M#eQmFH zAO$DdvXKj%y*IT;ot5LX{`mOuh~shkAe|aMm+OX}q30i2$huR8;iC1HUdVXLs9`iW zIvKJ7NyaqeV}o#tM~w4^V?c!Ygjv;WY_>Cdo5L_l3907i=2r8dd1lW#EL16N!86uj z?VNT&A8bvqKD0iwV5603y&`v3?^(s|N_JfvUb4H`Z`)(+S@u%2)0KiZeK>bDR0SdDi?B=V^ixKtn5hriSmV@R=HjyE)FDV=uG6viI62Z1~Nl#gD)D z0k-(@_ddWDKh0da=tj6xU0CR@a{syL@ScO`xJI0J(a}8z-bMG2E6vkA2mVF(8NU(l zIry2s%F{(xNvJE(JqP|pw@3IzeT2%7<|PyU zHVa$9%LnN8S!4N^53o#rd%KTKm(Kzl==S;EK5PGJ=i7Ao0DD^=;!Jd?;1lD=bo&G^ zA9&M!2c@uo`TR%Q5Vm)|$mMcSkT1tS&o|?}ml0r3BmT<>u%{7v8JR517t#gTA{-EY z5pD<%h0@|PBCfMu5h*!1LHtnsOx!4Ditw{|RlFw_m%J!7vZ%&L!6-HSEqPJu&hlGw zvJ7mK+L-@eb&MIuD5VH<8y7Y1Jj*F&KhTz^MiB2 zx#>i@@TB{Ahvg1OOUnWmzHqm>-@9ksKizz{3>V8mL+(|s2Qrl=ax{Ew=HNT-6!$yF z7-XTb`Az;EejGoCCuqoC{seBz_&a=2fjm{Mgx7`s0*n&Kwz5vxEgTbQR)Ks&9d3I(}x-18hc z3t3(j7INg}I?Q=_Rd|kP05dPI3S0OC{4e|s-pi}PD?&G6u)wgS8-+{(eip6@_k`l2 zmsf?iMOp-UY=KKesVyu$E!C8~yedqW7D;QQU6Pkq1uwAb+HCay?I^SU**sF85p?2Yjuws|bE`S>p+KTY)ugH+D62_TLr_+e zss=Iyd9s>RHSTnLSxu@Mg0h-aHOw;q8#^8HByFRejxVeK+39$)`d@ZBq^i-*;mc}z zV}#%%<0$TZ4m>*t$!b#75R}!Vs$mE3%W6{9@S5PuYEsn@l+~oFai!(UYEsn@l+~oF zAtBQcaFguFYtmqsdQKu}hbs)nGfCRGhVSxu@Mg0h-aH3Vff zscHzyYEsq6W?yQ1vYJ#i(7MEv)ugJ?oaD=DQq>T88h$LRNmWBoR+FlRpsXfU4MAB= zsv2pOzN{uy4MAB=sv3f_np8CeWi_d42+C?w)!>sV8K@G1vYJ#i_@v5AhM5k^YEsph zSMX&uscHzyYEsp}mb(5<7s&q7M`N;@R5b);HK}R{%4$;8@Vic3BR&QO#-aH&h=GBk zW(6~dfq}&)RXH3pFPga~VPHbsxgZ7xc36k4AO;2)qHeN1-%hs)0|URE)vuNPsoMF2R%4q^bc62t-d-ld1;dz<9EnR5cI>#*@{g zs)0B#o~$NS4MAB=sv3v`4L)j%8=Pgawv2I9bYvYJ#i>`;AKO{yAR(|lP?sv3f_ znp8CeWi_d42+C?w)ew}`q^jX*)0fqRfq|f`CRGi@f$?NDscHzyYEsn@l+~oFAt z^f53%$gUs;2Ex4pt8@tW3N$j{HG|4`sO^biU;r&(Mi2u7gUtzM5CenW+TvCa0|T?H zrB)CF1H^#|VqkzcFhL9qG;!KHK@1FpH}AaaLU{AeDHp<>;bUOnd9#@r#K6D~^ROAjz`$$RZ4<1v0qV91R@(q|+XSm^fVyph z)iyxgHo=sW3oJ7PM7Ij9lVEi?_C`R zE8$5yxTge@c4JhSrG}ad)gRSM>fdT%4W7ors}@>kEbvIyrfZ8dGNrJXkyTkEXd*5N}4)P}LhT*%5qd+;F(9$2Mp-mY)IY!knAybT}N%Wdj7 z`025Y6VcV=+sjnCtugiu)!gg6Yr4;01< zvjzB6*dUm~apAIXTPPxy7onCIG`z1B!85!UkjhFFt$+?vUrCWtq>rSP(st>P1iwmu zNv`B$L13snN!H{v`D=NT`V)Fpo%&vZs{d3yRsUS4%+DDe zf@w(#OFqQ3+V9zOZP4va_CEWh?L~G$aLCo@n;L<+ z8vR#lpl9lluK!96?3ubO=e<$`d#3hYssG}@<)Zj!dG<;@l%K?d#;5UL^ZWVJ{B`~T zUrGR8pw`x|!XRP1@PV*g07e5L{zoyfqF9F@AMxSrB3+A zFC|GVOU9yP;AhELlnhikRi-Q%L8Jdbz%Ou0sDDxM0KcFso0NUZN#&Zt0KXupaq1iD zh0(UA+h!M-JsV3L zjK7Qr+CY8e;=7pqZ?}M|9$W&SV0H;yGE`81NfFHVBKYnd|7zCTE{>(z)j3IZ(o_>DKC}(qizb|y)`|=8(!h8L`@GJip@A6T?v%-r4 z)%n6uVUob=eD@2dh3f)PpD!=^b-wU{xLh>E4DlzC)%gMoy~axeq|wq$X^8~X=Nojv zKy$ehh7pqFY4XSNYI&y&N96M|nLfQbU+Aq2Q-XEAQ~ppMDXh-7lP*pi=nfnhN+C9M zG0liRF8Hm$Z@;lGL3cGn{dC+|^y=)NjJS)mK=5@xPQ3t$mO^g?gg$5*PTn`-s4~{ zr*oUQecVZoN@Yv%P?;C_IQ|WOAU~F$&40=RVN#Csm-*X#5uv$*O zg>M8nD%e7fP(UmzRu{?A4}HZ@1VmgZZWj-Uzlx7dyw6H6N^PZ{(ohK|Nt%=L zd4+!qOU?4S9Qx+ap~}NCotM{TW`UVAD=UtisK}u^1;S&dq6+?{!tNCCFBNvDfPbm5 zI|ckph21IOUn=ZQ0T#jc6Zo*nU>yW`MhUaBDVPvvzF`hD$C|UvPt6UO0*2$}W%IUK z#42yqvZ($Thz~!*`otnU{87ushGVOMUDmE{H?=$1eQm`CIyb%){Mp}zaF+tu~)@WA-+J{}(8xdGg0&d0+;uxfys1|V29 zKurUI^byfDRAgrh%*KmIW`UXpAVz#aY$JM|$hx?9lekYjDP9vJ6sI9N%;w~EA%N25 z%kE`Bb0Y?FQ#ziMSv7o;H1?&RT`XfKJMwSe{Px@E&ggoMZ#}iZ)TyKK2b6&_rua7g)8`Acz?DD_$OMYXL8 zJ=LKq`$2uJQc*Q9rihOe0mc;Zks?q`uc#AYf%0sl^_e;>(ZAHc)h#_sXQnpfLNQmH zXKDk_)#jPnz;m^ErZzZZ{$YkHgsm4sc3oh8UET8RxizQ*0;4Dd3iMtGm$D?cnxx6*tBG$X)4fcd=pm zSNAU$aYx*<+>2aWbbE6{xk;SHQM2HF?lcEvV=Kk;e0`n;Dq%eDB`R5JRq7R1#sYt#UY?zE{krTLU8350LK0!b-9z9xm*P#Mqrwi-&MROwgYdd>08$B&P1 zjjreGf-XRLkrO+KvX~@J6F(MLi?CBXBAyo=F+zGmswy>>pq)fjON@H7RXQla8R-w{ zk;KWqUsrxlo-6C}CYb>|AWtr#R8}Y&^M*1|8LI$=FE=Qra$LEr+*XRH;5SB(RA=C= z02CcNs@iIfT0kqSRo9@Y)$(S?N{wD&DEmxXZ08LwmS6Ghw77bO;6Lm z*7xhDb-1pF%LFVZ36}{_%nX+au*3|P3E)A)JedGgh<@I3tO%RQ1ZZc6%LHI8>73)q z1W0tkWdh_m;W7bcyWuhc%5&i|;apciC;R!@*yYO~Eni+3>0fx$@n`O_+8^)bP*Hns?+L5>QyxM6&AF^z|yyd-rAL3v5)5`GeVc}eOL zg7T8oB?RRqsY?jTOH!A>Pz64z0D|(8)Fr&2wE0I~lDfqH2wz^3x`d#-By|Zvc}eOL zg7T6`qd=(9AZZi`H5w$10-;8Oq|txBKO#sPecT^W%&KVpyZsSa7EoZsBaQyo`Xi?J z{Sj-qyT5gIJ9kD*SVg$>;L@erH>i#F2@#Wmhzz;H&E&I-Rlqdbuw1O;%RdxJ7&8nd zXZOrSk)4|>Ee#Em13h)4i9;_6ogCbZ# z0n|Yete^nupztdw`U>FDN31E(CGE66G?`d;2(6w+tDF}L;{)RqKAFI#SKh-y2 zd$)dEzpUTZix@0q2a=Isj5PcL39yYEqkvh~tZp_nJD7b-DH4La7_g=N&Zh`7i$5fQHRBl^o-BC%1JAiL8A{DbY8i$3t1Ez#gy$US%t zjpU#r{*ORyF?U>~YyiPMTq1j6*BYqE@*@n^ejDpauDI15A7uOgc|8dO*@o&#yx#`> zH2zIJNg6?J_KV(cgMJ!7nPl&`K|c-nNeV|vzyO({B)*iXTqH||@N$tP1;WckB2;)n zt%`s$4_=$9!slwZnI2xy{ND!sG$0&a8>d6?w?RJ*2>v$crvbs=2K_V;DB=G$=%;b- zBQxF}@C*HM78Q}vf~1|5=1&_#umj8^er%6x?Ci983ou?g_rzV)r7@X=gHZ|GhT)?a z3uG(Lq}{`6i(Nn9-#_g70o6{my)l)hRPgT~cKu+zjX$Q+^#j2%m98HMj;VD0KyXZ@ zDHVcaDov>n98+mZh2WSHeJZF}01_T}@QqQ|GFntDDq)>PhvQnx~e~Dr+EUae*0hg9hOX&&*d>C%A@OrLK}cx&)(9j~+qzO=rzEGx_ME*&ha zVy#79X%SX4vDPB5v>J zeRvl?+BxYs^ukyo5vF4-`uIFra^$3A#Pm2(5NqhX-d9)j6#ahycuq3p{{qkd6?pz| zwURLh)0x1McT9~xNUrhUk?!cF_& zhq0Ku2>dV>a~DCf6K>jvNH^TH4-4FI(>}y<;ii4q%!Qlwp*0_F+J_T-xM?5y3*n}H z$Q8m(`!H1uH|_uDJ-Fq@SMGWZUjPcpjr(Ao zD+83#%1mX60$(cMDwdL^+)@guPpLIjXs&irWi?5irhcrhR(Gm!L_M!MYJ~QL#u$Il zTN|bY8GrDHM(DH{{RO>^-d#`B;XQq>uIrohefmlLnx3aa38S(h7;y#$jg7I!Yy&*ko{`?Ww}-PZ1D!%%yYt=Vbz*Y%c)(yHzp*a`sCWRxR9D4*$IrheU zJ05!T;cil(96Kk(2rme21agzYdqTLIbgxe|>)UAILU$pNvY~x@zC8g~`ih!3x=Z$$ z`WOyQZH1}Ihl#CDG{tckH=1rADm}wL>PP2NTOlV2+F&-5@QkRj-7Y zJ;(1sTE>{PCmb@sF#ij*a>-ZDpt9tDfn)AP*Y82<$U%4y(m4*YIRwb?zO5X>dypRT z5Z;6Ip#Yx=*57G}_k-KjzhwvVxKV@LPa^F@C)TZk9 zAeB@hya#ES3gJCSwKeb!FwFk~;XO!r#f0}Dozo#(5B4CvYk+TnVg46jrMj<}-Av|x zf$$!rN*09oAg#9`ya%a;4dFdVKiCl7gVe`?;m#C?Ah4_l=}!m3dypo&Fwb4#Zg#(O zPr1zh0#&$rTx;%4j`bidL$CrzCD6ZdtOuz!58*vXyLkxjLFy=gZ-8O`7sw9lL3&q& z@E)XxB82xKeJDYA4^kx=!h4X`%Mjj!)Ix#q9;6=>2=77aqe6HO(w{2$1{mglf$$!r zk~&b=t>1&R3^#pxum`EO0pUGJyNwWHJlF7gkUE;s&m3X;JxJ$F$TovLNbfQrTe`Ky zI$$yX3lIXcf&Gfz&1U`=_{`pDXWBp8S8e8hfx6C1P8TGajB%L%1@<^UI+vWkox(2j zzkqLmVg48J4KU3A0t`I;1;=`j{^YHH#o4Zn;3frktH zO+He1Qm7^{8WFHuy&tOwmaF$;^)OGQT)iKwN4PlU>it+f_z-6ns|O$A%wqMxa`k?! z9$2p4kJUpqE)AkpKUR-D4D;1=)sNLfY3&(}al~1y9zN4HYK$Y!V)am0e@XA6`>}dp zxq3fV51oy-3?gxOv3j^*+%zIhKUNPcSMSH_5noHWdOubV9;?oa)q}^X^J4YDa`k?! z9)dhYiq%7qr%17SBzjP;-jCHowoCjNKUNP!sq*@4DdOubVELZQx>Vf6z{a8J) zT)iKw2kJct@?*f`A|uf-6srf8tM_B|z;g9|tR7gd-jCG-%hmg_dSJPFKUNQZ0Ep#( zfaU7_SUs>@y&tQGY}_74>wc^rSgziW)dS1b`>}fPp)M@{10K}Hi`9b18H!6Erq+3PN&>N4o53{|}DGO8|v>&gSg>n@|} zG8nIZpnBb9R9yza?lP(_gC&~ZT}IVqPy?-HUUwN)mx141_Jl#zWyn+WyUVD$41(Qd zR9yza?lP(_gFMsgE_3Zp)>sQ>Tc289cNtZeL6EdK!~VpEwe~mmQCuhIL=**x#8UuI zK|F=<6vk5o556HlF+9cbl)zIGPboa5@o;#`;EBQ$jpqqGPvR+yryQQA@H~yDJe~@8 zD&nbxr!t-@c<@OXp1~7?Cl=4Mc%H*k6;Cxh)$u%!rv{#ycxvIPji(Ntx_AUU_3+fk z(*Vy4cpBn)5lD?B2em+-{lX^rP)Jg?wsgXdK|ZSlN@ zryZX5csk(eh^G^t&Uhp|uj7fw(*@5Pc;3X*6;C%j-SPCm(-TiGJiYPs!P6H{KRhy? zx9}w3>5pdsp11J~#PbfGL3jq^NyIY*&rm$?;u(f#I35Mh2s}x6lJShhGYZdWJY(>T z#WN1icsvvEOvLjD%^#ESzmxH(c&6a73piz+>JBt@IyikD#Yu5Ka#lLq9XRCt>imW9 zz$o`w_eHm@8)5@aay2*2{Td&7PrGp4ec+bjc&DU~k*~vxd^|sZA6+F>_lRyh*eGt?2>2d3nqSSsPW}i_Mk9}M4DAGFH1d2#)cqbZ z8hJh=NEF`_=Zd=M`HUb>EFo2v1Sw8>LmDWJmG;h-K9x2|rgU7gUps@;P~5I;g5A6M z-2~h^j~esG&Pzime=szyS)4!ZRMICNR7T9hs&IHvMOKnY^t-P@pY_pYBY9n zJVFo3Uox)%Gc;2*0`oIJ_MXuvgZY_(s_n?oOuiHHGlzN464a4u$a_{to~bQSzf{T3 ze2=_msq<(*biTm(^Obe)9q6D2XEcTuoU6YvD_wiWfCdH=0C)7F7y|BNWv@!Z_2Y|+ zs6b++an10|XoZv)%$p%I+MdH{)DNgqK_IS|XVbFoV@)^MvM%%}&F%`audTFZ8fa$z z)jDK0)}w5C{%LFPv~Y_!DdbZ7Z!GIBeEE=i@iKDGp3OVE);)3)myUo|06ru4%5B8< z*UyB*Zg^f8-si&e!Z#mdcq%4g@7gsq?zZCxl|g&Ah5qiyf&8>GCr`Rmg;o*QsgIuB zpG#cbQl*kg?RUT7Goq2Vmyufp{SBl4`QZWawSzyriw6bz*={vB5f^x@iY}^AMozH@ z#fn8W3YEJ(C|dN&9isQ{yR~m$lsL2nRoop!KkAkH&FZg;I(<6tG-d#P3{~7cs8Z$1 zeR@zIC1T4Ra(}5Gp~=qshtsaMM3YTM?w*|d*rRB%AXIJsmHSAorJ6galSw0JvNZAK z8&OxIFqm;sB#`zoagFpihtW{>umqUcXk1gGlI?b9Wj1`iFI7@Xw@ySLZ$@sl_+)vy z3=9qYgM3&SCB82%7N-yod$>&WuZ2UqB`r1=F9vJ_x^lk+GVns^!DG#j9m~i?qFf!Z zg93erY*zhHY;jfp4d%|Bo0b2+*n8KwD$4fn`&gKwm`sZjH-Xc_Ev8OTnt(b&YH8^N zv3YOmUMAP~xU^gwn*_1g4fIBNXO-fDA*$337*`0~nfm$q40Mnfo}`xLRx7 z*Zthr|MPsF7yswJd)tdXnQP9?asGba?{@3LSqm4=h$^Tf*1tJWUDs7SAdI&^_qeRl zaNtvfoe>!T{_#i<0ZlS+%Xno&ufB!i3u5|=G292Q@7XTCE1lbji$mZhGz~sh4K^A+ ze52nviL|`F5(_tiv+i>mVKt=V0k>tds%PGp2Pi;BQD%|Xyvc6xS34ZRm$j1IYu1zd zPoA_LMapkM{i;T*Rt=P<%hB>SIa56*gDW~=CMUowakx4h`Gm!tXUKHNtTt5x1{ebz zOUv=&#&JL}9ujfU7K1OeH`2XuoB_^xhI5<&&UuD&oKd;PsARH?-|6hV2rD6=+vdZBdZK0LFxsebD%?Jd}` zV@H)=UY?W(81#wsI%lo=xTtvLH){Q?t3I_|rCh^1XNS zpRM1WgK4KW)$P*mps8tS3|VRuu?WyToyY)1_*AsozvpJ#H{0{n)icTH=&qN5rP6u0xIzcELkIBn^|hun z)H&p?_+*=t;Enm$7P2D%|BfG4mjrWO-$gtjB(=gpJcz{hF-RCCl<|&QD*-VbmQ0G@ ztB%or<2EEx9P;+qa843JFd|V?9ohcY;XF$)`u$F8IT(9e-$e=AwHA! zxJ%v$?6&xJeLSp%bGoOr9;O)|8BO%11{o}-&_B#d#3z%%DR>+$xP1gUs_}*GG7F6w zNW}Ftz7Suzhe~^%hM>$f$w;`gHd!@m)vCp{lbhix9$)Bf}vz z_xWGsChWUh5ev>TQt^dTY_o$7JP4-pE@SK0C&E~ zltJT+$81^<$nJ%t?}0ol;o^CXE5A>sU1N|gvnOb3YJ7YFiXCh-ziRZ=SMi0DSERGp zrS3b;jz_~aTnGC;E(zHcXYV-Lvh(@R_)YvS-T|~33b%!(;xO(FHd}~eNtrHxnD~oW zws?8kkhFxf0RsXDl%}GnGrn+5ReS;TOY;@p=b8wFm3)(%FM+2t)JFy)QR*+p$WE%z zp6}#o>JQrx?q8g><a1R7jf2`0Oe)@wH z#E|2hpPA~bACSp{G`}V)>R!|h{gu0W7#`?#1Ay@y^IIZt8Ow?^3 z3JQ&PDKgGPD(;m~<1hsyZWSTb$cv7n2q|R<@*AZTDv5T|jS`$pyZiJr^djm7CY`2h z5M~^FH6=^@qO&)uU7|Tme9%8)t*_Ex%wC^;10F{LZqU>F5Y-!1?s(yS} z{Fr#Z=uR6S7G<`J#giBG?R&3p$8>+?93itBj<^PaJ(tLTs-ulUNID~fpK&2M6XbxS=-KF9&^CH<*zx5xYjqG5sh418B`=Gl)p7 zX5XiKu&uev$i+ON!3#`V?rr8`%hS{@?tY6b4$-yusk=s7K7cySy~*F_;zse?!}`UC z$D;tRZ$iLD>+M*K##j@4XHSTS@$rT1H*6656c>af@E&#`ltgz(A`nWVJ0$VuyFxpO z;9P28*f4q+3B6`GQhMNw={Zw+U{=LkO|dvuwMefVSYzWjZeD_b9~x1ve;c#1-A1&T z%}baeeYF1Y{=5R5X{tGg9%i)SFD5inrpCYni&g%Mo1h2gj_l z&5Q5eUFuG3#>MEJEsQ8EoR@%c-Ikc$iyNHlm(v5E;cx?-mq2vMd*vy@3|-JW?(1En z+)?JmW4?sw?%{$a8fnT{Wu7W1qt(p{5UBD_b-LP2BT->igA3a)Dzh}Nl3EoI_0&Pb z7oGze;l}pT2tH=44m0#sS|>Dh=IUQ-r}bYn2-2T4E`EDd?_-=RZbF~rk+{95a}VP? z6w`s>XH@R!y~%inYHPto*1_nCH=fo{;Z~f1-PCxWsI-S!RAqDGxr&UmL|&kHuLz_!^zi;p6Bg^k-B!gWB^=bR2VWXAIpzO{ID>fM{0l zLZ&Gj^XNX)hmA4dO?@`|q22?34l(R5_H<8&UJDO*r+OI!1`KfAITA52IWGY>mQ$et zE7Ru1LEhm1b4aI> z%!t2~M+?jb6c8HZDg^k2G;HidVz{{8G|Zk)uJ5?1)ox5c?Naf440s|tt7%if9q8^n z;l)+=@Q{f7aRV2szK)~sY@xI0-dRa9lV#_{Nx~H|Ix1{dSeQj>{{pEh>${1$OA5KC}At zL0{r)nEt=Dsp4osX*8}~x6)6Y3OrRBgBx-2qNDRJW zCa|oDa#)_ARQ@3k8@MTcnzG@0+-F3v**2@_w*O<67z>&BR{{K!cZe$bG$-dO^T7`$^>~e2=~1v zjfdmq^XIm;DtTr8#TaiOdp4bFttS}2P}zG48yb(dpHU6^((7&U33B^|7#f+t+qG}h zqx5k#l?G-z9nh5NYQrOOX-sNW*N%5YQM`~q)K1tmqSyh#p0**hzgMIUW~_-<+lQ9bp}MJb@%Z!ow3|c{91%wq7(G9K?;&y zlKKsjdJ}6_hPY%d6gEp24@I-I?@SVJJp}!0t$lIl_uG#g{r7Rrn*gNrW0tunTq?ylN7XTHb{9_pQb#g z@7CT>5z!W>9@TE@O}=f=FzxgxN`p^~$=Zj=33)=zMovf*6`oM)^)5=a@eb95N}|Tt zD%;liOg&^B5x*uAZ_>5NK6t}jorR7)DAAwQ&9Xd2htaRo;MoyBPlIPiycO3cm=hTy z2TKl0w!xUR37k7A7o1ElC(;Y@S@ZDNl#3D0@}0Qa*IvP$EIA0TGrj|dU>iR<=$d8F z;Pm+XIaNVaZ!UWQ6Cz%uvq_| z2;q{0LSq|phm*EHPFV7D`1TVgL?+u3EIxRiPQ>+fVHu7DhEDTMw&6iEZCHBbkh)}B zBJQ;Z$K&M0Hm!EI4T1g1L3oAPW1E=}n{300iEZ+x_M0{(2d>WB)xPE7|6a%Qb1R z_Y^*t503Z7Z`|c<0Ee#m{Xuq<5twYdf(pHk_LnD;xThn-x#+g=gg75b>rn!{E%@pG zq8xm>aRe#{>EaurN$4kp$d|-DgTztd$~3%8CI`hfijCbViK`mYzU}C%R#2GC%|A~h zb|znL;*zF=GRooy$u;x5zU_EfT_s_9>p5xKLNl_}W&PHIJ2*8Seu&IZyzzz;?X^<> zLMC`J7{9__=pqm>8F6$^(~(n!c2OxoJ*=DW&B$>lxh?|l4wncl1@aXK34AA!E{vDo zk@86f#iWp(y?*hcanVsJnlaKd7s`1;bmfE!Oot+}>X1(HcU zqo*0pIy+o9TyMwZ=@=GJ=G!qTiCv){<@Vlfo1B>)jfeHC6itJ(!s=|WLILgR1chjZ z*fu0CgOQ#aQa9h&19w(N=GNc?MY-4FON$q8MDjtie)wJZmU}6R(hM(3gW0hx%wPpJ zjor-Vu}9c)_B#7;HX|J;_n5|wjmD1l`j#yhw&anEPRFPY9rkv(;NxG6qn2B_9Sxin zlabqJKYjLD$EfToA1>+Dq@)W;?e+pZA=v8i8c~rM)h`EEZCm}KMRkkHy^a=KEFh`kE4U?;2*LmyO$3yC zU5vyzMdK0K_%HTGZ6awvEgSC_pFXg6le+ZC^hj)6Zz;N+%?>k>)_(};rpVwaAxI!nuwC|Rv+*#JSnfpxYSj(C$z*@SK{5Uv z;DI4lZuQG#VQwPyFo^fghiOw%^AcP7>?SI8$+P~s^6LG5v2?b?lN%e`=# z*!|+V_^FqsPF+~rqckekp_!~cD!#9nfgp#M$ul~&NC%gg$@DVC9j8uf1B_v}aK|ah zh0`5P+`Th64^G^@GdK@U-2FqgmI3y5GjFVk9hQS*s-aoKa@I-kDW(B`9qZ3^dDY=vnKx$e6?`!2>3?H54xxQx>+yj8NLbH2 zZnGnKA>2tOVIyzTbP!fiDETq5p)%gS&Eh}XbL$Z`U*z*BTurRNjTDaTli zx9Fh_85tKcmX+a`JG9}_rHz-Ov+#Zwo0Szk>8DAPh8ht@p0WStf(4cZ%gVNjF3l;J zo>PJ#UP}cT?=uy?1^XJ~3ixfArd4Ts@!9&3mv1Is#^Qoi6!f+$EXB+81+U6*`h9w) zbwXwgzU!Tdn?bLqXHU2skMr^whOclF_s?j*Ircy3TB|^=a5!1C1l_EqpQQbm{)`Vk zWO?JuL?koo;Rrg3-o*T^8z8{MRZI^S`m;T3)i!iEvJLcyY!;jU0}eFK;{5q{)@Sf1 zpIAOwR<=Bun6JjO?{FzBIzou-Y#99uM|5ZnTpXeCy~Ot$jv$qq1n4yQsBMulmv6^y z;4gAFIVj^vw!Ep`f9lH8`H?-)UpnQs@Q!^YpJboUkUVO|FZR<@@$g+0bo@AdoZJIW z;mdU!0SKvs6FM@4-u0;+>#Zg+VK3K6Om)5XCrByjYG8?j%kxMX{+7&CFNhdJ7 zCa$DYlG!yOxU_9X=0%jlJ+{Nm3J$(yf8{$o9#-YvT$xs+eWCf@zy$*{ntpzOGx-)e zMChLM9XO^F`p!H}p(bs|;OYZ`Of#_N6=}e9!#yK$)d0_o#60TZr&NXy?&^5iv2>_W zTr{3Qyerb~G@hL_c+z+>Dfk|5vaicF!*kcZFE?58STFE|kuCNso z%LJ?XxK?sNaNf3Hk^L+?$Nm}Pv=#ivTFDNBOkQ!i09SBbtWsY21{;wEdEFxrHpB5e zjw_OHSQb7wN6LbnCU2I3WTxCBQ$WTFuE^AnyRP7e7?Ks5iF-lsu&fh#p_w?ovs^y6 z*FYPbVICTF%&AD(YGx0gg4vD6i?B4z79TpMvD31-pnV(d~gEfoM0F*0dj;eWv!o_=^yWnJ#p*((~2oP1NUS$31(OR zoy=~5=S1I@33y3=q+sgve#*ZCgMA0I!ox@;-O30yKBZwJEz_=B*JcU`I4GKVkC{p@ zpfi{q3>;)sri%HKY0Q4iIB;X`L?8kL0w)oOSoa2-vIZv+h@fDubMVL{0dILPcfzMOm2@c#(fhRcdKM#ebGvEmhe87MwIPg;zJi&p_azIW3E^y!u z4m`nu5j=Q;1CR0G2@V`<2TyR|bvro0fleX=tPnhj3=k+f-+KO`0#eQY+fV_)6~Q;p zA>i48-eCvN4s?V7o*n380(f?y$Krx3x_6+ji{Ogjn+bgI>_9jFpC9bj%i!68eqI63 z4)lHnJUh^@tKivzK95>w)x85fT?5Y!^aBk%JJ6r%;MswG)&S2A^bP|&JJ1pTJ&ii# zB@Nu8_au1_2d_vk%I-h+Geo+R(VJ$g@)_t0Hr#c1(8kwouF@*WO~ zs#qodDU#?tN#28d^qwT|;ew<~7TJv6ljJ?jczlj@9wULgquP`g73VP$Rw$B^qx__h z=sii^L!ip2k?LFOB#hpZZ|!|Mj#J9<6h(jawEB^+yV|(a1xip{luN(u5kCb z<~#)Q3?IqA#ZTfB`DOfi9(M8yPtwp%r7`ridn%2g#ID)v?2Uw$LT4dNcwK;Tf?Y@! zJ{PtKKMKXdc>!(+1|nSBi#^3x#nIw)5s2M7Q~X~1Sv(_N6(5Mu0s$zFiJfG6h`|&Q z|0dN)ccfNT&>&;Y1%TFu)Ui)SQAq$`h6cJ1I|C9`vO>VR=wOd&2U-6Mb}^fg6k` zEDshUp2CGbdcZ;p&J&gg8$HlR&+^cn_k`tvNkns^k0R{gi9R}J2T%0TSOI3>D}@Vv zbX@?aUfc;pgB7ADEDr)DPgox8lssX1&{sBLdGoSX$da5RgC~DCQUOo?Zm9yE{M}d; zJo&qIDtPjDlQr<6#D_o*^6=2V&D=-u(~d)F3jQ= z^I!5VsxFvVT^CgsOsuYpstYDo*G1I@6RYc@>cT7HaB+$_cg1}9AKV1$R{p_F{DYfd z-ex8<|KKL%Czb!)RKPHz)3@>uZi4T||AU*z*UGg2TX7Rf9=M4a)dqqh30U9p#Oy$R zHad51**~;%rxXSLBkdeW8OVLM2_*669(aRd+Ea=GqZv;r3S4D8r6@3u^^~GOGtN_r zQklV-Qk3#RzyJQb0T>%6oxw+NZ!p0_4j)br2OOlAbL3$TT%HVbAO-|V;e44R4|Cw8 z0y>!#;G_aNnH1op0y>!#;G_aNnG~>D%oE+26!}gn-~wscx)CF22ghTXgLn^TBv0Z! z5HpTD@g9g7$DMc&OB7GyJ+x9iiTB_{4m*j%@UrGfyoV#2C-EML8OQmsLEbfhm~q^R z_dv`z?!g7&EMlU06)^6zX2d-9QWTq!xNF(A}dHg!3sEeBk>oEx$sTNP-p^i*C|T#XuV>2l0Q z4Y+hUrY#3tx*XG%11?>TY0CkZF2{VYhmZBux~a=CZ8`9?;nd}rwj6Ng3!U*oaOrZ) zcwv(J1O4-@w_{w4WQ8I6n zsZ0TvGsRSq*r5uz}w?!#R3#wl zr_UXxCt`fEazL^rBbhMn5_^lC&JCUUu+WwoNs85H&la3bLmdoRu;vXSaE--L^)~!* zKjL2GVIV(}pUS%gF5pxGIiG8R7+l;1E$58f+K9vSrIEim$~~ zVe;K_|H6f;3l3pW!!;X*Xc~&I5m*2ME8?njxw2oCwJIegWv6~uGPVpWd_>G#t$%9W z`kvNY57enA6B7dyZ`EUkqXk8*b2q)IJmX_(wJ*V7+(8URv`@2U%|IaR4b05-q#A_& zSUUwo6*NTqV2ToO!9*3pPd`O_jj3DHtVAg(A^DqVAD;(4KGD@Aj?;ct`}V7woUXzO zRCE(>EVthC3a8$n##2k_-fP-iu9{)RZ^I!sD>2N)IFLC;-J_c`h9dxioQaCzQ9Zij zMqKAbVl?I>Ndz;Ld79ZWsP{^nf8b0T28>(AtfMQxqf=^fZ3#nX)?sesVR_eUr5Kln z%1TRR9dm>(rx)lO+4JlT7L0$-RJj|@TJV2os+=@2N2bdCEby9hmSo# zdfeBB6i=Qtd2)GBstp6@D}o$L2F7m7gYtLV{JR(RJz<;ka}TR5Kay7jVMz}AA@R{O zf_B@=ZJ3o@tOl_EN(sR{d0x;E^@-mETonMJFvZmyX4dtq!_a;4wS-$``^(BKWw?}v z+|OV!2aYd3-7mJiwP%R-j^_UeGwsFIB&ff$tmwvWTrf+0E$1+m)zL5NRIRp@O}ejr z$C7fweD$d_mu-z3HEw*XFr}|qM|e`NKq|p?jNg<8MMW7=j#z$iF3rU+PC$!SvFj;7dOGQk#BhrRz^&b7kD`9GC$xSN;o9 zd6Saqgk*xhodm#0{>y=%vBOsT9{W*yg}v5pLNcM3@R~42aOJAeaYFw32(GSM{L<4c>0A8P6lBSc z!Pv3MYQRfcQ3I*IXPI)7EV~bxeYpvQ}^V6V@o=QJSb=5vnuc@u|u6pGz{j&OvzE7{% zjG_vaq%iBe?pOWx8~qz8PtPk$FOSi_nyAgWP>U^Kf35cxzdlNzJ_IzixZ%`;Q>Ti( z96Sr;T1D$$(%-gSck6Ops-e}8w#F8}MT;zprs~g9D|ALNm2?<&B~Ch*lJ5U0zvxub zMKkaoGn-k$kZ75iECUiPYsCh$5szJSV9MrPt~oGeb1v5$Z03k;&gGhe7kSU43YfAv zmun78*_`XB0;X)vbyNXYw9GuJfGL}E9aSnn7tN!}nWadvx*M3=qwcg=1Ne!ngbsg8 zqz)t{-AigCv1`eS^Wvo!UyL^RFUF){inY?FERo0|+ggO%>%+!{CkpV)hjoj<@{)R- z3#~YGI;}~;6YJ{6NHsr~749X(u=;~b&*48zF=~p}bW%Ur9Lb^%856I`@<=tG2tzH> zF}b5;d=n877Lixqkcl0Oo%Q#{dkN?Av$nS`My^IlHgm_PkTk z4`3s{Vdq7x>kwqd%@Dc$;p)=rQ{?pQjlt@n`lFjCat0}JDoj(pP%j!2^%Ui#9HpF9 z^HbC(wSK6%@zXk-nLq#0{2M9wHQ+(lc+){sC@r;=Zd5KQ15D5)g4XSuA&&dS?A7@gWl0nPyFMRMz6fm=IBwiLY>^=s9vE1`Gxu!9gJSa zYsMJk0|OQrtBfq;2cyV1Yg{uP8sJMkM}<-Ys1elr)O_kQ3N}%@C=$NEOx>k?=l~je z(EaHcdLliCUP?P?M~CQN>1z5f`hTJwVLgQThS|p)XTaI(b=G=eCY!`Muq}^kz0mNO zU_hG3)3}eg|IZBoJ>oZ2eUw$&1G~5w=Nw+`+ph{2Dijrcv{n0JRw9lhhF9aEEKTs; zKNoGQ^CVM@7|c$6WhEjTtHfgFgB?yXUMk%Mm*15#}BVM)9B2Za#2w&()ao}fs-ndh4!nkNjJQD!-fkRZ0Wem53fFOz;a-?@Vb;I zeLB})`dw&l5T1WsUM-Ep;Ld_QyE8*WwNP@3 z8D719y=8r!)JSfuib|#up%!nd49f9SaRzZMl4-A zyc#d^fyx6F_Ui7U_fIwO6um#IgQw_yhYkmIRd=vDsd_em+XRCw7w*gn=i zby^~3wA0eD4Ox{dU}qQbKGJt(B00vT;6ZTV1ejA2m7KMV90;<+AH*Ut?yMLZpB}rj z08eNkLhn|}Xko#JNX;0ydpG}Zhj5OsL0uOQSFn7xC2M{>9-%0*Gg-^Bc@iCh-$%|A z`iS-On%F-OZ}abpD>p5}w&L#;|0DUL=FY}`|Fx*RAjScSubsdB@y z?@Y`^Wd3LgCly7@#pjexIqTL1uG?9NrS;j;TS~?{NKige)+pa7`;_Afv0{Li`i$C1 z?X3<`&Hf;yt6!_T)nC+e>c3QC#eg8~CCvmKe54U82IOjowbR-k+I{UwomerzU5k;e z=j-6E#UNG;aMxlGD+ai0F^CldQm8K|Cy%I>0vg=47=+RRS+qHDxJEy83><(A97Ztj zGxM3x7-Gc$cP&N_wm%CotV@eQtQZX!!|*}~_^nl3U?04IciG0dqejuA02i1xT>Am* z(tI0}qtQL~mHyMx8s}U=;8!F!{WZicB?a3}v-H(z!{UdgFhBxD2;nPu@ zHpOomEXe%eTwH5%_<-Nuz8!*vkY-q->CQE<{YkwG3tc+kMqN4v8@3bybWB}S&%a|2 z<9Y%6wK;?OCR z717t%g8zyk(WmV{*msNl#TYSQqBwsB){zQCdTmPb5?tsmq~r>S2G2X$=;X;7`vPfP zRO6g}(S!vY?Knxy~_QVs~6M${P(L+w0Fito`oyo~n$!5y3)m%I~_s-$|aX@h>vw zHdh(&*6xsL(J9Goqp>?~kh2@9>;<&pxwnxoVTNUEU-=M!-oYt2qJd<7Gna#{t~&lY zTOcI9*%>SAJxBE5x()4G#P=s=iqGsLu!1w+UQ-@w5Eca)0(uV{Hmv)EhQ2=hlR}Si ze~{Jq1lRk*1YGL_`U;63;teM_ifn>8-Eu`XVVS;OcaLmB8{>JyJ+cXeyy+g<%nzepr_9Kv*z~>k zjQ7Zb0h+c~TS3XBJ(QU+`={BnEh}TAtrCV$QRaFX(H2EF+yGPA{A&bES39M|E5&sgSwcF7oS zo!2jyK1^r##2cAs^7yQl2WK5TXzk=@!^2-D-4O8{&NBdqioL@aipxyEQA2Ex zYgXUPcsz(XfbG69@hjIwM@kG{;8# zssh=#^K4`LW?^z*0yZhw&W{mJbxNjxl2eGelNPKbq)VJ z%!-&b>s}0=Q6Agv7uekst8mZWTyRgU!ZKmK;GS58HsbT5dtw#7759toiB$-b%-*Y$ zO9#c$dC5Jo3Zv!evU_3`NMzMLu?q7PPgy6p6wzj46*5#$StkT*p0ZBZt9i;g!R7EZ z6RQ>F`jtPh@^&v~?b^L-YxL%S;r@0nroYj@Kj1P3yDsh8RS;ShaxWSOqX(K9oI$FX z_hJSp$kxJRc=!6xjn6+PhjeJ#sA$m}2)=!z=#&zJCgS{2i=qvSw#6#Ion$0BQ`29eOSX^Gi_ zbI;mCR%Bb;i$SzS?Lj{r?$|ovn%WQ&L+0eTFy5{5^0S3Tll%HPOlFXuR~qvo+rpsO zI2-%w3)R-k(O6B44)UEm1J52g^iT9DnqzOqvYlC5r~6g{pmf+?ak6x;`e9dVuV@6y z;_D;bnsDLrm?KP!nZAQUaK>{lW>MYzy4xX;P)GiVsdZhao}enJ(|zF__b<*}WCG>~ z_!Xban<5jq&p&B*PnN)P`v$wa$OPI7-2``$32YY*2<{>i2uDPXyT}BNiWOq5=n|R0 z80iDaU1S2+BohqgSan)U9Qqiw; zQzY^u0;8&{?^XBJrko^`x{ymDA z$RkHAM|L9Xxf$}1%xhf3dph9t6*4j`8KWstpRF&^f7Z|FHP;NBBRfov-gxh+(Vu?k zV_Sz45-%w?Grjzbx!Q8A2F8u68`m*t)8IiD$mxwRlZnSLO>2L5W#ozM zNF3;_Fub44&c2Ynr5<7C1-IL^quT+VdRK&pH!G|2#?wl{{dSQ>A(u3f`a!& zriS#oH;TocH9iPFLUw-=vA}0Ie(9T^Icf`FajJ|Per7vAn?Tz3I9+N%C+cZ=S5+(VQ?o3iwTa4SZQf|sY3t|gg3H#e*OAUS%7D%!Ci|=;eN>SN1cq` zMi0hp7K8g_nGBZUKI@t+lfg2$PnOAG8QNkX&b?U-+xY{$bFxeZ%ium)CMOqgpDdHX zGPqBc$zU0-xlNYIU>W9%pNY=NG8rs`j}#y|C(C584DOR})&Fqdnu(w({8SHK@@&0YlZ_DLM}vgk3yj~eqDHY)G&M^fO)a6Ult@(^q<$j# zhO{y#WTJqYZd|1*TG2Lt{Hex!ojGGUW1~5GnKqJMOyi`O{y#L;$w%s_c1C0JGcDLTUBGrn+IJ!%CAbTKpZ$<_F3m zW!3(D21Zc`o9bm25iq!;tsn~+5($)BinrQEeO~RWaw^2Co^1%IQ$5=dkgSn5gicxL zCB_ZS(7>vDwjm%>_iRJl3^9me=9Qad1mf+0V|;9^#w5gE1CAMXtgwJt= zDyQH&YQ!ZG~cuu*1aDLpUT(F<@oN~eIoadAa-0^aRE(a!FF4I9K zKEq$-;Q`;mPTNiU2LYmhssAXj|7NeT-?29nz|?<43-1ZU{*fWT4u}4uO88S~EVdGZ z#fK5%(3K=nVz*oDqw6Op4@1gZI+6)@i|~s`pgaxYQw}oWAPGiE4rrBRg5Xa}4ZnX$ zGAI}TF&x--GL5K`Tm?qbUjzcea26Oze-YdZjHJH^?ghr-#(53g3yh?{2&L*JmAHeP z>YyZNfzhU}Kbce7tWh&$S)A9%kAeIapr?+5QhmCu!vJQ|uMi8MGrgJ0Qv!S2gAm2cFfKSv+`FV;b3^rMc0qv+f2l10HQ0ZlV(fiW6wcJmGE!=PpProN;VT!yj(je3vZWw3vumkn6w>_<^(VSlhAHq zMy$+)6?9ZyR?LW%nXt+ySm1KxP|TM9+|$25-JirT>XaANfhvqt&8U?#X$4nQGiv2b zT0x>_My;GlEAZCMsFgEm1z+lB)XJH(0(X=NA(_CBh6`mvNGAU~&xMKhgDJENWkN_M zaEEq11(KIQaDNIUFM;6x6i8kIVH@ju3M4Oq@G|Fm3M4Oq;QkayUIM{0wR8#x&WJ~9 zZg-}ZCfUI=wRFo4o~fn90+^HuXKJaX2%f2>Eg}$#(s|LDTIwl*XKLwZ>7Nj;X9yS0 zFrGndn8JDnvEdHu8N^1df-{I+g`>5`Jhb8oGv5W7fNlI<{uu9qOn~`%;et%S5qr7) zy4?ktfRO?|rwJ~|#D4~ggSXTM->J+nEy>ctm(sVAse2-CQ!Qn157Uw?E&M2(j8+n+ zC0SZ<57Uw?Eu2xVDi4sSOsgR($lom zrX^WgXr%}1?(i#c57Uw?Exc?DHpUuen3iN||M5Kj|HShM#Pj$-b3rCxitg!mggd&Y z-w~D=o_bj7+cL`JXN^gA0K$r>XHX%JTkHyp)o@i>=XSshEL9$w) zx~dT1TE5NI8(hn`xq5>qyYQF}W*5R$g#g#`ZCZL!6iHDw%2kB`vkT#>LV!!tYg&52 zrRg;-y$wA(kt+^Xn>5mGg5kke#9OMl?ny2T5h*B(~sjc%Hq zCCd|;US7rvMwDSnyn(o>vWad55+RZ6 z`^^<9xxfFIPbxnG$syycVwwG>IpVRNCJ)F*@V$R(?jfbmnNL2ENTq4Q&fM&rpA1rI zlCjbB0CV`Kk-!R1H+uT%FwNXfwxybrjuRgstym3^6xH(#|9qB#F0+N3QAE+RrrbOF7fI;MAHS*l96M;Tl6Fp z`H_^Wx$D3s`WEdjhlg3rV#bNc)tIZDbRwL!gy11!<<+h@Yq5j|vRz&#Dfp|5%NGx% z(Nyecc$ftb=*fBd;?b~$y)9f0brK)!67Cqok!Kc+*;eFn58l8zz9n?lEX%BWockFR zOv$+O4BBk6qZEVhFpc|FgxdSOhcA$p(9N44Z4R5@Ft4-mY?yt@yOt0v&_rHbX$irW z%cRNU?YpKs=%PecVwdenk2+;r&dpd8YYAzvCEQ3?OnYpX@HVVzk6l>ZPrJLyKF3}$ zg>-VdT*6XL_@dZ$u~^5sS#JMc2&RQfqNgRC)GpzqizJwhm&%_7@a8QdErbZKd{k!d z@Ntt6{2w^1bZawTd?z8#Bqx%u;I}k1B|HS*-)l>j;|r7}6r%%4CF1lCi;{iNtTIR% zCC&bG_UtfLkbsD?ETOp;^EKrSVf?~S5eA^~qMO`Lu9U`$1LQ;YhPhWBSA+t(ga^gq z>NKv*65=0HN#dooGAK=QaQAsw6V)Y*L@JgqHH-VyLJUHPt8^mbVh7>N;oanwsoWQ@5)6G18x%xV#yn%B zj*P$ej6Cj`@w46F$iTE>wfN$jlP6Ce?f2GO##_Wsg{9fRquoRCk#w|QyV%f@J(s!T zTMU{cD7G|WD<6|=<1EF1@q_8U0x-oUVgu9@VOcv_=r)8Z$zt(&I)Dp$)B?J&nqghrpp zq4G1|pO7lo111DTViOplye1b(A1e49+C>erf356Rx-96buTmjP&F4>GcHbf9Dhb6e zL7gCdD5Xlj^40ubd|M4ZFrw7A)ye7$T3h{X`MwHIY7_Ji^;DfW3lHcgbg0zp^(PE} zql*!45DsyEoIyCmG4zH9w@V%G$>a^` z<^f1M+r69}Co-AL_sqdgXsh{lNWewrkM{VsT0YZH|3QUpt&8TzcF~8h@3O>w(tFzI zqt=`{bXF~6&%cm}OJPnu#)?AN-Y-kR{r0uA+wJ4@^DhL1=VX=QJA64ig{$dTadB$; zU|jxl(BNWO^ew%gP8)K9oy*ntMaDm|7Je`?m0Qbg=O(_@Hm%}vnimRM2gHu}{`-RO zbLxxYbLxgwO&B+GCOs1{wiD}sEbj5P|13QJ0WNOMa;=T5*1AO_c%r0uf;-0nNrUXM zU$!sBtY~X~G8-`W<)f1@K@!H(ZMX5)i(o$#I*CTz1GAlLyC z9m=UsxRj7ES~!+eTZ)wpD3Ci#VbXrCg!@s9l+KH=OkDCsC$aaZZ7~Ep&Hj-cvZb%Y zcH(jA;_5l_Qn_A&RkFYQky{S|$<{-4KVmF9S??}$wW80>I(%yNuN4;L(`ThOe!D5v@nN_`*^!@*VcSf-g; z2-SvD%3?ZMl5(lT)M@GuilmwRTYml1*IzfQPO$pZ{acM1WsG|4y0w(Ysw^GMQfe&y zJsrkBOmUNc{2J-NUA4vw+n=_8lga zJIlY4I@*+8{! z{G^^z-Cx|`Ep3wK{^B@gDTyt>>Udc7=bs0D z9$SdTy)eh??7x8v<4kbj;L8~ADXD*$8nV)G2yj6lqybzq2ikE`IS<*Xd3adAARDM> zh6i*D=F&^cd!`#-P~+u4_<(cw*7d~1Xc)fSHl{bUqF0Aw2|bX0we`|QOP9tLZmk=y z$LVvZwG^zQ`fLuRNc$|qpnX0S9s>|=+CrQ*iuGJ`SEJmHO6M#?WCq}T9bNTsw>sxwpKa3@Zuy}!_1g6uo z^(lOa{Zk&o_$hXLUFv_7YRcx?yRk6d{w9Bd`^dg>QYWFekY$H=gd%%4DP8zlD5O4= zas@CwwY|7s1+!5L8(uj_eIaheefW^@hJdlUI3Zl@AQ5Mrzer+ruu963evpc!vyvIB zgXeG$HGrHH!pLt`*36CqZVIGrWAlPF>L2QT^+}Cnk)pJ>wWP@!3BGO6vbB8e z=&6qzef;s>tQzgF^P!{tr9DF2MdPsOufKmCPi!5jI9?x2VH(5-PmOmwn4>a63)YUpK}Xb|Y?feQrT798cipxi^bgaP!asUZU3L@HouiTr3r=S^Lq0xIYrACr8`-hoQc-=W7d@3$w-#*SQbhA?&mnSlLF zc@PS0GdPtAV`_yzuvxSv22X9id$X`wlv5OXHHLYg^_>|)D(yT$Y6!nWHvJo07C44| zf;)7T*gav;&?4hkwU8CLGWrX)D+_(tAvg^2;Xk2wbKkI?SUAb`Cv43DM z6iy14g}Z`}7$8CqM~P&jI7eJ6t`ol#lMac$iq+y@BD!3~P8mm7T!Qf)wKL(G3~x)5 zrMc2_X@it45w;`zE|Gd^TbW$y-jpZEl^@Ef@>+Sjyk{Gpbyr%`ae>H_FUj#eG9F}P z+{kjYX%P2NGoD;KNN6~NVU=j*J%vy<{_W@Z&{pJ^L!|HF;aWK0*(CBPt_B;s=i(NY zX`dC>=chh>Z0fW2mcowr!@}-`%~qAeWNt}cqUlK(YuQ+Y3fqeA^y^RH1@LMi5!hPO z@n9W!BC2?Pm9I4on?|eER>q2=!WwV9%wJVawL(c*B5r@ybS(0eXtj6FVjR<&j)w!2 zDxBL@dqW?lRjNIx%Kp^RnrbayZ=%=0-iW<>t)$~NFT6+25}c^?O&?+{s_9oSsL`N7 zKkGzT@s=^kXiqmxy^RbIz<~fo(v?%|hXv;9hYdKbzpEX+)lYwhnxG#yhEPZh*gAtW z!BWc)8TrlYtCAKm6DiVj*=~P^4z&*dc=+%-rt?$%3PS1kpN?U%gNwWKBtPG}JJ>X` zl1~^q+3sUi{{zXlHJC;ESxj`MK{nN(OucK>_zsh24mO{*y=~s{A=78u0NZ~ z!YXb%dw?B5{fqKt1L)fv^rx3=1NagANp2?hklnFS|AvH#r)c-@wlVR z7=dR~RI{q;z;!t3F&_7Dl3}3a7R!^oWoRQmFFP^B3%53@s|_!}A=<+2c&#`wH39b- zM4`X=?6XzRwy@9QX7G(hVG2(r7vF`b^X}G-c6e|tV`@i7?M=k3dujrnIU^4x;xaZh z0gua(yB$s`%=(td4S$X@yGWrougW@AmAyTOoO-U17^QOO2TU}J#D!#4Xw|llsB*39 zpQBQ9$N?{JA2D#IDsQUW4;INw_55}EcbCG|Z`ASXs?CldIgW51-JesCQkRI=!#3xz zlbc*0kdiij9-b82XzR6|T5m;LX#DgmZi!P98mgf1)YeBn+F`ASwnu4qb)5?km)kT`rv40)uxGLTVXkzT4aI2ZeXw**K!EUxwb=2on zvC2Mk(SW6N^-e#106n3E@H0*u@Ci+b7NIJsC-%7>{y*4z_pmC;x9|I0;67ypm6Vhb z+$5$>k{WI&NG&a$B(bz`f|OFzVd37=5!@wiM#xQ)I6`V_;Rw0KbO1NGNk&L9w*$CK zOGj|8$UNt@#`RlkJ>B} zcP`D3#KGHWB;Kb_$?ln*ogay3TS!D^#jj|(Nf(dDAGQYv+k)@2P7xt$2qoYpyEI2y zA^jljk&a8J=hw#mextA?u~T+tMSE`cC$HVUSi-hrd-Se8Q8Et|C31cwvD2*G{B-l? z)5!!{7kD=?FhBAM8gj;syEraC5=TC#=dWFBTbmzQQdBQJ(zm2&=i~^v^lh_8diCi- z+cohjq?_sKgnj|h-qF#grKw8Pmi!^dQf|uKuMCgKAA&u4kbi*)r^JC7mt>5?%nFoC zwMy+yjWa8iO-k-&oPUEzW{vo}FWNd4pVs-2IHM`rf;<%x1nUE}Nf7LoB=L?)tgs2i z`qc)0Y1x?dRW}W)^-<~+b@z`x%DYc1l^W=lRfs8eon|=<-ab=fXUah3>S?dU)1hWl zeT!cDi$0Pq)z_M>cj1%#LfNHZhp-2g74P1Cad&I-UCgEajY6OQR5 z_%lrLF+Wz4=u_YY+x4N-!vyMY|7P|~X1Glq>*+1C$ zn`{-E%hz}dKkh@3Rh`1UxT}sFwc6M@yKHU?};N z@e~TfByaxyFdP(gE{M#Yim8juB5>w(pZ8Iw;b9jfSb+{OPgo^v794rU0ts{|C5aB3 zbDtDFXoBB*VY3Jv8*~l+zfm@SHE!^CaQ!s1t6Y4OU59PG`_ zA|4bC%NNN25y#Tm^6gJ2;q{_f#2e^iN>6w)dB5+aeQU*SQ$v|i6T`+PHVZEqf}P-T zLUIK>C~6k&m2xaQRy-+HM>h)>iJ1wH#m5P?@dyl03Z6Ic5NT7TJ;o5%%UJQNFLB~p zT9nf)d_v+_{Db$^_|Cc^+2lqzSo(I!?dI)Q6x#809nz_NO4~%ZnKAItSlPOqx79wp z3;pxcvisyGGanx(fEvHm5GPGrG*JFn?xFNmBllD)rPCJWioc10gZy`(X$cdZmMm$L ziq~F>gu^w9SerfnY@C``15LP}iv&XveB#9yX_C}ir%h6yn6zw@IH`z{YAVkE_svHc z`1Ax3U)yAOx*;iVmc3p@lGN*fPe!xwzI|2Vz4Qe6t1n@xw(j^AEl(*{ z8h%%))zBeHd)0`zaml!2j4-}1eA44{D$?flw`Z=vC)#5JJ~anCmky(H_{vQcwtYE6 zY^McK7;!Fbl5!W~ZDZTi!A5;E(41?en(IvnteI<`G=k|abbtCodMpiJ(M#!dG;utZ z(0|fT=-Ks|K;~5@0uOdS?&FuYU*5jm9-LD&0)K9aJrfh{!FX>-VN?c+n9Iz4rZ%RC zS*me}VJEWlSPPCoRO9g$9O0!m@ZM+-ew3CSz`f1kRt9`koSEY|Z$L!!f#_&oFF)n0 zH~mw3_ojOTPOYbNKX7|EIL>(nXUzVHC&3vDhxz#S7}GYfzIXlllRM=`6=x^eciKv9 z4{_eUXBbJ*y^as^J&|$YxbdOL_0S%ioc&}-y~H(sHT%S%o6#P;w5HR#lh4nIe>5Se z(jGLLMCR`D-nDB_WVQX~kf70(_Dmbu*6iWue1i7{jYQ@K#qHmLXIW*Tz3LDn@b(EQrINGVg8Q~ zinEim?LmiQ3h>VYd{1S`Z;8W2aoPt5KKNioW|H`^G z3IX?ljHn^*1{IKl#*z)#s7d~$fk08`SUM{r{|o4#`mMpO@CX@(GF^H zGgpT9&#(tg#bfvJ6nr5@>9AMN_}4tgTpyu8ozEs{r5`xnNLiIa4H0(Ay^M_-l9cod z+D*Mmhk8bHV~R1?Txo7HbIspOxMU*YhH6Z;rNXFz)W=lb1Zp;wO0B12nMusalPyjj z^+H=vHuV<-_(IMQKdmv{mJXu_(jU_kXqZhCJfw3oR87xz-waJ^RW`A#>|*4(A!zrp zGgWdsKRcNY)~Q3+A*RE0h9vg=gR3;#ovU>D)yq9EUyiB7cecH9ZPBl|dnrTd*8R}p z;yuMJxHsQM=g?8Fk^?0r;r%bIi0IcX{3rph;Vmef`=05XS+z7Vn7a(bv-B$-roQ5N zt}Nn@KWIm)?)`{z?p-cy-u3nZkB~#E_SgXR(jiQoJ+|pI$!q6L1(*llGQT z#w%c0+>87QkwjBn7aybX7qe7<~BY;qbvy z%j2m*v!svZv8#PXhT}l|toV&g(rZeO%E!eb46CV`N$y{rGe-{C8h%cFLy1&IDN_{q zS}B*8DeZ+W@AO9q1pd0d66@gzJ4b#)y`+p%Q`I}`Rf1wTr(VUWDqWAbWG|}3%LA`y z&WtJ&esw~Dz1j&)*GLL)BBqme#~+`1LKSpk^&pO)qdK_!8cHqz7hY_Ad1eq zl^BP)BzP)*33Z>~n6e^=_!jH_OECyPn}I_W8Qw-fmv_Emj zo}li+#*C>5x#*sN4YY!SR&-bTEqXXTj<⋘Ai>}?VdRvNb6*e7F4-0qYqOxiJ9M# z?1j2^wRP>se8hE6E@VoXN~Q)2{^ZijzRQkef5N%pC>A!dyV+yx1@<-zoFCVk%j<@x z_XzF_ZWg!foemw$4!|%NeueslC_%!Vgi}bG=UU=-oME%Iuys$uy?Y3UbVI; zHyl4&=-b!q>u}dLBT!UafQFca>kaN;Z^HGS?GE-{RsZb7vu8IKPcOn}!wM>%xXN^x zUW9^*$twKJqzKlIFovFpHbWpj!-?uGd|p@3-b@n)UdF-QJB%wa9^EFrd3VbhkZJN|>IUt!oPia>osQ~{d_k0s3P3z(?v^uHAd(2KeWE5> zmNOupGxA)tUW-fSUq|iFeXq14ygX6_O1%VsaGS;J5?H@D!kd3zCO6SA23W6N_j*~yYm0CQcvgK;1Lv&S8F>mM^VB`^wA6`&pI40P(&`2gL{ExW zBnzuf2CO$C@Pc+)wOH}+zlWjDb`L|XxHhxr%$YYLaJycC#@4FN=IeLJ1EGKai~YMk zK|REch;!$jo$LC*@=@8wcQxG=@Nn0xN#XeJNq^INz`-nP8I?(Grw&sjytst7)Ax2ZVVz7c`9uyFbxuEsFpYJ8;~KA~?!Bvf2z&kTJTuT(c8^73qX zLmd2om#B_DZkoAm%viIrOEVY9{=)o2GuOj>gZd9Ob3VaQcta}6Sz8p$zsEx?KZ$oI zbiy$1bH_x^>7$-)i5)CL=gl#gLHs;~*n8l>D8HLRbJ0t9LyQz*lsH9P!)|4N68DQI z#d2I}h_$4q(n|4Fk)YxdB$z8X?)1`c(k1DRaTh%@sB%p@wk6Zj6I+5$d>q$B+*Ej0Bb?XrhhM$4sEqu#6 zUM#bWWk#j}+l|A zkra%grchr~Y1B{De(EGuPQg8@7TuI?Pxqn+)1S}@G|sD5(wpd9`ZpX=-J!i0Xv}yb zS;3jf?L@MIGn3niWQBvQCz2J0a-K+5xWaiNS;6x!ypo3+f+vy{oSEECBr7;Gxt&N> z*e-e^Sy9vFiDU)m)yQd_hf%U8k`?aBo=8@(obxW@JTz9@;x))+oCl&oIfB=qztw8B zp%$z`7p=ecp*B|gO2e0@mZQNzt;Ay$1w(cBRaCJKt|Xa0#(PA9f%D42)u?Fkdri%umdI<|I?jz&)lG+Y~oGz1YF*Cu{->bJ>;bCN`J-4ae+v zST7D5b8WdWZXowD=Xj5Cu%6q=9YKYM6ZZjKcp^%1;Xc6PeYkKRFjR;Wrs1p0iTi*n z!ULg>=)!%#Byqm@t?0si0NFUUlU%qDAbZK(k_-0%t>td=+p-Jy0q%QAvX*=<+i>AN z;FNMrK{}c0#C-sn@O`bia34TW2u(E??gQp(D{+eL!hJwvy{#Um6G?}q=m3|bqgroh z1RK!B=x=;zj5WS8mKy7f90Lv-1Z?ocF;F0qXRtKSF3B@knrD~f87$4SOY#hs=Gi5A z221nol01W@d3H&j!O}dtB+p=Jo?Vh>ur$vu$un4*XP4v|EX}h^@(h;d*(G@fOY=-5 z&l7~%LaG4k1@go`C;Tl`3q-mGUBv$4ha%3e#HHdo5% z%ax7FZiP%oiF(sd1)_&=mqP&2L%7Q!ps!|8yK!);ZPN-gIHg_F9%=RT=D2itLyy#f zJdVHC)AXP8{iwDq*WsRC%OI5EUdCYK6C=TZxyDL^(29RE$h^r5@2Do>jSMtDHYb>~ z%~TWCn-+8XZ?oELNCi{iDaOg6z$L~Bq{;XdhSG8LG&-4HLvN+?=wceK&=2T3OaRk? z>BGFo#4>w1gCvq>y0XFcB{(3*35i*T77Z08Phe{eUsDh{QD zd?*iOTSoL-i}|(uHXbE;r}%69Bfg%{T(ESDFiMyrd@ZC2KMDHoc$fZzw*=>uTNcU|-WI4GCMf67nf`bwbk zs)D17p-P-GO-WYPC|eaW=YuQC1Er1{pmtFEsPCzwN$NCp@!zK zwbOcN@8Sk3UQ5zoxwcW;tr0lyZH<6`p|wuNCnNMP^jZ2cJyVD6`eFSKolHV}jFv{I z0ey{O#^=TiW3fR7>jeg!GOihqjCy8svy=IT8EL{ObBg)3nP&cE?l(`GQFkaW8r(-DWI_V&BN8$p0hf5z($2!a#ItN5`zjm3 z!caDjoyI1!o8!l4CNQw!(NB2a_MhzNArtbsF&)MI@B=yjdq5`=#Mv& z3?Q4u-3Gxn-!=%f8C=+Ai`on>Y_mme1{b#3qBesI+iX#r!G&$MsLkNQHV$n^a4ss>jpWG9!J|D=x z%17`pl#kshCJFO}Z-p(wFG8VEDpU$kL-ZHh zi9JyEGg6EflSCj=z)Wbg!J^7OTmru?MrSBMlC?kTm@rfPe&mpWMe zL`_h^lThoWfhVChRRd2#ZLkiWgxVY(e)-+yNF|0;c*pRJJ%{s#XY4t+J5tGb37(ps zvFEUevJyRhr>;`OkP0u+p0VdZ7*+1E=crGsj#Z$6ZiA$yqT9RzE(-foDG+%7bS=zQTiNKb|CjXFskXf@eQoE`n!2ZY_al zKi-ZWPmg}wR|e01e2NIh-TUz<1w8xlJq0}b@mv+$iSa}w1Mb9l0*nWDVmtxHgF7*v z0OP?mn78Kg;2O+Zb9s1R)G-6h4kjVS6JR{dH=RINi{}ddR6ELw^&B0 zaZS1QTrX}gXNk1HsnT+aw7{v-a*DKICw~N0T7UD^d_y5v=psOW!Lphx71jwk!a)H_ zgg=ERLVYn12bB@xP!Zz9X(EBHZx!>zV)2Ry4@3ujUFsvfC&fyWB$zK*$@au9P)Y0p z{&G8+*ab$)@p6*9T!xMEZu$QT#QJP^#QN69|8c%>mPw-CtQb}3O>tBVHIbS}Suv{M zo~27-RKYzhC2`9aZgGRyIh^^z&-6Eq0p%h_rU8m22B56cm}j`7+Q8dvV!ET+ zfUw%!QEfn2ZEsP-sd3c*ZK+LntkkB&xbMIJ9tk?So+vo;lkYswPo9MeTd0kjnh^1Q zakMy9TquGk`@5M0p6u_<5_qz|yUXCo{yr*$C;NN20-o&e8wz-`zo)C<$^NdZmA<5P z)L3nZ_CX%%O{-g!KZkReBqo%=IZTo^OyC@*BT*71R#j1&tbxN`?#;3pZkx4#q*DS( zr*scnhJJ=;*fN|pJj0e@v|}mj+R1|RlyDvr;5;RqhXgdCJ;Rn^1ML~M3|$$|uw`(b z63#;coTr5IkO1c?(UD`hA>60jY)kBDX&p~TI8Y0yee0c2@{j3Dw2As`VyuPQxOGe9 z6+WLQk&WP0pYtTS2BCe78avBIm#5GcH%>coOxJK&Rnd*WNV#dHv znIfi;2BN{(*hXwv8p$j#`olx3`X&#!~Q*hpUN-fzvCf`C#u`a z{C&Q*&`h8|xsLjyjEIEJL?GQlQ28Q$qTm$N!U^Fz_n7k*ty#f4B3QEma*FK|kBX~A z*esHqBa*jqUQFlSlHj6fOzI(^bn^L{wc0D)3M-DiFgbKeXB3N%3C+uUmiKsy1MAT! zzmZMmZ)Eq#f)z6SC3ba-ELahWF~U}kaBbZ5?@+EQ zy_IjI7Ai1mxca`jLEa@VRKHWRR3xYqr$50D6Ym-NWH}Tg{jOeBS81CyqF4f5^TZE> zpj-IiUHVa-D3-uN&bo-RU?FE+#96SAvo7K+SjbryaTW-d`cuk9oGrDGvo&d|F$!C7 z88mb#5pd%329tUQw<@%rH%2uvG;3xybI1W=VxGl}NhLnRtgJm*8|X6)F;^(s z?;{iSi)c)OrYwr4FxKNV?cGuwIdUXX+cXOfi}Ib~8_)*DUpD5`E~O)Vi!-`0pS&F9 zi~5%8=(gy_Ci36rQGQXrc-XZ`9m#wwugPQ%wn82CW51F67PCnGK$Yjhwo$$&(c%;A zM{QIFBdlgwly5|{PV6HLreQ|yN+nQ{i9td4+wb>9mr0A%Fhc6-))|wPqWlJDKsVG_ z6|yH8N9+b$%7#^D-Z?Nw`@hAS6?=kh*F~YyyG1i;)_6Ae~j?XC+fb3St?)xWk zgxFBT?buw2=pu43Q>-{~ZA_GJ>6Db>B@w=9Ch z@GbMgaPzZAXdsUATeT{E)sm%Xp*Wfl_v{n)lTXO`Y3JW*c^$20F@fivp-(5QN$@$d z>Mknr_a&swys$K5h8?d_kDn}EDlY|e$EOD*#k@N4)mO94&+4PZ>vZPqI9#5G`d0d; zQfuU$wykrvZjJJL;JY*q4k!x)OQ;KfQpvvf5%%-X%6gV{D1k&8jTn(QA|y2}yt2U*dU2y;F)w<* z_~Pn_WV!}ghT75nL-NS;w6bOo=3Qna>cp?3OC=;V))%$%ONaR3&FXaOxr`nuMcze4 z1YB80Gi*L((6eXKQ`w``_w+4FWe6$8zw@t z^Vo@8I?r&cleYBhmU122*`b8A&WQa8JDZRb9+HBp*$m#BGe~sk{ZJH5o5Z{Tc%&I5 z!(m5~!!k!v6rckZy3)1zW++5Y;a3Trxp6#pnK|4F)U3}Fbm6M>P^zw*Moc*VTz_9-^vspDx|&7IXIQ*|QnuM--s#B))U%IlaqY-D2uiK^rAhW<73km{WC*21 z3w}0q!i@xbQdy*d|0A#=j5h>opAmT70Q3fpmPB?)x9cdDoSe|VF1lUv28DXreaw5( z1oIPV*|P4-E)LFoj8}_6p+2_Kdh#}@{2AF=;`K3pP-tjOxw-ry%D?i>s^85vUii^q zuCQ(D4(=m!CMBBbwaCpWuTNc~_RbkUuxwCgK`0X@Q{D}0*(-xcW6Gzz>F$`{(aa?8 zGL42H^Qqa-e35Apd@V7jb7A6C)MdA5i@~ZJ{Ay#X!OY*3`6yQNq2U*b_={qhEnq$EV%E<$eIk?_he*E2JU+@vL*xfJsDY(f#+Oq3K3|#_GDyD2JU+@vL*vp zk|UYRCEIJ`ch^Mw>r`CX1HFz>8$a27v4c-!^4s6@a4<)%froY?qwFC3v^*61R?=&rE$fK6xJIz%{%6uS$Z8RQ=jw#wrrS+Ob}l$ zye2I4nu-@jyB8X?1{9d&?M#v=850O2BzL!B6;THcRz1y)ySi5!zD>VX|ntxktNSl^q&sgJ#e6cH8-K(2YyAZ z?=$6Pwe!vvEfQOFR=xEx>dX2PRYYEK#TwDy&9^OW0?EF`+LhxohR?!y(qO&52A%X*wWONI zw7L52qXYxdJhuDVCU|Se)(zdRLnGscc2_^DUgqoSq7h}}{ixkne>KLGC)?)R&YY<@ zv%Wm|1qY&~@N%_z`o7{knVhQIkXN-hyF)z)0ErqT`HjL;fV zaVHkwuwzB}+6;f{-P#+yH*T!Ud}b^$8krlY*Q*M<)g(`4O0P3z%CjlyZSm8@ygb`N zTj0vNYi*aP#jnI>2ZnboUQ_NEO0-M7U zPDuw2VmVJ)2vl;OvJgn(J!K(4tWoZ3C~%rtoNFiu6+LAk;Es48vJi-rJY*q@stYRc zMunaQ!31LY!EX&;?{RU2k6E=r*|mFMGK|$aZ95$$i*j%EdpSm(sLoUK{*rG6RAyAl!1`xgylB6eo|&7nq6}N-2_@_` zy(ahNCLBPH?>0E2a77t5zv+sy34w@dE6Urh4&<(&X0WePZ3`ne;9fiMwM_))U{~j; zBcZ%laezfId?v@`Kr*wN6t$H}+?Z zK=VRo*?w<4h$&UOs*Tg18H$_oxb|8`YZb5Rwss)UEz z!h_78&3(#cnr8+Mek^AEvr6^%%zr+{zpOH!sSn{Kcy82=Q;^ zNOL5)86i4zPhpVgy#}8PL#A9Yk(G+dduVyLWy>)$lF?UQT56V(U>jtUcHh24eC-sX zI~iq;hDO=&<<+mr?PTwD@7Q2LObVvl$l5s_6uboE)6v$7^9Opq3<_*JgS zmVTd$NBztMugxQ4^()I37 zf$}rPkDpPZ+TxW7DpYT+iFR3W1TWmIlps&@PtUEHt5qFO&CWHNs?bNxlZNS67Uk9q zNExBGTNF0<{!;ylj9=s)UH`*pLIsW*1{CCI^$mX+dg+7pPxKj^gY}^XQQhT@METuP zW7_q@;`(3F$@=vW=CaYb5?`qm6nHnjrp24}^hrjje&uep4kyiE!&2Mzmr-2557wHW zm`T)JGw|^x<6{&)!`lv6nNyDuM}D6!eI$`bg1bJF$Roj1kKxaP)2n6aF*f48&BLqJ zje~!AwNM{PzsWG$U9S=WSL!~{FKqpI47=j&L=j*3t+ z0=}3)qJgd>VC15>cQM|Inn#JRPeY&6A^dsY5KEs<3Phi5^|J?d$3qLRPJ5)ga~&f| z9Jy2!6J-~!9{b9nMh$5oP6;jvyT!Z$`Q)mN**S@Q#$=Y&sA1LsGDR6P=Hi$WY53%O zmReY7E9@s}@)+q$DM)@zZc|ws=N{2p2sE#od{QYTI{AU(AIb#$_+Dil%#OCbCq(Y4 zjm!>TU65DEFN#A{I4;=}p4hjlf1mNo-iWQeI`}@JKVa*;;H$lU5WRfSsjF7mR@GHs z*E*`i_OnZURt>Y%QVoF*TCURaVIbA(cY-;IPDRW~_e+GhqPKjQzJ(8gH90!u-N?>J5n80B)L9 zrc-Y~J5n80Mh86Xs6zQ$PJ)9(~EKH4T#(Ta+%*4=P^p; z2H?{FS@OT?;;z_60Q*OEQ6Ics0fHe)$*`(x+*sia4ilj@lF}8<@o%hKC$A#|zi3YE z`>FS*pW4q6arRbjwou4bKjH{P7!RmY9Pt`0B5!t%PQlk_{JarUxTack3eLk~MovZA zSv27%#SEK@%%kX3yjlBJhXoczR79s>+iYg4Mrp-Jl8G1)9-V@3JILnglc6!uDGA}l z{1txS=>>QMRq*5Znmd<{!99ZZ)1Evv^`=> zql=J{Ckzl)i6Q(4!WcmpJM)iT5Tf{2Uz0I)!-)+W4k`{_f)I}#2@i1)6O>Hm1tOt% zAjBhG$RkEID@vp06vsnRBH2c*BnQMgH_xH2iC#I+KfFKw3TtD&@s5PC>Jd~o#`E!h zVr#Kp;to6BaXT77pPZ1gZ-tlkxl+9%u&g?xaBLP%JMtq+@O!b9#mFQ&=P&u0OerC= z@=D||^)}im{p348Zr=QCb9k-;cM@n1OkWwXZ}0}Zv`p6FO_e0xtd@V2_sK7-7Zs5C z7*%`jW;>(VBxocJLf~(Z_L_E9`s?d@C~Mqx8%NYcK4GaRz`+M`vo!+oHM-jx!6l!t z)DuARa4q?SrJjIysgaZ=pRm*uaDlo_0Zrr+mU;q^Kt@~g2}?auT1ERXEt&Rhx@F+x zt2A2`^S0=Xx%NSLvK8LXK|5v$^IeCtXXUd9vhz*P?4jW5g^aQ>k>U30PUzv?k$|Vf z?A6?N%s#FaTgJV`4hlViY=0obp;MPnof^b`q)iURnQ(QpP<)*cT7(IN7L5YFACq)Dw>!c@b|hdguD%saSnEj7kO2L49ZQl9tqh;7 zVsIsrK6WHb>p5*&=LlRM>|wuQn{Qy>>5Hh29SH&9oxGXj9r3CId zOSr<7WaAN9ZI5`KvwJ%w2cMkw2s}F>JoVZjBIzO+l$-3IZ#CZ;zQc|TlkpLL;lr|< zKfr$%9=jDi$jl0^agX?&({s3kTs6O#jpLecV`q%UK}?kL<*3x`>uCE+EF9a0jOG&y zEE%uELi15ccJqMF6Jl`awjzn>`kG(kXN%}zwkPed2gfuIM8G!QQfDsp;u>>RNhcyF zJEDe{m`fZW^|Uk^fdqK6bHBdqpdNc^K0XQayp^demm%xedN45 zslqQ(@s4UcdET2ONCPh%U?S@kkih~bhI~4RIU=!Eoh5suMa0xsfF3FjrrxZ_;!1-}Fm5L0>~-qpcBU3^YDACK$7g zR0HtIWE?Th8GjqqMnf~$gf6DLL?y>WkbjB!r}@MrNS#-y2VN~>dqdoP6S3k2~KZlDsmW_=ikgi1PE>*ai zc2+mk8G*s3(Fp{jqNxjeXo?cA9N#P$Av;<+a)U z?JKi8OzhC%v43O?zKO=L)$g<>cW1m!ls@+Fo$@3lF!9=SeDC`_PQpD$@6?i*Cy8De z@dFtGV%zjG4h%c`%^n@HG<#&w#tmT^2w7Mm{y8!4gy1}yS69SUCaTP-J3nn z++tp0Ix;MCvCr1MTepUgMNEF%K<~gnTjtGdiz(C>b#wHejffm;7m3qT#V^4pav@@Itwd(PCB&eY&)8BqAqgFQIu}1R(KZHNSr{|Q!^iF{p;ZG8S zqjF}F_3b&n`KQ;e?Z8PRvM&OXK z_}@DrW_Phr%J;Y95^i%+{k`?;@9U3;Rs%mWly4@!By<$M<2DF56+1d%mN1vA6gTm? zd`t0g_M=SOgT#IPoOqPS2}$;i;rseMNG#5%jR$8(>DO&f#N~7RGiu|@B}(~7j1oQ* zicn}TY#taZq8n}|QTwGzuvkX7-J1`jDanV440^I!DWlF?&;vN#hfxOU7c^gj>EAPe%*X= zbyHa8h3@N%*UD|%wsqfD5gPay58dGkYgRAxA+J+x-0_3V@4mfhujh+bjWREvfkUuq z+ADp+11e%uZpWtJ0b_rFqoUhc4{(!GRu6~bCg4?sIN@P@>PoumsZV%Z%GO6_y) z7T$;k@MOvQB~%Zy5ugX|oWiD4KTw@3@r0ZnP)OOXcJ&*d(#>9s?QSsDny&8D1c!(~ z9Mj=`ooLbriTwAy*H<WQjeeR^9O_wQ&*EqDyA&i%1`5V;w=j`q>cFi z;Q~iI9ksak_^|oH`nxw1aX@mF{rwL3#S{+NSdnaLhR5xc9L~)*#882_rjPJxBK#!! z2*fsBpCt~x_K3%E*rp%!4v_AN1JP~?F2AK^w*=3H${+IonRs<@`7PJ$x36x&7bCjy zoMybncc%!YLyi6VG-Fm-Tm=~!%``j{1fh*NM{-XPgs$dW=2`PEGqI0#oBz+;Jjn)e z;l4rp(;jY~DzlvahnuHrE|VHU20si#6UxWM;oLV&5d%)-Q!7VET?`AJ$fpVxytyXa z%UnP9H7=SHxXvt0RK~;Vr(V_&z_Am-s{uSatwMs144bV0crA5`N&L z1!qt&j1!Iu?$icwCIvf#g25f~N2m?pg8W^S2w4mo$z(t=K>kP`kE6B}oIJ=oqD0Dte0%4tbu)s1y7!nA(fZ0I*$n0Z)q!AL$fHMyk z_o{Z*LKuzakFyt9FxWC?71M@u=D~uON7{s^j2BwQBm3(h=P;KUelqBsx5JDbJ5;t3ISu|o8gnn=z( zSP-N{=^JT-*5-UD>zT;p{jTny@dk84gL<8TJPIlm$!3@+KF> z5f0QM4$?V=%jbUQu5u5#y8KH#bmUpQ?|jNn<`?i}VlGbdiE!Jl@h%#P7u&qD2aVXQDeP=t~KfNS>r1@Jx~aPKJM_$RoIg&}zYn zt0mwT!fgR}a0}tKfD7EROFfEHb-1OPs;|~c>#Dt_4cEqLFjJGX4DDy_kakA9p*_{0 zfllk4^*8k>{WE>Kz6d#hx}xXnzw1}^hk9M(B?CGdtTDv+)R=56FjgBs8bJ1rWyW2j zrum{7V)is0Xjr@HOou;i!bQ_CZB!$w4fQ%jaNsbW5-C?Y{9hD!ro(?pgJ(MY3k-Os z!+*zsXFB{VEO@5F?`6R=9sV5-$f2Leeeaj>Y;6(K}!LDE(`mQq{tV7>*<^!2}1SzgFAFM;)b>@S0 z=)2B*$if*wk?K10p|?h)c&;-a2tCYQiU-lUrxXvI>F-V{9yWMSDIPe}-u;qMTQ z=T)NcjX>TSM}_kO+`?h8uh>fLDiR3dI1y%wl9(a7xYW=fa>K9WJs4YvV|uyVbv8JZJUq9h{Zt z4$nA>58_FnyVbv83GdmzQGn~&zrhpV{E7$`zS-5k!4>Fk^>2ulJo`7e0^P0t4KroW z{tXQj&;AYRs26eX-_TKY@$pGo1GvXE5P}vA(s<2@&>{paa7Snnf)< z{|`_WxP!7D8!wp9!gS*534HB46S7RzEc$=h4b;IT8V7uFf{8CulClT2@ow^%`R@yd ze#QXBZs5=Jw|IhiY$bFR{wEyTQ~e45WjJ)H6ZQB#5htOyyKP&*;2FrEoT};<=@7an zT|FScBNcc|vs&({zyoNB&Y+#xM<4++G}D=RlZj$JW2Q5(h#~nJ`ONRkRpud6mj#Qv z=fdv6k1XNtm9ckO;yk<0R`ukF?s266tpdET)`8a6C{7)JW4{qXVE;F!Z4W%+u_w$F?8!OhO# zqqzRih>GP_&h6|2m=5gNY31eVd1P-gsNjPSWK0Nd)M$|Q*Y;m~{`%|v9Gue3JiJqb zBicEQBsCCyAi)H|hx%CkD}AZH&aq9+JSyVPjf5i~(&4Gzz@UxJ2AL{+W)xx6f}UD06z12AES(NeGL~eDinH&FVugq?{RJPBd3jqLHNm zX-Yp*OAMlWBi=fu%rLpAwolI zh+rBpCM9jqn3RX;CW;CqE8pwr6&jP8z5=a6ro$_QYvD(j(Ojo6oor#7UT)g-gp47& zTT$(Ra1Ru5;W=MgS8?2K*R;<-M+}+;`}ZHP1zj;F=Jq;bdmYZ05aoL%+CMqtA&OH5 zY#{-?BJPs`S9W7ki9Tz10I?uFM9S-cEo6088znI@egvUFKyo4xy`a=#hn)AT++BG` z$(ARohjuPlU|SH9Gq&^LeVwvHvd?87R;wCnBb!*+!q4c{xek-i%Gd@5qQKiLNaYULz{wpFLekgL9-m&?B>g-WTCroVdrA#OJ&Z^cYksEzW^ z(SC=Kxv*1PfBv~^^3U&lP)If3_*=)wl5Hy4b1pTAU>uDY$%ciri!+)#ICYR~bTJ7S z*^m0x9Hus>U<8F*&|Br^J#&Ok2n;pWq0s7TOiqNYnj*|WpSNEm86=f6^84eWV=DRy zW_qFfaWZ}9dzw5AH~13^*i@8z?0bN_dwXT6wK*O7YvENwIlono5}thzB5eD8Bf=rL zfnSitLL&sqUQ8)b!F0k!YC#Ap(;+CdM|c6_qMLz*H*?X=z`~okWUOG}&0I28u<&Ls z87tg&;LTiTC|Gzi7u^g9ligj$TDn$j%q}(S_naSutI_KGg#XY46z=6T0WG9{6tk!| zr8Q9!KNq!xH_G$vQx8m?8g3Gn`wNR5XEqTH`1oA(*_VJL$H&1lX0(`*QHe&T6y>3m z*!DU)0P_=;X5bsF`gA#wE8^0B_l@!qzWH`sXFZ!Aw>K_s^?b}3IbELZot@oey9;Bea9zN^&*=L)T~*`G6gb~Y4S0#ov~l(;y`-s4wcua`_plUpC0_OiMjxX!RPM5 zgQt@+gNR^Sd~WYKD}$-{IwZJH)y*oeuF&9&W{r6)%UC}dK9I+(P1Yxcd zE!I~q;qN)tXh}gRwOb}hy_fVZh(!I+aBLyR%I}(?^oQn1Gu|v+d%q;HB&)zY`4HEp zRv;HPgV`s{r&SL2$-I*6(`6q%{qVz(U^2xIV6FV(@CO_9QUcp;eg0-*au5!Ht6F#! z`w}wr3oqDS=v+CLv9OHnPLOVZQS@evLlO zVo_aDX1pWRG`|z#vxHrv+S;1Mpa7?1ao*Sy4&2-Lh@xgOBxLvg1Qee(i@hnmC*B@r zNBwZKSp0gcqQt53gnw?c*=@~YdlXHv;{~HxY*<9m6!Fi`P<&8Vcu9a8;t%p3d7^Mt zcq-NvX(_Lb^13oWnJOXldoJes+HLfK*(f1cGG&Vb4P|nAb(5OPn06{%!?aVWP;4p8 z(k4mCxPPpawC!axnxHlUhzpsp!H5tm}zmybVuS_J_ ztCb%WoOC$W4L_|Fd#MF8%N6)aUMjDXebggzsNg_Bj*`Y|RZ6Z#$nOm$FCB@k-7p(z zpuSDZQSYb)V%~Z^+1!S{tRwo9v*F>>!>^jO0Vto1(c<4S9Jc3KXsc@CH5Hf0L$0B< zs$+5KZJWg#oVJ&Q6osTl-s+QrkIx+i$vfa!g9M$3Oh%a_lzT=k^G?&JadZd$++*UZ zBEsE#!<%YCy-an-ARQ{25~xJ#8)^f!i#kfddFmErQogh^lmMKm1phs+)0*6iTnJa% zlN-bxFneozt5Dzbs3>*>x9KgSy$`@J-un-TZDOZJBo&;a)qSGutQL#BI)wt2Ygc{U_9Ch+lc|nBQZ{HDJ63RND03Phn1n2 zqf10Yp9>>Y_(EN(gejS79krhFhZ-Q{RjK8A9gSq^Mjl(OZ&~aDtI!%w;SNe1n+BtClmaX37$;wQ51MG!S7Mv$poKE zgC`TbF$11V@byf5fYHJ5yRmXI?u)XS+h#kwH60Dci%IDU^%b_R%CRwhaBw!e5UD zJ6crV0spgyndRI@?rk*?gT}TXrIrmqr&PH>!fLP7{PuaAbaV{{-{VBD?($;z76|wAoqndfmDs>(rVQ$w$*lGWLt@*D59gptVx;#0+(-=1oedUh!Qub?|e-b((ik} z|Ni7lfy&=%gtAR7)PW#T532sg1^NFgIPwH-t~U1QRD6#G`H}8H-~ON}wyGdMRAcwL zCC{M=257YWBVD~GfTWS4kH8>;ojrc2%Jm8ILz!1^dM`~9Gn#i~UTcXCmG0^X%q_b4 zmrPHl0~XdUK@OEHlY`2_nB2PT$NwxFoAiO^<&zxB(tY9lAp~IMb7Qs_z}Wz zp%GWaU*>m&p2N7s*xnGyE$6CPg5#Yl&S00(k4o@&wv;(Yl&4{N%+WWNE=2WSM}E%7 z4*5L_kDKxEBOk+(ao$~iHGO~!5#TtR!SljsR^V3%-+Y+Kz^}q#=1+bgvd%Yh7oI4nCNdH#&d14)aB&<1DbFt=O&Bt1R^)=Q)tYoZ3Sc|ci zU@gUxu$Ez^V5MSxgS8xM1=dQeRaoC*t;R~j`VMOiRyx*NEE#JZRt8ok*7sQJu{L0B z#QFhi6V_&|Em%Kd{e+c;wG~Uj+J=>lm4o#&)^@BNSUa(HVeQ7+gO!W57wZ?SeOUXk zRIEI#e5?Yj16T*K4q+X}`W5R4)={iuSjVw`!#aUgh^1kj#45rn#`+!W6xM01609>= ze_)-(I)`;0>jKtAtV>urRw-5)Ryo#XtSeYov94iV$NCfN2G&iizp(zsx`lNc%fPyW zRe@EBbrMnNeS~hQ+UPCH8^9=3R<{YZ9O?qf?9!*NZj1NI>6LwK>kh12N02MI_URSp z&*z^XZ|ce*+7M&b_Ue_`Yj{9^YCSy`6@X(+2n+HmY0D^3ji%{loLKG~eXPFmxA`dR0hO&>YQGMlEN*Ja^bq&jA&xFMd!Q-vB z*A@n9aJe+WcfZS3n$6iH4wk?3fZdMN?t|=2?$4f2C}_?H(!bH2m^)lG(?x8Hp~hw` zde9G>#Fqp@iI{g#nLvLcBnZp-xYZ=lYOGk6o$+~ z?n1L!@6ALqSABxQz$~n18yX}K(IckBy>LIWd^}N9)?w?^A>!o*;tyi{X!&PxwNJei zeAzCEb?9U8#aTCP_6R(vX7PFKFzJ&y^-`L6H)+zlR{PC`!WyYk_yhs6q6H~DtSlA? zupeS&PhdY(%AUY}NK!n3{otp10{bCT^#t}qsOAamhXTzL*bkAq3)mklcaf_D(uo=m z@1~Dzk-7Svi9~(+a?h7v-Zukf>@}0S-H3ls^nm}^h`WlnilX9&NGckA6J5Y0#IknH z;7a{-#DpIdOH0IcR4udN-NR+5urKXwJbim(+1l=h%kVAGJjC?=7FE-2Dhu>e`lC#f z#H@r7@XNC3>P+Kv^RN-tL||%+-#dPMN+q_ojy`*P?%kVGi7})dsi~CtJjA%IM%w*! zO0MzVd$#xLvIi`|Q1ET@Bn5uxG3rlmqvo4`=-mc&GVdu&~D!SioG400Iu{;n~FzQAl@hB9$XQwoBaE=+9QVP<1?#9 zNm;0&^9UY0|+sO%M&t5z`dIY+Ru10L!n7?r}u0Ky0 zF9;R4^YU8cU5!93dx)U0!-X}!vmN`8AuhgQH}%}K>1qTzIc6?x%foJAAm0?Vs+)vd z1TO^2m@nf=HU2lH4CK|&2n|1B=FTA@`QyfwjjNbY&mI{Ql8?8Z3r)s`@+j znFoPbWEKbo0l`1SmU)o0MMf>5RZyTMZ4pqEh8CHjd9G{S#I@G`?|nSaalFs_?)`q} zLl0K&`@V+rJbxhxpEeB{CS4#N*2XyE4|hQe@KB4iQNz^e{Mjey|=r~?^F;r&Wr)j4_xKj-)mztU#@+}?sz$o%F_;;VoP?!nZ`T)^Zo8#!7>6N$ZZr?C@Ef_k+)!r> zH=Fyi>J}R^?Yx2*hw+N)@xQtdXVLMP#^2$p^2dZ(5-gXVa)>Y7Nm$XW*Y!|=2Q)uS zY|tv3|Cxt8dz-ktcU*Fdh%@cmmM-u8TWIut@j_Z?i(Jg63Llk($F+TVXl%Xsgxtb1 z zB>LuueMhVCk{CQL1doQ`jSGPx9R1@$@Ms7g3<2tBjE3O3-r--Gm%hxxm%*bUcrXO; zXb2t*;a)!@DGe_ONJ+7M?xmuHv13<`9k<BnRd9ze>KAoLrP}DvJhk?gP&g97eh2 z%8Q-4jE;Tc3EM~IO)Fl%{{H&u#SF{q`W#cJz8{yLXmA)G^7Yrd-SFpk;ZQlf`kD%x zjD1Gt@y+95w()AhrcPJ5anhbb6g;8-q@_vSt|r28-}{Dt?%cRz*0{u3UUcXezwdtj?*BqIgu%^^Y2# zwJE(MuOpgvQ;7E_i{*Uf%J4O{Mqpj=>8&_VSLw z3q1Dnj=>8&_VSLw3q1Dnj=>8&evo(k*% zub5jU1RAE7Yme$!D10$T|Lcn?xrcG6{D=OSQFr~)rKL-+Wba;<7lIEqjKN#DG9rNw z*WIMjNDm!ayO*aljm}8*(O9Q%GPbSlGZitVq3epyWK{{N60-mN{{7L5&xMqSVC|7| zTidB0)rF;7a?fQ|-rhtcX7bLR>1&4MqVKTs_H$XsLh$KNH|k6_(HMBw zE3HaMkF+`F&wJZOZ;4n}RA+J8sdc!z+<1<_D3E9R@N+xo8yE;ZJ4R1=Rc~bxF6S*H z-2UqDsdlGMH7LVe*1CtnV^vv}0jui>%tOI7qLj}PIALh&k}!{(fP#yiP%%1uRDG0I9jsC%Vn;~V3n|CzmUEBtJ`l{t^7N>? zQBlorkeBZC)YGSHxQCt7&VgOW8~hUX%P$czJ+5>uO1d&fY>6)x*AgStz85H`e=+)7 z;hY@|t%E2r7+MDzVlcE0;-p|`9pp*D&^q`xN@1BC46TDeN?{4=$?H^C>x{&;bxvrf zqDZxMXEkBekO;hsUXMypZ>6X+lB1Y4Da^K~2TC;u;xyea)l^f;I~5V~6f5=N6EU?l zeaiC5xUyKLU8TTR)a9?j)h1lROFcq=ej)BZI2x)&>zsya-4$bSVcK&IdVpTg;kD0K zB@aqnkUB}H2j;IODP7p%%d&<{CG2c-SCFB8>@_t98s7 z+SR36f=MZ87jTt-zbGPupqjC)vSfA&F=GCZ@+b81Hk@zH4-%*No7ri zL>nV>_J9Xu^?0m6K6k&$ySaLGs!S^H!Q_C3O8A5nlnqfCOAn5#g{seBt1*_|)pxbw z+7xZ>RBDSvr>*F8MD9kh`8ZYV{AABYiEc{HGSkD_-`zNVHHQs z+qT_~Aqa9ev0FFlAhP6}GSGIexgsj@3PncGR0{uzj2?zPflIwCtuWF4z^qJ=uKCr3 zBu9o)F<4Cq4K%-+aGAPRgYDX3ZMyoWc3c zI0$x(?Z%Wju7Gp65dJZ~0skVp`=BpBlqc8MT7El!m_N-A|C7JZb3*+VSVP3;-9+I> z{ibA#s)X-c{Rd{TWf;GNZZQJhdt!5FCkBhnGs!LXyg*{}x}A<95f`u!$IMv1D_L0U z;-orJf|1g6X^FH^+AHNqL>A8slWWLC78l>>5Q}kJiZ2K_JG*Xnd>$4u?S1*s4**hE zL{h&~KJ_7n|DhD}G;2SR3 zfdcLLUV9;V72wcc4H!BiMlgKN!9=7xOW* zf%&4@#e}|Qumc4bsP|14qrx00Fu@9Tpui(`umc6Yw1XWe(98*Tpuk=y*ntAw++YU^ zoOOd8DBy7_JO>Kg<$@h3@EITMKmitz;CG<>?=J=1J_S2afCPVm4iq2@X`llICdk1K z6nI1lcAx-RNCO?D&`b?>pa5A&10AH$4Wruw9Vp-x6P|+<0*eW%C4elXfesWP3u&MO z1)em69VqaP8SFp-syPE4C=d*B?_vYhoPiD$_|pzXwZjA_*nt9%xWNt-@S`ReX#$#Y z9%_P-CSWh;p(Yq<0=n_RJQ_I52lHs)BO#ba19t@vHNi*|@R{hLCKzb~o|KwP3^l<> z6TnatMbb5?f-m47+R3kDqn9jCl^4ky z1I`*(aFi2aK5f2WzGn6|;UjaRshMdewGh9Uf0%IBtY-06wDpSB)B3;~XTfLIN-K~@ z12`M9MLXVp-yUVpw3pfNjqUMhDmYI#O&nx?$CdHzlYt^E|6g$&@TWJxOrTlUjQEA>+*qq0U*ObpkDx*3GD?*NEAj2)6p-m zQGmTdj$jL=LYPQ4-!>xFZ~a9@oQyd{>%^VnQ4!9HS43Bgke-%akSLBG0u3azaE3qw z$p`W{83GL?#0`PqDsY(s9%kkNWk!WS0|`}p5NIHwiVyl~Lp4=P)z)fM@txMdU-Gev z5Bwz`ReZN~c*O8ZK34GoHGHO#Yn(T(8E;sD2f|)6$FxnBK=>cZxpg=r z$8zqhbtNDGz*o*qv^D#`y_|yw<($B>e+LUNL6|2{+B$hbE(x~iEP)ZSOGdF2{-^_o|%K{uJgY$nTJ$m`^t@=+NAU1P5)y%o%Mn5bw< znzB_nsQjY*p}<|Gn(7C_j8ow=b){;kSthF&;CR*sok#{ea?x-cTy<{l7J^AKU+11N*W4zcsMh-Cw!``?3AMHBj0E3wvO{ zH6$9p*cA4_RQj(t*wa((?l0YeWcvQFhxc7zwY$G`2TFTr!ud;gptJ`T_P|PaV70ry zbcgLcVGI1fHBitqrSN;dHLxGs|69XAk$!CdZw(aTP+Ri<)(~8qhsnTdbN_D*?8o;1 z*6@NtKeqq32KHlnzx9j5UDEqwa}1Sma`FO>0Y<4a)nzJp2_Ig-M@l;_!0bJ@wb3O9y0bZzMz@P#7& z8YceGzK8*QAz7FzEE0&|%K*NJTzO1vAQHis0em4nVPWuhxMKIKKY{=Mo*z5btZ)l{nQ3A_vU=Hvr z3YneB01nIn?k~TAqCNx5Z}>nPrv;YZa8s+S2bSM3Q)k(PUil4A7)=aTepgec8jB3r zVC*&m%Wt6iJFxt|ci7C`L79w8m-1v!I+klvrUUpx9ayFV_(L67rUUpx9ayFV_(L67 zrUSh1P`(U>Ijm z8Sn7np)tF5@jjQ)baAhk6>}4%szYN)gntQF5Lx1%EpdKp5j^7$k?VZ=wCywXB*&aT zA9B7LmU*+q55#zBrnF27U-A;}p_)sUM3r7jPKWhkW0|77r#SDt`BS@}emdO>C&fMG zB{FREC4$&8SxwXBtrFBwo|M`Q>!rM^?3Yi-I}|vgoKgN#%9XjwD&!nSR@kg-KC)T`)q^qR)K#zs^!K^YJ#@_Lj17!x#DnV_(kAls-P91|oM z%`wKtBzjX8W(C&vB}TwVD^(w3QAQ>UGJr6 ztHwXTqf0oHN9a^0?lAAItDaSxnS$(zfE(WB_nG_M|+`WiL5-zX~*2VMx(vnODX z_3<>+L>A1SR}&XTY1PpG0 zlplb|h7}%5O^e8ozn9Mq#2qOIxQ{JRDyavR!y=p(pHO{6&mnorR}*0nV*~gPo+%z?GrZm;`za-z(otPqHxzFxhl-1y88|u4Z?0UrisHNWQ#xXbC5p+`p@#kb5!_;8 z9BYLNr4^b_>D0VRI@yB8psf2sIhvT-Pq~Tn-P3X8#Zgf>Lde6|O&FQ`5J!2mm-Wt1 z4jNQ2C<38Ln{(Err}G3&>eGHoSz4U&DGl8((3BAWpcWx0z^hA8q}KBi=BLI?rf?-3 zy5?i$RtxXY`WeU{df-p`KKc9pQ4P~GLU7UDGYX-=_Y7hH$5hVXzvoZYgvnjxq~-B= zpTqceGRJ+ zK4)73ODocrXp?22?&5&X+BoXsfKBdM8|Pcw1-5Zi*#n#0`zw10Y~!f12R4=WSN7n~ zabuM|1h#Qh*#jAH9k>0(sMJM?EhcwxP{D&5k40!~S~;nA37)f+no_vN#B@^BxlQk} zq}`Gwi;{5so#rTo$4^D06J%xh=n74n)@?ep1V!~jlR{I6U8sce2>e&64YjYjB{{>< zA$g^fHvAgivWt>hZ%IW+62+?Sb}zXl*YDtExF|_cl;NkHn^#Atc1=amL2q}suc*AW zC=s_%1CvU+Rzodm#&5^=lleq6i=CXhv`L04gAx1(dSI5Q9*AAL8Uv)<}KjnHDYIsy0B=i%LG{R8R z&Jwp%^PNl~4~6ADq^m+brSK{j%0JF;!T&JSdWOgMKxx>bq&dnvPNa0}St(EHE|E}S zOxTz)m3;|e@1u}?f{cXYG2MHi{3=v=TsbBGF2fzUpE69DE3cA2QL^P{_>@-s3AY?e zgJVi9wM4n#0{OU6ztg(;f>y~3>f`b$IvVJ&1Hm93-`OF(l(ioLC zpSUwWYL&R(qvxog1?Eh&F3p~=w*Cc$pVyriPmDo{!j(8Yqc5CMv63ST&p0Lg%FDQC znW)@-c8_($zI85VmGa|HKD*PkxVWSC6Tg#zt`d5l(97i9K38Ua@@M#Bq8bgpxX1nq zEsZN%mlk6UxXwBI+tzklw_b_ETHp`cu;H|0IL%KbIq$eLu2e*=Tupx^;E03Nx-Gge4@btP<6}IJQ{& z`?Vng3=m`Z6@rIB$Ia#}v7&T~AKzt*oA36KK9+zIvJ)giB#=4xM+qXOPu&=~vC~Wb zP>z!4%J(|S3*SUV79QFAAyn;E%Ur zy9MyaTe0Q_{P9+7w*aqbJ+;8*27b~ACg*Q%;C+3R9@yN#HNAr2Z*Gzepzg+NZbnL* z53RTyvM~!Qg)7F>yJp>;HEUxw_A-#yE-!CmHmVTnn{V%$iO=H;k>T6BnxF6e?)-P( zy>4sY){DlA;ojgX$G&4ep8JcBCQza`$t6xoZ`KMo>sT@0l}XPWxP*$NjoEk7aTi#K z9r2IF@=~i}4(da3Luy%-G4KwF%SSq8m0R%b-c=zrqvNdKtQh-YyF)tcu>NK5FX&?x z+LNrG&5I^H>Xf7pvEOjQQRX(oS?T~X2`a@ozdD1QvCd`bVHC%3cv;klGl#o_%%7zM z9!Qy%@0MUL%6|TFw+e^XO&{)Ku4!c-h4*xl3qPXJ_&M&l^p%^}WR?9YU)~E}VjqTR zWZSmA`3aAsWRRwqE%$S~_+pIUE#X0^F2FNFb-ppzROrqf7an#Z9oQz68M6d>1&QU^ zL4Y@eUg9Us^6XjS4Z9!SZiQpTVsV9-{X$7PDyto`0)=GYZ48?&k?$y3VyQSm+SqCi zckgSdQvoX0d=RDF9-E}UrHXPbnW|0bA^TFz<;60^FaIdRIho8hk1Gw8)(XK7V3i6m?l{G-%?|@hX1Y5LBEl>MRyP-X-N9xb&`5pA7 zJl+x^8TgDW?5IyzijP)E#@_RL_YTxI=$jYdy^%TZ&T?#q5^it$?qcc(AJ`uN-ZmFj z5t=Byde_{LbhPi}E`X-uOYQRXPmDP$yNaK#Js#VdW-BMw;R<}5am`5CylI&6jQOrn z%S6@uH`oM9Jxy&N=|w7`D`}b0&YXvy>*NdwHy^UfjcrDI>sOpvR>YhZGLSH zGXG_sv#wfzz<^83t>z$2FE`Cr^PD_Vy%Qd-=?Ib6B z>3NjV_2l+C1MLYWlsfvpJ@zxG6rSZY6z|!YO>5sUSGZf;?rz@wx84eQE0ve^T=#kR zH2;J9pm%!TZ7+)4N@s%5z<`++^-in}r?frLxHOKoWR0vszMGZK7d|HB@NI=sKI~a6 z3&XFMp(3unP>EZH~j7vB{L>H-VJ^HX7>IXJi+>aHdRc zt#z1;622Apb#WRt%-74}HvVQ}ZVFc5*ULJGb?!VgYRY5+Fzi=<)bfibuBm~wNA8@H zC-0xUUWTv>V{c*ja4z0hKqAi@c!&vxPqygrB9Ud|$=mOL8f5B60 z)-;DVHka4kVSe=)nr}|-ud_V&dMTP>nrOULL&L%^#G$RU9q09m(_z)`tSOkW!0@u(T4q_dB#k6%bIe#he6@ZU-3<^^bG6S6Q^~54@0lT z0{e)Wxyt$0$##BrvhBzJB#X;w=dr)h;&S^&i@K0!EYycSUGxzr){H zIiB|vUl6G6A!!c;YI{i91A*EelJ};7Ptb#g{K~`-pT#@)Tb_wBI}O5cyLX zgWTl|xzI;?kk_lv-o(m8Bdr( z^c21Nm5TOrYljXk7&_Z$h}p7tZ^+*GIWv?`jSo|k$KAa-MC{^HIG@fF4d|P zQY*r+mR__zHftKsY8^Cq$R%ZF^vhrn%+KU!uQq!(8NiRikttn z&XtQdu^?EKK~&!{J$m%$U5r?RHcW-|3&x7O&OCF1n{L9^f8wRt!U6p8(rn=Xfnp(A zIQSx>J+Tli900{a|7@3N;Q)c#C0aN@;C6`?4iLCqqJ=~LPjZq!VSh(@IV16C$K@MQMjc+1heM!rNqTvC?9q<-8Ooz?A|N|< z$gW)lyNdGgL9W*8gAe!*NIyiG+sV>!#P{|XomG^JCX{M@Uc(l%DDPP6B>A_a3+5N) zVmnd|rD+w0Y?zAq{&|}cFH6JUTwmHhtbhN(*oUA3q2H<07PrGI4n$AM(WE_Dao5+Q zsz~Xhe5}+|8Y^v;ee!V`3i~2H>LK3(?( z?tPf80i{*Er?qe%(qnQ$)yGxnF!TXn@0J%@$%l8BWKQ>y+3?A zN|PoVm|u{plKh0F-43=;enP=lq+5tq+i3-ICdp4&q;Z41y?fog)Lg;v;rE9($ioK& zg?juGlwUOJ2GL)kp-LE&ht6Ks@9E*jvkr7{-f)r}%KKUBP*w^YcM35qi8-`%DBTV9g)s7G>f}P95Dn3~42rYy_wc|Td$@(VPm!rp{ZCl2DMiYul zub&DIgj12_DJWS5J7&|B$uOSybGCqq;Nt`8x%W!a+GHWQ2PJ2d^DzKYydaL5RVBJ%e2u#`YP5;*@o?^b{q?9k0#DTvJs3_U z2}pLAdv3HeOIrRqp&lTq;~a6ti~Hpj?GWc6cak%!%HdtG9Q~+b?z=tFAQQVeW=k|G zw@IF{i}V>s*W={(cAUCbRnvN5Z+Saz()me~+GLlcEy%@Ehyy&5D>YY$5TAYtaG)TL zP^t1D?DbeZfAs7rxfsJ#Bg5zUnZi6jywCHqtVg7VZ;S64dOZ>eJss3tN_a;|PzQ{e zv$>D_u{^2&aih?HG9$AYG2mL6-)b>>re2t*=YMfX8!(|^Dqf!D$$1a_D!1;Bn3Fmp zmtKuCVQ0=nTYKd{WC~_!XW(L3HnI%A`~zmoU&=2?lmbUIfH%!L%i^Mn1VLE2X3F*j zCo5qp0}~#T`~%)LnbKscwFrYWc3b~VlAcUY(qjns!`G~tye2j#x^_uotE{r-QMFs1 zZ`m?BvQJiM7LEt5-j55->RLB6nV46Xa6t7!eT`>2o-sC-S@MIAyvYSFKt|wbLW2q?gCuNMwA&q6?E3REb@cSV9EA^6w()K}OF> zN_5i^sZHze=T{3ELS~~aE~Z3LQx@7TG&H&)n*OdQ9p62?p75LyC%n}NmjTyD+(iFJ zwN~W#QL$8@=DUH28bXo`cI4SIGg*MC!s)gb`CCum?C6Q{;#{$C6#{k!HD51ndkx32 zh431I{gkV{*P+;)~)sp{}UXe|##IJ6Ad_PU|c7?Moh=+R8`;rVpdQhF!F;q|6s01{P$<+MC=uT`6qsL6-PgC_ zqD$DKAIwM?j5RYy5TfWgZ6{JI0GJc?*<$T$ZI4z*Z>x3JfJx$6#@K%Sgno67zCz!! z@A8go0sS#$@FdLa|Oz36?2iwD0 zGdS2DKC;*n)Z2l=T`M@)9;hA(47P_So#0@5@Rp$74m7i!`?|Y9O?Jmzy@PfW{t)hR zei`MibvKr&IAb7v@I<}NPj1m2Y#540WTX{ezl4K^?fjEf2@*PZL1g97c${$@bft$X z;UWp+m~M~YX1R;G zEq!IijL33fbzGmsh;>TU51@L zrQ8*bGtM3CX;fs-Oo{0MYa28tiiaN`RR zdLVwhFN0xI{ZQsXzZwEzg$HAZZBC5E;N284n3;XVM+{m(Fluim*^vFYFTN1%(m; zM6w095<821#E->Hh6vjx_7Xm9)}jSZR+$&Fe3Cg}nz=07lgt5yF8?AO6n_!ZRm@y| z7cPq|Os%clU8XEG$dj*1p)%2vo>eF!4U&{klo`rWWs|Z`p;{9ceh;ZNRg$uISKn2K zt1v}fs6Hq<)e;pnsIEPuwbD9keYB4?A2)T4M(f01waeN)EnI&}hZy};o#G?M>lD-X ztq$4x&-z9EmR`lEW8i$o09q%GHf9-A>+LsA7*K3ba$_yCsri!G!+g&KG|QTc&9BWp z=8xt%^QsAPwDkLEonbg1ql1K(BB+Gw#7X2#(uyYA4NFoo&a&NkoIls0YMsYK-$0l75i{u8H z_nZ`-{zuym9$vxIw!?Pru_I?nBZYSaS|`sJV6_lweJ`96ei!ZtRmFNDJSWn-Rz(>r zt`}Yvwuq1^=Ha^TocORrwN_UVXeaH@g*+}np%jcahvD*nz?*{-j5mkRm0-L%1m{Ao zQhnM7&*)7H4-AD0#+$DV1r#aPJWWok>xA}uvU^-@qMea^` z(PEhbs+DRH2nYNC9mdZAKR_oPnd2wztC#HC_9IT+650#9%vsVEDv`6q@mLJNU<^zN zkK;xY{JGo{?{qL%yO7}qa}o>VI6~)OuIO!S3(&aPsZ%m%a3sNk3*1dE*iO$3`4*cg?G;G@R?ja{ zHY$6S9K}|kR0&gksjg}_wZE#UFj@UVU8n9;kE&NJq)%%vXs>C#wU0E4CxtX^ zt9DTPMf*d$t5wr^9isJDbg~yxp6E&)^F*`spY#hl29X<28qE#SfOzA5W0Wz|pp@G0 z49kEbT-{YLpD>%4?abG4KL^Ra=i2{T1ADIhuQjme+W%VrJMNA>*AHH6M{pkC?kH^G zKgHciE>Il(ba#on(cSCjxV8%v*u&CjSr{$&(`Z>3E%?)DSr{$&St$&a0)AEsL#2S9 zmBLUd;Af>UR7wi5Qdk0E zS2yyJgRgD~w7ihx1p+NEbaex>yb#ZaUEM(Xw?M}O$a=8j0Rk;A8?(QHEfuVKwDH&%3zG7J{jU->G1!MXG0XA)gBn z$~KT>3xu-uQw@jeKqy;3)$qO!!BoR}1`x{DPc^J-0vlfYNwz3Y52PBlw;-5mn1do6 zi+ReQ{uPsG9wPK>I92$A((9ygOxj1mE=4ARSx!RX8qv-I_JXEE`+7zDye>#N7B;!PV z*H%*V%Bz%;2Z2H$ySU7uPSjLlnB1$(9k}Ib^&|e>ss04l#POwP?qKmBr#e|BFNwFsAgB5PzEpVNR4)=V>AFPy z9lYrdbjP@qib3<J%?K5)E%kmRa~Et9d+zx&z>k`e>!LX zm)E}hvPtM4yJ-@mGUfg+Is30}F;8r5c<}g8f~ef21i(FrPyrPeU4YxO-R8X?%*}^< z2$fo;wKk*3EN7U9JNaV|<$+y7f57RaiwAM9X8|Uy<|bUs@iDf@tU$CO=EwE5kiV`v z+PZ7*#qXNt;=-;V>7oS`7WJ_;$@<({WxeBMTPPUA;D*$U^7uYZ{t9Qy72F4`%nJ>* zLuuH*`SO4PbqAzo;2L(b)6MDc;8i!>USgLzVJw5A95$i6qs;E-Vpgg<-ks~hDz`iL zZnbxFFviS1baajhE6hAMh08O4GjEs=TYYT!*gnqPvy&`R0TjA7I9S1z@ec_z>Sl1? zb6th1Lgr}h1dmxj!VclYNAu?C^T>1+5!oqs;>d{;4~9n9M?gy!Vfq*-@(X?)zmwl? z`@)JQ2*l}~==pbP{uy7642WjqrI!RK7XL;y+X<0|iu(Ey3 zuD`1f*Qe+U_4Oq9IkpmY_-S#t1}Q%nN;-U0!eYSOv(MH(GmL*rKDNwv{nH}vCT=t< ztRab=iuVVl={1iVgEF2b^>7rE7Uz;l09E*)(u@d|_#G4Ktcq+I^_&;HH6fr8$5h2cUc z2i|ec=zr-^P9b;EX=!va;2mR=xetXY&tdK>od@_FbASGF>S5sEDVMhN@E*5?%Xg!= zmRu+9VZOubm(X*O7Pl%I7gptIWpq2EhE`3Iy=M*`4yrHN>R;TfBx##yH^*KO}UM-lY%nDn<>k< zr&D&+pHu&}*Fs*~?Y^%Sl&?xJD7}GM@XRVuP&R4OBm-HjwmQa!Cn8d zk`4qUnV#W^{izWwxKmHhd`^#B*+YNW9HCd;nwG|+#vUd11}^^g@9Ggzue4PJM%VP; zK??7JGNeTnl-;Qhoop~M-gsw>@v6}aL;K;3NrawvtRdEFqlz`$f@5Z5tF6`DBDvBb zZUyQzt!K8IDd+b;8}h$9^Ep_}#c-c;Tlh?V2>&TRpNG|ar0}fJ0bMgm!Y9HE0hS7z1mZ4W z(xvc_SW|??V%vXonIy}EKwT!uG9gfxNwQ1`)Mb(^6J0faT_(vgAyAh|vP|~^c`Z?) z-)4V=^Fkrct7|x)S@)_56W*iv@W{xb$Q;7vCQ$H*4HDdmL#^ zs?8Zc{`UBFWpmPfqIMCJ$ng#&^L=KtDo-m{mugY-;zAyJNPh@W@V`u(x^G_Cym^b1 zH`Ny|k4ER@@`)+y)%WycD)T{PEc$um&p#I|xHB2w$g*Q*O#dOg#>;Wi5n&m)@)7Txa`O>_1wyS6n0b_!()pA3=H4k0+e*7>#gFui{9)uGmTV<2b0OzMhDxW6ory1j*kPD%73yg5eYp;SM!i#%0c=RPKnIy0oF zs_w?jJo_CK$BxQ77Iy4defbe(oh>N4SB=UIUmuUF8jMf+IO=w2yo#br61k7ctAw{( z`$0qGT}qttmI5WpSS2(uH1U|ycub#=>RAw;wOsy}Jo@A@IYljzpOP_T{V9c63_DLa zmU<}lFmCxzE~r@4C!|gtz7C*yrSg;xlS@+Ja%!YZpLXZz(6>GbV3RRvQ`UbUdVgFYhtnbM=n= zuvxCZW#SU^%jyO^gAd)u<|+L-GY)UFnik%~s1?Y`m@uKugxc0CNANi#fiR9*zcf}_ z>W?JmtoL1{3aCDsc<#GBR%iQM&J0uq!*OM-o?)-h=a?(Zb9UpkD9wGwIcGJt`#2vv zHJ#5LXzO%$0=YL3TS-arC3fD7c_Kr#0>7s$N4|i zLnICwgHO`*HCPzsWQ;)-QeqN@i{@lhLLumEk;0#zm#-@Dww$gAa%;7#db-CDb+wG# zvN~u2%U4dTf8qkXss`Z_B67566gppXP{eW8PC_>+C}*d>0SLT zZIixFhog6h6R2EgA-7MPz}t;`fN!}{KWVb<>!ZNN$7 zOHt1-$R2CYK`+!68^g!3Sc4ljSy7&KJmn;oN=!QGDJRil#iWy-auU|Nevb_0L_#aB zGe^1;PdN#PxL>);oIgJFs?Sx*PkW5o^D+2hG+2XD*+1fjFOHzPJp3e96`Qp>kJ+~) z5mQk#<4{C{G$MoD=AReR`2&1|O=GYvYOn^Y?pUEjYm6J;25azHIsQjYynp5i<};qE z{yR*Wxe`UZ$_8u55HORpw&D{ld!;oB+YUl*oti{A_V8>XOaYXX>_< zVWIr4Tt_}813Gq2pkoJS$*q)s$)xpdXuKzlkYL&?bP&(UC-`&xRX$XJ$Au`hpL$05 zT^=ShmfA}2m9SX(TDgearAb4{g#o>^549;uzE6sgt-aL_HmQGqmKU30)Y22g?keux z-}zz<$|4V`--}!H-^CjWe5l_*Ax10xS!0seSV=OV`$t$}eKy1B{MlvwXJft&zv@-Y zI_4qcW%IIe&lqjOEOR+JXZD*X%wqFzv!VsHtftmWRuAhviy%jfE%@5nWBq86w>V~7vCr6l+2yuptihgPh{KAs4Cj02lmovzcN`Co@|HWu zO&ROXamiDY>E^ll*GSVpaSCesPrD=4I)BJd49BXp%Y0I&+-o~3Aq4fa=q}btz+V*4 z&3q_LBmw_tpS6z(=kCo?r_3hHW7DR$o2FHnQ`aM4w6B7W`YxLF@bCrNOMKVbcS7*K ziQx0~uSbXA8#OpmrNszwCDPN~bU@KN)U3(ZBq<%s)5u)=(7XI_eoEa=AqX+W1vXxw#y zk^*qyUsA0thS|4|LFMG|_EpwL%n(jgLK$vPL~#ohghpIEPfGWhb!tlRF!!!7KpZX3 zdeF|mE@_Z3?K8qJUUqLuF%n$;=(zYYH(DOR?co0ElQ?xMk;KnP-uCi+IS2~fi2?7H)-2-q7TKPE9%7YtK`*ccK>o29#x{0 zr-T?(p(My;7sJ4e1?YP?!%veiDgCwi3KY7<+AXE4)=z6V6um_{RM(%u&#trH=YjkO zJpGR+{{c_`)()Bkw#AB4g({ZFX%xJB|G@bo`)`R%ZdSm1{q69nNM8v>!nr|jSD z;TTTu)N`J5@DVtfbQ9~3=!+B`G?PUA@>zLk!pTJKfTpp~*>8R${PxKt)Qv9EzbRbV zZsp2l)v;AgbVfR@PYx?7I+=(i>CshdV)HAeo=n8oZeq#jpSSsZW6ALgSRie5mbfKp zH_#VwG70;j;ceWtFYhlsnTWSl+6@<9K%efNvi8%;@a6-R*k*W_99_&5?N@xk1@~uM zn4fxYQ|&d^i9Hb+84}rk#FTjz-CAx77c2Dpne57biSNO`$Dcdro&y?sk+USR9$Mp0 zCT-t-e|usiO}N9u?Qj}uOe~o>vtVXoJ$(L7CLx7xVjGUuV5+mxrPv>^Z;=Km1C5Qx z_c*eBJMfn4s|* zBJd;_FOB8qa4Wb?BD0{uW%-^Q!{rMlLjKK*(yeaLO1&kmQohB?ajvpoJ)r_oNLH!e zs!g?*v>s?*0Ez)%D%T%1%Jc^2`D(3q)%*E8I6$tP9r_WS<`?DqqXv+>p_B2B;hVP@ zs}0C7zBfD@PCfHE6XMLb%t7W@lM1yhW+p|@v)P-6FTRyzePYe9F3`lWd{h!mIPv9h z2t{zE3`dpav$Gl0BE^9&UAik1<-MmLYgD`8{xJ=U%ttrq=5bFsf|p3v6B+-tl$+T<-3ng3u>ud;FZ zH?qo0@v&N#uztO}9%%A4WQaS&7lz!paZ%&fPf?&o`AO6|r8G}iliMq|ZSMZ~J6X-+ zKNBM}4|aHFd6va|LKx0u~m({BI0kjC>QndH!7k0Z+c8*#2)!6Ddu&cAnZNu zeXUsYJm)tDZu~Kt`|B{VM9L<1lHQSEzSElT$}hFLigV>2DAWTQG!;v8E7en;`{+Rw zLDl~W63h<81_ESu?W!CavR%as32=3DVGU6zN{ew4K0T&R#fY*Ztj{j2sTg}Xt4^=P z<Vd z&(X4wIwB4}vE4wYUqpCbI?fv?MzhQ1Bx@I*#GIJjxK&7tsd~3+)sP)z1CT}8X9Ku! zY>Nq*X5M!f&0A)qO=Zn*_AM%vt6#wQ3g~#gW5)| zN>wM80bLx_m{zv8+U@s~Wpja3$MpfYSaCzP%oG>)yC?3BFQ5RM5(CUuE_A+&-^V4A zwvI5rw@x9J(Cy?Fx-;yhcBu8Yi&)HQ+%P`ht;aq02nDvx;4|sN>Bsx@pEX*xOm0~t zG9xxF9_K!Z#SjM8VKdZY_6}S>6@R@4*9{c=LPk04Lu39z$AwR|4nv=!G1s z2F~xn1DtsCdw2ji`DcD#NR2{U{nan_#Nr~h&N%n|g}4|BiK-Hvq?gb7f~tCKu&+)> z^$ChkR?wSP3ERb$K2-`P>29ghD&%r14h5nO*%-K{{M}S~GcgF}>Oh0#uF~3%BRfFO znms;yWlB}ESbrQF_#X|r*Ng5J6-`{@V?2Z*ip-?=R?BQ}NCs4}D8AJ%InN|_PWquf z*E0^bNI!ZsMRx5r4*fC0CVn3e>xHF= zp~}Yr=2D@$xK992Z|=#>fo{LcqVILa%JNkS=!vF#jUMxC>1PS>MV6{ygG0vr(9Kh9>azzb>98dVQLCilV7Pg z>}lz;Vb7yll-5$a)k(u*bE1zC5%$6h@!A*KI&G&$)COSgDKBaHBOUzM21acF3hrfQ z1Lie=z@+8v*4F(0yxyc>mPj+W-u$7dvD)%=-lweJ%~L9~*Z$La->~Ld|Dp3 zSwxue|NYLJyMsL#}w+si(SIlJXPs58_29~#c*JN?aQ!Q8&pc^LHFtEI3znK66 zb;BeZ29~$%k6Q+ox9m3)z;@TK8z$K>P?pkQ&L6i7C%H@9ZO$LJ3&DB;x;r9l%lIDff(_arR+Nazl`)${6gwUSm_Yo@i= zBn=X^k=k@^uR=1^9L?6CR14E<=#BJ~N;kc~uIMmX_gw+{QT?obMR#?GFrGHj^cVFe z#z)3PLo*=F*lHX!p4WRLWV)Kko2W=^X7)5cFvpn$3^PoiXvGWWO|!D~q=lI?7Q|cc zTcfO*)-vlG>pS#_L6LRMs$f51H?iB$@Wxxk-Y)ev_IGdwqrwx^O)1XdC}?O z^mT?hsspS*CH2Xl&V7e-0W-1Oj_yC49@N2La@I)<-n#8R!qw#j4q~}Cxq+OI8pv(t zOb&9n^W1f=5?`Bd#<%As9*6}!onOLl@-q1w`8(N?p-8?aS5Tf%nkem**A-cTWM!(dNZFw5Rvs7; zL)6FA2I`9{c?BtO5K`5(>UQ<8N`q92OMv>?^IAvkZEdhNL7S)P8uC~UXeYHx+HLI- zy{<0k5Uanb57dc`!O$3xtDo1e>y?b!Ml-|r9w!sSfR-A zT!>^slwC-6gOgYvq@$7TuP;ZFBS^*kjld*UsLux{u>uW51Cv-GScql{5G+KKL8Ny8x+1v}1PjqL8PbBlOS}Tn$}37w#RD%H3Iv0fL=_0U z#1fZT;4%aY(PRyRg=mfj!9p}uhhQNZXFz@9d81=MRw~991Pajv6UasF7owRa1Pjq5 z3lgo7)^ux$g`uNXj%8cmhnujhRG4fBXQe`f6P%R_X-;rfDnz@%S*hs#3eHM}crG|A z6^gjvtW-$mr}BaRF9;DH6B-CF3S9)oHi1-Ot*~7SBB&O>lZn{AjI_GCM;YTQq8sIcJr`#+GK1Kp!{0~H(_iO zNVg7HC#_4?ZHuu@zzZ^&Z8NqBk-=oA~;H%evRwRF}4Y?*rs2&KRCuV0j8SzfFH**wh3hMKk?+-sw^NLL9#eiTqJG~cZ-Z|0z^D&AiXGckr>+qQl+)hcImKmT4HPys4qV+ca-0j zA0&%l+=qNXJ}F<4Z{r%4*d`FGyr~RS#wfED#x{Xm<-BrTsiZP{ucQL=_byR4V)z2F zO`udIe=pg48QTOV2bA1YaYKaeFS)7WhBSSveo*&=(jc(privS~jGv4Ph98s$@g~J0 z%rrfFFED>Efznv71<96|guv{*5Mn=OH?aNoULc^}cAN3^$leR}o#&m74$?{;#x{X; z=YY@F>$!R%)@4FU&(#aL?s=ENO_-|}61kBagPSl{FO+g&JcFAswh2t;nLLiPm&7*l zne<)|UK9Q?>7@xy(+q*fnNBl|5@rg^1V6tFDu_>rO+-Jx3<8fc zon{C;&UBg~@Ho?HhQQ-Yrx^l|Go5A#JkE5QA@DdSs>)cE`4q&VD)^5zJJmkdeju_4 zUHg9i;nVtL%+%NaOa9^icdq^IOnJ&&`!DEpstH2;;8?R$4VN76ShG`&xtiXwW~Uk| zalvMNSi%LH^`Q~Z%=!w?PBl=5cp$O}{KuM|YM^|bKx7eoAdV9QkwxJ5-ZJYgP?&un zvIw4#o5+F4A|PfF?;MmpWDyXvC=gi$#4Pgn&>dAEX3+%owCo{^fS5)89(te##4Pgn z(APB}W>Fxr2!ea)8U_%vC=gi$#4HL#76CDf{5|wR6Np(9h%AB+ta)l6vdA|q4MZ0G z-!SAua1Y&)^AUIbJ@o%#?@fTSsMdY&Crkm9G>L-DO;83AXo-S=goY>)5NHU90zyNS zd1w-3ROk=|0SRpo5Kw49nTLi5$lN5#sH6p%C3F&GRMLQgfRMh=^RBe-+xMLF?R&qv z_q*pib9bD4t<9Q{~da&0OTwR-k~dqK+dAz z9eRa$lbl6(hi--MJm6AVm>lFPA#M;cazi{n&Z-`dBjPe~+qUU}wn24C?ic_a;`Fgh z-1o)5|2`?MZy;i@T{q?!IQ35JapA&*3j>rF6bb~UC1lU+iUZSm%6IRcJj_X_bInyQ|`u<%|te14+p1&7F|^HYk>ct8@YOA2*P)(uWo`e_9tXW%40Iu%pR z9NlYj`IJy|~f64ZMq6bxqgl-UfGYVtZd_7dN{10lT<8X0Xd-aTE4vme$-H zt&A}g)aec~@bVVCxY4~Ww~6(d)zgx8-(H6KBRt)+!Y>_BsXSIx_;u7UZJ15vF(A{* ze*2&mZJxHNJXTcrrH0Wb4(aaxUle}FQ{gwgEMk9PO(8R zQ@=-7b+IOj%OOF;XeN@bP8RD^TcziJe5rlo_`_DhnNw31-={tn5YTRUzr)$A zvBD)lH2|J#qNDrN$G|>^hLHuE1xFwa3xs-DNW-#ktH?I10nX^wvu4?|0N-BnT9hx( zmnTHx)P%{xr$Wkdp_xR#Fa*iGzOC&SCK6|{`jXcIZ3sm=gwdx@BWilJ7^kjpH ziuAa`ZS4aUj?$$I^P1B8CKfoLw*1oD1jODby(g`dx69{`$S1lTJ$kfL=d#$}Ko0?F z2>3vKBOQOU)e{46d-zUxR?huRe#Ayf-N_AcwpLzq=7wlKDK_C`81@m$jO?*FBC!o7 zF)p>}+$J@z#t=AFoBg%?Ic!?j8p_-1JvKJJ1o$4x0j4VEshkq6yf7TjwWXE;p=@uD zAgu@5)u(HVG{(6gP6gDE2Wu=7Sz0AB7*G;CU+SV|Xy0q6(h8M*&lpXO-D=#1goK#;>7B0UKUH6Z=b@N(WXpCHB7>Ch~lg02&d!ez922Rx6{6@MFGiFTK zm`GDGrSFrsK5Hb1v+m~_v9H!aqaCC|q} z9k<%o>@`;C-4#gm5qft8&GGK8gqkSl!e34W-`y1q*MD~f5`D0{YkH~V%+BfK5OUHd zOG;mvOWkGKlUwc5cy;yI#d;944M`czb3vKD$4Qx`d=XZ8EB)XKltL zS%v!Juyt{x4rUASe-gDWuyoPz_W8Z(Ro=k2%7#dnz5mvj)H;y?Pebtr4f@2O5aER? zZ(J7c3Ar6BH@H2)H(*a7iT$I0S)F}u!Y z42(3q-71}sbk9byZbS7!o#tRJafk9ny}oU-k7VK(VRNmWo2yn0t6J{(z{YnKM*L}| z!g$Ghcw4J>G|DRQk<=rH@Vyf;_dri@*r8dVTvpBq^!IR1Ypo*DZi{kY1OcZ@@$brG zDQi|mY#_FZO-L)NR#O{I%IzV4pv~5vR2I#^ecy#rrAh%t#dGuGd)dgmQ$GC#XR?J2 zZ=-IQ92YJEtq#$1u#52l@?4aJJsDMOD%s=;N5u1Df{D4ZBl>wA!#`3l>8kcXgU9t6 zI`sq&sAtsULxx)LfmO$7X3VxfHI^G!-|uC>aAUHOV$Ly_Dm9FyW-$|}55TG&@fP(0 z@INx!Vh=6&&Vs!FU=J--+y?GIy9?&aFjU|@w6KID1S5_t;W%oyLr-g$^QKLkHuboQ zfs4Rfwo~}nO?(xk5MTDx<7i1(Hhb!^mM!nMyfdflBa9V7y^HngwMjU&tSkYB9YBO! z+f@9R7Cai+v17-EsrbSOW!zBL(i0ri=GcVqhQlhV*=fbF+qHk=kur-GRbMpqIKG#& z>CwJHe`cB6In-}(9U{N@qWTw8k1L9DOnJS0%;tiMQ}CI+eMQ{fM@>DxGN}XK@+r&} zZH@}Z&d8%V%fm7%)W0?L82J^>^1nUVD!K)~g|FEcQ#nY55+(|lRwPe7HV!K!lNw>n zXzFpOVssJCnX`l?!lviw0q|bM+Qs@$#%dZqyjv7*i{9s@v?3y(AzIdUWr_0h9-w~<_VnRZZsv%)%)On)TOEt(!XQmkwRW>t;V z&q>FGuCKngxe|QeM?1w$$R!ssFvrj3>!&5k@5$5pywl4aPja~Vx!Gu z_l}9lj43xX!zAU*)w-X5Uj6f_$1$g}Sb2Ta%yj76CfWR2-KI7}M)ZrqS{-s#dLb+j zK+F(Ys|hN+tBzHttBWR7QNCC6W3vo6VNi$U@}A4uJ?%*4jT%s5pHNhPN--)is-T|X zWzkp^4Sq7bEER6zj`;Z} zJd@>Q+)g@f19IV=XPl-^JBK3SlQ9yWvfSC?P|A%$ZrAhbiX?n!+Vq-J_g*+|xn+_! z&YNSu3$| z+`(-pZOe%g-~*|taLCP&es@zx>=f@w`!2*DP#Vasn)HH<%{IbBC}|7!jR?pYLa_H?1Mo`xf}U(2v*gjq;%Krq80&wt?Ag~(V#x84{gM-#f8xUvC&rAeliAl9_1o=E zc`ja42!tC+%^+-)i>A(wW9D;1dE$kX#;a^ADdWaH|QJXBQ~0g+Z^S7wdCN zg@~g=xf8>n075uGllAi%w7Ucu0XQ(G8dTyN(zp!4pz*83(xW2ZW{aY;KgA zlB&|ra_%Q{WGas6|FOf!BNFX^N>&HipMidh>PZ?13D z$Ziz4mn@gk@2s>bxKp0((WC#) z=!mo_STAXlg~9S4;w-3VUp5<9eeF?pDt`P|<{ZSHNwlonCr@F6q<7@dBQ|P5&K6p< z<3_yw8*W{dxxdYHXV7{W+kCC{vy*Kta3~*B--VX$1MYGDwmsavY;RZUJMibhQ|?uF zqq4<4fSoKnT5d5r;BRZBLs7!r;g~D@^I)oTj~lol%Mtj?H^y4fk5A@HKQ@s2nxDzN zC!XVf{hd#C#d*cjrXX1y?(^Z?Bv*4I2hQhHglW;?cwe5N(1=hG@&tI<-Yoql(1@@N znqYR=@TN!y*mO}7mer}j|1H90=a76(Cc6Ibzg!nTmLlf1$FKTU@mp!3@QbwXh7@@B zmHJ3R7m`5CmC{nO-td_EK-M@fjDhJw1*l-&t^w^j0M)zeyNm*DKnm;l76@T6G8167-(RecNV6H~Qy(+74{u|5Hqhg*}H zTd{FeLkmg52KQsRLrf!2rl)RybVF7^Lq*Dt?J%D@lUrNnk( zyLNyl{7D%Tw?YfE<2Un-o5oI~-FBk6mvNQPG za~5=Q_oh{`KXU8r$u=nI1?7A1bsoC;&W}9ljxL)I-}p_t8i_{=OLz7iN;cCxqL6QKFNn}qR5^T_#;3=RMS5U_&=M@lCL?~2pj}jvNX9rpx7wgv_a63_}`3EM$ zIMPL2QvyV@_aZh%VoPL7!C1QRr@5>n@(f(TYh#%H@?1=kqEY>mPaaKMG=(yiQ=GpJ z)laA5$DDCEqlrzxy2+3wFk9cQ-_=Ixi?m!V%6P^Ym9GTA@KtemQN~C)xL|T~Vptxp zuvY&SEAJtmic7|0Td*H{*vek_5$=X%%vZLoUR`~4Yyy57qq*LCj$TduGNvb938$E3 z3LZtO;BW2NjTnADsYe_{OT)|k#h(pIqrgH-76(|XEJ~wX!!!#}oQ2{jnbshCjkd~$ z3X_w~_4a(To*w0N)Q84G75goxRZbmlmb1iZZLH1v3%~#E^XcmujwjCzmeP_=7jaIt z?oQJ?*l~DPq-+u#)W^8L>HYc715Cpe2Hxg}7$Jh`2XNf}(p|J?qA*LKQrP5JSi)`M zQWp;72IF2xDKuDbU3aJ%mdmpg8ibATXX(lTjnb`C*T#Jre~vCna~#@?{hWAhr%{c!GFhFar(EjET)Aw}7T!K+qfu9_D! zIdYEMarBa7efm`IvtuA;r{={RxYbMD@$3HE^BUvjYe(YtUE8PdR>t98IlZa@L}Tk}a8|55@A)~6 zlQ%>p%)`BV2TvpaKv3pep7?Cd&DYIzqi9}BL7B?tbLI^F2^B{4Wv5XV#muVC7`%HX zJHJ|Ytp!@KlL31s6-~l%<12SPizjEqy^qJ?t#V!r)*Ln-Q0k*~+M;GrWQ=w#s)b0z<&c!UR{M39>68G)b>y#yF8 z(EO8*iU))gkA4|8Fc*lCL94{^B+496QRS;GQ}O4gmlej?F$dl`?CZbadi2MZhSXMtCP z`SbaJG-Abp+4q-=H@AofV*BRRNuo(hc-O97mt`?|LZxmG<8R%F#5xGJN%CgxNJzak zIqya!?h+2o?JM-c3v#s^QCVGa3*C{Botc>?*OxGI zMJ5>7!hTPmwm4rME+2@c89-m`ddt)ns!}fS6JA_V1L8>ERC?{`(EmncTvEQV?-@1l z`mwp!vKx^vym0@8oZEByFI>0~I=tMW!;L6B4xDu#v-VZDSX`p|?VT&gRnhi#{4Knc zJc}<6NFH>St>k{)-W6HPWKFAx%~$Xku)k?SG!Bb7I#RNi z^UtJem}TsUmCj2Y5|(8z!-2-Z5zDieZ9IDVblB;|$yu?p^J+9~WKxtpVxNpj&-NU9 zTFrf=?9z}-`2CzbYUe)q(Z;p25QFQYAcszCE-~$R#)Y8`QcY@ z*II#xe4OIwO=&cDt;6+W*~PQ78#~0+d|fA8vqdxO_Ni^d9(%0$W9?Jx_s5IQRO2@T zR>`ld!Y)lF0r0llCv> zFE)5UWs^51!)@VL{5%X762w;ps@A4>_Rmv|dnDC}Cbz=LqDW;VigRE_mE+Oz5;AiZ z)`_kmYEz}MRv~f|B?im3aP4kQo15xxRThSAFB&hRk^0@lHjmPl)q2pXEmbyT@lY?xN;WGsK?AX zb*lQQDbw(0Jj2?h9o25yT66J=R&G9NCBkuVUk-E8?e*UJ2qOQHGIXoXB705L^RKDZ z*W!m_asGq}VH2w3yZF^4_~IXl zOxA-);m8=m4k z#5W^+!z#{0d^5r~C`x<2H{V!Mc}DooJ;>vO4F8BPUK9V=skKae$|Pa0*7ev|g7 z|2k{5FE|D2Ilp7a<{gj4CC|gnz9*LUV8Xx3i|z|f8M#flxsP(^CDXHHwQ6=Xz@6y1Xw@TvPFM(H!d9IGWfQY@B8Jjckb+CW~ekX^wqNaR1z8627 zCoAf5cB47NU*{k45dv`-;8lUW{>>6<@tcG!0g#%3Pu69{xo#tIfzU#{$zTzS#7lTU zs(#{F93C?k2jayyX*~UeR5|Y7XfG;D#IL395010F+Q4R!@U{1zmK*kH(FR{Fq21_q z?eY?qq+>j#p$tL0K&E^ViKRexfmg%|il{KT00bn1N|00yPpSS=5CrW4OfCRHy8x35 zz(MV-#_R%2F2ImrdXQ8NS1@h#m{Hvj3`VMkamEbe3nNIX2HKgJU4Y32;B#}0xyuZa zs-dpc++ubCCKrHjt;5zY7KM$NTmVxTo?YPI*?I^`3xk~h4O`DkJZ(KAcyH?gZ|m{2 znee7CL?Cabr_BTpQSE6nVVpQaB$|k)&4h5Na?!_%5vsv!fO#J)s4M$FRzT-XW*1;` z0q_vj9-$geuG8EhZmUPAhHst2&M%Jl{NKcd*W8}&FqfVI7@-UynMGAv$72%+GR{TwTByv);M9~y@QyL<@FQrMk zM98g^5?qn)OZZSP3o@H{!8n<0VPqFzasde11(;j_f_4EW7l68IbCuZzm|OsYb^#_A zfS_G~$ps*27hrM$2-*dhTmXXi873Eipk08;1t4e_V7Hk66)qqM+6CG;-JAgq1nmOH zoQuvKLOEAiJ) zjc0ZNCKrG~!UTcY1(;j_NEOHI0!%IdABzh`W*1;`0eDJ!R(e_LB*{{ego0WLR!KXg zAEX?~k-}trJ&@rgxxI|z8JX^!U&&i#I4IMV_K_S&%qeXZcvBgoysxAwy0SSir-v)b zedRH=x+usW2-79Xg-X;W#o2<79!Qv+C zZ9=fP$$Fa*EN-&iCIpL{thWil;wI~DLa?~WdYk_`4GO{HChKiNu(-*3n-DB+vfd^H zi<_*s3Blqf>uo}?xXF5(5G-!8sO^7u0Gy{lu(-*3n-DB+vfd^Hi<_*s3Blqf>uo}? zxXF5(5G-!8-X;W#o2<79!Qv+CZ35{dL+z2^&;K^Dfbzeg_DEn7;h;Sd2H6wrPuo~l6_Rd{;E#3T;51m=WW7x|$g$X=H->;W`62xKd>XIwthWhQ`1|~0 zLUp`tvEC+(6J`is2pa@XAOPWFWzoAr(hU+m7uSd+_w)n;P*-9G0Z$+R!Qv+CZNh6Z zGYEJB0XQwQ*#fVy-X;W#o9yiZJcEEI5CEDju;M1`ZNgI;n=N<(0a&H&(0FEq}COKaA6;33zE!;9ChKj&Yef@EZ!7?()obeCYQPbzy`sIL z!60pd#->25w+X@GChKj&$NEBjoxVr6bk^I1r;KL}R@`L0O;}~@Fn%zoxXF5(@RHfy z>}~eX@LGL9>hI82A9S*0E40-IIhJFEw)$X1k+sun^#RrTLR)>1=I9RV|FHTGgvvUp z{sW=1POASvEGKcHtv)!)*<5I=5Bl(4|A*CofNFiD-t$_0FiF6OMo6m<%89%fs@{Xe zA`O3o>OE*EiBhO~5B5lw6sq2XPB?lGRqsL0Km8w8|A7&TijzU+UZwgEJo@KO&gwsb zwnnIW52|Z|7OLKZ4VtNWtv;&%K&&q5{T3&hDLTsoK@f$;NN9+1_fTkzga%iQ0K^ti zXpDpgK@=Jzp+RZOL!mJe8Z5BZTDz@mE7!Vhm9Q(?nB-|;ceGiOXRf`{26_cKZx>+5 zk!2hq7;>bH;{gZGIQX9IM7T9whP{QsE(sBqxSL#ty@h*jS*{w_h-;0{BlJ1~)44_5 zdTuZG6UVT(P>HY4GfE!A-ok2rC;ubQaGOsGbp&W85CwFkkRmYbEgTZg3BL=4LV2;4 z_@Wpu!dv1{@dI(TxKzv#zZdbPLZpq|n~>8SKoMk%SvTxF#K+ZB3~D^NgT;E^#&AZxu0B*Fw3=Fs_NvxHgTdNFZI-q~+oWY_^b`yCw6c0Ny^-EpPtf1h$Lc`v z+4VZvoslA|molJ|QQv53bT;}K$;L;z13~U*8A}Y}q@OS@8*tAc z&TAvHwMkluvHzzyuMo<4rB{ALn^xfn;@73I_sGSt2b=L-J zFkYLfeW`8K7*PJM2BmdM7`M{9=!rT$b?dM|C$Mz3o~z&1OBfXm46e5@IvRbAQAVmU z*H~%5cH@X~-Y7uY94Z&grY5vAdzr({$>yi#a&wD$z=SjAb@QPaVb!!^EYjA%U~8f^ z%OXxJdEdO@`PsG#~Ccc2@hT$?8Yyd=*x!JJlc63+hdkf;@FJXr>Vnmoh(;eAuSJA?=*@yH==`*K6r7 z>hTC{)`#jJ=(F{udWQbJeoBX{`UCxOqlWRk5odHa1{yHlm}z`zY&7;6$Bkc&y9Sgt ztC$VURwf&OPcvbGN&1y+GuOOrmar;fa@HcRMqg``m1@nkR$8##I%1u-3M{ar>}Twz zj7&G&o@{?=FSobY2W&WFU$-CH5l&4f#(CB0;lN;LqC+{dO-`0`!ny3gJ*TW&%?%)E z-FMxwE=+e9x$9ko9lH5$0Ag5)tIxIMI&=Lv<~V@WoZoQ(jA|Hk9Ka#o?>GR@hV3~H zz_Vd{jsqAk`W*-VQTzrS2NIKELp_-!=zV2Rh7H@1%za)ikUbeTv{NYGGFkCt*l6{CDIF^5^>wmgdopZTtuq_8 zC&Pwj1|)^Ur%T0pSV26ijVOefm!+0$%TV6U}z+u3%mecLYK zRCJ)8LvjI(?mMXt(Fb9>bHq9C6gc2UxzD&wU1;a_a)-N<-A~=+E=8o_j7tit2(Bhd zQ3$~bgE?fYa+Cwi;!bdvIk?A_<*V_89%S)*n9eWa*YkUMvQPcVmlB|ofa)lrv)~0y zfRZM`ph+DOf-hq1K@5T~V)P&uF9E%XeIU)2mP#4Y_tGf|u1XJzUc};L65hi z`B(Wa#lvmJto;a<2@7JL(q87g!fp8^NjaQ zcn?A2J!=_3(0I>UMi4aKvz8GAjrXi&1VQ6HBVL17Gh!{HcpF$5Xtur7&al6?PuXzQ z_K4SUPIqUZ1LK{U4!X#keGWlt?>c~Ha<_ro%I)GNy2#3PA;9N#v)x?uj+Njla!`+J z!J&5y0~M*Ij9#TXExG*mGL7y;3#yF+m_stQ9p!{6Nj)NuK_ zJ22R!?#>c(lbL0nFfW^M&n#~gtpw{`Ypey+twq*)Yp?Z_m2aW2%Z5sJeY>Si zUYcZ^tX#0#WVDwP zc9*)$Qx8|&2QKp-F;9Krd*K)ap**9@?2FsCa|AR<;@As#;n}jJcfi_ML|QQn6Wu6w zjw{dC;<2n1&%ebpHPTW(gNN_=Q~XsvkO>o>7ve(uT^j|;$pE9_2fC?Z7co(U_rz)9 z0&%UlTg(=7#oHp3kSa>#KIka*l}1Ua5|EIAXbB!H0X$m5aCx%)sk~fkKGz1b)*1!)EFQ&tjdL2Co z5}%`kA0%GO06$1P!vH@>JkA6^Nc^}7evo*g1q2cgy*&e6pF?lYK-cHc+cWqpg3FzU zTb!(G0pdV{86XZo-nC*b0}epOXrzuif9E2c{zm@22hKBYqdWMH8z3|1UFUfo78FNH zw=3Vw%Zt0!*PZTy{~M3VSN}JD_5Uf45fpihioWsnWbl9Ex69!F#?J=d<>@&kaCRu;hDdXQ;?UB zO;Hx}rT2do%lTv=$jcAM&L2H&owW(Q1OC}tngjmXTXh!%*H6>})AbXzz(0FC%7K6O z)`tiG?Ck~*{@L3k0sOPKaw7O=Z;M6n&)ynJ;Gezik-$HD>m-AJ_Ld`q$KLVKJK&$a zJyO8S!?4*~APgEhd#kR2fA+RP1OMzTRtHJ%uaDM)_*$?7tti6RGV~56?WPzETg}ir zDJ+AB_*xUuJG-a-J#E_I`KyZ?IM&#qjESHRGHC6bTYT=^lL6Gkf6xp4Uy+OfmW&A^^?;aqp-4TL z#A#e8QV+`ECKQU)gT=hTha&Z$p&$yONIlpiSlF=pL+}_}&`FfVP^2E@h%EEsF}Pra zq)MSkJ$NK>awt*{(qvr@Md|@D^+J()SP3?h3~;Fet>@HF#;F+nT%cse$>+b%~U^ZBXT zsuYZDwnaTw*u)ju&)Ox;d#eG42j+kl2oUsf*G0e@ERr~|g+hin36<$^oH4Hx`7!Xys-J3=`geZ`?W!eSo$ zJ3>Q*K=^iqJp%Z5gia`I^X&*ZBKUWN5fb=!ghvwicZ4(<{5wK*CD+>#hV{cEvWu>$ ziez{hHAJDP%%JHQ=wFtaojm|I=}CzhBgT%sHFi(x1*OC|YL$m$mM%D0Jfle${)(}O_Y|tsq!| zW>G8fGxGauK#cs*s1-0qelThUl(hby5t^#8NHis)Av6+Al4KwcxUO&3ztd0Z zl!%7VNHis)Av6+AiD(FoL{lOfLLqaDG?2! zZ44@7KvlP)E4r+WL1m14fi}iN#1%oy;w@Vqbt$KFkZ;Jn0OOE1HzUe4&DtEuTy^0? zZeG!BDu)AyWAzL#A`Mi%0_%dY)FAC|*Pwyo|ILk%oT?J?aGY6Lql)hRQP1UPKy1jb)_0h%{Il z%Sd|>X^?f6k@h0e;ANz}h%|T^X)huTUPjuBNQ0M=_9D{YWu(1`Gx|)kaUd9= zX8CCd2B=wn8iE08mY;@TfSTo}p&>8wUHNzTF+9spLoh(i^3xCuP_z6rA^H1 z7@%hPX$S_WS$-OV0cw_?hG2l2<)@L=>IJA-ei~vGNnrtMmY;^Bimk8!HOo&!A5~FV zfSTo};fCs}EI`fj(=Z83Ei6FI^3zaG=XDmKX8CDYtOo>H`X!y^r;C69)FNg1X`uQ) z3sAHCG;}g$lLe?(nLErMOvo`ElTjyMvf5j{t%oDfV2w8s><76|1#X?#-#jzPT6c(W ztk^AU5GZ<|zj*%q7-yZ8hv=sFBVzNh0)5ir?4!;LHng?hw8@E;X6yE5`#T#>+Ww$5 z3~>BGYq;b1gVr$B^#`q?0_P7}!wSwHw1y_UKWGj6d4JFv-VppjYq%u%gVr!c^ariM z|MmY+0{_?l37L?nzMwVuzy2>M;Q#u6hag?w*T0(z9stD)T0^KIhl1AN|N0l#febmp zum5K{_`m*78{q%?e`7qPuRjn1xb(}|yUfDgzW=vh z2y$8VuF3od%dl1X2)d@TTBSQ0Sgq21pQgPyS8_|BS+)wk_#|y=vZUAMuIX6eOq=5( z`9Clz{0mROUFXn)0O|JLFn8$_Oqx~#>G8aAB~2?KbX-Z(N_g5V8dsWRWn5;$H|Bmb zv@s0ibsS^`?-W3n3eqZiq;Po0_S?4L58H3sf)5?PZ3~`o{kARm%Jti};04Za+k)>n zzikV;@qXJDT;%<>E$~i_-k}kSi+{>y&7W^z< zlBq}M9U9>sWsDNqqk}(`l4@v=?%{`O`b2uin?2i|4XiNf1`3n7d)rR|s=WHlIe-5C z`E>P%QP}?l@efhVn>a9?2pm_^)6@4)ypV(?%4Ubvs?!Iixe6}?a*98NlZBLoa^{YD4~ z6}?a*9707eln94V(F++Nz&~DkS^zH+?j^z@RP;iLaPW_peip$$UV2A@;CP9>Nf2hJd)!&x}HXR5K2Vkq_?@L2lou&i9;Q+AdKyWw!0}Ov( z8txeWzBEiV{e5YuVEOyffB+qw4g`k-(8TulrD4AvifVYp0X7{74hP_p<3}~X7}t+# zfRdaa)d0a^0GkCsZQdIOuvq|X<-K75n*~5y!5ap!Spb|AykP*F1;7B&8wRjh0NfG1 zVE~&20MR|xNV}w?5}O48X)i9A03~&A7{F!$Fi-b}0c;ikwGD3=z-9rk)$oP^Y!(1*O>Y>$W&v>0^o9X!77$Qt zg!ZKYNgsA-UmB*`-Y|g80-%E9?@Pl9yzhthrJ;%I?@Pme*WZ_hH#mP^8ZL4EzBG9E zeeb#tB?W(98s-W9zVyG5XTVm`-4cMS0E``&dQN}B$@G|V&Eec!w8 z1K~yKzK_>^E8Y6ag00p;>#X&g^$4%=(f0qn#{Xx%#)E%||B4CzA^y)MgoE@ zUm8M1x73%0P|+>*r6E*wOMU78*q5|HH$7jHzb{?nOJbs1>Ptff)8ChdP|+>3>= zG_wQID;le9`fk&vtqB=j&uOJUJBw3sAQ{c>-C?^QX&1FSns+|S)dQovle#?@VN8Yl z=a4>z#;rNJ*R_7rD5F=^Z+cy8Kme{AnB`&kM_j#f~tR1t$Hn{T-!+07ldO3r%lvtk@^O2N#O4rT$RAzHyAJ9BLdgjo|vhHVxx-{ zTO%Lrg23`Jap4%iywS9N*tNz7goZ4ND8bhPnD;N)pR8N0^&z}+3Vi2HqGVqpUsD<~FQ7J=oZ2bR* z;xS^XIe@yVYcUuD9d%zFr%g(|*0@ZWGCQzXs%=Q6Nl>LqNtI{kwl1y8lLALdC^MJBE6H)T>vn!~7}80fvt;U|3rmcBbTHD2A-8yLF6p3mXkUDJD*dj0k8;!9SE0oVN)#_qqU%Q1W1RcRaSeXe z@{RSzUgIZ&d@OO1DymX24aAr0pfX|Dq$$Y}*BYZRY=VJycf&B@mhri^$Na*iW6unI zv;j9vHXSFm!0a(SL-jci7n#?FED^$&)Hc-AkB!jWv6Ws2Z(IK zDX|3wjjuJ%&RlzGTI99HDaBJ#<~i$}9S-vV6(Pd@a0yvLnOdAI$=rTRJVe>)2(^hfD!YSC10<3@fXASd%i!nDjb(U5oSw^SrP^mN8wn)&ZJiT`>LhYjU4u-$t1K~ z>u2;*sR)F10cv;VYv+{+y`~qE^eFqbLZEB6pTlqJNOOgZDFBb{m#PRP`yi=z! zCb1T;=#j?XDiB}u{!D6jURGZ;l2xGgV7qmJhUkRZ*eEHAoqug~Ks8K;dDQ?a;m4cQ z2K)Zo`O0bqb}H{GW0l8;Ew@<17f@edEiqYRDA~eIyzGdkZaeq3wGTT4v0DnMB`;iX zFW|#a6i%1z)+89364AYT_3pPaFn>ISBL^ou##iSBz76k9*5M0&18?%jcyF@4kL59X z$_Jf=#Xk8Y?314L<0az7Gh93bdGYA3Ty(YMd}+0hHb5Tn8^Tr zq{y^dD=;;T>fUd({TivcIk#<($ufK@&sJGmc#(QlE!*~C#iS@DVC{l%OcEZ|Ur^hs zqBcZ>Zc0GHK9kC(t&~|>QPE+RL?rDp31L4-8f}hU5C<=3Sk+hv<_IiJhob*1@b~Jy=ZLL;MHSC*Ed!Z6#|TX;BtD zV_io1%2++usbc?$HR6C_t4mQ4je2N6U-#!7Rz#y7+CHy{_9=Jnnt`~!Tlq*GKkIx^ zua1e1mdTu1t4qVFH+(<5ko5Ow0Z4~#tyxqkU z4k6RK7Vp}1QuY$z-zCCRReT=_Fj$AJu)=fC>CXY~3Xk}1^(Op{{M!R`KHEEb@7`$p zRxb9OVuf5?=-;T7eL^@F9bm2FyXVANWu`O$=*xODLZhj~{YyY8bZG~iU2*-`Ez4-F0ahv0IL^Ylr-x&W=noG*7v!l0t zw{6>i4uyC$8QG?8T|Hp)8X;NjUMc>{D~&r;ly-}S7WJK=om@(-q!vh@%2D$A*H4Kl zSH;URGaTHOTPw9k*RI`P8Z^9T&z`llK=$Z!B~w`^1=R0Dfe`HTrC$|Rp)CC}_F&$V zrnPUSo=|p5rL_wZbXOl>wK-8^B!Zb!p-}x^tCbcf-qQw(<;6xiY!?!A)^qNxex!HS z;Hs9dKaMTtO2*EHm(6=7EZ0XFC>%7t#(!{1KVv|I{?H(-1p!4`nS)K3Ej6=~&5mXj zlbX}3P4E}srd!}Iz*Vxh*SD`aF=z2Fy#4W`qmLeKY!CYhj~DHahofI~$UhS&_$Pki zFhU=Ah(2%PbkB9l2#@`V1Zt>Ryk^bxClBve`~8EG1kD#7kR@ZqcHg z@YypRI&?@MI}VTe?T@1i+Zeq0H z%`Rb>JV5wH93Z*^wI*VvTsFjPFMZw-8QCot^1CF!Kfp=KMG+^Qj#OFhEiq1wBEggn z1wu=iwKz|7%MgIrC3EHaa(S_@@}js_hPg_jyj>~48g+s4)39C&V1;_XsR0=h`cf(n zpfyrKZ)_8tAAcdQnf* zpO>jfy;0e%LoH>NNd@_l`n%F(dAbBa@B!lB8SGmQEu&KD5xrQ;GQ#n%s?+V%V{vYGcc%?M+81oEe@XRA z2=*^W+9~#&oR3j%vn+#REXy_@7=7TtifMJyaR*qIp`zT1&M4QM+|Di{s{XvKPyZV^ zKo-SlVwX?5W!t<>Wvkb)g@T4d`SM~!#m1QaI4Kc-@--2X z#BYRv6}uIRG@gs+VQzqibC=uxcUkdW31u9AihcR+68Ro$Nt?t1EcMErrIzw-VZD?r z|MYsI3}4Gp+-^5Ve%DjKdI!|q!YT1BL@Y4E0t68YjIe-K9}lsx z-dt(k(;-VeZ!*LJBP>7=vA_rm5JW5xVPT6?c;FIQaq$}D03x{OO+(@}N9W+h_AZm2 zL%`3E{niRA15gZCaa<*EmBdvFS2(WHxUh}|WpO=*>v3G=a7EzaaFxdui7N`%6S$tl zRRLE;TuHD!8iRs)nmNt{S*7iVih#MdPZ4>uFri;Hr(Q4z9Ym>fw48SAAU1 z;c9@ZA+AQa1YFPKYK$ue*9*8_#MJ~>Q(Q0MYKE&ht`@jn#?=y6EUs3#L|mlIwD;%bX49@lHQ+Tm)Cs{^jradpJi30G%a60R<|y5dT})eTp7TyNm&f$L3NZ{g~R zs~4``xZcLq2UlNQGOm8O`r}H(^$xCgaSgyV5Z54FgK-VPH5At{T*GmVz%>$=f@>76 zBwWe3M&o)9*BD%5agD<@9@hk16LGzd>jPYqaXrG0n~MLQLd$y(J8b@9-q?Ba?~^AZ zmlG^~>32()cC~w-m>3qh?3Z71emRm)u6$J@J&?PK$elFzRY;;+KrU;XxbsefPfenPM{ z@8C>n93EXGm*Y2Ug9F96W7iqMQ0%_PNW1M~(qL(3iU1;R8d|uLd(FwbTvWX2h7()fgg|C_iCJsT9e^&$!r$0D<)<`1~$Eiq>e5= zdh`bK;+6pGXUD|02hoD|$o%BpiD4E#;)ET+sSjR6`Qm`HBod5AT7~L9vI=39@Pke( zH(Hml5-Z=Ao1L}}E5dLT98IvEIuVY?+t`7}%~$Q2%6qTpHnNDjvEaD_n^8T0D#yIM zg|>BK*)n$-Io0s`mv`|E`-;$TX#Hcz!Ebi$+~hsUnK*u;_+Pc!7y8b?J8>W93ulAV zY#28}(tg6aRBdP2)o?swhdIK#O>F`eq!78FdjMFl-1^?_QoKu-sWo~ygB|>$ab+Eb zFL*53ozC42h#`Rr@#n+$+U5EDoFyFY$5oss`Bo0yQy=HD_mgM@$fFr8)3TAzbAM(sZa>jHuzSRzEp26X1)VTb2ah+y?*zipB zlw~F!NguVSQ^ht%(lh&GVf5sjakxulCgOegxs60O!wg7fZg zKm@|hmIt`o;s7yq3Y;L|4rn-n=2(tUI4zED3(%|{F&ZLqdPd=xhJW6s9gG2xmU2K) zt8?7%T=E7YjrHPTIA69Ly3+XM4YT>B`~mcg3dG#0CA=scz>DNG7jC{DXLq-=h41YP zP6KhT2tSF8hvMN-z~iBKIF$2Sl#L_s$RCz)=FE;W*QBSrkl-+3O7SUEqW{5%eoiXx zUGh;G#l>i4Bq<{_S6)~8;K+ikj4PCHQ9q-9r{pCT<|Q}Zs6DCHQK6aIL48{tsWJ`R zHWg4ar~a-Mstjy4w)tQ9?Fmc3I3cLyZA3Fi^ZbV~kr$3q_^?V9w+hgdIxuj>=CB03iLjJ=ft!M# zq_70s<{oaS)iga|>grIvLl|DC6V?bH>l4I6y8&q{@GJPRLVlHWrY&=a;#iZkWqdt) z2%+D9<2eOU(OAk1OBg?Xd_-g|3_YLJu1qIPQL_$@qN2mP;y#$3+BCgc=jhInVO?=E z%9&rvxLIl4+Qqd_hLNv0P(W!i2cHQV&Vi^)y`BvK9_F30IvSnL?fuLec1<4lvU#a* zn>a$pQecIQ!7mRUJTDdZ$&!87E`-baT-EE31oDSZg6U=5Ux@cs~{Yp2?yH zVF?>IH@#8HtYr2;0?bYWr*%lt`~f|A2bUN`ZUlyI48WpR#M_$;U|_#{Mlt(Id#Lk) z1B3vYv!<+5&1vKiJq}H2HT388re;5Pnu&K4wCPoicizHjUkSIOoAP;6w^=)P&Yi+r zSlS3nxO}WyRCH7{e(=i)-@1ogsJokP!gC%G`Kgv$o(B~3T9dg?IfTAcy{kacZffT zURNKyvcA{Vhpo~<>8$jdL|y<2(osc>*3)2vbfZ)&Dp*S6d#Ww3j~~tde^Sr#L-h z&hHqIoQW#4sUx>FxFFq1KW)V{pak@M8 zcEODvW18lv)cr&!*L~$45z_VdXg6+ZHVqiOW{iFA<>#K;S`0tAVZ5yt-k3-)IrygY z<+GC?Ou;YejIsHVy}#?-dtoBsAPbUSd(C}~l!8#MTvEB7F&iTjr{KA(p?XssKY40_ z`t^tJqW5gvOE0~&Y&ISoMkH68+<(RxbgGR>y&k!IDj+2ClVWMhr!Gpm95!RZfu!8M zVd$dMp3#=4S(cS@w8j#BlTJX-)cXmMbzZJhXUHN-ddJ*Wp~NR~+D#?FsAe=WS{sXu z^XrZJ^YBVDV`AO9)$6Xw$FbP`)U|m%^Z?tcrkQAz)@b(|Yryn%C`c`WQ*PG|pn*@j zK6Qy1Bo_kV2MH`lckb&m5*gZt@$ts0)73>PGGJ?|0V?6QH1)aep{(ZEU)wvkZj9{N zxLK>r7Wgk@4mHo3-y9g5j;4suxb!22$u@4wCL&)#xaBdLnsB9BA*aS0VW7Acog6y zWwe+clN}kcITE+Ep7OuSj0N7ZTNHLuX&!|W$H;_gg;Kxw@g^C~Npht8aI`$77fuOL zWEOUOio8zVBflvRk^hh%^%#e<^}OZyE;n`2zFsclPYxUq*Y(gL{t%AA>;cLPD2|F) z*AE}?Hb+$%GEH6}-($y&OSC6)fUm%p6a(jjgVbgdCie=9Ny3TR1Pm2o_R#pJa!3&O zYL%xoO~OCa!|E_CU4gF@+MQ`ry{7%GmDAygPv@jx?wYT))OV^#P14~beSUzG^`m}H z>!|isk)ju2FveXYH3g5&K#;pxD)Dc2>cqH%7fl)u4mA%M$>vfsLV=pfO7pyY;UC5w zbhqvrrOlZZVJy#>1?Krf*7Z#M+H8&@ciA=TDVu^zo$S+Apo2;xkz|BbzOkItG* z_x`V^1u8f+v_Qa_sKAEANhv zSalW`x=5+L?>>6#gmVKG_R~x{Gl7}Os3`DZf>i?W79P&NLD$$?K ze(68Bo#JT5y`6p{HWr5}6BVE(*%x>m{De2$-{fc&XgStd?W?+QJosF7=y(Lj8!N@WkZv~zzN%}(KASd)45I4%WkpcOg_VQm;X zbSOP|Y!rf_TnoE#1O$MM8#h8S?tr&iy%b@ zy? z!KBV`SMNT(+dLJ@=)6%h>7l@k0PM`A5%Le!fJx^%qBQnSBYNP z@Q%D#{#z8|6m}2<}4D_<}#pQU6v=`rH`&qt4xflb|()xI2Cs@aYC) z@TePi4iQh-qW;bb=A+?7+sj9j=K@w+!F)9M%hHsOK3tb=5R2EQ+IcHhWUgp{MaiDA zc$=RadsnYN69^|RU5L(&!scf#YqFHZtH*`iB}Cg0S;t+H<#(6d{`Wq7*lX6QCI8Ta zHhRryp$}0gL#xNX$Y*d8I%{AxPn}9fT0D=0Kc?`oHbb=$rQ78T=Lh37uiKc;a@Ik%+3}@=i;iSQU($r zdXAF<8FnbMg^gmRax1sqvam!70|*8Af6YrGDA{v)j;z|ViAbp&eEJ^mxDBf!spB>dxlwtv`Q(Paqy{6|`G zfuH|KD=zT!AICB?7+A=xWwtXk3%ShP!Zu`~1>1>zf*r`d#!h8FWLL59CF`sVs&P2} z!$}=HesfdsKDV6P#O>kWFn5jvK9;|SZ^P523Wo9%`FHuHJld^!%CW$8K3cd-ND?{= zeQ|U*9tR-8V&QY4Q21UrDUd`J8i}pMN5tOZOX6q|P1PcNCTAqNF$^-B}zeTmM|Q0R63905PH7S>lOUZS9-kyJzwi6VG}Q20){B?x-v^yqU0%G zDF>8als^>sTlkrjqCTY#R>!I{R9L94Rky1p>T&h5dW+UjgBDsR?Fnt5M)|l8wN)B? zsqNQFwF_D`y}o{*-d=~t_2>2BdbW;|XMK~tM~B0BR{KrC`KE(~@#&R<_ zSjesAh~Vi0JfQ_oBiDhv3-AP&;OPQ9!6kUQ08elUo-V)>T!N9#$NJrwj0eZG*4!{$h!$qR&zaaeu{H9i^ zbu`C+LHY}LU7MvX(H#E;=`Y}KdSl)7Uy%L+7V2wnzUMFNq`!a`20iQ@{{=nV!SBBy zfG7C<7hwsw-+w{+3m9rmwBEHG{{`tU!0*2x{RQ~_7o@)czyE^t7vT3_kp2Sv{tMDy zfZu;X`U~*;FGzm@e*XpOFTn4=ApHf9p4;_bP;3nR{tJqYf!}{Y`U~*;FDM5Ie*XpK zAi?jyApHdll_$!s|AO=v;P+pU{sIT6p8taM7vT3_kp2Sv{tMp_#qnQ|{sR2|3({YJ z-+w{VLHJFt(p~=rO$Wj6zaaeu`2828zkr42T64QuVjedyo20*h7FH+A^0! z4!fAe)jN(GPqL)HfJR&^?h&px_Yy~ok_8-i$tovU1rPJRcqdskk0<>Fe8V5*UH=8? zFW@<0n2;sR5k3(%;Kcio0KW-ULLD(dd{Cqz`4ACa7iWn}M8|(Y`V07*G*~0{i($OsK6LW+4 zwRs3*%x0BY$4amsv}i0b#DdqYS=JIO&-%(bVEtnKVZq;Qijq)(V6aX43s`8cwb9sW zlmCMB7vT3_kp2R^8^3em2fzPJM+>CCfX{?& z!ncCszaaeu`2828zkqMVqvCnd@n6vR0sQ_8ni7NGe?fsZ@cS=Fe*u2~1?exq@4uiS z68QZWq`v^a|AO=v;P+op3=b?y&IoW_h!*b>lf=$qU-1=jya?}zi*KgNoY4R{ zvjG|njFw1$0e=4lg}A`)zo79R`2828zW~4gg2EZ#_g_#r1N{CA(qDkze?j34@cS<) zoB@9S1%)%f@4q1Z1^E3Jq`v^a|KcBJe-r%v3({YJ-+w{+i@%Zo;>4eICm@cpF6P04Wl!TA2Nz(qC0 z>rU{7p%_c{Ew%pFfDzt6|E~e#e+?MYENO{Ei>w3E{~9p##6JN68iDvHAV4D!{{#eR1md570F6NW6A+*g zh<^g|A20CT2?)>##6JPSB=;YRe*ywD0`X5kfJPwx2?)>##6JN68iDvHAV4D!{{#eR z1md570F6NW6A*C18{Py2uA0s&+ns;_jX?Yp5TFr=zcv8W8}Qc#fO-S|2?)>##6JN6 zzr%zkAmDeH&;$f%1md57z%9JzFrf(u_#GxR0Rg|mgeD;1cbMFa^!FG26A=s-_SiuJWw}srr}ZIq0+e3j59q-JWMw~GS`?MB_60f+0pVS@vzd`V(qg$N<6f) zAG7`52=F7iS~J}k=*PUu_`MNunz_dKy%8{ueVg@rBcLXCXSf03dLv*yx0>^NBcK`I zf%khOz@J5-C<=5Jo)z3I3Pn-C&7!#8i0$bjtyhT>uRqhaE!&pV4O_)iVxH?Pp z?}FgrPQ9hh>xAlZNL{d6cTrsqsS7$7L3uOysg4A7glEm5ycx(K;}^)l1S=?ShFk5R zycs^SgYss$p9#vFVG9$KH^XCWP~Hqbvq51yueD`C3sc}%A0}0$bNwgOpray`zaasPq!*Tc{6;Z1m(?e zze@6EPap$ZR2S9d5E09|2+!IXwrtO~T_Pj=YTvLKCZ2JL zjNs%bycos5-5X8g?v*l{A_3vMaJpi{26h8rs3wEcxB?Eo%b z-K#D>Og$f5w^z+gAT|VsZmw345}+#vWZ`J!(W6bmKl=&XOitwvuNNXa(vFxCHOxW;sX5d+PopHdx>J)HpZc-01jkrYxXCN0$e88{Zg4s z!0_u2Df3f^@cP9U>K7FJX{WrZKomkHG9||(5t31iv|F*27}YgN{I@+ovit|gv0o5Y zra@&HW<<*@2+m|?+7O({#4%a^nal^bjJh~#RAu>^niS}eDT(vytFO*ashTM8RONxL z*SdCHQ;TZbJtBMbD9fJr=dSE8H^uG0u#W%oO<})s9ORqyhT6^LoAie2DOFv$;}rA+ z_8MXfnun4^2oG)xK~Ha{iFBsmRo8!rF8Dfgjzypo~D8e1Tvo=|AbpEoMjLu*@8+KaXf$PNWvFVjzSP05TN zke!SXhT);Ua}w)k*3X6;)T{eAKtg zD^-@^20vZ?^9SG(^MR209u#lA0zoKV7ZqISic8D~Lgsr=yg?cSp?H@x2tx6u=n#bB z)iWRn#am`T5Q^8@JjZ{JAcYf2SPX@ZW)PhZr_CTbAI4c89q)t{*z6l-3{i;u|M zoEF7n*cn4ZXNQ!>U%@g-MgrC?z(!m?&?#{Ri-?&CjT$uqnPC`8D4n(7RXYe*hikSA zSFg0_t9(d#>R=_?u1VPK_EhAPVE!qnak!o$bE%Q+JQS!eVZX)vH%mMA%`@ z!k|HbV!{Y2V?z`krZMu{%vN@Sd_#gOB4y)#;7{?ntjNU)=T_W->DTHBM3v$%nq(ezbObWX6ik>eFK}63p z;&!eV_qZ^EBctinU)aII>yP2t3it5$gh3PqDZOK6C8T1UIxQtTv@IiJWJX5ygn2Po zf{IVtg^k~u3BA&`r4<*4ijT0ngaN%quy3;S;&7>!B~bO_57Awn!Bf&;$*+zFa>x7C z@$i~FRragnp_)=(@vGy3N|b(eJlvzUQT^(8Aa}f99S@zgzM5Yh59E&btK)%sC~xT} zd)7}q7vDQ^o(^t>!rhUASE0x=zA_FNKuc10NBTnK($uQ1<_Y{TeSs0jPzVrOv!;Lb z_*2+)t4JAm1f!NVM)>aoEHN>}K1wqkQaA)Jl@qKix>PzytBqno`G?0o{IGh$(bmy7 zu!1tHdIFwA4XWD5U*IqWh+*%8AFCbkyjjzb7IR8gXkI=x@8}f<3ABC-gw4`B)f5h!cOz3h7zv3}X zBPu8hS;^LAL(Dp+i23dwDm9d*Fc{Qmb~G_P24m^b#jUXJlO9{Y-yZxYc41;MlfA!l zN@}-mp>C}imd|{CkBxig8%aF;#3j{kUfDx%*S+BGd);*}xcgpr-3wod2SnQU{=fa3 zEp`89zx|bXLKUk2f%CQohyl_HH1~mXrw+jf&PFSG>oyE_)=sI>eO@R#{_r;acXVg2 zOOKs7Gc>b8|4**NYxMJXn#DRJ#FbEW?-ZU}aptQ(jT<-adVcJXAL!HCqD8wFajg~~ z#LoDDs`Qv}RRH7F{Ys*TRp3>wNvCiReVPHup#Eg#5j>ju%bn65>ka6+U zVs!klP*q6`$&gT)1F6V0=o1z)y#32m`$N0!0t-_m4e(g+er9bP3`-o=u77c%ef-X) z6)B;{&0qw33)|Rwm`kzVLKFB~7R=*wK!GV0} zs@)TLpm=Fa5A8qbns2ABc@6C~y}9-Z_x<WO~^A7j4q*CnBw2Z*JMInu2R-VDTM$3rOLhJiq7b6gBbOB!CN{cP~_-5vt zsHzimYOZ9v*}KiB%{S}`<`L5}uT~h6z330>(GcWfksVbHAs6^3Il2f57u6Y_Ibj$! z6dxLGyw5B!N^SbvJI7$J-O-P`_HhW8iP@d3YafTZxFnABoS{AQc`C-e7T3xLk^3T;2rv+)RlF!BuhmneigyaKE>AFsEz8mz``DY&dcx^GJj8 zA&AyO(8a!`P^b@QC<58r_(mITJf~$%G@h|GRJ6abGwozqtBP-ref#Z9Yg%cKTzpI% zUS>poi(mehmv`?j*gYkp>A^M?(f0Q{zWmbs65E8IG`WCYE0qLo?M(Li2dUz?PgeE!5!NTaF&HI|Jq-nV))_gI^c3^9JQ;DYvq zMGO!6Hq&b8F8~;D0WgCZXEg-DbZiS2g6Y^VSqP?MALqc~Xt?Rv!yKFoq+^Hj5KPBj z=OLJmeMczu(y=FC`nBoPn-x-1FyGG4ry&Py)UkAcG>T@0<0Hq9KP_-#viPJ(XkwTy zekA%;M9@IGU-GMnuCG^jEu^b!_`JjKAzs+c8h}%e?q^!Ju57(by7me+kYah{d*Q9S zQo2`$cJgDg-&O>><)3A;6*)xukCyDhJ6z49%?j#gE?H8xBwZQ#W}Av;1z1_iO3iC1 zexmd(9;`LGn4J?jIWjUaJH-k|g(lFQY_9T<3V7?<->eYlA^B$A-`lsZY~N0u@IHQQ z!pxpEmTuv{Y4xD`fxf@XIRp??s&{_!=@H!BR|?eHU4w10@^ zlqR#*uAHNMt8Gwz((?8VE=JDWGV&lp*|D;+*(F1Y2N&a&aeL9u=*)!T#<>lD7+kz^ z<&l-Od*f>%t%Nv{HwfjPrn<>_wOvg%l)#vImJhh zPC7a>yUhTCv_D1gAo1=}?oDtqfo3iF;U+-P2c2>GtjqD9Y zeMa`_GwNjFG8}5GH^2(hnCtCns&+Pes93jeW4x<+tFfyl1XpADsSU2i?r_lx9#IQ| ztFg8W1Xp8UGZ0*jJ;MSvJptFb)o02OBN|3Z%*>HDKI>!J?ViE1)L<`HdIt$J+Rjyei?T zCmZKR*DJspa;hkcv&E0azX+GMlW@sV^R3=~=bdqPrtim7vvu}mec?tq3{gl*DjICx zL?OT_yz>-E_DfGZ@x=M9iuP4r?zuGj#7_J6+i!2eWS?unV;>0*^Llgo%L|{{u{jN| za`EQJU*9qLjynpZ31debi8a3;GmS^YC_apf<@=Skr`3m)m4#Rlo-R)qI}IDgYvhqx z19R7B61O2!*%H24R49>Z)@kWhwYJQuHFZf%%$qWD%9J&Eedpo<-E(skKI>2Cjb79> zx9{u?xuxTCN2^b*i_IOf8&A#BA5>w}#9Zvht;1mptjw#iW?p_@?F)IQJXRTT5Kbyz zYJbQJrNzeQMxjw>UDeSv>?YIv@_KFk(J!bMOX$6f8727kn<#hIm&&heFiZPIcH+%W zx*5E9vy*Oy3r01wzDeSvu17AP(`s+oSq}Low52N+MWGPue z(?H+)lU8MP?Q;rI3Du?5FW?b>wf4YPIjaVR!4HxD_{U0VjDAUqlKaWLc%D*XX|kvS z4r-9uix*+M&l!-Non1VlecDey#r?EqJRY5W@(!gQN^P`Yc6lbgO%JB*pWQyEYV9~2 zN&}va(V>Aj`#YEtn_4(``PShJX7|l4NuDtqZ=@}kX0^##E4NsEA#-%*AEWx_9*R74 zC{wvtCO|dfiVah2)lT4C-d7-qhx4l<9UO-GKiBI%T@uNH=_n^9d!BmV(>NhJk^<4p z!%Q#c1!e?80Ip9Nz-u#elsV5tu(z>I*|uy}5B52B7@Nh;VLxFDyGL}0h*;AYzuaXh z{byJ8T0|rPJc4X0Cjx#vESgj78!>$N@TwCj)GMd8#u_%LJ%yE=Yp{ys^Vz-Z)g$cF z@9#_v(-cRhrj8mB-5Nm;McFoy9tiXhg`|g^5zo&aCcV<(a!l2MWPD}Qti&RCK~eTA zue@?NLlhU{Rjnv{$dG~|r*Yto@H(j|yM24JJ>cQ>M$)`_W%EWQjURP+{!XPW+^#$P zhBrnm*Kw4HZ_~3$;fW?5^zD+O6RXB2(!3ej4Q&UdM1+7<>hO`05Oav}*Y;r)`3Q-Y)tL#4G{u1FMd z*n)f6jdHW>8aHq4FhqL&&&X8v%srH~7%w^joyOBKg!3d|ZuYU>{7Vm%@R&QFzb&)T z#LT!%{BSJmJu$KUq(f1gmIezO$`VC zI?Tv2<`|zCu)+A+IAr{0R3WD`!FrCqNiMX4Xlzj>t zvT-BgGI0!TKqlJH|JQMJf3M z4-_}Vu}xNG@BZB<#&?bHl$cVxJhjEe7A*!fot28u8W@AU$TylI#x*Ww7jA0eMl?)q zoIG)2+{8DU;$yj8|K|L|{BWdyKievP>Lf%b9ceBT%L~5;xm?wb`)Ff`D2b{;P4P}n zC<*AtJ2tqQ!elPQ)#chY5T1Ty$RwP^r)D>n;7!4Q;fWC2-X``R)pruUYs#ck~ z=67>Hb7z}laIC{0-1fh9z!X~D-c1IIcf9!0OXf>}RET=R)~;385-;+N*g;JiM>cL8 zlk|M%1@5poLVSyZ1>9#GApq**cPv)EM}{^s1xvhY4U+SyTjN!0fKV;tk>2fAYw-3! z-5Rf21EW>y)_Bz#s1XK~I9F||);HV{vTt%hSH0aB9qE8IY4QGbQ|e6sbVmC1@0eJ%`|YK*hgU&_jEly&S)tJCuG zQ28QXPrI27p5MUH8=Q9lqLr8F4Ri{}FO{f3#Wxp2xQ1pC^_k90j}RmzwhGPaIFSE4 zH;?(m+F)J9le>0}WO`xKw(1B&_~X0l%u4K(dJ1R6@ocx-aAOB$1N+B!4Oc6vnejT) zC@&^9gyXu7?5}KEk0_kj3}RR=k&EQoaiuSFJsFW%#Az+?83pZn?`$$&@c8!7o_F~6 zJ(71e>m+`{hv#YZ*{I?l=X$X(u%*P$4bRhh(sS=pME`Ij;IKfqs93D|^B4Gkh+Y;A z+&Z4y#sjyG=eF^{t>d|EJaFrHZWavz*) zvd7-Ew?-;nw;0l1t~ah3wN2K9MDtP8@5+Dz^E=aVWjHQmAX$dz%Fq!CVL7FLr}O{p zRhh;!ty{P5X9Jc0cLYM}I9SKITDo!E+gv;ckMcn+ z9el?JwRG^J5Y*DaMIorAgUMo0O9yqOpq38lAVDo15U%=ZIbC+MF0e!XL8h>an{|OF zm7ta`i%b}f!IZKtVAItFzw%($ty>pp1!L1xjjH7~Z8T}i9)(NJRP_UOrAm1iaNKpC zq7?jr7|O$JvbDH#O%n0kZkE^E#?b-+o@zwas4;0ydZ%g#Q&$3$ti0(^AUdNuw_EaF;}W{vt?p3qnMZ3mFyPwe@@G! z)NPrp8I3=08*slyD{hCsfvJG#adYr{yGH(1ruGT=>nAjy2Y>y9=JRdC^^?W)SSp`5 z*CvO;(@#GQGCoD<6Fo?Upe?P520>fedhKQ^=7#2)(}$BSZOoEArU zQk$p`som9Q)eKcuXRGkB z>dY2@Rd1+d+JOhOF51&tx;8;`Ogpec`$0RURcg2DaXP0b>+qyLNFSq5*FVzN=(=94 z!!iAm9%VEz?l(Fbf{|vxNMnlefw9uqV(c?aBmDo{dSNWlW99%;GAEhvp1I82XzmW5 z61Ev*0i6=vtbW$3)*F^$Bs6Y|SpP;XC_; zeZ{WH+{v^Ie@);;{M}Du<}<6At&G8xF>sNo&fd;8V>_@tS&_|TVKO_HUBS}BFANys zpf1;hdx-1KJfq1{zQ53{95k`tr#1BLdO9&2^(8Cgf z!zJ7;{Vbi8Y$-;DyXDq$H=InoD!(C91RB=KMe>ib7lDRHm7t{~nulJ6x_T4+A>E5W!^ir1eV6V!=8d0U38<*uuctHiowl3yU}Oxq5)1a0Nm`e8-0e0deBk~ zWVH8NilMFB{mST9)4qA%gm>skf!$>A*DTYWkXeoyG*r25t z?&jRK}#{bCoU5=in~SEQVe%XK}#{LlY*9FcvKEris3ssXeovlm7t{hewahxqPJfSaGq z!^eEkQVb6WK}#|05Q3IsaH0TS5&%fH=C>5XNGWJ3hDbSRDTeptprsh@R)UsdAd8jX zQVfr(o~8KXch{>xD|`1^O}A?BU#sa>4gPC2-KxQVt)^Qw_^;J;s|NqII?}9X0?|I* zYc<`f!GEo$TQ&Hv)pV-{|FxQK)!@HY)2$l(*J`>|ga2Ahw`%ZTtLat^{%bYes=W;h)BLn=*eH3|YPwZ} zcdcIX#!_{=3?=e$`LcYA(okukbW)yBV4(7vGFACdS*3ib>{m(^xS&*1>#O&v?ZcSY z;VNXS@2d_E&%xnAtagvqMk5}cgTn)lhv(q%z~kXL13JtJeXslVJkZ++>Up5t2KxsgU7>j%HZJf@SHL@csx9(3=SR-&%xor9QhM@gY44W>nPyy@SHL@csx9( z3=SR-&nbhWBF^REIc0G0cz8}39HUh(56>xsgU7>j%HZJf@SHL@csx9(3=SR-&%xn= z$HQ}Qc!2o+n>;)xC=2D5%foZZ;NVH*oH96g5;>;~4rKjscz8}391>WUhvy_-z~kXL zi5E!WTppfN1_zIa=ius{1 z9hL&|?f*vvMlh$0wF{Pbcn%H^BDmYQrX2C`92_3Z;XdIuaKyuNaCnfwKgf6GiHGOl z@E{M%RtI?E;W;=wND-bA{2Em#5snL`L80=!;@{apZ}lbBzq3OI_V22HX9pe+&&f_eIDFyD zPQV;Jn4JI=6BxdoodHhQ!^=(pX)XNO3GjG$PIdwYTEXlDIAQ`XI{}V{^k#Mfad_bI z@EjZ-csx7@hX)=H&%xn=$HQ}Qc;NBy92_2$bH8(b(I}8<)ZyVdI6R0DZWEdc#KUv? z5#aIgoPGp&JUpi#0Ui&}=|@0{6zuc>2>|?^9#r22J3Zj>@EjZ-WGlf=55%g$P7i7r z-F}3F!#kg(QK#pHk15boR$=aIfCdh4$-^x{P%pns$9!p6TlFVy3A!2m3{Nj# zWI#|a-^YZYUjBp$SInB0JGiE~H4vuQkI9DH?I0!_f_nKT4EP7vG`EIb%t7W?#>)#p zP%r-jd;Sz#$==G>g%!gC66FxnB^Oo>5b~}#axHYma7t3%= zz9fGjH&E_ZIx2#arj(9UrYIjME0uL`Viwy1Y-;YFg#lD196wN;7uH|X-}&lZ^@wVz zA|iw!PTO8JkzQC; z84=Xg#>OrKm{-og#TV_pz>ilWx*GWLYD8B92Vw2t)rhVJe!Lpd)xeKeBf1*+@oGd@ z13zAk=xX4{s}Wrd{CG8@s{sw+t4j`Et*2y(;K!>GUF~{EzV$V10>kv__H>|))RZYV zrtF?d5yT&V4E4-IRV<>JD3;6nch%{~bopFnC!Vr@pN&QZ=ln*wrgzYL>Y|>h6I~xx=vYG0 zkLZ>jGU^&l40y%wA=*~XNX0S3ln|0PpcPv)Ju3QXre;@9ww%7f-A&_K9fD7KDSX@WCXftA8z!al(iFs&G#s|;@^ zJ|+$jrRVT3zuD+0tm|ilX&^KS2f~23qi~vpgMSoGlW_2l!f6r?AIK|ZcN9*OaJW|? zKfOl*fuI4bwF=!-^4xnA5cp9&t@u~&d==jX=ip$+_fxF^zH(aIeitE}}*jlnEs2x*+ft9P3#@*jHEXMdO^u5@(Z@l@~ zPZW%@sZ>k_=u?=l>28ks2}2x>mgVh9#*fq}bH(Acxlx$sn)xSa0&cgOS$@#O^%Yj` zA&ksGUS3?@zH(d@=US(%Tr+yb=NKADH=VH!P^Fpr&I4@Sq?B6eY5ZFnWwXqrqZrN( zw@aIaccLTV6t0!`mB$uSNG6kU)}x8c7W)QcUpiacek^&r0SW;|7Ffy&tr# zA1dKXN+?~Fo3u7@_*(s&4za~EQnBs5n=f_#5L1sX&BeAs^zL%Z-^K}1ooA(XO_nLp zL?{RWrU~-}Kdl6A7n_N+gc3y(B#mR>Z6;qF!)EZ77?SErWh@S&x=Vgq3945QN`6`i z_!Ary-~fMug902dMwzboX(iw#IGn1(b~l}2E?k~_|NYnQhsybssa_VjY}pajJB?tJ z7Ceo%SJ$1>sQczwF#`vh1E~v8Ij=?yyGA$!V&cfByDoo@yY$Sw=;W%2`Ux@|!Y$Ws zxutR*)iHNm+p%NOHsl$=ebs*X&2MddZsj$h|6Fin1N+07u2q;)&|T+7v)vX zo*OxL?jroh*n-9D+wbdZ0HI?2q}c0Mjffv8!T8E6>MNvfs$5VxyQz(r3_8NgM`FCp z)PKPaX7#02mGf_+AgWS(wQUZqgIjK15F_ zLsMRkdEP)W!$mz*gK{%h5Ghf)fTHD5m=7P-E5g3bZfd_{p_KFUUwd4_&eX3FjE^(k z->zoWxBhOV7~5ZG=IC|Ugt%eV52g0#VfG+%U*)`rh`5M@<@kGxXRk47Y?i`0JLmg< zI~lh#cM3mc3Vzw9mnGF`Hhe@`*W{DzJ$GXfrg~FKxW#kMO7d(%6z28^wJJ~C5VJFX zNOIc|WrLgL znW6kn>n97&SS{>M_7nDIzVol7X)L8&^&z~<5AKQAKm20bLX7AI4&V(@5pzT@Z~#u? zzzZCJlQ{4K2jCW0ivM@= zm(|vAXSJ0x4-pELbHYkSJRXbkY%CW;wQAMi3MQ6v7UMYwV~|afR*p&UoW;A4iI7%a zGJ9w4%9Zv?)bBOK0`id-qt0M3C9OOq#ZIB_9KvPT-GKe1oRp=Bm&+E`FYa|3gOO?F zeopWY3Y?!;BDP=se-*#`9(|7%nB{!Drj-}Yu(4qEF%GP2h`Npn( zv6K$)(q&PXv~nyomnHPoPgsC}i?nh?NL(M6ml7WaNc0c&$A3r3qfZk=eASV)I)r_A zTf#2yHNAz-R$CekjXsO%uC($Qx!BNJ2J{t@DOQWAsqWcVFO;pdZZqkCzDIX>3$qIg zw-grki$&l<#}pE~U$W>E_3}?-G&|RO4G|}HVv%9tqLNyPg9Z&sjh$Cq7Fkx7YQAia zGJiJCqM!vbgtv`U%N-XR7Q|T2MVIc#W$H!sdZw-aLXGbR4Q@2(SwfhXqM~+1?MkAP zkx_8sLSX?=moRLtwQjK++P~Y|J5?W_JGjZf_;bn4lizwP?yW%-A?_HxxoluFXj)OS zFC6)=-8K37_~r3ekT5YNk8l(+p7$_q+O$DU&o3z0Tvk!LPt%hg@#EXshGq-1lX=Hul=AMq66$lGu`{fN z)>`X6u0DUJ2(ckj=L zKQ}BFU4hGn;Q_qAG8;45#p=4Z-hV&zes!MFn(>ZPsI_);|FM$$=$pY*?q1VqYHsBu z>`vrs%;#s~r{Qn6y7{VJGp};eipUi!up$0#<)mIFWu>#WuXCRBpMQKNXB+)&uuoB$ zjU`A}so!nv)18%95qC_3l?G$TTCTRynIy^ zAH}N-seR#ed5`#|<`*V4uzH&>nWZJ#yH<@U^<##`;Jxec+>;y1u+&&DcH_p(jdRcK zFRLGeG@soyrr~wx<|F-=WjoMk8QVB!c}D$;{CqYau(Gs%;QoT9^%Z$Y_6=j88siN1 zvzTG*!{&$>n6(n!(Er7C?w+Uc5N*xc|G-*P^xP7>q~8#nfD)vM!GO|sSDZ?l6d1i_ z^ys-Ic<1anthhsQ@!S&po%Z}=M)58@<0~TO7SFh`YnQr<7!5a=x!)FDD=O+akPeL& z$6B4cx6L^DWqF+Zw!BE*uE_7b$zJ1ar`K6u{G39dXl`ov)uQM zInpOmf>CWnWTYBN2X`}!K7QWe^Uu%b;oXBq2w8-RT&eFcnyIIZvxVgs%gehI4y-`< z6WH_=z;78u;jbmwnL2D6Dxq25@ja7t)@zW^dadeJwTAhg+~m4KJ!z zwAb3&RT(=ic+P6CKWvk`XQ%zXe#VCDb~JMrlY|NXzRWAkcn02K9Lm@C%t_`dQ;UU0 zERj}vvoEou*|*pQEPTdpW4~p~+27e3+#OtV4j$%uaW8NqxHmZmfRXhLca%HNMew)r z2*Bu2(4nBF{_rVgxFo`%ff zR|hZKX1^;z-jub{T{2BF2a2!AQ_9UnRI9Nm;E#R6op|HKkSAS|$3YX?THN*?Ytw+B?G3nN&+5;phVSg^vmq zYzR10?b2)g<-cJ~6}9fGL_&j%)%s80KRa8i`r>D5>k_((rW+@;C&iF2YluZcV-@seSvq@mgTRP6!*aA1m^6U zl}B%$j)z6jwuwKKoA+4I$rx(%Hpt}krn*P{$$+Ca(joc`Q@^(k8Glz&6nJXdEQOX= zjm$i(Z7(;&n5Ey%Gsb@@$@u(Dl5rf}kYwU-VHIm8Tcy<@Wg!vmD)b*&rhHub;tx!$;vsND<3@{6ERwXneXRc%TwDOwNN&N6t1V8jqK#}^0llclMQf`Ovf|eu3;O8}zf+xy)M0Cmr zhcuMmk)M~oG0%uuDvU?^76D>fDL=h>Mt)GqDiMF*H?U=AKo`-`67fvO)1>H zJGA>o|EUE-(iZ2gQb}pj=(fpI3$PD{vEt9C7FC)v zUrSH#xtR{PXGT8rOnUuUG59H5lr0nN0Y8v4>(5#`4j)D7>=ia=Jn=AYu=n0KF^6tg zO*t6O1vm5OfX81+zXZH&%?h>0ThF+pB))TpnH>-Um4u&|ehGOo(+Hi#k9_b@TEF<8 zJN*1}`cCYMg!qpil*34hyYA}8w;jpjxVSA*FSt87XvryRjG^=C!ZE(4pbF8;Qt~6eEaQsNtZ{_L~aZo zy+@WJ2dnz>tXc~CH>X_A%${^~S&y7U*A5+OIfvMz1Xw$=bi8%5_dIOHwys(`8=nEtxpQX=P^~>Z z772t5^(Rxaky`a{IQBMFR*lcZ3qFbN@h>PMgzw5OGbT)^n9wgFd(wtVI&5Xq(BtQK z{e>}z5b2kIh`aT6)xFgSIf3Mbwuy6^GLJ_hcOf}@;FJJ@;>hyW);;(+n^FTh+raj%^>pLU`qZJML(AM*(~7Hk9Y?UbUHh zoz~oKiKy44ISgZ7yZMlYQM~HUQ?A9i0lhT2S9CnS z% z;nKFD`1cOam*Je~@N`jo3XuZ25%cDS=JgX_72iO}R!#A4X*##Co3v~mj%hNc4wK|Y zGe`7F!?{7`kZsdbCT$;)zI+m%)KYf(^0}*5XRa=m-jjL`#Gh$Mj^@VVq_`(C0S4i= z1O~_-$!laK9EIDxygmbUl<~sj+$=HdIeTaUqWYERYd2NClnKv(t}7WXE58dpRJVut zi3-6U;)5E}yZk-Gukc2!krvRi0s@uB+!zFc``gq!c(&5$z6C=%#G-qd_g$@WAJm5(;LS? zHBXMg&r5CuLMRqlaBFG9#M39*i2o2{?R)GtcGf@a{`OFNqW!MD)c)d{*}*hxUcl*L zF23;&SJ?JdoLbbpFltoUs3waqq%{oHtiVHaVd{*U75MtTQ8nkp>pNb5{bn`gZ;BF9 z96$1VT#-WI_M;y#gl4RHAuX+4+HS@^k8{7%CmZrN?Qfl!Czyc@IT71_Va3MRtRVgc zd+`ORHK}IB;20;pLH0X%g*~AB&TQsf{ujK$4X(YJ`H(xx++x?NOtIi8Yw(Ff{CyoR zXI>D$d0<-sG)$Y3>0~&b33EEOmorO*Rb3jVh6?TiEAg}w5Q3uUHA#g zNQsS)jVILY%C5u8&UG16@ZbX^92bDKgS;BRiz#0Z*eUUQp@+vi<^ z244BWrkfu%ZcpJ&rebMCGEEuQ7smE$r9Yzg)*ToqEYO1@z0&4}BhqV}i#KxI5boNQ zW=#9)(@!fu#oOQ4_yT~2TN*Yj>y3Avt%Xf&9M#ih=bdBkywjw7PWjnirC6L|+hF8Mm2X7Dco2niWwmjSV_3Up|2|wKATWr5k*rRwu+8+D!7snUea?6cdMx_wnHau4S z^Ff4QiWrl2*lkw~-Bxg@AT>2LBc-u9{O@MUk)vhj3J_J1RuVOK?AWt~!}^t2$F2Tn z@kTNxtptz#%-H=^1vuTyFH9@$-8XT{`t^$h2Sz&*Cr8hCJ@8dwbZ=T`AEtQf$v7LaLQbRWV^R1``ncX8*aOJ5}!e}YKNIpHA~PNc`b!~iXF_N&`ww=)E6Nb zb;_0?7V%KNVAQF{++BFCrIqwb?JEN&y;CO^)X(jm3TN0)bwoAk z&Yk8i18&}F_I66n&pi}B*l7E{k(WGrHjbL+8XLE};EO4np(K7{?uLEk@zE8B;uFf6 zt*>evL);2HhqkXboGpBA?~>H!%`=;aZ4TRzWl=A046-cp^RP!WTwOI~S_eZO^SXDjQ8V|Y8l?9D?D(U3gG;RMOx6Wdx4nD7=MD3obezdQ>kB$3ydHF}FO8 z_tIIrQxFT%Y{RhlL#f4)#l@#J(s~?Y=xYJkWUNN?0yn4!Zc@(;>Q!}ZMwkVBJwjRU zPQq(ke{LwZiu>~Z1vl_Le%{{PEJ1&8<3#(5AIbFhV~U06|LHJ%>U47+zW8~8{h7VZ z{??}GR}cJS75>X5r%Oi>mo+~RSKT?|qwp3NXHm!PUoG})FKCmSpF0M>>a`c+Fg!nR z8qOqYtH>^2Tt9gakHmVsXQrzkEF6Omn&}CMs+g-b+MyOL$5rwa)%vh2x6|)kpLm>rc+cFBU`3|L*!2 zOox1=N3YzB^W$9gXSGbXHjP21Ma)uMY@gMKQ(}ZSy6?o*f9nXSwfksJiR`LWpVIN3 zblzC5UNxGUcfB_wer*VvBah~Q@q+0{SCL0krGJAwnupEC*59oW=2Q6M#9ztb)MxHv+B1(c z&ojfBZ03C?dU199V$4n0P<;V@X7TL&_9jW}5i5xui&!4^ut{oX=g+O02`9tgrM4VB zAck=dv(StEe-I2kd_lbaB)-~WO8MHq;IV$-?lBZty1KrROv-&lr&A6FTrYQ z>&<0~vr9SeEK|})m3iJ53&b>SRtG#DOMmRnCLUNkt%g>&4dHk{om zjlr))c%}I1$WK3QpkBER7cS}9QTW>Fs7mT2^*wc&3LDkk_*ZaN{c{~c8HiW4H#9}d z(bj3}P54netzFY<>#UxrKdSf9;bncC{aRVBge>cxraBZOZnmN_{(1caym*#%6)VyHQvid#?+FOrX z&s)Q-Z0mh%xwXkUzsEXkowKeYZS-4^3B;J6pC5A}3h&XE!ud17PQy~QF~$DCCW1zH z?I8oV7m-Xo=3b^9^B6OL`Pt5-O8qisBeR?NnK_I9&BU;9H`|)+#`a@hW#3>GHiw0E zY!U09ul@f>8)o^_hEI2XL4V-|!1rl-$~zt2c_+Oq&9#L01PFHM?-n80pI_GyNKPV1GxwZj8N$46C zbhTJLrn-{Qj#^tmi&yoRFut)&+4v5O*FM(@HIGaWt@KZ&u877WGCd)#V4MD}9^Nw< zcNlaR1?PZqkD_mIXlwYb&d-@Z-zmrH+GKT)_P}bwS{KVq*;5r-q=R@Wd z?)-S}9d0rA`Tc|0>$|KRQKybw zCoEpb%?;(o2~P{@!USO^&a85U;ZBq6QV$$S-4Ni45R}KBUoBF+u^<6&S|HP`0-vAz z62cD!yjz1jYSbtiQWT5eW*=R%?DiE>zO+}O?Bk_@ixhbOJ2 z>V-v^Enon%5fwL6N8vSrKXn972-3?yf)j%DGLS$a$V-ZwfxIR`ZJ9!lUIr3oqMNp! z>180{pZQeagdn{PBv7pIk`-k)uGC;vP>JiXCnD3&Sz9HqGVXGl}r{PPxNpJFONxYT;; zy=pu4F?9fbkHGmLdEX<5(eBn-Yu&Vdn)5vZ`XCi)-uDQc50dvi0_THtMXzbxX|yzW z15%9_jZwxlW4^K4AYeL_85fP}=Iv%PoP_i=MH4d3$tI!F^Ub{`q0J#=)wP;9?@KGg zk}a5ReQXij=b-hgMFwf`E2POF4St0*8KnR9jQqb%#@VlsCWG`}GS1*vNE6!!{0ixR zkKqG;g)}ktA^3F=H1I2=snP&`g)}kL!LN`egEaUR(qxc^9AlkPWO$VZ_)jQcPNm_W zC}4*5PZTiGhD@92UtXmFLQIgw1AYb~RT{vZ^ro{D*qN-#LM|I*@jx;cWbr^T7i95( zGovNe`Y$e>9GgagZo^(Kt%RL4o8&<0u&isj?T1 zqhuVE$!;{xVevqw5@hi}NDZ=hV73}$@j$#5Wbr_*7G&{2vL0md0PVN^EFMTR+@!J- zRE7$JTEkvx7$%uP77wPtf-D}$v4SifNVJ129w@MbEFSb{1X(;##spbBkjVyFJmAKN zT^0|_=7KC9i06YW9?0c=-*{y40KrH7EFLHpf-IiDL|woibs2!~Oqhf-_GOY+8ip7- z$l`$9mp%Eq^heB+Xvl2l;P7;fP3PLCf3J9T{fQUfaqCgQzi^@?5t;k6rv=dNJ2vk5$ zk`|Pc(%6EW1k!>WCp1t2IX3&co|~8_`+fIbW9_}yTJIWTf4ILm#&pave45<3uK(}% zhXgg~;sL*hlmQ5kt_58@;MWK;00FY}po<6m9#RG%KzL0Lxp+boCe}mBTs%PO;E*>awgDxIO;DRn5xXJ}xJdn-@T|7`# z2)cM6OYqf<&N{%|!TWGF#3BgCjd zH6yH3gK9>I(}HS7DA0l~9`JieSq&-HFqJcW?V@5py74*Y6uvk18mxvCs+y0RtcR4< zkV2OEoymGgSq&-pJ*2FL6!NSC7V9BpHKY)4dp)GAh7|lBQbvb>-$Tl3NWt$RWi_PW z_mHw0QWOz;J*2FL6#O1i^0x{+#PP55L-?`$G@kUGDEll3Smh-F5`@vhr@}nJ^J+u5 zRepe|h>$Ka7w}&3ck#05icnR0Txun~EcKP%lRlC(39@?p|4J?URoiP5{x7Q3TKW{K zz_DUY_(QlMup)TqDE1V?*?-6vNvrF#|1eNWlET@4D3L%8Xa8ZMJX;QD{~=0wObKWI zVTrO<31|PIx%z?{&i=!8^;b2V{f8dfps)eoFB+WGu4v)xKaA4T^lq3uVG1VmSK`v&5xhIQtLvrKhEE_8-e^|n=<-^&3XfC`UgtPy!UHDZ9XaAvxI7kd< z|KX%~MGR;EA-E>GBte<_4_?ZYx#I@oMk=3_QdkZv| zUXXf8gC(kOp?DBrK1ezxU6abowL-~L=phf1Q{+!%isWsPf05y&d_|7LbOtpMcU9h2 zV3d-kP!yg5c*m4W3Y002sIls^Y8Uk_b+|e~g<0xSHAnqXJ*1vjZ>yCxsIO6I_zi8S zHcp$aEz)3(ma7$Ne`q&woJrG6=&1M96ZQA?$@+Yqa-)#1<2W<46l-iynhru3l`+Ry zVQez?8OII4I9(u32NTU;nhv6@V44nCJCL8IgXVTHO$XcUV44nkID?!N=M!hH^R=_Z z`Ne^g&J~Aog>76+DY!7oO>;BdW$s3IPY95LGWQWKmV1`#!o7tM-vkb*<}!!-kvqhl z=WcVAd8p4n&Ho)8;1}_*hR@{-`9Js@{6j(=;Yk5H3O$8H;eBDUFrRk50^|$65}%Ct zFi=bqJ-UhDCMXd>swO=lQR_9qO)ycKEn%mJv`ac75!?h(@?&yK`6aoJJWM9I36{uf z-Gnh)1-2`{DyNid3dJs)svT75p$<}0)KAp8>euQP^%oUR zs#nxVt-97wYom45-qv80mZoKD%e0N!9_^TRNrN)&5j|FaR_~&}r4QF9=rBuPs^{oG z>WB36`fa_k0ricijZVfJMu;ym78$U{$TbR$Ka3m3LuMWGNfW3%G7;mxlg;_&Ds!6& z`DT$>YCd4qv>IDjif6$^;1%0!!cqZ4 zFTx?=yl`8nEJA(pX|a>|hB#ClCr%d^iLge@6&Rd6T?PJ}yIv3`#ZS38l62iqcORp#Y^ntx9#qe&H&u$vLUZi}t(P`f8>3Ct7HZ#W zuwDCAJEc)1wwB&h@1R2ueUP4_f1=OTzt*?tzvysMzoJJP)s2Qm8>6f7wgIDzG$Yek zW^6R}7{`oD24H;O#3+N=#eB;gZcZ>^mbugmi#^K#kWNmC8mj);xf^zi3P7G z)~ktyS<+G|NBU9nYGR?j{IuLjena+ZV!`W)^=e|Fqr!S(y_#6aSBjKUKp1%b(}g~U8KSqHCGLH9|Fk_!`+8K^22cVVbMT6NoVfEGw_FtS{e!? zVRP`>kkz92HAJsA17DOW~Nmt=TAIju_)N>S?GwClTLuynaJ!vudy|vc@%1V#{{d1078+$qMvJ&265-2P2 z6}Or57L!0FVT?s$i%IazOx|J=>WWW^qUbLs;T!P>(GvZ|BzR^fZ!rm;naNvB0^3ab zi%IazOx|J=JTsHGm;}$vZ-Moi&af{}Mxx4y6WaPsh}N8_H;4)GxpGB=kre)j$9ClTRW(sXb{rN1)KtS}9&H zuHgORo5C;hiz%vm4kLm!Hg-zKEjui)b_3r|bqq2<4*ss=7YI~h23WsK@20KyqwlQ3 zXQ4%&&>}7L!s=qIw{}@io7r?3VWR=GcWy4p+hV?CvE>gEL--jLu_5)R0Xiir+IN(Ql#!!Hj+}OCaspD5i;A0z&bjvW^3!v!*SKFE`}F@)I%zQmxQe(XG6bq`sQVKtEFyJ4SrPnSZ^ap^aNg*UNJgqKo9Lp z2Hnk;sPugV4;b`j%~n4%mKaCWT?QO6)|hkLefDEUC2O0RZvtJD7g?i>heF?19d&rf zX45csU7lrPZyvyv_S7+ZUY*@TPI)e&=dJAtAA{IAO(Uk|~{O@1ENP4RMaL?>)J)5$^i?!Ef z7>iG>TZOnLY$CULvuB^;S?efiEH{z?6(||>kQ0mKX2ZxLQM4^RlXV&bt(^oYrkpj)fmUXC9`xuO1-~V zP91)$K)vrd$eXC%_Z%ebsDRnmSJnO#*gXzz+LQ2mZH=*Bi`6D*7d2R_%~h^wTa=gd zLirW#h79a$jNan6W%|&Dr%uBb*;7UmEFH8Uv(G zTxo7K_it})eQnIWjJnjyHsu+;SsC~xqpV{T>NsA>DDz~3Uoy%%M!_!`WgVjsDj5x% zl|es_i88%e8C>L;DASvj!FZmDGQC+DR1%md)0>s0QH!8AD=TZzNW}aZCdcmykGD}# z6F?!+f`yw(rMJYyRtUvK>^MF8^yvg~%Cmj@_U$Y$`9=gvmx~8F{3PO^H9nj6wjLwG z1JXkLZfhs~A<_rwmX-O<#dF7fy5jp z8s2Uw!&0TI+|xRSABZco%IbIp3++0oHGQEf-lTU@j_X557S+c=dMEu^ zqvLYCj5(yPYLSC)?2_Ku7~pHnAGZT5XZFYK;1j-V+zzaq z*&nw9D`)n{?ZC>J{c-yQDrY`J>GYM^=P>va&wp48AyagG;Cm!a{E**Jr?7ot;mT}` zjBeoVTD$ShwOD+UUzt5&Ld1j!K@fi8pA!&QuU=CCn&mxaqB{KhURf)%4rNuq+#s&l zIyBVQ3SCyiMd2+ms%=+csyIp*{OBYxYEOH7yL~GETP!eS6hMmjey>wWcuYdscDI%- zuC#11M*8;UH5sG}sDN+STjK9uj~A~=OGH>^G#5L_oy+16V#F7d_N9-{8k5ygov*-M5 zSO+U5!c?W&^ZR5Ie=c|DC?)SwoVt7Wd)+S&MIsqOZZ*^aMBwM*iA|RiF?1b~sp}E? z7qX*7=#MIBi5-VOuy4?~(Lr4!e=D-#;{ErTKU@ShUG#^Gz^04-a1q#a(H|}X+KX_y z=noeW;iu`MKU@ShUG#^Gz^04-a1q#a(H|}Xn=bmp#UwUej4Z~7V&9Z=h_ysG&CcU} zBdTu-UO}%Sebhjx>&%*2f|u0p+bY@9=aenwEMGNyOq3CoooOV@JW7|e^l7OQHKP~xLN8}=4x_#kjncSCzmjXN2edZ zMWD$gEurvv%3|HQ;zao%f0l=v{3M)Zl8q}?*v6F#FkdR=wn<(1B58QNSgE?)ri*l5 z>eL(Qg}y1$?kyiHU$bahs9VI`zKY0`DP5-50SwSXCqpYQI$;C!0;> zYa*1F9uR1>=}k7l8*O@%O?h_Po_|x$`hiHjuej5xS=rZ56xhnS+Sk171iWb=M(luzlNl3{?Ry z+5K9aLqsmsdT$S6rqTNk&CSDmW@^8Z?z0NcAyR+OK71FyL*UlQ5NUF`k3Gj3Z-3%+ z+~=I3O6!^2pAH_@HvBHvTp@2(N~-iye0%%t4i?f|#SSu6Kz zQ32_~zRo*0n=2!@V=l~olSc4teHQK1v|*0D!hX%ZjX$W!-)iDr4RY*7+#2q@O&gOE zewhr%#HYE7{2Sa!{%s)=?`pUlt>sb&LJzl=nC*5DVb{Hh!Zmz{&Jh>3NQv(ibG%pW z(s;aOuiWwOyC>dV&<=Uil{@nDBl250ys$z3S*R`T=yE25DVJ0+beZfEZKSIZXoVco!lP#NH+P^s__B`qq(okROqJ=0i^($HB$ zHWCHjsr%6hb9%oOtH!ZSj?mZQQm#1|nLy#Z-eRr=mxnAy2`?y7q zR~(Vk;f(XYY2PmGh|8#A^S`3hSV~&w9g!Q|4PvdFvIYpEJUtw=i}f z(|F_si#9j?+`A&Q6i9jTt<#!&h3m&Xz{4RY$=+ul$DdphPXJ6&{mX1IcZo;AjSDpF zLV}{?a(%SmRP2P~#j?wF@au~_1{~nye5N&)t0FzlL$XlUrNHB2&fxO6aw60a8;Nbj zZX(5@C=CV6#qUKg4n=7w2#-T$N#9BElXO_RAl;G32h>8whgxs>9XVB=AupB20Cfk@*^m&6 zSN|)$&8>P~W}h$Uv2_kVOiK^eC(c{@L0zTv~jk|EXm2hnQ1~SP9?YH>0^2NLQBn#FBc!5 zRmxHT#8Vz`Y#drne0uCN&)j+@uCR3m*(bZU@7gsX7T;;l+yB~jyxO`x8HBaRjvH5R zT<=U2LQ$!1+>+c#D_SSO>QIAD>l!t(8_^pwIcL=>dllegE@lUZkX)#sdB={39ji^# zWYIraI2x(bKr0 zFSBUv0rdMEYS2pS8vdy)LfXrjzB=I-kCvo8q}EZNR9UnnX>9iB?CjK>X{q=nzAm$@ z%U&Ge5!If5`4o0{KXYVN|1`WaJo3PS9fcKEP+81Uf=l`AJ#{&Ypz z)s9v1UKwHJVgbUc(B)*on7o*n%`t74L>1$$;^_4LB4g;^HC!D5u*a9}(~fH?CK+LH z16RqS{;QrE-Bvd0Pgu~}T58aeoh9CC+4#uxF3FdyGHZezs-ABc+T&Jt)>vze+#SXf z4z1-fou%jAe3O5Z5WK~R1pRh#ECQ*kQ*b^Sr^D;>yBx)z_JOlkW8ES<#eq+p9`+zR z#a@4Z=?ecN)PxXF6XMbp-WG#PSGXhwm##2D3NBrtvK(BxURfm5(lx&?sik(~N80nJ z^5vUvR;t8TBA4%V8JnF)spJ>ILGMv(Q^-L+0$(F%dKH!{Ec{6MMu}6tQ;L-t%9RVs zcfUk^P(GP#@8=LguR@-mBS-R%>`hEe?tzJ#S?U?6fY-tY)&97n`CZLZHl0RVux z`QLG<{h>p(CnLLcS$|!N>N^Qx^~I&Fr%lv~Np*y>+|Og�NvPR-RRR0kC3sbi3xqNkB)Tv4!ZYra8?-+Y7Gl5T21OMMhe z8YGr%ZsXd1h55C<&wR=3V}e!9`a{Rx(GiVQg5^z0`K-5qI?yg!tObiouwaEc%x-Fp zvxnPztYi32hmGbQvl6aDP}S{F2^NeA8LLUX2rLK- zUJ}*|!op;6zPL(cEm#zUy;4(ZEVYwfljuEK0bg00vwKMFX9VHPd-@pxE$=5zlZ;=@H6{dwP?IeP+W7FI&$6+8G#1DLA3m!Cc9rv^u@JQJ^>HC+<2&oZO}7#k zKC6SN+(IsVRtL5CraaB+yl5==y;v+7o96doQ8aeFyM8^;va-5cy*k}!U|+d?`<4s8 z3)H1TRVvU*d|B)(z9&+b3RS7V3BwdGh0E%xkSKgR$OlxeEHwGF18<%CJc}oD= z0Yp~a>*6C7Z>rE$#4RsAi6hW42Q*pp&_f~*i+(}xlwg6K3u!!xXA>>k|;#K0wLnIDML2^BjvHi9LFIxBDsX&|K?R); zGN>R3K?W5}A;_SDBnBB&u*D#Q3W^kDP$5{)@R1C`dWI?r;I$#Zpn{OxZs9?B31{Fju$e@D71sPP3`5=P|4j*JtK^1}wDsWR( zK?W5}DafFLBnNft5R5+zP(V?F3@W%vkU<4a4Kk>}Ye5DT3@yl@f~W@>RIv0Qg9@?{ zWKhA2WrapS=13D%GsvIJMFkOS%OUQt6e}=lhuz^zuE;Hm8P!#&=piIL;IKJ4_$%k zS)S25>nOR?Kh$UHC_tx#>u>rw{g(c)QO^Luh%;U{hG2Gfn(?Kv8aLfWfpOZnZd5R9 zo6XGU&6|>$V7|AW`ac_rtpD>}bDjyI1deH&SIu%(4Xcp_ZLMzB086pbtdbH!JBE|z9B|G!ADZxA zy2J2!ya|VO7;csJOMZtT1-PigP)?UWmzT@m%dl7eUA`>4a#iJVrIqrs0)3VDl#dim z$-)WEPs(8hE+}`DDk`tGP+wGgtM915`b_*f6R4=w)#!scUSl8KumH2K;UC@qp}F+# zW_{-z*7wObp_yc!PA#UuYE1nWQ(!fwev2uv)*QdZ6n2`wndeNu#S~b(liy+rtj3hJ zm>$p*Y+yB}ev2uv8dJZ;6h3#BJKsBgi)kng{j%$~n8J51rJ(&5Q+Sc18q-v62FF$+ zaDY3*{l!(}>+(w*Rm>3KU*ZOFw|G?iw|GzFq!vRPJuq3$|D2fT6&6A6+?2BXp~6hc@}EP`W@lmSlQ>mJ7jRAv zHEnL%n=?jO)(B^<17f#{Sfzu*&@5DYl@&LozaSjryP>re?xBnF1on%$+!Uv>(f4Av z$KYB#4nM)CiST9UcT^yr7OC&Fw$#QDZ#8U}j(fi*l8n|t;d_C)JLsx^LUN?s&C*{& zL`ePh`Wu8Zbe6`-RZ!|4_A8nq@0Thl&nxsRDjTf;j%0CD$YUF5pFSTbB&NV{ewO@i zrH0Z-VV8nX<)nr;NV*h!s2)|Ya*|{?^|YO8MODx~67U`qtem`CK`$6iZuJu%#yyc-Jqw z?6SLli%PiJZ~=wB)W6)R=kY7~ zt^9ue4*zQG+ajS0wQ9X8j26mTZ6tL!&-06lD|L;)HF~{jsS#i7{NjsLVfT}j_-LM> zgw)77nm2cTfls2!C4|A+WBRy3c1bbLAS-r`!~h-i7DHFtC%a;1D^Yk&f@V7+rG9GUtaY;nly8w50on2W z#1Y~|@vhuOrj!>{mWY3fQbKH5|3e%gv09}}ctEX|+Pe2dxw?9HqcrG4Ogv*U(~K(lh&sC-^5Q zL{Kk#N%8mu@*UThgrTZimB!-gF*Oo{UDqeMxbqGvY0u%}?t(hS#iGf3LsKKE@oDvH zdo>XXF{S=H4w_9%UiJ841xJN^4--5^tRXy8dt(IIz+3`tH5Ar#mKdBUCH zcIH^QbWsyd=X$FL;CLEpNmuzY4cO!Lt@Fo0XV&_SPeIiEIxqQXcz8-85|`GiW4){ zPvnI%JSh=BONe~)CSBzhw41cPjv7L%-bc$l`e^M*QOXr1#K^xILOlDZcNL0|Me%D@ zD6iB~nkpR>@>bN5pOiyBky#1@VktES;Xo{<#vmMsrPNqxcNU%+gK!|0_OK8R#8PSu z!hu*yjX^jNOFZl%$_HR%rGO$~Q!qrA(w&7W5J9W zCuS^8!TI&`CzmeWymWC&uUn`;Zac|tZ`;ow!itB*DW%EL9qppS_}9KTWpcqu+dc!> zd9gTU&Ybi)Kd3L-O-ibrX=)ETy|Delg^N>gS>DQ#9a!vi!j)&mg~Ct6-yAX zh*uk3$CC2e(UU+jdfG5GLHD4l}rMQ67g+(=GIc)8rm zFW(;n3a@e%&=tx(&h2%7cQ3m%?CY0PI5dcsxQr*G&~*cMjt)T%*t1y*E-q~=W# z1qj`$aS!pWx%G%#bI17{j>X1l@dx#V*PbEWaz}ZsyHR{!PHHavC=TVXJ%e$Rgwovv zZU}!qeIxFH2O=K0Apb5#a32eK!lRe+`LrUwv|hG2Um;t=q*t@B^ya6;jnXS}2-$A} zq|IG(AJ!e}KBR<9IhB+-5@|F@#Q{`naaQvAT%ejRZ^J`;E`)D*h|h)a4G;0T;B9zX z>eNj%4C}u1&vb9YLkk|Dro(VP7Zw`d8sU6ybW`*T;~(?&UM2Az&9Y(NQ`8h6@EUaw z4lzGBA8c7p#Ev!myZXZ1x_&I?gs%6(SL5cKP+b%zaE{71|Gj=y!K$NpA%pFsw{Oo= zuJ^>J;RUnoxjmT6ARX`BR#yK#tlKd;t%mZYnVwJFUa#nWSn7bRMe&xo)+Gzd_OHU& zB3X5Ai&wbuwtI%!h_L)uf08bLAKCvp*tcBYzSrg5b`^`a_9_)@*lRblpSRmvgeoQP zTj(SWJ~!9i^Y5lqO7p{6$h2=d8||J>A7t@*xwUY&>~?VKBh^2g-=>rnm&KjK_{ZK( zn+qr;wAy``Tj%_P`^|aJ9l~iYWVtU3eTDagAeJc_&yxkro!A4<^Fju-HoE2}1AtMMyVLFO!Z%6sHv@+FxlVTe_pRk|o|DZ`Zs3Q@ukjtLVb4B?nCQNj?82@@p@;g~Q{ z!Vr!L6JNB6FyZELczYVz^4OnPqNs13O(0#UpbwuZU+B5#^yDsM;!5=DUtNrQ^ie(3 zU|2PKREu__+qJ7|ytoW+a+m9u4P1^lb-+##H)Pumy4B*?BKzOgIH-EzeV3< zH19k{N|M@4&&rAD9;d46G~*weDj;{!y;FY1MFWK|Kctlz?}wBEMBnFA?=0Sjx_6>_ z$O7}uCVbs>mw0Q40b`9ASvH@tNa|06w4?*p-c_Ym(ryeKUboD zY;dhqi_C2_|9n_}@N5NqetyvUA~ql|~Q@Et+&e>a&+~W@uyC}d6Zk_dv+lt@)^>~NM zIH4!kMP#r$m2r-Dp_Z`3ZDVz{1_|YbVbsi7%Q|UblR1Ay=;dM%`zat73FYyvLvmE>r-x%`6MOCBu47>uWc;9aGvc$im)pL5xiHqCSxu_=oB?v_gD9 zHMKj~q`JZ!`8H=fW>)t(Bdm_tNeH7(+~CeTQ6_CW*B>ZE63WeYzjl`JQ>}&8w^ln2 zUc=yj5_iL%ZDbppxPctxVk<qPIqc>2W`UqxB#v^p4Zxw}}|Ig9}ddJVu=)J)#N4`}?v zTYT{ll?RvIi@e{M*ygvyQl-O($W7dfJeiO*eB|(VOV{0tz%TUTq34j7$Wo?Ez|lkg zy-2)^w^etJn>exF#Cwr=fnA{D2zOT68ubYcpNIb(n$T2x`{Q0BVi0&?@2frMcBrj= zg?+8dmfhnl4QNtSz;igje?~ijBf=t@5vGpM*55yjS6o=GAJ8+j-*ue-ZXHJ-;g3QIEPCLPQ_lVK=Nu!M1^jswak4GXKzb=r5SVjR^*R`1I6M%*yjF zW-a+4u^=yt}Rqov3KkH8v=RwWGranqONm$^3%|tq&{dMOMD^mRm&N zORTlbntqgS#jm>k?+(<9%v1IQKQ}e2JJ8Sp`-WR&P=`$@V>-s(>|D;4i_hg%uEMAiibq{T&*lIGhOZ*h@g#=sD)`o=fuPli3y2#Wm(?! z%P;GF*}D`U_sgY!OU1X<`>4WosiZEI^z|;qcg?0V?#uFn6S2gwcj@TUqes7rp`0)J zAvI;uOg6&(c+WG>*v|k4or`bRt$VBPQP;)~2xK)>s-3{A$Obuj%8#q!@e*@c{!Z?# zB$ZPJ;HalqRPFGy#l@6M(Rkpn+i?1ca&6& z0=80&5v%0c>XrNfx77ze&X1?)^ErGgMre&bL8^nJ$;78)N|m>?nkp~{SB^GL-J&g0 zCu*CHYuPjFRKeF=?UbE&cJ8dQkZLR{l&er-e@>MCkXA=~QtLQv4^w@#>2CZrXXMBe zBWtJNbL#q%ty}ADt(}6m-8}VS{fr7P8)pxx@HYkN0@0% z?e)JC95ded%s91KE+@;lKRCWoZG%ku+XhV5ldN_#`;m3 z9{9gI;9S-qX0_5L^3^^p(09tkBY)i4-Fv34W-GPqwsVZB*fQxkA)r5R2}e^#HDsTKo%RwxNItzDG1RBNft zLBvpe&D<{ks82F0|4iRIC4~zR9ZBv*;pPk4f!XcSBfcmzsa0)0a-!OkFOzI6b7YSG zwUwztV|}AaY188xY7@SkD`Q*sc9Yfhjgf1i@&K4uR<06%F?^6dmu4GtW@f)l=kI>-4 z#S2pC6UoK5641nQHv!q%xA|9ul$3iZ5ALAk*}QrDJerhO+)-Nf!MxpwPsHTM#Slx5AGQD@vvbJT8G7Yg7D<eJXZVT$jA)EqQxe z;NN0uN16s9p~v11LuEGDNefBt`tI9XSaqLx_sy>5x^}(VveSb43R7s^WY>^3blpJ7 z7q*k)M?}fYF8G1EJQ1fDH?Q{El2V*cE8$5W3HddM@eJRyePb)xXYBrb}Ez@5C zoZ%a(6`My%k4X)+w~ZY6j~`L5cjlv%tMN$XE$W?JmVjTART8hp_bS(`7k0LPJ5;(a zX$pDR-Yu`ynn4%p@(R>aR_F|87?V*VJ}n^kOaROhW?O2x9IKGuREcW zUP}u%Y5^&=!i`!GBD1VCD-+-QA++QeeqDzfwP3hC!45ZS-ERf*jav6xfqbJD{GVHa z(pI_a|2&p8AZuWH&eeYDmBq@HX?nlTb=>IH^=}XXUM2h3)dmkn&r0r>j`yp3w|iwR zjM-G?zEQ3)0Vk>Pl{T4pCBZMg2IaemtadOS$CPEuBZ*~1s3N*S`Hsu+;jlca%Y)mK zqk5&|+ZSVA53PtOjDT6`c@;M%Bxdz_74?dB2l7Qpb?fj?@*S&m&B8bJ-3H}5rLz{n zT<5_}7$Fmeq7M^T8|H88j z&vHB~@O*{mYdkCQtitmRo^SE2#GfoCnAb$D{{e1~T}o(*_5;`tuWCOn(*Y{9b? z&o(?i;MtDH#FL9B56=!fJMsL8=O;Y7@a)F32hUzS`|$jX=NCNt@#N#N@cfFW08b&F z19%SN`3=t@Jcscd!E+SPF+9KHIgaN9o|AZNJVkhl@tneQ8qXhi&fqzV=Nz8%crM_% zi09vUF5$V1rv#6K=L(*ycuMj7iRT)g>v(S9`3uiYJh$-N#&ZYHT|D>jl+nR`9i1*J zyrtqt%?uKG53d-zd7%nP_#oS)@6(U#B{~?@40yt5ZM;Sh+WkV*>w@Wy&4(IFXGW|vz9C5D|7WZQo|N;P|Ecb z&hj_;6g^G&TMavze?TPpb35^s=c04sa?%k8s>1U{6N{mFiyUdT*qWa&(%dJ9haY+7 z!hA_0&**pwXz)W-`{I$4B-X`A=ph(^# zO%=|{p{8bKpo0IwZ-{f0Y;KXVPdSd3Z}>y0raqyLm!DRbAgZ!Tf%ijZ?@G!Qd6#ro zjlx+6-T=d^ZegvqLkq9Eg`nAcyADCKcMk&w86k$!_}XB7&JZ+vk1`=>_AWDXeY5v5 z6`%rM&kIr#lZT>HG)jWUy3xG3)Ox_KY5zah%8arusV&`?-2YCkOup)UDnmG`LZ8Y& z-S*)YcX(UaZiQRii!KReLbQt(_xAYZ$^p(vTHFuJK!zyEabbZOh>@O=s)*&3%N*;& zgLP6cFa!5L3jPkvK!MBxGXtcaY4lVQ-_1^kBda6D{U#uHC&Q(MZD!l<{|)-I}8&vUm7* z-6XMdxz3%j;MIsQM+*(i=S++>^v4{tA7h52=D*GGXal@!eQ1S88{n4pu1=hvqYcnN>E?z<8*m>>ODaFc41GE3hGa438s=dRE^v1^{7bzb zV;*gHNade#2|k*}f5!vs+x$vgz%z#=cgvo>0Vv%IzS$-HsfR5Z-P_<#y0nVJbUvrct>agtyyKxgDUl zMfKY4$RP>g?RGRqfKRn~+DeVJ+fljQ@fv#F*%*r`h+MO#cuj5nWxcO1&-MtM0s0hu zf&PsSKj^^#J79lmAi$33RWQJw>;ISEx|T{93nK9eyg3w+gNLnpmSDwMUPKPQv{qZD zRe(d<>sAH3ww+5$B*{*&F(P*ox!QtHZC1s?Qn2u-)5Kv_EGz{JUpbo{R>czGQuz}+ z=i+S59qFIXth);gJ&{$@NMu+27iANMK*XQg9qOR&t&kZGW2ZlOa>3W4Sr2X z1`oasp2^_Bx4|cHI!NdI`d3@zF89ewlcqW4f-v-ZQ z@bG|GQ*11f4W7y1QR>9f5y!=nkPIGt8$6T2gKvXpGI;Q9@XS;Qz73wq;9;;bMwzOR z4W7y1!MDLP89ewlcqW4f-v-ZoP2k($nXd_a8$9zhfp3Fnz9#T(@M~~vU1)%BgJ-@b z@NMwS*95)|p81-Sx4|=IQph~XZ17B(gi5-gG6{SeJX0otZ-ZybB=BwUYcTwRt1#aN&t&kx z`m_D|Y+(J_etkBu{%lsCO)_}!ZSYJ651yF7^AbSl^P0ms0mo$UaF9F8-Q+0F$7Jw8 zYg!r?e9JQ#JY3_;3$<`F+d*J5c=$w^D|{_%5j-yeR2S*{pKS2VO8~wNo_Pu2S;@1( zGcN)7HhAVG0N)1BWbp8Z?AhR%3?ANBJRAIdiKuUbXJHeVqk1-Yh7*HtgJ(D~_%?VZ zg9ny2@xvx?Q1@)`ENlY44W5Nf;2Q1+YMC_UXQM0l#Pn?NY;*oTEiU9v%!~e zRA>!P@U8h*c)!pZ*7LjgBfMW|4KE3Oa1DRI&|26bz(L`xa8sxxMvF`a4}--qVrUu^ zN_LzQ;hN~#;F$~_K9M{dJd?pgb-AJJ$2>A+2*x~O6$r*Wauo1w@Jt2|z73wq;NcJT zhI)S|gfWjq4c^x#Yh(i1rm+nXJfPRq$#6~E8uz z9w*UQE?3CGAKVR0hlS>bd`~`+&wZbt%+Kdn@!R-({tUPw&<6K+6&5X8RKR=W8L(8) zM}kM50S)Kw2vmQ_$TN6HOvQ2dV$mbd;4iVFR9AXR^2jroA}x?S{}{C&0!3%r%iU#< zJcF;~&GOIk3E3mhz~-M)LQawULN1rgdB-HZW-PoRNUgXj@x(AQ)& zh#r9k7fe=z=n-hZ!ZbdC1{G~qgXj@xupn^ve$;{B-TNyC{JZx*+y?G*F737dzI$(Q zce}YqT~>n_!!>*053Di(8m!`K_t_?#mun>&4R&(Bap$;O9IHf(;~`jySir++{yJYl zs4X-To)?HlgJ31%RRPM0K?fKFD-o+o5MGJ+9QUaN;W!%6Xz-%!<7h;q-8>+lk^g)v zWXLZkidW_TZ(U&EV`+>^10PFcR2ukL8l%#{$I=*;20oTXRN810K1CEQoJ0dc(ZWeI zAQUZ}M7v2STJK|&l%6kQz#Qjrz3q=}2=5-J>hZMj?(t7gO&^N^|HZ|)a{csw61D=q zIiHF1!87N7?i33|j)QN`XX1SD&H430;(T!B@cQBc34C)t6X%0(&fibQXBox;8g2-X+3&>&b}oTovszBpcoV1041eudQ+$E+aHQ3%r6hWyPr zoUFze-Iiex$7RhRYu83SpN&a{R}Ix5Ys{t%#%^OkHttu3WapL3%Zo$Ta}|>}sggda zw;AfB-}dv*KM%=P8P{@RnpxI=8Ep_rIKJBa-J}w8&mWOQa`6+Z%3_e!8EF;$%i3V= zwvJkMF3u_05)YqpMJKG$R)X=c{rs_TdWfTO>hm_U55RK!dz&6Smu<2S?6ygW<@9yl zb3Sr3hXz3KlXKXaY3gPbcb>D-;oaQc?mO;Nj%_b?jk^aA-aFVf+bbPe?b@p(}S^{|R$q4}@Ydww@r8=FRW%|j2}c?dE- zrL-=EP%e~(=$Sw3*Uy-okxu-KN>w7bvR)}fZ*6>b8WJfPlbS}Hop~kyYDW6)^o#eX z_2VzxTWt=tepJB7%k|Q;+93UqHsZ@gEi*FG$Bi5JZe~V$#nTllexSdHmO)eoI>g=N zE%Ay#HV2A8N;0SjByVm;Mn+M_q`572==Aw<22Qm!n2S{DsrG&Dd^I1`d`xbM%Hgbq)* zWj4~=>fLmbEL22XABfkdA151!I>tr;N$NvsSEI z(qf05W@p;VY{)j(n>5`i6^mCm@T*hJJ?_wTub(?X>*T^4ZdY@@iyu9AZa5RH zSr#m{E}EA#`daVEP31b-xs=$s{}ohm-@X(3J}SYuT8&e?c17&E?lMyU3$B8-m;;hw zw&z*vNL}FzKKh&+Q-+tOdIIqu@TIU?2zRMK=!YHVQh}}Felgso0^OtmQn*V6ewQvI z-BeY6Ty7=5Eccb+J^3R!+@%6{!>!Qpfn+&I00X7>Qk5~#5_aP>QZz~t{k&MKcY4iN*2|{31>m+e@dxnM5%mn zDr$9p`lByC`snhMIvQ1Qo#{U5c?E#g{XfqLu z8bkR66Q-K1QR)@5pE<%TZ(Uih)2i>b-3FTxlAGPCRwwIhRa~Mym>rc_j9gS+wbHDP z=5Z5BOxC5-)EuGLv7c~(D%}$8C+)~jDM_4TV|Bqo`&&C(r!Tx~@AbfcV4O8>8l4O_ znwaZAkwe{{+fDY#H*kMhPF1x10%nWvp4d@Vm8|m|$8&(Y^d@e5x4R2doZsAk8n+x; zxy^I&H?Y;+k5BSe!i!E{VJyyH;WT%htH9UhoAJ-{5}&}sX#Uf`Q9ql%%0oG!hR{f8 zD|8bE2#Sy{z~=(-ql{r9OBg&Z1}$OmoyfFMo+S)kl!BJ9+yl}X=`X3GTvv|i_0NBv z_~&msY}=0M^XaF_pSCUR8W9_hkEgbU6P858%G6}Cux()lOsphu@5r=^_+b1LeEzj9 zoOE@r{MMUucFvh|M*fE~txsvf!GpIB)=umiQ5}6|Ek%qNVW|2edy2emq%wuWRM5P( zg(;^~QdZle2d$!RlIRB9=s_60sCX({Ij@|$t(@t;qjhoXJlv(0+#8DZA8iY<0V=I+ zVbkLJ$}nZTGUBU#y_5e;PClyiPr{f6RKN#OmhmO`lX_S^gR;%MwgpJ%j4Untp`V{@>u+;nT%ZaQKC`im42N|?g@?4JRtIZ^i5^d@r@l}F=6o!%+SsM~ zY#c@>eQR~Jf3-HQ#4z!hRb_KAY5W^ypg1b@d37jjJAw07j`o>C$^VJ=O}ml<(au8W z1&3m3{q)D&mM(b9La%}X4!UREaIM|{kX&ui-?`fMcuTVYKX5NN8Eb#~soqbiEir;N zV8?jz$LA^_lhYzG@yrhArd7$l8*P`gU?k72PM5_OvB?CBOirhz#Yyi;8&)AegF*Mh zhg)=NnP8zU2Bul?Ldpk90lH8<5N}>Z;YBJ&nrHDPb!)gF43EeA zPJFLn=CEOuvaUF(rdYEkU?B1X$&`*4NIR$Em7+$<>Cjm7e&j2ui{wH@9jM@&-=J&%vxqwR7=LP~myc0^es|Do(agdtL0bWLuT ziV?D(3fm>ODA%IJ^~81`wUp+oeWYzFvQyQSQOW~arczmJH?u^7x3y~WO)N%Ob)MnB?T--XPXGb3i6FkiPKtoG)Esx7THLqaa!^zoYke;J`AmOamAo(Hh) zt9H2O0f^EI_dI~>RCOPBTe+U+0W>$u4fi|%&$ZyfJrAMReYocVNc0fydAMouC+bX( z$1ovOb*omTloy;Ded<&~&V>w2-ksn}>NdtG`-M#W;!CSxcQXf=ikZ;oLPn2*V;>(o zhGwoOPia32?HW)M+~v%WTUmVQAwa~jfni8Vae`pSv@G8MbI&ni)SGRPoT(vyDAJc# zTIXZKv*M@6UsR&Sj?Kk0bYJT%wwE}-cWAuY&Hg}| zB1L6%!DrLv6&v$%@_H;dUtTyUH5JaR%SN|n^ik>IH}IylR}tjvBJ$0x>_*Zwxto;H z$23ov7c%jtlhNz*&+C1DArrrpGWtvwF3GS;m?Ot3!;r3NtelnFJPwnT+3$1`*D6EB z*OaqL68Sx&Kb$CcP_yM%-s}?8dx{F$n(trhKTvE#)uigj!c_rJPn9Xs!Tc zm>H=(rxo*m@~PTx4Hj#Lw*3EK@7=>=xc~p}*Y4)vJQ6}h7)gqvOp-0Kl#!$kiLy-; zb)1UQqHIJ7S|*92qD(?j$4R26lD_XEScZyy~Y+-yu z`@|lj#dqwf;wSt|RBlfrveCFWLtJP3cKa~a*{w$GHhY73Rb zFb-13sgR^DQrD_GR7ovRZ>Wz{@Yb4X9kd>rD~1us?W|wUdJJPgTdJcGFR$9UE3=lQ z@B|1#9;l;n-4Mf)6jV%iq^8v(JnE8EM1Lkr8^!QF;!$zE5lfsUsW+*BC)AP@6z#01 zXnKWL!0?DADd>$KNG}#vPz^p0!18a!-qF++`grZUL{=Z{8Uy!63>a{2fT0auevcA= z`svzFOHy&%U_g8A7QZe@Mfr6*np6kjtLP=ns@L%t9c+v13CJath=YvICgB{_JiRQ@z`AXb4Y)zM;$RgnET~ zg8(g;z(BzObVv9#Bx@)vuzr?#0uTf>1HTR9B+=GWM$+{ycZ?>Ufl^ z9$ESJw71_rroQ+VF`Y;EullB}9)l;=qf#V`&aaLqoNQ)hNoIuB|L=hrtH)u3FrS#(es+)8a2pi5QKD z=Tud_Mr7Q8O{xl5*+sM`uBj=;Aipl!I%c@`4pYdyMnfWfiCIbic_WOSDSEN>C}>%` ziusleVl&x3Y&zSAS?59j=!5E`3U={dekMP^$#faJiQPz#u^y$NgbAh#tlPC6c%e7r zZdl<_A6%s09nXbWQE4zDj>g>?aYQz9GY2hY0&KYq{H0>(6b|&?vk`UdL0jHTwt?+$ zTbK=vFL>P)dsO26F}G|Z`8xcoA-^6>Pxc+4my$zl^|*-`led(_=ak$K2!rS7FRiyjxaz@v8RY3>i) zDzu=u;@!LH-DDs!N)^=|cghzSf=Y(mzB3hze<;I=$e!UpmS7ik|5_qU+#~xr6c@w)<+o4Gsl;G_@ioHSguzJ&EjtAqEBxMt7qdGHBtf%O) z*6?QBLhI!Ac!dn$7QXL|(G)3{_4w^pDv$tqU+#6T3zx&?bLTi1XnV@VSU+K1*+c(_ zV$~B~g%ACVS5y#EjO{;16T-Rvan?%SB9w zyz4u0yr%&kP9%xw>JoOJv;IJ%XWqzJ2Ly; z{s@FT+sRMlV#9?81#yS=M;Nam9CJT945zFHvJlV*ym%_#UvUt}g@)^R=Pr#7!)e^q z>-jr#5yF~PdhAHNmSelD{B>nbL3TvIhRJsdu%3KW8h3u81Ybx?rDEm*^Cq=S{Xm(h zCN|*a%JVwyHTcGF0eWpcPPbzKH_cVx6i?s)p-^(QWD@V)M zusxeX{i5DdpQ`ap=B{ml0d0CWxQ7UsPyFy>Jt<_g^~g96c7yf>y?}*x*@@^fe}T?y zPJ*EP8F*VVG9T_Dq*2`YZcIG}_R@by4d@RweUNbmBSDyctPx}0+EBkRMDFwQH|i3F z&I>rLGWb{2L6`v7$1~+LRIY+fMpkP%fVDX2tq5z~T5C;cS>%$$ugQ>Wa%9?SGA_vSjSnQV8q5{P&>8Fy zj-pD=ugkXREVAY1&iUx0b$;yPZ}6td z^1Yt1>c*;7p5J%#$@0PZa^4~_$=;Ekw`E&Kme0hAmWelMVGACOH}k`?%COL{49d+y zU`Zz3dURpx)}*BMNm;&lq!#2~$XG3rl$e;9EZ?}pad8+nF87v(NH0)qi zpf^tOwhkP=Gc2o1#kSt}S7zY>xl^A*{$&7*o8?suXw06 zw3CO*@;$wCZ&6iT7AEWv4(fiEFAld`^JT;-bxW8(q{mXN6GM)CF|gnPeiN_*&hmxpStL&;-u}CCp~zo;QwEZpxlHPX z{F^iL?q|^TPA658!!Sh2t6TNB1n(X~ot++2ipbgE{52&MrBz4V6x}B=O50=-zWJwu zl+Yy&EeINs=!G^^xdv;*AH*qCx=8R7qOpV7N0w0^d3#Z>Q5%#TC2a>h7wg%Hx{Cn7 z@#<%4-U3xu&7gYjVM0P>!eC##v#_2w9Kujcx;~>f9}XH$(AVgp%mn6hW(gxQJKF$q zKD4`x0!rDMG73nv)|62=0Y`Tk#s7p`#yaAbfd}l?T*Lf6lFlvNoSSXR&OR2@Zqaxj z-$MuQc~$VSv9W;X)?nW%!+f%Q#zAD>%|zcreJTv|hxm-HC@pda-?DP9p9++KriNOaKisdpB23w?rI za_2Rqj4i{x*=>>j5{rzN?b130;(3qmdQ*=^2aV1O%ff7$=pb+0gdE7OQxFq4#V5=j zzHa+t!{tNRk*&7>oC$M%VghpwPS99*Z{B`;K)|k49|XLb;nuIVy_m?jyW3H~`van< z<@Zu?A+am90;fjcjid7w$kaOoTJCt~dEf$d22w3Es zb`5K&^-6zg6a_Y_o!DKhO*N-FQY_`5-~@GzQYk~rIPD|tG+j)?1KNXW!o0zBW8P&5 z(Fg93`{CbzpC6w)W`pf7 zn+tj|B;s6xZ`FzaONiq?;%D$TN5vP8DZ`=kEPgYOW`~9=W3m?*woTtZrYB7lMS0bd zqCRs93+Y0@RGSt2Vj&~-D4v9#iKA`52*mhqh3{{(s*SQB+2+buTq%werU;NMTo*Hi zTOvuR4!1wHK`ow$1qla9TFJ|H_{(1945+!p6Jgn_TmElxrSyY%a8GGP;TUg3drGty z(g2B*LS=}O2g_^iqnrjVAES{AoRx3NeQm>RL~~+NIx8?%nXVA~%E&vc^#y2>RDwy>b(m}k;*T*DLp}Q=qI(KHjh7r%X5w76im<>;nYk<6*$(g zJCqk%JE}W1fa0jB6wISmP@C~FdG(ag(1>nLccr805%gr5r!#2SNbjMK(na)Lx{@Zg zXkcbAp|JY!W8g4zo+)FVF?CtO%0{rDV}N9|xPz700v25UmL04;u>Bung=tn27qQjq zvcd%uM-oS>t#F^7kT!9Hn^VhAm?-xYTDoio&N-_DZ&HzX>I^O$d!3+M|2n zmMO5rDq5@29+d^%443f!oI06X%YklVTJ41k#KzQ*t44c3H^X(IJv;}x8LkWM;jN&X z;RXwxg}%ZtVUhsjY=Yp9_5i^{$QrSQm3E>%Fc{e$ceDox+e5t0U1$#+u*>!m`$M~@ z)Kqf9B;+eRRU$S`nIfsPmL8Ly1ge8io>{Jdb=M{Yp z3Dtv0eGUoLgGhZ23Dtv0eGUm^OQ;Vb+fo?YOu;D1UGH&)f_qpq`Ork>(U%@ZPoiNC z>OHcM<*kA`pPzG1`sR6JXcun*Z9un#f)1mb5qnLT0s zzkq!%vi}16Tx9+o_BmiJvpuubDOz0r=5OmKF zC+y?kPw=M%MIf*b_=&orVU%bS+u6F?&=uz=@femO_e4$fu?O3sv%N1)peNbq*adOE zeU}}M*e}{|+h5rC2qvd&2wusCr1g?rI)v&8z~fh{EjO1t%B&nKkCkD%yii^(Z>r8;XK>@Fn(z+PTpmxOq2}_~#6ZpE@p8s#K3u*m}jQ#F^zQU4)g z%C$WHmx!tD9Eq4J;U028BBsb6{{S0ja~c?|un}*L6SiwMJw*sw^Ids8Mu_J#_>DYN z#|TkEAUYgDZ(*n~LHJx)B8biuAviCT3D1POqBA*D93;XxF-cq`t`&EPl2{<#z++eR zwl}jAHI$wr1oQ2y>|5s3~+gQKUSM(Gi7_5A(%u*IB>lHmk2&!X*^b{eejuFyRgrGV`NKX-h720Oap`FmK zX?ltfw5GaJ(bNcPGNq>o!5-=;MI25mQB*)ug#Im03S4h&Vtrlyw@&$0WV?AcAR=zm%*oUDRwM+Q|M{u%#o2yp7 zz+jthE2Jx5&Z1j|?TM{6-yEeWdWsNC=NIy;`R)7xUQZDMPob&MPUtQS5cCuw(2MdD z!Zkrp5rWoYS20=~Arfr~Nf83FU?~#sij|_CA_Qc&Il=z9eTiL95rXsfGW#=oU8#kn zrwG9~DM?x+t(8b@DoGK7N0PVPOzt3)f}NxY!F+j@yjA{LCfzql5duG@tzuF7E2G?X ze8-e4imu}eCgH$+|IzW06d|XM@3!jnTXTx^fav&UX^S<~@o6MQ2ySXmG*{_P6g@DV zT1c&?wo?ZvJw*sS>85l$+9hY2N5cwwGwq;BL#n3;L2ITfL)^P{E$BuD_Ap18B3$s` z`ox(c1ijgz>;zWdND^ytIM0@`&)B-w7EUebAS=|=g5JQ%xYe6$#&zIyE$B23=5wpK zt=!L?t_3yOfY^ywYeARed20K~cFcCghJMS=6d~x$_vMH2llVEjo+1Q9i*cKO!Pgh` z6d@Qad@Rfo77Ju`NK%C0rtn0lEjAZBin_x%On*gTx*$yOw3E%Cvxjp+n6Sc5ti^Q& zn?Y(M0pV}m@mts<9hKbiTj(thmEG}MI4_sU?)a^90_%?7!Xw37b;oaEzDl&2)%Y#= zX>B!v<-71(*rffWx#PFcnd(cqw|Rrur{T~o6}!r{wK=#C)ktnV;9?wB{~vi4 z@~WSOCx1H;0Cb?lQP&GU@T={GcIkszT#4cE;E~py0=-kKZq&fp&(qb78t9!`b)yD) zr&islfpbj7R5xm%cWTv*8t9!`b)yD)r&isl!6|EXXbEZ5z&*5tSgeD4XbEZ1U=FTu zU7;nUK?C>D5|UX0t`3bfXe6@)+(S!9gI2X?fs-`AP05~DwVSJS15&%Ch|5J+>GtxT z=OKsG18STiVA5)y zBAAC>{p1jcAA+fxrwHt#YMvqxMOU99B#R8r(l_ZRbZw?N(~)`QWL_OcMzYAjy}0Mt zsVumP`xERnR%H!VXk=||?P`s-j<8O)k}NXVXx(EyYAr%r!%8d3A_Ftmn;Xha;6CS; za3qTi4s++ZGVU2y*G3dl5w@2YMmEI>SA0u5;fitSsJY1o)t3fwK<$jie>EWDNxh$?F$uZTE5lOpr+;9It^-CzP(97P0P1mD5z=q_AU)N z#9z(u!+j^jU(N7?4)O11eq$~%cbJz9=n#K3!w)*dU(N7WwU0(2LyZ6w)UMvR(T-FW zeI}+H#l7$->vHSr$P*_jPxOw|QHy8SR$IHj<3ue?0|p#;^%NaKAnj!!XMLZL9y@o6 zI|21ey@vYuxsJbFF$hdoqbxz*CgVbgv5&M9_wym#CmcbG zpKh?{*q?7j$v(tCjE}#)>`n$QtAQupbhwhg_dP!phvSVJHF{=;z7iqVNJJtb*QQIL zink?F6Y1G$$0S%Nxsz+7YIUNnGk`qOW$0M0_RS% zN8LK*!ZIo`Bc&OXA(nC5rv8eAgi16hm3440AOn8=TI5z5R;;L8F{_g+C!|M9a`K)& zJr%8X{e5P)Mhv6U2#*iV#wF)JN!uOEkRGY;Tj_~1&zCK7$6IiHizAWBK9zNdh$bc` zCFV#W@ylPy<}hIqYagy%dp@#~B%}aO3?p$BP-zdKaw-itqz{c5(mTwmpwSXWOca^6<)}t#8xIb*o6_dtl1pOVy z2cYj__`R^iLusQ>a8nd?ITWT?llv2gW8%Be&GwOvM*xNBE%q?rto>hqZary>v5iC( zDI`xy!!Jf@#|O4@1}zlX`{U=JiCgP<)L5Xqz`1kdX5;DEpwft|@^QSLIE7O-ZyPbs zMDIZaHBCHT>?BjJ?9ILG?_CLbUH(|8wRWks{4j~PDMPh!WgTB1+-s_Ux}-`Y(IL-A z9jeQ2<-nAKHXvW1k-`lAD}D|CwS9x#X{gjt$QE~t59|Tb_x8Lu?A`3&imAe9()}Y} zf30BXP0N;*n0eEp;jlPd7R-_sOE)EWqR(FrR_)wBbwg~G1S4e~({@qXPN&y~N|55B zwD&n32CtxiqSCm)v|zz{<%DugQ5Ayo{rB^i`zuDHqIVcE>#g$3C%PnD7^y`1F?AV! zf6Fmf^5vbt$FW4##1j`vR1c4d35csaUWvk)9?m`<8c{X-_=Jtrbetd+c#X$^732NV zSllSzj>F|CMIeqJ;zmdG*&4a?D1Hrph`S!TAmi9E@fhIgIp6nw=zwVh2Ha%M0uJzg zh|`ed09^UP6Wq?9iX&E-#CUVlgO)w=cQ$QmXgVsgkjkVFQfH`A>Tl}4S2N^Keu%?m zTU80+PY8Y@6GP#M+(J}VKkG0oH$KaWFFgG9*PVrtSp;9;(e{&U4NuYg$XB!P4>&gb zAudvij3it2cD@H59yl;8u3HAdiWXuWJHh&b8!Vn^T!Psz!*Zwir1^x&A2BnS@LJ7% z?I#=IO7K|R53x_TMI5KU>`Kb{I;J{xT8tjT>3Q}CwRLB-(oj6H0)t{Au6MtFy`&3n z0t@&P4Cqq}36~UWtr!ST0~vt~U^HuLis9!B!FI!5l?Htze1 z*%jGi(x!UjHnnr2m(TQ!>#^5uDDfh0^TdnRXn&1cWU=wqH{YnhZ*&2je6P)9X8`nEOJFqJ7f(T!U zk@i1D=gxX-q`bury2)6z#~8#&Bc&-)wZ~Y(W$7>JxuZ!2mY0F?@LYOB?k2x0>t-b1 z$e=4ouFCgiP<)lw6(ErSIv0?xJm|b3D}1H0?`&isE@4ik&dAzF*5>yMF#c@ngK4H| z)5tdlcbO`Q!~VBHR=B4YY_IjD zY=N{#Y-D2M)Wlg@-|`t*SR|bn8uTs4LT-9kE@B5wwDMOr%Onv7%1C5UWKU1Ds4b6; z+?LTkFg5~t2S~!3sYe4mXSCqGLRL+p9q@Zw3VAc3QTvh`iTKs&Uqouvh>-$p;DR|6$AWqa?QcJZhG>Q2E z;=eFu6tT)#R+-IaYI&vXuiB42Vp8I#HpzJBofhxx=z_BPcD~tJ?R;S6)Z?sfp%X;? z!YsAIhcB9NZ*ZrryV*``rZv|J-#)>3nYuCDnGxCCZmwsGB-CoQ^Tqq?6n8)PLu4W{ z9+Ot6GZ$=gP3VRRwzq+7Y)4lHS&5woNk;%ZmV<;S#AEq#!P@JbZ3zG2la+iwn^AyG zK?k3s$`LuAcD{2>bLVyxM&J@n51EANX>05t`iifMUBrIka1lNg=ZfhfInJFr5i#$j z*udV(9%g^X9=FwQZ((oei(lecC!hP@he{^vp_0)|UD+qUlMf1bS_5iapy)vXqPG zh7D^mY(*7zk>et#@D0nnQ9js_H>*TtI9(}UsEks#E2~S1Piq;D5>_+q8X`xwZfa@! zsR%@@R;RtY#I$5d3eM{{sdb+oS3Y>r;6e!=)B~P>&xF%Mo|U0uaglLI1$xNBnBxt! zO9FnIq&Z8bl(_{zr^yk->#mX1}C+abh(zOexeSfbNGA(66jkBpjqP|=pOMI{aX)MM!(J6x%QlX zs`O+6)UF%vihFiDG8VBO3;vXVX$nlq$DY{w0C-OdwJq{5HNEZ2RdG1c02X zvvEU~A`A8$V`N(Lzap?8ynzy1U19qllVe)Bl4Ist|8P9;=fU0Hk+?e|%r!&&N+iOe zgCcQvgug{+IEwvk`v$6?eacqvAAa~Dlp3IL$z9Z#985W=iB<6Q4kxt(uaCi%{EjnO2 za9}=10$uF#DU8fbFrW(Y(CEv7SZdrf@=j2twDeg1X9p{P6#h6BPhcWB;RP}dhu@1k zf`Y~frFfSTVI^@KhtEiobib$&E6GEJcz-u2D#U|o46dB!D~I3j`5S!`CyAR|dyS9X zcQE!hA^k2^%0-12O&2dNc{Rp7V85$A_0yV{cPb!SG2iaKzD0$2k~Y)MDiEkn(|W5% zaj~^g^Ryi;2Y>l*t*88f+MarwA{s1c+3uE>PSrsb`9S$wDp7_nPh2S2AGkMgTgm>w zCWi5`-dIVb#LXRiJ@9hiT;g|1hAXA6fhty5>3EPfs zZXLh^aY3PM$kV(#m)&Bmb1J-#^(pgPeU$Xgw^AP@VWnDBh(&%0LI~Ud?xA%shrTC6 zV)z^mh?4de_mrz+3$PI%GKj+}+uet3Un$DKz2@M3S5&yiv}cbe#t!!8b)4_~vg9Z#_)YrlHv*s(6%qlhpMBvLJfnIO{n9@B!K~{A*IC`RERS@h5z-)ON>+oN z*RD;y<`+4egUoj) z^x0;AS6yk(!7LH=8OBVZx&0VgpeC!6*xMT1qQ}_h(ao6t8Zlz2O^jGJ(ZsIh#9u^I zb%9PcvCmsRn-zYs z>K1A)2eqf~a-&DZAHrrD2AT#A9K|i>)^mDNI8;Z4>q+4--L}xS+D4+nWm}2up)Fys z(v%OJ;hTZqKLcMCJd;e}Q15y=qY!7$^B+e}HyA_%vB{sq&r3LKI(s${wN+$!evMao zC+Ovh67R?^4oSk|YjPUaU7`8BPM&0D3H!ExIm0LP5bCx=+svLed-h~O`3gIO_1oY$ zBK%D<7F2X$^qEO9aq`+GppjRK3xNsEM@@M6qQd-)E*4}r#)%KV^~THjSpLe4H1Rv} zN3p^03$c%`5XaiH6ti5_`}8YRq{=Xmv|~7DC|;7?#9nOgwqq}zb7wR?%mxU6aAKWa``?)1W~G$5+a|l>JzXbW+0mDM8{} ztB|Bwl>Hzjpj)%!SxC@KkGrsX${}ymSjlSlacb^%XQYv@-RGe3*_uP5%4hDc9 zIB*~-fiuLsD?&T*AxhU|eo@QUUbDQm!!Cb^=iswCqxn`K#mqS^za{0`!+U2JE^2UL z2Ueit_CK(%!=Hff?O#b7q%Zh8doC3GmR0K57vobWV@M#55^nEbZd$&4TwKeH3)n`I zR6&?%KWSfT|3SVizb}=_GbM|w!j$%= z_U+eehwWtF-Vv3I&_Ws^u9o|%2V}E~_?iUwR84iL-r8W*$pQZbv$e0a1?o52wtEZY zOnZD~!h?b;Iq%8$6<7h@)WELAQk>>ok=Kc1_EB)0x=P)rh#8*lg$LDUc)AzfQ{4>j zCegj?+y*w);Nx6-V()kpQ_0|u~U^+7ftPsDND3AU;rj9evT7`S5eof2Zi zvS^XE2+;Zn*Ec1B?Sk^x=NfvZU=t9~(Q596hiU;!Qs6;%wXRmaCDi3^%H5$P1uv5p z!@cnkDoM>XMAqL{vSDx%@+&QdAWl+}>W!$&9EyJLPD#L~xLHZqEtjO?TyYWCfPN4A z=z#C;G!l|YCOgF~9{jk7 z49KU9!sG2}Nor|HK6exFPHxa66^Bc)_8Y>ZG^{_!&sA_;sf4v;3;`} zLPA19bm}<`+YW+F6ZheW23`2yZ7caLe0$sJRyLeEMlY=z_r({6FQ#(~xz*fQb-uVt ze3n**Ux)P@Vpd?8iay-L3GVZgMsYXy8+VD*2yI5Je3EbuwSEJZES5xX9H6XU(R z;GOBWM0hHayiuaoy(17;UdRzIi|5u7gf4p&1_n+_M$^`x3Bhpi+Vh>3sh>~#{PX$L z_F`;*vWCF(Yc0hPafU=v_GXF)(d^&p8A)2%%N&`Rz}NByIY%F@94l1*P=G`%8n0cq zKNWoESf=(l)U%HI2jE#^N$gSpJ=I#`Hnky7sDlN!w^2ZtLU)fqASQwC9)ZQgB#?Ln zCYZ1x)tu3EIAMm#RJBDj5qUwiMTqVY0(u%a8PnO>O1kZvRR_o5UI7{FIH=9EeG~r& zL@X=uV%}$#G4QWZXUQ&0hPUtT9kVngc3N!g)WR8^@shP9YS{e{rw$;&t6Sp`W%Cp6 zi*IAAV2H%p0Rap>V&}9a5j)CFqi2K?sKt_qePKl5-q6*o4z*YkBLktQqRYuim>(?#V(*xP6IRaW$sPj_k=jCXUoHi=mQ$H| z*p~3gZCF$lpv3A}ll znv+K2RLACzCQ~zkE`@e6vl-@WBz&A|je44ks6d4zFZrM_4 z30NiGp4hiau%FzNy)C0b?90=k*`Z`%78uwfFe?nt{M(VG!fR0h*AMLv#Z?3G z2K5{Gvc01;g4_Yuu34`6S?Be_bwvF*W9Apb^we&Fcm8O8{_3jq}aZblb5Ace)P;mGRtRS+!k5+2eKi`A~A(-<#=&sSO{g>$*3rehjmHU z?U|piG0fh1U~6f{ltbV<;4%KdXemJ=Sa#yh@UVy>fh!ES>0BK-B+wgs@~P5AN%tRh z7X5?;Aq)ta{Xn$=DcRx%7JB1G<3Q>QD%Eg2V!WZH5by)Fzcw~^v8gek2czM>sAq+Aq4c!F(=7*J zWw4%F6;M*5l{jmUlPBquBx-U6vLu7)a2a6|Q!A{I_C!X~4c_d4i}0Jq3$=+MHIQ!O zI{h^>S9BUucSyp{X=fx>4%m6?xe_~7M$=;@@VJd|THQWmJJTB5A~GP&=SLr06tzI9 z>Iy2^WZbn?}ufH08^|KA)i5O-PFW548;H^ja z8+?76x1h5upzF^!@v8)qNO4L4qCdaOSMqJedt6uC;@=;ej^FQQLF6_cgA<-%A{p?I zY0rywJTd9RtKyjm!FD%2x;@JdyX-DKx^82c5QRe;w6Q!$R1&G)SR&4P1t(lX$$+H0 zq_|8{z~z$SGD&&Lv4Pj`XOO+P)8heeUO02(%o(C(zP$`o19ivWDtCh6jb(t2ORurJ3qDXD7C3nKDO zRy@z?o|AJV7ey1RrGE&Bi&6{fg%m*{0dZR$Q6s+O6#+3xBldY)t<(OMfLN@+Gurj! z=nsw?0r4^I!v_Bc0>Yq?qrzpM7expNiEVA`POrC;$1;#zUddgf68M=MxPZ@d0$c!y-p|o1sE*+3$>3r_Fb1lx*4#O7o zykwI7WT@%Iyh(+9ee;xOx zu!3E&0&tvoPid|a-WGS%jD5N~$i7dXxqv*d_j5)OabTvZIikR%BzH=A|MsGlT-wx0(X*%fK=d4 zQW1~}++&dbyB=FtsX?_3r+xu}J4r=cIAIt&iJij=Y!<7#aDw|eLR>gumUXe!b&e2_ z3f#{TG8_Sdy}3v#0#boHN##67+({||Qh_^3ML;Sj;z=>0lT-wx`tMH*a3`qb8vSJg=>^5w=Ec{NEz1X$osQW1~}+)1k5^iUcm(4W&wXpz=qcFSnIC-7c+ zMN$!v3KlWdBozUvUTKo7|9A+4J4r=ADsU&M2uKC)Bo*-x2A57Fi`&H!kP6&MDgsgg z321kbR0N~~can;LRNzih5s(VpNh$(TfkUV!sR&2~?j#ifslc72B0ENKC#lF_7u-oI z0#boHNku>^a3`qB8KRA!&j431f&9Yl8S&- z;7(EzkP6&MDgsi0J4r=ADsU&M2uKC)BozUvz@4NbAQiZiR0N~~can-MJ%FS&6OS?1 z(gWN{Dgsi0J4r=ADsU&M2uKC)BozUvz@4NbAQiZiR0N~~can;LRNzih5s(T1KpT^JUSMjiw|Cv9Ex+g>yOj3t1~CEUjnK;{xXC@U^9r&05%RTONcex^=Qy34yC-IfLmO_FMDbPBzk z-bDXI!?7A*Twex;F_W0;RGf?r8UMdK4JTLg15Jao2B>)FZh3k6OAX4U4ce*kyNW(- z+Up+wX!e28LaSa?+WlLP4A947c;5iMTUm_SyB_VSZiY|pmP^L>F$~-I=fghQus545 zJ`&%ym)0jZqu=Yki$b(sebSHKsF?Zoi-YXfo>HGW^CP*e_ulx9-QeXpgxZ%+b@sYj z-T*Uwy{nd$fMK53eS`69{D-M(g;!NAFnYy%9)Q<;yyGz@+Tiil2K*_{j!jXY=G~9> z3iPT~tEXYQDULo@t69UQ5Z{XSHLUijGz5BmQ^$9!zsFX8&#g_H`PRy$8<#dLfyqtp z8){eh*NNZiUw3O$o^IW`oDJ_7)bWk?3hI^^w)*2=Tl^g5wHqyNTL(L}@&R>6SFF~KX<%ai-b)nVWa-&-Q zuBkoM&oJkczJ^y%uGZ((lZ(%*{^Y75_~iP*%(o9#x*pst=AQ>QpNc8_+i<6%K{U+v zsw#nKwz*(BVG=6&w~14THlbo&cZVu*AOj-q|p!QE*r)G!70+yH|ey_0VO|BsgphG`$}j zmJP23hi!vqiNRsHR($V%XdWDvln(*HVaK5b{%aw$3=X>tba0rXv^V||cOWo0?7`Kc z_}=Fb92{meOn$wC+0Z)5Y-rQpe8tdqklFCY2(zKx-mzvw`$=X)hiPWRN2 z8#*nrYJ+tx=~}Xt&jSmRY0U6A~@=bA+kf1A<7(Od}nV5v$1!S+1RJQ z**LlHAhWUG2(vMItoe#DW|G<1f126&?%vPM#sTxp#(|6RE!O2`<9ln(#@LPK=Ek_~ zX5*k;<|*(?*cId8!)D`<6K3Pky=TqF53ZPv!*1aFhu<|DM?5qeN4~)SPCD^;&!uX+Ag!{v!C%T(+`_XGftRI zN%&bzGq0FUvu@y9X5TfNK7VL7eSx3FG{+QWnp-!@#N%f%B{z>Ur36QrCZ~3YGR-qb zd3=eV#bbVy*<(R}v&TaGEFNEtFncT-YxbC&Hp%R4k% z($|_jGB)B{mTfnCEZ=4J_y#|V$BM&dkCi9P9;@)Pczk=s?6LX=zGcl_v&Y(pW{-9F zSv=O8qC7U#jq(ujvv_1SkMhV0j`EnC-66_jqdCg+JNzu3o1)B~-}g6rZpP2zxn+de zbL&{M=j3gZ%%0n)nLU5N&*Hgbp4s!q#b!@CeiqN1wPw$q8}Ti<+s&T4c9}hQ<7e^Q zbJ*;;_k`K=C;Tj)`>vQh9XIeT`|p}Pe|~88`~^RY=K)ic=fS#Bo)Uf*&%EYQo`-^? zJSXROi1Ivaj`I2yKa1CqD6`jZ{mouS@w0gSKEmvEY^>R9^6^P#uM^YEUMKOhc%7PO z_By@T>?Px8@jA2C>{YN4-%_~U>~(gR+3OsB7O(S%&0ZHyn7uBJK5O=x2f0P*+wiYT z8EcBtmldU_6{V-*>)A!=iACuXi_+uq#qgr^xT5r!qV!07(XA*wtSG&GQF;)*@GnaD zElRIbly3a7DE+zTyte7{==6Epnx@aA(&u@n&(o6UWj{%trzT%cw`6X!WM<>vYb=?| zESYJR%v5|a+me}R$((4(jK>$lEtzqa%os~%B);fo$qch(wzp&k;R}CDrmrQljwRFh zy(ROxN4HEz<{d|7={85^Wk+VABlEZ;Gap~+uGzb1Vj?CGP z%tS}#LVzg3LlXu)H{x$6=Z+(%)R8mz zvLmO^k#pRUlaDXkj+`KT;qS=tb>!4>p z$!l-P3&I!vmONieUL8xG(ULdlIpFUn?~Ws{)PcW_Bd^ercifSek1zH+@^T${+Z=h> z_+pJCZLH9eMHiVz?tO&XE`6$cw}m-5hygj=c7cydX#3d4ETq zuOqLHBhLeri?H9T-d)X74I5M^+Wm;EGw+-aRnxNzH`;su~idoNuP}c zpS;$q*OQ5F`OiMnrdKbAHnP*I6E}l;_0sa%EI;;9*fG{W?VRtj^A2_-lXP)raAxZH z?;0&WpWEo0^Hn=K6whNl|1LQBhNQ$;xFMf!vYp+8Rmmx2ni2;(#h~? zqtL+sAAC0T+!gSShA~ieqIj!8z7hCgRSaY38)A%xogH?xGMwrV5^9JD@vFmx8Uh{| z(k|Xn>v(#3Xr5JR3P#0NE~qFjJ2ORlsV>vLYF0NI5)CVv5UBdI-0)Y$qSD1GG&C&k z4vQgkzgGT<6cPZ7>V|mzY3o&Dm||!=s#fp!qO=j_&`zB~yNp^66Y7UdF}%%ry>4o# zwS}<6fTL3b1|2;#z5JU-jobQq5B2h0T=LD>!t4m6Glc$XWysX?(d}1YaivwTy)p-G zK6_jFtaYzm`@SwLW!v`3YrXQ^c~jw4&mR;xSa8_$_}P=5m(HH|yme0TfPaF^|5yNh z{#fG6cxHt7h`t#Zn_8M6`Yl%1-`ZAYf|ft2t&XWzR0{?z_&hbXcpMjGFr4#l#UyLP zpPp~<8Iy}Lw?{Le@z{G&7F!~pRI8yA~=xFmrI4>0yJ z^xa=?V6SNngROfmcbXn!HL^3tTW4A!&AQI|qcyGJM+F&;o+cJr;ScL$Yc0;7dz0(Q zy~nk*1%1Yu;*wiFI*@8$lNMvD0XO_kXe%|Yq7th|Jv72g`YIV8OCNsTp$J~FL`419t=Kob} z%SR7#PYTzCa=|FVyJD~$F7}nrOH;&TahX`_J8`eL{A2T3Q4fX7-x=5bz{T^Y>1Tp7$?$=4-QQ-Jqdw|(GRVW-F+ zXy~u^g;qy%DftJDR@1UjA`tE7x?Q`IcH4)JE#%9%|XyfQGd^j41|R;_`=y+|7)=ThcESh@{`A z$I~KHUXi#f8Y=DXZTV+&A(G7 zjQgW=ZbKnRcuVLbd>~8|8j>J{k(kn9`Zm4YqvyH*xVH@!JIE2DRZhMpRlB!M-5cJ@ z<-zN5L&>rM*rw@%%6L5Sk<-fCp-D(){DktZ6)<^xuL! z(&bx{!E_{Vbn8wJCNadgFAL}SGN(C8b;n(3GzGZeP^nA^mi|k{Y|33f7Sdo(+Ys) zD1xdjlYALgKA=dX+d*HW^AIm%sQ?sCbq zII@)N%0{yz*!n{{w@PAl8`t114ans4rONt`JwI^|9wUZU4XmxKVb(2MyHEeXI?)PW zSoJLUk$0*-4BzdU3dPn3Ru{2CL=zrw+EO_all*ee@zhP+PaF`_pw_k*f{%?BcL;rL ztz53I5ewcTyh<$stPH(G=>}p0m-9F|YFuZ2;P(pbQ^xb}MB6rf%^OuBqyVC%7Xj~$kjvksZ!ovgH0}(1)H>`zkwEwkN?an3#chSWQ1jEOrCzC9Z-wbI z)M!Nt_bJz%1NT1c8qi>&_u-P@ZOSjoY2}^hi=Nf@s5(&nHD(RKxp%UBzfh}9VjBLb zK39L&T56`%@a^F7LEut+9nw}YJG7sfPi>U{c2VHuxZtpkfZZy10>&`JxXP*wK_2v0U$f5J;bM!6xDUFys(~0qT$;2_H zL#$@kikuQP=CF+v+ul`U-0Z63Thj zcGH$W;!y}zEE6u=V0~s7|4c8?`-v*r>;8w^u|$lXcQU%zW2vs**E=vc;ecZN|no6HNdxJLU=K51IMks^E8mSeBu z(AXPGhFcU~p7a;98ux|}`k%{_emVPM2-N%XdZhd1*^rnQd9cG7(}j>T^EbwUYvNzY zoa1gYPr2j;oa^%Zn4Q%%ycMx;*~0E;J8pUH5_^Yz`I0R%k&>a`>xPES`w>667;C>7 z)yOPa(En;#Sf2o=7idJOe^^(E2xfMEEQFA?O?xr<-l9gPZP|E+! ze|#q*GwF|hx#aQ${q`i6XQnVk{1wl)UYXq=)z8o6h`a|~i9Qy4%7essd;;`^eJ$dB zI;(4!`y$v$>Q(-#TKgoKly+ zbuUrcDG?%nqx?)VO+Nz(ts@@<$VB=bC$E$7bp1+Rg^$2N`HWmDlQ68*SzS8^DBlM^~Vmv`?GFM_bVrr>&k*ze|mz4+C+Ur?WVq~j#dj|wgZ&Blk5An zxnMO0Y-c^AY~dPzIJw(r=gcA=7z8AM4u_NfDB%zI^IH-GH2GhI zhMEDDJ-!I0Dk92NNHP-r#L*%vmgi&o#9#(UGo2#3)<2c2PyV2$gyO1qHQ;j6>MY9t zKgH{bbWk=JWNd!U9M^uu6~WRn7%A_9lm99?3I6;@ylT=T{-S-{(c~YX#DprjzGgjW zTK>3=(kF&ybbA`c{hi82yRO1i<57xf3x({93X{|^ z5STRJ6On0?Ce9H+fE*^wlnt^C+id?#Smx7SuU+lMea0KjQ0=LNx+T7 z6v?XrTmdz=tCs<4G|szqPW;0!EBEP+>$w4h9j4r|L4Q;0EXe_9>hSp$y#Avz?yZ&f zrZ|`mA8&p_x+*=9I?HEdLuAWl3!0BA=1El5vRZ+>-1!>Rv|c)_b=Gcbid=|Dz)nhy z8-)YMPV)=Xi`yT{6JOV*O7Bfj<0?I>ylU5_=GLcA%tURJwOhlfnTj=bwx}Rb9k0$( zUv<9#K6bzExK#zV;)ZHlBWUwO*CYL`n6lw;xeIuMslK_A4^&JeJsYQWC zcw5|p2jb)LS@;rsBOY`Rcbe7wB5=5Bu)k^iWO!23p$G?-d1ti{_j=VUSu8J=k6-6? z6@(;3mA-ucF(0=WQtvxZLESa>LI=XH*V7&Sdl<*n4({<|-~IVSJh7cfCBSd7l`Jh| zY6L#6Ke5F}LiGZyJBoqO;i74z59Ro1S@SoG9t7G2_1eq8B+&aUg9nx|6txBRz6^$@ zGR9Ifs937u{cQI^L)@dF3AdxU&-C$OZc$MA<{RuBk#)DLb7ajTssosknp{3Ms#o)X znM1h3@$I4_K1%K{ChQ+HvQpo`#JSsh1thh|xrjf&qr@HOoNwgZm_)-(-_8F1w{y~W zY_IKNQSN@3;aDE&L*#A)1(8p8ypJ4L`%9#!iqc6k5bS1X^4{>#sbaK4jOPAxmj_-F zu_x4fnhDFRPeU&>>_9WL-RddzZ9KBz zPYGr`=y3(78$0FQsMDwzypeuL{}pZD zWdnmvrl3(SXZRdGe_>wBqO~rq9N}nK3Rk5y?bh3awlUgTZLd}dw_k$G!&*HY;_bOm zsERkjLAnryPoSD9aa28OBYqGsMEtU82W#(c3D=q2NDuF}ZQV!5iKfkBb0S0B72bLX zF^Raw8I*ZbM-}WOju97$-7*J(Z4`PhU9D25EEW61n}S6YbGM z@uLL|hoBbIbX2Wa-7*l)L^I&ZnJeK+>dk26Tjfc(YdA_~k%(K_j4OxV)ULC3ZT4p$ zNU%x!zOvwvP{0ClrC@`kmyVmadPcWi6$@Oy_JK4);-_&N{eHj7l|JFl(f!}8FDf9n36N}Q63l17;o>9!w1LjjqIgN2FEd(umM z_}%XJ*Powemcq~diO{y{v^0PzwCJ|qOUaanDO1Jy;>>t)?ELCOF2Wa+fiTq}-iy9O z-+FEJ7|Qb8ZgAC#UQ7V7EB}`G^d$v5Bt+f@I(nOK)h~}}7FgUGI@V;Jv92T5XDfzl zGS)ZG$GfgU=cIz>O1RP+AEiviziA1|PR0G0a#0z_t^DlajcTf~k=j>&@Sj@R#m9x-hx+~%$ekm|HM z>@_IYt`Z8_DX2wi^@7 zOl0OT05L-F%df+U^B`=yX)$ByKL}QrB}Grwh_DErp)CdU*coMcoPXYBIH5f@0agXny3eDE^JQnLo^D z@He4j?;DXET+%$#h6uADMi@eb^%u7bSmR_+-{DPWbNsIGN*IOr5F07LL$oN@c9)KxLyxA)h6RquKm$Dn>8lFBAt{bW9Dk%fo!crX55zSa zS^Qr*uW6fnR9>Lmm9fEj1HH`#kR?=C8Y|z0xym4Xf)a^aF?_RfSjkY3nR{q2cQax` zB1QTB-d@4#M73;=TKG}lv)a{JukKe*sTo$}QZ6;#sdX|3RhAdXmSl7ix0z!Yts zwo?0L>9#+HSI4m>riEd_o+R#vgTZ(hF5-)*P56HJ0o=eX&+v-Gjz%plSDSZePndLe zp%Uc{<41|ZMEP&+(7Opfn}7~S-H`sRM_tkldJVt;5_t`t$DOv6#GDTlNI0|p;(q@| zy`c<#6n4sTJaK90cnW3KfsN4pbb`&Ho^+0e zp>ybbdeFH1Y7yz1Lh2(+hbyxo9kh+@$4HXRLs$PY_z>=PzBKw4V*}Bce`gVihTtMu ztSJ0l7C4>oO-A{S?n*uGy(T1@*R8{e}TWx5B%nuJf;M+$^75ocw?+ESllOIIY}-K zA2Qdox`~4(C?OnAEr7}ckn_SMHbpO zCUTm4p#Vp;(t8orq~l5=iAW)uwA%)US{1+nkWqFT=Y zX+QC@q#iAyQava;EW;utt_ZyDd^`2WMYr@UF&Jv+YK!2T=bbk`EW~D+n!9i zuJ+ce328v@l)6BE@He+)Fs{Ts^H-)!m|#LziJ{^l0c)Au!r@b91-}*%;{wFyN@uaJ zV!bD$v%p$$uXsY7n(bk}Bckc7x)fcn3p6}SWdo(t=kzVBo$EA-lU7OW(v1ZuW(GWz z-btENOJ3Y+bl$pVKD$>{8>vRvB-LZRyP_r;t$z6U?~;|X7#E&}FNCSdm9|c>G;cWiRqbo) z>;>1IjBlRZbsEiJh0Z#L9`w`B2CXt(30m)>cTDR(c%s!Ks3hD8esJ+7K5Vq-X0|Ur z3coq!l@l~IUBmZO5veZJEeb_j%&b8WMD?33;ndKT009I76TXf*V%90--pT+@`0+@p|(F zFvy-C`pqMGVu^1i;%fpOu&MJk$B3zd9p;|g+TlkgYMvF=&!J*lrJES2AhfIx)?DW;CJsGdLSoYnb3zp@;r7UEILV)!}Ox~KhT#rV=!@1A|sQ@x*do2brF zm#N=A!bK~NW`_NRh-Z3V1$UiG)QODVJqK!MM}SSH8$sJ$esxdt9j#FNrd`Av%ZZyqVc%XtZKP)7pQ&qX zKJ|g+SPP7Sujrj2wDD#8ziAUsZ=;XW&5!rcy&vV{$Njv`f;tQee|2*6j~&BQJPmX^ zaqG(t)=uZEC%|>jFWMl24SI5hB`jud)v|6R=qxwz6cP{&VqLB|`~(JY3}^b2TgWAH z#+TkH+e4 zPusB$62=L7+RjArw19yQ$zBeXZsrNag1zW0hKRsN=`W6iUqH0DM%)eYg7%liE_J zUv{hUy1ZE_ma*x1lf63`W>EmeEghs1;VWQ)5)XfW%Rh?EBoxuBT_e?m>RX_i)w?&U zZ)?L)O2`BX*h|1RZdR{l6^x8@Qnbj$N~C z4GZ^lQbysB`rA*rjBlfk;aTwaNB35fiEtsjh&{7C2NC0-^D|~K@hz$kvL0L_eB0Hc z^ogO6_(p*0WNNxI9Q5?re=Z4@lUm$;3%({V@C1nv2UZ=#j(BR7=us2~?pban?h3UT zLNyB9Vc$^S*d?sZ5Nbb}ezeEKcKsrcKkbWZSUEin-DYw4^f&9-imB{2P&-^m^|BsC;cvt78BrQg6+xK-=tZv8A)( zbQpy_wSY&7heJ{QLc#4uT46y6g~4yYR=*-8&(_B~D)RuKC}`5r2O*IA^l zhuhZa#|jMQI~kkLunPm3Z%>0_!w1`sj#VUV`l5}@LFNpT!+>t*>skk#Z=6t3&c+#* z)PWDqP*ayl&Gqljc!eFn+25m0citp4R%8}dwV(%VYz;AxYcr>dctuDWD^BOETmrX~ zs}Zt(VCAvX!ccK5q88s!EcA zLZ#3_%%W$2qQsz`&Vz;~2Rn>Ru^)TfFzt*3Cw+mt)>ebiqE&i_Tr*{OLD$5*f0}JBo_gu?g=iVfe_o!0 zm}2Nc`$F!nG|N{0=rm|<`^g5oXD@wluu_?H@A>;>_;sZXcNUtXlAb6)If29y}#X}7B?wy4WD#xaogr}4Pvr5ihfOH{6;|h2Qiq~&rP`%NJlSq?!3DG zE(`K?S6S>~sAC_X`+A&ReOC{K$A67L#IN8 zO}q@|Q6IG=Dg`d}T;K!b={mc?Z`XE+=%65si@Ug*22(hWUdc7$Y?(&ie)O+-coN#S z&M+?}g4C`|l-loj&;%xmDT`xPoci-0B)GCOqYc*`=Kh&Cv39Jz4D`)P+pfE;A?FV! z{KbO*+U~!yLpl5VocV50>pOF{_vS`$Q#rsY7rFi7E+`-xCBEj$I8c)}^PYTneh5E_ zpUW@jx37F2yqiDHk8aa_T3aJkv2JY=ORgh#W;kZB`Gv1Z}$(Bnu^PGY3*3 zR7AVu@!`#Ho=ABuEcS)l)>Xch;kH%Jrdcc2lMG{w!BZ+_-Kx5OMw;32p`HjZqbG7&gO$zrVLX*s2`Q-Fe+~s5XLa&Na2T}0TS`o&;f_3>ZcHB_ zP7@Ufhel;ho8Ee^kY)9Ew& ze*~}QfI_GDJxq93Q@$InG>WI?UjHzM5Xa z8zIDH5tHjB>ad5&EI_aa-!}m9`WyaAh0{EBhNkEZZ=rV>rS-ZYG%&) z3yr4?$eJt|#$?9|;NQr;cvFV2echWtS62ND?t{1C?p>tSB8F#_IXt>)H|7G^uT+x? z_A=MYm41?|34pbSH)oAc>ewFNY~6ZnQ3^G9o=y z%0HeqDotk2lF@&WD9Nv8H`})LOv_e6X92t;-wZKQe+g}{j)lfk z+o@D4o3d1hTi|v05$#E1hXcUAU4KO!6DQJh=(l1neUO8os~ot0`$F3w6VWOEc#LAE zGgc;nakx09D49Wgv~DwO+txE=4hf@sCpSriDcudIv83pD`;^0O~S8Cc7ii` zz)<#D{6r3WW_^;Iyd7e4Hgku$Wpq{ksrZ?5kgTgk9lM4Q{V!j-n^*DrTCZa%gRJXi zRfMP=wry)mp`*}WaGN|ND?*47z*=FifbzDes`WEyd-F~3vxSSgwk1lm?^Pt(#w*A`DiAKCLyq*g(7#l}4F&68)VoK0 zM_v97T0!P#Um`@EPL$zm)xE0egnCtdqQ+P9{iarjnmy<;*g0%08XhCGrx@C{wl>xO z$T+ZRn%iV>#`U2_vncxyMgQ%a0v4Fl$1m|5hue~3&3aUB*E%XdlX$W-^PI^-Rr+#cx7#RyC~rb3v40LdPa0z-Y|{B3au}5)3)pKJdn+q_!nXsS5;asqCRTU8)=)} z-fQ{2{0TnhD(_!9{xx65*A)KVVOzJN2@wnuE_@x4^-FmSZV0`q{+2P+zS&JZAl&*3 z$ktEVCSssbMnk7pH_waunyv1 z8q4mozkK8td_3Vu*_uV(C1d4r8^Fp>2jnJ{9vbeT{M8W*Dq7|>%+OBhq3H4PW<5Th zQ*#w8pos1Pesdf}qdi{&9R&kG#;YKL00e5CXH@hwSyRccUAd}rX7>-95U7=o*Jf!2 zSjF23JL-Z`j?=Yq8!}xL4V;!SxWGYqZsL?!voszo_ne69@FNjN&^%)Sew3&}U@_)} zk%Rn870{IkAlj-2iD-H~v77dyE!T-WqL{EJoym*sp)=H^zkZ)AnYf5VnyK>o-SoFp z)1PRZaT`7d>-`cS?eR3~*~avMk83hQH&Op5oAf1Z=t5)11O9jTa!8>b<+a(D)F5l|F)#co{PTT;lA^#_bfqL<8a?`i#wD8MZ9UiLFDQqo;($)h%=A0WX zRQ4E?_1Ef&S?@GEEGpZUX*$ThNd_2c-|{9VI*GQ%X=23%A}#F_vFpi%)4Q9X4e>yH zD~2|hlZC6JB{tnksn?Wostu`By=Le=I6FYZu~aPC%b9aqPH~aZpq6&aCT$IqXUj`v zpt-I2^h=an1yWc$4lUxn#u$7Q9qnMTu^kqw_Z4hN5g6Q~sbiT^Q#Gre>O3`w0F%@x zq7q?K>!qA>sJ7nNZUe9HkPi)i`Uh&B^RzeEztYytUplW9KZAj5&uUvPTyibYR&1#Z zVUz$-AC632Zaz1DwI_-@2fsS#8$6xB2|H|=d2!@0|BE8(pym6)AtHvpK^!33(^qLk z;Hu!SxwW|_^(E2B_H=1pi95QxA0=J^VD z)jKF^pk}16GSlzj9vRCBIJpa~h(H|_VVYh-mF6uPsx-qnTL&G)*w2F6R=tJpWSlQf zE7B38!82^yRs?NwV>exDmk4Oq)BA5P5xmoOMwq3^hmrh49+GP!exE(faYsdAwwd2}k zVPbZS@I?c93w+y8qik<3#&m(qR#6mEr32<)$a`Oa!0ANyH$j zrP@X6uRc&_Nal(bDxH+pFZMzG(^w|elozyQQ3DN-rCT;_Ye!@pg3p3WTRx@BYX#Il z0iuU2>KIbA)@z~x^-q8>F}A$z73wp^4r7W&^l0OFLqs>S$`V+ljwT}11@IHttD^pC zd;-%y)-P^fLnAZ~t(%s4Y*@H{*Dv{3+qzRb1|`T~*QJ}T`U9aEj)0}$L4c6;QMz3G&?N0`gC_D1al0S>| zs06oeHf^iU4BB<6au{ezA^MjN|0>#eIRJp2H$o3krzu_g?m(OB!U6CLJ%Gk81)Sft zHUfmx(exU6H(f+u;2zO$IO`nFk!i-XXL>Uum}~!dnQgZT^Th~s)*q!ZW01CWZ+LxH z1`D7FYuBaDiNn|{G79$sNVw$sK(l(^uCzUmEoK37h9P+CdHBrW(i!?yfAtQVwzVc}W+w`u z`{X~fRtQsAGvw#j(;qBGxVgv~>dcySTSvx%iM9 zA$h2vrxXl7fO*nNDM>eQhg zX!h@@_1C0fPb2k%{tu*Ut=P66(hx+q`(*IY^^2ZPfK&J&{QMNK)qH#WF3(@Hzgg#t zT_Ktf*cS8pNHE18m99y|T;e>O{gVkG!QcLumtxyuKX({-N+Kj>$&y(DS&B{)p51KQ z)^0+uP>Fi>)fCo-0)l{s|C!Vx>g&c^0abQ_2cc;Ax6S@$+UQ9GW(bYl47j#ShqkjhG#i8E~5R#Y`RvCqEtNF2*{ zr9dpZj@`$eWZOP4#&^AqZwJ3h7phznIeTw@8HZJlHx%67K8McWz)eo1+wu-l1Kth( z`T_jE0bTnS`=Xn^@jm~CA5$8obE`J*;C@aF{RJ=v>W`m&ottGF{wuEfU%&hT-nl8=V}%2Is^jDyoZEscSnfL^(bC#7rB{>46M^sgzK z<;>MB=b+LRD&M$eTedEc(Lw`6ZxBEImwN=(cZ?|7>ovz<8~rU6;!nso71U1(_Gb~8 z+M}x@DqWqSWoNz05+Fuh4L<>W^e<8kTJ-+K?e)?XtX&*7x3J>CTISm&@z==kJlx6m zuZ-W!lQP;&*P7;Q=D1bQT>C~3LC3bSj+)rBcrZNj?2>qVCdHei-< z=ZgTxo#0*Qukwbfo2e7Mfo{lL-t$-P?h_GlG(f)BjJ{pN9&s?Xb9i;gmFL`fl)=R? ze=zWF@ccc`pMT-UQ~_e;8)?F~$LoZx(GHx?RJit7gfs*tHV>SS-ra1l-cZ z9%@@>tkEuh8ODaJ1K1yl#^`Y~6B|{zZ=>dc&bhAfy>7SJUN(8rY)7u<8nDvZma}ky z@SQRXvU!K_j^7{7tNP;WcDottE{KhJP#QIJYeQ)ae+u?KMV!v(AV%*_zN4G-^u0*h z>ebQQjh#MoPgvAUc=lKl?30=0`+22L7B0Y@>n%W>%~`juN78J$^7(cfGSSY}Av^p) zrODe9Hx&2EWQ+br3F+&!vpat6TvN5XZ{RYyk;O6~{c41ZrMyMGTaH977{Zo(sFVvZ zJU4n=z1%?*cnT9>5X5a3xRf!^KIf(ex2_dSS8Q%fC2pr7KX-^w1 zwD8zzo_|?>Bv*rSnl|{I&!my+thDJo`e7dm{H^fHHsz?Y!}oL15igjlT*eN7SEL&1 zLQ$998;`2q+Mm7V&+B>F@e+4T1sBx}x|#N!FlhvNi0G;1=mX-)vYJ%A0c>Tsb!{L& z=Vi?(JRCNb`&nSCzmBMP!>&HsbHS%c&3WDl_!<@*!;w7r(e(E2MdQ2pS0@09JNjiB zDkSWukjb;Tle4M@-Y4D=KM0_4!^uvJH_tHdXtZ4c0{Op>zAlZ|Sdky{{nhT}*C)i| z=%aU5S}J>}{!hTEurOsOJOHEEu7-zag#dEr-w_qT+Ryq}{)y-p`sgpZULoALx)j=j z1#J=P@eqw4t&Z+U;-4m%USu3%XT%5$#BpDW-`NjLaBX}YAVr>tEBbh6Tok%ix*lQV>y z0;JSU4RJp;w(Za9@auHXT&P5bI#{qu+#$ZL`8EU8`FOJe3TcB||1MEd4|w6QKPzR| zioW7}HGiXYP&y-l9I1i)L#-q?(L}YgJW$RHkt5`otEuP4uY>E>%8*VlLr9U&%Xj3H ztF|qCCu{O^Va>DNGriYNpXI(U==X)b8LshNz)EbCa@=Ev!`xf*9Bxt@a{zC@Q$fA` zfzrNvdtm7fx;XZy$I#*3I;*v$rqV3cv;;bcCTV5;7FHW#aH-FLcQAv99YmrS!Z?YG;3MOGftM>|s zibj&)yW}e}MizT6^zhaLjv-9cH@0XRg^t2t@V_j9BR(fibuAiax6SD=i3{)_ZP^xbY3JUEXd0ji@;Hq$!r#LY;5y^djKPvZR-{dfwo@l|;=yKS*07@K zJpTwb`z(GiZ+Xj1ukH2Nrn6uxQIhZ zJ0_I0FhS@xvE4!eY2ahhg|WVib$QE_qc*`x1F?+=x{AqFdgqQ8XNgNhbi4p(ME3^O zax8Tm^U)M(lB_P0m()`lCQXri<&_c!s^-|c-p$wTYcC~udNXRj$!)X~>R?%a1lwSSlDbCCSHQeV87O+G34MVD%NM?~icz3rFsSa*i$NBTznKXzEHF@mJPDOpqHWX;YGH6eUw~IY$cE@*La)Q zPL>iF=FZ0Y1-^hRY?2}yX`9FhW-+-Iz9KBYaF9{6)*eH>DTZlubq47LeY zboAwkDlfw@`acZYoc;Sl@^&7HSVn^_v<^K-u;MDrUB>V`gL#GQOq&(0``5rCcn{vg zpJJ}ScSJE`&zhatmTbqVed6EE>M)d@%o@?L0^D1s>sz`m|!|NyUPR|RrqgOC^&go)4v`DTlgu)s(HvWFW{uBhPM!ag^AUu>l@S3zj zY9SzAwGjcUn;i39CTtNz;jED9ZCtKwRPO0FM+uf=ErK)O3B44`XbvNROpKWCt17T;+C}^{hHl zo+j(b3&AgZ%#wUVekOmCr}(Zw&hIiGW%n~(vSQcJMf4KqD#P|IbVyR>i{QL+M=4ak zDQw@Kfa^ZM5!n2Zy4Gd4YCluEtYSStw_rz?bV*Y|ElriCY2C=-+C=gb!E5Gi+EFb_ zyQ?jAZjZc?Mr4i@Cau(+-w$eYKew)NI6x<|Vf+5^zK!eNThNGTOYEFG*FAOS0{>CO zbOKn31VVRJJRtUx6lboa1F;Kq=2DapE`p2U)^gQf=f{Ia&tGk~=?zePlF1$R zPm?f#$DYRL6&y~1?PC*vh;OP@5fteYkIB|mQfr}$fD+1P2(HK4nQaW#PR3Qwgik_Q zWpUQgDL)k}2+Yz~Ea@;fH(VUZ0bNOTS+q28&IzdVTRtcit4fWewvt5(l*UW5B>V32 zMhSDuspFcTzm%6@xV(o#+UL}ne|Pms~}eT{%2hK z3dKs(pI)Al4vQUZ{Sv%Y%9WXrB_Gp$kYgLQs|o_tihwfsV%e`oY1dUdtPkiN?CkPE z#UQ(&1x%RKdXb~GKgh2Hx)S`O882xMwH3}DwnuR0j!CQg;iGXDe^T4=U5F&zzA=VO>y~GLPD)EFkNE%4&Z+9>+wr?O} zG9x7OF7hu1tRe;Gcjf|VLo!F7?djecN=*@X`|kQR;ktmzad7WeiM1^nl&gH32L)jb zU$!M7PoVRmsx#hG=Jhw!u1RqaSjZEU-GhlKKKZY;ib8H#G)jvl0PxhP1uz#`(*+jP5y~Lwz zDVo)KE`+0l^D->!+h^9uHQ?g!yY8}ZK!0^0UW(~;VZ8Y{P`6*?9&m5Da(Ki*r&wc8 zzK$@3$6m%iFGx*U0e8y$5&j%sLnx5G@>S$@QW7cn34?_&q1)7IZpYi1TT#1(MJKnSfiYJuHaSva3)uJDe)t^%1&CS3_8mf)X^H8;pDaQUirjT^BDG_ zjOMn84(pIMw9H>Q^2~Os9jnYxVwE;?c!vYZX&BY~GfXC`Zy;FGeYhj|Z_F1u!rF6M zu8Iu;{ev63pzaA8LHlo%Mw8>U8KfP#Q47)AXTFx`?AbxnO!|Fn&!qLbxT^d`?VrvV zuoj2?6K^x;ytmG^0H}X-7gseLyojpc37D?<`iP*9_>C%^;6yJG zbp$+M>HPhtLW*~ui_qJr^%kx7&xXt^hGH;qGUQm=lIU|1x|4mC@)?lMUuPb}J)AvT z(LP!G{;Zpi&%dz_lb&uoU6J$~un-OnIFyJuB616S7|a1}clG63&^9?$-Phnle2eF$ z+i!BV=4sZ?u#JV8JXRF{rU0By31v|CT+h@M-b2ZVN{y zZ7LQ@kvcT?XvNTgJ+7ml$lA{tm;3XPkS1Ob?~DB#G|w4T2mGFoHZiTGE)p%lh#AQk zD-D+SNmy*2*|j+Tssx@$5H2kDmz!$7axeG=Sf~vt4SZC@3eZ{hajpgrR?wAVLEn*JRrgRwxYr!0hNuy0jEau1C)6dH z;fack0Kvg6Tqd*0Qbn(WEokLGE=M9`L)xF+YIW(`mL*| zNhmI)+2A?%JU%uQaBu`KrE;qnA{*1+aeq1p`giCk`py2VkncOMMxZhVY~w%L9~Z;@ zu^o0kL`qu~-JblL;hCu|Qpr;XMIG8og$R zFRWFSsJLM1sRJOliqEdWoId(*;tp}Z{Q6tG`*XXLpSd)=12T`@QfJleX*1(DKsS`o!P@P~E(W&)j#%yBL=hX9A$&)t`{& zZg7`pCi%}Lz<-NZDUnSY8j;v~_tmjsfmO9ZkX-{D|i z^x5BPD_*}d-E-d0PL(-1|Ag9=( zYTN`MI|-l}`~-eQ)pUa8OD|q8gyF_r_F{>%*z%z7b#FK_^wlaPu5h_n7j8O}t7M$6 z8GmbrXm02inY(Jo{9Hg_{GF2`xF#y%2XTBI-<;`nsQmg;60B!Oo8E&j&J@#_#1jZZwathU z09X3%{+W;Qi2LzlzNDyaV(%@mu6iP4dzBN)X@}bi2Ci4q)t}AP4c%vh9o@lv$Nyd6 zOjp%b@R2!k=){rDqO#NX~czB_y?a= zJ4|KXwQD={IJED6Tf#yF5@0-WE%KQAy_u)|SJbcDVg~^PFT!0SklE`KQJD-Q?O&41 zm+jfKC@!#fk7|}-3=qksEgc3PWK?p1oDW?RNgBi+pbOfSOU_zvBysiYXznq6CLJ-S z_vCR@q;K%W&_A;lcfA;vgkS>WlarFiw(NDsV&vA3Z`Uf~<6y~s?F74#mA?5Ww%Q)s z3ncB0!sGCkV&LFk+)(KvqSZI1lhT`yc5$)rclXV3OpbhsgV=5BB3JE5imY9GUu3=# zL0e0>{OrE%(juEwp9hG%#PN4iN(ZY$!VuUg?%Ktrkchn9wVArs}7Q8EruC<*SOP<-v9MLsmTLfA?j7QILZI{%9IrZctRf`w(@mgEx*mb zfPgFeY{BqlUyaWrGe?lUgyB%yqNNGTcN4PO&Q&5x`gx5{F;S%5Au4uJTg?* z_ANm~ful>H#rr>)&eUbHKRyO842M!= z;$ZDz|0N1^7EJ@idw7I6H2k2EXh3kBVb#3Qngu_%ERELo06T~@;sSw|$pI?^EaPLq z&_EOpw1!7A-DTt!(kPODQ@2QrwzN!a6#AJ2MheLcW>Ev!Q0h-sV}PD{e4Rqs94ON_ z#+{yX;Lsp?9NmUk+{L$v@@Jr*}D%F8JfhO;WqwlyrYK=57PHk;9r|K>J5B|b)a3Sf& z^Xn-U0G*H5`0b1(l|jqo*}_+0#rMOTKZDho`?dK(ypZ>eNK2FLMDTFq3+VW%s_0UK z+Vg*_ZbUqRR6H9`5@X=o&?sIMk+5atxt*0pKh65~lirfvu>e$LT}palm|d$MIiOZE z`{Kvaub@j)A9QZd*rr^?y#J=sP1rqxs$ zVQh`P7Ya2oVuTY>eD6p*0wqvoH?^4qXAxitv61jg-`NA1K%Nty34rLdv*RXO7RO8v zM8hMPO3o+a$?aq+nN6;tUXym%1PhbcF0=-vlh42kYCJoKS^{4WB6XI!MHvgIFVyYI z?ds6YX{NyLM^#FaEmTBOZen0XPU74{37=g1VHizFx-4TuE zN0d}$K~YsGsp=A(AF)m0ATeuFg3b+%f-u?*0yxZ`hP$`ttp4}d-nE53KM zXbUHDXE}Gs6VSP>c~OY#fb%tufmZw$bs(>!^}f8mkpwE2+)L5t$3p%aT>6>N?zkMT zj-lK8%BL-v;GTxiXEpIJ!gcwXP%K-m@~^D2+m$`c^F@89*P>qPP4T%{_E`+8;0YjZ zYaUn3!Q8U+ZUv0gnFk9cou1OBRi(Vn&1w__eSZ8+CS^Yvt&Z*6DNAL{ArE-pES`-* z;&bFfLK_9c>nSbZM=($^hbR%yqPte9(#!p*lBF0C8fH}Qw90CIwY9qOqmA3zR|OD> ztoBQfa$2MAR*$QfRq#lCuZ|tj$@FKCzYBW%!XYkDLkd2$I-Z1|(d@8}ChxGyo=-KM zdR?m&)MMZlWY zFa2PTUlBT>DY-U|wd{_8nYVC&j3lj#Nn2LZ7V0C3f$5ehiJd~7DV=_{mI71RXeu6Z zO^#ESsYld%${x@uLwu0|9QnVq_dfkc*R^2dkUMZdNPQF&cbD#$o)`Ip27gKw+3U6{%G9-Zo7>cG4=-Ag2lFn3t4Q!K^cr+$gra3`9U7BdRLvpfa)~yxO@N*j0)zl>nRP%hHm1+pe zGXd{R1>zutdQT$y6yoaT;L*+fyej;WgbT4g>ZFAz4J5`Bx0+VGoS-}KCHIxvL&UyH z?s1I(-FO?1XG`1+%b^%BH&C~EqrNG^Y1DX&+(vyNu?WkbiB#x(0U&u^s<4p?XBSax z;C0G!in>naQN@%!eQZcOGi^d1?;-Tny{Bf<$R1fDX7#BkdT4aAklG zgTgXzoY)ioH1%-wQU)M{x5V6Fo-v=8%4{xcXw71~!*^xPNN7Nz^A`x9uCqIZ6YND{ zh)~2DI8z<2Ip@p0UgR0XP2i%qm^cm;p5Duy;I49=R@)v!wsKK50;G+Vd)n+H7a z@au=2qgBL?cqd79#S`{$x_h2Ku1^T)W#020G`*UnRD?6 z35Bns>{W9=8A;o_D63_xW?l_%@UZxpd{KTNzm?l7)o~XExWgJVOwqS0NlM^nKX=5V zg}qXl)LSyCr7o(My5l2yH|_c!_~By_2cIcl99m`cww(0K>AR^mr@AdLS)H~#Tk3=} z*hc3ID)f85QGcj2g1VXh4(jXTs`+T(SKr*B{fS?IRn6bz7lwNdWD#*MW(wHkkU-zpC)AEc?cIU*rD)!S#uM>YYoBo%vEJ}x9}0Uc!mk@1)WX{ zqk!kBxM?akpNr?PSDC1N-r~yrSL?ghN}!lS{FKx6&1nct8^Qw}Of}%$!EZ88{v_Bd336+(i|9^^W5pR_b4V0G{nLn! zV!rjx>Ex8z=WM>17JBgK>H5JCKc@FjkS<-3y0og7H=r3&jP@_!R|B0b_fR&;c39oK zTHeo#ZRk+YRdK>wDIMU~p!ZMXS_M9P@A_sbsDFM}GN<=Gj~Zwf^&lh)=oF$+g$U~a zmZ?jfcdPZ8%PQ)hKm#*I3@|MW3UXHX89H_(IHTs%j^`kO$nu=<`sEJBCIu`}?# z6kzb_R2hjHDD0p3V?6rAT_1!_LBf(9QCUT(eMS&Zo7#LasB^;?L4BzQct{*qHA27e z?~RMLfa5Vs1NEpuy?dI_@>rxCC~SdcUgE$|@KHnXP&a%p#j$Is9jw)Z)!Qea9qAKy z+nY(+k47x_dwa7N(us809@_aQQNXTFHjNHr7wVTpqPGD+4vS&T6z1`Xf5P9To{0wQ znf=Tuc>2$SyFau$wtvocWU*u6N3s?sAa*ENz^-N=v#G)*_8vUGYpl5z*OWtHlPB(a zBSDlA-6m=jUO3KO<{okVR@=_A-#Ji&C-@8X-O^BkEQ*^3D|mr-{Ps4a-jzN0=&eY;xN&OvI5k~UK>Q+e4FWC@8UaA z6KhFUNEC2LznoEj6|sW|k}lLAQvl{l?})8ZvXm*^mU^{nk_U!1YgufN>&VSzU%9V5 zN;aX@@jzv#jG6NqdcP|MEvftR8+i=X3qA$fDgL-MN7F5dh}Yk&S39#_-R#xby)U8S zR@PHZgSdA@6tHXPF8NDK)d}gVokVrH1a7GX>KC<&HgCib)AFFvE^u}H-%6II*)PQJ zYgn);Ak4+{f?N{^X8ead4O7djRZhI_X+72d!X?jP5+<`*_AvJx6E=jCLs__|G+l>quudwswQQJ#aUt#hlbkF zq2LG{|F=*F;qQNoLeswyMIEl(8JEZxKvL65osI$ z$1*b*@Zv;9_~+CM(YByki!G@39ovn?q;PN|Yk7hV9r}VjEr6TsQ+Rntm#;P)Li0qQ zyX!uU(}O6S3$GTT`c=RMt+t(K!_?VoOWt9)XBrsDpH=npwU=-B?NbtHT~e0v-||(V z9B~n&1gs=U{d6`Hlxc?qN$|uQip6qe(OI$Xl)H#}`HB^NvpxJe=r{d)V!wLVK8vMB zse!cgT*c4;T`{O~j+PvTPb^p{fe?O=gv!@rDWFxWypU$Vqqv&<-|}T#Di2i-$(UPS zGw;vEn*@N+$2WukIRAH6`oS;2qR;K6pk_P&nF7p<0``S|lb3#O}9 zH9>V4zS#-Q|BqCF>X)MyJAyGK22F6WXyDiUk8WSfaYMd_jWG=mYwf9%k3lCGmN|<0 z6Su-o0F^J3j;*_T*GDg3G5$nal&s%dKQ=Y|bj6^B2Dm`%e08J8JHl4JKriw{+#1W} zm`xQ#_YI`=S5oR(xIME81y-@UsWkWrpy?l#FZ*Wn)w}KW@->@& zz4t~=BE5%B@9)bL^!^v$I)SNJcKD@d3_N3Pve2G6__R{2%V0cqm4pHFB9tP4U@4zc zFNJHV)|}{yiZ(bk3O+gmO$K#X^9uhfH1cTdv5R&&nb}(sa%5E3Dm`ct3)>hJyU$UD zzlGXRk?6^lbmxX}H5}KYZL4_}r$$Pw~4f{?Uw*-sq2 zudQ-Q4pc^qKv%x+68{k|i4Vnh;{GAdH>)H&)JUr~}toAwP2c8M=vX%?lyJ+StD7u>2mf$h%@N3736bU+(5 z$2q>#J<474tk}3l%o*IDg@(q$;Ngy0_1-rc?&N`}0-pl>YNfv{oLIDhaI4eqq$9+) z{ttU!0$62nwLLfcO76ZumJ5U=L_!wA5^4*g;Fbs?#igwzNDypT3PC}sptTSc1W~M# zAa$vt6@wOw6hsV&)QzAJtfd&&2Ez9dQ9uN8|L4iQGa0S~f)Eq({lVkRbLL&n%$b>Y z&Uw!}cSN#%(b16m4=i3g=+XxVe)=JQWOmKa&%d$HAL8-;Qq%iiE|{|B*FCETX1nV) zbO|5mp4-2x`J!&qU$H=@fL3NJj(P6d5$44CKqHQaXvQ=yz z9@P5*4>z6Lcmyv!u$0yrOTOuuU0tP6g- zz#AYccBH>q;vDwjJqe@Zw@&g5+A7iq{Ka$4fWiT{4cIZ@+My5q$*}$LNA``b-OBL$ z&z21tD&l5k4ZUdA)=6IH%Hu=7UzyvXV4QbbfeRBt_J2Jzb^r0@J2<-@`}wE=>&D|3 zSo@S3Qt0ZschvpsAOGX3QGb73d^BqBsAHq**Izf=ylK>;o``{lqi@WlTd_aPl1VR2 zikKBNZ`KEI?fB2;9#49|9TJ^CxntIE%CG(8uJV|2`d5T^hCMthd_kuLX$uA{=rZt& zDt_8w>~V>^XVFuJ?)}oQNdM=8i9L6}GBg7%&@O>h=2V z!hcmvczNlv{{5UkGt9Z9AH1z^E&JCpW9_ob%ik$ChE>IeO#fi>0FhTds{Gi1wdK!! za`UYBKKa!rfBsMT{&K_Xme*J2TJ~%i>}d#aMSSZ;zj<%yCqu`-9yqGTxbv~s!~Xg@ zqR@McTlPnak$lj*xd2_spY{}=Rv%2PIq>4v4O_jxSmKWTq~|9C@sfAUCxO+~ zYkG?n0d$o!!XR}2?wD^r5djGcW4iDE+5Wu!qxP>HT7i%?Y^?Xj{)p?3S`A+ujuJ7# zhTkU;MGqy2KY5CTsD4%8m!`!K@$P~!!)^P!8AMKP-2lwIBKH-G;m+=cT2WG4cS(ZS z_o8KhVS1`TOslP{|N4`}!{LVi=_@XbyYs@p3;z*r=ziH{;&|$XfkDF}424tn8^j;( zy)bZ0K=dp_%~6ARe)@%ho?m|$V^~y-4HEu-!LNga$#B`9_Xmhs7hM?m?$Iu@#9N;R zh`41%L7rvdhA(CZilN8fKK4ywf3pGmKw97}!cD)}C>9*g-4Ys98E2@?+iwxM#e2UF z62Tr3B0@!&2;VOvMC6gWXwktSJk^0h44G0`=oxm&5HW1h)MC#yH%%Eox!67I^(o^g z78g#b`NrT05+P;clE7;``)3;rB3vx-L}rJL5e9+4`|AP%lJUR&b(e~ZvUho|jKQx1 zj|w{ya8uasVXxt_h~b5vsgsJP z6_1}Z(Ifg~WQ>_SUU-HT++29g_}dF(`x=&H4llfULFUQ<6&D^&F@AM$Sb;%Y>nR-n zNufJ;{6x?ALR`Us{THWIyMR-V( zK^zs=hl>&8ClpSdV+y-;%Anx>fg>VQgT{FbBJY>i^~}ulWQy?<4dT}E$EOB}!Yigt zm@GWKGVo)|1!D@=OuRq@3z0kN`)|at#Ud)u-OoL_xaYT~uuu^kDsCEATzKhCzZG%f z-QZawC&SZH%4I&m=iE)R?(!JehbCe+~41M!Sy>V7u{MoaoT%@C0)f8zwi1~^7Z21V(jm` zUOdSvCKY+6UNrUciIb-lFP*xv+wj7v_quo3Ce6BS=)_B=Oq#sI`2NF=KH|;ayK4fn zbB>Aw;k|oj2@&{NRal?S#?Bcv0e$+4@$s3x!;Pt#y)&~s0rek+^h0;aG>G(J<0lth zAPUE1&J0N0VXO)4`+2~_&a5$+H9_xXKinrr)Qa1K`t`kDypUOgUx3T#leyG*taHXp zLsmu~k(s@_Dy&zA*tsn`v-h-KwSD>?>5dz0>U*?LFL(c5nZgo;1F*M!vB8#;weDww zs{3Z))m4|A%nwDcw9Efj3>tq$wpe=A_$zvgU!@HUvh=PG4V*e-;!W;hlRk2Z|7PsY z=_6KM*-so?GX9Fbp#iy*Zo6#K_?yRNev=`3{wF6gJL8+&%+P@EE*&}WKN(-tUQ{zM zYo6)bD|?HG{{$bpypQNO_=dhBE_Lt?{Y3x4!)k^UWZcoScU4&L3~|HYVd)nS%Wykw zQ;&3y%Xspht1rH%b4{l0hHT5PdcT={>6N_?4E*D;alPGBmlb39O#Q>~nE@G>XZ~!^ zt0OWW?t9U&kgtLcXJzzCDY#$Hn!JVF?HJ5Y%y!v*xo-A^QVpNBbIc}Pq{XySNZ6gOS8o@ z)AGmN+@;K9_;CFHio3`5ODRYh8I#>heB3>M`#4j^XSaM2hyV5I@w=KKeKW-!j?kp* z(5OjylgGY_8@yzEbwn@m7ZFu6NmIc>sK~Cr|hf5^;ueM-%x(fN6kw~xy_n9fg-{sJX1)mHllt`%;a^?eFS|$COZ|F07<;cNLnP*v z?#CX6i>ABBG~x@KVLlNM2v_fX(pdZsSy^yIGF_V*TH5qoF!6Hal_ zpRcTvx?;7zJaZyxBPO!M>xlGr>tDjwA-27}^i3ra4 z>hkUbuYUH8f!{wXE-JonK|dk(UG(Q+OCDSJU0Jtv{~0ENBKxoV`E1L~yuWpQCbMrp z;m-TpWtOMs86R8Nqu{mv3xA%svUqz|T*mK~{=JWwv-Fkkt7boz_tNFRbf?@lD}9nX zFYlM#KP`Cw&6md)k9+rTp#dXuYX`Y4h8bVy5B}Y>z=EPOQ@Hr{<*)NU3SE?uP#7SF z4*%?L)qOV`mIa85uDZnXtH%}&xhSfBmGi;D8!|Rr@Z`_0eskU8*_XUAqF{89AzvK7 zdhmwJ(=JB;yQ}c6ztya)d};byAHVd+3h}Q&gEu^SgFEHDm#>bxwwGA3X2YXvHr%yl z!{TXcHjH1hVbq!pufBm_liiTBW<&Qi8@jI9VBNcBL*$wbV$FuHBYXW-R3F^%{=p3u z2RHov`GXtq-{ONC?moC-0&>?M+%WjyhRlN-+>KT>K0W6+TdDo1}2{S5x1#snz%Ad`sOr25LY4426s2P=FM&-9* z5c0pTRqlMP@~zh@S3mz+4k;-L9Dix4X&OFaP#2mUk|PxKDhc~ zfWCvPFBn`MKe*bAqw9lviT|Bnz5Dt3)m!IRSInhWq$Q&fZ_A2 z2hFd}nqS>z@BC`>{OW-D)dzx5$IrG^f3U6kjcwI0KfkT|nQhgNY^$ELt@>7gvD>Og zZmYgxTXlbc3$|4!Y^yeIs}5Pet@``GUShAU?vv+jbsyU5Hrwjf*y_pwp0d?FWUDK& z)y)E!VynB!RyWdCcLl&NY;`?tbzN+A_9eEuFk9Vs0rtAWx^2%F*1c9(_d;P^Sz+CM z0Jj&`-B?&RsIV^S`@*`2!n*Gay~G#KFRpukaozgGbuTWidmP|_#dUWruA92J?zaFV z7uOA1T$j1HuFEZp>pCv3i&9CiGXJqIF0pa{O+!`=BuClBm83mdSS@68xk zTX)zX0uJKHU~wB(jNjBnim3m7`(l(KQuOR3oYA76K?E0l`hCbQc;ekL_~ouco`GVJ z$i1Ro^o@Vdl8057ryfg{AS@6)Mo}d^p6M$W1Q1Oct}n-5&7=agRV~ z=P&LzI>d$I=N~5YOFwqlZcnZfZ;MLAekCOJdM9RfdTq=@Mwk`Xh!J9x80it$itEJn z;#V8RZ`Pz1Bf|aR3nGN4pFm)?NE4p-!~k)LxKwy97gvZY#Z|&K%#wBWvx&dlnw~x2 z!fa2p$Pq44C_ER7zG5t%bDn2KPmwM%#jGsxJAqGsgWa=k7URVfaeLPRGfM_6%#IR$ z#7%!P9v?X0m@9sUW%J=*h-bzdH;FgJsEb5zG5U|j4hQSD4Z01lbHB)rcq2hPUiWy+ zd+86Qe|abZKa}M8yI3vei&ur`A7ZUoEFKXFe-cIFhM1wnL(_-u-E$yvP4>I5XKxkn zM7){ZarL0Lt{*aU=)Z+k|Jjcv8#|PYKU*u|ZUb=kXL2Z-{YXg_!lC zC>JZmOK%N5)??IA`*?A$SS1cWCe}>NxLQ0YJP(UUMX4wgzrS-@#tmYQ`0HBZcaw+y zepJb&CUJ`>IVxVcIpYDbNIdj?=Zq!evz``n#S7(PyV!BMviS*YBB4hlvr35;`af^<8Bj0|2{6p-m)rO z?5|7w@3&Ka8y@IJ5P}#{eq7x7ZH#e|p|itSwCuPzI48l{eYM#BsMWCJff!@>{<`Gb z#J--hEQY=n7ExDQcf8YTv88jYNZxqZg3Yk%ve4H&J$B$n+%{Rn!S@!40k?^$q4nan z8{f0oj6%G9v+4aqx#$5(1N8)@gEBywpe#@? zP&TMHs1K+ws2?Z?)F1RS(1oC%gMI-T02&Co2s8+EG3XM|V9*fIrJ&0|mxHbVT?xts z<$O$PlAGzByjR1BI1x)pRAXgX*H=yuQ@pqZfGgYE>) z0?h{1dpPbn1DyCrPQZ@$c9iw(WPIpPVd8=wM_#-HykI}xt2hu|*oOInbICvu{$^i> z|8)Qj1I2)T4dOM&fjEy8gQ7vJK;(ac$;W~e`|M(6E3hQ?{xy}4!jq2k70WqST~j!| zxNu^_G{(!5&D-Y{OojI@?V51~lMAOdl;S-8#UqVHiY5?rRTYh&Sco32A@|e<4^6{m z1~r)1KI^(ce)?zVo`JKj0bk^EFTttVa24+vu)!M)a_@acqv4u#6E*l3 zA>h=8xt2CIq!eaI;We@gVbtTUII%lc^E#JTZeTa?Pq>ylg+73Wnhh_czZ34xhPHz9 zv_V#RS2{KCLId0l`UB`5&>ul_KyyJQpnF00f$j&*1I-6L09pWA2zn5-2=ox>VbEgG zBcMNl9tAxHS^_Esm4TLm9tSN0{TcKG=tmbfxZSE0DS|J&*n3EJ~uV~IsU5u zxa`1@q2r8yeGub6`EUQq0PlrQ4Gn#jMhM_hcDaYnLAdc~c zAQK2LiPV_qK;=2N6i!6XZ{FDVpA+J6-h}a!r;eJ^DY<48`lXv3Hk2cTQ>0dzx}-e1z!1xk>YZgyO+Zz$CC<%XaP*X@i3on_8m#t8YOBOW@pYY%u_3zh4u4TQI^4I63IxNASn_W52*24QA1}GAS4HXpRQCHenu5Lgi2mg+~JG<$Ut#<(x_Ma*lAloFhgr zH)46Kmk$Ki%Ww26f55N&1;6rLe&yf$m8YVS^y^;+tlxjSU-=_`<(vJ=zwj%!LaF-o zvw-#MkM=8{?N`3iul#+#@_N7WSm;QQ`RlSB~L$!u9(A>(?LQ zSALIQ`ICO-ANZBm`IWmdAoT110$8u#M8EQRe&y@@%0KoikH9pjUq1y{zy5W8<+u8k zKjT-v$*=rdzj8AMmVW&~!2133{mK{mmA~j$zT2<-m|uAh%xC)buK?EXf4g7#qkiRE z{K~)bE4O1Yq+dT9Sik-lzw*2N%3t;?ukkkC(qs^~~IXL0|5BQa@_bcD!S006j zhAw|9uzvj;{K}{Ml`r=z-|Sa@$gkXrhn9Z*OMvzJkM=8HPw^{X z=vThMuY9*(d544(uipb$zy7cN%5V28f8MWri(mP7e&u%eiPs+jtk-XhU-`p+32|0=)oJN?Sb{K{Vhmg~AutP5qHYfpWRc&6*Z=B`(H9RK{+tK>^r zf;CzE`SKV8j>n@-t!b}CJ`wa7D)k#YleS}BSBRA7FAXiQR7Mt9;)-*5bHj z!=JnsWgQ9X0s1H88UndINM|C2c>>-LiwE-kGjb+qh>|l{YX@FKUXQY!ulnhN_15=z zCVhx?Pyn74)K8MJ-m%qG?~wItE&b#}7Bl4A1Nr(RHA6m#iF~~y$9Tw*ZQSqZX{>c5 z8TUBikvf4b;G0oyF$O!G#wcgJ(dbMvnw>q7W&`Jd&+}#7PNh?MOiT5>EvU@rs9QZ! z7wX2ox5f0iqaJO)#pH4_FJ(BDoUPIKIDRrfM=@?DW8fFU&iOgkYLF9SDaTe2O)55f zB1t*6lhs3?OW4LKI2Y#G2{!TBw7vhFrjOaC+LQboz#C zZi5r+HaM|vgA?mEII(Vn6YDlOv2KGC>oz#CZi5r+HaM|vgA?mEII(Vn6YDlOv2KGC z>oz#CZi5r+HaM|vgA?mEII(Vn6YDlOv2KGC>oz#CZi5r+HaM|vgA?mEII(Vn6YDlO zv2KGC>oz#CZi5r+HaM|vgA?mEII(Vn6YDlOv2KGC>oz#CZi5r+HaM|vgA?mEII(Vn z6YDlOv2KGC>oz#CZi5r+HaM|vgA?mEII(Vn6YDlOv2KGC>oz#CZi5r+HaM|vgA?mE zII(Vn6YDlOv2KGC>oz#CZi5r+HaM|vgA?mEII(Vn6YDlOv2KGC>oz#CZi5r+HaM|v zgA?mEII(Vn6YDlOv2KGC>oz#CZi5r+HaM|vgA?mEII(Vn6YDlOv2KGC>oz#CZi5r+ zHaM|vgA?mEII(Vn6YDlOv2KGC>oz#CZi5r+HaM|vgA?mEII(Vn6YDlOv2KGC>oz#C zZi5r+HaM|vgA?mEII(Vn6YDlOv2KGC>oz#CZi5r+HaM|vgA?mEII(Vn6YDlOv2KGC z>oz#CZi5r+HaM|vgA?mEII(Vn6YDlOv2KGC>oz#CZi5r+HaM|vgA?mEII(Vn6YDlO zv2KGC>oz#CZi5r+HaM|vgA?mEII(Vn6WiU5HZt)LV10cw#;;tr!Fl}4e&xCi&T`!b zC)RCnV%-KO)@^WN-3BLa%Qm=NXMYbHf%I?KsME3D#yS;tL$P_Mg#?SC;a{=28~9v9 za~&(!)2CWzpXpkc*TPc2!5@aC;SVmqhI{Jo!FU}1{MX>*>vf{-z&h<$b*e>uNX2H> zuijL9-qq>9zBc(MM14qkR@SH9w6Rs{bn;jM z&JbFxz&<=n@!tPz=9AZb^_RYgdQ*;Vr-ih!q3*=zn@)SfuR@*v&F5dKH2xv%p@)t(cr<*)1kS?JTN zgk1FLg+OOspI&9dyuZa1V%cJOSwCX`p4^m%@|ej0*%%RkvRdb^&Bek!jU+(f@4Umm01+h3=AR&XBS zv(l^6jn=K&^RcybD(8{qkc;!kZlvCMWO>6gY>R2Pb&F~FNuT5GNk3elam+R9hhwgB z{nA?c$wvo2`ItNXm^$5Juk+wDcCAL0Qebt>o4ozc{3qwR1io%%l$&zHG|?^s#y zRHQaMPdV2lVLnbWn$$D&RP~m9;%wf9oor5~9i9*3J61kF_>NURKaz~KmY&8vmTcpf zmK;1c`a|9vJV&yPTfpB0*()sZNS(kI@XaW<;5a9akH>jDU&`Gc`!d&{_h4?CY{&Z) zq||Axxx`dtFEPn_x0X)%{3wK66ChV9(x;H}`B7+}U@C=th4!aF6O^3oSw9Ung3nH% ze&~T|j(*P9xrY7nudowY@9xmOw_ldquu`?R=X!IFjmF%{^<3i|Yl_=yYW+D@uICQH zrs8_82jujw=MKS+GR18%^#C1;mHIi8@kss3KY6~s=4JW0vc};M7l!ZEAdut$B9)`MT~3K%KevV!fqbItQz+5NqrE2-z=p;#oz% zbTs6Ye(7jy2;Ownnxn0ippbTLud!eLH|mG_fsUf&e0i#8!TH)RWxcVhpV*K3d&gsK z)b`9DS8tv#|75$h)OvG+8?i{3@5{PiR|@D4^QEY8=h&8XA(a^`+@v#qpC{!$8-I#_ zT!a36g`6jS?vj6|{fO6PmC=l)?v71$dK@yb9*0b<#~~Bz zamd7a95S&UhfJ);ArtFy$i#XaGO-?qOsvNt6YFuv#CjYuu^xv^tj8e}>v71$dK@yb z9*0b<#~~Bzamd7a95S&UhfJ);ArtFy$i#XaGO-?qOsvNt6YFuv#CjYuu^xv^tj8e} z>v71$dK@yb9*0b<#~~Bzamd7a95S&UhfJ);ArtFy$i#XaGO-?qOsvNt6YFuv#CjYu zu^xv^tj8e}>v71$dK@yb9*0b<#~~Bzamd7a95S&UhfJ);ArtFy$i#XaGO-?qOsvNt z6YFuv#CjYuu^xv^tj8e}>v71$dK@yb9*0b<#~~Bzamd7a95S&UhfJ);ArtFy$i#Xa zGO-?qOsvNt6YFuv#CjYuu^xv^tj8e}>v71$dK@yb9*0b<#~~Bzamd7a95S&UhfJ); zArtFy$ize3C$6Q&0PD|>hyBW5_AA%pka;~l4w+bwLnhYakcss;WMVxInYb;-Agybb&+%5Dvg zud+tQZ?hWX-?5tFHzHjN{0jIhQC{Az_n+UOy7^ZeOzoV4VaW1Jwz zoQxBk=U#5DfPC}ZyFu+cPLQzd#>W2{jsVW7<+hdK<+d`TZ2M5m`7%#Eq~I91 zLWTcx0gsjjeskx0p0EGOd&oI4ABClms|@mOMEWLDj=6H%o8hZ%8^hPzUJtLZy&Ap| z@>bZM1AY?x$0>XGvq+x+E(5<5<@m8i;Mc+5i1IhX<-LMWQJ?emImdS?@*R>Kb9{dk zVr?5^j_*=9=J+l}j=5;-?uPGdqOHrV%r{3r@|d%k8(PB;JtgBrKQyuKhbGqj(8RhQ znppQk6YG9xV%-l-toxyfbw4z*?uRDU{m{g^ADUSALlf(MXky(DO|1K&iFH3TvF?W^ z*8R}Lx*wWY_d^rwerRId4^6E5p^0@rG_mf7Cf5DX#JV4vSocE{>wair-49Ky`=N<- zKQyuKhbGqj(8RhQnppQk6YG9xV%-l-toxyfbw4z*?uRDU{m{g^ADUSALlf(MXkvYj z3u4{3OsxBsiFMyHvF=+Y)_u#wx^J0S_bn6azGY(Fw@j@2mWg%WGO_MkCf0q+#JX>p zSobXx>%L`T-M37v`<97y-!if8TPD_h%fz~GnOOHN6YIWZV%@h)toxRUb>A|v?pr3- zeapnUZ<$#4Efed$Wn$g8OsxBsiFMyHvF=+Y)_u#wx^J0S_bn6azGY(Fw@j@2mWg%W zGO_MkCf0q+#JX>pSobXx>%L`T-M37v`<97y-!if8TPD_h%fz~GnOOHN6YIWZV%@h) ztoxRUb>A|v?pr3-eapnUZ<$#4Efed$Wn$g8OsxBsiFMyHvF=+Y)_u#wx^J0S_bn6a zzGY(Fw@j@2mWg%WGO_MkCf0q+#JX>pSobXx>%L`T-M37v`<97y-!if8TPD_h%fz~G znOOHN6YIWZV%@h)toxRUb>A|v?pr3-eapnUZ<$#4Efed$Wn$g8OsxBsiHEoweapmS zfTeGl_+h{Dm;K5=^DEbV%RFEAEfed$Wn$g8OsxBsiQBSonf@b)D5Buk>wx&;+Y<47 z#z)|=ZG^FFm1}Au$?Pz8B~`iPx*6rlmeYM{{x;tEY6oR^#yo=d__7PuGe}v-ew|Ak zpLQux`vSI>ZA*XO$B=6R`y7ITX&qhDZiWPXl z8!G_u8vf37e}U8WH`Yxa!@5a70`u2`(4EDlXfVcNMWuOT(5TBRd*s-{(i-EJT2q$> z$i+2PU!)_DQkRCbcw1k{XGj|Xia+Td1LsngxMjm%Yw3sa{6nE9#&AmgT-l>>ua;Bk z=WP0LYu0-`_S60~8l3UeW011m6&>?kMX~v6o;_8)WxqcgABL>IycYYEe5b%~7zRTw z##7&cl>M?WcCf1y@)gG30UE62+IMUK`z2#H7)LH+H@0W4jH$_Jo_@~Pd8iWg z<#z)o)|>J3?YrLmovuG(Z|@6`%I{f{gYJz?4r*R3$oZ;o)|)XfM?>^_*P0K9G_T(B zncPzAp|2qqV_=f;@RKnxUx!qhlS6CGUx$QPn3poN$Mq1`=={Bcuk3g>`hKqfyAL`( zvp4SPf2wtXY@3$S&o0QtJ^jrfxu^dw`{xd`qu#O0?s76OWjGW4a2+83hXFt5B-h(+W1;73FFI*IIivHm{qmv>?wNd@UNjsyZ9C|${hvc)3 z_4Rmb%n8!B^crr?as3k38T=NQb$TOdr)5Plsn+~P5~(pxr!Ch>wr^81k}r?Z`v~*& zM^GozfJKXAPk3jH_q5gf7*I1^YP2~Bf8cVII&p*K)PlxHoCB{lj!|1ap%345OUWP5n^nPW4>#oBVwCT(4xe13Ai$fgvEQ z-2sIq*c0h#AWNhrnB<9+^+0*Metuqo3jPP}u>~pHgZjJ*^}jdx)5uL)JG9mHP;Y$n z&u+DCr_ z-@s(p)c-~**LeKhznu+KZ07I(5zBh8O2L9muhwnHrs_k!taDSk zzXNTy3+vYnQd64wtT)EV~L+&J&QQtUCufB!f3h?nb! zv1kXbAJ`t=^~2maQ`{|axo8#HAKI!u8F%$3_%0b|#Mn>j)9fgAnjP3N7T(noM;h|~ zclLJVK67jn`kC!WIqs8;X0(J^`EO69OR4WL%mtVt&-r&n+&l0%WaFOANstdN0_4s3 zUEB!#E^Z)x7uRD?G9I_bBXt5>z&E4ZVsznma^3j7+(i6tZW4}5#PM#N=W_6TDL3@5 z=4#GilF$0+`Ey;j9=I2M=!Ze{p{Icu^Rdf*7%gvx4?PWZSnXwdDmh!#KMDEShZ_10 z8VPb@FJ}C52DD;!OaQG$zHu*Ny&n2AhV9Myg=-D!p*89x_1%<=VYMF9 z+rfWqoUi)%E9?w@b4UHiZ|=%FZL}7}wvBJ@s2_fFNBzie?h0dv_cS69~DoAXg63aY#9S0y||{b0A+}r*WXH zW_=TRzK);E5J$;aJ?clskLGsFv4wYPw0~M#KaB6Ceq?-aV5fNa5OQpRokoD#cYH73 z{dUGPnQL3QFFsbYc0_fkwZy6PbH4V=$*3>qb^m%7JDWGJpRe`icN3&x7?<+fiQJAQ z4*rvCiT0>(IS={Qn{&~RsW+c9@=uJNYl-oJYau`4RTH8HzrOb(Yu@ zpJ%N~AQf2l#FHAIcPLkDW6B}rYcFf&U!ff??||Q1KzbqCg>@X2kk?^ULceCkXXx#5 zuI;pbkmVA{bphn!w{!(aF`gh_f#s5f3oOGE(k-JBGA$F3-VRK@ltaMP7<(!=%G@4x z#rS&0n(()q8uyGTGZxuff6tf(TNHBLMOzf!@c#WAGx<) zs%xDkAM&NT4uIPC-g?x}V~9tl9n+|vr4iJTZ2MEK=jAaiF@Ewf-{nKD63ADA^d+Qt z#EN3)OA#}jx~{~9sZ`E*2yb1Blrzz=|bA7n3yC_*|GxB&colo#N*u{gd6=ka_g zcd)kBZ7*vk#_@B_#5n%{1##Z5hflcPu~+?uSZnHZ59H(TyqX~!e_NS4t#>4uf}Pz= zQBJqX=o89b8vm2e+_9$mRd$6-V zc8J?g*V+Z?p( z>!8Llz1O+c+4^IeYwJ~zYb$6kC>Z^dYwK0ct&nc7bComL#e93#5636pB~U+&&zmhxlOK=vu1P4GQl1%jNY zPj1JGj-+DrG*WIyDTiK<_GtTXUu62Axi7MerSR^H+!$}rs?T}I_rraWPrvW+>Gn-N znSR^L+Kv7$+W6d?NbValH!k1xX_vOKZwU7$;=Uo=n@H{(@^P2JE@Rhx*T-G%0JYtH zLq=l0pbw>2ns?m1gmf9^ZO$Wo(@O1q(>7XHq(#_Pr2P{4QuY3-z0V`uLy6BX?x7^# z;a%CIn>{S8dGGM#cx;KaC7)f~Ln#9CaSx?|NV&E!q(wkS-Ry?6fuM+!>Z-lW2~t1Y zLy2}epJi9}D0Wguvh7bb&$q_A#*vVbV~w%te1Ff_boMQdwWI0X>@^vr9NW=!Qe!>Z z^H@tk-5X-l(GHAFXL~T7wJ+KNvFY{|NZYDDrCd$vhkSXAzW!tWT2LbBIgDSvBj8>% zau1#rY2~(e(;L6HI8{HE*KetLhI`RG4EeYh&D%&h&%BxbF#0EUhEIPR^zcdj>g{Eo z;a)*;69hcvJauW z-M-`IJTnjNa68&ztFJvc&n!g!UrfBy^^VpKXQEH`2l*%4Q6K9pj|Lg#K}aFOkJ>Ba z3OBApe^O^$0M9(?GuK`3=+~KKcI3KAjeC={WqrzLVOKOZzw3DdDPs*;r{vH)YjS9@ zd1>fcPzdt>cj7SkT_wMDav+uSjU}?c0#bXRoT`7yKG+h^gM8?w9`74+F%Kp~zG+D5 z)3ik9S|TH_vIIpAw}{B=E%gzI(1;udJPG`%kbRn^Bht>m-M~*qeY)Ye&N#j!&g1z~ zZoSX8muJX)D2zJ&1@^irM9Mj#e|SOkgQ2ajQ`!=vA>R8Z{(w)6C)oAy(98L~(drKE`pQ^JQLN4>2!oAHKhl z<4%63<9#RFc6BN16s*kwXIk$rc!sKHyzhCy=X+8_^PUH-(TC4Py^o^NsP8(A137j* z7`yvI+PA(rXEEM~`#j2clH{PBmct>fA5X&PKlgcLybt$zl<_`ahpe+Chwj84j|V{Q zJKjg?hx?Dx_s#K4{Uir9`n%8MnZonspBy*(9LRDE`yXW!HY-*j*BdLq^$G7KZLJDC zdse`Q^D@?<_hIhEa1@)uN*pW0N#(XpVWh@y7ErF%IlPXni~suPe4USWp&jVsr>!M@ z{FcaW_UiEF`5g83IM?ewj?0yhk3RmdkV+r_SK$NgDhQMl?*3%^AT(#6gVXJkAp3*fXZ**oJce^` zOU*Uh2Z3{q+y~*S@H9LZ%#N?Z4`Z%LQ{S?kO3w3juAz_ScNoO%doz%7%qAJ9MLifg zElRfispcAaOiSs9K7bn_7kvN=k$QbJ3!_FuzDGlE04-E819RLH5F3&MU#xBG4aNwF;3$XF&5+U7&GLx7*_+Y2fqTcZ;I)O zG#fYv{QfAxo0b@J{UFQz zkn0fkfOrFG56Fl9g}f>5{-hpp3zHJ!79qbdDG>NjEcsHN_NXh)kNhTrYq2MgQdgG9 zr4bK?E>+(RwAT3R0a-Xd-VM1pKfa38J3qb}F&gqc8hSVARV8P8)enE0p88pZ)T^JB z;SYwwT0r~Yk-`3})}9`i8v;+4PWP30+q6+ml#XZv@7i}Wj;Y{@TQ;y9m5c|FZ z`g{p{&TRJSGq>ZW4&|LlJEL_2klQiuN9i&I z=gU9Y7tZxOE3ey>ZpfF%==Ww``cAmF80*cw#bmw9JLPpKifvxK<@Gs7x5RUhdy8d3 zKJG0x4k@35g|S&3@EZjk3S-BCvXp-Gc3>TK*;-@nl=s)=(w}SO%VV0-57+#1pAo4a z?lXelX;Ae(lR4&m>6d)hxdHm-H{YCJ*>3fYO&u~_jdRke>Mh%~CHiGPWZ`#;<&cZt zDSm{M_N&>sse{qEu0xdbl@7tqmpart$~zo#ywqX8k|CJHQ`+Uxo6I za9kCR{{ZK`(}Cwpx!E`PoZ*_vzc0&UTB2^W4Y=RHbEp%)Xa58#$6TuGxeobg`&8E_ zpy!$;XKRc(xn615;{wk&#&P}v{spur>eD|4dt5|Uxt4>zL4Eq4)L)>FQMR$Jht{Z* z)VJOzbQ#H)$22vM&>zJ0+t1J*jHTfDNyeSgeO-<56RkO(=nvWmx#$nthm_-~Kjh0X zRz_zV{~6uW_-1sHabt8mQYWwld^5@|#!rC10)H>c_u;s`IQ}b~_enI*m+hjr-A_55 z=ojI5T8BC{><@ty?Tq}+XzUFUo$mTFIs^H1*FS;RMU&qgnOmbD%CW`Yo1s0x-1TZaE{0A#2$ami@|A)ddvBV--~g6;`d^5ema^yH?AgwR2q9Uozyrkb^W!+`KcG$ zf%6l;7nAc-U$n)Pj9cPXAeCeARO7TY^eN?PNA7N4gd1ud!yQey5}s zSf-?2r{2$=s^0SYEipgkLzWvM7rzgfgH(PWFeP=G<@VI6mf5M3EPqTLXPEaSON z3y@Mj!@6JZoCEoWbzcCwzRm8pBIkPUyWS_<8~?)hIOy*p&)OeR82!VaMda6N>&kFq z*_J3*0!(>ZCAcKWSz{8q=+h4Qbdt!X~ay&(g@=7p-!ihk@}FwG&P5F z99@Ay!0$4rW06R`VH}zFBwiIJ&uz^)dz-iwsB>z>4X^QVcU%^xR@HCH80 zFzeIT9fNPAW70>5%6hk^PLKA4&l$15T_N8_q||9ldZ{fmz077vf5LXW=d-q>JXlKw346X2JjytG|^`@Jp;YpW2%^B|Qv-H=so+mLl@ zNL$e93y_OC-Huf1bVF9D?bWO@+sj!`*j8jcYkL9muE<&qydL}t$iC6G1?l_1AA-Lf z_i_9doX7KJ-P+?gWn8VCdxv8V_RhUmA-cACbMN^&KXH!fuzCF)Fay;_6BK5a`iDP^ zl==3oANic%_ZLz>d`6Vo+lGE-LoVv)??|P7{%#KnFSYj%pN*9H_N*WN-VWz={@%_} zv;*h26349}C62?Y-mNvi2TmY@N-d~hvSCh`0H>U z&u@-SIl4cT*FxyX zkNO6l_ta%+N=EWec5ljYEr{}S|FJr>2lpRidob=f8Er8-^jrH8-`4wCd(ry`XorU1t8{C>SLrTsR3$X-{m>r!J7YljE-D-Km*1Bk zk255BFl@*qa((5B)UmX?d!CDX-s>`uQC4 zQ9mxoN4uwc!sm`rkgt1!%gMZyf%TPh24SL$_mino1Q%ACXr_#^) zTJNat-k2LJ(x0(!LZ8O&eG`n`o3{^%Y@3$om;E5iL3A|E9Tz}8_D$#j@{LM3n9@BV zpnFfqnUN5W^n&i)ksp;Husc!z&pUNLir9HSBc}_#(6wn%H3N1mCxp9QKx#${r^Fl?VJ0bb!R&( zu;223kTTyKIa{Oe$#pQ}-1(c`jC21vzLP_HVn2hNPAig0xgFm~BIR^CSv}g@IvCSW zL!7$MgI|63+)d)42D>vyh8>Z~O--WI?{79{bdvg0D; z7bd*|{4Dxxqs)4nw3l@kbw$75W~92VIQL6EoJv>cYaive80@2rb(Zy>l3LMmMRKFQ z+he^M<9$E$?O*RHsSBE=Z`mhWVr=qR$T(1aVmB+M1-S}Jx zN1bTv3_vPvoy3$;3E{AH>?u7H5>qk~GLa4dCSS^PDw$hjew1r6&T;fl-UmB~{z=Fw zRwR!~m;*a)K=-PIZ&h)jn1j@X6GG9?*^U&ehJFw;JCYS{2e%t=gW4{+pfK=FQrazLM7!s z$kgYkZq3taYxHF~e;(bhz#V~zUZzSj5o>1R$?>^$BK{j}y-+XewUKzBnS1mlXKAF-p`M(d7l zX492Pe+KnNexp^^1LbN=wa2l>@3{EefX}1C^0&J7BoDD;kwB}e_2Dyenz8y$s zBIQ_H)@_Jo2jpAUZ6;_)v%ahK?{hbVApRvJMm!&NZQhWJIWimLJ|d7WiE3aq#0ub0 z^#?K3{CcMEPuYL?=ka(NQh6=CUj;YO-^iE8H@U8XF8Moj|H6Uto4l#`hHXc;V)fnH zsdVYzM(0bte}($;n^XPS&*%QAZjHaW*B1*roqdj@|o{hFIQ!eD^2K1pTzf+B$^R?cLA>y|?dcBXwvEHr!d(HXK z%O1$bZ$eG5f8{r!rucH3G5%RwWc(Ah;P^7z@wigk!MHNp{d*hz9?ScGz<5mN& z2fqU48*y9(j$e=SR@->K)M>ExjBPJ{nR5+oNX|9$kb38u64Nu?N|Y^fs=h4SrX}Z^ z36P6(%~MFdbIkBx+f$$kO3vVRs-H)V-ZhG@pHbb)jI!-drJwV4u3^7qy%~4( zXQb?x#_nat_FiwsTgiIMwHafrSoh}W8(Vw|Jdzv!&}X`5YTXrAt3hs;|*`2kKt^u72-Y4;Nx;OJa+ogElD_&}p_bS$a%X~RYz;wlXMDaE&-WQ5zjh5$T`Er(k(TX=)@m4C{`-)eu zc(EO1J#u|HYrrjvw?y$?RlFL-3yG2E_VMMc0V5Re9>sf7@jg(zI>mDvWj%i3%UJ>@ zD&9QBTc>y*D_(?2o}1#!Spu$8yjvCT8O7VAc;70X*(~cZ$d|JQ^`*N0ms}!$D z@yZnMABwkE@xtt~4f^?V)_{?UH%IZFR=n+scR=yFV3%T!C~Lq#U(OORS@9lFy!DE= zOYx$xgR%GARA0^#aD(DaSG?tlw^{KHDV`Pk4134)CBB?BV6@^bQoNOlSFL#Uiq{jn z*L!8*KK9=0%~ZT4iubnS)hM15yWo4z?c>W?0>&!dJ&LzV@jg(z0Q?Go_guFxX9*al zcoP-xam8Dwc>5GD0>2^PmASt!XAQVc@k$i$8O5toyl)jRF<#0t$d|JOOi{drinl@W zb}L?o1bJ=`U(OQnYsI@=@t#+_EsFP@;@RD@9z%RNYrq)Adsy*aR=m#?Pjr^&X83Z} zfU6YmPQ@!zycdy^&ka6X_~(6Y1o~1h=5t0KCoTLFpD(9-iUq0X6wj+OoQTtW&#?gC zeYyn(h^3(gmP-5*V^i{Y`KNk{HdM!VUqgduFflMl{4;Wh#e?hqGjb+qi0}IT&r|V} z*Eh*n@7QXpcbu#Ga#flbXu_`0^^P3lAxE}xzoVzI){$h~~tEV zobg7Z6TgV)?1?lRI0t;5@0IC?ZS-Sxu*LMbqaJnLVsbf|Z|eGI+vm7aOAHJap2!?q zK{Tn@?1?1h*iO8s?2nE8{q%J^ag}!B_0D`E|a_m6z>Ja+ogElD_&}pyzgbc9M@%%_lV+cR=h71&l)X{%kt&8E|a|3inmhn z-dDVO#f!zS!Fbys*O%kEO!Af}-m8jNqj(`P^0+>}9M@%%caP#dsdyhKUY+8(jove? z0l)C&xGs~td5X7A@jh0(2$MW6#h2r{O!973yk`_|lj41=cxJQr3`@WuUykcC$y=y+ zFDl+{#XF{WJuLFRSNL*Vmr35Einm4azEV89RUVh^%W+*Md3P(`%ZgX2c)})+i}&TY zE|a_>#Vb?1e<J_hNM|s~| zU(OORQ}LE4-rI^-qj=6v^4vbY9M@%%caP$&QoIioFCbPP=l12eE|a{8iubtUty8>x ziWh<3Ta@cEdG2+JSK`ZA1D;X5D#iO&@eJ9quO9QP&V*m&Q1Q~7Dvoo9RRlk3#mw@+qgnKAaZs`2;3`Nn&_ zGq*aXym zz}-x{ElC*v-Ar47w}8J1>&reN=fktFZ)2Z0z0Ob9XWB{|?Tls{$!Fyc+vumBGx1AcmLyny=Xx9`8EY*) zje9KF#xE^77{B;ME~Hz5w}8J1_pGqQBXt5>z{f9oA>9r9CHQ+#UfX8Iajm(;RAetP zovSvID4VM9Pu)jr&E>XQb2ocik%!}DEBqWy z$>Zh!n03Y>JnKzyTTDGbhhn|gX}Uk0{W_!ASzsZRz=ugHcAj`oxejRbCH~a9FMv0v z2sZe+ZtKF>L$Rf}ZeeT>(CORyr&=?3=i`+z=c>N)8QPrr_H^_0iG8E>=BFg%%9x_q zbJs>{K8{@+Q;O>r#=Zku?9)Nh2EUrE$`w=R<`%$F`&ksmxg6CY|2j;BBK*J^Rk> zyQaR$@?DcR$9GMV_p~o(4X9AO1Bz#il*bM9<@l~i@*YsU7Zh)o;(f1psZsL2m-%vh z*Cct5DBfnp`$F-o(ek(~UykpZByYCjtyH}C6|Y|LVmo-xumt4#a(ve$c}o=URmH1O zypR}qTpwSK@0uj<9>sf7@jg(zI>mDvy=U-UlRS5#;>}aMb&B_~;zgL`xhcLJ-!)0z zt%~=I;%!pAZxzpMmiHax%kf>4p2;eWiGI zt2{2-m*cx8$-7(eURJzH#S=DpT)Z#GcTJL4qyy=R!T=6z5-XX=ay1Zxb zU6VX_wBjvNyp@Vqt$6i{*R!KMH`kZryC%t7qIhpBUX9{8v9A$l6>C5rUykpZB<~)@ zTcvm(C|*FUJkIUQ@m-VTO;o(c6>pv5?Nhu6{DQE2*CfxqPVq{7IlgO>$5kobw~Ch- zFV7w1%kf>4v=je395;+QvZ-TRZ?0kxeq z>XI(C=J&du`!(TPT`SGUaoxANhFF+yD>g_~!cNOW?xy{Cr(XwQg2A8nxW<^SdG2+V z3S4)d`v7QNn^^5BJ=;%!#E zFBH!jEziyJm^^o);>}aMb&B_~;zgL`xhcLJ?J>!_Rq>utyiJPtt>T%@ z^1g$7Ioe~Aw@~q3RJ`4acTDkmSmb@L@a1TaN#3K1w?*;3Qarm=9+&OQ(H@h$yA|(c z#j8|2VUx$j`*O6$B(F&E$`tP(inmws!tCBNXphNrM=IVN#d})uwkzHN#p~jb=MMDc zXpc$W1B$m^@pdU*lv5s;>dVm{lf3DQw_NcyE8Zc+v%0)z&>oZLj#j)yinmhnsuizZ z@p^WY=jQryw8tcGiQ>Jjcr}XW>?DutPud%li)U*tNOlC?2%&&OOw9hAI3PGeob<6+sKdx{}`@oNE-o)_lrMk zz4uY9@0C4d?Bx&Zd$xW3OxwSrW4@~>Hs3c6ekjk6ZU4g9!LCwVw=nh&&|trD)_U!~ zA&c+Frp9~g^~3u9)a_4s`0M9wN1k$9O-9?1XGQYLn0M39y>INz^u;kpaoso5-vPB9 z-`Mudl`%CLP1pCQ?w@>jNSWG7|4a_LH!?Y>Y2V>b-9D7%a7feg{Mh;P>yS!wa%ipj z>yQu&^WN*UzK;UY`;O1-^4rKC&YwTFzPs$7JIs!H$1c0e$^7Z+d$#YZ`-kt0PKqGa zM)eOT?TkM0p67loDA%EHB<-}UNG8>q-$)`!U#ZmZxxe?x>-NKS8Fw1&78r+fI8NgG_ys!;DiPXG^z7X>65iZX9W^vow~}cIvA@AusKl zmTM3BY&)8sWUR>`^@qJdlH;M}?tOAyd+(?FU}WFy3;CvGgc(;LZRx(r{U~-eP_dc& zQV^e9-k&~>T(-w7$W#_xZT*Lmt>yY=Y3$rM@4r&SnDbxT`F>BfM-^l;#oZE@3rSnL zf0!M`PO}4Fy1>dPaik&N_P#T~UNMl)e9nBdGQOcduA5_wz@9aM*t5oCPck02$0KzD zTfjG?++uWL4;wf3vPs0AHc2=x5y!i6p3A}WPaI2)el{=vRI#=v_oMEzA4W~hu*=dw zhkf7G$hoWW`sd6Ru;VLM)ZFZt09uW_{I*Emv-NBv){%QOp*>7RvF0Y%y+5|C3u6ys zt#39J#-@P|``JL}uB}h(BeFez_Tk;}QyEmt!rz(OMY08`O4URjOQh z*6>bppMW3E{XbT}ft|9fIk;|Mr*WXHCgU*9b}XH#eseqK*up!>=kU3#Z#>poIkvz~ zBS3BE9Za#ao4qZ4BS?9QolTFgpT0koIQY-okAB!6T0ELQP5R`{bZ+9WEF=bo;#dC)ESDr)U>Tl}ZW)!3X_P zoKITsIW#xUYA!yLBNOc4U@c=)PL*Mow1We_H!3M zDdPeP?RObVaos}uYS3LRw&sxbaK0ojdQp8MWdBok$zedb;J{?hl`^ah$5t8feXOTM|lB` z8;j$Ma30V1-n;eZn|jzd^^U#1Z~V_)8`V3KOu^1>rYNV|WOQ~knVn{&5x_y_EL_&|(G4;swVAyyy5T)&H+$3m+#lPIy4lUnG&}a9 zwMRMo*|8Tb?$ghXy=?9K9clJj+!K4*B6R>;z&D}Xg5w-GJ|5@s{I=7N_Bz)(&s{%~ zbLlGQR$O(jbComL#e7?-FZ;t<=eg?>jrCpY+KcP1a()e3d)j!avt0}Cb>?=g=twF? zE0c0Np4i5%|D5)IXC!@I=WdQ_&UZwo`wr>Ewrag~*QZ_1eSF`?T?V_1UGrTZ zcew-9a`Am~-Pkv+)ZRC3qjg1Egl$FIFOe_x^F_9Pf4s6sH+xuG(|Zqj`^1_1U=3*z zsBbsBA#ETi!mr+~*SD_hQS4-$z4iLx_&Zxafz!VUFQ$=^JDwto9Pcj2l#R>{cX_0 ze)d~y_QwLmR7rou59@ob`Xj#~*wa8}2frmCKDlmwdK*^u$AysT#l$;Z?x`}ZY-t2xC-5H7qmbFh zS0cO(xCita)Wd^(w;_Ke_=rE$9M?wr?_7N|Fx0m#nRUNayrA!>XWIvR^xO# zcM)xWwq#mAXqeVlAb#`D_@>)<;W=8_XSsQ{$hJN-PI*h!`(dtalWl!Ig|AHOi^o1S z%P#U)_1f(nvT^D|{VBeNyNI*?{{a-wUMcBYvy44!srS`f*AQn*;^GMd!I*Hign<42 zc=Of}+4>@H^w{1psITvp^0I%vyJWcAb^_&IGL!=DE}G{%(wEjQieBn%uUC!^eRe+$ z0_&Me>agV)lx;tcrA%Chvi6_WI0yGTb?bm;@(`|G7kJS=t;;tTULv34e)iKHz0i-@~uJsTJRCS zBD?T5qSLBFUhVFIW^3y+D09E}4*Nl`)BYsl2feofzfwi?V$q#99w|M<9hv(bF?au9 z>yshwh0=DEJH+h+yihd1Q}V_WhC|$mxjUS+)c3rh9pw&jzW|(H@Q$cl*FOXPHu<4d z1aWb|Pr&x`YtdIu^1$odmvbJBY8-4%#o85>*6e z&FTHCaJFFkYbn&J+v6W5ct}6BVC~cPgI;f+n-i&t;%^g*pfch`^W#QHZbS@C@M;49!XYsY~JMoom zwZ4(9{n3Q?4IA*>gK5u?sJZXMUJY}AO-1o%uz+VSFh4eR( zFNOTCgYUeV_!Zf#@65MZwsm52V?ch++y-3(^4oytRLj?Dd~A~&%5a9xl#-tX{1>tt zzOeQx-1x}m3VfTwv{q*OZJA?Zwzg*Nk8cB+)>$r?)>vLO)mmOMc`Xwr2SN!r4?4aL zgz#Z#Zx(;srRN4lMv&Wa6g_}gerx&4hG zTeoM{M=5Xd^8@pRPf+Gd!8`2df=>IN5I+~Z75J4ZqNmq!e%#5o?sPZrltXKegQe3V4TzxXV+=a)7DR)fT;#YsxS*pGp{jJgf%H8Nc0BF5w=N4HXY^rF$u3dv+ z1Ut;*6(R?%CUlD(x}@{!Vh@klA*H(U0N%U7QV(9YH=cXNrtm-{@x z`r4Gc&H8tDyY+AG?beigw{;S7Qtp1>KLLFZG9R~oi0~@#YoN~{{TlLJMg9-LNBrr! z6mGsK!&#rQU^}O^jmm-vfeQ``w*-#~GqoeaC$(b;$AO;)Jqei;f{4%o{Py6uP>p)r z9vlIF4D?~7CyM6m5#8bUV*Mj}t!?yTeL{GlepvWj{V`#*enj{UQsglp`hG@^?z2^5&8l@(4((SzP^Y*kpVOz{OGyM|J8nN~XJ7ZGVnXsjt z{{XB;oIT?gzJ18%^gCLq`nkhw z?a%h+E&j0cW1rvo6@M+tuX8#OuJZd44?ELsHow=Btt_@CwD|jY$sgq%{vN*C-^sh7 zPqn`lcnj#wyu}~lOAy`ye8$(xU-Lx}b^`AKJ&JVoz1DoUN7B_MCta&GzY8Gg3dw(T zHOaqswa8dWRZw=XWO@(oJ$zJ1bNzJBTJkaL%>3;1@>Baqo9 zRUs6BmxEr0^m61AkiQCi#II(fZ0p4Or`s2H8Zd|3e6>!uug-ZV!fyg6x|*z9{f~{+ zqcvgY0M-iM^rxI3)ufz+r^_tdSk17f%*PP-_Ko#eM#4k5mG!| z@51>$ty`lG?cT{@z8`f=iCvEO#16;%V#IMp3`0)Dv0UnKtdP1K7AfkmN_!CQ13mzH z9O(ndw-5REfRFf#$3`Ao*rRSEt@_7IHP*1z@$#tqFMvwK*&3eBnT78k1J$$Te+FpX zKVGhWw|oZWzFaNi`{VBx%^g*w??5%L`kt{?Z9nOmsF?Iv%kTI83h*_=+5LIN)Am#D z2!Gted{Voy@u;VfpG3JwJ^g@2)iW}=+B$taVSOoc-OlEMD9#j2dSY|u2r~7}cYSCK z3VYc7427@H{oV-wBtYx2V86GKKZA1jd;0;!;}2x}Z9F#JZ!B}?idp+juFA=I3_H23=1>%gz&L_Sa{!l zOt@?x5vCybvV9!*Y0#5MpFqAO@}CCZxIp~rV@u)Ib74=s{5U|Z&6e(?yUQn0?orP( zfZatiKa;*;kNUm7`SwwZf7nu7^@(6FRNX$e&ix*=n81QeEgd^{Mq?elu6oy&o!dHe z^j!Hl+NRx+t}dNU4{Bqh>#I5)jd7o)-=(B{tE=bX@9JoGEY$OZZ|~gEd8h6=Mp01e z6|Q^xqOONKBi%bXKEtnP=-3{+UMkX&IYj7n?)BgAi*(i2*D2%g11(B;PxF1cI3z6x z&>xa@w*a;gqSNg~Wp(s^84A&nE%pKkr#R^w-n?o;#$zh#q>cAZY-(1zyw z@4aW!`Z=C|qI2nZ}wB7vA5Y2+L!77X5CI*6wssFpzGFcN7$>| pt&6~RMC)EqmD{2Fr=R;efByUI)#rpcbLQljb+?dDkzNao~9=U|$EFIq|;| z7K_GvoDk{s{+2^Gn`W=SG?1DWdF%kf*nyK`F*KQiZF3r+g$XfC(Bx#9jCeprKqT_A)r|LR%{g-4p)LACvDS< zod-jPY1RI*q-gRr)_W@Th#spWw)VA~FlM4OoWskmqE#oTsLCrOiw&Fy!vJ1JpM5Ox zf|9kfYGEO*hg(Ii;MRWOgsmjjFk^Ai8FbNmDr-h@%!M**0d>Zwg2q@PBXnY-9hX9Z zeh^S;!60N_Hm$R$PKi0v5i5%t&*;RoxH90_VDu%v5t(Wd1w$F_La)rEH{d9rsv3~7 zBu?9@(IQ4Fcyi5X^0JUWsn3I4o`iABPe>$ZNxaioW-K6>>><@iiDENyPpq-35KgOQ2bLQ z#@0+f@mL0wiG0SX&lFGSx3ziOq4^+Eu$afjXNUwO(MVOYFsSz;k7elsW%sVe1eUyJ z8Z%kQP6&6hON9wS(T)h(9{RKpA>_(erSQQ_(goolJDJ_q$}Pa~h0L^vosEJ*RnkUA z?p}PYHGXA30i74sW}jPCEvlje1t_AyDiAvbgWmEWMh>Ymb_o4U6qREwnCui#T4b== z>DN_BvlL?Xx65RZjug@7gOoE?K?p^gocT?k5|~-Q`*-SR$nx96X|pv>D0_fMMmLkcpur?bRUwg9%Teo z&8uZEqhFv))7y+FuXs9*x+FRcm0We3)4YO_+0QwQraZ&T z_ClaMJQClH>gB!Qbpr*9BB5jI)&sPlU)gEzh`ld?rVVdn>uyhdQpXJFDe1@{{5Yxs zXntX%t`R&CKMFM84HVZQ6$L`M1y8UY=)pnvaFC&(wS(9Q4f}CcFH}x&XxO~~`;)|a z!S!MH$Jl=8PZD0-rop=%=1;I;pa$qiw3gsU80xLW0MIG)0`5-|<|Wu8pk8Pk`l?{V z`2OL$tv|%b#};G%&LzV~eWWKsGsb!MNSSD8KifOQ`d?;6Hq-qwbkUvTe-Z!FlMtgn zNar64MWHK&BO}7d)a8d@D2%eodh%Tkol6hYdn%d~87;~rt5aA4w%!R|0wsfZz9zJR z%Lmxn6h;PI@>HKPhDu~Vqx&?H(~$vqDld+mMBm&fPm%`|4L+Xjm&zRBpCnS>@cS=v zn#ZE@@k~d`+!nF}!zZYNZPlo23=f`CHfQMyskmunLq)Mr3V@yi@t-rKl~vRz7HCCR z_=w&+l*-r%vV6PsEtztBSKvvu6-ieg9zCV#=Fk<=anp*9g`%QT=xur#g4PejVQAQR zK^Zm;Jvi*{2`c+>RuJd{dJDIpmH3lHB6<&3{R1%s^pnI>f!BD`@ZAsQW!R&jA?Qu? zk1&=Gx))! z6N^iW{kTcN#xcWySCaWsaL|otf4HOYVr1te-n^bRg08z>)esumE+|bfG)g}gAa+_t z;^1EKWMN4(6k0E@rQFD-{obc%!6XohRJfh&1Lx}U>txz`4NKGIJ4r|fdmUIfY-I+a zzDQV(<@DFl%hMnP>Z?o`CT%j79E%Y+i^~{y!*2U$K!rjMx3VAQn8|SGiKt>BDyGb6 z2+0n}B;ZjYJa$1sIIo&9fc0?|os1^D;Z2s3aIU(O0{Q?%3sC2-AjLUin7BSo+|8jf zY(e7|)gyk~*k1457qMJ|Vk^Sdq!_F8S`E*awZmiJ`DIC8ltsz@f9X#bEL@ zVcaBi;@$c=aPb@} zpYzg97{#XXbM0KjffJ6HcB)eboUKHR%q0vnNf^Oh`ZHGs{}lf{pUvlTsyLW2z-J5*C-dB!H3N9tW{v@+XW)AU z##{mpq1l*7;9R(12)Jccm80`Dfg z$AD!Jlw)y3y3i~b-OPW1ilyTKKkM)7LMRMMqT>WqDo}+)pBQHlI%Tve(={gW7Lnl0 zf2^B8f^&k_R$?DiXS|>U8;|xKc6SG*{16LnjPd(Kn*heJq=91vXhVP`&L0az2}y$U z3mF46V0c8T#3TF%dXdQBz?iW^q4nW5ARJk2wCMdb=O*(sGyx}$OuhaM{ZjbmR7!tF zzd%0?I(?5;9Rby$w~QCG6MvFuM(-I{?;v`Bev&N{+}cm7_T&R>%Xppe_AL02{rmxk)Pdo{`8E+NWTB`8|lzLy|e6 z-2b2xvJLsHW-wH`rfvNbL6ic_ANzqe>_#yzJQwYU2s1PqHV!jl;h(*A6UN4<*uPQZi(mpXAC#Cb5|j(KR&2rP!g44@dz(3Q>Y11#4p9lu;%S3kMdreo;`emo z^JGrsN{XS_PZ%HsJ$d#K#bE4ojvOXVrugd#+EIh#qk6#&BmBAM>`Z2nSiQvPf@{nI z3g%;e5yNM5UEBCc8ZYQ|n;VDLKOkBTm4Q&+NjuBv5++xCh{YHN!;IRU?THo0WW!FX zF||sF85_=iM)u>)9mGco#@lrcM+={Yw*?LfM~I6e1pOs%#!Fxn5E@EID-4B-&l-O4 z=5{mo2FV{P=LV!q22NPUtRltsg|Y?IU?HB-izDbmKU5S}xrQW@pf*JGU|wu&JVP~o zlo|*!Of7!UMid@E#>Pg&Fh%rZ)y@w$kYlJ@s$kpsvxBiM$Lj%;mp;g9{}>F?UMxcB ztmJ*gB_(c11b}Eh#F97rQe@f~*O~XAuDE=(;-hJfHf26q5$-1VC*y|xIXv>SfnN>1 zCO9QIPhhHjiCms{y*Ee{#`T61N4Y{TQIN<((;Q%QKBftLb7g7Mu?Ei zCIiux38TGQWZhgyeK<-~n(>d!TQ-dyB`Q@?27CfQL)~O@COJUZ0|&SSZqZ6?B?%BYvP0)NJ+m$(8y8B_jj;s2yj zFYy3Q{ilukf2ZH@7f$gPO!FN~BX$|gCx4(kDyZsYqVw?n7rFg(T*Ih{%cw#QUE?D1 ziXx+iS8-F|tC;r1!xl-UjYSn{Bu2@q_XcpfV_Pq*h?rnUV<+EO%iy12F|7 z6hb^vUI)R4vZ}UXIHY=3M`(CSsOu6+NmZs;n}V&wZW?zkXTBM44`#(ow41T;;x;$y zY6grx(MsoeF=8erJ!i@<#Z^(=Wu9}F0BC+%a`ph5J#wu(CaNNuxvsjdij;ZtnLoj) z)3%~RVzYM&qSyxUk;OdWNQrCoII|2e+J)JM?cy>VQ|unLe2_7YAsctM2sEn&_>&}K zhKR;~r#miR&U6j$2ph^@*FH2-^03W5f^Z1=n_- z%pU@ByHdHrY)%zSuM`Ix9*Gx-yK=3#ksZgFCAaCl-b0>Z2206cSSk{I&b;`1&(LX| z%aiGxwwSM2sR{`4P~BY74e%oPU;6 zrCNbqa%TFE1ULfxgYW|UKimm{G^ew?gt9|0VC&ST_{cMexBH@pjtKR9aqf5;Q1O!g zB0wd%< zP3_n~h85N27BhB$22_JJZ3y2E0v`Rf5&kT?_18xD|AQz%aJlptO#(SL{kg!#f3a)w zuXmkrft;1VuoT8TPuT{CA2t{{+gKz|Q3|VxR>ZrOh8wb?lEl+s%E+cZA^@gP57c9) zPwpN*z6O1U_*(JjWGNtI`6aCrz+-xWWGzX& zu^O33764fl{a&NQKhy5QPM?aJsmQc-_lVfQC%QQ z>`OkWBpo$VB4qrkv8c!xd?a(gU67Q}+xiLNSvcFr~_( z3uINV(2sOt9SF`ARXdBHafo#p2L%H8U>M7h&@oBIQNmh);}5xjd5e!J7Z06uq0{Iv zydr1%EQ39R#yi}eCuT4)aExMS3zBk59hS%74zcw8V`*wM;mhZI>PqaAL`G9oSdOO` z+Rz=H;z~rdIk5da>x86P(Z%{!M4@*Wl^rJQztT3y>H)om8SjiiP%Bpq=*~#wYTNQ?CO}tBeKe zOEO~v^;2ExfKh4%Wa56st~YmR(4#L`}Z!Be{(kMRAw!bUp~ZsKx%{jMf^`sLUeS+;r_Wui)IFY z_a%m986%cy5ggrI6;tNSVa;!0G_*7(XT$N03~AFmd+}Woo#C`7kJS%z#>Jo)I->cI zWb4S%NjRF{&%TSr^};465z&V4V^}@3w8g{{s8GayAP(SVsS>vMBb&l2dV6Kaf#uIB z1ZX*-jGDvgFQc!;1rwrN`*G)4>lzkfe^FHmPnkieiSEnAb(TFI2&xN3>%Zj?{IT5x zLQDouA+NsA5FDdl;YWWFZ7pKZqu1d(53|PAnDQ75zqgmz59EJd>7;nGP_>zuazbQ9qN^%MLVr*b16ppEK z8Ae4fd*6Gv4*rtE8a3&lAjd?_8BK7^d9H3T3O}P4g69=pC5GoKwzc)jPx2}FZ zFnAq-H#1+DfCo|dt`rqqFi1JEs%pZ3S4xGIUxTZ#D)8iBG!Vvyb(c(f!3SE&oRP7d zHPP|dBC%|mwIYa`+LQdvR6dcnpsU5%+SUcoBO$A(#uyNM75(5NKY-A_@{! zCKwWKx26yA?Q3a8&xL9<)?X&{>xKLi=uZU#Y<`dQyomx>F6T zh4{QAn^&FrT0f5v(^qKR8NjlJ3dtn6D&gk9sLHEMj3BClszeX)p}Z(z zn5c=lEQ)8$EfinZm98M9^rP^H$HrZ=W5p(~v7*l2(ZqwonfP$bBvm});%qHVguln< zvzY)TInOCM#VPr#uBEG~C-s@B_3f~yU1R_Pvd_&E0kJ}Oc)M*!Mu45vfXCYU+F(5` z4Hqeh4Kf5c`UzG8q=FFsAz)3(xln+O2u6kmxg&ys6QlcrknXmK5GM$5rW6dZLqvoC z<#t4bnA=VjRo9p^5kLn&;{=cTCCRlP!^CZ-ijFh&v4*2^Ecn1K^w3LMU zT}@JIU>zOZsY_Qw11z~D_Y!FdEs@n$o0gH3)thQhS65GJTI!3uj=E%-)WG^$k|q68 z!`C)}R=)NKsO<~=jnV+xl1NMbO4^V}s7;MTZEB2?K1}rm;7e#pyFh6*HOc$w4;*Ip z_V)y)%HPC4*!%0fZRn8@$+to>&%m;Oc`2tB@Q*8IZL@vfZp&{gwskww*W-`NHZ@3_ zsrsfK{oQp_*Zc?THa#oTpVKS$Z62n^Jv9^GOHI+h98Qn=Z=QUS2PFQ9%#_4*YhOOU z)b?G=fE2Kve`01Oul47N{rYZyd+VpBY_FRi;{X17YzI`9(^gCf%P@?!Ma-N zE|T-=p21*EEh&geu)9QU0bD@ixCQJ&czb$%zLhj0c_t|;1+f71gSWehzo##t?W7>K zAqc;NV0AU13M=p6VBk%e`c6sSCn?CG&(&ya>I1a`UqC?pZGf0SwnI!IW{@3_T@VY% zZipph55x*$4cP~=f!IRqAodUkh#TYx#2w;}^hNqZJRk_jQSUGW#1rBL@rn%aLij_x zA-)hlh(E;N+aCcz0#^VeK%#hk5l2I&sUXP!AOVOVZ=?q#2oekl4sdfvKtdoPUO@=p zZ#WVX3JLZ1Km-N5BZCl-Fi1Eg5)y?7LT;RzOW;U9LKCb$r9{7by(RabS7G|l|MzG9 zf$8}ETVeX;M*=i;v~{7-uRjNnb};ggt^G#=`BKW})d!E5?MTcnUj1uaF>c<;<#HzZ zT`Mh)@6t)kcPMDNe-QibVbZZ&?c;a67|^U8`vS5JHoPtUP3!m;9aYVbO*gm?RG{p% zuH@C0dAWT4P1x|RWA4@?L@wL6w>#Ls>%KC`W2g0t#bDV2A;n? z8W~)C`H8mFeVbfb-^vt>ffdekMX4r;caN;rKkj?CUbQ3Z&5Z-Q8*}LIO6{z!y}h4aZr#kN zPp!;Sp*sd`H>>WqI%@l9zn@yLnY(jqyQ)IN3aKZSI18%;ee_D6%|q*kph&jhhQsZa z8+uPRkq6&Cv8mqpe*LMPm(9l(@1JwGwE6UwM8{-NY#637Yq$OKq?JhzZS$m)V3RZv z(dSI%tr|voHgj?yTzKq>#eECubNhYlkKQPrHM?Xzz577F!^$%(Yl!&VTQS6c>5ll6 zTxqLx_j%H~H|sAuupi$ITFSPsW!v0MdemAxb}=IK#rF8H{m(~l70^za7T4JBOjv2U z-!$t`ZSu|S3-8PAtIDF<{rc?E?t44;TU-S_JGasbz3YsP=$+!R1xee_?4Mz$r=2Wy z=atRncSf78$K82lyUI>$nW@#CsQpi}IwV%79 ztz~I_k8mHu(0SMv=P#JuG5hwfiCx8AkGkZGZu?(oPoIB(`>BAG{PYzsUuxc8?fBHp zuAX0z-5NFS$4wnR(?JMk4l56&cjX1)0x<8~cVgMfN3eM16yrGKl~LmZ`U?`G41T>l zTh56GmTq8dgG3(ZywF|H+51MSVD2eyd9#$bQtPe?%$-aCBOGtKO zJwje@T9Ba|d4YhVUs&6C=jaCc^FCtqeNoNOs9niYaprltS?+%OvzFB+&HEpRd2eW2 zALRY4a*;yLvqn)zV^d2=Bb@HOo(%j#=g|(yNT)wV7kd?V#h2 zf;ZU_?TCql`Q}^lJO(EcX0>d;_i6E_wh*-tCRybaZ%4Zbw^$4}B>C#taKi>+WhE-N+o?h%<)9L$W5KWMEozEFCW+#PV?LNm1qey@>G_QNWg zYlHpyEhm;Uwx|(n1r8O*oWXEkjvOJU(!fIVss?@WW~KuHoRX*JZXY zj>&J(Up~qMr#$IOyH?bidi$b^(W)&q&rru$rIv~#a+G30`s%qmK2?fpH4*m(GBJUE zhHa}C&t2Ao{D|*Vk6CsXKJ zC6u0^b*NiO4#BwIWREom#8yQ>md!h_v**^niCLEI0eE)6H4=iLJ|jHC3VBc9Vta>#y%W zUD$GD<3ydCcZHYGlTnC1-8yD1WnKFVEO7q`59{28s)x#N4$dG&gv(=j(zAYRKN9XW zGa&8B+;^7`&nj<*o{~FjmgKd&AmY7FWx@joneu8JZxD}aTI;;7d+`e*$u_lQUGI*> z)HOS3K1*Vf;*eUmYE6^EKkSoLe|+ISE`2_@=62G>RjbcGCmEZf8a>%C;y@zf{(^UDh!_^8HHpbk~aY3k#^VadHl4#3n?r>jiH7^qet9jm@3Rix-JOQXyBosqjM`-C`Xj#L?H z!LeI)PHxtT$HjRzkKGt@V;hfzf`+yxRW7`2d`HUiXzi1$D{K;}ONLr@_-a03BQtAr z&Y}0^Szkk(-?wx8W28cX;A8pL8;m0tZ?4;Ll0#4u;M(4=(<#p3X4jj& zax$^==D$TcyK7}@Z-(tQ@x40W#pz9qZR5WF7=|gMjikdCmtQW1N#n0>lNsF{QYw90 z;Z!zHE$if?#vm>zbKh%ei~L|xoV29dO~4t48Gc9xxW0GZ%MI8kotIRccjAxi<^}vS{KH4_bVwbIMEp|bIba+ z@9IQY;F;A63QkCap3m)aaYs91{1INOEJg(`*Nwes;f3=jF5+)>nS45}6DwzFrblyu zq&(#)-4vsza&{q{F1moEui&4;oO8Ot@OAmC-sG=FnI=c z(XKjN{5%|W*_DKB+xcF`@_QC8x)`}2y(^N&vX%Ghn{zJb6l&)%r=~t>AM5Ol zJr!DU=M z*R+IfUhT2@W2xU}Rv^ZH9SlL|UU^HQTvn;vWHf7TmvgFg&wOvc_}E8zbt{>6$A2@C zk%PX{SboahLZz&-7+x^<8ZCcSkL>Z8XbYcWnNQguLD;#B%wPX@cs3`kOw9y;I?>$)T2=yys`_GDB4sM8E(j1}@n&a!V)N#Cb)cB(ayv0ppk?*Ds zevm>$Px|$+`mjF1g{+??%oA1?LQUcQ&0 zaQ+6464l|KZnpkPS(o|qn>|~O9eKHRQEuDIRSgTyOV8)|Y<5A?y%z@=5}Y0{M44+- zy=OJD)~L{8Xqy(hE=Q;#S&#>#T1zRQjZbQ>=hiutLKj(?o)>7=E~KDQC_&^~c%k{Q zgX=ZNWlgDzetj1g^Vlvm%Lx5cu4B8>{33JZ7wpY~*`U`(7xVJDKAXjheEqJ7!yc;0 ztbJmpvl72Pw2QI`G~f5BK6CF`D<*1iPo_*>dA5(-ahOSDw_$GGpa8S7ctIYaXkr56 zshYA2MW^;Egz93mSKpsVW1R7crkxH-_ofQRacE@h{2T_-q0-f74CO@rt#L$u*O8TqV-6`=qevHH&5_hOM>iyM4&TvG%Rk z6WEK+Eu9ndE>waheNX%Izzuvv4dtHqfxy`Lm6>J6xaILQ*4z8;J7;g<8Ll<4sbajj~;%GceQIF0;y1ghSvAmlXsYzmhbv%dd`2!id~5E! zwfDe%#&+#CuJO=;l}FK&I}fiICd>YU9=201o;>BNke;R%r5Cqz^Ikf+;7u%iT|vji zd5WMVN*b&B`RoLc52(&yX=qybj36PpmH5t8>|5-G}Xz=q<-NYnSXijMPuq z97!>_gI$~~hS9|HrV(v>e7;wm3x^n(tc`epC-+*!!$GZmIw2hWFlobb9(e!8Hv zXe?h;U3C|cY;GOLht2SupCo}?eh*_#K`1|h5&V5XW(p`!n}!K=)ieQAME@&Hpz#eR z(2zLv-(UjC?GM2O+W!zH(E2@0U;{t^2#C+Le?RTW2Yzwmzc}%~bJnL2((j!0?|!cD z$DMU`4K1zjopl?(JxlGErn!CiAZx$jZPU)f+!GsX$p?4XHZ7kmf5}68){%FMovw9! z=xF+o7V0VI9G7)y-RK*~nY(L=2mSJo$8GR)B-|-jr``G}-rLs6D$&u>Nqc>6=PK*O z#%*_pD57X)dNiqon{H`apuW_qdH&{zg0uFsk~NF=E$)c&O1QZvd!zcXM>7(iAF94i zxxQQ9z&tZcPV-E|9N&Z?3-uVi1L$j6otFCu81IwbGD`QcOp<9eo}F1nyi)mU8%FD zS#mEP|2Bf(M>1K}$yiXb!&RC7zG(CabPV?}t@76L6}Y5VPtqCEarGCJ+cs6gm9FhS zW4k#R+|emEb3HUB-g9@uv7pNJ@^E~UPPnV`ove^YsgG@|?UZ|OEzWvqx0s``!}jQq zLDr#TE8bfe-`o5tMg75Y%lgOH7n#OYN}*Zq%8F;!?mC^fp~uWSRJXpn@ruLFe07hE zuxJli(?w9W!m4EbxsJuki}h_9Cl{T16|rm=Sn7=0{FpNqWBa$|FT7-umYd!qm!h)( z$8b5}ps_XOW#Z)h*lUZ*-INXqo~fP0QQ06Rg`+j|x4Ad04?4cDUDtE>Tg}auadDe) z#!(^T{DnT{QTu1CF`Bgo?Mxp$8{Hljv5qNc(V{2c^FVg)M&-2mY&U)d=!8$vl@)vL z?UKrSl~Zx72Pf_4X(-55sz57cvgpMst!|#7uT(BUrRH0Eab{*w9T#<@BVhQaG*s0s zZsnxgcAt7&@1;XFyQN|*PdQ&7?c&p*n+w!J4-CI?9DJc*=o77Qrz~L*|9p5wuOl*J zdFe^(E>UULJ6C~ggR6{TL8IwMgSu6hMKd0EX?d);wFugGcttSh(}M$stnt1%KJ254 zm2CkvWmJEVv~<++`xPv7J7tza%17T!Bv)o3t!(1L#|!uq3yI|LoR@>mJ)SYIkGzX4 zSQ-4Ve@XlMcLyj3C@Ww5I_{S|FhJ?FDa)2(*mi$9wEwDdOW~ZPfLL44#rNK?-k{+k zTCDfh>-3og4s*jRXB^mhh4|7Gbap|M88T$1N5I+(9$q%IJz81=M)3o3!~Jp%d7(PC z6Py>D7GoV!EJ(-Aw0~WImb&6rF>IS1qbz?TuhO&$MmTjEK1Y=bJG84oc*En0gLGeF zPFjR{osM+9UVXa(@5Ae)%1weRmv;62cIwP^wsAuE>yU%FZm))Pv*$k7Tc$j7b>c5p z)}@PLiYwEqavRLU(!D?BzVc~JLROSKdS@8%q-ML#b-6200~y!qEglqt^fkjy%L~>H zi81_RS@h;?O|UA{=}KvqnIrA-F8tZugNKV=XxY|vbq)(%hS0(e)9V%OkgFfEE2MLs zIQL&}j(wlF|Ip%Gqxx;miubI}79V`F;_b(J+YJNArcspN-|in0*#GnP0R*c&LfsKT z8_f6Z0h@avgF~j{D_}iU9nFn^@&|s}G{hU}Zw5rYHkcV`sHy3zt7!ljy0)&G&So`r z6*V;#K+Fp1@lPb|yhD5u8~nTjg5k%Gga*Syy!`+W`AZAPpba|#xKN-+tU;lx1w6!(0!AHT< zJaug~U0}qLe_;R5JPmbStv~VrIW++G{hge;mYyUS^E)1JqYmsizvBUN8bA=~_dIQN z4InV^2cCxJ-?XcvCfU&cAg81A$2K(7)c=n@tLyx2S#|xt;pu1rqyK#y8fsdS@Z*ooy$P4h7y$KtY7!X0>Rww*TtZM{HxX&`G{@86m8XmU1ktS zdjvWaO4g_y^0Yzu`v)XklqL)3Q}2z2b^!8%Y=5T@B0A(AtrF8-?o; zW+8ZlNJ|_R&d~S1^OuOomx#8jAkrn!SXi@(ck?FOy*|{v{>)_v?4_j9Du`nVAl4CB{k+{zSU~6>r!!NSaX6; zvw9?-b;0@|UMd?mXA5NJFz+gTBIwp-2Wg4H!a2`dWo?iv{pw_(9tq{up#@um$$dlh zkJJk~7{cv$2B#6(qU@+6Zgb^l8>-yAOuHmzcYxesxLhuv)CXRD2!QjO*Q; zz;1)8HgAl^yhu&OSGl(wQ2u!n1kygwb)bo zY&0YWk$YtRN^Ea4GO50ur{Vgu+3g<3D8F5dOfz@=2P(>=Q)f>pc$ON&@m8XNh%msOQ5iwcxKaKq2l6w$D1x4I^ST zHC&zy=KRWn6V`r@d&iYXmw&Hy*kIFTRGcCb*ki21d`F*YLo>RTr;ke(CWYG%J78(# z-?me?U33lkL?psScm{D^6>&KhfOle^(hRxCG(mygS=m3Ms<+gPxW z@jV`QV-~BU(DvrZ7PXm-ZN+TrHHurzH6EFslV=z#>8Rom4FmgLUfP9k$o|MDzBZYZyUEmTkoaNCmq1Yjab z@#X`Rs`RItaE65dsvp;D+7?tbD>PwWK-V+pB0OytFQCC`;R)eMfHAzY@V(F|WfBX) z$}m()djR%Q1Pj4ZEA)e2*%qP*5^vEbx26B?DeCW@yp8`s9elJS1opuWLZ3%F9<_}> zdC>Mq1#Hr&G2#54{)9XG0XK&2y)~?%BJ|o7U>jZoW?>8@ARm2#9&~IES(jxdSXvNn z5u887fCAxpwLXp&<)M%7h=*MX$cLMcV-s!=NVRyh;Gfi^e^AXH zsql}o!YAZ_Yty!v3HJiBpZ@I-5~!4(0PF`>wj@Km11pxhVYEL1CL>&E{K`+#+ZGGN z?l0oGvTVn03U08FISx}Odd)pI<+}Q1=SOdromG+@<}!aEZ}3jGrsyTccDD6H!?%yo z9pef`Z@6bZvANv=oVuZN6&x)psFn&5>}K^6n9!*OaE;2sayUwnvbM=4E+SFf1&&eY z%S3F;Zj|Y$Wm0GukhnS69#KhH4+m*j4=xl>7eSPd%FACB&7ts;=PmAopKx<_La>YM z9d#iT`(gvIacBsE1>5^3EH+k1awm*G>+(xRm4@@3sl!+K2by2{ltQGmdzLrt3c3t7 zE{iwpGBg!98cFpP`bohui^)X&{GTIp$eRcn%Y~?purpvz5-L7*HsMH0TT`RZsm{}# zRom+QD%y0+Mbw$Vu2(_<(JUd>dMu=TKq=^sx0uxIcOCdxy%WEC zI^QS$*|E51jr_g8ma>Br^DA~XvK+N|Gz569@mbcsd@8^gJ&X7KG&n|_JW$p3qDd5F$!o{EEv!*s_^ASx{ECjm7d}zjM zDs(Db!ye3%NLsCue&g=-K|iK~7eiD&44JgWJeBkf_!T(-5rsaM=iY`P-nZkSp!1-b7)?l&w25BK&rNECg9D&3~1ax=sb<4$#_fHK1^Q5 zr=9)lWY;Wl`KI1oV*rk2r0E-+%)ByVc&AF7;ccYK`c?aFa|FXBmh+kw65U$f3{gIj zNveIz6JAa#)6^%8y2}^VsTsZ~SgaE-Lq<(016fGwMlW`A4O4>1T(y*WV9u`w;%d&W zkZ*459mbsSc^C2rowVVkR7lAf)w_3P`4a95ZNvsr<|)UL91tAxOQJmsl!uSHgGnx| zS)NeL2_O}ScC!(Uhg=Nz_nr=5(~(`JB5r82lG*g66KVT8FB1SJ^u81>cTL=s9EoiX z#NI4K=qvsXFlU^!bJJc%9ufPZ#!9-ytj77cuQsdj<8&Vpq3o!C!zyDeZm{V?2J_ zA`~4;ysD&qLCHye3Tg49Kk;Q=t-r`NNwQ~M;egSmUcr}n&mO3NN-;gvKg%?3G} z_|MG{dlHPZO$!lVAAqlbVG(ebt2PKL(2phTL%Gxq{m?V_LkZ1|_t+9eY0{#@Qw{@)_w2>G2vtRhi3>04!f2yzQ1`asUOOgDENE!BwuGZpoDR* zdK^l`V_Ez-AQ0i>P+nacTwopoIQzFkX0Mkr!!>~K{sh`Tje%LpwfJq!2L2L>rE{4# z_L^)PCBlWpD3Me~Ii8%mY4n@k@c3&#-hot|x1g{6dhka zzhcugtWyXMHf%$_NFCvNe1D&6mbL7#Er6@>uoH-Vh4l?fb8M@9m#M>BlFr+?TV7{H z%+VH{0Nc0r%_cZ+KRf_xBj5!KNTI0y0f*ef&puB-O>lmxF+6sdXWW1(U1t;W{S&%C znVC#nIVWyb1qn8@RV`8!&5oL{au)PSoN89olQ^26N_sKJ<@@2`l--_I!E)t{=ordQ zl_oQlS8bi(b(r2_P52!|mp zY$M*RahqF0zI@Ya(95RO=O`p9DGJszGY0FrX@n(g1~GN*N%AVI8Sbd$x%sy8yx!$w zO6-za-^I7hxHpipi4cr)5rO-#Kfg9;954suv5(}S2CdqGceOmWO-vnb1fCa-1B*86 zz3MhqQYIZR;|+2{9=0~yFxtQ*1NfibmW~NGnB5C)n`vegbwQV0_ zRTlYj^*tWYlPwCIGiwVGFo-9QJTCwq*ap?52*5J5M-9L}2C$6hFY0)W*t~zpnDC!p z84re>!5!kTax499$e-UBLfbI=T2HyhkYu3`%Z{*L{MU|%KdgKT^zmBThcBkin;hlA zO715QV;IDGwBR39?0-;;|DZxW$})Ssc3`0c9?r0pvjp(5Bb!mwrndc>@b{AXI0ie% z0q-n^mqN1y3-~VIrunRyx=umu!vFPgZejGR$RmxR`Lq=d0&Wu2-Q~R#Lk2Zb14z!` zov_m?di~MrlFAI5we2h9J$UTB&1cguOu_q#+c{g_&<*x1ThpLdo3MzBf?e$4 z`yERzujZavO7|akkKi}!yx^9SKAtDt%oq25$;MYO3R0L0;)Rmcw!=1%5UdV~@7kt& zWr{=)gn7uA)*GK4%K5NJ<8gEIHVOvy&V9Vs*eeehP@lelu1-3M#u++{$5~24h8A4L zgpv6c-hfSjW_5?U^x251Z=d|qxF&=hjM1M|uE(Snf@Z;q3WcK8+WTb~z>1nu@}F*s zj!8vyDDP*bL-*rh=B4i_kxFew#+j-gDaKB|4Ld5d?RS}8` zgQz@cPAqzH*c%^nba7&kHPJ6{Szm6L|NY(G+@86V^;+)HOe6C;@;$Ti=j+m}T1_OtZ<5CgTt0~|ErxRbtWh(}QQ1El1VF<#H zMc>8B*(P4u*8G^Qj=rCPe0=cRjUOmEJ?KoVXd1J6+#qXjF6^6{huqRG;s{Qp7hT24 zG=I*5n&z3BCUMA^GCf{nJ&!C{#h)xW(08&V zgOl6k39v_$@VMNSb8b7lX0hT2X`Fwp3;5tbk2F5HlyQkSSp$8x>*Nsj)SL$|uZYA? z(~G?N>p-+C5gg2|@Ak#AW$hV$HL)_B2w$L630cOsYYyLNXaUa3Jr1jPjP*k8elHL_ z&U3j966R<^%5F*uPAnyYdTx^~?O}DIxvw&7egsJ$ z&UMt!Yc(wtGKD>%!8vvHWDHZ^ zE01d|e&5iCIueU({62nsNu%`t3;LGN$?@wA2QQ zMPJ(Ucr;j=&%FUbxiLxfI!2%ORK3Mr|srB`W1W&@K3WoXwpFDEI-){3IAzKiyB{z*;C_=c&Sx1g+Ux;;yKIXsr^vJxW`n`pk=Vlu5C%D-H} z!O31~?i>>P;SCG5SC@dEgNhkb;YwG*oBSrdDiV$-1ItV*ZE+531?Y^E`)X*?Py7wu z12UoFcbeE=jlg6SNe)U1>sANtMbnnnYJ<~;(4cf)<31q((Ugi^wwU?P!dBL{r`lR^Y}}mh;&>@ZZ4qxIGp945P*4mf*X8KoVDbGix_M_XjXg?L z!Bj`{$#wNR2?GrST8Ny+IetE7Uy5WLk5l!RYA&)B+mKIJ7hCy3x$TsUPm0?pky4j2 zQi^nr&?y>n8Dr|-^bG}KVmgQ=xu~}tnvq5-$8XQ=w=Nb|O|~zqFd#7~{V+rd_s^bG z+0DRAnxsu?uG1&4J4}F?Do)oY-;~fyO|OML%a(&MA^2-tHa^1ww zM|P?3H8%=)a>LXK?GJ+JeB#kHJa*r_c)`JWKaqKU&AnEW7UHE-_w&S*X>o)zoo2!y9ga+Ld5xkK-Lo zNB45Dgpo|0TZT-T9~S&&&>+Ha&8YRj8AZ2<+x2B%?=KJ9ZJZlYGW-~~2_H|FtU3aC z!inP28{>xKJZBj_zoL|xhO}VANQ)FVr?NNQIgI1Av9FYCbi#@QhcX8Z3%dHab^S4O z6*W3YwLbOrtbb`~==W5;2|6z7n30mJ!ElHS=Y-#=d-}(glUxh4TGqvvFmM}1aWw8} zEQYA;m#G1r_V%xS_T~w|Tef;z5P~gwW-)=Gd}c=+I%)8s!CQ@J@vaV!+O3)@in)@m zAWt2eNa2?(j*)-Lv{BPQ9b$@xGK#p>t{|l?FT`azXzwt;YF4YYl}K6h{A1JZn@@q9SaB!(4kO^bzMDO&L!-OfYnMwoFTK?d5QnfL zDNz}<=2c;16vDhIjzm;0W0pMqjnMpipUnK=AXodw<&e#VwRmf&QM#Xr_&CS|_=V zTeqAt5Sur?6cLmzNmGzumIg>MV%2-}Ay6r(@sJAu=HKXy*X3x@Vo! zn;{b{lH$`C-|QSJaZVh2f4ZoWrxB|90RHW$~K zkix&h$jwt84vF&0==p2?)KjK$ELoyW6CBJXzn=x?PVyYZivxK-5cA+o1K&M4X77Au ze%pm&hoiwG>_v;>*q2UgIxkgMI*d0bs4hCfZY#c1J?W%nS**~+fv(cslUALGpxH2k zN2$g}tTvZ%!fD}SIggj8;GL01_{pQmWs3GvJ8bYMFpf}ckq*g|b{Cg)V(LwaY@g)| zUfrqj8Gul3-v z@xs-r>D~wWPrTR&t~IkF35HR^WQoJVGG;=ZNHvgxo;9=AMMALdPXC<4zUr6es>l+U{c9a2VUcOE znX~cfk;pryl*Cda%7&u+eY59|{j$T*68jZO1{GzEjf@!;bv>^8^HUOs!_*IrkUm)J>6fZcnydT&SfLkB^lTa=v~d zOR#*;ajj3blOhYTCk?g1a%(rYQg2vhS*2YlVV&le^H)+jXqNYbO>qgqJZK)u@1Lae zzo|lUcq_7!SVJgS1AE3+s{ibmO!>vPZ=32LQKrnM z?Q~R>^%{09m}!l3ou3mRZ7rct_ivB9ovKl-S)sBs!r&N82Vp_TbgDeKBnoGwY%MCk z4O;Tt+?hp1MqDVUeoWazVJiG4Kcc!hJD&B5tG%Vx1O0RT__=F_aj}tE7~@g-PjF5C z*Hy~JPomgcmjZ_2&q&UO;;yfrw=DG<{ehj?Yj41VY#f6LpBhJoL z`k7DG)XC*FsZzXO3}(C%QCd!$>|kLYppoKWOUN--Ceu;Dl&Pb#DqMFtQP1@NEuU4y zX0nY9%g(cZMWHpdpSq1cPNRYyg}!Mqhd))}J_-;2PDnxHRCE9yE4sLjM7N`?JFnD{ z6^w!{$5;dZ{9L__3EB(gjE+_0I|_*T=J&Nkad0e@*>L|2`;{p8Eq1YHn-f`Iad9an@CLs#qe2_qa-l{kg7^+VT@TB5N*dcDTX;)9y2)?oE2k5}q)m zq3Ys__JEmZMsk8r*r+na)~2)bzKVbumqZl1@Tp&Hz}K?JvD{viS8RQ?dCD?1wEXe{ z;t`M#t@h1^HSzchIi%YRccK!Plkw-*Ljuh=@_}p5?CPvNFXHLsLpbWc%3L{;(cgZ3 zDYwvLuK&EtC&nJ9`Eyht_YKDVI@Q7bcb1_*byH?bOv8BTb=`4g@Vmb6a_5_@ z$BgmEJhkZ3o^H@*Tej3eU!Bx$uO%7-hht8``DG$m_g0C|`-T~$wL001gB(WlMuhbN zbuN7t%|Bpy$6a30WA5S051!N>8JXT+QN~ z_>9mwS@uj#4Qq_ZCi54iLTWy9pBC^jh1DJ!npH~F&b|EBNG4pUM}4CtbE5R)2yNZh zCQyobF1V9iX*rr?xA*WMF}LW=PPxjNZ}B#m;UW(OLGp|gp}%}vGI{>ctuSeWj}sr} z06AA>0AkXjn!+lEe_nPf9pSEYKZmfxdC%0}ILBtJwvH~J=&1u~ie}?*u%-KzdZ)G;zPoWFi62Hvf@ZhEop59xN=40I1l}Cz z5Z-%|jOa)D4cmsiJ|G-JnKLmYf=8;mK=;^=Mk!8drl3Ck&2m=qPUt8Lb@`q$C*n=e zPTXeal~}-mt(K&maT;sk4EGrw-n87A?OTri!>_>@Mg1Dea24-93S@^O<&U}hjMrBv>1S1?8X;4KFS7i8^ zCItKQWMS?)eZxC!=w)%5l8S!Uuu7*C=XY8r>7iP0bCR`>eqbV|JL8%iqX<^h3+B)6 zy=$(>V68Q|!->pDtTuZ?sI8xE)9Y3_Te~S-B~l%QCAlJ>m^4#_Fbf>ynS+&v>qGJOJB-7UxuFOL#lNl`A#!6G@U32oGoluZ5{nc?EW6_ z$25CERK#+2v+G=0>u7mZb=+v!fpuxLlGk5|WhmV@LlXMyX%QC~Ibj_HqN5|4G+kUoW(vvmSSEAXRjjoZ zo44!&6!V(0rTDI0h{==ZoANeVvAo!gJau#pjz+4Jk^LG0R}0;sD%hYmDEjTI+G)Qo z6t=t=6KU%$ZeznQfpTScQM6aBi^baF?Qk*@e2^Z@csx6uziZB905Iqhp6pVG9v?Dt~J zeePyCY%*%f*f*nORkD*jX=)KRadva6N%3rQVn+|J?3}BS&+P1%F)OF=_$P*AcPrZ_ zJ1_~!QVh>lHG3D7Wz^}rgmgg#E1*#1MFCdW36oX`;slNVq{FyYA>UT635LSx53i?+ z!&5eAmcr8Mbnca|S4hEE7($A|`AXjCTuG~N)cle5=$ z2qH?_8V)JsC%6fXGDaCd)KZ8~@>bVZqO_pKKK6_6Fa*fQk+ZWlPypL& zfPjo0Vvr)(*&YxScD5H)c$8&e{6j><8W3mrLmo)c0SN;4fJO-MLu!va0?_o^zz3E; zQhfkzfQ7`5CPIiolBR|bVhx0c0mvh05d#_=9#sCr%D}fl{RkjgIcZ`BUf$n~kHh($i6qa4@E|Auk8b}q9wg6>!2Uo5$urO+Fg*D6 zAB+!_-&zFpAm9h*fRu$qL?pzh#lRMhV0%*oJz4>43q#NYNeB!vursx>x3(kZcvSiL zHnh*n0v$k|HGuP0`jv=t&9QFtoW@UrhnZlIOy9y z%*BUc0j~aYCOkUrzg|*Nl9ZK^{o70bbN&l0F7#JD;4=!Q?hVpO$i-G-N z!adX<2KwME78X|G|6Twe(E3ODN9`|{0`7Qp7vQo#o%nG72mMdyJ;?mwJ~p6-Kj;tK z|E~RZ7yaM$2i|ZiK9nkck zjh_Dh$D@0groW%uUvu^ES^W55Wb`b-|A#p*0KgG|Mzjpf#2icybB{yoA5C7?_(N1$(fiG5|z? zl(Z=X0!+uph4T1hK@aN)z%mLDKS%&11QG^`fW$%4AQg}*2x6fJF#$nr^bEk1kM;wp zhhQdRz`TDg?8p1xBmW~g@t?VgK==Qg>VkhJGjg!e^YZ?cwU{igVS=H8!y7gKO0aCY zrZcR=1Y%JrK2h_n;;q%NKC5jZ>RVj-OxUg6f$9FpS_US(&@nch9=ROdqt=+r^Vfa? zY$&+uv=|K-lKQl{CA87Jm=b6j{Fj5ytRqa*x-*l!FCYUK9>0Fw#lHDwg8rE__s$_r z7A*p6j6h9tQozL9LEJ(CeHQ;nmS^D=&an~m^)iv=?ljJ^0U96Hox8$my+c8YZgX|{ z%#29dMMm(czkRdQ%3);F-t0{vt=r7EOmURvxNbumPuya9XTO>X!xhUFdSUxs)}XD- zBX*LhMA8~D2j4ETvhg_17`@a!VTWkii9m>Z2LFSVKP?*3*@T#+fDT=3@GGo=|?0T3Z!zk;yPGr zC1W+cj@}#k`Lc(OMKXW?Zi?jX_^|y79dM3XHbZo;GMQ(&Gum4^QMR4Sccz(!Jqn*2 z395J2#MDb?pWFBPG>&=KoJr!R9vE&UdcJ;6#LnoA=86m+I@yG+Ksx)1A(5VJLi<@x zssR~8*lkGsH1;&XP;4V3&%Qag*i?3uzVG{oG#wvgu@+Ix&0?`#txa+5Wgf;1%=;#1 zw_7FuR1HSMsc)LF(9KUilJXVYJ}l%TK5wRKzM32uRNBbH zw!UJ!72b1Qmw>=)+-|RAYT(^jCt089G->g;dR8y?c_|Zjpo`-u?ko0xWD7PbN<^XJ zM)UWO=t@sDiXdVa3pcL6YQj`l7ZAvM-oEoGc#Km|*(d1Ns|L#|nImv)p80SZA_hNd!v!37w-N~iRPv|Y zcYkiB`{-5u(wG?T?kxD)D(76_EKLrCu=`OiS&NZ4^SfRa!^D9g8d4~!EKAUm)dy8? z49UQZf%T}8Z@eHxtj`wOMT3G=^p|6}O-Hh^6|F>_sM@Xav@SB#Aft{Fx zk%O3xnc+`VWCEb>Pe^12Hbwt{#E09zAQ2G#pD>XgQ1QQFqUvvCWqE+ie*vW6BSeaW zqyUJN1<8TrK?)!xkn$s3>Vfn@1|UNa81#tCAR~|wuww)ngG@jsE;c4$E08J33}gYa z1X+QsOs&8mYmhZi+JI~xHkuY-Bl|yUb`PiyvH{zfS{s6FEF2&pI}ii}F?IeYAcO2d z_9k{gh|qRhU4W0~WTz3PngAI}I*6C@gqfdGSDM0V(yus%7&0?&ik*xO*<1>mmixwBa^* z5$bKXE&Ti`%*L}!P8CzROe%b*rdv5^z5;AM&A1PhzY+|oQIWFO+)~efzNN#kLwk*# zJ)(DqH*b-DJ$rq&deAgk-p$IN`&Hnuhl#{$dFp7jaoq@vy{Y&r9&Y-3OUt|IW0>js zS874>#XUnkB2oNB^2yPK@6C`F%A7OhjeaQhj3}99(y)@K5^|`lbBGp-Nh+9v^*9;v z63aCUC8E2PawQ72Ih12kGNW?ctPFG2W|*V-qcg|dde=9>2=Tlc@pC8c8 zYJ?!IGNme+@jZcX?acnm(Yjcv>^`~8kueF6izZ~n`%u~Q*c{C1>22TrO0{|GJ3Srn z5cT-h!ii$SPYzeL249+}-jy$}IL!R_y$J8)Gk@tUPy{D%i{9wjOw8?ml1pCrgdU&& zLx&C|7AB+6nbBor*qOVcLYjllg4n3w?oNJv1uqpNjdY676{{Mea&(iLWnnZN~(t;v~}6<_OlE2HD9&=Ol>Ir+P@Ps1VF8k@2uGzEkM7u0a3KcU1J&K<~(&-4f&4|9RiBCap z!e=vc`DK&EZKTV{dQn3wLR``8^QhfIqeAAw()J)upCWzDIC{9!CsVMy994zYX&3to zPHxTio`Y&T?%%IMPaHPLJz#D~FLE8?S3YlzY}++k%P;18{MzH3b|}q94zHbY|AdAW z@2r#VJt=_Y1aJItVaPdK`b`@hGu_rmkY}a_iR4o+CR=ArB)UVfwVp|mH$+ae$s^pCbu~C%kPf@ZYL3 zLwrjXcsziQ0UcEGsk8L*X}AyiYnn8@H*gKT`!q0&+Am^t(V9qM0vrpN+Z~w-80+WD z+jw@k^Xo778hv!LtkX_zWE52tUxB_#{`joEq176Em1WSiV~xV^;9?xTNF71$K@hB} zDX4LTgsjZ}6apP>%^v4PaX^hEA#9pIPV{r@xDpTRbL{Iw1LP_}LI@mz7UbPv@FF4o zu68`bQ?O?pW7ntj$pW=tRo@TaqA$!a6)Oa_>QRx8G4Tmk*4b*_G2i1If}{0Mg1rGf_f4y7nN_B|*@q zX=w@SMS@im%?xyK8>@ebU!-4%ww`clOIGbFIxwjpw2 z?=4iu=dOCWinp9kI|`*jj1Cx92I849dTMowq}uOnQ(Z>g?=}_#J%k3{pizS zLQGM;(o z&F4__G+Ar~dCm3k>VI#VRkoh0GctiuZ?b!jN*(SoP;;EGMy3@UBK5!aABE((*9iL z10ib@Yi80hJ4JF6=+=A>T9M;&F4v%+jj95%N?da}ZW)WONbN93`WaVHM3nBBA~zN3 zEqQ&YOu-N{ZrE%S`)gCZ35)xTO@r@71++z9U_ATSFYQBQS?gG;TF&elFaDF8UxmRM2;}_L-!!dm~8jN&3lX~`%6^ZSeiIB2kb3kw?eY}ojO zQN%cLsNUEAc_RZXaXM|zqJdS0vPJMKhl-8lT*g89Gjkw+d~N>gNrMd~*hFPdM%irb z&^EQ=tT->$@#qPi825N*F`bC>w9l46l94mBAB4i(=W6MN__r z(bhLlduI6Ejczf?b@D%R-?EuS>e6EiLU$Ra$HrbYvB2QT)}yC^c4`nB6X#m7`GjYL z3wvg1^G!=t7J%is+Sa5bmF!00&tzM~UtR>nM=j`g&!LnXjAqCUw3sxcmYGf8}!EECp>Vo8&s9;W`{m(JkkrNf; zwAR$L@mYkb^78n`opUQrZ{+mjWcViD3hP0i;(Wczeup8VFWe%RH7~Uxi37z~bj951 zBHDyfVjOMoT+6!nVwZs=wB&EKGfdE=I#W^vMijPOdNPVVdxep+ zobEm-T^0GH9fq4Au*v{B^s@HcX7!cnlqDSYF+$Pmh&_z@;??M#$2t#`icRD7Qf@^( zselmE(+Y%3{YyW=3qG#uZNKfKQ$&Mq$8_>faYn1tvZ5_GHm2rqu6!T6QLEVBz`RY% z1gmAAgj=zz+xyH<^zCgnxZjcJ_fNKyTk>lJSAD{{I8*GQqHgY@T7#cOU@!Rorj%`< z>*`(6C#zbg8sM;DA*`HOU?|XEwiJVG3G?$i^1~aXdR-3WSK@RFQ(Yg#)Se18kYHPz zUK}ldoE5ZwPO~<)|JoFZezYrWQE~4QA9F8i&hWUpcv?MZDqd3FNb*jgU1K+7_OfG- zM;&h5Xv!3eyRt1xh9uX0lAYo!=o^!pEIyxy-J+WP2mj?!^&^VsMF%6Qrk*+IyM99J z;`3=+qv+UI;`R9u#M1*KK^LyE3IrFOl{Oj?+r9SVXE1Y1ALBZh$fE;NBtEBz)n2}T zVkW?c&oTSmh>5~*zD(0H+*PeLQ0${(M}YP5MZqt#RR%}K#?f*XtZNeVI@`mW?Wm1& zW|GaWP%c;-xZf};S7(6_-Rdzcm&S`6>tgN9WFcM zhkh<=(Zd!_rX9qE7qLR+;_s4w;6b3@#v9D_-P}eldAlJrYRY1+d+xNi*+nKNfNFRiS*&#EaOehVOV@+rb$_$?wgw!&(yRNpVBI8 zzx$#8(+MKH#88DaNNfY=47bAXX}qelnSolniS6OQ8H^V?VkaI|*soDWhSmS>`3+-! zdGp=rEOke6#nyj@5#$cN)FrmpIOp=@uTn1XriFv-z`tbOUgDUe*>NPox<7hXY$8Y7EQ*1z50gQ@MDEiE5V9=p;EIQt}QmB{v_i_-VIy3)#+pBP)Xpa%lz9l zkd{`}>INO}{bJ`pUy${jWzCHHUJavwZ#_N=ezgkq$ZLY?Tbp&YHviIZ!E;lFAFtEW zXz)w*7v(C}(lhPOSy!)%KM}%PT%6X(vov!NL@k$fHe{@qH4dHqB% zu8FF-#*NIp6j^I7a?UPl8=A&T?2q~tTiudrNZQZp%bo8$Xy8CN#$?92EMj(^YPTrj zu9mxKcH6#5DX9dq_Qu_xpBpq{H~R^Rao^m!43eO=ScRZEp3Jh}u!hi@@}_tCHYho( zl2AKsvYTz>i^IOyMLkZfhMX^)4iGgLTJZhK^BgKZ+ptDM(3)VQ$iq-VZ2tHT{r&fz z3Y=s+>7JO{0{{Elx!9lel9IA_HaW;7_)l?40Vy z!(tu%9N5EKM0Hmjhod!wlPf8s?yyL&Lv`HuF9tI*%s*1gEY_F3Zg^WB6|}Tzyhoq$ zrrgo4R`E7xYsjgR4+(nGwE9qPmx20O#3D`UkcO-!Xx5>{dBtAsiN3UPY@ZC(P=*K1 zc(IaoFr9vVdZ6vaQ=3#M8zLh+=PX#Grbf2UIwDlP1a3(`5`7Ra*bCD6;V0b`;ffN7 z!!wpS6w$<3UrJ!YaP5#~$)O@BQLRzxxj;XIJiE9uQm$;E+E18SGZE#|@xg$TuF$vL z^xgHB*iw#z9Ceu6BPC1RP$j)RX8P!+h`sX@8=ZxgzV0gbXV18!DD45m)t=>0;v5xM z8t2!b+epV)ck9!2t7N)-8%0As?~nGFcXuC3=*wtUH!@!y9gL318+-^@@&S?izAyxF zdDq9favb^z&3#mx>X_$F(}2KC#pBDgJPdZ+-BNX>3{q$Mwax z)lOYX!m(wfCst!$SZ;}F+aN1l5hBAT(;vtCX7?e*rcru|1TVhruG(K3QJQPh>ne^ z4cGz*bNs2^+Kxg52v|HEnK9GRGZ51fo7mgiaDqS(6MbuEI>QG>eg}IKfKLK!1)==w z{K?r4Yy`yn8GxYwUq25KaV8dGBjVp}9E@y0{QcpF*y?v118}AXxZq!H^c;*2CoKPI zqi6oFEWp431W5kN2ZW#g+s4EQoNN4tkD2Med<^sqZ2zl1HXz9VZ&?Ng=7*!J|L9|4 z{ok~4{I`vPo|zGd%>PT4fq|XZXZJK#?W5Q7vnWknGFKZ}@vv;Y7A diff --git a/lib/CPUs/MIPS/doc/mips_pipeline_stages.pdf b/lib/CPUs/MIPS/doc/mips_pipeline_stages.pdf deleted file mode 100644 index b05de04c9a1193ec42312562184288df8547bd1c..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 9884 zcmbVy2|U!_*MHf{6v|fiQP#u^#@NXovSh7niNRO~Gh=70(PoX5eJe_6u}0QPDikuw zHd0Mlrzo=i???6h_WORH|MNVr$Gm*z-gD16_nh}VpL6d$h??u_OUug0!$do0l8ayp za3tLKj3-P@4RH*Eb0>Ph(STxs(8qccF?cva-`kmp(Z#sM*R`IZa6s@A3bM_n0NPgD0S>zsGyxr=`~Zf5K6eq*dJElpZK z#yPE5X6f40=g`teL;1QIzBvNf0O3w7uw_KF3YZ?*Tb?b^>Qw6>pe)bh_Zy`@Y0N;ZJEYGDeCm|?8{}X z4GcZ>^{DrvTC+y5$5K4EY>gzw)xs&9Q?@&&Y(2}Iu;wj&I_pLWD;ayIY?%hC{K}m6 zmN})GYZ{qrJ}V@p7m}>B*UuG@bU~w#G@!j+rnO#{uyQ#<5p6Stb0CV zXzE=Tso^K=%|lEvrB>#ZZk8On zee<@k!ts%bu_|+Y&Ec1Zdfwkp}>Z|rNK^qMU6l-O2ZKicGO(nze( zu4O|Ol3bI}^-HAt9Y{YdO)ur7-lU`^k$FW`bLO0fLfuJmIV#JqIoA$F=QFX>uC!Hs zqmUWaLRm-=QR5PAz9<@>OWcN>UApwt{vRs}Zx_h!UhVT%s?DWYG}W58r8n$j{$93u zUhS%;l71$^ol=aBJi*h^OS_wlDaCYDb|p4SUy5D({0O^XaQxKCc6x+)%XHvUP66o( zt(9+}7myQH9O}xc^i%H4Z1xa2&oTy3vZ*`}UZDxvwX5Q0pAmpV zl8nH&;OnhY^uFq}yyzh2a4U*E9d)}sFWz`L*RGwu*IXSy#yAx;I+w?>g?8);ScG|K z5x#{VSwB1xy$g`X2u2WPK}`pu{A4@}7U3e51wy-Ni!2Yx*F!SuP8@l1jXb1?TG6#6 z>50@`VU=L*q&@)%p%_q@i1um^>uEFN81pv?eh>KuK!w}~);2KwTnWIUTFIOo9tA<> z&<2bR1E?z(=ZiLhm3#Vl6^fNn=vfMb6nJe1aujI@VLTJmd>EY{zn!K9z-G&VR`uXM z2v3;~AOdM>D9EqjhfK+Q4=hf-4{+aMDgdpOEuAKd2t_&;(zLzBG1f_lqG&|pV*z98 zb>C*x)z3DfFP6INH>f;&dx*cLW~9uc*l)lFU;0*zzq>YtFE65Mhm525cXibB+7wj; z^^V-m|l+H*}*iuSNKMPo5;TLP-*?i&q3!GE zcz?d;P9G>_x#b$cwX7(osnCCAWk`tSx_-DBic?+tisk-s{_CY(x-E&J1rVnJl}w5o>L1d^tS)#|rKB z=VYp}W3}z;{`ua0dE)B_0wQXb@GGv(Dw%l6@Rh~zYv~`)51U1*I_Xc|t?s8%Ypcbi zD()k?$uh-Pnyi!~LYiNuJ(+PVP40DR7Hf};{4q3Pu_EW3?4xbkDt{smVC zM@sk|LyiTy6|Ks}B(-xPgYq=N9)oODgeGGC6ID3byDyF;05a83Nl2Yg!pcwy^E#Tw z^zFXk0!}kA1X(~rW6x;D0eVQ4&_}RUm}_RE?&fQ)d-pYwdr!@Dg7@XJ*mtS2e3PuD zmDES1L*^}YE8QyC!4T(#YAv_c+r71hgibW}z`pPH;wF?+TAcxX43(E}OsZh%$cFs{ zR+0)Y0?%znJ`UQK@XSenXD>N=lDU-{OdvNiPqufCx0c ze+L>2jt`dZ8*(UFLrlTaKvax&rPU0K?gr}V=0T|Mj$)(J%r%K3fO$+)b}fGnr?Za- zLj8nnl={BK`&TCGStVMHzXE>`xX%Nh{H7?S^e~zcr8JtM2}A4O&e-rfengiOnSkC< z-1LxT7%a$#+pKrckWdOJo?Z>df$=pNBR6ZA4Sf1W?wVvheS8t1I>L>o0#oYFjx?BN zwfYDP2(|TYkq)?Tc?Mo701WQ;t21449%NJiSSaRQJrKAa0&rKa1Lo?3h5*@+LpcmI zqBG|p_f5IhhyVoORS9#GD5USlHV96TrNNv+4A7GbL2&@&3;-j@?3Zs)12G>!(lE(N zng&uLkk9zCXxbUixI_EdAVjcsbWWq7=`Rbo2FmWXC)QKjHggK8P|dtGz}@@ z(#ykNY~ah8e#jDb~L)o-5h4)n&O zMyAX)`TFL3Fy||d7La^>UI!fY!qz9#lii0?YF+sHQb01-;f3~3m6Gjb;ckC{zNqPx zk6;58=;J2~vna>rvtqZ>xiCvTD;AtW`u}1A{ii#YKc_I++xk(_B_TMSEU<^7OO$~| z{1?#J4l+708*HM0sfinivIHAbO2H@-P#^WzF6uZ)57sBt8QMk>v(e9KKz2*p&wbP@ zj3OEWyhs6AU6=*hNC73I)r_7w_&KGN{QVz0sW8jxbIbO+5VslT77aVFhra!y{yJ{_ zrf5?q*x&6MzuJS1$_Uz!93^SbTJ6}H+$j!pLR?Cjts&bo<44#@RB+gkw}K8U(O_3> zq%wR1yUEzr8AcU4ny3qH9ZdlCaZ5SufHJDqyG7YzbSxy1XWxbV+IgWf%x*|t2IA<| zTt3re=`gkGa7pOfe70>?mro-?vo~I%MqoTVXn8|1u+4whW>IgMn^Owr3XX#ui3wpB zy7$SUSyH+>(p1mbY{5NGW@Tu=`&mW4W6rAFLP$=tYBJ{g&=s?)o{Del@&&W!+_J~# zbgVw8eENJ2SC}AR;(KvSzH1@!$Jndz7=wP-oMz>^^gLx=hp2Crcc$qEzIosZc2sp= ziq?DE|7z`fPJg@Av(IMPKb(3O9!$mmSdpa9J6ZQKwwsDQ0$)#DDJ zoX#8=HK=>Gv1Ul5R}VGzJNY$~{bBHGcu0-kB=v6y8Rz%kq!1EZ!-;{NN1&-@x{Evq@ld ze$G2Fpf=3SOD$F~JW%19!}&4l%*xmBn-P+P{aIcLkuQf0Eb+o`_N=}d(N0#$DypOV zB#o=S%I7j*#+@eEQ_CfgnfJ)g!qNY^5eNuVIpJNY-5}Y zMZT$wo}XOv96iFO`d}#So8rU8{+^|zlml~vBX<;V1qMHQ8a!T^2|PdX z^o;4ReTkiF;qTcTAuVFBZ|7d@GxRmjy_`Zy(HIZ;_;$_G)X6(JNp)i> z{O&;d>Srfv(+iFo;?moo;bI}h2a%&@z2UiG(^X~*QrFYcEr)`~1f^GPZ>$Dy&Mm$; zI3ySm5r1*Eg@0p5Mv0pS2Iu3x)u0vF3PR z7fTG$4gv1DaD){mm*6e}?d$D|fQEE21Q$HkkLZhsD{raXS~+M0 z2I>ZQ0#V1q84pJ(BaS)$YAY!rY_YCH4}u+BK>@w>3t8}Aeqaz)Q4U%s=!r%v!qKu2 zfJnHUB4jA^QIdyTLvHc@q(Dz)6bj;p790mE7Fe7+m=>pnBVhmPTLzpVLU9I}3}F1d z%3FZ^69H?BW7-DRe_yLR`TK=ZoFz|6UnOXV-@1n) zamKt%?2BL7odVTP;FhnSMHJB>pwRiNI1jC8$3-`c`K-E`jX19KJUA@Ie26g zx!#Z`qiG?z7;nz0v1j8GKk2&%xz=ZNl~{cGP_YYo?tJH@l69*W!xD!v&ubcY^HumQ z-1~EGowPl|Zv+o2m6tKFv5GUX&UNI5Su0;Yj>4EZj(T;t@9g~t=U+eD zVLE+E|1Ouq{WHN;XEEM9A{9>$iHY|;q8(90pSxyx_+r)FGZV)x2ffqUYLmF6D?ZBS zsVBP!bU%r|NywXw%j6x99yZFp;OsJ|^d|rI%qzjmKD}fMr6-|Rq~t?Y<^vW|hVB)e zd?P0A-7Bu=r+;_1wTz#W<1=K&Yw7pWdVCH+^H0QhGP*Ar-G2RG%xZA8V{_^hdUws8 ztn#W`f-6$BdIR1wchZbMNUMn~RBxZjor^p$ZLqk>$|7t|(09=;F>!Mmq`SNSoKTi5oZq zm2%;*@Lg_n7rM3NX&U?0neAZ>GaSOgT03%>UYK4?N!P{=MkDzr%=p_`>V#qL&hq66 z-Q9^xIK?)$zT}<^dBXLEzJ?HL*8TJb-c6C0M>Az|8`P2Tui4ue2i|c!e|FvPh-cH%?96guhpXDFHrCtMEOxcG%PBU&j*sIxUKmjb z%^~ys)8yv7hRLW;QBDsD@1N`#;^@P4rHBmK9fLR4`pkY zc4URotQqFCua2Hos)+Ubk(M!uwM)UW4elK(e?x1>J9VPK@#c@z33Y#`PDu3smpzd{#lN%XiC-C50ZOiarBW@B zOm()>sUhMRNT=oq3xp-Y8l+WcgbTtIfkC(aXM{9WXKpPl88r<|n#HVzKaXdt z=lgV?M`D8;J{Een_o>^1OB%YG%w0$AI8{jDCvqO2IxYWckyY4pW$|Wj z0e3o6&7e0q9yY|CeR^hf&j9!RClus~7vKGylN`*M1IulE%y}4nnooIsgS9i154y>{ znSFnF|4dBJ4LQ|n-ZtmGyWMJJZ6^cF=I%?oC7iA~d2U2k<$WEzugDpjUDy0;@Z>lDE+nD zCl+Bc4mrI+6BK(>t&(BlGVnHRHuU(9gPId9_iRp9Jc)61FrF_TU+3cwtdLbz8#;X| z!)srkwXTU|2{xcXKVvphX0xns(^m09k$#VC=aZ9@)VJJa=~E(!XzNll`4ad2`_3BZ zn{eJph%+rHJ8lKzI+l2Y8w9aS8PSuU%h;sg-AzAF8HMBvMeJpaR;Y}lCPg>Q4F^z% zqIi!oTF70v5pS_xwvn!>aG`qt2jlL7!I%6#H(I`ZrgD66`4VErE^ri+{!xCwt@dXk^n6k<@g^lG5P{BCbg(sh>FYNoDc5B8vi z(Z=C|tPF<@YQv4y#MhqJ`8Uh0Ip2JLL~wb3@9F+@%qi~Y0e2j$WR_nto~>*h#?{Z7 z2JYx0HK^~jf1yBhBfpx`G01U$6*5p*xl8j=*P|!5V!tWI7d>d=o!vg$cDtopkG~Q# zvJ7K8o6?%6modHcF_Ri`M%%MQQm#3}{kdY5ldhmBWmPSFXUGh5b>ysjpy~JL?n$%C z4+@WNnwnM~B;!ss^80V(c_$c$&lH(8i01hpc-M`TEMhd%F7&t}dk~|QBeQ>EW9O=X zV1)F>Nc(&R+uj#CW`Yq+JR`w3l%^eY3Ww6uT+a!!IwfsmWf#6qe`0?~VPWe%r@Oti z9n0k1NvGqxP0xAl?W|!K3_GscFDMdbpWGeJmoDEa?>TF`cSnaxbo{kFnmplmw1vZX zll$-}!x0~w@5@|FgAzZ4n)9M}yxZO-f1r5ZSoF4?%TuNaF(py<@AUSKe&$YS6wQsL zY@;_yiQ)fxTH!mRvZ)1y{!*j+euQJ3?aBQSUi_v{o(&ZSR~J?B+u57HFKQfN4`!MB z^6seZ(oqTagASwFVaJO4Ukf~6?ufAX9!_2DY4s9`h7T!{^T^?di@3R4>NY2vz2*&^ zeBRC7z4x?RZ(6ZJ;7YX3hr{P5TyL_Sj4abO?X?$Qe{aC-8hUIkPOv|Dcl2X_hfCf! z%7+W9tq+hKpH~gjwucJ&f2<2im!j|us&Aq`x=RrhLK{X`DzP00DieoRW>cSWKN`JV z>ne#qS>ohSU$B1(ad;U{HS0o8TA=cGc^&&vbGP#LM$B6A3w)UR+w(?>^TW?3WRdv> zSKcY06WZ#hW*?t39z+d_4ur<+pbFt%sg>PZX^A45IstgyDMSA?wBCqTUx_n}D z#)G>f>+`L^^H=H3ez5i2UO!M}VOxItl4y+(PjrO;;iS*(r#W{wMQ}L2y>ay!r-{SO z3kLR&rWGgjcHZ(0c}WbnoLhf=g>X-Y(cO8)0e>8x zd{c*kX<(F+tC~<3N#PQA7-My3c6=<-iVbEft}?EoB|WB{zxqV}%Shm{j;Hfx^Nr!! zvhz$A$>$C=Pp=*8Q$`%l;Sop;-?!Gbncc|7>3F$2#g9u&q5mCvnIn0wDd-lhY+~cZ z{lZ5hSD8ghZNHSW>9?Ptc|C-^z@=Sw8MAPpd#3w*=|mEB)~O|O@+5A-nlwGREA#Ch z>H}2dSEg#`NhUp^2CK$`M|zrmI#d_t&s`VQIFZy>=W`9%1T|~RnH(lgKf2_mb}DH) z>=;g;|Kl#vl&-)*>1)dJgf3mZ`4LoGt0P5fxUlx*0sXYv?Cx7K&Bw1DIm6F>R(b8& z`+E&eZjworN=r8Mp1R^vp1jIZ7vGU9?0tF^Dh~(KV^f{8C;Qg~9_KeXJvMPR($2CJ z-d0l}6~<;Iq*_zFS8JQN*gYl9^Ygc|6Ju$umxf-YRw>5rrt7UC9@@|eb);pVVx}5q z?fkBO!=^phv3a=8*P+m|*}WUh_w3_JaFxyw?Q715Br^ANXU*x{C2cOeRt?BRvMUlkXyW3T#;E+#NdF@FPRJ zE>nzyr8CXPH{RWAdRT5et}9jFC4~~kN8U+A=5MgSd4o=T`Bh=RL2K6F!^Vu%(S@tw zrAeMHM;&%fsQVOVj~tl2at`OO+OjuB$L`BvI%-ME=V02StVIJfh9kure@>TPAKu<9wf2XPPj z_;kKckUe)8%y->9Lapb^^opdL!@Io^3qepr-VEW zmtMcZz4BZ}X+$&{X2#vJ?fTXG`w+(XIAQ)r6Yo?{FgYW8^mt2lzHiVxyl#^hp;8l5 z?RsgxBkPM23&IX9j0*p3mco2ZflcUpz#f)iRgpUmBQJt{=V-3du8CKBq#kvU{fq`z z3mk5XT~>N%d;o`~Hm=HwIz^D`*I!&-Y11Uj{6@53^InFKWkPy>6lQj>Qvfo8c8^BQF`t~oX(BPV-inNb#xC-&~7<$M^|&# zzd0uKIp$!pNC5Ke`1uCAg{TAcUq(|~oK*a~hmxWUkOh=0Q)wT=Ei!@{S@;yWrD&8& zzu?bCvw88CFC+$=t}M$+FjuIZB4)&9K2i)JKmM`za@u7vv#uuEo$2Z4L0qn0!S`|& zzcsR-For2`?~wFA(0+WUSyLQG{vHXws~$TYci-Q0OnZ;RE?EKOg|JE{{~%G^ZEF6J zm!d~?_nbXl#LnKSy=O_KKRVXSus6**v3TF)RgaN!rsLmBGylFDK((}AR|8NUbq#RA;3W*qkHHN* zd&kw|gCX5#Dm zKX6!KiQX6qAFLn2$q(y?@djsfCjt>vcL~2|@x@E%<1rYhPK%O3%EG1L9z>#_3Iaj! zIO7{EVcv7s1%DI8SU zeL)=?gp36oVTg0{h5ss<8|uRC)D-pgbWzH>`baIb9vX#4D(EU}Dd{WdYU%4D6=YHR c8viqg15{lHp@1iDEu=Dl2PP`2XQmJPe*%M9uK)l5 diff --git a/lib/CPUs/MIPS/doc/mips_sys.vsd b/lib/CPUs/MIPS/doc/mips_sys.vsd deleted file mode 100644 index 6c62de1cc6e753bb037a772f9defe822a63850af..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 30720 zcmeHw2|!av^Z2}%lgor#@klsSpke}eUx}!IiVbpzTH62$f+9h{TN^}FJSr+4t<}b( zwjTYAXRTI^xAjvSk6K%`jkh9dB8Vsg?>`%S7Wt&V`m4Qu-+$YAyKl2^cXnrHcXnoI zPa7SttlHvn73!pJz=3MU2Kcq=DJ&DPCNY2;7RY-w!!R|K09gG0=^wNLRfuaRBpwHW zi@-x5G#4NU5o{1_5$q7`5gZU2Aczo<1;7!(3Beh`1;G`8@B<5t@ZAHUF+vlBrU=at zBnVOjPXsRnZv-EN<_IkiS|a!&_#yZsyoJyTApoH@f(${95Qq?j5RA|Up)Eo?g!Tv> z5IQ2Txcr02@~5F11seP(8)?xC(lO733AkdvJ-H#ru*lN*nUe>30_?XwA+#o|dFCv1 z74%pAn{p?wHO*iEq(T;g26`e4g)uM+lB}52{<8jZ6QC(FKH*)G*WdD&U&zos34>wc zL9}(uQIKGrdv6>&88OL3JQ8p{2xjRuO<(!+#qr4=NaW|Yj^7a5e$}IfI6UL>c4|gEqjtMa%Ym`T!Tt~sMQI$ZW zV1_*Z?*6d54>=8sN^r<&z&tKtN}pK-)RTuWE9dS*H*Ss_a#SP8VPOCM{c!8nEe1}V zItAOdZ8O8NWy?Gv2a=iOWa!tg9|UWIgTcdt>=GmqN|M9{rXemVoK?YS`DI2Zx>})v zM#UBr6@yz+v1J%&LE1etH6hIp_EG`-8@Q2l;?WfWv`a9@DJFGP5|br;J87IWN)tCK zA>9u=1Ly|9w3ephaF)Yn0w)XF#uQt+-zhzmxUsfNxOPjp_Di@9_|jkrSG0sHUcz-;!d>gMgzG$3 zGEXdsgoKSy-9t)+dDCIuoDE^#+%Rumm^VMnTVM&3o|W8i);4PaRZRG2-norcRQytx z{XX=5pS_&@p55pwW_Qca8CXKEf%oV<2Kv#T!aZsw18u08a2RGVFdL@heqY$FJ)SC` z(y3FS8#N`vR4Hx=^4Qiv(~c=I^B_f+1M^Z^qwdK*?f$B z@3wQDzvo5-tyeIr9A3sx3bSIcWP9V8Fp!e32<5fo!Z#ntU4kQ(OBHj~Un@2bxWG9? zL%SY}!yJHi1ZtE@`!)p~`JJdwRGU=?Ro|&@^&2s0I%jxfABFOwda|T?(ELg}O;Zhu zN>Gzy4x`V-f1x<5xslx3^+s~cTT#^`=;{%i>ftj5ZNg~CbAWvLr5NhE`pROBAXOD= za+vQeS2dR0**^8{k(oBPdgRfTkH;*qsiOI9X&3_IjsuUJ&;G@hD%+wAE*|21=w}}y zrGTS!1&%--#|1A_hWEn^pAadpxdZUKYooPE6W5OKALc6=G2i>F!;IjuZ5-fnM&B5Y zE6wpNxc-FGk>9=5boc1FONGT2+dxVnmpZi_!~ej^H|WN&J#7QW1xoFftfE}GBLkL8YprvSXCfRny7#=+L_u^0hR3_Npb~VJ9=bfA6J-Put^8o zXYH3BDmY(oMw72EORV6H2pSh-p3&uLK~U!G)l&~RFZp5ZzJ%S0#g-Ytfy&Oh0XnsA zv~HU2T$E=^J#^If)xWFP=x6JX?)%DThm&&i`iW|Z!Pn5qa8Mm)&QZ<}KCJ(K!_K7Z z8=tQ0!^?qThOvfx!!pAchGT})hHD1+N}p)VHqJ1DL1b)b^fz+D4X0zhb;d2mL&o#Q z+eV;Gh5EI6nP~#QkLjy~9RSxiDz9Xl3QQlGHkkI9P7b1cE}8C|7?Y#f+uY4;XM(1t zk>)Ap0`n^KHuJaU3ua-F`I*@`pt(Ea$8=`;F`#B9GSisFOsTLrMOX+{|@+4y}G;2oBVR)7n zq7I@yqANp0>7pFbLeX;0T;Mz#_r#{bynO0Ofq?aNI%-@}dX_U}VP{o|MI{j}3Xcy9Vu}pAhqPXL;^xk4iauqfim$3l4NUIi%9B)T zk%1{`_2IIVCf5~@UAT$|O*sZj`7=}1`v%VbHawG=-Q*2?X zOSo`>4}z-|)Kd!uQ&OA>t-hk}lro`Ltkhzv6s-jPYQ}%62(=9+*cqhT#I#+L5Jf1l!n@v9jppt)n{ceLgAu|e~6gcHHkFKIAj+4LGPV6ssM6kGv zn{!3{OF-vDD4A+pC#H(2exw%L+J)snyrPGO$(WFtIy?nQ;M>Db8rZR8dq!HLh4f%F znHieQgzQvClipe??Vgs#BuSrBP&!tVnV6K4z@%j-rMHG^_v%cD7iFa+WF#@IQ_?a# zy*tVoxg4t3KoDihgT~ay)u@$~ucOkQP_cNKm>lBji0CIkb*XqURqjlei$iaf30qJ@ z!9ElIg*?ftZX#Vz8Nl1i_Nj$Oi)|NnmU8^XoupJZfs>4a=B>Jk2FqG`4)YYYd|&3{ zw|)6r4Fq;MM~Z9r1lRI&)Eo9%B9=OrTOL3AqG75n!v1T;5+q_j?M%r z<3kDgueyZHXJ)@`cUZn7}=8C16LCiT{3OQ0_zDk>`RdETHGX>bEa z&BX?^0O0Aw%MAIF2hAAN)|U%8)cz`)d!@&*uSX_rC3M1ue3Tjm>ZyCyFc3TPEpRWk z^bCf}s5H#&%pPRM@y0^$a&&8 z{5sfFNPK12pZLS~ddeR<^_H&fC3TUYG95)Tu4I=v*AyQ1EVfuIl?-4{40dJhNsC>P zo~oG#x5}DAC^;Uua{$i_j@c5y@fU#^d#TZN%i#;ubwiQpj1M7t=%7}N+Z;mm(D~Zu zC&*kL^ZW$yb^cWG2|pRc14Kt~J>De;2+$J*)mNc6HI4s(qUYj+vzX7+93cR^8#)S_ zx(E}w5+|FbiDGy_aX-N(yrW&+K`Iptlz8%m!YkdVF`Puncfv+uNR;MEoT&AVRg@>+ z)@hdq7lF6Sy^)hp;!+~M3NcgMA5b=wzwIs$yIt-P1(LSSEsF4fuD+3H?0l|LyFBpU zuUsuQ&L6idwi&3>FT@9p__u_|Lfg#n7-#M8o>yVUz~=KhidrVEc_r5E9t9*mBs%qNogJ zs4Mi4cGXGOAf2)qc$vOPg|}}rD{z}MKgf?e92Nxg@`Idu$!7&F^#DPBkk_Z;S%LmH z`eH@UB7AfLy9fC}Az+^$)CU|g^Mj(Uz^uT*Aj%KgmFR~JMu1~}Q0CaOZR-R2( zCUuWJn5^8LtlXNc+>oq{U7f64maJTutelN6xyj0j$;!-R&2dB*Vf$bC*of5d}{d)f{Un-RRK%^jNO z9Eg`Uv}YbGl#!pGE6Qd%xhs`l;mORLxLKl5o;H`OQOz+cX2o1v5Gyb#`j3*08<6ik zHFmr6y4kS@oeN{DPc;yqmhvAD2MQGz6t}!$nCd9!UW3(;_K9~O9wYhR2?xt43TDN1 z*DQ$Z9pAo1s^-H+adTkcviP3M;^oWY-)-Wf6u_+E!1sz@>pQ+p>mPYnEBd*@Fjde~ z#qK#V5j-YY&KrHX=gJPvmk+p6&WrCQ_puw!i>GW-)uT*$`1swc=FrjEX}z=~vp$0C z4S5;yc^MIT86EO6xT`;t=U;)Q@fvWw{-g&J8QZ|OU+>6hT|l58q<$t(r`o)K&JOTK z6%>0hv-gpV_$!p)$FZgT7uhD*fnUCy?lL%w>Zew}Tehb|^SlXBZc1f@eQxYeNy@v6 zVt*RCI&$DN*r=ZD*>!rpcj)x(&Oap`bY3)Yda1g}X{pdQ@!MREpIv$8#azlYb(5E- zjRr!8s%ALp2Fx6t+DTWSS*6*$ZB!Qb-z0pgT7CUV&z@1X(LJM>?)_|gXwtJYC7QIf zq|CiqqxPycw{#+>%iyz8#{%zy4$W`8Hy@f6G*;%s?U@rxU0D7#Ox?Co zf-N8FHs~TK&H)_^{?cyJv0cqaAKT@3YEb9g9KN30)%BFfl%dbncZ7Dz8|4GS zx^L9))k}@~tNMy8yZCMcxk7`7!8Uki?u00QSHpsVgTGv>R*r4ycXOuUqrJuIgR=y- ziTvHyI1c5RN3Z>Cuo$9@;9}%eOwmlz#2HhKlZ+K-gbR#oj1d%fxACOWC3ANXG#|aY zs7Y1arRZ_4qmLFfAHDKu(Yso%XryV1$sw>q?9A>_G3!lVn@*WZC-Uenk+d>u(SmJ9 ziYR_D%eVmIN-f~ZCi5^Do6!nA>vE zg5kjqEvl6v0}4xiRCu`myeLZ2$Q_0Uw{0=;dSlo8>*38eOiOR!>DE+U<+Q}R(wSc< zt#r;^9zaz&9rRw^lJEVEKPX@Y_)^njER7TN9Qc{Ka&yrqJZj&Ua@6yvYO$Q^n*eTs zbYpo>hWbLDvqF5(t@8B5>yzEQCGERf7M&FL?K~$`Jo`Om+Cxr=TYPw8{~ttmMU}Sl zMT;Jci+fNuvANh;shl2PSW+Y|zu%^dRN>Z85zsT{ndj5=j3@~VlZ=(*OO{E#knEG3 zmRyrq9=Q$ePkA2;;i19Dw22seT>Tv!hI|SemApiUEg}4}?oY-HYV0JIDU!RJio_o_RpiZH)hjorZSmSjj~ zahG>0&ZPE_$&GslVhYB^p2^Igb~YO-{&p2x7t<7M)xQ07VF$raSREWdBVerP;!6`T@XX(~7mhxuiq z*r#}CZD=9x*+MLDA#Sp1zo5_7gZxe4+Z*m5XnppP$HU@&?Y*8V+;}GrojlOe7Dg|- za{s_eS65&D!m_)t*oIvHZHgUCdF@ZPbTFTFgeGSs<<1{%glw@iUM!6eOFPUKOS#LX z`C)jsd17&`{^6T;ZTf}S_Ux&R3W)074^o#)OYR?N)5WIpDmk$hCVL&JgfL2w)Iv)w za zLpPdseHP-wv}3}Vc}yDf{=>*itqYm8%txc_zp1eQp5fkMD$1wcPI3@QM1i6n0_n5Z zSkZ921P9N3U$QsM;A87QsZ&WlB5EL9_+dDm5k(8O7Ff^&R>>XLoD4Ev(qP#%1 zO14c_K6o>nliie+%WM>l6#)u`qQ3%$D#j>gDn3%2{p@03(K-FX{6mWKirejTD`N*{ zfiedwW9=hWCS-JXTkYG|O&=Z#C;Mk~k61mXI6^;Xhkjws8rW30>DpBNk*oTJU#yw? z`B#Oob;Cu~>|q~gZJfwgH&pwpp^G|K9k0$*_cbh0uT$?jz-#bLMT1jnle(h3;wV=G zZW>=r4?#q6lxCP_tY!g4iMS;*4=&ZL*C-9AG$su^)Nr(}+Lqc7k7HZN-as#z+8|3i zUAxk0=J73#Gmqzdg*(G#?Ew=MI2Cjo-MBjZM@@QawkFfo)IlyE->$=zpf=*31p^9F z3bg*B{DNf#Ulf34}a!NUTM&Q;e^*HH(3b?@plx~aNC-G=sgS9Z3Meo?YdcUpJ5 z{o^m+e%AK!mtY?;`gF$-XWF-~vnV|D*cQm>-kW}}Z*S52y}l@!!r52~3s=7{TEFUx zlJ%Tff*qxLTR5+uet5~b&n{91XG3#Cdqd6?!#jpihH%LO!y3cx{^EnXcZCmhNxh?PpXb+*`cZIj7P!_7Jam^U?;*M;r4KoVd5? zJTI!yxYpQB!fm-n2KFt@$8X3SOcGPzPlp|QnYeML!mHwRlY5Jmw=V`1p9S|;7tR!( z$@5!-@E~BNVnfwWt>`Na-RC*!?(}5FB&6AfMfO%jb~i_xlgtxmJMP}?ctq0Xg5+V` z`@Iq$E1pRlWH}O9$CMqtddddKQe?Tqo#8ee8b!E^qc|eFAS;r=Gns=zqG)q*M)wd! zjH2)=V|L(z(tYUMOS;TlU5X|&q z;+Rxs67vDGdRbV;m92|3xnDD zf$ypT2fO%j;OLAAv?jMjVfwU%t6S>UuL4bORAJE4@zVw_3wkFfpqjF)q_~YeoF&aA z?Ilwr%6BBA9GASGD_JC2zt=fj3xl<3T7AR^TAg-__K^0x7H(^wYV8V|7RU;^7ep7V zE{Far^^YcOeZOFS!RnbiLU+u79ihkOx^D@hu57(N=Zb-|1gd*CTs~o|{LuJq1$3bC zGYTeb9dfA4vD|Hm|DL1^9rTe7HtP23j5=3+sg9?=Z}ii_Y zH?6OBWFOacQTk!}v0n%$kGc8Ld7sD+*N$$c;C{8f>5(;tlY01BZ_(2R7efm}2SXnN zTD^wlKeS}#HF6@h_0=;!{Qk3J)0HXL~9?_+|6DXt4Sqg`7aY~=K%GcrBKrNT zJjb@}MZHB||7)aZiUz zmos^L%)+EIGY55;ZzguzIr2O(*{*K$ctg9$+`O;l`!fHXDgH)#QG0JS%z@ZSFXdq`-%Y?ovgNqNf6WK0SR$t7-FgXcSWwjlv2K?C|*H0PS{=!~LYgYS^IIqxcpr zrF_*GqnpZCB|Z3Hz!sG%K{c^|qw%4Fc0RLJjt9W)xYK^h?f42+q3)pWqrO(@k*0oMJ%7k9c?;h3FY#uODRvH1 zD&xO?Z}9cA>Zg-V!yR>n+FsL4BiDpz1iEAmbkvF6?5;F%2`*W!*{+Fje=_|`wcGSB zW1lPj<6Xb~dY)V34^Z(Rumu(W9i^<|uP@>3V2+hQ!06zTyQM*;A(_R@AS~~9<2)|! zQrg5;yvO;ZKh+);|7DXs=#ARFTKJbvr!Uoh1cM(0>)$Fk6ws@2@7;~#45@}mJ3Y6? zQjfA93Ds4ZmS{Y!IGklAU|qiSjZ+8{-PmK;sDGWaB*JO5;|eRMFep z@jK%!qsP_8RYs8sma8V2lFoXax!x!UVT9>4rI>fAy!W~b_ATy2#d!Ak#&pqi&-C8l zCidoLW{{h;d!~Om*qmm5-#p*E+MKi9eAN7d`L4Or+<=iXbj}(1l3`CnLYNrl=AX&A~yOhd*y{e|Zr#z!4`N~zVyO77-~$1}j9@8^OCGjcBTd)ZR;_Vp(enorRJdkDVEs)AxWjMT8W02~LVC(O02hD*|N zs}-9Vv6&l^YG{q$mJu_yghD@xir*6L)r=G$ulD;HYW#i}f`G9w{N<3xiLNqZgq95~ zvupEAIIJm#Y_+1O^rraaG==VME;Ebzif)xrY9T#T_;XdHB&zp-Yx2pWwYZ9Hj*D)T zV|0hOym3ymfvpakzx>K5o9w@OEBHM7lH{Wd8(^_)#v3$YjQ(Cz)Fh-OjnJAen z`9!i=a!~S}1a3*5NNi1E{eAm zRY)mwbibHBQsoq=H(c9RH628cw9f7k?h`o0PBObo^uI!Uh4W57`M6#3AZK^gxp zlt<1CN-vbpz&J1_Dk)2oHpc2bf?&CPSO${{kqN_-qEi(UlOQ4~+lD$ESRR!$d{-d! zPS0S*WJjlIvZ03{AuH?Kz(@tB@3R>CR#{{M1#wJLswqhtk($n=CP7pZg-DT56Y0dH zbS679H7OIntD0cT(U+#Mt?BQ;^;v zX%vi2t;(Vysn3{E8NdX~DF{V9Xjl4M=-q$_O+_hGegO6yX$NUWcI!uuLILrB5D(_< zp(D{VahTUS2nwO!Q_E?7@ILBWVVf@9IH&o6a%lSjfcv;0Xz$?B20A);nA<^MMzu|Q z2>!WiqaZnS?B@{#Q^J3;32Fz?DL>m($?Z@;`b7k^VQO~c?4%u|iY?I-pnK+O_n4~G zO|HRkkP3#_eS5{b_lm#VE8eRP2 z+Fo#!s_I!(f+qM^%WF9WbeV;Vi!~0tqopXC_O~BxvZw5zbz^Ag03FavlyduBZ$A;l-B#WD45L6eKdXhNLoJ2mNb|O<{=wlMgG>~t>sI1AMD6iJ= zsBF>Y<)UKCDX_nfONTy*{U~g|q^$3#TV-ZEd^k+WF&h~ExJ)eixyttmbIHZKV$pS_ zukm=VhRP0fn+B7Q|5#c2q^LxmFbL^m-6+xFb|S74Iuu(llFI$|qw{kyR$-cOQ31Ch zXwO1gMI|i9=o1XqXn~k7FNve6>SBv$vBl$aFlC>tL_N)t$3@v-ARcZMJV-+^XtEQ2 zi1skR8Z0Y{Eln%NL6=Fe2AzDN8;UJHw;vTTU|(#JhTMKs#=t`AAUc$)Bra8cJ7I1i zhvM0xU-K5mYK?=m5ph+Jd=SEmEsb}AIx?&=Y&r<>W=mBNCFY*yQVqPZ?KHDRF%I(1 zV%sx(v834YZ%V9=`3T)(eDT_1%Z{Go;L#+puDOfziG4ePE9OuJowz+lpmn|d=&?@h zL_%!-u?aglGQ zgg@%kNs)mrV?8Rcc%A?#5isS1%o9;aBoI89O>D72`szY)n2S)nxd730W8n6%b9rM6zD|N*dtzWL#?_ zJO$Z9aFjLLy(Z=ak6g&dHn zRIdTOd&Nc9w6)fg>WJQN_YLVD-Rt=`wdda*>&V_%I0$D4vE@TbHBM{o;A&|A6k3crd zPoKY&ITJ#WZ~9l52ak_`4dv%z6`7p^G4F|;O~BvS zB#gqW`Cy!{F1I6K7jEe7#dT(z~ zVO>v*MNfcnsQjj5{A*1j!&)cs{GF@-dEbnM?I>0)uuT5ig6*EovC8@v7C5~1H}aPo zq)g^Yq_K9N9_=z|#^3KxZpFpSC$UtOH_fY8AIn74CyT>6A z#h;D*N8W$$oNB9lY+r;&-=sXT{noecq@Hb4du&pUL-0XJLl}beC3{r{=0v{6Lb9-v zO|p>v7TMrMKmU`=k-dyf?Dw_DCjI~3eT40oS4;kD?+c`!ZBu*f+Vft9FUxUaD>3i! zeBLW4rEmqMdqMkOn>X7(S&!GHDZ!(5V*4WXWRGlxFdtvKV&@w%PsSXN6D)T{{E~(9 zF(+mAJ6^4IAbqg)1h?AdKMGGGM+DE+m=iqbQ>z6ls0o6Nn3FP#!>{34cklkE@KFau zl<-kE%vnC_%uxzEbN(KD6o7aUJ_^U2<)d&;SHv$_7=Sq`{}%eNZ3s{O5qw1OBz#2h zWcet7vs%y@_vLWRNtwmr{~{k{;h9AEXaeReAC2WJg=6`D4?apkya*pn!<^-#Y5cB; zU$QU-b5i~-^kLilQG7)3Bz#2hWcetCzgjSsKS3}Jb5dq;_`k?UVq93lM{bz2eB>-t z3Y~?24?f}{UWAXN2rM5-gtNyak%i~fORUP}Q11@|zIKr)ZT z1AqTt-Lr7Zev#O|-t?T?z1QguaG=cvf*&uo>kqx59va->c6Tt7x`FqF)(GQ7i5dDyqjc|@X;upmaz?_tS z3(v7_{wUcXcoKdhc(Sq)z?sKGeVZ4KIVrO^V6(raY$W0)NMwW9eOTE@#53ctkbr`l zh-U|Rf7Lu{-^0lo`=X4q`)6Hw$0d4^*uKbq__}-RubqW#zqQx8Hjbp8ZBu(}QfAK$ zqEivsAUYK*8_vQ2zO(S}Asa+jA+kYq6;?K+LVv_BiqFHGl-W6w`TFAASemf)`00yv zAm!Jk0a>rwiS3uvv*#PZlkgM4la&pga2^kJKb{nGQf9xyX7%D(myc?X&3;enUUv?^ z#z(B}+G;;UTbb2nA6VP60i}pi=C>yjNB22Jl@u)qI+I&aW*cZQL>F`(1=^o+{ zg>$mn+U3`kmD)0g-M;9T)U)z#JqvLl>sg37 z!4uCvtL+KTLbN~4d$FFi<)kj2b!Fq9!bil$oR9NfiMjkaAFZGQY*tWz4?ZF`X2M6r zc1z@+&}Sp%hxkR=%*ULRSswW{`mk*XPyG>mMDQfG0)pqf=X^AunrF3zZ^WFGSsZ>1 z&$@hs-MvWc_oVK1=kQz34Wd(#HMaWFp6{{fJF`V!8bXu}`qB{od-hnXPKC6z>Qv8V z1NAAi0|mU`xxaFcwdyK}pH)|R&U2`rSnX7(tDvpwKY7j?{J7ed_N|0BJyt46Q9ewROn}edZG;vb5dsU!Ku8YpRn}=&%aWR4kKbj zj;wz6=W>L8bzAhaBShJtpB>@9M~`2DdB{}lb}Jgx`vgkGNX?TYv%3r}E9%D;u@*f!YJAEJK|JPAJ$JXv4J3GQma56DZmFehae2jscG<+)*% z4U}uEY&<_VP!?=aHV~q0P&N?$d(I6a8{}?6WP`n%{J;&c`GNcQxSJ53Bl|JoIreUH zi|dE@McJIdoRohH&#`U(NZBB=OYmgxCMUS_tTKEHb5dq;_%+!eQN}I^B#{_PQpPTU zLkX?>xSjQqfjxjdz13lx4GswvSjXOBNZSB>AvsOa)^8}9L}sGkLM67W@f6my!~e7_ z*7|UGuZ+8_`QqiCX=~3G{O=moj7%`8>67h|B4FbuZJJ^dA}@vFTcMEKQ@xDK74BGYw&xuwA9Rq#gk~HKKNhzsvCh<^E-Y&ZU1#6$m;9=&t6Y9va1H4 zH@BX3BeLq7@Bel^>qb)5*Z-fro@|8En_kblkxBK<_kX*dbt8)E>z`fEm(S$iy1#R4 zovHsB{qype?B4p+7Fg&)+K>ukyCOJZAlJ`Df9R^?=sk_2y)wuIKXQ zdH;UdsOv?num3ki%U5~)ULNzWrzPu!d(*V6>pgpU-oKxgb-iBo_5Y@5`6>_9%VYla zv}C~My*)3_`}fnbu9v31{@)-i|HGs5@|b@ITGn_u-aIW|_D;M!?>9lqm%R%0 z_0OJFtWEa!=D+;^7hm`Pd{{HG7sgMb@8L!IE%*=*1o_L5Ho!Wx6a&e z)o((>ko>}YyWc)d7yFW@o~)fl*@XwJEuse7u}4lPcs`iKA@=h%3=Ll|iSD)8=YME7 zVC1Z1?}uKtZ4>1iO-FgUjJM*7EGqABj2C2wU!EWj>4mMoqhC)RlVCLG3-~%aGA)P@3ceU}P+yeiHlKdf4>9&k zylw6GWs`|eo{@qgZskW}8iaJDw$#KAPWy;hT=S&oO5=&+_=hWU|& z+)r;z4w-$dSACM%#R(>mcW9JJ-Uw)en^+niM&Axx(Yw zF=#KpK4s|*jU*f_m|P<$CX z7hUXK$1D&2#??y4OnsAZs^?_I8)B%xO2&D{nHs3ksF(6#Ov)|w=mme+p_5-SUx|;< z+hlF=4cEY@&ad=h4@$E>;#Ze@6*NDr^<3er9-Ud4+KiZ0M+;YSN`8VtiZ}hE6~*jW zjN*Ja@mKng;Gqi!!(II%4T0Hjf;^XuH#(;mQ$ms&dgC_FIb}^RGLd%PV)HQ14%&C9 z1~{#Djva|&S$I*`V3Z82uRODKvih)-J@)aA5NFJB-yY^|!`Jea^xoq1N}C-PqZQnI zBduof0YEC@Yi;hwGkKr$Uo+iIi&@uE-Ip*pTMljeSWd4z*aL0*T0yUTs|p-f`qmw^ zUucE4eY0deEALl#u*hnYOT{ODV=2pq?NKHWO!h2d;#J(b6=osqrL!`iEMJ@R$cGbM!LQ)Ajmc z=ZDVcn~VvG5pv}3YYn~>7+JG@lh`A6?hE2fz1ErndaVI_O-5?|wp*?>@rfXzOhTrw zlRexuQYOjs{R3f09>?+L_g}#ce|2;4g>@mBn*`IVo<+!ZoS%~Lw8TayN%1lWIt_9o zxfue?rFG)(y>kpz_QD>2AW@(gTfBkBm~r;CK3_)(JLxq~Juaz~wvuzlzKuI{MR8O` zVAAq9bv(A!Z|-CCx_snnv=cT|`yt0W^+G)V{*DN?-Cp7QedNsGiekxR0bIov+ll( zin9F5{GfVEan)uM(ts2JnikEZR9od;jFih7%oJ`RZ_3U-(va_ z3Mo<+kr^hY^q+GN&!Bs;RF_jU>EAS2I~o{OszZJCjGi~FYg#hbXFJCSvBvfdm<=61 zL$t)cwKRNyw4T4^=v$MXIOHXG4o1GSF)<+XsS{h*u0Srl0uyjCS zAQu@=q(YIjx&o5%6p|;|9!~))jscluZ-l2>0$@#o0>*eBDk!J!L)A3e6NS?hf+89u zP#g~58-PU!PzA@JMhcWxybK{A>9>D06MqylP#fqVbk9Qy6woF(P@t9&n*W9nYbdC} zlcw@-C;!$#GxNJ3{-Ht@N5#34oc`4H$1?urNBuAV-|j;IeFI%6Tv742b9<}#t=SL- zp~)Hkt!8g|f6k&I=>MIi4S!Fn;3#-nKmc8J11+qwxE9{k3r{83ZcNnL<@{#*v{&1fYZa-G?LKfEmGo>P)eOAW$?z|9m5nNGPrSLHpf< z$jHb-|J}f?{}=TidLS^UtSoA;p%4fttfzkLwE6#Sp9+{qU>Zpx;AkjH z77Ua$+?sX;bD}_z(hxwIVo%E?kP0RN&Rq*naB}`Vq-{KHjwT8Lu;7s;*eesAT)_l{ z07g{2n<FA30!JU^4rndvgWz;Zo-Ku;~lM z_X1*Xn^hZ4C6$9?ZUdJr-LBM-`T|!+v0tui{n{#M`81tM=^Axf92;#IdmA!rPYRqlv(YlOy?E~G)4|80@0K&$ zqOx2H(#^B`l7lyxDw0r~c^g+FO*^yk8shiue0CErWnIYXUS85DO*Snx&u^dPNRqD@ zeatex%&c*FXsc=F_Zwa_?C4C|@lZ%;`gLZM54e zN4jP^N!lS9_4xr{a;uizOgdmLF_yb743+=-jg-=z549KU#rnivhuPTW4di&(q`!RJ z&AI(m;WjFdF-9ZS)QvpkiJ$6PUvE$=kdW$&tLfq%w)r(-V=tRqvC&v2UELxmq^OF$ zE4ohgR1PyGY%ARf$XMBJj?Bopm$>Py>ZS9vJH}QDYZxbK8Z(oX^FDWj@HHs{qn)idg^tr1$>F`TQpS~Zpdk<-{tFSOr2He^52n5Q{r7C--0r} zDTAb+xb!YK(EkSWCmXKXk=$eU`iB-5y2An-E;T}LHCSS5Q}*kBVf8-}*(UIKOuXD@ z% z@n$@(C5_}{@8pAnyk)$KJ^gOMFIvmfmbdi!O!_ZLrHQwt_H$WvUbs2*O5dthiB2Z2 zFTcUyQQOX0mXc?I9^>bDB|_EO>8aHD#!}U+)3XMAh6V5HEnOsfiymq#UU)g?QA~e9 z(CJ-?34_klmDT;rg&9HoIp2R}uv5aYRWAH?Sm|j~{+!stg^*S~Hs0fT7;t#qXZq@0=%#lo5Sm zOV{*^_2<)*AKCqVf1+Bt*j{GFkDb1uIJ=|wCXQovf;?8%J(_eA z_yeQI4t=sPhb!!hit%ssrkg^%mb>H4sQgjWFLTQK_R$OPg0C^#@F|opj`!s!53qzu zQ6BUYF=igF3la` zYpj;v8}D*s#uv{Piq!~zHm^+{#A$CuFevtzHT5Vr?O@kaLb`6>(K5X5t1YA@-=%hM>b-}(Kea32a&US9)mnIt$a&$m*Wa*S3yYVxsZx8n{$#-Kj zBepDJa6=@Jx%%Pe?0jp-oqh+)GL}TCj5_DF>Eut;oEXgCOva_X7}UjF_uO?G`FVb5{!4$)qfvp z{+_;rsgBj-2zA%C6o&7I)~(7F>-_yZR#;Sc*Zdo=*>YBXR9BgR8bF{6hiZ&MF-N54 zPTsC~8)&CvXvcXYu$IWWE8`R@H*p{^fH{o9UT6p5LEe3~?%~Y!Wa&6>e;C1ME143S z{I+d!QTsbWx!uz`QRTj@?a!F+_bj4bFxC>~{lvV>pl4-O)x;&|Zp8BXtxtTM5|$a$ zea?FRO(eIrT~eTv{52kpU?+bhYzwP1y}m&oCc-HB6pAXs-AP1XRDRs_K-Yx9+G{Hs8y`n`Pe> zx>-WU zl_TC95YWDo_%o^2<43qd`S-==HJ_%$C< z-kiIffZm3yHt}Pwroy2gwX~a&kd0g z&fK{BVHa(xZB4k7!Vzm6eH;Nlcfxd?4lffg3_tXjUbJeOJiwZ+w^ET+Up?`8Nr=km zi68!{6tSC)bN4anW}_z7jlKVVuvphZIoaXzfqRB=1J3IS(xW6jC6>N{YD)o}Thyaq zkFwzWcSY<8qh2Ogq6$x)fJgDE@D{S|zG02tPW@tjKf$S(ji-eeN$rrJhN^zi6mWq$ zRaa>ruru-)dow)3z=)^UjQfzL{j^vi;i>(ujjFAXPN-s+ZH&%A|+*Cn?(}Yl~|b05-punI{KS5Ak_x@8D}iy?$+I>2G^Cm0%xx*Vj=q zH>QtxW-zTiJ7HCX$}_YTTI`)fu8Cq=S}=sS}L}`q~{&Fe0=04)pO5u?Gbsrbrq)K+%RZ}s1)e$DoYBTiG@2+?` z#A~hRJeXa0?b@(up*yn?&&jasv$U-c^h2gs5MNO0wU8a=%zHt?FpK*`J{i?o>@}TP zW*N1R_f&rML%POG#oAOw1^ae+^+0(Csh^LYiFh!xta6k$9NYM1N>U!>7@NxL@owyx zcW{vnvq^dVkX2S#+~Li3nNom=a8qjinE=v7&!&+k&X7?}h1n2(>zgw|ys_Hnh^IHV zhx=7uT=}6e7pkcf)nqT*HuvU1)rtwa-tEmd_fAnR~CW z4rny1-oFtFi)`+lgUx#mx#KRD(kXq><7ChtSK$ebWa64I1p=Cw#UCHzN>!D_w#yw@ zK-gwi*+SIQ(G`Z#JT}~cuu%71{p@~GmtK-fn0wIJop@+y<0P*+H!9nw@KXH|$IClA z9MxfZxr%zWM@sI_$Z_`uH5on-)_fwZRAJN5{najaG;!mV-lYNUeT#jXhYb&DP8^*q z2{>`NQPEyc~L+Xd?dQCn^U1nD|538&{ z$#+v7YeGLJ5rYj#ecGXYhdYSj7mUScJmAZLLdnHTpRtK6^o}^;wQ*PCRYSdnH;I_+ zMQKz@JrKVW(d9c(6V$)Y5>lC?_1auNi#wTxiK88*|7` zn|Wk2#oZX~bvn3W?43=c3)}ni$3o3sy>MxLZ6!Kabv|7EV!Qd4=StO1XK$H(&CI^= z&7(Kg_T8od0{;uC{o^4OM7|t6?eSz0O#>aMrZb5`{R6jwqNQY!qTq8l_&*DkKq9Jv z5SoaZ90CTzz+ngw0g-_tkm4}7FbpOPvgwi>{tpgg0@W2S;zn?%*id{aHg2xcFvOqw zNn{ZX@Hv|XzDY~L;801ZGnMKt2LKdjJCcu-10G~l_M|$4d>8OUis)ZZmJb>42tp@t zBn0-?3o0ukgOq_fLVwfXXaoqi(OyvEpEOw+1PCSlFAa{OK`#HI$zc9NgTde+-1l!j z)PMNkXcQRdfAL{Z|FMgZ20i-^AN)UjaE$bSXb99l^-;+<5R@Q;f1yDEBZ40uj0+S* zKS?0KNJA;00G8-Tg6<&}ATpx{wUkGKFcb`pM4)8VWK~o&)RF24w3?cXtOiO}U0oI? eqxgSwSkqun3Kd7D?rnxF3Ly;<6jayOfc!t1uQ?z9 diff --git a/lib/CPUs/MIPS/doc/toolchain/howto_build.txt b/lib/CPUs/MIPS/doc/toolchain/howto_build.txt deleted file mode 100644 index 270be3b..0000000 --- a/lib/CPUs/MIPS/doc/toolchain/howto_build.txt +++ /dev/null @@ -1,46 +0,0 @@ -# --------------------------------------------------------------- -# 1. Binutils bauen und installieren -# --------------------------------------------------------------- -> tar -xzf binutils-2.19.tar.gz -> mkdir binutils-2.19_build -> cd binutils-2.19_build - -> ../binutils-2.19/configure --target=mipsel-elf --prefix=/usr/local -> make -> make install - -# --------------------------------------------------------------- -# 2. GCC bootstrapping -# --------------------------------------------------------------- -> tar -xzf gcc-4.3.2.tar.gz -> mkdir gcc-4.3.2_build -> cd gcc-4.3.2_build -> ../gcc-4.3.2/configure --target=mipsel-elf --prefix=/usr/local --enable-languages="c,c++" --without-headers --with-newlib --with-float=soft --disable-multilib -> CFLAGS_FOR_TARGET="-mno-gpopt" make all-gcc -> make info-gcc -> make install-gcc - -# --------------------------------------------------------------- -# 3. Newlib bauen und installieren -# --------------------------------------------------------------- -> tar -xzf newlib-1.16.0.tar.gz -! Bug in newlib-1.16.0/newlib/libc/machine/mips/strlen.c. - Newlib von Hand patchen (32-bit MIPS targets): - "lbu $3,0($4)\n" - "nop\n" <= nop einfügen - "bnez $3,1b\n" - -> mkdir newlib-1.16.0_build -> cd newlib-1.16.0_build -> ../newlib-1.16.0/configure --target=mipsel-elf --prefix=/usr/local --with-float=soft --disable-multilib -> TARGET_CFLAGS="-mno-gpopt" make all -> make install - -# --------------------------------------------------------------- -# 4. GCC bauen und installieren -# --------------------------------------------------------------- -> cd gcc-4.3.2_build -> ../gcc-4.3.2/configure --target=mipsel-elf --prefix=/usr/local --enable-languages="c,c++" --disable-shared --with-newlib --with-float=soft --disable-multilib -> CFLAGS_FOR_TARGET="-mno-gpopt" make all -> make info -> make install diff --git a/lib/CPUs/MIPS/doc/toolchain/make.sh b/lib/CPUs/MIPS/doc/toolchain/make.sh deleted file mode 100644 index 1568da9..0000000 --- a/lib/CPUs/MIPS/doc/toolchain/make.sh +++ /dev/null @@ -1,151 +0,0 @@ -#!/bin/sh -TARGET=mipsel-elf -PREFIX=/usr/local - -SRC_BINUTILS=binutils-2.19 -SRC_GCC=gcc-4.3.3 -SRC_NEWLIB=newlib-1.16.0 -SRC_GMP=gmp-4.2.4 -SRC_MPFR=mpfr-2.4.0 - -# --------------------------------------------------------------- -# 1. Binutils bauen und installieren -# --------------------------------------------------------------- -if [ ! -e $SRC_BINUTILS.tar.bz2 ]; then - echo Downloading $SRC_BINUTILS - wget ftp://ftp-stud.fht-esslingen.de/pub/Mirrors/ftp.gnu.org/binutils/$SRC_BINUTILS.tar.bz2 || exit 1 -else - echo Skipped downloading $SRC_BINUTILS -fi - -if [ ! -e ./$SRC_BINUTILS ]; then - echo Unpacking $SRC_BINUTILS - tar -xjf $SRC_BINUTILS.tar.bz2 || exit 1 -else - echo Skipped unpacking $SRC_BINUTILS -fi - -if [ ! -e ./$SRC_BINUTILS-build ]; then - echo Building $SRC_BINUTILS - mkdir -p $SRC_BINUTILS-build - cd $SRC_BINUTILS-build - ../$SRC_BINUTILS/configure --target=$TARGET --prefix=$PREFIX || exit 1 - make || exit 1 - make install || exit 1 - cd .. -else - echo $SRC_BINUTILS is already built. -fi - -# --------------------------------------------------------------- -# 2. GMP bauen und installieren -# --------------------------------------------------------------- -if [ ! -e $SRC_GMP.tar.bz2 ]; then - echo Downloading $SRC_GMP - wget http://ftp.sunet.se/pub/gnu/gmp/$SRC_GMP.tar.bz2 || exit 1 -else - echo Skipped downloading $SRC_GMP -fi - -if [ ! -e ./$SRC_GMP ]; then - echo Unpacking $SRC_GMP - tar -xjf $SRC_GMP.tar.bz2 || exit 1 -else - echo Skipped unpacking $SRC_GMP -fi - -if [ ! -e ./$SRC_GMP-build ]; then - echo Building $SRC_GMP - mkdir -p $SRC_GMP-build - cd $SRC_GMP-build - ../$SRC_GMP/configure --prefix=$PREFIX || exit 1 - make || exit 1 - make check || exit 1 - make install || exit 1 - cd .. -else - echo $SRC_GMP is already built. -fi - -# --------------------------------------------------------------- -# 3. MPFR bauen und installieren -# --------------------------------------------------------------- -if [ ! -e $SRC_MPFR.tar.bz2 ]; then - echo Downloading $SRC_MPFR - wget http://www.mpfr.org/mpfr-current/$SRC_MPFR.tar.bz2 || exit 1 -else - echo Skipped downloading $SRC_MPFR -fi - -if [ ! -e ./$SRC_MPFR ]; then - echo Unpacking $SRC_MPFR - tar -xjf $SRC_MPFR.tar.bz2 || exit 1 -else - echo Skipped unpacking $SRC_MPFR -fi - -if [ ! -e ./$SRC_MPFR-build ]; then - echo Building $SRC_MPFR - mkdir -p $SRC_MPFR-build - cd $SRC_MPFR-build - ../$SRC_MPFR/configure --prefix=$PREFIX || exit 1 - make || exit 1 - make check || exit 1 - make install || exit 1 - cd .. -else - echo $SRC_MPFR is already built. -fi - -# --------------------------------------------------------------- -# 4. GCC & newlib bauen und installieren -# --------------------------------------------------------------- -if [ ! -e $SRC_NEWLIB.tar.gz ]; then - echo Downloading $SRC_NEWLIB - wget ftp://sources.redhat.com/pub/newlib/$SRC_NEWLIB.tar.gz || exit 1 -else - echo Skipped downloading $SRC_NEWLIB -fi - -if [ ! -e ./$SRC_NEWLIB ]; then - echo Unpacking $SRC_NEWLIB - tar -xzf $SRC_NEWLIB.tar.gz || exit 1 - if [ -e $SRC_NEWLIB-jens.patch ]; then - echo Patching $SRC_NEWLIB - patch -p0 < $SRC_NEWLIB-jens.patch || exit 1 - fi -else - echo Skipped unpacking $SRC_NEWLIB -fi - -if [ ! -e $SRC_GCC.tar.bz2 ]; then - echo Downloading $SRC_GCC - wget ftp://ftp-stud.fht-esslingen.de/pub/Mirrors/ftp.gnu.org/gcc/$SRC_GCC/$SRC_GCC.tar.bz2 || exit 1 -else - echo Skipped downloading $SRC_GCC -fi - -if [ ! -e ./$SRC_GCC ]; then - echo Unpacking $SRC_GCC - tar -xjf $SRC_GCC.tar.bz2 || exit 1 - cd ./$SRC_GCC - ln -sf ../$SRC_NEWLIB/newlib/ . - cd .. -else - echo Skipped unpacking $SRC_GCC -fi - -if [ ! -e ./$SRC_GCC-build ]; then - echo Building $SRC_GCC - mkdir -p $SRC_GCC-build - cd $SRC_GCC-build - ../$SRC_GCC/configure --target=$TARGET --prefix=$PREFIX --with-float=soft --with-newlib --verbose --enable-languages="c,c++" || exit 1 - LD_LIBRARY_PATH=$LD_LIBRARY_PATH:$PREFIX/lib make all || exit 1 - make info || exit 1 - make install || exit 1 - cd .. - echo $PREFIX/lib >/etc/ld.so.conf.d/local.conf - ldconfig -else - echo $SRC_GCC is already built. -fi diff --git a/lib/CPUs/MIPS/doc/toolchain/newlib-1.16.0-jens.patch b/lib/CPUs/MIPS/doc/toolchain/newlib-1.16.0-jens.patch deleted file mode 100644 index bf61a14..0000000 --- a/lib/CPUs/MIPS/doc/toolchain/newlib-1.16.0-jens.patch +++ /dev/null @@ -1,11 +0,0 @@ -diff -Naur newlib-1.16.0/newlib/libc/machine/mips/strlen.c newlib-1.16.0-fixed/newlib/libc/machine/mips/strlen.c ---- newlib-1.16.0/newlib/libc/machine/mips/strlen.c 2002-03-14 03:41:43.000000000 +0100 -+++ newlib-1.16.0-fixed/newlib/libc/machine/mips/strlen.c 2009-02-14 15:52:58.000000000 +0100 -@@ -60,6 +60,7 @@ - " addiu $2,$4,1\n" - "\n" - "1: lbu $3,0($4)\n" -+ " nop\n" - " bnez $3,1b\n" - " addiu $4,$4,1\n" - "\n" diff --git a/lib/CPUs/MIPS/doc/toolchain/newlib-1.17.0-jens.patch b/lib/CPUs/MIPS/doc/toolchain/newlib-1.17.0-jens.patch deleted file mode 100644 index bc28abc..0000000 --- a/lib/CPUs/MIPS/doc/toolchain/newlib-1.17.0-jens.patch +++ /dev/null @@ -1,11 +0,0 @@ -diff -Naur newlib-1.17.0/newlib/libc/machine/mips/strlen.c newlib-1.17.0-fixed/newlib/libc/machine/mips/strlen.c ---- newlib-1.17.0/newlib/libc/machine/mips/strlen.c 2002-03-14 03:41:43.000000000 +0100 -+++ newlib-1.17.0-fixed/newlib/libc/machine/mips/strlen.c 2009-02-14 15:45:19.000000000 +0100 -@@ -60,6 +60,7 @@ - " addiu $2,$4,1\n" - "\n" - "1: lbu $3,0($4)\n" -+ " nop\n" - " bnez $3,1b\n" - " addiu $4,$4,1\n" - "\n" diff --git a/lib/CPUs/MIPS/sim/ModelSim SE .lnk b/lib/CPUs/MIPS/sim/ModelSim SE .lnk deleted file mode 100644 index d30cd7a6a45d686675fed466219cf9a237c53233..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 1455 zcmds1T}YE*6h3n+6bdFTP;s@Ql@!c5f7+%&OJ|P!+;GOc7@4`HpSVr7Dmr zACm$jFuQPFdE>yFQiwu>Kq9IOrI4sJ(SD?hDC&8?Z+`vI&rMgIao%&@^YfhZp6`8E zM??xu23Dd;aiyAz*y^CGPt8Pix2F^}*Y77A%cd1{PbIvax~rh`8^lP36fdtfg@(4c zo;hc9i&kDe{3Mfh8;w`7m4m)1`>9ymcq}g}vdPupJkVh4foT^hNkuESZko>y zdMx!L8brA$Od)E++Cl;R{IKOxeHvlH{E=4^=d8BZHTD!6OjT5x#+WcK^B&8!B*Wl< z;6r97MX|P0J2g`|8OQ{kC?C4i&xH9i&|-YB#6;UO#q$)v>jN{%M$2R=m=WtR7pw%I z-Z_?3Lwfk2FBFRqrt1oa+QKb?fZxlp2BQAf_U3YfsnsihyZ$F+JL!?}`xBz+|A6$Ej+3g% zj&JYAoH*R0T39$({(Sy^A)b>(d#PWrre9lEkll%YONG*F{w3&IJyw7Al~!5#;eucT zf8WnI>@0b96>>rHF~btTY4n@>?C;w?ja zdb*dq36oMK-e>kl;(~o23rdrj%ruF)FyERkyw)n?Cs$($@W7&0Ifk64n=3^9B_vB_ zH8!R(h_Wb&n24!gI0w#LpGAdqN%lU6&sNkcIKb0}UZHR%CB8QnvxdQHw9lpJA?i&I z_6jb -//#include -//#include - -int faculty(int f0, int *pDst, int len) -{ - int i=0; - - pDst[i++] = f0; - - for (; i < len; i++) - { - pDst[i] = pDst[i-1] * i; - } - - return i; -} - -#define NUM_ELEMENTS 20 - -void saus(char c) -{ - volatile char *pUART_stat = (char*)0x80000008; - volatile char *pUART_data = (char*)0x80000004; - - while((0x02 & *pUART_stat) != 0); - - *pUART_data = c; -} - -int sputs(char *pStr) -{ - char *start; - start = pStr; - - while(*pStr) - saus(*(pStr++)); - - return pStr - start; -} - -void print_word(int word) -{ - int i; - unsigned char c, nibble; - - for (i=0; i < 8; i++) - - { - nibble = (char)((word >> 28) & 0xF); - word <<= 4; - - if (nibble < 10) - c = nibble + '0'; - else - c = nibble + 'A' - 10; - - saus(c); - } - -} - -int main (void) -{ - int buf[NUM_ELEMENTS], result, i, j, cnt; - volatile int *pReg = (int*)0x80000000; - volatile char *pUART_data = (char*)0x80000004; - volatile char *pUART_ctrl = (char*)0x80000008; - volatile char *pUART_baud = (char*)0x80000009; - char msg[] = "MIPS R3000 CPU\r\nReady\r\n"; - - *pUART_baud = 0x35; - *pUART_ctrl = 0x55; - - cnt = 0; - memset(buf, 0, sizeof(buf)); - - sputs(msg); - - buf[NUM_ELEMENTS-1] = 1; - while (1) - { - result = faculty(buf[NUM_ELEMENTS-1], buf, NUM_ELEMENTS); - - for (i=0; i < NUM_ELEMENTS; i++) - { - print_word(buf[i]); - saus(13); - saus(10); - } - cnt++; - - while(1); - } -} - diff --git a/lib/CPUs/MIPS/sim/asm/faculty.s b/lib/CPUs/MIPS/sim/asm/faculty.s deleted file mode 100644 index 9bbdd09..0000000 --- a/lib/CPUs/MIPS/sim/asm/faculty.s +++ /dev/null @@ -1,255 +0,0 @@ - .file 1 "faculty.c" - .set nobopt - .text - .align 2 - .globl faculty - .ent faculty -faculty: - .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 - .mask 0x00000000,0 - .fmask 0x00000000,0 - li $7,1 # 0x1 - slt $2,$7,$6 - .set noreorder - .set nomacro - beq $2,$0,$L7 - sw $4,0($5) - .set macro - .set reorder - - addiu $5,$5,4 -$L5: - lw $2,-4($5) - mult $2,$7 - addiu $7,$7,1 - slt $3,$7,$6 - mflo $2 - sw $2,0($5) - .set noreorder - .set nomacro - bne $3,$0,$L5 - addiu $5,$5,4 - .set macro - .set reorder - -$L7: - .set noreorder - .set nomacro - j $31 - move $2,$7 - .set macro - .set reorder - - .end faculty - .align 2 - .globl saus - .ent saus -saus: - .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 - .mask 0x00000000,0 - .fmask 0x00000000,0 - li $2,-2147483648 # 0xffffffff80000000 - sll $4,$4,24 - sra $4,$4,24 - ori $5,$2,0x4 - ori $3,$2,0x8 -$L10: - lbu $2,0($3) - andi $2,$2,0x2 - bne $2,$0,$L10 - sb $4,0($5) - j $31 - .end saus - .align 2 - .globl sputs - .ent sputs -sputs: - .frame $sp,32,$31 # vars= 0, regs= 3/0, args= 16, gp= 0 - .mask 0x80030000,-8 - .fmask 0x00000000,0 - addiu $sp,$sp,-32 - sw $17,20($sp) - sw $16,16($sp) - sw $31,24($sp) - move $16,$4 - lb $4,0($4) - .set noreorder - .set nomacro - j $L18 - move $17,$16 - .set macro - .set reorder - -$L19: - .set noreorder - .set nomacro - jal saus - addiu $16,$16,1 - .set macro - .set reorder - - lb $4,0($16) -$L18: - .set noreorder - .set nomacro - bne $4,$0,$L19 - subu $2,$16,$17 - .set macro - .set reorder - - lw $31,24($sp) - lw $17,20($sp) - lw $16,16($sp) - .set noreorder - .set nomacro - j $31 - addiu $sp,$sp,32 - .set macro - .set reorder - - .end sputs - .align 2 - .globl print_word - .ent print_word -print_word: - .frame $sp,32,$31 # vars= 0, regs= 3/0, args= 16, gp= 0 - .mask 0x80030000,-8 - .fmask 0x00000000,0 - addiu $sp,$sp,-32 - sw $17,20($sp) - sw $16,16($sp) - sw $31,24($sp) - move $16,$4 - li $17,7 # 0x7 - srl $3,$16,28 -$L29: - sltu $2,$3,10 - addiu $17,$17,-1 - sll $16,$16,4 - .set noreorder - .set nomacro - bne $2,$0,$L25 - addiu $4,$3,48 - .set macro - .set reorder - - addiu $4,$3,55 -$L25: - jal saus - .set noreorder - .set nomacro - bgez $17,$L29 - srl $3,$16,28 - .set macro - .set reorder - - lw $31,24($sp) - lw $17,20($sp) - lw $16,16($sp) - .set noreorder - .set nomacro - j $31 - addiu $sp,$sp,32 - .set macro - .set reorder - - .end print_word - .section .rodata.str1.4,"aMS",@progbits,1 - .align 2 -$LC0: - .ascii "MIPS R3000 CPU\r\n" - .ascii "Ready\r\n\000" - .text - .align 2 - .globl main - .ent main -main: - .frame $sp,136,$31 # vars= 104, regs= 3/0, args= 16, gp= 0 - .mask 0x80030000,-8 - .fmask 0x00000000,0 - lw $2,$LC0 - lw $3,$LC0+4 - addiu $sp,$sp,-136 - sw $2,96($sp) - sw $3,100($sp) - lw $2,$LC0+8 - lw $3,$LC0+12 - sw $2,104($sp) - sw $3,108($sp) - lw $2,$LC0+16 - lw $3,$LC0+20 - li $7,-2147483648 # 0xffffffff80000000 - ori $8,$7,0x9 - sw $2,112($sp) - sw $3,116($sp) - ori $7,$7,0x8 - li $3,85 - sw $16,120($sp) - li $2,53 - addiu $16,$sp,16 - sb $2,0($8) - move $4,$16 - sb $3,0($7) - move $5,$0 - li $6,80 # 0x50 - sw $31,128($sp) - .set noreorder - .set nomacro - jal memset - sw $17,124($sp) - .set macro - .set reorder - - .set noreorder - .set nomacro - jal sputs - addiu $4,$sp,96 - .set macro - .set reorder - - li $3,1 # 0x1 - sw $3,92($sp) - li $4,1 # 0x1 - move $5,$16 - li $6,20 # 0x14 - .set noreorder - .set nomacro - jal faculty - move $17,$16 - .set macro - .set reorder - - li $16,19 # 0x13 -$L36: - lw $4,0($17) - .set noreorder - .set nomacro - jal print_word - addiu $16,$16,-1 - .set macro - .set reorder - - .set noreorder - .set nomacro - jal saus - li $4,13 # 0xd - .set macro - .set reorder - - .set noreorder - .set nomacro - jal saus - li $4,10 # 0xa - .set macro - .set reorder - - .set noreorder - .set nomacro - bgez $16,$L36 - addiu $17,$17,4 - .set macro - .set reorder - -$L37: - j $L37 - .end main diff --git a/lib/CPUs/MIPS/sim/asm/fibonacci.c b/lib/CPUs/MIPS/sim/asm/fibonacci.c deleted file mode 100644 index b707efb..0000000 --- a/lib/CPUs/MIPS/sim/asm/fibonacci.c +++ /dev/null @@ -1,179 +0,0 @@ -//#include -#include -//#include - -int fibonacci(int f0, int f1, int *pDst, int len) -{ - int i; - - i = 0; - - pDst[i++] = f0; - pDst[i++] = f1; - - for (; i < len; i++) - { - pDst[i] = pDst[i-2] + pDst[i-1]; - } - - return i; -} - -#define NUM_ELEMENTS 100 -#define NUM_RUNS 1000 - -typedef struct _sstat_t -{ - char v1; - int v2; - char v3; - short v4; - -} __attribute__ ((__packed__)) stat_t; - -void test_func(stat_t *pObj) -{ - int *pReg = (int*)0x80000000; - - - *pReg = (int)pObj->v4; - -} - -char sein(void) -{ - volatile char *pUART_stat = (char*)0x80000008; - volatile char *pUART_data = (char*)0x80000004; - - while(!(0x10 & *pUART_stat)); - - return *pUART_data; -} - -void saus(char c) -{ - volatile char *pUART_stat = (char*)0x80000008; - volatile char *pUART_data = (char*)0x80000004; - - while((0x02 & *pUART_stat) != 0); - - *pUART_data = c; -} - -int sputs(char *pStr) -{ - char *start; - start = pStr; - - while(*pStr) - saus(*(pStr++)); - - return pStr - start; -} - -void print_word(int word) -{ - int i; - unsigned char c, nibble; - - for (i=0; i < 8; i++) - - { - nibble = (char)((word >> 28) & 0xF); - word <<= 4; - - if (nibble < 10) - c = nibble + '0'; - else - c = nibble + 'A' - 10; - - saus(c); - } - -} - -int main (void) -{ - int buf[NUM_ELEMENTS], result, i, j, diff, num_right_elements, num_right_runs; - int fill, cnt, *pReg = (int*)0x80000000; - volatile char *pUART_data = (char*)0x80000004; - volatile char *pUART_ctrl = (char*)0x80000008; - volatile char *pUART_baud = (char*)0x80000009; - int testbuf[2] = {0x12345678, 0x5555aaaa}; - stat_t stat = {0x0D, 0xFF5A3FC1, 0x1E, 0x0F07}; - char msg[] = "MIPS R3000 CPU\r\nReady\r\n"; - char msg2[32]; - char baud; - char *pPtr; - long long product; - int op1, op2; - - div_t div_res; - - *pUART_baud = 0x35; - *pUART_ctrl = 0x55; - - cnt = 0; - fill = 0xAAAAAAAA; - memset(msg2, 0, sizeof(msg2)); - memcpy(msg2, msg, strlen(msg)); - - srand(0x19701031); - for (i=0; i < sizeof(msg2)-1; i++) - msg2[i] = sein(); - - sputs(msg2); - test_func(&stat); - -// div_res = div(testbuf[1], testbuf[0]); - while (1) - { - num_right_runs = 0; - for (i=0; i < NUM_RUNS; i++) - { - for (j=0; j < NUM_ELEMENTS; j++) - buf[j] = fill; - - fill = ((fill ^ i) - 1) << 1; - num_right_elements = 2; - result = fibonacci(i, i+1, buf, NUM_ELEMENTS); - for (j=2; j < NUM_ELEMENTS; j++) - { - diff = buf[j] - buf[j-1]; - if (diff == buf[j-2]) - num_right_elements++; - } - if (num_right_elements == NUM_ELEMENTS) - num_right_runs++; - } - - if (num_right_runs == NUM_RUNS) - { - *pReg = cnt & 0x3FFFFFFF; - cnt++; - } - else - { - *pReg = 0x40000000 | cnt; - saus('X'); - } - op1 = (int)-cnt; - op2 = (int)((op1 & 8) << 28) ^ rand(); - product = (long long)op1 * (long long)op2; - print_word((int)op1); - saus(' '); - saus('x'); - saus(' '); - print_word((int)op2); - saus(' '); - saus('='); - saus(' '); - print_word((int)(product >> 32)); - print_word((int)product); - saus(13); - saus(10); - - } - return 0; -} - diff --git a/lib/CPUs/MIPS/sim/asm/fibonacci.s b/lib/CPUs/MIPS/sim/asm/fibonacci.s deleted file mode 100644 index e042654..0000000 --- a/lib/CPUs/MIPS/sim/asm/fibonacci.s +++ /dev/null @@ -1,555 +0,0 @@ - .file 1 "fibonacci.c" - .set nobopt - .text - .align 2 - .globl fibonacci - .ent fibonacci -fibonacci: - .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 - .mask 0x00000000,0 - .fmask 0x00000000,0 - li $8,2 # 0x2 - slt $2,$8,$7 - sw $4,0($6) - .set noreorder - .set nomacro - beq $2,$0,$L7 - sw $5,4($6) - .set macro - .set reorder - - addiu $6,$6,8 -$L5: - lw $2,-8($6) - lw $3,-4($6) - addiu $8,$8,1 - addu $2,$2,$3 - slt $4,$8,$7 - sw $2,0($6) - .set noreorder - .set nomacro - bne $4,$0,$L5 - addiu $6,$6,4 - .set macro - .set reorder - -$L7: - .set noreorder - .set nomacro - j $31 - move $2,$8 - .set macro - .set reorder - - .end fibonacci - .align 2 - .globl test_func - .ent test_func -test_func: - .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 - .mask 0x00000000,0 - .fmask 0x00000000,0 - lbu $2,7($4) - lbu $3,6($4) - sll $2,$2,8 - or $2,$2,$3 - sll $2,$2,16 - sra $2,$2,16 - li $3,-2147483648 # 0xffffffff80000000 - .set noreorder - .set nomacro - j $31 - sw $2,0($3) - .set macro - .set reorder - - .end test_func - .align 2 - .globl sein - .ent sein -sein: - .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 - .mask 0x00000000,0 - .fmask 0x00000000,0 - li $2,-2147483648 # 0xffffffff80000000 - ori $4,$2,0x4 - ori $3,$2,0x8 -$L11: - lbu $2,0($3) - andi $2,$2,0x10 - beq $2,$0,$L11 - lbu $2,0($4) - sll $2,$2,24 - .set noreorder - .set nomacro - j $31 - sra $2,$2,24 - .set macro - .set reorder - - .end sein - .align 2 - .globl saus - .ent saus -saus: - .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 - .mask 0x00000000,0 - .fmask 0x00000000,0 - li $2,-2147483648 # 0xffffffff80000000 - sll $4,$4,24 - sra $4,$4,24 - ori $5,$2,0x4 - ori $3,$2,0x8 -$L14: - lbu $2,0($3) - andi $2,$2,0x2 - bne $2,$0,$L14 - sb $4,0($5) - j $31 - .end saus - .align 2 - .globl sputs - .ent sputs -sputs: - .frame $sp,32,$31 # vars= 0, regs= 3/0, args= 16, gp= 0 - .mask 0x80030000,-8 - .fmask 0x00000000,0 - addiu $sp,$sp,-32 - sw $17,20($sp) - sw $16,16($sp) - sw $31,24($sp) - move $16,$4 - lb $4,0($4) - .set noreorder - .set nomacro - j $L22 - move $17,$16 - .set macro - .set reorder - -$L23: - .set noreorder - .set nomacro - jal saus - addiu $16,$16,1 - .set macro - .set reorder - - lb $4,0($16) -$L22: - .set noreorder - .set nomacro - bne $4,$0,$L23 - subu $2,$16,$17 - .set macro - .set reorder - - lw $31,24($sp) - lw $17,20($sp) - lw $16,16($sp) - .set noreorder - .set nomacro - j $31 - addiu $sp,$sp,32 - .set macro - .set reorder - - .end sputs - .align 2 - .globl print_word - .ent print_word -print_word: - .frame $sp,32,$31 # vars= 0, regs= 3/0, args= 16, gp= 0 - .mask 0x80030000,-8 - .fmask 0x00000000,0 - addiu $sp,$sp,-32 - sw $17,20($sp) - sw $16,16($sp) - sw $31,24($sp) - move $16,$4 - li $17,7 # 0x7 - srl $3,$16,28 -$L33: - sltu $2,$3,10 - addiu $17,$17,-1 - sll $16,$16,4 - .set noreorder - .set nomacro - bne $2,$0,$L29 - addiu $4,$3,48 - .set macro - .set reorder - - addiu $4,$3,55 -$L29: - jal saus - .set noreorder - .set nomacro - bgez $17,$L33 - srl $3,$16,28 - .set macro - .set reorder - - lw $31,24($sp) - lw $17,20($sp) - lw $16,16($sp) - .set noreorder - .set nomacro - j $31 - addiu $sp,$sp,32 - .set macro - .set reorder - - .end print_word - .section .sdata,"aw",@progbits - .align 2 -$LC0: - .word 305419896 - .word 1431677610 - .section .rodata.str1.4,"aMS",@progbits,1 - .align 2 -$LC2: - .ascii "MIPS R3000 CPU\r\n" - .ascii "Ready\r\n\000" - .section .sdata - .align 2 -$LC1: - .byte 13 - .4byte -10862655 - .byte 30 - .half 3847 - .text - .align 2 - .globl main - .ent main -main: - .frame $sp,536,$31 # vars= 480, regs= 10/0, args= 16, gp= 0 - .mask 0xc0ff0000,-4 - .fmask 0x00000000,0 - lw $2,$LC0 - addiu $sp,$sp,-536 - lw $3,$LC0+4 - sw $2,416($sp) - lw $2,$LC2 - lwl $4,$LC1+3 - lwl $5,$LC1+7 - sw $3,420($sp) - sw $2,432($sp) - lw $3,$LC2+4 - lw $2,$LC2+8 - lwr $5,$LC1+4 - lwr $4,$LC1 - sw $3,436($sp) - sw $2,440($sp) - lw $3,$LC2+12 - lw $2,$LC2+16 - sw $31,532($sp) - sw $5,428($sp) - sw $23,524($sp) - sw $22,520($sp) - sw $21,516($sp) - sw $20,512($sp) - sw $18,504($sp) - sw $17,500($sp) - sw $16,496($sp) - sw $4,424($sp) - sw $3,444($sp) - sw $fp,528($sp) - sw $19,508($sp) - sw $2,448($sp) - lw $3,$LC2+20 - li $23,-2147483648 # 0xffffffff80000000 - ori $7,$23,0x9 - sw $3,452($sp) - ori $6,$23,0x8 - li $3,85 - addiu $16,$sp,432 - li $2,53 - sb $2,0($7) - move $4,$16 - sb $3,0($6) - li $2,-1431699456 # 0xffffffffaaaa0000 - sw $0,456($sp) - sw $0,460($sp) - sw $0,464($sp) - sw $0,468($sp) - sw $0,472($sp) - sw $0,476($sp) - sw $0,480($sp) - sw $0,484($sp) - ori $20,$2,0xaaaa - .set noreorder - .set nomacro - jal strlen - addiu $18,$sp,456 - .set macro - .set reorder - - move $6,$2 - move $5,$16 - .set noreorder - .set nomacro - jal memcpy - move $4,$18 - .set macro - .set reorder - - li $4,426770432 # 0x19700000 - .set noreorder - .set nomacro - jal srand - ori $4,$4,0x1031 - .set macro - .set reorder - - move $22,$0 - move $17,$0 - addiu $21,$sp,16 -$L38: - addu $16,$21,$17 - .set noreorder - .set nomacro - jal sein - addiu $17,$17,1 - .set macro - .set reorder - - sltu $3,$17,31 - .set noreorder - .set nomacro - bne $3,$0,$L38 - sb $2,440($16) - .set macro - .set reorder - - .set noreorder - .set nomacro - jal sputs - move $4,$18 - .set macro - .set reorder - - .set noreorder - .set nomacro - jal test_func - addiu $4,$sp,424 - .set macro - .set reorder - - li $fp,100 # 0x64 - move $18,$0 - move $17,$0 -$L54: - move $2,$21 - li $6,99 # 0x63 -$L47: - addiu $6,$6,-1 - sw $20,0($2) - .set noreorder - .set nomacro - bgez $6,$L47 - addiu $2,$2,4 - .set macro - .set reorder - - xor $2,$20,$17 - addiu $16,$17,1 - addiu $2,$2,-1 - move $5,$16 - addiu $6,$sp,16 - li $7,100 # 0x64 - move $4,$17 - .set noreorder - .set nomacro - jal fibonacci - sll $20,$2,1 - .set macro - .set reorder - - li $7,2 # 0x2 - addiu $5,$21,8 - .set noreorder - .set nomacro - j $L52 - li $6,97 # 0x61 - .set macro - .set reorder - -$L50: - bltz $6,$L65 -$L52: - lw $2,0($5) - lw $3,-4($5) - lw $4,-8($5) - subu $2,$2,$3 - addiu $6,$6,-1 - .set noreorder - .set nomacro - bne $4,$2,$L50 - addiu $5,$5,4 - .set macro - .set reorder - - .set noreorder - .set nomacro - bgez $6,$L52 - addiu $7,$7,1 - .set macro - .set reorder - -$L65: - beq $7,$fp,$L66 -$L43: - slt $2,$16,1000 - .set noreorder - .set nomacro - bne $2,$0,$L54 - move $17,$16 - .set macro - .set reorder - - li $2,1000 # 0x3e8 - .set noreorder - .set nomacro - bne $18,$2,$L55 - li $3,1073676288 # 0x3fff0000 - .set macro - .set reorder - - ori $3,$3,0xffff - and $2,$22,$3 - sw $2,0($23) - addiu $22,$22,1 - subu $16,$0,$22 -$L67: - .set noreorder - .set nomacro - jal rand - andi $17,$16,0x8 - .set macro - .set reorder - - sll $17,$17,28 - xor $17,$17,$2 - mult $16,$17 - mflo $18 - mfhi $19 - .set noreorder - .set nomacro - jal print_word - move $4,$16 - .set macro - .set reorder - - .set noreorder - .set nomacro - jal saus - li $4,32 # 0x20 - .set macro - .set reorder - - .set noreorder - .set nomacro - jal saus - li $4,120 # 0x78 - .set macro - .set reorder - - .set noreorder - .set nomacro - jal saus - li $4,32 # 0x20 - .set macro - .set reorder - - .set noreorder - .set nomacro - jal print_word - move $4,$17 - .set macro - .set reorder - - .set noreorder - .set nomacro - jal saus - li $4,32 # 0x20 - .set macro - .set reorder - - .set noreorder - .set nomacro - jal saus - li $4,61 # 0x3d - .set macro - .set reorder - - .set noreorder - .set nomacro - jal saus - li $4,32 # 0x20 - .set macro - .set reorder - - .set noreorder - .set nomacro - jal print_word - sra $4,$19,0 - .set macro - .set reorder - - .set noreorder - .set nomacro - jal print_word - move $4,$18 - .set macro - .set reorder - - .set noreorder - .set nomacro - jal saus - li $4,13 # 0xd - .set macro - .set reorder - - .set noreorder - .set nomacro - jal saus - li $4,10 # 0xa - .set macro - .set reorder - - move $18,$0 - .set noreorder - .set nomacro - j $L54 - move $17,$0 - .set macro - .set reorder - -$L66: - .set noreorder - .set nomacro - j $L43 - addiu $18,$18,1 - .set macro - .set reorder - -$L55: - li $2,1073741824 # 0x40000000 - or $2,$22,$2 - li $4,88 # 0x58 - .set noreorder - .set nomacro - jal saus - sw $2,0($23) - .set macro - .set reorder - - .set noreorder - .set nomacro - j $L67 - subu $16,$0,$22 - .set macro - .set reorder - - .end main diff --git a/lib/CPUs/MIPS/sim/asm/idata.ld b/lib/CPUs/MIPS/sim/asm/idata.ld deleted file mode 100644 index 5913b2c..0000000 --- a/lib/CPUs/MIPS/sim/asm/idata.ld +++ /dev/null @@ -1,24 +0,0 @@ -MEMORY -{ - imem : ORIGIN = 0x00000000, LENGTH = 0x00002000 /* 8K */ -} - - -SECTIONS -{ - .stext 0x00000000 : - { - *(.stext) - } > imem - - .ktext 0x00000180 : - { - *(.ktext) - } > imem - - .text 0x00000200 : - { - *(.text) - } > imem - -} diff --git a/lib/CPUs/MIPS/sim/asm/init.s b/lib/CPUs/MIPS/sim/asm/init.s deleted file mode 100644 index 41a35da..0000000 --- a/lib/CPUs/MIPS/sim/asm/init.s +++ /dev/null @@ -1,28 +0,0 @@ - .file "init.s" - - .text - .align 2 - .globl _init - .extern end - -_init: - .set noreorder - - # set uart - la $26, sys_uart_baud - addiu $27, $0, baudrate - sb $27, 0($26) - - # set stack pointer - la $sp, end - - # jump main - la $26, main - jalr $26 - -_terminate: - nop - j _terminate - nop - - .set reorder diff --git a/lib/CPUs/MIPS/sim/asm/jtag.sh b/lib/CPUs/MIPS/sim/asm/jtag.sh deleted file mode 100644 index f03567f..0000000 --- a/lib/CPUs/MIPS/sim/asm/jtag.sh +++ /dev/null @@ -1,7 +0,0 @@ -#!/bin/sh - -TARGET=$(basename $1 .c) - -xtclsh.exe $TARGET.RAM.tcl -xtclsh.exe $TARGET.ROM.tcl - diff --git a/lib/CPUs/MIPS/sim/asm/kernel.s b/lib/CPUs/MIPS/sim/asm/kernel.s deleted file mode 100644 index 7ec783f..0000000 --- a/lib/CPUs/MIPS/sim/asm/kernel.s +++ /dev/null @@ -1,251 +0,0 @@ - .file "exception.s" - - .section .kdata,"a" - .align 2 -_k_stack: .space 256, 0 -_k_msg1: .asciiz "Exception at " -_k_msg2: .asciiz "EPC : " -_k_msg3: .asciiz "Cause : " -_k_msg4: .asciiz "Status : " -_k_msg5: .asciiz "BadVAddr : " -_k_crlf: .asciiz "\r\n" -_k_hextbl: .ascii "0123456789ABCDEF" - - .section .ktext,"ax" - .align 2 - .globl _kputs - - .macro kpush reg - addiu $sp, 4 - sw \reg, 0($sp) - .endm - - .macro kpop reg - lw \reg, 0($sp) - addiu $sp, -4 - .endm - -_exc_handler: - - sw $sp, _k_stack - la $sp, _k_stack - kpush $8 - kpush $9 - kpush $10 - kpush $11 - kpush $12 - kpush $31 - - .set noreorder - # Get BadVAddr - mfc0 $10, $8 - kpush $10 - # Get Status - mfc0 $10, $12 - kpush $10 - # Get Cause - mfc0 $10, $13 - kpush $10 - srl $10, 29 - andi $11, $10, 4 - # Get EPC - mfc0 $10, $14 - kpush $10 - - # Get real EPC - addu $10, $11 - kpush $10 - - # set uart - la $26, sys_uart_baud - addiu $27, $0, baudrate - sb $27, 0($26) - - # Print CRLF - la $11, _k_crlf - jal _kputs - nop - - # Print real EPC - la $11, _k_msg1 - jal _kputs - nop - kpop $10 - jal _kprint_word - nop - la $11, _k_crlf - jal _kputs - nop - - # Print EPC - la $11, _k_msg2 - jal _kputs - nop - kpop $10 - jal _kprint_word - nop - la $11, _k_crlf - jal _kputs - nop - - # Print Cause - la $11, _k_msg3 - jal _kputs - nop - kpop $10 - jal _kprint_word - nop - la $11, _k_crlf - jal _kputs - nop - - # Print Status - la $11, _k_msg4 - jal _kputs - nop - kpop $10 - jal _kprint_word - nop - la $11, _k_crlf - jal _kputs - nop - - # Print BadVAddr - la $11, _k_msg5 - jal _kputs - nop - kpop $10 - jal _kprint_word - nop - la $11, _k_crlf - jal _kputs - nop - - # Set Error LED and ExcCode LEDs - # Get Cause - mfc0 $26, $13 - la $27, sys_led_port - srl $26, 2 - andi $26, 0x000F - or $26, $27 - sw $26, 0($27) - - # wait for all interrupts = 0 -$w4x: mfc0 $26, $13 - nop - srl $26, 8 - andi $26, 0xFF - bnez $26, $w4x - nop - - # Get return address - mfc0 $26, $14 - - kpop $31 - kpop $12 - kpop $11 - kpop $10 - kpop $9 - kpop $8 - lw $sp, _k_stack - - # Return - jr $26 - rfe - .set reorder - -# word = $10 -_kprint_word: - .set noreorder - kpush $31 - kpush $10 - srl $10, 16 - jal _kprint_halfword - nop - kpop $10 - jal _kprint_halfword - nop - kpop $31 - jr $31 - nop - .set noreorder - -# halfword = $10 -_kprint_halfword: - .set noreorder - kpush $31 - kpush $10 - srl $10, 8 - jal _kprint_byte - nop - kpop $10 - jal _kprint_byte - nop - kpop $31 - jr $31 - nop - .set noreorder - -# byte = $10 -_kprint_byte: - .set noreorder - kpush $31 - kpush $10 - srl $10, 4 - jal _kprint_nibble - nop - kpop $10 - jal _kprint_nibble - nop - kpop $31 - jr $31 - nop - .set noreorder - -_kprint_nibble: - .set noreorder - kpush $31 - kpush $10 - la $12, _k_hextbl - andi $10, 0xF - addu $12, $10 - lbu $10, 0($12) - jal _ksaus - nop - kpop $10 - kpop $31 - jr $31 - nop - .set noreorder - -# char = $10 -_ksaus: - .set noreorder - la $8, sys_uart_stat - lbu $8, 0($8) - la $9, sys_uart_data - andi $8, 0x02 - bnez $8, _ksaus - nop - j $31 - sb $10, 0($9) - .set reorder - -_kputs: - .set noreorder - kpush $11 - kpush $31 -$kpl: lbu $10, 0($11) - addiu $11, 1 - blez $10, $kpex - nop - jal _ksaus - nop - j $kpl - nop -$kpex: kpop $31 - kpop $11 - jr $31 - nop - .set reorder - diff --git a/lib/CPUs/MIPS/sim/asm/link.ld b/lib/CPUs/MIPS/sim/asm/link.ld deleted file mode 100644 index e175fa8..0000000 --- a/lib/CPUs/MIPS/sim/asm/link.ld +++ /dev/null @@ -1,47 +0,0 @@ -MEMORY -{ - imem : ORIGIN = 0x00400000, LENGTH = 0x00004000 /* 8K */ - dmem : ORIGIN = 0x00000000, LENGTH = 0x00002000 /* 8K */ -} - -end = 0x7FFFEFFC; -baudrate = 0x0D; -sys_led_port = 0x80000000; -sys_uart_baud = 0x80000009; -sys_uart_stat = 0x80000008; -sys_uart_data = 0x80000004; -sys_timer_sec = 0x80000014; -sys_timer_usec = 0x80000010; - -SECTIONS -{ - .stext 0x00400000 : - { - *(.stext) - } > imem - - .ktext 0x00400180 : - { - *(.ktext) - } > imem - - .text . : - { - *(.text) - } > imem - - .data 0x00000000 : ALIGN(2) - { - *(.rodata*) *(.data) *(.sdata) *(.sbss) *(.kdata) - } > dmem - - .bss . : - { - *(.bss) - } > dmem - - .eh_frame . : - { - *(.eh_frame) - } > dmem -} diff --git a/lib/CPUs/MIPS/sim/asm/load_store.c b/lib/CPUs/MIPS/sim/asm/load_store.c deleted file mode 100644 index b39630e..0000000 --- a/lib/CPUs/MIPS/sim/asm/load_store.c +++ /dev/null @@ -1,64 +0,0 @@ -//#include -//#include -//#include - -int main (void) -{ - - -__asm -( - ".set noreorder\n" - "li $8, 0x81234678\n" - "li $15, 0x10000000\n" - "li $16, 0xAAAAAAAA\n" - "li $17, 0xBBBBBBBB\n" - "li $18, 0xCCCCCCCC\n" - "li $19, 0xDDDDDDDD\n" - "li $24, 0x11111111\n" - "li $25, 0x22222222\n" - "li $26, 0x33333333\n" - "li $27, 0x44444444\n" - "sw $8, 0($15)\n" - "nop\n" - "lwl $16, 0($15)\n" - "lwl $17, 1($15)\n" - "lwl $18, 2($15)\n" - "lwl $19, 3($15)\n" - "nop\n" - "lwr $24, 0($15)\n" - "lwr $25, 1($15)\n" - "lwr $26, 2($15)\n" - "lwr $27, 3($15)\n" - "nop\n" - "lbu $16, 0($15)\n" - "lbu $17, 1($15)\n" - "lbu $18, 2($15)\n" - "lbu $19, 3($15)\n" - "nop\n" - "lb $16, 0($15)\n" - "lb $17, 1($15)\n" - "lb $18, 2($15)\n" - "lb $19, 3($15)\n" - "nop\n" - "swl $8, 4($15)\n" - "swl $8, 9($15)\n" - "swl $8, 14($15)\n" - "swl $8, 19($15)\n" - "nop\n" - "swr $8, 20($15)\n" - "swr $8, 25($15)\n" - "swr $8, 30($15)\n" - "swr $8, 35($15)\n" - "nop\n" - "sb $8, 4($15)\n" - "sb $8, 5($15)\n" - "sb $8, 6($15)\n" - "sb $8, 7($15)\n" - "nop\n" - ".set reorder\n" - -); - -} - diff --git a/lib/CPUs/MIPS/sim/asm/load_store.s b/lib/CPUs/MIPS/sim/asm/load_store.s deleted file mode 100644 index 9aa8fca..0000000 --- a/lib/CPUs/MIPS/sim/asm/load_store.s +++ /dev/null @@ -1,64 +0,0 @@ - .file 1 "load_store.c" - .set nobopt - .text - .align 2 - .globl main - .ent main -main: - .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 - .mask 0x00000000,0 - .fmask 0x00000000,0 - #APP - .set noreorder -li $8, 0x81234678 -li $15, 0x10000000 -li $16, 0xAAAAAAAA -li $17, 0xBBBBBBBB -li $18, 0xCCCCCCCC -li $19, 0xDDDDDDDD -li $24, 0x11111111 -li $25, 0x22222222 -li $26, 0x33333333 -li $27, 0x44444444 -sw $8, 0($15) -nop -lwl $16, 0($15) -lwl $17, 1($15) -lwl $18, 2($15) -lwl $19, 3($15) -nop -lwr $24, 0($15) -lwr $25, 1($15) -lwr $26, 2($15) -lwr $27, 3($15) -nop -lbu $16, 0($15) -lbu $17, 1($15) -lbu $18, 2($15) -lbu $19, 3($15) -nop -lb $16, 0($15) -lb $17, 1($15) -lb $18, 2($15) -lb $19, 3($15) -nop -swl $8, 4($15) -swl $8, 9($15) -swl $8, 14($15) -swl $8, 19($15) -nop -swr $8, 20($15) -swr $8, 25($15) -swr $8, 30($15) -swr $8, 35($15) -nop -sb $8, 4($15) -sb $8, 5($15) -sb $8, 6($15) -sb $8, 7($15) -nop -.set reorder - - #NO_APP - j $31 - .end main diff --git a/lib/CPUs/MIPS/sim/asm/make.sh b/lib/CPUs/MIPS/sim/asm/make.sh deleted file mode 100644 index 2f39996..0000000 --- a/lib/CPUs/MIPS/sim/asm/make.sh +++ /dev/null @@ -1,30 +0,0 @@ -#!/bin/sh - -TARGET=$(basename $1 .c) -TARGET_CPU=r3000 -ROM_WORDADDR_WIDTH=12 -RAM_WORDADDR_WIDTH=11 - -echo Building $TARGET... - -mipsel-elf-as.exe -march=$TARGET_CPU startup.s -o startup.o -mipsel-elf-as.exe -march=$TARGET_CPU init.s -o init.o -mipsel-elf-as.exe -march=$TARGET_CPU kernel.s -o kernel.o - -#mipsel-elf-gcc -O2 -march=$TARGET_CPU $TARGET.c -o $TARGET.s -L $LIBDIR - -mipsel-elf-gcc -msoft-float -O2 -c utils.c -o utils.o -mipsel-elf-gcc -msoft-float -O2 -c $TARGET.c -o $TARGET.o -mipsel-elf-ld.exe -G 0 -M -T link.ld startup.o init.o kernel.o utils.o $TARGET.o -o $TARGET.elf -L /usr/local/mipsel-elf/lib -L /usr/local/lib/gcc/mipsel-elf/3.4.6 -lc -lgcc >$TARGET.map -mipsel-elf-objdump.exe -d $TARGET.elf > $TARGET.dis - -mipsel-elf-objcopy.exe -j .stext -j .ktext -j .text $TARGET.elf -O binary $TARGET.ROM.bin -mipsel-elf-objcopy.exe -j .data $TARGET.elf -O binary $TARGET.RAM.bin - -./romgen.exe $TARGET.ROM.bin $ROM_WORDADDR_WIDTH -./ramgen.exe $TARGET.RAM.bin $RAM_WORDADDR_WIDTH - -#xtclsh.exe $TARGET.RAM.tcl -#xtclsh.exe $TARGET.ROM.tcl - -echo done. \ No newline at end of file diff --git a/lib/CPUs/MIPS/sim/asm/mips_exception.s b/lib/CPUs/MIPS/sim/asm/mips_exception.s deleted file mode 100644 index c8c88a1..0000000 --- a/lib/CPUs/MIPS/sim/asm/mips_exception.s +++ /dev/null @@ -1,31 +0,0 @@ -main: - j lab -# nop -# break 52 -lab: - li, $8, 0x81234678 - -# SB - li, $15, 0x10000000 - li $16, 0x00400014 - mtc0, $16, $14 - nop - nop - rfe - -# Address error exception - sw $8, 1($15) - sw $8, 2($15) - sw $8, 3($15) - -# Address error exception - sh $8, 1($15) - -# Address error exception - sh $8, 3($15) - - - nop - nop - nop - \ No newline at end of file diff --git a/lib/CPUs/MIPS/sim/asm/mips_load_store_.txt b/lib/CPUs/MIPS/sim/asm/mips_load_store_.txt deleted file mode 100644 index 30b75bc..0000000 --- a/lib/CPUs/MIPS/sim/asm/mips_load_store_.txt +++ /dev/null @@ -1,86 +0,0 @@ -SB (tested by SPIM) -VA(1..0) DMEM_WE ROL -0 0001 0 -1 0010 1 -2 0100 2 -3 1000 3 - -SH (tested by SPIM) -VA(1..0) DMEM_WE ROL -0 0011 0 -2 1100 2 - -SWL (tested by SPIM) -VA(1..0) DMEM_WE ROL -0 0001 1 -1 0011 2 -2 0111 3 -3 1111 0 - -SWR (tested by SPIM) -VA(1..0) DMEM_WE ROL -0 1111 0 -1 1110 1 -2 1100 2 -3 1000 3 - -LB (tested by SPIM) -VA(1..0) REG_WE ROR -0 1111 0 -1 1111 1 -2 1111 2 -3 1111 3 - -LH (tested by SPIM) -VA(1..0) REG_WE ROR -0 1111 0 -2 1111 2 - -LWL (tested by SPIM) -VA(1..0) REG_WE ROR -0 1000 1 -1 1100 2 -2 1110 3 -3 1111 0 - -LWR (tested by SPIM) -VA(1..0) REG_WE ROR -0 1111 0 -1 0111 1 -2 0011 2 -3 0001 3 - - - -*SHIFTER* SB SH SWL SWR SW -shift_byp 0 0 0 0 1 -shift_off 0 0 1 0 x - -SHL = VA + shift_off - -*Byte Enable* SB SH SWL SWR SW -be_byp 0 0 0 0 1 -quarter_word_en 1 0 0 0 x -half_word_en 0 1 0 0 x -align_left x x 0 1 x - - -*SHIFTER* LB LH LWL LWR LW -shift_byp 0 0 0 0 1 -shift_off 0 0 1 0 x - -SHL = VA + shift_off - -*Byte Enable* LB LH LWL LWR LW -be_byp 1 1 0 0 1 -align_left x x 1 0 x - - -* Sign ext* -se_byp = shift_byp and (shift_byp and not be_byp) - - -00 11 -01 10 -10 01 -11 00 diff --git a/lib/CPUs/MIPS/sim/asm/muldiv.c b/lib/CPUs/MIPS/sim/asm/muldiv.c deleted file mode 100644 index 1f15755..0000000 --- a/lib/CPUs/MIPS/sim/asm/muldiv.c +++ /dev/null @@ -1,134 +0,0 @@ -//#include -#include -//#include - -#define NUM_ELEMENTS 100 -#define NUM_RUNS 1000 - -char sein(void) -{ - volatile char *pUART_stat = (char*)0x80000008; - volatile char *pUART_data = (char*)0x80000004; - - while(!(0x10 & *pUART_stat)); - - return *pUART_data; -} - -void saus(char c) -{ - volatile char *pUART_stat = (char*)0x80000008; - volatile char *pUART_data = (char*)0x80000004; - - while((0x02 & *pUART_stat) != 0); - - *pUART_data = c; -} - -int sputs(char *pStr) -{ - char *start; - start = pStr; - - while(*pStr) - saus(*(pStr++)); - - return pStr - start; -} - -void print_byte(char byte) -{ - int i; - unsigned char c, nibble; - - for (i=0; i < 2; i++) - { - nibble = (char)((byte >> 4) & 0xF); - byte <<= 4; - - if (nibble < 10) - c = nibble + '0'; - else - c = nibble + 'A' - 10; - - saus(c); - } -} - -void print_word(int word) -{ - int i; - unsigned char c, nibble; - - for (i=0; i < 4; i++) - { - c = (char) (word >> 24); - print_byte(c); - word <<= 8; - } -} - -int main (void) -{ - int cnt, i, j; - int mix, *pReg = (int*)0x80000000; - volatile char *pUART_data = (char*)0x80000004; - volatile char *pUART_ctrl = (char*)0x80000008; - volatile char *pUART_baud = (char*)0x80000009; - char msg[] = "MIPS R3000 CPU\r\nMul/Div Test\r\n"; - int s1, s2, sp, st; - - div_t div_res; - - *pUART_baud = 0x35; - *pUART_ctrl = 0x55; - - srand(0x19701031); - - sputs(msg); - - cnt = 0; - while(1) - { - for (i=0; i < 1000; i++) - { - for (j=1; j < 1000; j++) - { - mix = (int)rand(); - mix = (mix << 8) ^ (mix << 16); - s1 = (int)rand() ^ mix; - mix = (int)rand(); - mix = (mix << 8) ^ (mix << 16); - s2 = (int)rand() ^ mix; - // s1 = i; - // s2 = j; - - div_res = div(s1, s2); - - // print_word(s1); - // sputs(" / "); - // print_word(s2); - // sputs(" = "); - // print_word(div_res.quot); - // sputs(" R: "); - // print_word(div_res.rem); - // sputs(" -- "); - - sp = s2*div_res.quot; - st = div_res.rem + sp; - if (st != s1) - { - sputs("Failed: "); - sputs("d*quot = "); - print_word(sp); - sputs("\r\n"); - return -1; - } - } - } - sputs("Iteration "); - print_word(cnt++); - sputs(": Passed\r\n"); - } -} - diff --git a/lib/CPUs/MIPS/sim/asm/muldiv.s b/lib/CPUs/MIPS/sim/asm/muldiv.s deleted file mode 100644 index c6de7d9..0000000 --- a/lib/CPUs/MIPS/sim/asm/muldiv.s +++ /dev/null @@ -1,391 +0,0 @@ - .file 1 "muldiv.c" - .set nobopt - .text - .align 2 - .globl sein - .ent sein -sein: - .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 - .mask 0x00000000,0 - .fmask 0x00000000,0 - li $2,-2147483648 # 0xffffffff80000000 - ori $4,$2,0x4 - ori $3,$2,0x8 -$L2: - lbu $2,0($3) - andi $2,$2,0x10 - beq $2,$0,$L2 - lbu $2,0($4) - sll $2,$2,24 - .set noreorder - .set nomacro - j $31 - sra $2,$2,24 - .set macro - .set reorder - - .end sein - .align 2 - .globl saus - .ent saus -saus: - .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 - .mask 0x00000000,0 - .fmask 0x00000000,0 - li $2,-2147483648 # 0xffffffff80000000 - sll $4,$4,24 - sra $4,$4,24 - ori $5,$2,0x4 - ori $3,$2,0x8 -$L6: - lbu $2,0($3) - andi $2,$2,0x2 - bne $2,$0,$L6 - sb $4,0($5) - j $31 - .end saus - .align 2 - .globl sputs - .ent sputs -sputs: - .frame $sp,32,$31 # vars= 0, regs= 3/0, args= 16, gp= 0 - .mask 0x80030000,-8 - .fmask 0x00000000,0 - addiu $sp,$sp,-32 - sw $17,20($sp) - sw $16,16($sp) - sw $31,24($sp) - move $16,$4 - lb $4,0($4) - .set noreorder - .set nomacro - j $L14 - move $17,$16 - .set macro - .set reorder - -$L15: - .set noreorder - .set nomacro - jal saus - addiu $16,$16,1 - .set macro - .set reorder - - lb $4,0($16) -$L14: - .set noreorder - .set nomacro - bne $4,$0,$L15 - subu $2,$16,$17 - .set macro - .set reorder - - lw $31,24($sp) - lw $17,20($sp) - lw $16,16($sp) - .set noreorder - .set nomacro - j $31 - addiu $sp,$sp,32 - .set macro - .set reorder - - .end sputs - .align 2 - .globl print_byte - .ent print_byte -print_byte: - .frame $sp,32,$31 # vars= 0, regs= 3/0, args= 16, gp= 0 - .mask 0x80030000,-8 - .fmask 0x00000000,0 - addiu $sp,$sp,-32 - sw $16,16($sp) - sll $16,$4,24 - sw $17,20($sp) - sw $31,24($sp) - sra $16,$16,24 - li $17,1 # 0x1 - sra $2,$16,4 -$L25: - andi $5,$2,0xf - sll $2,$16,4 - sll $16,$2,24 - sltu $3,$5,10 - addiu $17,$17,-1 - sra $16,$16,24 - .set noreorder - .set nomacro - bne $3,$0,$L21 - addiu $4,$5,48 - .set macro - .set reorder - - addiu $4,$5,55 -$L21: - jal saus - .set noreorder - .set nomacro - bgez $17,$L25 - sra $2,$16,4 - .set macro - .set reorder - - lw $31,24($sp) - lw $17,20($sp) - lw $16,16($sp) - .set noreorder - .set nomacro - j $31 - addiu $sp,$sp,32 - .set macro - .set reorder - - .end print_byte - .align 2 - .globl print_word - .ent print_word -print_word: - .frame $sp,32,$31 # vars= 0, regs= 3/0, args= 16, gp= 0 - .mask 0x80030000,-8 - .fmask 0x00000000,0 - addiu $sp,$sp,-32 - sw $17,20($sp) - sw $16,16($sp) - sw $31,24($sp) - move $16,$4 - li $17,3 # 0x3 -$L30: - sra $4,$16,24 - .set noreorder - .set nomacro - jal print_byte - addiu $17,$17,-1 - .set macro - .set reorder - - .set noreorder - .set nomacro - bgez $17,$L30 - sll $16,$16,8 - .set macro - .set reorder - - lw $31,24($sp) - lw $17,20($sp) - lw $16,16($sp) - .set noreorder - .set nomacro - j $31 - addiu $sp,$sp,32 - .set macro - .set reorder - - .end print_word - .section .rodata.str1.4,"aMS",@progbits,1 - .align 2 -$LC0: - .ascii "MIPS R3000 CPU\r\n" - .ascii "Mul/Div Test\r\n\000" - .align 2 -$LC1: - .ascii "Failed: \000" - .align 2 -$LC2: - .ascii "d*quot = \000" - .align 2 -$LC3: - .ascii "\r\n\000" - .align 2 -$LC4: - .ascii "Iteration \000" - .align 2 -$LC5: - .ascii ": Passed\r\n\000" - .text - .align 2 - .globl main - .ent main -main: - .frame $sp,88,$31 # vars= 40, regs= 7/0, args= 16, gp= 0 - .mask 0x803f0000,-8 - .fmask 0x00000000,0 - lw $2,$LC0 - addiu $sp,$sp,-88 - sw $2,16($sp) - lw $3,$LC0+4 - lw $2,$LC0+8 - sw $3,20($sp) - sw $2,24($sp) - lw $3,$LC0+12 - lw $2,$LC0+16 - sw $3,28($sp) - sw $2,32($sp) - lw $3,$LC0+20 - lw $2,$LC0+24 - sw $3,36($sp) - sw $2,40($sp) - lhu $3,$LC0+28 - lbu $2,$LC0+30 - li $5,-2147483648 # 0xffffffff80000000 - ori $6,$5,0x9 - sh $3,44($sp) - sb $2,46($sp) - ori $5,$5,0x8 - li $3,53 - li $2,85 - li $4,426770432 # 0x19700000 - sb $3,0($6) - ori $4,$4,0x1031 - sb $2,0($5) - sw $31,80($sp) - sw $21,76($sp) - sw $19,68($sp) - sw $20,72($sp) - sw $18,64($sp) - sw $17,60($sp) - .set noreorder - .set nomacro - jal srand - sw $16,56($sp) - .set macro - .set reorder - - .set noreorder - .set nomacro - jal sputs - addiu $4,$sp,16 - .set macro - .set reorder - - move $21,$0 - addiu $19,$sp,48 - move $20,$0 -$L44: - .set noreorder - .set nomacro - j $L43 - li $18,1 # 0x1 - .set macro - .set reorder - -$L51: - beq $3,$0,$L50 -$L43: - .set noreorder - .set nomacro - jal rand - addiu $18,$18,1 - .set macro - .set reorder - - sll $3,$2,16 - sll $2,$2,8 - .set noreorder - .set nomacro - jal rand - xor $16,$2,$3 - .set macro - .set reorder - - .set noreorder - .set nomacro - jal rand - xor $17,$2,$16 - .set macro - .set reorder - - sll $3,$2,16 - sll $2,$2,8 - .set noreorder - .set nomacro - jal rand - xor $16,$2,$3 - .set macro - .set reorder - - xor $16,$2,$16 - move $6,$16 - move $4,$19 - .set noreorder - .set nomacro - jal div - move $5,$17 - .set macro - .set reorder - - lw $2,48($sp) - mult $2,$16 - lw $2,52($sp) - mflo $16 - addu $2,$2,$16 - .set noreorder - .set nomacro - beq $2,$17,$L51 - slt $3,$18,1000 - .set macro - .set reorder - - la $4,$LC1 - jal sputs - la $4,$LC2 - jal sputs - .set noreorder - .set nomacro - jal print_word - move $4,$16 - .set macro - .set reorder - - la $4,$LC3 - jal sputs - lw $31,80($sp) - lw $21,76($sp) - lw $20,72($sp) - lw $19,68($sp) - lw $18,64($sp) - lw $17,60($sp) - lw $16,56($sp) - li $2,-1 # 0xffffffffffffffff - .set noreorder - .set nomacro - j $31 - addiu $sp,$sp,88 - .set macro - .set reorder - -$L50: - addiu $20,$20,1 - slt $2,$20,1000 - bne $2,$0,$L44 - la $4,$LC4 - .set noreorder - .set nomacro - jal sputs - move $20,$0 - .set macro - .set reorder - - .set noreorder - .set nomacro - jal print_word - move $4,$21 - .set macro - .set reorder - - la $4,$LC5 - .set noreorder - .set nomacro - jal sputs - addiu $21,$21,1 - .set macro - .set reorder - - .set noreorder - .set nomacro - j $L43 - li $18,1 # 0x1 - .set macro - .set reorder - - .end main diff --git a/lib/CPUs/MIPS/sim/asm/mult.txt b/lib/CPUs/MIPS/sim/asm/mult.txt deleted file mode 100644 index 72f9226..0000000 --- a/lib/CPUs/MIPS/sim/asm/mult.txt +++ /dev/null @@ -1,27 +0,0 @@ -0x12345678 x 0x87654321 -HI = f76c768d LO = 70b88d78 signed -HI = 09a0cd05 LO = 70b88d78 unsigned - -0x87654321 x 0x12345678 -HI = f76c768d LO = 70b88d78 signed -HI = 09a0cd05 LO = 70b88d78 unsigned - -0x12345678 x 0x12345678 -HI = 014b66dc LO = 1df4d840 signed -HI = 014b66dc LO = 1df4d840 unsigned - -0x87654321 x 0x87654321 -HI = 38d16e98 LO = d7a44a41 signed -HI = 479bf4da LO = d7a44a41 unsigned - - -p1 * n2 = not(p1 * (1 + not(n2))) - -n1 * p1 = not((1 + not(n1)) * p2) - -p1 * p2 = p1 * p2 - -n1 * n2 = not(n1) * not(n2); - - -12345678 * ( 87654321 not and FFFFFFFF ) = + 12345677 = \ No newline at end of file diff --git a/lib/CPUs/MIPS/sim/asm/rmd160.s b/lib/CPUs/MIPS/sim/asm/rmd160.s deleted file mode 100644 index 6028ab9..0000000 --- a/lib/CPUs/MIPS/sim/asm/rmd160.s +++ /dev/null @@ -1,2482 +0,0 @@ - .file 1 "rmd160.c" - .set nobopt - .text - .align 2 - .globl MDinit - .ent MDinit -MDinit: - .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 - .mask 0x00000000,0 - .fmask 0x00000000,0 - li $2,-1009647616 # 0xffffffffc3d20000 - ori $2,$2,0xe1f0 - sw $2,16($4) - li $3,1732575232 # 0x67450000 - li $2,-271777792 # 0xffffffffefcd0000 - ori $3,$3,0x2301 - ori $2,$2,0xab89 - sw $3,0($4) - sw $2,4($4) - li $3,-1732640768 # 0xffffffff98ba0000 - li $2,271712256 # 0x10320000 - ori $3,$3,0xdcfe - ori $2,$2,0x5476 - sw $3,8($4) - .set noreorder - .set nomacro - j $31 - sw $2,12($4) - .set macro - .set reorder - - .end MDinit - .align 2 - .globl compress - .ent compress -compress: - .frame $sp,128,$31 # vars= 88, regs= 9/0, args= 0, gp= 0 - .mask 0x40ff0000,-8 - .fmask 0x00000000,0 - addiu $sp,$sp,-128 - sw $19,100($sp) - lw $19,12($4) - sw $20,104($sp) - lw $24,4($4) - lw $20,8($4) - sw $fp,120($sp) - sw $23,116($sp) - sw $22,112($sp) - sw $21,108($sp) - sw $18,96($sp) - sw $17,92($sp) - sw $16,88($sp) - nor $2,$0,$19 - lw $6,20($5) - lw $7,0($5) - lw $21,0($4) - xor $3,$24,$20 - or $2,$2,$20 - xor $3,$3,$19 - xor $2,$2,$24 - addu $3,$3,$7 - move $17,$21 - addu $2,$2,$6 - li $11,1352794112 # 0x50a20000 - ori $11,$11,0x8be6 - addu $21,$21,$3 - addu $2,$2,$17 - addu $17,$2,$11 - lw $25,16($4) - sw $6,12($sp) - srl $3,$21,21 - srl $8,$20,22 - sll $6,$20,10 - sll $2,$21,11 - or $23,$6,$8 - or $2,$2,$3 - srl $7,$17,24 - sll $3,$17,8 - addu $21,$2,$25 - or $3,$3,$7 - nor $2,$0,$23 - addu $17,$3,$25 - lw $8,56($5) - lw $6,4($5) - xor $3,$21,$24 - or $2,$2,$24 - xor $3,$3,$23 - xor $2,$2,$17 - move $fp,$25 - addu $3,$3,$6 - addu $2,$2,$8 - addu $25,$25,$3 - addu $2,$2,$fp - addu $fp,$2,$11 - sw $8,36($sp) - srl $3,$25,18 - srl $8,$24,22 - sll $6,$24,10 - sll $2,$25,14 - or $22,$6,$8 - or $2,$2,$3 - srl $7,$fp,23 - sll $3,$fp,9 - addu $25,$2,$19 - or $3,$3,$7 - nor $2,$0,$22 - addu $fp,$3,$19 - lw $7,8($5) - lw $8,28($5) - xor $3,$25,$21 - or $2,$2,$17 - xor $3,$3,$22 - xor $2,$2,$fp - move $18,$19 - addu $3,$3,$7 - addu $2,$2,$8 - addu $19,$19,$3 - addu $2,$2,$18 - addu $18,$2,$11 - sw $7,0($sp) - srl $6,$17,22 - srl $7,$19,17 - sll $3,$19,15 - sll $2,$17,10 - or $17,$2,$6 - or $3,$3,$7 - srl $2,$18,23 - sll $6,$18,9 - addu $19,$3,$23 - or $6,$6,$2 - srl $7,$21,22 - nor $2,$0,$17 - sll $3,$21,10 - addu $18,$6,$23 - or $21,$3,$7 - lw $6,0($5) - lw $7,12($5) - xor $3,$19,$25 - or $2,$2,$fp - xor $3,$3,$21 - xor $2,$2,$18 - addu $3,$3,$7 - addu $2,$2,$6 - addu $20,$23,$3 - addu $2,$2,$23 - addu $23,$2,$11 - sw $6,8($sp) - srl $7,$20,20 - srl $6,$fp,22 - sll $3,$20,12 - sll $2,$fp,10 - or $fp,$2,$6 - or $3,$3,$7 - srl $2,$23,21 - sll $6,$23,11 - addu $20,$3,$22 - or $6,$6,$2 - srl $7,$25,22 - nor $2,$0,$fp - sll $3,$25,10 - addu $23,$6,$22 - or $25,$3,$7 - lw $6,16($5) - sw $8,20($sp) - xor $3,$20,$19 - lw $8,36($5) - or $2,$2,$18 - xor $3,$3,$25 - xor $2,$2,$23 - addu $3,$3,$6 - addu $2,$2,$8 - addu $24,$22,$3 - addu $2,$2,$22 - addu $22,$2,$11 - srl $7,$24,27 - srl $6,$18,22 - sll $3,$24,5 - sll $2,$18,10 - or $18,$2,$6 - or $3,$3,$7 - srl $2,$22,19 - sll $6,$22,13 - addu $24,$3,$21 - or $6,$6,$2 - srl $7,$19,22 - nor $2,$0,$18 - sll $3,$19,10 - addu $22,$6,$17 - or $19,$3,$7 - or $2,$2,$23 - lw $7,0($sp) - sw $8,16($sp) - xor $3,$24,$20 - lw $8,20($5) - xor $2,$2,$22 - xor $3,$3,$19 - addu $2,$2,$7 - addu $3,$3,$8 - addu $2,$2,$17 - addu $17,$2,$11 - addu $21,$21,$3 - srl $6,$23,22 - sll $2,$23,10 - or $23,$2,$6 - sw $7,28($sp) - srl $2,$17,17 - srl $7,$21,24 - sll $3,$21,8 - sll $6,$17,15 - or $3,$3,$7 - or $6,$6,$2 - srl $7,$20,22 - sll $2,$20,10 - or $20,$2,$7 - lw $2,44($5) - addu $21,$3,$25 - nor $3,$0,$23 - sw $2,44($sp) - addu $17,$6,$fp - lw $7,44($sp) - lw $6,24($5) - xor $2,$21,$24 - or $3,$3,$22 - xor $2,$2,$20 - xor $3,$3,$17 - addu $2,$2,$6 - addu $3,$3,$7 - addu $25,$25,$2 - addu $3,$3,$fp - addu $fp,$3,$11 - srl $7,$25,25 - srl $6,$22,22 - sll $3,$25,7 - sll $2,$22,10 - or $22,$2,$6 - or $3,$3,$7 - srl $2,$fp,17 - sll $6,$fp,15 - addu $25,$3,$19 - or $6,$6,$2 - srl $7,$24,22 - nor $2,$0,$22 - sll $3,$24,10 - addu $fp,$6,$18 - or $24,$3,$7 - lw $8,16($5) - lw $6,28($5) - xor $3,$25,$21 - or $2,$2,$17 - xor $3,$3,$24 - xor $2,$2,$fp - addu $3,$3,$6 - addu $2,$2,$8 - addu $19,$19,$3 - addu $2,$2,$18 - addu $18,$2,$11 - srl $7,$19,23 - srl $6,$17,22 - sll $3,$19,9 - sll $2,$17,10 - or $17,$2,$6 - or $3,$3,$7 - srl $2,$18,27 - sll $6,$18,5 - addu $19,$3,$20 - or $6,$6,$2 - srl $7,$21,22 - nor $3,$0,$17 - sll $2,$21,10 - addu $18,$6,$23 - or $21,$2,$7 - sw $8,4($sp) - lw $7,52($5) - lw $8,32($5) - xor $2,$19,$25 - or $3,$3,$fp - xor $2,$2,$21 - xor $3,$3,$18 - addu $2,$2,$8 - addu $3,$3,$7 - addu $20,$20,$2 - addu $3,$3,$23 - addu $23,$3,$11 - sw $7,52($sp) - srl $6,$fp,22 - srl $7,$20,21 - sll $3,$20,11 - sll $2,$fp,10 - or $fp,$2,$6 - or $3,$3,$7 - srl $2,$23,25 - sll $6,$23,7 - addu $20,$3,$24 - or $6,$6,$2 - srl $7,$25,22 - nor $3,$0,$fp - sll $2,$25,10 - lw $12,24($5) - addu $23,$6,$22 - or $25,$2,$7 - lw $6,36($5) - xor $2,$20,$19 - or $3,$3,$18 - xor $2,$2,$25 - xor $3,$3,$23 - addu $2,$2,$6 - addu $3,$3,$12 - addu $24,$24,$2 - addu $3,$3,$22 - addu $22,$3,$11 - srl $7,$24,19 - srl $6,$18,22 - sll $3,$24,13 - sll $2,$18,10 - or $18,$2,$6 - or $3,$3,$7 - srl $2,$22,25 - sll $6,$22,7 - addu $24,$3,$21 - or $6,$6,$2 - srl $7,$19,22 - nor $3,$0,$18 - sll $2,$19,10 - addu $22,$6,$17 - or $19,$2,$7 - lw $8,40($5) - lw $7,60($5) - xor $2,$24,$20 - or $3,$3,$23 - xor $2,$2,$19 - xor $3,$3,$22 - addu $2,$2,$8 - addu $3,$3,$7 - addu $21,$21,$2 - addu $3,$3,$17 - sw $7,48($sp) - addu $17,$3,$11 - srl $7,$21,18 - srl $6,$23,22 - sll $3,$21,14 - sll $2,$23,10 - or $23,$2,$6 - or $3,$3,$7 - srl $2,$17,24 - sll $6,$17,8 - addu $21,$3,$25 - or $6,$6,$2 - srl $7,$20,22 - nor $3,$0,$23 - sll $2,$20,10 - lw $13,32($5) - addu $17,$6,$fp - or $20,$2,$7 - lw $6,44($5) - xor $2,$21,$24 - or $3,$3,$22 - xor $2,$2,$20 - xor $3,$3,$17 - addu $2,$2,$6 - addu $3,$3,$13 - addu $25,$25,$2 - addu $3,$3,$fp - addu $fp,$3,$11 - srl $7,$25,17 - srl $6,$22,22 - sll $3,$25,15 - sll $2,$22,10 - or $22,$2,$6 - or $3,$3,$7 - srl $2,$fp,21 - sll $6,$fp,11 - addu $25,$3,$19 - or $6,$6,$2 - srl $7,$24,22 - nor $2,$0,$22 - sll $3,$24,10 - addu $fp,$6,$18 - or $24,$3,$7 - lw $8,48($5) - lw $7,4($5) - xor $3,$25,$21 - or $2,$2,$17 - xor $3,$3,$24 - xor $2,$2,$fp - addu $3,$3,$8 - addu $2,$2,$7 - addu $19,$19,$3 - addu $2,$2,$18 - sw $7,40($sp) - addu $18,$2,$11 - srl $7,$19,26 - srl $6,$17,22 - sll $3,$19,6 - sll $2,$17,10 - or $17,$2,$6 - or $3,$3,$7 - srl $2,$18,18 - sll $6,$18,14 - addu $19,$3,$20 - or $6,$6,$2 - srl $7,$21,22 - nor $2,$0,$17 - sll $3,$21,10 - addu $18,$6,$23 - or $21,$3,$7 - lw $6,40($5) - lw $7,52($5) - xor $3,$19,$25 - or $2,$2,$fp - xor $3,$3,$21 - xor $2,$2,$18 - addu $3,$3,$7 - addu $2,$2,$6 - addu $20,$20,$3 - addu $2,$2,$23 - sw $6,32($sp) - addu $23,$2,$11 - srl $7,$20,25 - srl $6,$fp,22 - sll $3,$20,7 - sll $2,$fp,10 - or $fp,$2,$6 - or $3,$3,$7 - srl $2,$23,18 - sll $6,$23,14 - addu $20,$3,$24 - or $6,$6,$2 - srl $7,$25,22 - nor $3,$0,$fp - sll $2,$25,10 - lw $16,12($5) - addu $23,$6,$22 - or $25,$2,$7 - lw $8,56($5) - xor $2,$20,$19 - or $3,$3,$18 - xor $2,$2,$25 - xor $3,$3,$23 - addu $2,$2,$8 - addu $3,$3,$16 - addu $24,$24,$2 - addu $3,$3,$22 - addu $22,$3,$11 - srl $7,$24,23 - sll $3,$24,9 - or $3,$3,$7 - srl $6,$18,22 - sll $2,$18,10 - addu $24,$3,$21 - or $18,$2,$6 - srl $7,$19,22 - srl $2,$22,20 - sll $6,$22,12 - sll $3,$19,10 - or $19,$3,$7 - or $6,$6,$2 - lw $7,60($5) - xor $3,$24,$20 - nor $2,$0,$18 - addu $22,$6,$17 - or $2,$2,$23 - lw $6,48($5) - xor $3,$3,$19 - addu $3,$3,$7 - xor $2,$2,$22 - addu $21,$21,$3 - addu $2,$2,$6 - sw $6,24($sp) - srl $3,$21,24 - addu $2,$2,$17 - sll $6,$21,8 - addu $17,$2,$11 - or $6,$6,$3 - srl $7,$23,22 - sll $2,$23,10 - or $23,$2,$7 - addu $21,$6,$25 - srl $8,$17,26 - sll $3,$17,6 - srl $7,$20,22 - sll $2,$20,10 - or $20,$2,$7 - or $3,$3,$8 - nor $6,$0,$21 - addu $17,$3,$fp - lw $8,28($5) - and $6,$6,$20 - and $2,$21,$24 - nor $7,$0,$23 - and $7,$7,$22 - and $3,$17,$23 - or $2,$2,$6 - or $3,$3,$7 - addu $2,$2,$8 - li $11,1518469120 # 0x5a820000 - ori $11,$11,0x7999 - addu $2,$2,$25 - addu $3,$3,$12 - li $10,1548550144 # 0x5c4d0000 - ori $10,$10,0xd124 - addu $25,$2,$11 - addu $3,$3,$fp - addu $fp,$3,$10 - srl $8,$25,25 - sll $3,$25,7 - srl $9,$fp,23 - or $3,$3,$8 - srl $7,$22,22 - sll $6,$fp,9 - sll $2,$22,10 - addu $25,$3,$19 - or $22,$2,$7 - or $6,$6,$9 - srl $3,$24,22 - sll $2,$24,10 - addu $fp,$6,$18 - or $24,$2,$3 - nor $6,$0,$25 - and $6,$6,$24 - and $2,$25,$21 - nor $7,$0,$22 - and $7,$7,$17 - and $3,$fp,$22 - or $2,$2,$6 - lw $6,44($sp) - or $3,$3,$7 - lw $7,16($5) - addu $3,$3,$6 - addu $3,$3,$18 - addu $2,$2,$7 - addu $18,$3,$10 - addu $2,$2,$19 - addu $19,$2,$11 - srl $7,$18,19 - srl $6,$17,22 - sll $3,$18,13 - sll $2,$17,10 - or $17,$2,$6 - or $3,$3,$7 - srl $6,$19,26 - sll $2,$19,6 - addu $18,$3,$23 - or $2,$2,$6 - nor $6,$0,$17 - addu $19,$2,$20 - and $6,$6,$fp - and $2,$18,$17 - srl $7,$21,22 - sll $3,$21,10 - or $2,$2,$6 - or $21,$3,$7 - addu $2,$2,$16 - nor $3,$0,$19 - lw $8,52($5) - and $3,$3,$21 - and $6,$19,$25 - addu $2,$2,$23 - addu $23,$2,$10 - or $6,$6,$3 - addu $6,$6,$8 - srl $7,$fp,22 - srl $8,$23,17 - sll $3,$23,15 - sll $2,$fp,10 - or $fp,$2,$7 - or $3,$3,$8 - addu $6,$6,$20 - addu $23,$3,$22 - addu $20,$6,$11 - nor $2,$0,$fp - srl $7,$20,24 - and $2,$2,$18 - and $3,$23,$fp - sll $6,$20,8 - or $6,$6,$7 - or $3,$3,$2 - srl $7,$25,22 - sll $2,$25,10 - or $25,$2,$7 - lw $2,20($sp) - addu $20,$6,$24 - addu $3,$3,$2 - addu $3,$3,$22 - nor $2,$0,$20 - addu $22,$3,$10 - and $2,$2,$25 - lw $3,4($5) - and $6,$20,$19 - or $6,$6,$2 - srl $8,$22,25 - addu $6,$6,$3 - srl $7,$18,22 - sll $3,$22,7 - sll $2,$18,10 - or $18,$2,$7 - or $3,$3,$8 - addu $22,$3,$17 - nor $7,$0,$18 - and $7,$7,$23 - and $3,$22,$18 - addu $6,$6,$24 - addu $24,$6,$11 - or $3,$3,$7 - lw $7,8($sp) - srl $6,$24,19 - sll $2,$24,13 - or $2,$2,$6 - addu $3,$3,$7 - addu $24,$2,$21 - srl $6,$19,22 - sll $2,$19,10 - addu $3,$3,$17 - or $19,$2,$6 - addu $17,$3,$10 - nor $2,$0,$24 - and $2,$2,$19 - and $3,$24,$20 - srl $8,$17,20 - sll $7,$17,12 - or $7,$7,$8 - or $3,$3,$2 - lw $8,40($5) - srl $6,$23,22 - sll $2,$23,10 - or $23,$2,$6 - addu $17,$7,$fp - addu $3,$3,$8 - nor $6,$0,$23 - and $6,$6,$22 - and $2,$17,$23 - addu $3,$3,$21 - addu $21,$3,$11 - or $2,$2,$6 - lw $6,52($sp) - srl $7,$21,21 - sll $3,$21,11 - or $3,$3,$7 - addu $2,$2,$6 - addu $21,$3,$25 - addu $2,$2,$fp - srl $6,$20,22 - sll $3,$20,10 - or $20,$3,$6 - addu $fp,$2,$10 - nor $7,$0,$21 - and $7,$7,$20 - srl $9,$fp,24 - and $6,$21,$24 - srl $8,$22,22 - sll $3,$fp,8 - sll $2,$22,10 - or $22,$2,$8 - or $3,$3,$9 - or $6,$6,$7 - addu $fp,$3,$18 - addu $6,$6,$12 - nor $3,$0,$22 - lw $8,12($sp) - and $3,$3,$17 - and $2,$fp,$22 - addu $6,$6,$25 - addu $25,$6,$11 - or $2,$2,$3 - srl $7,$25,23 - addu $2,$2,$8 - sll $3,$25,9 - or $3,$3,$7 - addu $2,$2,$18 - addu $25,$3,$19 - addu $18,$2,$10 - srl $3,$24,22 - sll $2,$24,10 - or $24,$2,$3 - srl $6,$17,22 - nor $3,$0,$25 - sll $2,$17,10 - or $17,$2,$6 - srl $8,$18,23 - and $3,$3,$24 - and $2,$25,$21 - sll $7,$18,9 - or $7,$7,$8 - or $2,$2,$3 - lw $3,60($5) - addu $18,$7,$23 - nor $6,$0,$17 - and $6,$6,$fp - addu $2,$2,$3 - and $3,$18,$17 - or $3,$3,$6 - lw $6,32($sp) - addu $2,$2,$19 - addu $19,$2,$11 - addu $3,$3,$6 - addu $3,$3,$23 - srl $6,$19,25 - sll $2,$19,7 - addu $23,$3,$10 - or $2,$2,$6 - addu $19,$2,$20 - srl $9,$23,21 - srl $8,$21,22 - srl $7,$fp,22 - sll $3,$23,11 - sll $6,$21,10 - sll $2,$fp,10 - or $fp,$2,$7 - or $21,$6,$8 - or $3,$3,$9 - nor $2,$0,$19 - addu $23,$3,$22 - and $2,$2,$21 - and $3,$19,$25 - nor $6,$0,$fp - lw $8,36($sp) - and $6,$6,$18 - or $3,$3,$2 - and $2,$23,$fp - or $2,$2,$6 - addu $3,$3,$16 - addu $3,$3,$20 - addu $2,$2,$8 - addu $20,$3,$11 - addu $2,$2,$22 - addu $22,$2,$10 - srl $3,$20,17 - sll $6,$20,15 - or $6,$6,$3 - srl $8,$22,25 - srl $7,$18,22 - sll $3,$22,7 - sll $2,$18,10 - or $18,$2,$7 - addu $20,$6,$24 - or $3,$3,$8 - srl $7,$25,22 - sll $2,$25,10 - or $25,$2,$7 - addu $22,$3,$17 - nor $6,$0,$20 - nor $7,$0,$18 - and $6,$6,$25 - and $7,$7,$23 - and $2,$20,$19 - and $3,$22,$18 - or $2,$2,$6 - or $3,$3,$7 - lw $6,48($5) - lw $7,48($sp) - addu $2,$2,$6 - addu $3,$3,$7 - addu $2,$2,$24 - addu $3,$3,$17 - addu $24,$2,$11 - addu $17,$3,$10 - srl $8,$24,25 - srl $9,$17,25 - srl $7,$23,22 - sll $3,$24,7 - sll $6,$17,7 - sll $2,$23,10 - or $23,$2,$7 - or $3,$3,$8 - or $6,$6,$9 - addu $24,$3,$21 - addu $17,$6,$fp - srl $3,$19,22 - nor $7,$0,$23 - sll $2,$19,10 - or $19,$2,$3 - and $7,$7,$22 - and $3,$17,$23 - nor $6,$0,$24 - lw $8,0($5) - and $6,$6,$19 - and $2,$24,$20 - or $3,$3,$7 - or $2,$2,$6 - addu $3,$3,$13 - addu $3,$3,$fp - addu $2,$2,$8 - addu $fp,$3,$10 - addu $2,$2,$21 - addu $21,$2,$11 - srl $7,$fp,20 - srl $6,$22,22 - sll $3,$fp,12 - sll $2,$22,10 - or $22,$2,$6 - or $3,$3,$7 - srl $6,$21,20 - sll $2,$21,12 - addu $fp,$3,$18 - or $2,$2,$6 - nor $6,$0,$22 - addu $21,$2,$25 - and $6,$6,$17 - and $2,$fp,$22 - srl $7,$20,22 - sll $3,$20,10 - or $2,$2,$6 - lw $6,24($sp) - or $20,$3,$7 - nor $3,$0,$21 - lw $7,36($5) - and $3,$3,$20 - addu $2,$2,$6 - and $6,$21,$24 - or $6,$6,$3 - addu $2,$2,$18 - addu $18,$2,$10 - addu $6,$6,$7 - srl $8,$18,25 - addu $6,$6,$25 - srl $7,$17,22 - sll $3,$18,7 - sll $2,$17,10 - or $17,$2,$7 - addu $25,$6,$11 - or $3,$3,$8 - addu $18,$3,$23 - srl $7,$25,17 - sll $6,$25,15 - nor $2,$0,$17 - or $6,$6,$7 - and $2,$2,$fp - and $3,$18,$17 - addu $25,$6,$19 - lw $8,4($sp) - or $3,$3,$2 - srl $7,$24,22 - sll $2,$24,10 - or $24,$2,$7 - nor $2,$0,$25 - and $2,$2,$24 - and $6,$25,$21 - addu $3,$3,$8 - addu $3,$3,$23 - or $6,$6,$2 - lw $2,20($5) - addu $23,$3,$10 - srl $8,$23,26 - addu $6,$6,$2 - srl $7,$fp,22 - sll $3,$23,6 - sll $2,$fp,10 - or $fp,$2,$7 - or $3,$3,$8 - addu $23,$3,$22 - addu $6,$6,$19 - nor $7,$0,$fp - addu $19,$6,$11 - and $7,$7,$18 - and $3,$23,$fp - srl $6,$19,23 - sll $2,$19,9 - or $3,$3,$7 - lw $7,16($sp) - or $2,$2,$6 - addu $19,$2,$20 - srl $6,$21,22 - addu $3,$3,$7 - sll $2,$21,10 - or $21,$2,$6 - addu $3,$3,$22 - nor $2,$0,$19 - addu $22,$3,$10 - and $2,$2,$21 - and $3,$19,$25 - srl $8,$22,17 - or $3,$3,$2 - srl $6,$18,22 - sll $7,$22,15 - sll $2,$18,10 - or $18,$2,$6 - or $7,$7,$8 - lw $8,0($sp) - addu $22,$7,$17 - nor $6,$0,$18 - and $6,$6,$23 - and $2,$22,$18 - addu $3,$3,$8 - addu $3,$3,$20 - or $2,$2,$6 - lw $6,40($sp) - addu $20,$3,$11 - srl $7,$20,21 - sll $3,$20,11 - addu $2,$2,$6 - or $3,$3,$7 - addu $2,$2,$17 - addu $20,$3,$24 - addu $17,$2,$10 - srl $6,$25,22 - sll $3,$25,10 - or $25,$3,$6 - srl $9,$17,19 - nor $7,$0,$20 - srl $8,$23,22 - sll $3,$17,13 - sll $2,$23,10 - or $23,$2,$8 - and $7,$7,$25 - and $6,$20,$19 - or $3,$3,$9 - addu $17,$3,$fp - or $6,$6,$7 - nor $3,$0,$23 - lw $7,56($5) - lw $8,28($sp) - and $3,$3,$22 - and $2,$17,$23 - addu $6,$6,$7 - or $2,$2,$3 - addu $6,$6,$24 - addu $2,$2,$8 - addu $24,$6,$11 - addu $2,$2,$fp - addu $fp,$2,$10 - srl $7,$24,25 - sll $3,$24,7 - srl $6,$19,22 - sll $2,$19,10 - or $19,$2,$6 - or $3,$3,$7 - sll $6,$fp,11 - srl $7,$fp,21 - addu $24,$3,$21 - or $6,$6,$7 - addu $fp,$6,$18 - nor $3,$0,$24 - srl $7,$22,22 - sll $6,$22,10 - or $22,$6,$7 - and $3,$3,$19 - lw $6,44($5) - and $2,$24,$20 - or $2,$2,$3 - nor $3,$0,$17 - lw $7,48($sp) - or $3,$3,$fp - addu $2,$2,$6 - addu $2,$2,$21 - xor $3,$3,$22 - addu $21,$2,$11 - addu $3,$3,$7 - li $10,1836056576 # 0x6d700000 - ori $10,$10,0x3ef3 - srl $6,$21,19 - addu $3,$3,$18 - sll $2,$21,13 - addu $18,$3,$10 - or $2,$2,$6 - addu $21,$2,$25 - srl $8,$18,23 - srl $6,$20,22 - sll $3,$18,9 - sll $2,$20,10 - or $20,$2,$6 - or $3,$3,$8 - nor $7,$0,$21 - addu $18,$3,$23 - and $8,$7,$20 - and $3,$21,$24 - srl $9,$17,22 - nor $2,$0,$fp - sll $6,$17,10 - or $17,$6,$9 - or $3,$3,$8 - lw $6,12($sp) - or $2,$2,$18 - xor $2,$2,$17 - addu $3,$3,$13 - addu $3,$3,$25 - addu $2,$2,$6 - addu $25,$3,$11 - addu $2,$2,$23 - addu $23,$2,$10 - srl $3,$25,20 - sll $2,$25,12 - or $2,$2,$3 - srl $6,$23,25 - sll $3,$23,7 - addu $25,$2,$19 - or $3,$3,$6 - sll $2,$24,10 - srl $6,$24,22 - addu $23,$3,$22 - or $24,$2,$6 - or $7,$7,$25 - srl $6,$fp,22 - nor $2,$0,$18 - sll $3,$fp,10 - or $fp,$3,$6 - xor $7,$7,$24 - lw $3,40($sp) - or $2,$2,$23 - xor $2,$2,$fp - addu $7,$7,$16 - li $9,1859715072 # 0x6ed90000 - ori $9,$9,0xeba1 - addu $7,$7,$19 - addu $2,$2,$3 - addu $19,$7,$9 - addu $2,$2,$22 - addu $22,$2,$10 - srl $3,$19,21 - sll $2,$19,11 - or $2,$2,$3 - srl $6,$22,17 - sll $3,$22,15 - addu $19,$2,$20 - or $3,$3,$6 - srl $7,$21,22 - sll $2,$21,10 - addu $22,$3,$17 - or $21,$2,$7 - nor $6,$0,$25 - srl $7,$18,22 - sll $3,$18,10 - or $18,$3,$7 - or $6,$6,$19 - lw $7,40($5) - nor $2,$0,$23 - xor $6,$6,$21 - or $2,$2,$22 - xor $2,$2,$18 - addu $6,$6,$7 - addu $6,$6,$20 - addu $2,$2,$16 - addu $20,$6,$9 - addu $2,$2,$17 - addu $17,$2,$10 - srl $3,$20,19 - sll $2,$20,13 - or $2,$2,$3 - srl $6,$17,21 - sll $3,$17,11 - addu $20,$2,$24 - or $3,$3,$6 - srl $7,$25,22 - nor $6,$0,$19 - sll $2,$25,10 - addu $17,$3,$fp - or $25,$2,$7 - lw $8,56($5) - or $6,$6,$20 - srl $7,$23,22 - nor $2,$0,$22 - sll $3,$23,10 - or $23,$3,$7 - xor $6,$6,$25 - lw $3,20($sp) - or $2,$2,$17 - xor $2,$2,$23 - addu $6,$6,$8 - addu $6,$6,$24 - addu $2,$2,$3 - addu $24,$6,$9 - addu $2,$2,$fp - addu $fp,$2,$10 - srl $3,$24,26 - sll $2,$24,6 - or $2,$2,$3 - srl $6,$fp,24 - sll $3,$fp,8 - addu $24,$2,$21 - or $3,$3,$6 - srl $7,$19,22 - sll $2,$19,10 - addu $fp,$3,$18 - or $19,$2,$7 - nor $6,$0,$20 - srl $7,$22,22 - sll $3,$22,10 - or $22,$3,$7 - or $6,$6,$24 - lw $7,16($5) - nor $2,$0,$17 - xor $6,$6,$19 - or $2,$2,$fp - xor $2,$2,$22 - addu $6,$6,$7 - addu $6,$6,$21 - addu $2,$2,$8 - addu $21,$6,$9 - addu $2,$2,$18 - addu $18,$2,$10 - srl $3,$21,25 - sll $2,$21,7 - or $2,$2,$3 - srl $6,$18,26 - sll $3,$18,6 - addu $21,$2,$25 - or $3,$3,$6 - srl $7,$20,22 - sll $2,$20,10 - addu $18,$3,$23 - or $20,$2,$7 - nor $6,$0,$24 - srl $7,$17,22 - sll $3,$17,10 - or $17,$3,$7 - or $6,$6,$21 - lw $3,36($5) - nor $2,$0,$fp - xor $6,$6,$20 - or $2,$2,$18 - xor $2,$2,$17 - addu $6,$6,$3 - addu $6,$6,$25 - addu $2,$2,$12 - addu $25,$6,$9 - addu $2,$2,$23 - addu $23,$2,$10 - srl $3,$25,18 - sll $2,$25,14 - or $2,$2,$3 - srl $6,$23,26 - sll $3,$23,6 - addu $25,$2,$19 - or $3,$3,$6 - srl $7,$24,22 - sll $2,$24,10 - addu $23,$3,$22 - or $24,$2,$7 - nor $6,$0,$21 - srl $7,$fp,22 - sll $3,$fp,10 - or $fp,$3,$7 - or $6,$6,$25 - lw $7,60($5) - nor $2,$0,$18 - lw $8,16($sp) - xor $6,$6,$24 - or $2,$2,$23 - xor $2,$2,$fp - addu $6,$6,$7 - addu $6,$6,$19 - addu $2,$2,$8 - addu $19,$6,$9 - addu $2,$2,$22 - addu $22,$2,$10 - srl $3,$19,23 - sll $2,$19,9 - or $2,$2,$3 - srl $6,$22,18 - sll $3,$22,14 - addu $19,$2,$20 - or $3,$3,$6 - srl $7,$21,22 - nor $6,$0,$25 - sll $2,$21,10 - addu $22,$3,$17 - or $21,$2,$7 - or $6,$6,$19 - srl $7,$18,22 - nor $2,$0,$23 - sll $3,$18,10 - or $18,$3,$7 - xor $6,$6,$21 - lw $7,44($sp) - or $2,$2,$22 - xor $2,$2,$18 - addu $6,$6,$13 - addu $6,$6,$20 - addu $2,$2,$7 - addu $20,$6,$9 - addu $2,$2,$17 - addu $17,$2,$10 - srl $3,$20,19 - sll $2,$20,13 - or $2,$2,$3 - srl $6,$17,20 - sll $3,$17,12 - addu $20,$2,$24 - or $3,$3,$6 - srl $7,$25,22 - nor $6,$0,$19 - sll $2,$25,10 - addu $17,$3,$fp - or $25,$2,$7 - lw $8,4($5) - or $6,$6,$20 - srl $7,$23,22 - nor $2,$0,$22 - sll $3,$23,10 - or $23,$3,$7 - xor $6,$6,$25 - or $2,$2,$17 - xor $2,$2,$23 - addu $6,$6,$8 - addu $6,$6,$24 - addu $2,$2,$13 - addu $24,$6,$9 - addu $2,$2,$fp - addu $fp,$2,$10 - srl $3,$24,17 - sll $2,$24,15 - or $2,$2,$3 - srl $6,$fp,19 - sll $3,$fp,13 - addu $24,$2,$21 - or $3,$3,$6 - srl $7,$19,22 - sll $2,$19,10 - addu $fp,$3,$18 - or $19,$2,$7 - nor $6,$0,$20 - srl $7,$22,22 - sll $3,$22,10 - or $22,$3,$7 - or $6,$6,$24 - lw $3,0($sp) - nor $2,$0,$17 - lw $7,24($sp) - xor $6,$6,$19 - or $2,$2,$fp - xor $2,$2,$22 - addu $6,$6,$3 - addu $6,$6,$21 - addu $2,$2,$7 - addu $21,$6,$9 - addu $2,$2,$18 - addu $18,$2,$10 - srl $3,$21,18 - sll $2,$21,14 - or $2,$2,$3 - srl $6,$18,27 - sll $3,$18,5 - addu $21,$2,$25 - or $3,$3,$6 - srl $7,$20,22 - nor $6,$0,$24 - sll $2,$20,10 - addu $18,$3,$23 - or $20,$2,$7 - lw $8,28($5) - or $6,$6,$21 - srl $7,$17,22 - nor $2,$0,$fp - sll $3,$17,10 - or $17,$3,$7 - xor $6,$6,$20 - lw $3,28($sp) - or $2,$2,$18 - xor $2,$2,$17 - addu $6,$6,$8 - addu $6,$6,$25 - addu $2,$2,$3 - addu $25,$6,$9 - addu $2,$2,$23 - addu $23,$2,$10 - srl $3,$25,24 - sll $2,$25,8 - or $2,$2,$3 - srl $6,$23,18 - sll $3,$23,14 - addu $25,$2,$19 - or $3,$3,$6 - srl $7,$24,22 - sll $2,$24,10 - addu $23,$3,$22 - or $24,$2,$7 - nor $6,$0,$21 - srl $7,$fp,22 - sll $3,$fp,10 - or $fp,$3,$7 - or $6,$6,$25 - lw $7,0($5) - nor $2,$0,$18 - lw $8,32($sp) - xor $6,$6,$24 - or $2,$2,$23 - xor $2,$2,$fp - addu $6,$6,$7 - addu $6,$6,$19 - addu $2,$2,$8 - addu $19,$6,$9 - addu $2,$2,$22 - addu $22,$2,$10 - srl $3,$19,19 - sll $2,$19,13 - or $2,$2,$3 - srl $6,$22,19 - sll $3,$22,13 - addu $19,$2,$20 - or $3,$3,$6 - srl $7,$21,22 - nor $6,$0,$25 - sll $2,$21,10 - addu $22,$3,$17 - or $21,$2,$7 - or $6,$6,$19 - srl $7,$18,22 - nor $2,$0,$23 - sll $3,$18,10 - or $18,$3,$7 - xor $6,$6,$21 - lw $7,8($sp) - or $2,$2,$22 - xor $2,$2,$18 - addu $6,$6,$12 - addu $6,$6,$20 - addu $2,$2,$7 - addu $20,$6,$9 - addu $2,$2,$17 - addu $17,$2,$10 - srl $3,$20,26 - sll $2,$20,6 - or $2,$2,$3 - srl $6,$17,19 - sll $3,$17,13 - addu $20,$2,$24 - lw $8,16($5) - or $3,$3,$6 - srl $7,$25,22 - sll $2,$25,10 - addu $17,$3,$fp - or $25,$2,$7 - nor $6,$0,$19 - srl $7,$23,22 - sll $3,$23,10 - sw $8,56($sp) - or $23,$3,$7 - or $6,$6,$20 - lw $3,52($5) - nor $2,$0,$22 - xor $6,$6,$25 - or $2,$2,$17 - xor $2,$2,$23 - addu $6,$6,$3 - addu $6,$6,$24 - addu $2,$2,$8 - addu $24,$6,$9 - addu $2,$2,$fp - addu $fp,$2,$10 - srl $3,$24,27 - sll $2,$24,5 - or $2,$2,$3 - srl $6,$fp,25 - sll $3,$fp,7 - addu $24,$2,$21 - or $3,$3,$6 - srl $7,$19,22 - sll $2,$19,10 - addu $fp,$3,$18 - or $19,$2,$7 - nor $6,$0,$20 - srl $7,$22,22 - nor $2,$0,$17 - sll $3,$22,10 - or $22,$3,$7 - lw $8,52($sp) - lw $7,44($5) - or $6,$6,$24 - or $2,$2,$fp - xor $6,$6,$19 - xor $2,$2,$22 - addu $6,$6,$7 - addu $2,$2,$8 - addu $6,$6,$21 - addu $2,$2,$18 - addu $21,$6,$9 - addu $18,$2,$10 - srl $3,$21,20 - srl $7,$18,27 - sll $2,$21,12 - sll $6,$18,5 - or $2,$2,$3 - or $6,$6,$7 - sll $3,$20,10 - srl $7,$20,22 - addu $18,$6,$23 - addu $21,$2,$25 - or $20,$3,$7 - nor $2,$0,$24 - srl $6,$17,22 - sll $3,$17,10 - or $17,$3,$6 - or $2,$2,$21 - lw $3,20($5) - xor $2,$2,$20 - nor $6,$0,$18 - and $6,$6,$17 - addu $2,$2,$3 - and $3,$18,$fp - or $3,$3,$6 - addu $2,$2,$25 - addu $3,$3,$13 - li $11,2053963776 # 0x7a6d0000 - ori $11,$11,0x76e9 - addu $25,$2,$9 - addu $3,$3,$23 - addu $23,$3,$11 - srl $6,$25,25 - sll $2,$25,7 - or $2,$2,$6 - srl $8,$23,17 - sll $6,$23,15 - addu $25,$2,$19 - or $6,$6,$8 - srl $7,$24,22 - sll $2,$24,10 - addu $23,$6,$22 - or $24,$2,$7 - nor $3,$0,$21 - srl $6,$fp,22 - sll $2,$fp,10 - or $fp,$2,$6 - or $3,$3,$25 - lw $6,48($5) - xor $3,$3,$24 - addu $3,$3,$6 - nor $6,$0,$23 - and $6,$6,$fp - and $2,$23,$18 - addu $3,$3,$19 - or $2,$2,$6 - addu $19,$3,$9 - addu $2,$2,$12 - srl $8,$19,27 - srl $7,$21,22 - sll $6,$19,5 - sll $3,$21,10 - addu $2,$2,$22 - or $21,$3,$7 - or $6,$6,$8 - addu $22,$2,$11 - addu $19,$6,$20 - srl $7,$22,27 - nor $6,$0,$21 - sll $2,$22,5 - and $6,$6,$25 - and $3,$19,$21 - or $2,$2,$7 - lw $7,4($5) - or $3,$3,$6 - addu $22,$2,$17 - addu $3,$3,$7 - srl $6,$18,22 - sll $2,$18,10 - li $10,-1894055936 # 0xffffffff8f1b0000 - ori $10,$10,0xbcdc - or $18,$2,$6 - addu $3,$3,$20 - nor $2,$0,$22 - addu $20,$3,$10 - and $2,$2,$18 - and $3,$22,$23 - srl $8,$20,21 - or $3,$3,$2 - srl $6,$25,22 - sll $7,$20,11 - sll $2,$25,10 - or $25,$2,$6 - or $7,$7,$8 - lw $8,56($sp) - addu $20,$7,$24 - nor $6,$0,$25 - and $6,$6,$19 - and $2,$20,$25 - addu $3,$3,$8 - addu $3,$3,$17 - or $2,$2,$6 - lw $6,36($5) - addu $17,$3,$11 - srl $7,$17,24 - sll $3,$17,8 - addu $2,$2,$6 - or $3,$3,$7 - addu $2,$2,$24 - addu $17,$3,$fp - addu $24,$2,$10 - srl $6,$23,22 - lw $2,4($5) - sll $3,$23,10 - or $23,$3,$6 - srl $9,$24,20 - sll $3,$24,12 - sw $2,60($sp) - or $3,$3,$9 - nor $7,$0,$17 - addu $24,$3,$21 - and $7,$7,$23 - lw $3,60($sp) - and $6,$17,$22 - srl $8,$19,22 - sll $2,$19,10 - or $6,$6,$7 - or $19,$2,$8 - addu $6,$6,$3 - addu $6,$6,$fp - nor $3,$0,$19 - addu $fp,$6,$11 - and $3,$3,$20 - lw $6,44($5) - and $2,$24,$19 - or $2,$2,$3 - addu $2,$2,$6 - sll $3,$fp,11 - srl $6,$fp,21 - or $3,$3,$6 - addu $2,$2,$21 - addu $fp,$3,$18 - addu $21,$2,$10 - srl $3,$22,22 - sll $2,$22,10 - or $22,$2,$3 - srl $8,$21,18 - srl $6,$20,22 - sll $7,$21,14 - nor $3,$0,$fp - sll $2,$20,10 - or $20,$2,$6 - or $7,$7,$8 - and $3,$3,$22 - and $2,$fp,$17 - addu $21,$7,$25 - or $2,$2,$3 - nor $6,$0,$20 - lw $7,40($5) - and $6,$6,$24 - and $3,$21,$20 - addu $2,$2,$16 - or $3,$3,$6 - addu $2,$2,$18 - addu $18,$2,$11 - addu $3,$3,$7 - srl $6,$18,18 - addu $3,$3,$25 - sll $2,$18,14 - addu $25,$3,$10 - or $2,$2,$6 - addu $18,$2,$23 - srl $9,$25,17 - srl $7,$24,22 - srl $8,$17,22 - sll $3,$25,15 - sll $2,$24,10 - sll $6,$17,10 - or $24,$2,$7 - or $17,$6,$8 - or $3,$3,$9 - nor $2,$0,$18 - addu $25,$3,$19 - and $2,$2,$17 - and $3,$18,$fp - nor $6,$0,$24 - lw $8,44($sp) - and $6,$6,$21 - or $3,$3,$2 - and $2,$25,$24 - or $2,$2,$6 - lw $6,0($5) - addu $3,$3,$8 - addu $3,$3,$23 - addu $2,$2,$6 - addu $23,$3,$11 - addu $2,$2,$19 - addu $19,$2,$10 - srl $3,$23,18 - sll $6,$23,14 - or $6,$6,$3 - srl $8,$19,18 - srl $7,$21,22 - sll $3,$19,14 - sll $2,$21,10 - addu $23,$6,$22 - or $21,$2,$7 - or $3,$3,$8 - srl $7,$fp,22 - sll $2,$fp,10 - addu $19,$3,$20 - or $fp,$2,$7 - nor $6,$0,$21 - nor $7,$0,$23 - lw $8,48($sp) - and $6,$6,$25 - and $7,$7,$fp - and $2,$19,$21 - and $3,$23,$18 - or $2,$2,$6 - or $3,$3,$7 - addu $3,$3,$8 - addu $2,$2,$13 - addu $2,$2,$20 - addu $3,$3,$22 - addu $20,$2,$10 - addu $22,$3,$11 - srl $8,$20,17 - srl $9,$22,26 - srl $7,$25,22 - sll $6,$20,15 - sll $3,$22,6 - sll $2,$25,10 - or $25,$2,$7 - or $6,$6,$8 - or $3,$3,$9 - addu $22,$3,$17 - addu $20,$6,$24 - srl $3,$18,22 - nor $7,$0,$25 - sll $2,$18,10 - or $18,$2,$3 - lw $8,48($5) - and $7,$7,$19 - and $3,$20,$25 - nor $6,$0,$22 - and $6,$6,$18 - and $2,$22,$23 - or $3,$3,$7 - lw $7,0($5) - or $2,$2,$6 - addu $3,$3,$8 - addu $3,$3,$24 - addu $2,$2,$7 - addu $24,$3,$10 - addu $2,$2,$17 - addu $17,$2,$11 - sw $7,64($sp) - srl $6,$19,22 - srl $7,$24,23 - sll $3,$24,9 - sll $2,$19,10 - or $19,$2,$6 - or $3,$3,$7 - srl $6,$17,18 - sll $2,$17,14 - addu $24,$3,$21 - or $2,$2,$6 - nor $7,$0,$19 - srl $6,$23,22 - sll $3,$23,10 - addu $17,$2,$fp - or $23,$3,$6 - and $7,$7,$20 - lw $3,16($5) - and $2,$24,$19 - or $2,$2,$7 - nor $6,$0,$17 - lw $15,20($5) - and $6,$6,$23 - addu $2,$2,$3 - and $3,$17,$22 - addu $2,$2,$21 - or $3,$3,$6 - addu $21,$2,$10 - addu $3,$3,$15 - srl $8,$21,24 - addu $3,$3,$fp - srl $7,$20,22 - sll $6,$21,8 - sll $2,$20,10 - or $20,$2,$7 - or $6,$6,$8 - addu $fp,$3,$11 - addu $21,$6,$25 - srl $3,$fp,26 - nor $2,$0,$20 - sll $6,$fp,6 - or $6,$6,$3 - and $2,$2,$24 - and $3,$21,$20 - or $3,$3,$2 - srl $7,$22,22 - sll $2,$22,10 - addu $fp,$6,$18 - or $22,$2,$7 - lw $6,52($5) - lw $7,48($5) - nor $2,$0,$fp - sw $7,68($sp) - and $2,$2,$22 - addu $3,$3,$6 - and $6,$fp,$17 - addu $3,$3,$25 - or $6,$6,$2 - lw $2,68($sp) - addu $25,$3,$10 - srl $8,$25,23 - srl $7,$24,22 - addu $6,$6,$2 - sll $3,$25,9 - sll $2,$24,10 - or $24,$2,$7 - or $3,$3,$8 - addu $6,$6,$18 - addu $25,$3,$19 - addu $18,$6,$11 - nor $7,$0,$24 - and $7,$7,$21 - srl $6,$18,23 - and $2,$25,$24 - sll $3,$18,9 - or $3,$3,$6 - or $2,$2,$7 - addu $18,$3,$23 - addu $2,$2,$16 - srl $6,$17,22 - sll $3,$17,10 - or $17,$3,$6 - addu $2,$2,$19 - nor $3,$0,$18 - addu $19,$2,$10 - and $3,$3,$17 - and $6,$18,$fp - lw $14,8($5) - srl $8,$19,18 - or $6,$6,$3 - sll $7,$19,14 - srl $3,$21,22 - sll $2,$21,10 - or $21,$2,$3 - or $7,$7,$8 - addu $19,$7,$20 - nor $3,$0,$21 - addu $6,$6,$14 - lw $7,28($5) - and $3,$3,$25 - and $2,$19,$21 - addu $6,$6,$23 - addu $23,$6,$11 - or $2,$2,$3 - srl $6,$23,20 - sll $3,$23,12 - addu $2,$2,$7 - or $3,$3,$6 - addu $2,$2,$20 - addu $23,$3,$22 - addu $20,$2,$10 - srl $6,$fp,22 - sll $3,$fp,10 - or $fp,$3,$6 - srl $9,$20,27 - nor $7,$0,$23 - srl $8,$25,22 - sll $3,$20,5 - sll $2,$25,10 - or $25,$2,$8 - and $7,$7,$fp - lw $8,52($sp) - and $6,$23,$18 - or $3,$3,$9 - addu $20,$3,$24 - or $6,$6,$7 - nor $3,$0,$25 - and $3,$3,$19 - and $2,$20,$25 - addu $6,$6,$8 - addu $6,$6,$22 - or $2,$2,$3 - lw $3,60($5) - addu $22,$6,$11 - srl $6,$22,23 - addu $2,$2,$3 - sll $3,$22,9 - or $3,$3,$6 - addu $2,$2,$24 - addu $22,$3,$17 - addu $24,$2,$10 - srl $3,$18,22 - sll $2,$18,10 - or $18,$2,$3 - srl $8,$24,26 - srl $3,$19,22 - sll $7,$24,6 - nor $6,$0,$22 - sll $2,$19,10 - or $19,$2,$3 - or $7,$7,$8 - and $6,$6,$18 - lw $8,36($5) - and $3,$22,$23 - or $3,$3,$6 - addu $3,$3,$8 - addu $24,$7,$21 - nor $6,$0,$19 - addu $3,$3,$17 - addu $17,$3,$11 - and $6,$6,$20 - lw $3,56($5) - and $2,$24,$19 - or $2,$2,$6 - addu $2,$2,$3 - srl $6,$17,20 - addu $2,$2,$21 - sll $3,$17,12 - addu $21,$2,$10 - sw $8,72($sp) - or $3,$3,$6 - srl $8,$23,22 - sll $6,$23,10 - addu $17,$3,$fp - or $23,$6,$8 - srl $9,$21,24 - lw $6,28($5) - srl $7,$20,22 - sll $3,$21,8 - sll $2,$20,10 - or $20,$2,$7 - or $3,$3,$9 - nor $2,$0,$17 - sw $6,76($sp) - addu $21,$3,$25 - lw $7,76($sp) - and $2,$2,$23 - and $3,$17,$22 - nor $6,$0,$20 - and $6,$6,$24 - or $3,$3,$2 - and $2,$21,$20 - or $2,$2,$6 - addu $3,$3,$7 - addu $3,$3,$fp - addu $2,$2,$15 - addu $fp,$3,$11 - addu $2,$2,$25 - addu $25,$2,$10 - srl $3,$fp,27 - sll $6,$fp,5 - or $6,$6,$3 - srl $8,$25,26 - srl $7,$24,22 - sll $3,$25,6 - sll $2,$24,10 - addu $fp,$6,$18 - or $24,$2,$7 - or $3,$3,$8 - srl $7,$22,22 - sll $2,$22,10 - addu $25,$3,$19 - or $22,$2,$7 - nor $6,$0,$24 - nor $7,$0,$fp - lw $8,40($5) - and $6,$6,$21 - and $7,$7,$22 - and $2,$25,$24 - and $3,$fp,$17 - or $2,$2,$6 - or $3,$3,$7 - addu $3,$3,$8 - addu $2,$2,$12 - addu $2,$2,$19 - addu $3,$3,$18 - addu $19,$2,$10 - addu $18,$3,$11 - sw $8,80($sp) - srl $9,$18,17 - srl $8,$19,27 - srl $7,$21,22 - sll $6,$19,5 - sll $3,$18,15 - sll $2,$21,10 - or $21,$2,$7 - or $6,$6,$8 - or $3,$3,$9 - addu $18,$3,$23 - addu $19,$6,$20 - srl $7,$17,22 - nor $3,$0,$21 - sll $2,$17,10 - or $17,$2,$7 - and $3,$3,$25 - and $2,$19,$21 - nor $6,$0,$18 - lw $7,56($5) - and $6,$6,$17 - or $2,$2,$3 - and $3,$18,$fp - or $3,$3,$6 - addu $2,$2,$14 - addu $2,$2,$20 - addu $3,$3,$7 - addu $20,$2,$10 - addu $3,$3,$23 - srl $5,$25,22 - sll $2,$25,10 - or $25,$2,$5 - addu $23,$3,$11 - srl $2,$20,20 - sll $5,$20,12 - or $5,$5,$2 - srl $6,$23,24 - sll $2,$23,8 - or $2,$2,$6 - addu $20,$5,$24 - addu $23,$2,$22 - nor $3,$0,$25 - srl $5,$fp,22 - sll $2,$fp,10 - or $fp,$2,$5 - or $3,$3,$19 - lw $2,4($sp) - lw $6,68($sp) - xor $5,$23,$18 - xor $3,$3,$20 - addu $3,$3,$2 - xor $5,$5,$fp - li $8,-1454178304 # 0xffffffffa9530000 - ori $8,$8,0xfd4e - addu $5,$5,$6 - addu $3,$3,$24 - addu $24,$3,$8 - addu $22,$22,$5 - srl $6,$19,22 - sll $2,$19,10 - or $19,$2,$6 - sll $5,$24,9 - srl $2,$24,23 - srl $6,$22,24 - sll $3,$22,8 - or $5,$5,$2 - or $3,$3,$6 - addu $24,$5,$21 - addu $22,$3,$17 - nor $2,$0,$19 - srl $5,$18,22 - sll $3,$18,10 - or $18,$3,$5 - or $2,$2,$20 - lw $3,8($sp) - xor $2,$2,$24 - lw $5,48($sp) - addu $2,$2,$3 - xor $3,$22,$23 - xor $3,$3,$18 - addu $3,$3,$5 - addu $2,$2,$21 - addu $21,$2,$8 - addu $17,$17,$3 - srl $5,$20,22 - sll $2,$20,10 - or $20,$2,$5 - srl $6,$17,27 - srl $2,$21,17 - sll $5,$21,15 - sll $3,$17,5 - or $5,$5,$2 - or $3,$3,$6 - nor $2,$0,$20 - addu $21,$5,$25 - addu $17,$3,$fp - or $2,$2,$24 - srl $5,$23,22 - sll $3,$23,10 - or $23,$3,$5 - xor $2,$2,$21 - lw $5,80($sp) - xor $3,$17,$22 - xor $3,$3,$23 - addu $2,$2,$15 - addu $3,$3,$5 - addu $2,$2,$25 - addu $25,$2,$8 - addu $fp,$fp,$3 - srl $5,$24,22 - sll $2,$24,10 - or $24,$2,$5 - srl $6,$fp,20 - srl $2,$25,27 - sll $5,$25,5 - sll $3,$fp,12 - or $5,$5,$2 - or $3,$3,$6 - nor $2,$0,$24 - addu $25,$5,$19 - addu $fp,$3,$18 - lw $6,16($sp) - or $2,$2,$21 - srl $5,$22,22 - sll $3,$22,10 - or $22,$3,$5 - xor $2,$2,$25 - lw $5,56($sp) - xor $3,$fp,$17 - addu $2,$2,$6 - xor $3,$3,$22 - addu $3,$3,$5 - addu $2,$2,$19 - addu $19,$2,$8 - addu $18,$18,$3 - srl $5,$21,22 - sll $2,$21,10 - or $21,$2,$5 - srl $6,$18,23 - srl $2,$19,21 - sll $5,$19,11 - sll $3,$18,9 - or $5,$5,$2 - or $3,$3,$6 - nor $2,$0,$21 - addu $19,$5,$20 - addu $18,$3,$23 - lw $6,20($sp) - or $2,$2,$25 - srl $5,$17,22 - sll $3,$17,10 - or $17,$3,$5 - xor $2,$2,$19 - lw $5,60($sp) - xor $3,$18,$fp - addu $2,$2,$6 - xor $3,$3,$17 - addu $3,$3,$5 - addu $2,$2,$20 - addu $20,$2,$8 - addu $23,$23,$3 - srl $5,$25,22 - sll $2,$25,10 - or $25,$2,$5 - srl $6,$23,20 - srl $2,$20,26 - sll $5,$20,6 - sll $3,$23,12 - or $5,$5,$2 - or $3,$3,$6 - nor $2,$0,$25 - addu $20,$5,$24 - addu $23,$3,$22 - lw $6,24($sp) - or $2,$2,$19 - srl $5,$fp,22 - sll $3,$fp,10 - or $fp,$3,$5 - xor $2,$2,$20 - xor $3,$23,$18 - addu $2,$2,$6 - xor $3,$3,$fp - addu $2,$2,$24 - addu $3,$3,$15 - addu $24,$2,$8 - addu $22,$22,$3 - srl $5,$19,22 - sll $2,$19,10 - or $19,$2,$5 - srl $6,$22,27 - srl $2,$24,24 - sll $5,$24,8 - sll $3,$22,5 - or $5,$5,$2 - or $3,$3,$6 - nor $2,$0,$19 - addu $24,$5,$21 - addu $22,$3,$17 - or $2,$2,$20 - srl $5,$18,22 - sll $3,$18,10 - or $18,$3,$5 - xor $2,$2,$24 - xor $3,$22,$23 - xor $3,$3,$18 - addu $2,$2,$14 - addu $2,$2,$21 - addu $3,$3,$13 - addu $21,$2,$8 - addu $17,$17,$3 - srl $5,$20,22 - sll $2,$20,10 - or $20,$2,$5 - srl $6,$17,18 - srl $2,$21,19 - sll $5,$21,13 - sll $3,$17,14 - or $5,$5,$2 - or $3,$3,$6 - addu $21,$5,$25 - addu $17,$3,$fp - nor $2,$0,$20 - srl $5,$23,22 - sll $3,$23,10 - or $23,$3,$5 - or $2,$2,$24 - lw $5,32($sp) - lw $6,76($sp) - xor $3,$17,$22 - xor $2,$2,$21 - addu $2,$2,$5 - xor $3,$3,$23 - addu $3,$3,$6 - addu $2,$2,$25 - addu $25,$2,$8 - addu $fp,$fp,$3 - srl $5,$24,22 - sll $2,$24,10 - or $24,$2,$5 - srl $6,$fp,26 - srl $2,$25,20 - sll $5,$25,12 - sll $3,$fp,6 - or $5,$5,$2 - or $3,$3,$6 - nor $2,$0,$24 - addu $25,$5,$19 - addu $fp,$3,$18 - or $2,$2,$21 - srl $5,$22,22 - sll $3,$22,10 - or $22,$3,$5 - xor $2,$2,$25 - xor $3,$fp,$17 - addu $2,$2,$7 - xor $3,$3,$22 - addu $2,$2,$19 - addu $3,$3,$12 - addu $19,$2,$8 - addu $18,$18,$3 - srl $5,$21,22 - sll $2,$21,10 - or $21,$2,$5 - srl $6,$18,24 - srl $2,$19,27 - sll $5,$19,5 - sll $3,$18,8 - or $5,$5,$2 - or $3,$3,$6 - addu $19,$5,$20 - addu $18,$3,$23 - nor $2,$0,$21 - srl $5,$17,22 - sll $3,$17,10 - or $17,$3,$5 - or $2,$2,$25 - lw $5,40($sp) - xor $3,$18,$fp - xor $2,$2,$19 - addu $2,$2,$5 - xor $3,$3,$17 - addu $2,$2,$20 - addu $3,$3,$14 - addu $20,$2,$8 - addu $23,$23,$3 - srl $5,$25,22 - sll $2,$25,10 - or $25,$2,$5 - srl $6,$23,19 - srl $2,$20,20 - sll $5,$20,12 - sll $3,$23,13 - or $5,$5,$2 - or $3,$3,$6 - nor $2,$0,$25 - addu $20,$5,$24 - addu $23,$3,$22 - or $2,$2,$19 - srl $5,$fp,22 - sll $3,$fp,10 - or $fp,$3,$5 - lw $6,52($sp) - xor $3,$23,$18 - xor $2,$2,$20 - addu $2,$2,$16 - xor $3,$3,$fp - addu $3,$3,$6 - addu $2,$2,$24 - addu $24,$2,$8 - addu $22,$22,$3 - srl $5,$19,22 - sll $2,$19,10 - or $19,$2,$5 - srl $6,$22,26 - srl $2,$24,19 - sll $5,$24,13 - sll $3,$22,6 - or $5,$5,$2 - or $3,$3,$6 - nor $2,$0,$19 - addu $24,$5,$21 - addu $22,$3,$17 - or $2,$2,$20 - srl $5,$18,22 - sll $3,$18,10 - or $18,$3,$5 - xor $2,$2,$24 - xor $3,$22,$23 - xor $3,$3,$18 - addu $2,$2,$13 - addu $3,$3,$7 - addu $2,$2,$21 - addu $21,$2,$8 - addu $17,$17,$3 - srl $5,$20,22 - sll $2,$20,10 - or $20,$2,$5 - srl $6,$17,27 - srl $2,$21,18 - sll $5,$21,14 - sll $3,$17,5 - or $5,$5,$2 - or $3,$3,$6 - nor $2,$0,$20 - addu $21,$5,$25 - addu $17,$3,$fp - lw $7,44($sp) - or $2,$2,$24 - srl $5,$23,22 - sll $3,$23,10 - or $23,$3,$5 - xor $2,$2,$21 - lw $5,64($sp) - xor $3,$17,$22 - addu $2,$2,$7 - xor $3,$3,$23 - addu $3,$3,$5 - addu $2,$2,$25 - addu $25,$2,$8 - addu $fp,$fp,$3 - srl $5,$24,22 - sll $2,$24,10 - or $24,$2,$5 - srl $6,$fp,17 - srl $2,$25,21 - sll $5,$25,11 - sll $3,$fp,15 - or $5,$5,$2 - or $3,$3,$6 - nor $2,$0,$24 - addu $25,$5,$19 - addu $fp,$3,$18 - or $2,$2,$21 - srl $5,$22,22 - sll $3,$22,10 - or $22,$3,$5 - xor $2,$2,$25 - xor $3,$fp,$17 - xor $3,$3,$22 - addu $2,$2,$12 - addu $3,$3,$16 - addu $2,$2,$19 - addu $19,$2,$8 - addu $18,$18,$3 - srl $5,$21,22 - sll $2,$21,10 - or $21,$2,$5 - srl $6,$18,19 - srl $2,$19,24 - sll $5,$19,8 - sll $3,$18,13 - or $5,$5,$2 - or $3,$3,$6 - nor $2,$0,$21 - addu $19,$5,$20 - addu $18,$3,$23 - lw $6,48($sp) - or $2,$2,$25 - srl $5,$17,22 - sll $3,$17,10 - or $17,$3,$5 - lw $7,72($sp) - xor $3,$18,$fp - xor $2,$2,$19 - addu $2,$2,$6 - xor $3,$3,$17 - addu $3,$3,$7 - addu $2,$2,$20 - addu $20,$2,$8 - addu $23,$23,$3 - srl $5,$25,22 - sll $2,$25,10 - or $25,$2,$5 - srl $3,$20,27 - srl $6,$23,21 - sll $5,$20,5 - sll $2,$23,11 - or $5,$5,$3 - or $2,$2,$6 - addu $20,$5,$24 - addu $23,$2,$22 - srl $5,$fp,22 - sll $2,$fp,10 - nor $3,$0,$25 - or $fp,$2,$5 - or $3,$3,$19 - lw $2,52($sp) - xor $3,$3,$20 - addu $3,$3,$2 - addu $3,$3,$24 - addu $24,$3,$8 - xor $2,$23,$18 - lw $3,44($sp) - lw $6,8($4) - srl $7,$19,22 - sll $5,$19,10 - or $19,$5,$7 - xor $2,$2,$fp - addu $2,$2,$3 - addu $6,$6,$19 - addu $22,$22,$2 - addu $6,$6,$fp - srl $2,$24,26 - sll $5,$24,6 - srl $3,$22,21 - lw $10,4($4) - lw $7,12($4) - lw $8,0($4) - or $5,$5,$2 - sll $9,$22,11 - sw $6,4($4) - lw $6,16($4) - or $9,$9,$3 - addu $24,$5,$21 - srl $3,$18,22 - sll $2,$18,10 - addu $22,$9,$17 - addu $10,$10,$20 - addu $6,$6,$21 - or $18,$2,$3 - addu $7,$7,$25 - addu $8,$8,$24 - addu $18,$18,$10 - addu $7,$7,$17 - addu $6,$6,$22 - addu $8,$8,$23 - sw $18,0($4) - sw $7,8($4) - sw $6,12($4) - sw $8,16($4) - lw $fp,120($sp) - lw $23,116($sp) - lw $22,112($sp) - lw $21,108($sp) - lw $20,104($sp) - lw $19,100($sp) - lw $18,96($sp) - lw $17,92($sp) - lw $16,88($sp) - .set noreorder - .set nomacro - j $31 - addiu $sp,$sp,128 - .set macro - .set reorder - - .end compress - .align 2 - .globl MDfinish - .ent MDfinish -MDfinish: - .frame $sp,104,$31 # vars= 64, regs= 6/0, args= 16, gp= 0 - .mask 0x801f0000,-4 - .fmask 0x00000000,0 - addiu $sp,$sp,-104 - sw $17,84($sp) - addiu $17,$sp,16 - sw $20,96($sp) - sw $18,88($sp) - sw $16,80($sp) - move $18,$6 - move $20,$4 - li $6,64 # 0x40 - move $16,$5 - move $4,$17 - move $5,$0 - sw $19,92($sp) - sw $31,100($sp) - .set noreorder - .set nomacro - jal memset - move $19,$7 - .set macro - .set reorder - - andi $7,$18,0x3f - .set noreorder - .set nomacro - beq $7,$0,$L10 - move $6,$0 - .set macro - .set reorder - -$L7: - srl $5,$6,2 - sll $5,$5,2 - lbu $4,0($16) - addu $5,$5,$17 - andi $2,$6,0x3 - sll $2,$2,3 - lw $3,0($5) - sll $4,$4,$2 - addiu $6,$6,1 - xor $3,$3,$4 - sltu $2,$6,$7 - sw $3,0($5) - .set noreorder - .set nomacro - bne $2,$0,$L7 - addiu $16,$16,1 - .set macro - .set reorder - -$L10: - andi $5,$18,0x3c - andi $3,$18,0x3 - addu $5,$5,$17 - sll $3,$3,3 - addiu $3,$3,7 - lw $4,0($5) - li $2,1 # 0x1 - sll $2,$2,$3 - xor $4,$4,$2 - sltu $3,$7,56 - .set noreorder - .set nomacro - beq $3,$0,$L12 - sw $4,0($5) - .set macro - .set reorder - - sll $3,$19,3 - srl $2,$18,29 - or $2,$2,$3 - move $4,$20 - sll $3,$18,3 - move $5,$17 - sw $3,72($sp) - .set noreorder - .set nomacro - jal compress - sw $2,76($sp) - .set macro - .set reorder - - lw $31,100($sp) - lw $20,96($sp) - lw $19,92($sp) - lw $18,88($sp) - lw $17,84($sp) - lw $16,80($sp) - .set noreorder - .set nomacro - j $31 - addiu $sp,$sp,104 - .set macro - .set reorder - -$L12: - move $4,$20 - .set noreorder - .set nomacro - jal compress - move $5,$17 - .set macro - .set reorder - - move $4,$17 - move $5,$0 - .set noreorder - .set nomacro - jal memset - li $6,64 # 0x40 - .set macro - .set reorder - - sll $3,$19,3 - srl $2,$18,29 - or $2,$2,$3 - move $4,$20 - sll $3,$18,3 - move $5,$17 - sw $3,72($sp) - .set noreorder - .set nomacro - jal compress - sw $2,76($sp) - .set macro - .set reorder - - lw $31,100($sp) - lw $20,96($sp) - lw $19,92($sp) - lw $18,88($sp) - lw $17,84($sp) - lw $16,80($sp) - .set noreorder - .set nomacro - j $31 - addiu $sp,$sp,104 - .set macro - .set reorder - - .end MDfinish diff --git a/lib/CPUs/MIPS/sim/asm/rmd160_test.s b/lib/CPUs/MIPS/sim/asm/rmd160_test.s deleted file mode 100644 index ec7382d..0000000 --- a/lib/CPUs/MIPS/sim/asm/rmd160_test.s +++ /dev/null @@ -1,556 +0,0 @@ - .file 1 "rmd160_test.c" - .set nobopt - .text - .align 2 - .globl saus - .ent saus -saus: - .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 - .mask 0x00000000,0 - .fmask 0x00000000,0 - li $2,-2147483648 # 0xffffffff80000000 - sll $4,$4,24 - sra $4,$4,24 - ori $5,$2,0x4 - ori $3,$2,0x8 -$L2: - lbu $2,0($3) - andi $2,$2,0x2 - bne $2,$0,$L2 - sb $4,0($5) - j $31 - .end saus - .align 2 - .globl sputs - .ent sputs -sputs: - .frame $sp,32,$31 # vars= 0, regs= 3/0, args= 16, gp= 0 - .mask 0x80030000,-8 - .fmask 0x00000000,0 - addiu $sp,$sp,-32 - sw $17,20($sp) - sw $16,16($sp) - sw $31,24($sp) - move $16,$4 - lb $4,0($4) - .set noreorder - .set nomacro - j $L11 - move $17,$16 - .set macro - .set reorder - -$L12: - .set noreorder - .set nomacro - jal saus - addiu $16,$16,1 - .set macro - .set reorder - - lb $4,0($16) -$L11: - .set noreorder - .set nomacro - bne $4,$0,$L12 - subu $2,$16,$17 - .set macro - .set reorder - - lw $31,24($sp) - lw $17,20($sp) - lw $16,16($sp) - .set noreorder - .set nomacro - j $31 - addiu $sp,$sp,32 - .set macro - .set reorder - - .end sputs - .align 2 - .globl print_byte - .ent print_byte -print_byte: - .frame $sp,32,$31 # vars= 0, regs= 3/0, args= 16, gp= 0 - .mask 0x80030000,-8 - .fmask 0x00000000,0 - addiu $sp,$sp,-32 - sw $16,16($sp) - sll $16,$4,24 - sw $17,20($sp) - sw $31,24($sp) - sra $16,$16,24 - li $17,1 # 0x1 - sra $2,$16,4 -$L22: - andi $5,$2,0xf - sll $2,$16,4 - sll $16,$2,24 - sltu $3,$5,10 - addiu $17,$17,-1 - sra $16,$16,24 - .set noreorder - .set nomacro - bne $3,$0,$L18 - addiu $4,$5,48 - .set macro - .set reorder - - addiu $4,$5,55 -$L18: - jal saus - .set noreorder - .set nomacro - bgez $17,$L22 - sra $2,$16,4 - .set macro - .set reorder - - lw $31,24($sp) - lw $17,20($sp) - lw $16,16($sp) - .set noreorder - .set nomacro - j $31 - addiu $sp,$sp,32 - .set macro - .set reorder - - .end print_byte - .align 2 - .globl print_word - .ent print_word -print_word: - .frame $sp,32,$31 # vars= 0, regs= 3/0, args= 16, gp= 0 - .mask 0x80030000,-8 - .fmask 0x00000000,0 - addiu $sp,$sp,-32 - sw $17,20($sp) - sw $16,16($sp) - sw $31,24($sp) - move $16,$4 - li $17,3 # 0x3 -$L27: - sra $4,$16,24 - .set noreorder - .set nomacro - jal print_byte - addiu $17,$17,-1 - .set macro - .set reorder - - .set noreorder - .set nomacro - bgez $17,$L27 - sll $16,$16,8 - .set macro - .set reorder - - lw $31,24($sp) - lw $17,20($sp) - lw $16,16($sp) - .set noreorder - .set nomacro - j $31 - addiu $sp,$sp,32 - .set macro - .set reorder - - .end print_word - - .lcomm hashcode.0,20 - .align 2 - .globl RMD - .ent RMD -RMD: - .frame $sp,128,$31 # vars= 88, regs= 6/0, args= 16, gp= 0 - .mask 0x801f0000,-4 - .fmask 0x00000000,0 - addiu $sp,$sp,-128 - sw $16,104($sp) - move $16,$4 - addiu $4,$sp,16 - sw $31,124($sp) - sw $20,120($sp) - sw $18,112($sp) - sw $17,108($sp) - .set noreorder - .set nomacro - jal MDinit - sw $19,116($sp) - .set macro - .set reorder - - .set noreorder - .set nomacro - jal strlen - move $4,$16 - .set macro - .set reorder - - move $18,$2 - sltu $2,$2,64 - move $17,$18 - .set noreorder - .set nomacro - bne $2,$0,$L44 - addiu $20,$sp,16 - .set macro - .set reorder - - addiu $19,$sp,40 - addiu $5,$20,24 -$L50: - li $11,15 # 0xf -$L37: - lbu $2,3($16) - lbu $3,2($16) - lbu $4,1($16) - sll $3,$3,16 - sll $2,$2,24 - or $2,$2,$3 - sll $4,$4,8 - lbu $3,0($16) - or $2,$2,$4 - or $2,$2,$3 - addiu $11,$11,-1 - sw $2,0($5) - addiu $16,$16,4 - .set noreorder - .set nomacro - bgez $11,$L37 - addiu $5,$5,4 - .set macro - .set reorder - - addiu $17,$17,-64 - addiu $4,$sp,16 - .set noreorder - .set nomacro - jal compress - move $5,$19 - .set macro - .set reorder - - sltu $2,$17,64 - .set noreorder - .set nomacro - beq $2,$0,$L50 - addiu $5,$20,24 - .set macro - .set reorder - -$L44: - move $5,$16 - move $6,$18 - addiu $4,$sp,16 - .set noreorder - .set nomacro - jal MDfinish - move $7,$0 - .set macro - .set reorder - - move $11,$0 - la $15,hashcode.0 - la $13,hashcode.0+1 - la $14,hashcode.0+2 - la $12,hashcode.0+3 -$L42: - srl $2,$11,2 - sll $2,$2,2 - addu $2,$2,$20 - lw $3,0($2) - addu $7,$11,$15 - addu $8,$11,$13 - addu $9,$11,$14 - addu $10,$11,$12 - addiu $11,$11,4 - srl $6,$3,24 - srl $2,$3,8 - srl $4,$3,16 - sltu $5,$11,20 - sb $3,0($7) - sb $2,0($8) - sb $4,0($9) - .set noreorder - .set nomacro - bne $5,$0,$L42 - sb $6,0($10) - .set macro - .set reorder - - lw $31,124($sp) - lw $20,120($sp) - lw $19,116($sp) - lw $18,112($sp) - lw $17,108($sp) - lw $16,104($sp) - la $2,hashcode.0 - .set noreorder - .set nomacro - j $31 - addiu $sp,$sp,128 - .set macro - .set reorder - - .end RMD - .section .rodata.str1.4,"aMS",@progbits,1 - .align 2 -$LC0: - .ascii "\r\n\000" - .align 2 -$LC1: - .ascii "* message: \000" - .align 2 -$LC2: - .ascii " hashcode: \000" - .text - .align 2 - .globl RMDstring - .ent RMDstring -RMDstring: - .frame $sp,40,$31 # vars= 8, regs= 3/0, args= 16, gp= 0 - .mask 0x80030000,-8 - .fmask 0x00000000,0 - lbu $3,$LC0+2 - lhu $2,$LC0 - addiu $sp,$sp,-40 - sw $31,32($sp) - sb $3,18($sp) - sw $17,28($sp) - sw $16,24($sp) - sh $2,16($sp) - .set noreorder - .set nomacro - jal RMD - move $16,$5 - .set macro - .set reorder - - addiu $4,$sp,16 - .set noreorder - .set nomacro - jal sputs - move $17,$2 - .set macro - .set reorder - - la $4,$LC1 - jal sputs - .set noreorder - .set nomacro - jal sputs - move $4,$16 - .set macro - .set reorder - - .set noreorder - .set nomacro - jal sputs - addiu $4,$sp,16 - .set macro - .set reorder - - la $4,$LC2 - .set noreorder - .set nomacro - jal sputs - move $16,$0 - .set macro - .set reorder - - addu $2,$17,$16 -$L58: - lb $4,0($2) - .set noreorder - .set nomacro - jal print_byte - addiu $16,$16,1 - .set macro - .set reorder - - sltu $2,$16,20 - .set noreorder - .set nomacro - bne $2,$0,$L58 - addu $2,$17,$16 - .set macro - .set reorder - - .set noreorder - .set nomacro - jal sputs - addiu $4,$sp,16 - .set macro - .set reorder - - lw $31,32($sp) - lw $17,28($sp) - lw $16,24($sp) - .set noreorder - .set nomacro - j $31 - addiu $sp,$sp,40 - .set macro - .set reorder - - .end RMDstring - .rdata - .align 2 -$LC3: - .byte -1 - .byte 35 - .byte -100 - .byte -42 - .byte 89 - .byte -118 - .byte 121 - .byte 46 - .byte -89 - .byte -85 - .byte 108 - .byte -8 - .byte 117 - .byte -74 - .byte 53 - .byte 94 - .byte 93 - .byte -128 - .byte 106 - .byte 54 - .section .rodata.str1.4 - .align 2 -$LC4: - .ascii "MIPS R3000 CPU\000" - .align 2 -$LC5: - .ascii "Failed\r\n\000" - .text - .align 2 - .globl main - .ent main -main: - .frame $sp,88,$31 # vars= 48, regs= 5/0, args= 16, gp= 0 - .mask 0x800f0000,-8 - .fmask 0x00000000,0 - lwl $2,$LC3+3 - lwl $3,$LC3+7 - lwr $2,$LC3 - lwr $3,$LC3+4 - lwl $4,$LC3+11 - lwl $5,$LC3+15 - lwl $6,$LC3+19 - addiu $sp,$sp,-88 - lwr $4,$LC3+8 - lwr $5,$LC3+12 - lwr $6,$LC3+16 - sw $2,16($sp) - sw $3,20($sp) - lw $2,$LC4 - lw $3,$LC4+4 - sw $19,76($sp) - sw $18,72($sp) - sw $17,68($sp) - sw $4,24($sp) - sw $5,28($sp) - sw $2,40($sp) - sw $31,80($sp) - sw $16,64($sp) - sw $6,32($sp) - sw $3,44($sp) - lw $2,$LC4+8 - lhu $3,$LC4+12 - sw $2,48($sp) - lbu $2,$LC4+14 - sh $3,52($sp) - sb $2,54($sp) - lbu $3,$LC0+2 - lhu $2,$LC0 - li $4,-2147483648 # 0xffffffff80000000 - sh $2,56($sp) - sb $3,58($sp) - ori $5,$4,0x9 - li $2,53 - ori $4,$4,0x8 - li $3,85 - sb $2,0($5) - move $18,$0 - sb $3,0($4) - addiu $19,$sp,56 - addiu $17,$sp,40 -$L60: - .set noreorder - .set nomacro - jal print_word - move $4,$18 - .set macro - .set reorder - - .set noreorder - .set nomacro - jal sputs - move $4,$19 - .set macro - .set reorder - - addiu $18,$18,1 - .set noreorder - .set nomacro - j $L66 - li $16,32249 # 0x7df9 - .set macro - .set reorder - -$L64: - .set noreorder - .set nomacro - bltz $16,$L70 - move $4,$17 - .set macro - .set reorder - -$L66: - .set noreorder - .set nomacro - jal RMD - move $4,$17 - .set macro - .set reorder - - move $4,$2 - addiu $5,$sp,16 - .set noreorder - .set nomacro - jal memcmp - li $6,20 # 0x14 - .set macro - .set reorder - - la $4,$LC5 - .set noreorder - .set nomacro - beq $2,$0,$L64 - addiu $16,$16,-1 - .set macro - .set reorder - - jal sputs - .set noreorder - .set nomacro - bgez $16,$L66 - move $4,$17 - .set macro - .set reorder - -$L70: - .set noreorder - .set nomacro - jal RMDstring - move $5,$17 - .set macro - .set reorder - - j $L60 - .end main diff --git a/lib/CPUs/MIPS/sim/asm/spim_load_store.s b/lib/CPUs/MIPS/sim/asm/spim_load_store.s deleted file mode 100644 index 864d660..0000000 --- a/lib/CPUs/MIPS/sim/asm/spim_load_store.s +++ /dev/null @@ -1,50 +0,0 @@ -main: - li, $8, 0x81234678 - -# SB - li, $15, 0x10000000 - sw $8, 0($15) - - - mfc0 $9, $12 - li $10, 0x02000000 - or $9, $9, $10 - mtc0 $9, $12 - lwl $16, 0($15) - lwl $17, 1($15) - lwl $18, 2($15) - lwl $19, 3($15) - nop - lwr $24, 0($15) - lwr $25, 1($15) - lwr $26, 2($15) - lwr $27, 3($15) - nop - lbu $16, 0($15) - lbu $17, 1($15) - lbu $18, 2($15) - lbu $19, 3($15) - nop - lb $24, 0($15) - lb $25, 1($15) - lb $26, 2($15) - lb $27, 3($15) - nop - swl $8, 4($15) - swl $8, 9($15) - swl $8, 14($15) - swl $8, 19($15) - nop - swr $8, 20($15) - swr $8, 25($15) - swr $8, 30($15) - swr $8, 35($15) - nop - sb $8, 0($15) - sb $8, 1($15) - sb $8, 2($15) - sb $8, 3($15) - nop - nop - nop - \ No newline at end of file diff --git a/lib/CPUs/MIPS/sim/asm/startup.s b/lib/CPUs/MIPS/sim/asm/startup.s deleted file mode 100644 index a53059e..0000000 --- a/lib/CPUs/MIPS/sim/asm/startup.s +++ /dev/null @@ -1,27 +0,0 @@ - .file "startup.s" - - .section .stext,"ax" - .extern _init - .align 2 - -_start: - .set noreorder - - # Set Kernel mode - li $26, 0x1040040C - mtc0 $26, $12 - li $26, 0x00000000 - mtc0 $26, $13 - - mfc0 $26, $15 - nop - mtc0 $26, $31 - - # jump init - la $26, _init - jr $26 - - # set user mode - rfe - - .set reorder diff --git a/lib/CPUs/MIPS/sim/asm/test1.s b/lib/CPUs/MIPS/sim/asm/test1.s deleted file mode 100644 index 73f2ec3..0000000 --- a/lib/CPUs/MIPS/sim/asm/test1.s +++ /dev/null @@ -1,39 +0,0 @@ - .text - .globl main - .globl __start - -__start: j main - -main: lui $1, 0x1234 - ori $1, $1, 0x5678 - andi $1, $1, 0xF00F - addi $1, -0x5004 -loop: addi $1, -1 - bgtz $1, loop - lui $2, 0 - ori $2, 1 - lui $1, 0 - ori $1, 4 -loop2: sub $1, $1, $2 - bgtz $1, loop2 - lui $31, 0x0040 - jr $31 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - - \ No newline at end of file diff --git a/lib/CPUs/MIPS/sim/asm/test2.s b/lib/CPUs/MIPS/sim/asm/test2.s deleted file mode 100644 index 30353ab..0000000 --- a/lib/CPUs/MIPS/sim/asm/test2.s +++ /dev/null @@ -1,40 +0,0 @@ - .text - .globl main - .globl __start - -__start: j main - -main: lui $1, 0x1234 - ori $1, $1, 0x5678 - lui $3, 0x5555 - ori $3, $3, 0xAAAA - lui $2, 0x1000 - sw $1, 0($2) - sw $3, 4($2) - sw $2, 0($2) - sw $1, 4($2) - lw $1, 4($2) - lw $4, 0($2) - lui $5, 0x0001 - lui $6, 0x0002 - lui $7, 0x0003 - lui $8, 0x0004 - add $4, $4, $5 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - j main - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - - \ No newline at end of file diff --git a/lib/CPUs/MIPS/sim/asm/test3.s b/lib/CPUs/MIPS/sim/asm/test3.s deleted file mode 100644 index f24d9a4..0000000 --- a/lib/CPUs/MIPS/sim/asm/test3.s +++ /dev/null @@ -1,40 +0,0 @@ - .text - .globl main - .globl __start - -__start: j main - -main: lui $1, 0x1234 - ori $1, $1, 0x5A5A - sll $1, $1, 1 - sll $1, $1, 4 - sll $1, $1, 2 - sll $1, $1, 1 - sll $1, $1, 8 - srl $1, $1, 2 - srl $1, $1, 5 - srl $1, $1, 1 - srl $1, $1, 8 - xori $1, $1, 0xFFFF - lui $31, 0x0040 - jr $31 - xor $1, $1, $31 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - - \ No newline at end of file diff --git a/lib/CPUs/MIPS/sim/asm/test4.s b/lib/CPUs/MIPS/sim/asm/test4.s deleted file mode 100644 index 830808f..0000000 --- a/lib/CPUs/MIPS/sim/asm/test4.s +++ /dev/null @@ -1,34 +0,0 @@ - .text - .globl main - .globl __start - -__start: j main - -main: sll $0, $0, 0 - lui $1, 0x1000 - addi $2, $1, 0 - lui $7, 0x1234 - lui $5, 0x0001 - sw $7, 0($1) - lw $3, 0($2) - add $8, $3, $5 - add $9, $3, $5 - add $10, $3, $5 - add $11, $3, $5 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - j main - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - - \ No newline at end of file diff --git a/lib/CPUs/MIPS/sim/asm/test5.s b/lib/CPUs/MIPS/sim/asm/test5.s deleted file mode 100644 index 89d8a63..0000000 --- a/lib/CPUs/MIPS/sim/asm/test5.s +++ /dev/null @@ -1,39 +0,0 @@ - .text - .globl main - .globl __start - -__start: j main - -main: lui $1, 0x8000 - lui $2, 0 - lui $3, 0 - ori $2, 1 - ori $3, 3 - srl $1, $1, 1 - sll $1, $1, 1 - sra $1, $1, 1 - sra $1, $1, 3 - sllv $4, $1, $3 - srav $5, $1, $2 - srav $6, $1, $3 - lui $31, 0x0040 - jr $31 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - - \ No newline at end of file diff --git a/lib/CPUs/MIPS/sim/asm/test6.s b/lib/CPUs/MIPS/sim/asm/test6.s deleted file mode 100644 index 65809dd..0000000 --- a/lib/CPUs/MIPS/sim/asm/test6.s +++ /dev/null @@ -1,31 +0,0 @@ - .text - .globl main - .globl __start - -__start: j main - -main: lui $8, 0 -loop: sll $0, $0, 0 - jal subr1 - la $2, subr2 - jalr $15, $2 - sll $0, $0, 0 - j loop - -subr1: addi $8, 1 - sll $0, $0, 0 - jr $31 -subr2: addi $8, 16 - sll $0, $0, 0 - jr $15 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - - \ No newline at end of file diff --git a/lib/CPUs/MIPS/sim/asm/test7.s b/lib/CPUs/MIPS/sim/asm/test7.s deleted file mode 100644 index 05d9457..0000000 --- a/lib/CPUs/MIPS/sim/asm/test7.s +++ /dev/null @@ -1,17 +0,0 @@ - -main: li $2, 0x12345678 - li $3, 0x87654321 - mult $2, $3 - multu $2, $3 - mult $3, $2 - multu $3, $2 - - mult $2, $2 - multu $2, $2 - mult $3, $3 - multu $3, $3 - - sll $0, $0, 0 - j main - sll $0, $0, 0 - \ No newline at end of file diff --git a/lib/CPUs/MIPS/sim/asm/test_addsub.s b/lib/CPUs/MIPS/sim/asm/test_addsub.s deleted file mode 100644 index 0e0c700..0000000 --- a/lib/CPUs/MIPS/sim/asm/test_addsub.s +++ /dev/null @@ -1,76 +0,0 @@ - .text - .globl main - .globl __start - -__start: j main - -main: li $2, 0x12345678 - li $4, 0x12345678 - li $6, 0x12345678 - li $8, 0x12345678 - li $3, 0x77654321 - li $5, 0x77654321 - li $7, 0x77654321 - li $9, 0x77654321 - addu $15, $2, $3 - addu $15, $3, $2 - addu $15, $2, $2 - addu $15, $3, $3 - - sll $0, $0, 0 - - subu $15, $2, $3 - subu $15, $3, $2 - subu $15, $2, $2 - subu $15, $3, $3 - - sll $0, $0, 0 - - addiu $4, 0x1234 - addiu $8, -0x1234 - addiu $5, 0x1234 - addiu $9, -0x1234 - - sll $0, $0, 0 - - add $15, $2, $3 - add $15, $3, $2 - add $15, $2, $2 - add $15, $3, $3 - - sll $0, $0, 0 - - sub $15, $2, $3 - sub $15, $3, $2 - sub $15, $2, $2 - sub $15, $3, $3 - - sll $0, $0, 0 - - addi $2, 0x1234 - addi $6, -0x1234 - addi $3, 0x1234 - addi $7, -0x1234 - - sll $0, $0, 0 - - j main - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - sll $0, $0, 0 - - \ No newline at end of file diff --git a/lib/CPUs/MIPS/sim/asm/test_muldiv.s b/lib/CPUs/MIPS/sim/asm/test_muldiv.s deleted file mode 100644 index 9c85e8a..0000000 --- a/lib/CPUs/MIPS/sim/asm/test_muldiv.s +++ /dev/null @@ -1,17 +0,0 @@ -main: - li $8, 0x12345678 - li $9, 0x87654321 - mthi $8 - mfhi $10 - addu $16, $10, $9 - - mtlo $9 - mflo $11 - multu $8, $9 -# addu $17, $11, $8 - - nop - nop - nop - nop - \ No newline at end of file diff --git a/lib/CPUs/MIPS/sim/asm/test_slt.s b/lib/CPUs/MIPS/sim/asm/test_slt.s deleted file mode 100644 index 0f55466..0000000 --- a/lib/CPUs/MIPS/sim/asm/test_slt.s +++ /dev/null @@ -1,57 +0,0 @@ -# .ktext 0x80000180 - .text 0x00410000 - .globl main - -main: li $2, 0x12345678 - li $3, 0x23456789 - li $4, 0x87654321 - li $5, 0x98765432 - li $8, 0x10000000 - sll $0, $0, 0 - - sltu $15, $2, $2 - sltu $15, $2, $3 - sltu $15, $2, $4 - sltu $15, $2, $5 - - sltu $15, $3, $2 - sltu $15, $3, $3 - sltu $15, $3, $4 - sltu $15, $3, $5 - - sltu $15, $4, $2 - sltu $15, $4, $3 - sltu $15, $4, $4 - sltu $15, $4, $5 - - sltu $15, $5, $2 - sltu $15, $5, $3 - sltu $15, $5, $4 - sltu $15, $5, $5 - - sll $0, $0, 0 - - slt $15, $2, $2 - slt $15, $2, $3 - slt $15, $2, $4 - slt $15, $2, $5 - - slt $15, $3, $2 - slt $15, $3, $3 - slt $15, $3, $4 - slt $15, $3, $5 - - slt $15, $4, $2 - slt $15, $4, $3 - slt $15, $4, $4 - slt $15, $4, $5 - - slt $15, $5, $2 - slt $15, $5, $3 - slt $15, $5, $4 - slt $15, $5, $5 - - sll $0, $0, 0 - - j main - sll $0, $0, 0 diff --git a/lib/CPUs/MIPS/sim/asm/test_slti.s b/lib/CPUs/MIPS/sim/asm/test_slti.s deleted file mode 100644 index 7c47f70..0000000 --- a/lib/CPUs/MIPS/sim/asm/test_slti.s +++ /dev/null @@ -1,57 +0,0 @@ -# .ktext 0x80000180 - .text 0x00410000 - .globl main - -main: li $2, 0x12345678 - li $3, 0x23456789 - li $4, 0x87654321 - li $5, 0x98765432 - li $8, 0x10000000 - sll $0, $0, 0 - - sltiu $15, $2, 0x1234 - sltiu $15, $2, 0x2345 - sltiu $15, $2, -0x1234 - sltiu $15, $2, -0x2345 - - sltiu $15, $3, 0x1234 - sltiu $15, $3, 0x2345 - sltiu $15, $3, -0x1234 - sltiu $15, $3, -0x2345 - - sltiu $15, $4, 0x1234 - sltiu $15, $4, 0x2345 - sltiu $15, $4, -0x1234 - sltiu $15, $4, -0x2345 - - sltiu $15, $5, 0x1234 - sltiu $15, $5, 0x2345 - sltiu $15, $5, -0x1234 - sltiu $15, $5, -0x2345 - - sll $0, $0, 0 - - slti $15, $2, 0x1234 - slti $15, $2, 0x2345 - slti $15, $2, -0x1234 - slti $15, $2, -0x2345 - - slti $15, $3, 0x1234 - slti $15, $3, 0x2345 - slti $15, $3, -0x1234 - slti $15, $3, -0x2345 - - slti $15, $4, 0x1234 - slti $15, $4, 0x2345 - slti $15, $4, -0x1234 - slti $15, $4, -0x2345 - - slti $15, $5, 0x1234 - slti $15, $5, 0x2345 - slti $15, $5, -0x1234 - slti $15, $5, -0x2345 - - sll $0, $0, 0 - - j main - sll $0, $0, 0 diff --git a/lib/CPUs/MIPS/sim/asm/test_sub.s b/lib/CPUs/MIPS/sim/asm/test_sub.s deleted file mode 100644 index f3ee61d..0000000 --- a/lib/CPUs/MIPS/sim/asm/test_sub.s +++ /dev/null @@ -1,57 +0,0 @@ -# .ktext 0x80000180 - .text 0x00410000 - .globl main - -main: li $2, 0x12345678 - li $3, 0x23456789 - li $4, 0x87654321 - li $5, 0x98765432 - li $8, 0x10000000 - sll $0, $0, 0 - - subu $15, $2, $2 - subu $15, $2, $3 - subu $15, $2, $4 - subu $15, $2, $5 - - subu $15, $3, $2 - subu $15, $3, $3 - subu $15, $3, $4 - subu $15, $3, $5 - - subu $15, $4, $2 - subu $15, $4, $3 - subu $15, $4, $4 - subu $15, $4, $5 - - subu $15, $5, $2 - subu $15, $5, $3 - subu $15, $5, $4 - subu $15, $5, $5 - - sll $0, $0, 0 - - sub $15, $2, $2 - sub $15, $2, $3 - sub $15, $2, $4 - sub $15, $2, $5 - - sub $15, $3, $2 - sub $15, $3, $3 - sub $15, $3, $4 - sub $15, $3, $5 - - sub $15, $4, $2 - sub $15, $4, $3 - sub $15, $4, $4 - sub $15, $4, $5 - - sub $15, $5, $2 - sub $15, $5, $3 - sub $15, $5, $4 - sub $15, $5, $5 - - sll $0, $0, 0 - - j main - sll $0, $0, 0 diff --git a/lib/CPUs/MIPS/sim/asm/testbench.c b/lib/CPUs/MIPS/sim/asm/testbench.c deleted file mode 100644 index 1cbf3b6..0000000 --- a/lib/CPUs/MIPS/sim/asm/testbench.c +++ /dev/null @@ -1,322 +0,0 @@ -#include -#include -#include -#include "utils.h" - -#define NO_ERROR 0x00000000 -#define ERROR 0x80000000 -#define IS_ERROR(e) ((e & ERROR) == ERROR) - -#define TEST10_ERROR (ERROR | 0x10) -#define TEST11_ERROR (ERROR | 0x11) -#define TEST12_ERROR (ERROR | 0x12) - -int fibonacci(int f0, int f1, int *pDst, int len) -{ - int i; - - i = 0; - - pDst[i++] = f0; - pDst[i++] = f1; - - for (; i < len; i++) - { - pDst[i] = pDst[i-2] + pDst[i-1]; - } - - return i; -} - -int StatusRegister_read(void) -{ - __asm - ( - ".set noreorder\n" - "mfc0 $2, $12\n" - ".set reorder\n" - - ); -} - -int RevisionRegister_read(void) -{ - __asm - ( - ".set noreorder\n" - "mfc0 $2, $15\n" - ".set reorder\n" - - ); -} - -void PrintCPUinfo(void) -{ - int result, rev_id; - - char *cpu_type_str[7] = {"invalid", "R2000", "R3000", "R6000", "R4000", "reserved", "R6000A"}; - - // Print Status register - result = StatusRegister_read(); - sputs("Status : "); - print_word(result); - sputs("\r\n"); - - // Print Revision - result = RevisionRegister_read(); - rev_id = (result >> 8) & 0xFF; - sputs("CPU type: "); - if ((rev_id > 0) && (rev_id < 0x07)) - { - sputs(cpu_type_str[rev_id]); - sputs(" Rev."); - rev_id = result & 0xFF; - print_byte((char)rev_id); - } - else - sputs("Unknown"); - - sputs("\r\n"); - -} - -int Test10_LoadStore() -{ - int *buf, i, result, data, err; - volatile int *pPtr; - - buf = (int*)malloc(32*sizeof(int)); - while(1) - { - err = TEST10_ERROR; - // Basic Load/Store - pPtr = buf; - *pPtr++ = 0x00000000; - *pPtr++ = 0x55555555; - *pPtr++ = 0xAAAAAAAA; - *pPtr++ = 0xFFFFFFFF; - pPtr = buf; - if (*pPtr++ != 0x00000000) - break; - if (*pPtr++ != 0x55555555) - break; - if (*pPtr++ != 0xAAAAAAAA) - break; - if (*pPtr++ != 0xFFFFFFFF) - break; - - // Filling from left - pPtr = buf; - data = 0x00000000; - for (i=0; i < 32; i++) - { - *pPtr++ = data; - data = data >> 1 | 0x80000000; - - } - pPtr = buf; - data = 0x00000000; - for (i=0; i < 32; i++) - { - - if (*pPtr++ != data) - break; - - data = data >> 1 | 0x80000000; - } - if (i != 32) - break; - - // Filling from right - pPtr = buf; - data = 0x00000000; - for (i=0; i < 32; i++) - { - *pPtr++ = data; - data = data << 1 | 1; - - } - pPtr = buf; - data = 0x00000000; - for (i=0; i < 32; i++) - { - - if (*pPtr++ != data) - break; - - data = data << 1 | 1; - } - if (i != 32) - break; - - // Walking ones - pPtr = buf; - data = 0x00000001; - for (i=0; i < 32; i++) - { - *pPtr++ = data; - data = data << 1; - - } - pPtr = buf; - data = 0x00000001; - for (i=0; i < 32; i++) - { - - if (*pPtr++ != data) - break; - - data = data << 1; - } - if (i != 32) - break; - - // Walking zeros - pPtr = buf; - data = 0xFFFFFFFE; - for (i=0; i < 32; i++) - { - *pPtr++ = data; - data = data << 1 | 1; - - } - pPtr = buf; - data = 0xFFFFFFFE; - for (i=0; i < 32; i++) - { - - if (*pPtr++ != data) - break; - - data = data << 1 | 1; - - } - if (i != 32) - break; - - err = NO_ERROR; - break; - } - free(buf); - return err; - -} - - -#define NUM_ELEMENTS 20 -#define NUM_RUNS 3 -int Test11_AddSub() -{ - int buf[NUM_ELEMENTS], result, i, j, diff, fill, num_right_elements, num_right_runs; - - fill = 0xAAAAAAAA; - - num_right_runs = 0; - - for (i=0; i < NUM_RUNS; i++) - { - for (j=0; j < NUM_ELEMENTS; j++) - buf[j] = fill; - - fill = ((fill ^ i) - 1) << 1; - num_right_elements = 2; - result = fibonacci(i, i+1, buf, NUM_ELEMENTS); - for (j=2; j < NUM_ELEMENTS; j++) - { - diff = buf[j] - buf[j-1]; - if (diff == buf[j-2]) - num_right_elements++; - } - if (num_right_elements == NUM_ELEMENTS) - num_right_runs++; - } - - if (num_right_runs != NUM_RUNS) - return TEST11_ERROR; - - return NO_ERROR; -} - -int Test12_MulDiv() -{ - int mix, i, j; - int s1, s2, sp, st; - div_t div_res; - - srand(0x19701031); - for (i=0; i < 100; i++) - { - for (j=1; j < 1000; j++) - { - mix = (int)rand(); - mix = (mix << 8) ^ (mix << 16); - s1 = (int)rand() ^ mix; - mix = (int)rand(); - mix = (mix << 8) ^ (mix << 16); - s2 = (int)rand() ^ mix; - - div_res = div(s1, s2); - - sp = s2*div_res.quot; - st = div_res.rem + sp; - if (st != s1) - return TEST12_ERROR; - } - } - return NO_ERROR; -} - -int main (void) -{ - int result, i, j, cnt; - volatile char *pUART_baud = (char*)0x80000009; - volatile int *pReg = (int*)0x80000000; - volatile int *pReg_usec = (int*)0x80000010; - volatile int *pReg_sec = (int*)0x80000014; - time_t clock; - struct tm *pDate; -// *pUART_baud = 0x35/4; - - PrintCPUinfo(); - - cnt = 0; -// *pReg_sec = 0x12345678; - while (1) - { - *pReg = cnt & 0x3FFFFFFF; - - result = Test10_LoadStore(); - if (IS_ERROR(result)) - break; - - result = Test11_AddSub(); - if (IS_ERROR(result)) - break; - - result = Test12_MulDiv(); - if (IS_ERROR(result)) - break; - -// printf("Iteration %d: Passed\r\n", cnt++); - sputs("Iteration "); - print_word(cnt++); - sputs(": Passed\r\n"); - - clock = time(NULL); - pDate = gmtime(&clock); - print_byte(pDate->tm_hour); - sputs(":"); - print_byte(pDate->tm_min); - sputs(":"); - print_byte(pDate->tm_sec); - sputs("\r\n"); - } - *pReg = 0x40000000 | cnt; - sputs("Failed with error "); - print_word(result); - sputs(" \r\n"); - - return 1; - -} - diff --git a/lib/CPUs/MIPS/sim/asm/testbench.s b/lib/CPUs/MIPS/sim/asm/testbench.s deleted file mode 100644 index acc1d4d..0000000 --- a/lib/CPUs/MIPS/sim/asm/testbench.s +++ /dev/null @@ -1,924 +0,0 @@ - .file 1 "testbench.c" - .set nobopt - .text - .align 2 - .globl fibonacci - .ent fibonacci -fibonacci: - .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 - .mask 0x00000000,0 - .fmask 0x00000000,0 - li $8,2 # 0x2 - slt $2,$8,$7 - sw $4,0($6) - .set noreorder - .set nomacro - beq $2,$0,$L7 - sw $5,4($6) - .set macro - .set reorder - - addiu $6,$6,8 -$L5: - lw $2,-8($6) - lw $3,-4($6) - addiu $8,$8,1 - addu $2,$2,$3 - slt $4,$8,$7 - sw $2,0($6) - .set noreorder - .set nomacro - bne $4,$0,$L5 - addiu $6,$6,4 - .set macro - .set reorder - -$L7: - .set noreorder - .set nomacro - j $31 - move $2,$8 - .set macro - .set reorder - - .end fibonacci - .align 2 - .globl StatusRegister_read - .ent StatusRegister_read -StatusRegister_read: - .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 - .mask 0x00000000,0 - .fmask 0x00000000,0 - #APP - .set noreorder -mfc0 $2, $12 -.set reorder - - #NO_APP - j $31 - .end StatusRegister_read - .align 2 - .globl RevisionRegister_read - .ent RevisionRegister_read -RevisionRegister_read: - .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 - .mask 0x00000000,0 - .fmask 0x00000000,0 - #APP - .set noreorder -mfc0 $2, $15 -.set reorder - - #NO_APP - j $31 - .end RevisionRegister_read - .section .rodata.str1.4,"aMS",@progbits,1 - .align 2 -$LC0: - .ascii "invalid\000" - .align 2 -$LC1: - .ascii "R2000\000" - .align 2 -$LC2: - .ascii "R3000\000" - .align 2 -$LC3: - .ascii "R6000\000" - .align 2 -$LC4: - .ascii "R4000\000" - .align 2 -$LC5: - .ascii "reserved\000" - .align 2 -$LC6: - .ascii "R6000A\000" - .rdata - .align 2 -$LC7: - .word $LC0 - .word $LC1 - .word $LC2 - .word $LC3 - .word $LC4 - .word $LC5 - .word $LC6 - .section .rodata.str1.4 - .align 2 -$LC8: - .ascii "Status : \000" - .align 2 -$LC9: - .ascii "\r\n\000" - .align 2 -$LC10: - .ascii "CPU type: \000" - .align 2 -$LC12: - .ascii "Unknown\000" - .align 2 -$LC11: - .ascii " Rev.\000" - .text - .align 2 - .globl PrintCPUinfo - .ent PrintCPUinfo -PrintCPUinfo: - .frame $sp,64,$31 # vars= 32, regs= 3/0, args= 16, gp= 0 - .mask 0x80030000,-8 - .fmask 0x00000000,0 - lw $2,$LC7 - addiu $sp,$sp,-64 - lw $3,$LC7+4 - sw $2,16($sp) - lw $2,$LC7+8 - sw $3,20($sp) - sw $2,24($sp) - lw $3,$LC7+12 - lw $2,$LC7+16 - sw $3,28($sp) - sw $2,32($sp) - lw $3,$LC7+20 - lw $2,$LC7+24 - sw $3,36($sp) - sw $31,56($sp) - sw $17,52($sp) - sw $16,48($sp) - .set noreorder - .set nomacro - jal StatusRegister_read - sw $2,40($sp) - .set macro - .set reorder - - la $4,$LC8 - .set noreorder - .set nomacro - jal sputs - move $17,$2 - .set macro - .set reorder - - .set noreorder - .set nomacro - jal print_word - move $4,$17 - .set macro - .set reorder - - la $4,$LC9 - jal sputs - jal RevisionRegister_read - sra $16,$2,8 - andi $16,$16,0xff - la $4,$LC10 - .set noreorder - .set nomacro - jal sputs - move $17,$2 - .set macro - .set reorder - - sll $3,$16,2 - addiu $16,$16,-1 - sltu $16,$16,6 - la $4,$LC12 - .set noreorder - .set nomacro - beq $16,$0,$L12 - addu $2,$sp,$3 - .set macro - .set reorder - - lw $4,16($2) - jal sputs - la $4,$LC11 - jal sputs - sll $4,$17,24 - .set noreorder - .set nomacro - jal print_byte - sra $4,$4,24 - .set macro - .set reorder - - la $4,$LC9 - jal sputs - lw $31,56($sp) - lw $17,52($sp) - lw $16,48($sp) - .set noreorder - .set nomacro - j $31 - addiu $sp,$sp,64 - .set macro - .set reorder - -$L12: - jal sputs - la $4,$LC9 - jal sputs - lw $31,56($sp) - lw $17,52($sp) - lw $16,48($sp) - .set noreorder - .set nomacro - j $31 - addiu $sp,$sp,64 - .set macro - .set reorder - - .end PrintCPUinfo - .align 2 - .globl Test10_LoadStore - .ent Test10_LoadStore -Test10_LoadStore: - .frame $sp,24,$31 # vars= 0, regs= 2/0, args= 16, gp= 0 - .mask 0x80010000,-4 - .fmask 0x00000000,0 - addiu $sp,$sp,-24 - li $4,128 # 0x80 - sw $31,20($sp) - .set noreorder - .set nomacro - jal malloc - sw $16,16($sp) - .set macro - .set reorder - - move $4,$2 - li $2,1431633920 # 0x55550000 - li $3,-1431699456 # 0xffffffffaaaa0000 - ori $5,$2,0x5555 - ori $6,$3,0xaaaa - li $7,-1 # 0xffffffffffffffff - sw $0,0($4) - sw $5,4($4) - sw $6,8($4) - sw $7,12($4) - lw $3,0($4) - li $2,-2147483648 # 0xffffffff80000000 - .set noreorder - .set nomacro - bne $3,$0,$L16 - ori $16,$2,0x10 - .set macro - .set reorder - - lw $2,4($4) - beq $2,$5,$L73 -$L16: - jal free - move $2,$16 - lw $31,20($sp) - lw $16,16($sp) - .set noreorder - .set nomacro - j $31 - addiu $sp,$sp,24 - .set macro - .set reorder - -$L73: - lw $2,8($4) - bne $2,$6,$L16 - lw $2,12($4) - .set noreorder - .set nomacro - bne $2,$7,$L16 - move $3,$4 - .set macro - .set reorder - - move $5,$0 - li $7,-2147483648 # 0xffffffff80000000 - li $6,31 # 0x1f -$L24: - sra $2,$5,1 - addiu $6,$6,-1 - sw $5,0($3) - addiu $3,$3,4 - .set noreorder - .set nomacro - bgez $6,$L24 - or $5,$2,$7 - .set macro - .set reorder - - move $3,$4 - move $5,$0 - move $6,$0 - .set noreorder - .set nomacro - j $L29 - li $8,-2147483648 # 0xffffffff80000000 - .set macro - .set reorder - -$L74: - addiu $6,$6,1 - slt $2,$6,32 - .set noreorder - .set nomacro - beq $2,$0,$L26 - or $5,$7,$8 - .set macro - .set reorder - -$L29: - lw $2,0($3) - sra $7,$5,1 - .set noreorder - .set nomacro - beq $2,$5,$L74 - addiu $3,$3,4 - .set macro - .set reorder - -$L26: - li $2,32 # 0x20 - .set noreorder - .set nomacro - bne $6,$2,$L16 - move $3,$4 - .set macro - .set reorder - - move $5,$0 - li $6,31 # 0x1f -$L34: - sll $2,$5,1 - addiu $6,$6,-1 - sw $5,0($3) - addiu $3,$3,4 - .set noreorder - .set nomacro - bgez $6,$L34 - ori $5,$2,0x1 - .set macro - .set reorder - - move $3,$4 - move $5,$0 - .set noreorder - .set nomacro - j $L39 - move $6,$0 - .set macro - .set reorder - -$L75: - addiu $6,$6,1 - slt $2,$6,32 - .set noreorder - .set nomacro - beq $2,$0,$L36 - ori $5,$7,0x1 - .set macro - .set reorder - -$L39: - lw $2,0($3) - sll $7,$5,1 - .set noreorder - .set nomacro - beq $2,$5,$L75 - addiu $3,$3,4 - .set macro - .set reorder - -$L36: - li $2,32 # 0x20 - .set noreorder - .set nomacro - bne $6,$2,$L16 - move $3,$4 - .set macro - .set reorder - - li $5,1 # 0x1 - li $6,31 # 0x1f -$L44: - addiu $6,$6,-1 - sw $5,0($3) - addiu $3,$3,4 - .set noreorder - .set nomacro - bgez $6,$L44 - sll $5,$5,1 - .set macro - .set reorder - - move $3,$4 - li $5,1 # 0x1 - .set noreorder - .set nomacro - j $L49 - move $6,$0 - .set macro - .set reorder - -$L76: - addiu $6,$6,1 - slt $2,$6,32 - .set noreorder - .set nomacro - beq $2,$0,$L46 - sll $5,$5,1 - .set macro - .set reorder - -$L49: - lw $2,0($3) - .set noreorder - .set nomacro - beq $2,$5,$L76 - addiu $3,$3,4 - .set macro - .set reorder - -$L46: - li $2,32 # 0x20 - .set noreorder - .set nomacro - bne $6,$2,$L16 - move $3,$4 - .set macro - .set reorder - - li $5,-2 # 0xfffffffffffffffe - li $6,31 # 0x1f -$L54: - sll $2,$5,1 - addiu $6,$6,-1 - sw $5,0($3) - addiu $3,$3,4 - .set noreorder - .set nomacro - bgez $6,$L54 - ori $5,$2,0x1 - .set macro - .set reorder - - move $3,$4 - li $5,-2 # 0xfffffffffffffffe - .set noreorder - .set nomacro - j $L59 - move $6,$0 - .set macro - .set reorder - -$L77: - addiu $6,$6,1 - slt $2,$6,32 - .set noreorder - .set nomacro - beq $2,$0,$L56 - ori $5,$7,0x1 - .set macro - .set reorder - -$L59: - lw $2,0($3) - sll $7,$5,1 - .set noreorder - .set nomacro - beq $2,$5,$L77 - addiu $3,$3,4 - .set macro - .set reorder - -$L56: - li $2,32 # 0x20 - bne $6,$2,$L16 - .set noreorder - .set nomacro - j $L16 - move $16,$0 - .set macro - .set reorder - - .end Test10_LoadStore - .align 2 - .globl Test11_AddSub - .ent Test11_AddSub -Test11_AddSub: - .frame $sp,120,$31 # vars= 80, regs= 5/0, args= 16, gp= 0 - .mask 0x800f0000,-8 - .fmask 0x00000000,0 - addiu $sp,$sp,-120 - li $2,-1431699456 # 0xffffffffaaaa0000 - sw $19,108($sp) - sw $18,104($sp) - sw $16,96($sp) - sw $31,112($sp) - sw $17,100($sp) - ori $16,$2,0xaaaa - move $19,$0 - move $4,$0 - addiu $18,$sp,16 -$L92: - move $2,$18 - li $6,19 # 0x13 -$L85: - addiu $6,$6,-1 - sw $16,0($2) - .set noreorder - .set nomacro - bgez $6,$L85 - addiu $2,$2,4 - .set macro - .set reorder - - xor $2,$16,$4 - addiu $17,$4,1 - addiu $2,$2,-1 - move $5,$17 - addiu $6,$sp,16 - li $7,20 # 0x14 - .set noreorder - .set nomacro - jal fibonacci - sll $16,$2,1 - .set macro - .set reorder - - li $7,2 # 0x2 - addiu $5,$18,8 - .set noreorder - .set nomacro - j $L90 - li $6,17 # 0x11 - .set macro - .set reorder - -$L88: - bltz $6,$L100 -$L90: - lw $2,0($5) - lw $3,-4($5) - lw $4,-8($5) - subu $2,$2,$3 - addiu $6,$6,-1 - .set noreorder - .set nomacro - bne $4,$2,$L88 - addiu $5,$5,4 - .set macro - .set reorder - - .set noreorder - .set nomacro - bgez $6,$L90 - addiu $7,$7,1 - .set macro - .set reorder - -$L100: - li $6,20 # 0x14 - beq $7,$6,$L101 -$L81: - slt $2,$17,3 - .set noreorder - .set nomacro - bne $2,$0,$L92 - move $4,$17 - .set macro - .set reorder - - li $2,3 # 0x3 - .set noreorder - .set nomacro - bne $19,$2,$L102 - move $3,$0 - .set macro - .set reorder - - lw $31,112($sp) - lw $19,108($sp) - lw $18,104($sp) - lw $17,100($sp) - lw $16,96($sp) - move $2,$3 - .set noreorder - .set nomacro - j $31 - addiu $sp,$sp,120 - .set macro - .set reorder - -$L101: - .set noreorder - .set nomacro - j $L81 - addiu $19,$19,1 - .set macro - .set reorder - -$L102: - li $2,-2147483648 # 0xffffffff80000000 - ori $3,$2,0x11 - lw $31,112($sp) - lw $19,108($sp) - lw $18,104($sp) - lw $17,100($sp) - lw $16,96($sp) - move $2,$3 - .set noreorder - .set nomacro - j $31 - addiu $sp,$sp,120 - .set macro - .set reorder - - .end Test11_AddSub - .align 2 - .globl Test12_MulDiv - .ent Test12_MulDiv -Test12_MulDiv: - .frame $sp,48,$31 # vars= 8, regs= 5/0, args= 16, gp= 0 - .mask 0x800f0000,-8 - .fmask 0x00000000,0 - li $4,426770432 # 0x19700000 - addiu $sp,$sp,-48 - ori $4,$4,0x1031 - sw $19,36($sp) - sw $31,40($sp) - sw $18,32($sp) - sw $17,28($sp) - sw $16,24($sp) - .set noreorder - .set nomacro - jal srand - move $19,$0 - .set macro - .set reorder - - .set noreorder - .set nomacro - j $L111 - li $18,1 # 0x1 - .set macro - .set reorder - -$L109: - beq $4,$0,$L117 -$L111: - .set noreorder - .set nomacro - jal rand - addiu $18,$18,1 - .set macro - .set reorder - - sll $3,$2,16 - sll $2,$2,8 - .set noreorder - .set nomacro - jal rand - xor $16,$2,$3 - .set macro - .set reorder - - .set noreorder - .set nomacro - jal rand - xor $17,$2,$16 - .set macro - .set reorder - - sll $3,$2,16 - sll $2,$2,8 - .set noreorder - .set nomacro - jal rand - xor $16,$2,$3 - .set macro - .set reorder - - xor $16,$2,$16 - addiu $4,$sp,16 - move $5,$17 - .set noreorder - .set nomacro - jal div - move $6,$16 - .set macro - .set reorder - - lw $3,16($sp) - lw $2,20($sp) - mult $3,$16 - mflo $3 - addu $2,$2,$3 - .set noreorder - .set nomacro - beq $2,$17,$L109 - slt $4,$18,1000 - .set macro - .set reorder - - li $2,-2147483648 # 0xffffffff80000000 - ori $2,$2,0x12 -$L103: - lw $31,40($sp) - lw $19,36($sp) - lw $18,32($sp) - lw $17,28($sp) - lw $16,24($sp) - .set noreorder - .set nomacro - j $31 - addiu $sp,$sp,48 - .set macro - .set reorder - -$L117: - addiu $19,$19,1 - slt $2,$19,100 - .set noreorder - .set nomacro - bne $2,$0,$L111 - li $18,1 # 0x1 - .set macro - .set reorder - - .set noreorder - .set nomacro - j $L103 - move $2,$0 - .set macro - .set reorder - - .end Test12_MulDiv - .section .rodata.str1.4 - .align 2 -$LC13: - .ascii "Iteration %d: Passed\r\n\000" - .align 2 -$LC14: - .ascii "Iteration \000" - .align 2 -$LC15: - .ascii ": Passed\r\n\000" - .align 2 -$LC16: - .ascii ":\000" - .align 2 -$LC17: - .ascii "Failed with error \000" - .align 2 -$LC18: - .ascii " \r\n\000" - .text - .align 2 - .globl main - .ent main -main: - .frame $sp,48,$31 # vars= 8, regs= 5/0, args= 16, gp= 0 - .mask 0x800f0000,-8 - .fmask 0x00000000,0 - li $3,-2147483648 # 0xffffffff80000000 - li $2,13 - ori $3,$3,0x9 - addiu $sp,$sp,-48 - sb $2,0($3) - sw $19,36($sp) - sw $18,32($sp) - sw $17,28($sp) - sw $31,40($sp) - .set noreorder - .set nomacro - jal PrintCPUinfo - sw $16,24($sp) - .set macro - .set reorder - - li $2,1073676288 # 0x3fff0000 - ori $19,$2,0xffff - li $18,-2147483648 # 0xffffffff80000000 - .set noreorder - .set nomacro - j $L119 - move $17,$0 - .set macro - .set reorder - -$L124: - jal Test11_AddSub - .set noreorder - .set nomacro - bltz $2,$L120 - move $16,$2 - .set macro - .set reorder - - jal Test12_MulDiv - move $16,$2 - la $4,$LC13 - .set noreorder - .set nomacro - bltz $2,$L120 - move $5,$17 - .set macro - .set reorder - - .set noreorder - .set nomacro - jal printf - addiu $17,$17,1 - .set macro - .set reorder - - la $4,$LC14 - jal sputs - .set noreorder - .set nomacro - jal print_word - move $4,$17 - .set macro - .set reorder - - la $4,$LC15 - .set noreorder - .set nomacro - jal sputs - addiu $17,$17,1 - .set macro - .set reorder - - .set noreorder - .set nomacro - jal time - move $4,$0 - .set macro - .set reorder - - addiu $4,$sp,16 - .set noreorder - .set nomacro - jal gmtime - sw $2,16($sp) - .set macro - .set reorder - - lb $4,8($2) - .set noreorder - .set nomacro - jal print_byte - move $16,$2 - .set macro - .set reorder - - la $4,$LC16 - jal sputs - lb $4,4($16) - jal print_byte - la $4,$LC16 - jal sputs - lb $4,0($16) - jal print_byte - la $4,$LC9 - jal sputs -$L119: - and $2,$17,$19 - sw $2,0($18) - jal Test10_LoadStore - .set noreorder - .set nomacro - bgez $2,$L124 - move $16,$2 - .set macro - .set reorder - -$L120: - li $2,1073741824 # 0x40000000 - or $2,$17,$2 - la $4,$LC17 - sw $2,0($18) - jal sputs - .set noreorder - .set nomacro - jal print_word - move $4,$16 - .set macro - .set reorder - - la $4,$LC18 - jal sputs - lw $31,40($sp) - lw $19,36($sp) - lw $18,32($sp) - lw $17,28($sp) - lw $16,24($sp) - li $2,1 # 0x1 - .set noreorder - .set nomacro - j $31 - addiu $sp,$sp,48 - .set macro - .set reorder - - .end main diff --git a/lib/CPUs/MIPS/sim/asm/utils.c b/lib/CPUs/MIPS/sim/asm/utils.c deleted file mode 100644 index b704173..0000000 --- a/lib/CPUs/MIPS/sim/asm/utils.c +++ /dev/null @@ -1,179 +0,0 @@ -#include -#include -#include -#include - -char readchar(void) -{ - volatile char *pUART_stat = (char*)0x80000008; - volatile char *pUART_data = (char*)0x80000004; - - while(!(0x10 & *pUART_stat)); - - return *pUART_data; -} - -void writechar(char c) -{ - volatile char *pUART_stat = (char*)0x80000008; - volatile char *pUART_data = (char*)0x80000004; - - while((0x02 & *pUART_stat) != 0); - - *pUART_data = c; -} - -clock_t times(struct tms *buffer) -{ - volatile long *pReg_usec = (long*)0x80000010; - volatile long *pReg_sec = (long*)0x80000014; - long sec; - - sec = *pReg_sec; - - if (buffer) - { - buffer->tms_utime = sec; - buffer->tms_stime = 0; - buffer->tms_cutime = 0; - buffer->tms_cstime = 0; - } - - return (clock_t)sec; -} - -int gettimeofday(struct timeval *tp, void *tzp) -{ - volatile long *pReg_usec = (long*)0x80000010; - volatile long *pReg_sec = (long*)0x80000014; - - if (tp) - { - tp->tv_sec = *pReg_sec; - tp->tv_usec = *pReg_usec; - } - - return 0; -} - -int settimeofday(const struct timeval *tp, const struct timezone *tzp) -{ - volatile long *pReg_usec = (long*)0x80000010; - volatile long *pReg_sec = (long*)0x80000014; - div_t res; - - res = div(tp->tv_usec, 1E6); - - if (tp) - { - *pReg_usec = res.rem; - *pReg_sec = tp->tv_sec + res.quot; - } - - return 0; -} - -caddr_t sbrk(int incr) -{ - extern char end; - static char *heap_end; - char *prev_heap_end; - - if (heap_end == 0) - heap_end = &end; - - prev_heap_end = heap_end; -// if (heap_end + incr > stack_ptr) -// { -// _write(1, "Heap and stack collision\n", 25); -// abort(); -// } - - heap_end += incr; - return (caddr_t) prev_heap_end; -} - -int fstat(int file, struct stat *st) -{ - st->st_mode = S_IFCHR; - return 0; -} - -int lseek(int file, int ptr, int dir) -{ - return 0; -} - -int open(const char *name, int flags, int mode) -{ - return -1; -} - -int close(int file) -{ - return -1; -} - -int read(int file, char *ptr, int len) -{ - return 0; -} - -int write(int file, char *ptr, int len) -{ - int i; - - for (i=0; i < len; i++) - writechar(*ptr++); - - return i; -} - -int isatty(int file) -{ - return 1; -} - -int sputs(char *pStr) -{ - char *start; - start = pStr; - - while(*pStr) - writechar(*(pStr++)); - - return pStr - start; -} - -void print_byte(char byte) -{ - int i; - unsigned char c, nibble; - - for (i=0; i < 2; i++) - { - nibble = (char)((byte >> 4) & 0xF); - byte <<= 4; - - if (nibble < 10) - c = nibble + '0'; - else - c = nibble + 'A' - 10; - - writechar(c); - } -} - -void print_word(int word) -{ - int i; - unsigned char c, nibble; - - for (i=0; i < 4; i++) - { - c = (char) (word >> 24); - print_byte(c); - word <<= 8; - } -} - diff --git a/lib/CPUs/MIPS/sim/asm/utils.h b/lib/CPUs/MIPS/sim/asm/utils.h deleted file mode 100644 index aab48c4..0000000 --- a/lib/CPUs/MIPS/sim/asm/utils.h +++ /dev/null @@ -1,12 +0,0 @@ -#ifndef UTILS_H -#define UTILS_H - -char readchar(void); -void writechar(char c); -int write(int file, char *ptr, int len); -int sputs(char *pStr); -void print_byte(char byte); -void print_word(int word); - -#endif // UTILS_H - diff --git a/lib/CPUs/MIPS/sim/asm/utils.s b/lib/CPUs/MIPS/sim/asm/utils.s deleted file mode 100644 index 56b6d8c..0000000 --- a/lib/CPUs/MIPS/sim/asm/utils.s +++ /dev/null @@ -1,184 +0,0 @@ - .file 1 "utils.c" - .set nobopt - .text - .align 2 - .globl sein - .ent sein -sein: - .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 - .mask 0x00000000,0 - .fmask 0x00000000,0 - li $2,-2147483648 # 0xffffffff80000000 - ori $4,$2,0x4 - ori $3,$2,0x8 -$L2: - lbu $2,0($3) - andi $2,$2,0x10 - beq $2,$0,$L2 - lbu $2,0($4) - sll $2,$2,24 - .set noreorder - .set nomacro - j $31 - sra $2,$2,24 - .set macro - .set reorder - - .end sein - .align 2 - .globl saus - .ent saus -saus: - .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 - .mask 0x00000000,0 - .fmask 0x00000000,0 - li $2,-2147483648 # 0xffffffff80000000 - sll $4,$4,24 - sra $4,$4,24 - ori $5,$2,0x4 - ori $3,$2,0x8 -$L6: - lbu $2,0($3) - andi $2,$2,0x2 - bne $2,$0,$L6 - sb $4,0($5) - j $31 - .end saus - .align 2 - .globl sputs - .ent sputs -sputs: - .frame $sp,32,$31 # vars= 0, regs= 3/0, args= 16, gp= 0 - .mask 0x80030000,-8 - .fmask 0x00000000,0 - addiu $sp,$sp,-32 - sw $17,20($sp) - sw $16,16($sp) - sw $31,24($sp) - move $16,$4 - lb $4,0($4) - .set noreorder - .set nomacro - j $L14 - move $17,$16 - .set macro - .set reorder - -$L15: - .set noreorder - .set nomacro - jal saus - addiu $16,$16,1 - .set macro - .set reorder - - lb $4,0($16) -$L14: - .set noreorder - .set nomacro - bne $4,$0,$L15 - subu $2,$16,$17 - .set macro - .set reorder - - lw $31,24($sp) - lw $17,20($sp) - lw $16,16($sp) - .set noreorder - .set nomacro - j $31 - addiu $sp,$sp,32 - .set macro - .set reorder - - .end sputs - .align 2 - .globl print_byte - .ent print_byte -print_byte: - .frame $sp,32,$31 # vars= 0, regs= 3/0, args= 16, gp= 0 - .mask 0x80030000,-8 - .fmask 0x00000000,0 - addiu $sp,$sp,-32 - sw $16,16($sp) - sll $16,$4,24 - sw $17,20($sp) - sw $31,24($sp) - sra $16,$16,24 - li $17,1 # 0x1 - sra $2,$16,4 -$L25: - andi $5,$2,0xf - sll $2,$16,4 - sll $16,$2,24 - sltu $3,$5,10 - addiu $17,$17,-1 - sra $16,$16,24 - .set noreorder - .set nomacro - bne $3,$0,$L21 - addiu $4,$5,48 - .set macro - .set reorder - - addiu $4,$5,55 -$L21: - jal saus - .set noreorder - .set nomacro - bgez $17,$L25 - sra $2,$16,4 - .set macro - .set reorder - - lw $31,24($sp) - lw $17,20($sp) - lw $16,16($sp) - .set noreorder - .set nomacro - j $31 - addiu $sp,$sp,32 - .set macro - .set reorder - - .end print_byte - .align 2 - .globl print_word - .ent print_word -print_word: - .frame $sp,32,$31 # vars= 0, regs= 3/0, args= 16, gp= 0 - .mask 0x80030000,-8 - .fmask 0x00000000,0 - addiu $sp,$sp,-32 - sw $17,20($sp) - sw $16,16($sp) - sw $31,24($sp) - move $16,$4 - li $17,3 # 0x3 -$L30: - sra $4,$16,24 - .set noreorder - .set nomacro - jal print_byte - addiu $17,$17,-1 - .set macro - .set reorder - - .set noreorder - .set nomacro - bgez $17,$L30 - sll $16,$16,8 - .set macro - .set reorder - - lw $31,24($sp) - lw $17,20($sp) - lw $16,16($sp) - .set noreorder - .set nomacro - j $31 - addiu $sp,$sp,32 - .set macro - .set reorder - - .end print_word diff --git a/lib/CPUs/MIPS/sim/hello.flash.bin b/lib/CPUs/MIPS/sim/hello.flash.bin deleted file mode 100644 index cd652ef12f82962bcc1fd2a1770fa71ef9360112..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 7936 zcmeHLZEPIX6+OE;x}}q~Lv7>~3!FBHs9ig|#1SU3 zybE;^RacHnEjo=|DL;_fABz)88k|fhl)5S@76p__Mg0&`)2c!iKiafHCF++fO1nLG zcE_Fsdqi8L{s2qQGw+>y?>qOs`|f?Sx8K&&2Ec%i{~OspXn#g95e@{KgRocNgXaDJ z-`{tBxcS8kAH_Ud9R{or2CW9{w=|@!FfvvI_gbwuU`^mlmWeN07*Y(RDhwEF42-Nb z^oyy$7z)ayOyKtk~jhoC~+-&wCYWAbe+>4mG5A9|O zaWjpr<`A}-!`N<)pu@~zhnYvhoW!l>Fqsgq{F}(&UXb78OG@B7@GF!3PH1SCj zl(9E6HEuLeHpKn}K4Av&akCD(iIHy_L8Jm)lH^75Rq=xLd!X700QRRsIJfy{#f58R zEQp1GgZT=_pv z31U;krie{ZmhTJn@!V!jLG|Q@@Fo~aLf*{{6XdQOJ-~OF>q`7v#1#*GmUz$uf1Y@? z2mVvy(;oP5i62`5zmn&hlyiJqv;T zCy77ofzJ`od*J7ZPk7)Lh);Up7m1rI;7(3Z5I8DleLNJvB4uU#V;GIX@F#K`li_@* z7J6uq*)DAgCV9`v4QgoRd}iCE*m|TC5f4JO=Men{>R<&vj!lF3LzL4s!yknIXbtoF8YUgAPXZ9bJ`B@uSvRHK%4S7I; zy6Nx5+Io?d+^-W|DgOsC-dZ8LoHHMyD~-u;X)Q9dPHkHxFOd@-3Tq7I>-0Q#ly;q3 z5@ap;mA|}pJ|(PZioaN#h)RKRv_ zfdHS_q(Jlne7bdgCEYr~fUc$e7kQDb;(erwH<2snTupB^+v^bE`RJTg0tni3iT&02 z*m2FXxx`0g4VTa5`Bk|u(cdLGH}7l6Tl7}oq>5i9`{Q-*)%Hqu)|Kav(J!%s!W!NO zU*g`3o7H$Fu3%;sc+uV`*zZT|_i7yH_)DhjPY@?&LERwzt45N#x0!k*&z;?Gu18+Y zYin>Z;1BzG2Cu~+*71fnzi|zkLTTo(doj-(SB=7~!WLw! zEjhz=JkR$~MegUoah_+&=L7yL$8HFX;O%0{zJF3@N-f_Z80UT*;d%_(TpYWiSH-g+w&grH z_FiWEh%ZtPB&MA^z1;652kVms+{k#=r|01(zLxL8akV>sE7wQo_g#r+SG)>qxi)La zEy%cU9v9sjJjwIZwn<`D`VPm^`~L72b(F6!&;EtJ>#E^jZLXE{f%CI((jBvl8wJHj+@j;+qN)SS^g)pH;{{<%W+kWTSiwIki>JF2BPX z%el2Nz*ziLT#w4SS08>zUC+G8eC@+4 z#I8U6R`L8&+zGF{$!|OLBu<cDu&D;Oldr7xJG>L%(VA6bMf|g4 zEKgdzZDZ4d!)QZ7pSL!-}#q-5Pt)Z+M}N(2W>vkz~2Mv_}hTW z-w3MtTY+uAP(YaL=V1+jGp#+jEC_Ptt^UVMF3p2ny&qdUWF4u61>psOb z=I;{EO>v!>o1dNHI=}0CKf?HwSd)79YH`qxCFZ2d{3+$DnKLhz_tjaaXJnlxfnVC| zt=Tc)J`3IC_qhs&760T+RFrGHoC!HU#UiQFH@8mT6*||gpySl4^{7bbj7bF({GH|n ztA}$L$tU6{RIpZ_U~WCa^Bp)UwMpt-HHfiJNS$)>h}5dm9s8`cXOGlpmAX&!J;~Z! zvrYK%oSosF`i$gS@qHgTo;oFU?S-jRr=+HpaO&B1m2w@F-%|W2uqJ=SuE{F%t<>HM zXV^ym`4yQ}w(l0Zp+cUO0hyMJfqz`<-TGn&1n z3R+Z)Jd_zd+)}o!wP}%oT+5OzEv7{tjJo>m?6saO!6Mj2fee%1{#V$&z;hF1EYAm_>2~xU+|`KC%aQJV+g0M?T%zb@OLBcX1Th-FfqEeY+@=$wu0?wUnOQ z%g>JTb4TeJi;SlM2zY_Fa6$fHYmbPgZR zW+E+eO!4{5*uh)`ke zW9w(z$ChRrX3MdSu|3R|XPaP~WaE$7#x&b8wgTHpwzF(=Z1ZgA*?!J;fo*~9BHJal zMK)}N5oA-@LTnnFP!TTnlmFgqfYE&&j1z3mnAdZ}vEe23K4ZSJy{p?_eJWmi|L@*> Uy#iOg&vSfe?!y)Mpsm2a0f^t)^#A|> diff --git a/lib/CPUs/MIPS/sim/tb_mips_muldiv.fdo b/lib/CPUs/MIPS/sim/tb_mips_muldiv.fdo deleted file mode 100644 index efb8705..0000000 --- a/lib/CPUs/MIPS/sim/tb_mips_muldiv.fdo +++ /dev/null @@ -1,15 +0,0 @@ -## NOTE: Do not edit this file. -## -vlib work -vcom -explicit -93 "../../../PCK_FIO-1.16/PCK_FIO.vhd" -vcom -explicit -93 "../src/core/mips_types.vhd" -vcom -explicit -93 "../src/core/mips_instr.vhd" -vcom -explicit -93 "../src/core/mips_muldiv.vhd" -vcom -explicit -93 "../src/tb_mips_muldiv.vhd" -vsim -t 1ps -lib work tb_mips_muldiv -do {tb_mips_muldiv.wdo} -view wave - -view structure -view signals -run 8ms diff --git a/lib/CPUs/MIPS/sim/tb_mips_muldiv.wdo b/lib/CPUs/MIPS/sim/tb_mips_muldiv.wdo deleted file mode 100644 index 046f859..0000000 --- a/lib/CPUs/MIPS/sim/tb_mips_muldiv.wdo +++ /dev/null @@ -1,78 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_mips_muldiv/rst -add wave -noupdate -format Logic /tb_mips_muldiv/clk -add wave -noupdate -format Logic /tb_mips_muldiv/mul_divn -add wave -noupdate -format Logic /tb_mips_muldiv/start -add wave -noupdate -format Logic /tb_mips_muldiv/busy -add wave -noupdate -format Logic /tb_mips_muldiv/s_un -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/ref_hi -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/din_hi -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/din_lo -add wave -noupdate -format Logic /tb_mips_muldiv/hilo_sel -add wave -noupdate -format Logic /tb_mips_muldiv/hilo_we -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/dout -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/ref_result -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/md_result -add wave -noupdate -format Logic /tb_mips_muldiv/check -add wave -noupdate -format Logic /tb_mips_muldiv/uut/pre_sum_vld -add wave -noupdate -format Logic /tb_mips_muldiv/uut/mul_en -add wave -noupdate -format Logic /tb_mips_muldiv/uut/sum_en -add wave -noupdate -divider FSM -add wave -noupdate -format Literal /tb_mips_muldiv/uut/cycle_cnt -add wave -noupdate -format Logic /tb_mips_muldiv/uut/cycle_cnt_load -add wave -noupdate -format Literal /tb_mips_muldiv/uut/cycle_cnt_preset -add wave -noupdate -format Literal /tb_mips_muldiv/uut/s -add wave -noupdate -format Literal /tb_mips_muldiv/uut/sn -add wave -noupdate -divider {Multiplier internals} -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_muldiv/uut/pprod -add wave -noupdate -format Literal /tb_mips_muldiv/uut/ppadd_cyi -add wave -noupdate -format Literal /tb_mips_muldiv/uut/ppadd_cyo -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/ppadd_op1 -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/ppadd_op2 -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/ppadd_res -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/pp_op2 -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/pp_op2_r -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/add_op1 -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/add_op2 -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/add_res -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/pp_reg -add wave -noupdate -divider {Divider internals} -add wave -noupdate -format Logic /tb_mips_muldiv/busy -add wave -noupdate -format Logic /tb_mips_muldiv/s_un -add wave -noupdate -format Logic /tb_mips_muldiv/uut/div_start -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/din_hi -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/din_lo -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/result -add wave -noupdate -format Logic /tb_mips_muldiv/uut/div_add_cyi -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/div_add_op1 -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/div_add_op2 -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/div_add_res -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/div_m -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/div_m_n -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/div_a -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/div_q -add wave -noupdate -format Logic /tb_mips_muldiv/uut/div_qbit -add wave -noupdate -format Logic /tb_mips_muldiv/uut/div_en -add wave -noupdate -divider FSM -add wave -noupdate -format Literal /tb_mips_muldiv/uut/cycle_cnt -add wave -noupdate -format Logic /tb_mips_muldiv/uut/cycle_cnt_load -add wave -noupdate -format Literal /tb_mips_muldiv/uut/cycle_cnt_preset -add wave -noupdate -format Literal /tb_mips_muldiv/uut/s -add wave -noupdate -format Literal /tb_mips_muldiv/uut/sn -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {7735999838 ps} 0} {{Cursor 2} {512321 ps} 0} -configure wave -namecolwidth 149 -configure wave -valuecolwidth 171 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 100 -configure wave -griddelta 40 -configure wave -timeline 1 -update -WaveRestoreZoom {0 ps} {8400 us} diff --git a/lib/CPUs/MIPS/sim/tb_mips_sys.fdo b/lib/CPUs/MIPS/sim/tb_mips_sys.fdo deleted file mode 100644 index bca6968..0000000 --- a/lib/CPUs/MIPS/sim/tb_mips_sys.fdo +++ /dev/null @@ -1,42 +0,0 @@ -vlib work -vcom -explicit -93 "../src/dpram_2w2r.vhd" -vcom -explicit -93 "../src/dpram_1w1r.vhd" -vcom -explicit -93 "../src/fifo_ctrl_pkg.vhd" -vcom -explicit -93 "../src/gray_counter.vhd" -vcom -explicit -93 "../src/fifo_sync_ctrl.vhd" -vcom -explicit -93 "../src/fifo_sync.vhd" -vcom -explicit -93 "../src/fifo_async_ctrl.vhd" -vcom -explicit -93 "../src/fifo_async.vhd" -vcom -explicit -93 "../src/bbfifo_16x8.vhd" -vcom -explicit -93 "../src/kcuart_rx.vhd" -vcom -explicit -93 "../src/kcuart_tx.vhd" -vcom -explicit -93 "../src/uart_rx.vhd" -vcom -explicit -93 "../src/uart_tx.vhd" -vcom -explicit -93 "../src/uart_wb.vhd" -vcom -explicit -93 "../src/gpio_wb.vhd" -vcom -explicit -93 "../src/async_types.vhd" -vcom -explicit -93 "../src/async_port_wb.vhd" -vcom -explicit -93 "../src/async_defs.vhd" -vcom -explicit -93 "../src/bootloader.ROM.vhd" -vcom -explicit -93 "../src/rom_wb.vhd" -vcom -explicit -93 "../src/mips_types.vhd" -vcom -explicit -93 "../src/mips_instr.vhd" -vcom -explicit -93 "../src/mips_reg.vhd" -vcom -explicit -93 "../src/mips_shifter.vhd" -vcom -explicit -93 "../src/mips_alu.vhd" -vcom -explicit -93 "../src/mips_muldiv.vhd" -vcom -explicit -93 "../src/mips_cop.vhd" -vcom -explicit -93 "../src/mips_icache.vhd" -vcom -explicit -93 "../src/mips_dcache.vhd" -vcom -explicit -93 "../src/mips_biu.vhd" -vcom -explicit -93 "../src/mips_bcu.vhd" -vcom -explicit -93 "../src/mips_pipeline.vhd" -vcom -explicit -93 "../src/mips_top.vhd" -vcom -explicit -93 "../src/mips_sys.vhd" -vcom -explicit -93 "../src/tb_mips_sys.vhd" -vsim -t 1ps -lib work tb_mips_sys -do {tb_mips_sys.wdo} -view wave -view structure -view signals -run 3000us diff --git a/lib/CPUs/MIPS/sim/tb_mips_sys.wdo b/lib/CPUs/MIPS/sim/tb_mips_sys.wdo deleted file mode 100644 index 4d0670a..0000000 --- a/lib/CPUs/MIPS/sim/tb_mips_sys.wdo +++ /dev/null @@ -1,45 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -divider {MIPS top} -add wave -noupdate -format Literal /tb_mips_sys/debug -add wave -noupdate -format Logic /tb_mips_sys/rst -add wave -noupdate -format Logic /tb_mips_sys/clk -add wave -noupdate -divider Flash -add wave -noupdate -format Logic /tb_mips_sys/clk -add wave -noupdate -format Logic /tb_mips_sys/flash_cs_n -add wave -noupdate -format Logic /tb_mips_sys/flash_oe_n -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/flash_a -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/flash_d -add wave -noupdate -divider SRAM -add wave -noupdate -format Logic /tb_mips_sys/clk -add wave -noupdate -format Logic /tb_mips_sys/sram_cs_n -add wave -noupdate -format Literal /tb_mips_sys/sram_wr_n -add wave -noupdate -format Logic /tb_mips_sys/sram_oe_n -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sram_a -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sram_d -add wave -noupdate -divider GPIO -add wave -noupdate -format Logic /tb_mips_sys/clk -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/gpo0 -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/gpo1 -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/gpi0 -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/gpi1 -add wave -noupdate -divider UART -add wave -noupdate -format Logic /tb_mips_sys/clk -add wave -noupdate -format Logic /tb_mips_sys/rx -add wave -noupdate -format Logic /tb_mips_sys/tx -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {1165707237 ps} 0} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 100 -configure wave -griddelta 40 -configure wave -timeline 1 -update -WaveRestoreZoom {0 ps} {3150 us} diff --git a/lib/CPUs/MIPS/sim/tb_mips_top.fdo b/lib/CPUs/MIPS/sim/tb_mips_top.fdo deleted file mode 100644 index 1f1298b..0000000 --- a/lib/CPUs/MIPS/sim/tb_mips_top.fdo +++ /dev/null @@ -1,61 +0,0 @@ -## NOTE: Do not edit this file. -## -vlib work - -# RAMS -vcom -explicit -93 "../../../rams/dpram_2w2r2c_ra_sim.vhd" -vcom -explicit -93 "../../../rams/dpram_1w1r2c_ra_sim.vhd" -vcom -explicit -93 "../../../rams/dpram_2w2r2c_ro_sim.vhd" -vcom -explicit -93 "../../../rams/dpram_1w1r2c_ro_sim.vhd" - - -# FIFOS -vcom -explicit -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd" -vcom -explicit -93 "../../../FIFO/src/gray_counter.vhd" -vcom -explicit -93 "../../../FIFO/src/fifo_sync_ctrl.vhd" -vcom -explicit -93 "../../../FIFO/src/fifo_sync.vhd" -vcom -explicit -93 "../../../FIFO/src/fifo_async_ctrl.vhd" -vcom -explicit -93 "../../../FIFO/src/fifo_async.vhd" - -# UART -#vcom -explicit -93 "../../../uart/bbfifo_16x8.vhd" -#vcom -explicit -93 "../../../uart/kcuart_rx.vhd" -#vcom -explicit -93 "../../../uart/kcuart_tx.vhd" -#vcom -explicit -93 "../../../uart/uart_rx.vhd" -#vcom -explicit -93 "../../../uart/uart_tx.vhd" -vcom -explicit -93 "../../../uart/uart_wb.vhd" - -# GPIO -vcom -explicit -93 "../../../misc/gpio_wb.vhd" - -# Async port -vcom -explicit -93 "../../../misc/async_types.vhd" -vcom -explicit -93 "../../../misc/async_port_wb.vhd" -vcom -explicit -93 "../src/async_defs.vhd" - -# ROM -vcom -explicit -93 "../src/bootloader.ROM.vhd" -vcom -explicit -93 "../../../misc/rom_wb.vhd" - -# MIPS -vcom -explicit -93 "../src/core/mips_types.vhd" -vcom -explicit -93 "../src/core/mips_instr.vhd" -vcom -explicit -93 "../src/core/mips_reg.vhd" -vcom -explicit -93 "../src/core/mips_shifter.vhd" -vcom -explicit -93 "../src/core/mips_alu.vhd" -vcom -explicit -93 "../src/core/mips_muldiv.vhd" -vcom -explicit -93 "../src/core/mips_cop.vhd" -vcom -explicit -93 "../src/core/mips_icache.vhd" -vcom -explicit -93 "../src/core/mips_dcache.vhd" -vcom -explicit -93 "../src/core/mips_biu.vhd" -vcom -explicit -93 "../src/core/mips_bcu.vhd" -vcom -explicit -93 "../src/core/mips_pipeline.vhd" -vcom -explicit -93 "../src/core/mips_top.vhd" - -vcom -explicit -93 "../src/tb_mips_top.vhd" -vsim -t 1ps -lib work tb_mips_top -do {tb_mips_top.wdo} -view wave -view structure -view signals -run 1500us diff --git a/lib/CPUs/MIPS/sim/tb_mips_top.wdo b/lib/CPUs/MIPS/sim/tb_mips_top.wdo deleted file mode 100644 index 12b16c3..0000000 --- a/lib/CPUs/MIPS/sim/tb_mips_top.wdo +++ /dev/null @@ -1,223 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -divider {TOP interface} -add wave -noupdate -format Logic /tb_mips_top/nmi -add wave -noupdate -format Logic /tb_mips_top/rst -add wave -noupdate -format Logic /tb_mips_top/clk -add wave -noupdate -format Literal /tb_mips_top/debug -add wave -noupdate -format Logic /tb_mips_top/stb_o -add wave -noupdate -format Logic /tb_mips_top/ack_i -add wave -noupdate -format Logic /tb_mips_top/srdy_i -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/addr_o -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dat_i -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dat_o -add wave -noupdate -format Logic /tb_mips_top/we_o -add wave -noupdate -format Literal /tb_mips_top/sel_o -add wave -noupdate -format Logic /tb_mips_top/cyc_o -add wave -noupdate -format Logic /tb_mips_top/mrdy_o -add wave -noupdate -format Literal /tb_mips_top/int -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/inst_shifter/dout -add wave -noupdate -format Logic /tb_mips_top/uut/biu_rst -add wave -noupdate -format Logic /tb_mips_top/uut/cpu_rst -add wave -noupdate -format Logic /tb_mips_top/uut/cpu_run -add wave -noupdate -divider BIU -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/bout_fifo_din -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/bout_fifo_dout -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/bout_fifo_re -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/bout_fifo_we -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/bout_fifo_full -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/bout_fifo_empty -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/bout_rdy -add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/bus_timeout_cnt -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/bus_timeout -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/cpu_imem_err -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/cpu_imem_rdy -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/cpu_imem_en -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/cpu_imem_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/cpu_imem_din -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/cpu_dmem_err -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/cpu_dmem_rdy -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/cpu_dmem_en -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/cpu_dmem_we -add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/cpu_dmem_be -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/cpu_dmem_dout -add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/cpu_dmem_din -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/cpu_dmem_addr -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/bus_idle -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/busy -add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/dmem_be -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/bin_fifo_din -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/bin_fifo_dout -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/bin_fifo_re -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/bin_fifo_we -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/bin_fifo_full -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/bin_fifo_empty -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/write_fifo_din -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/write_fifo_dout -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/write_fifo_re -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/write_fifo_we -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/write_fifo_full -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/write_fifo_empty -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/read_cycle -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/dcached -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/dcache_en2 -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/dcache_en -add wave -noupdate -divider {External components} -add wave -noupdate -format Logic /tb_mips_top/clk -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpi_0 -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpo_0 -add wave -noupdate -format Logic /tb_mips_top/inst_uart/tx_complete -add wave -noupdate -format Logic /tb_mips_top/inst_uart/tx_empty -add wave -noupdate -format Literal /tb_mips_top/inst_uart/uart_status_port -add wave -noupdate -format Logic /tb_mips_top/rx -add wave -noupdate -format Logic /tb_mips_top/tx -add wave -noupdate -divider {Interrupt Timer} -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/inst_gpio/timer_cnt -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/inst_gpio/timer_cmp -add wave -noupdate -format Literal /tb_mips_top/inst_gpio/timer_en -add wave -noupdate -format Literal /tb_mips_top/inst_gpio/timer_inten -add wave -noupdate -format Literal /tb_mips_top/inst_gpio/timer_irq -add wave -noupdate -format Literal /tb_mips_top/inst_gpio/timer_ovl -add wave -noupdate -format Literal /tb_mips_top/inst_gpio/timer_irq_ack -add wave -noupdate -format Literal /tb_mips_top/inst_gpio/timer_cmp_we -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/inst_gpio/reg_data_wr -add wave -noupdate -format Logic /tb_mips_top/clk -add wave -noupdate -format Logic /tb_mips_top/clk -add wave -noupdate -format Literal /tb_mips_top/mem_area -add wave -noupdate -format Literal /tb_mips_top/inst_flash_port/s -add wave -noupdate -format Logic /tb_mips_top/inst_flash_port/ack -add wave -noupdate -format Logic /tb_mips_top/stb_o -add wave -noupdate -format Logic /tb_mips_top/srdy_i -add wave -noupdate -format Logic /tb_mips_top/we_o -add wave -noupdate -format Logic /tb_mips_top/inst_flash_port/we_i_r -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/addr_o -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/inst_flash_port/addr_i_r -add wave -noupdate -format Logic /tb_mips_top/inst_flash_port/page_mode_en -add wave -noupdate -format Logic /tb_mips_top/inst_flash_port/rdy -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/flash_a -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/flash_d -add wave -noupdate -format Logic /tb_mips_top/ack_i -add wave -noupdate -format Logic /tb_mips_top/flash_cs_n -add wave -noupdate -format Logic /tb_mips_top/flash_we_n -add wave -noupdate -format Logic /tb_mips_top/flash_oe_n -add wave -noupdate -format Literal /tb_mips_top/flash_be_n -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/sram_a -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/sram_d -add wave -noupdate -format Logic /tb_mips_top/ack_i -add wave -noupdate -format Logic /tb_mips_top/sram_cs_n -add wave -noupdate -format Literal /tb_mips_top/sram_wr_n -add wave -noupdate -format Logic /tb_mips_top/sram_oe_n -add wave -noupdate -format Literal /tb_mips_top/sram_be_n -add wave -noupdate -format Logic /tb_mips_top/inst_sram_port/page_mode_en_r -add wave -noupdate -format Logic /tb_mips_top/inst_sram_port/do_page_read -add wave -noupdate -format Logic /tb_mips_top/inst_sram_port/rdy -add wave -noupdate -format Literal /tb_mips_top/inst_sram_port/s -add wave -noupdate -divider ALU -add wave -noupdate -format Logic /tb_mips_top/clk -add wave -noupdate -format Literal /tb_mips_top/uut/inst_pipeline/hdu -add wave -noupdate -format Literal /tb_mips_top/uut/inst_pipeline/sdu -add wave -noupdate -divider PC -add wave -noupdate -format Logic /tb_mips_top/clk -add wave -noupdate -format Logic -radix hexadecimal /tb_mips_top/uut/inst_pipeline/ex_stage.ctrl.branch -add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/branch_ce -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/pc -add wave -noupdate -divider COP0 -add wave -noupdate -format Logic /tb_mips_top/uut/inst_cop/ir_en -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/ir -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/test_reg -add wave -noupdate -format Logic /tb_mips_top/uut/inst_cop/test_reg_we -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/icache_info -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/dcache_info -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/cop_pipe_id -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/cop_pipe_ex -add wave -noupdate -format Literal /tb_mips_top/uut/inst_cop/ctrl_in -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/cpu_en -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/cpu_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/cpu_dout -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/cpu_busy -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/ctrl_out -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/epc -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/cause -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/status -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/badvaddr -add wave -noupdate -format Literal /tb_mips_top/uut/inst_cop/eflags -add wave -noupdate -format Logic /tb_mips_top/uut/inst_cop/status_save -add wave -noupdate -format Logic /tb_mips_top/uut/inst_cop/status_rest -add wave -noupdate -format Logic /tb_mips_top/uut/inst_cop/stat_reg_we -add wave -noupdate -format Literal /tb_mips_top/uut/inst_cop/exc_state -add wave -noupdate -divider Pipestages -add wave -noupdate -format Logic /tb_mips_top/clk -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/id_stage -add wave -noupdate -format Logic /tb_mips_top/clk -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/ex_stage -add wave -noupdate -format Logic /tb_mips_top/clk -add wave -noupdate -format Logic -label .stall_all /tb_mips_top/uut/inst_pipeline/sdu.stall_all -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/mem_stage -add wave -noupdate -format Logic /tb_mips_top/clk -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/wb_stage -add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/rst -add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/cpu_run -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/inst_reg_dual/reg_mem -add wave -noupdate -divider I-Cache -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/ctrl -add wave -noupdate -format Logic /tb_mips_top/clk -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/cpu_en -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/cpu_busy -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/tag_match -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/cpu_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/cpu_dout -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/request_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/fill_addr -add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_icache/request_count -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/flush_count -add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_icache/fill_count -add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_icache/s -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/cache_entry_out -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/data_ram_we -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/tag_ram_we -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/inst_tag_ram/ram -add wave -noupdate -divider D-Cache -add wave -noupdate -format Logic /tb_mips_top/clk -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/mrdy_o -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cpu_en -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cpu_busy -add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_be -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cpu_we -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cpu_hit_we -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/instant_raw -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_din -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_dout -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_data_reg -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/request_addr -add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/request_count -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/fill_addr -add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/fill_count -add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/flush_count -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cache_hit -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/tag_match -add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/s -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/dat_i -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/cache_entry_in -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/cache_entry_out -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_data_reg -add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_be_reg -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cpu_we_reg -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/tag_ram_din -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/tag_ram_we -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {Cursor {5877623 ps} 0} -configure wave -namecolwidth 188 -configure wave -valuecolwidth 154 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 100 -configure wave -griddelta 40 -configure wave -timeline 1 -update -WaveRestoreZoom {5846736 ps} {5910641 ps} diff --git a/lib/CPUs/MIPS/sim/tb_mips_top_syn.fdo b/lib/CPUs/MIPS/sim/tb_mips_top_syn.fdo deleted file mode 100644 index 4c72deb..0000000 --- a/lib/CPUs/MIPS/sim/tb_mips_top_syn.fdo +++ /dev/null @@ -1,55 +0,0 @@ -## NOTE: Do not edit this file. -## -vlib work - -# RAMS -vcom -explicit -93 "../../../misc/dpram_2w2r1c_sim.vhd" -vcom -explicit -93 "../../../misc/dpram_2w2r.vhd" -vcom -explicit -93 "../../../misc/dpram_1w2r1c_sim.vhd" -vcom -explicit -93 "../../../misc/dpram_1w1r.vhd" -vcom -explicit -93 "../../../misc/dpram_1w1r1c_sim.vhd" - -vcom -explicit -93 "../../../misc/dpram_1w1r2c_sim.vhd" -vcom -explicit -93 "../../../misc/dpram_2w2r2c_sim.vhd" - - -# FIFOS -vcom -explicit -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd" -vcom -explicit -93 "../../../FIFO/src/gray_counter.vhd" -vcom -explicit -93 "../../../FIFO/src/fifo_sync_ctrl.vhd" -vcom -explicit -93 "../../../FIFO/src/fifo_sync.vhd" -vcom -explicit -93 "../../../FIFO/src/fifo_async_ctrl.vhd" -vcom -explicit -93 "../../../FIFO/src/fifo_async.vhd" - -# UART -vcom -explicit -93 "../../../uart/bbfifo_16x8.vhd" -vcom -explicit -93 "../../../uart/kcuart_rx.vhd" -vcom -explicit -93 "../../../uart/kcuart_tx.vhd" -vcom -explicit -93 "../../../uart/uart_rx.vhd" -vcom -explicit -93 "../../../uart/uart_tx.vhd" -vcom -explicit -93 "../../../uart/uart_wb.vhd" - -# GPIO -vcom -explicit -93 "../../../misc/gpio_wb.vhd" - -# Async port -vcom -explicit -93 "../../../misc/async_types.vhd" -vcom -explicit -93 "../../../misc/async_port_wb.vhd" -vcom -explicit -93 "../src/async_defs.vhd" - -# ROM -vcom -explicit -93 "../src/bootloader.ROM.vhd" -vcom -explicit -93 "../../../misc/rom_wb.vhd" - -# MIPS - -vcom -explicit -93 "../syn/ise101/netgen/synthesis/mips_top_synthesis.vhd" -vcom -explicit -93 "../src/mips_top_syn.vhd" - -vcom -explicit -93 "../src/tb_mips_top.vhd" -vsim -t 1ps -lib work tb_mips_top -do {tb_mips_top_syn.wdo} -view wave -view structure -view signals -run 1500us diff --git a/lib/CPUs/MIPS/sim/tb_mips_top_syn.wdo b/lib/CPUs/MIPS/sim/tb_mips_top_syn.wdo deleted file mode 100644 index 1dde5b7..0000000 --- a/lib/CPUs/MIPS/sim/tb_mips_top_syn.wdo +++ /dev/null @@ -1,104 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -divider {TOP interface} -add wave -noupdate -format Logic /tb_mips_top/nmi -add wave -noupdate -format Logic /tb_mips_top/rst -add wave -noupdate -format Logic /tb_mips_top/clk -add wave -noupdate -format Literal /tb_mips_top/debug -add wave -noupdate -format Logic /tb_mips_top/stb_o -add wave -noupdate -format Logic /tb_mips_top/ack_i -add wave -noupdate -format Logic /tb_mips_top/srdy_i -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/addr_o -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dat_i -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dat_o -add wave -noupdate -format Logic /tb_mips_top/we_o -add wave -noupdate -format Literal /tb_mips_top/sel_o -add wave -noupdate -format Logic /tb_mips_top/cyc_o -add wave -noupdate -format Logic /tb_mips_top/mrdy_o -add wave -noupdate -format Literal /tb_mips_top/int -add wave -noupdate -divider BIU -add wave -noupdate -divider {External components} -add wave -noupdate -format Logic /tb_mips_top/clk -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpo0 -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpo1 -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpi0 -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpi1 -add wave -noupdate -format Logic /tb_mips_top/inst_uart/tx_complete -add wave -noupdate -format Logic /tb_mips_top/inst_uart/tx_empty -add wave -noupdate -format Literal /tb_mips_top/inst_uart/uart_status_port -add wave -noupdate -format Logic /tb_mips_top/rx -add wave -noupdate -format Logic /tb_mips_top/tx -add wave -noupdate -divider {Interrupt Timer} -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/inst_gpio/timer_cnt -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/inst_gpio/timer_cmp -add wave -noupdate -format Literal /tb_mips_top/inst_gpio/timer_en -add wave -noupdate -format Literal /tb_mips_top/inst_gpio/timer_inten -add wave -noupdate -format Literal /tb_mips_top/inst_gpio/timer_irq -add wave -noupdate -format Literal /tb_mips_top/inst_gpio/timer_ovl -add wave -noupdate -format Literal /tb_mips_top/inst_gpio/timer_irq_ack -add wave -noupdate -format Literal /tb_mips_top/inst_gpio/timer_cmp_we -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/inst_gpio/reg_data_wr -add wave -noupdate -format Logic /tb_mips_top/clk -add wave -noupdate -format Logic /tb_mips_top/clk -add wave -noupdate -format Literal /tb_mips_top/mem_area -add wave -noupdate -format Literal /tb_mips_top/inst_flash_port/s -add wave -noupdate -format Logic /tb_mips_top/inst_flash_port/ack -add wave -noupdate -format Logic /tb_mips_top/stb_o -add wave -noupdate -format Logic /tb_mips_top/srdy_i -add wave -noupdate -format Logic /tb_mips_top/we_o -add wave -noupdate -format Logic /tb_mips_top/inst_flash_port/we_i_r -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/addr_o -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/inst_flash_port/addr_i_r -add wave -noupdate -format Logic /tb_mips_top/inst_flash_port/page_mode_en -add wave -noupdate -format Logic /tb_mips_top/inst_flash_port/rdy -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/flash_a -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/flash_d -add wave -noupdate -format Logic /tb_mips_top/ack_i -add wave -noupdate -format Logic /tb_mips_top/flash_cs_n -add wave -noupdate -format Logic /tb_mips_top/flash_we_n -add wave -noupdate -format Logic /tb_mips_top/flash_oe_n -add wave -noupdate -format Literal /tb_mips_top/flash_be_n -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/sram_a -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/sram_d -add wave -noupdate -format Logic /tb_mips_top/ack_i -add wave -noupdate -format Logic /tb_mips_top/sram_cs_n -add wave -noupdate -format Literal /tb_mips_top/sram_wr_n -add wave -noupdate -format Logic /tb_mips_top/sram_oe_n -add wave -noupdate -format Literal /tb_mips_top/sram_be_n -add wave -noupdate -format Logic /tb_mips_top/inst_sram_port/page_mode_en_r -add wave -noupdate -format Logic /tb_mips_top/inst_sram_port/do_page_read -add wave -noupdate -format Logic /tb_mips_top/inst_sram_port/rdy -add wave -noupdate -format Literal /tb_mips_top/inst_sram_port/s -add wave -noupdate -divider ALU -add wave -noupdate -format Logic /tb_mips_top/clk -add wave -noupdate -divider PC -add wave -noupdate -format Logic /tb_mips_top/clk -add wave -noupdate -divider COP0 -add wave -noupdate -divider Pipestages -add wave -noupdate -format Logic /tb_mips_top/clk -add wave -noupdate -format Logic /tb_mips_top/clk -add wave -noupdate -format Logic /tb_mips_top/clk -add wave -noupdate -format Logic /tb_mips_top/clk -add wave -noupdate -divider I-Cache -add wave -noupdate -format Logic /tb_mips_top/clk -add wave -noupdate -divider D-Cache -add wave -noupdate -format Logic /tb_mips_top/rst -add wave -noupdate -format Logic /tb_mips_top/clk -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpo0 -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpo1 -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {Cursor {521186431 ps} 0} -configure wave -namecolwidth 188 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 100 -configure wave -griddelta 40 -configure wave -timeline 1 -update -WaveRestoreZoom {168108075 ps} {1570099575 ps} diff --git a/lib/CPUs/MIPS/src/async_defs.vhd b/lib/CPUs/MIPS/src/async_defs.vhd deleted file mode 100644 index ecb9f09..0000000 --- a/lib/CPUs/MIPS/src/async_defs.vhd +++ /dev/null @@ -1,68 +0,0 @@ -------------------------------------------------------------------------- --- Project: MIPS System controller --- This file: --- --- Copyright (C) 2008 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -use work.async_types.all; - -package async_defs is - - constant ts_flash : async_timespec_t := - ( - T_leadin => 00.0, - T_pulse_rd => 120.0, - T_pulse_wr => 70.0, - T_leadout => 00.0, - T_release => 40.0, - T_pulse_rst => 80.0, - T_pulse_page_rd => 30.0, - can_page_rd => true, - nbits_page_rd => 4, - pol_cs => '0', - pol_oe => '0', - pol_we => '0', - pol_be => '0', - pol_rst => '0' - ); - - constant ts_sram : async_timespec_t := - ( - T_leadin => 00.0, - T_pulse_rd => 10.0, - T_pulse_wr => 10.0, - T_leadout => 00.0, - T_release => 00.0, - T_pulse_rst => 80.0, - T_pulse_page_rd => 20.0, - can_page_rd => false, - nbits_page_rd => 5, - pol_cs => '0', - pol_oe => '0', - pol_we => '0', - pol_be => '0', - pol_rst => '0' - ); - -end async_defs; diff --git a/lib/CPUs/MIPS/src/bootloader.ROM.vhd b/lib/CPUs/MIPS/src/bootloader.ROM.vhd deleted file mode 100644 index 1b0920c..0000000 --- a/lib/CPUs/MIPS/src/bootloader.ROM.vhd +++ /dev/null @@ -1,2082 +0,0 @@ -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -ENTITY rom IS - Port - ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - addr : in unsigned(31 downto 0); - dout : out unsigned(31 downto 0) - ); -END rom; - -ARCHITECTURE data OF rom IS - - subtype word_t is unsigned(31 downto 0); - type word_array_t is array (0 to 2047) of word_t; - constant word_array : word_array_t := - ( - - X"3C1D8000", -- 00000000 - X"27BDEFF0", -- 00000004 - X"3C1A1040", -- 00000008 - X"375A000C", -- 0000000C - X"409A6000", -- 00000010 - X"241A0000", -- 00000014 - X"409A6800", -- 00000018 - X"401A7800", -- 0000001C - X"00000000", -- 00000020 - X"409AF800", -- 00000024 - X"42000020", -- 00000028 - X"42000022", -- 0000002C - X"3C1ABFC0", -- 00000030 - X"275A005C", -- 00000034 - X"0340F809", -- 00000038 - X"00000000", -- 0000003C - X"3C1ABFC0", -- 00000040 - X"275A114C", -- 00000044 - X"0340F809", -- 00000048 - X"00000000", -- 0000004C - X"00000000", -- 00000050 - X"0BF00014", -- 00000054 - X"00000000", -- 00000058 - X"3C1AA001", -- 0000005C - X"275A0008", -- 00000060 - X"241B000D", -- 00000064 - X"AF5B0000", -- 00000068 - X"03E00008", -- 0000006C - X"00000000", -- 00000070 - X"00000000", -- 00000074 - X"00000000", -- 00000078 - X"00000000", -- 0000007C - X"00000000", -- 00000080 - X"00000000", -- 00000084 - X"00000000", -- 00000088 - X"00000000", -- 0000008C - X"00000000", -- 00000090 - X"00000000", -- 00000094 - X"00000000", -- 00000098 - X"00000000", -- 0000009C - X"00000000", -- 000000A0 - X"00000000", -- 000000A4 - X"00000000", -- 000000A8 - X"00000000", -- 000000AC - X"00000000", -- 000000B0 - X"00000000", -- 000000B4 - X"00000000", -- 000000B8 - X"00000000", -- 000000BC - X"00000000", -- 000000C0 - X"00000000", -- 000000C4 - X"00000000", -- 000000C8 - X"00000000", -- 000000CC - X"00000000", -- 000000D0 - X"00000000", -- 000000D4 - X"00000000", -- 000000D8 - X"00000000", -- 000000DC - X"00000000", -- 000000E0 - X"00000000", -- 000000E4 - X"00000000", -- 000000E8 - X"00000000", -- 000000EC - X"00000000", -- 000000F0 - X"00000000", -- 000000F4 - X"00000000", -- 000000F8 - X"00000000", -- 000000FC - X"00000000", -- 00000100 - X"00000000", -- 00000104 - X"00000000", -- 00000108 - X"00000000", -- 0000010C - X"00000000", -- 00000110 - X"00000000", -- 00000114 - X"00000000", -- 00000118 - X"00000000", -- 0000011C - X"00000000", -- 00000120 - X"00000000", -- 00000124 - X"00000000", -- 00000128 - X"00000000", -- 0000012C - X"00000000", -- 00000130 - X"00000000", -- 00000134 - X"00000000", -- 00000138 - X"00000000", -- 0000013C - X"00000000", -- 00000140 - X"00000000", -- 00000144 - X"00000000", -- 00000148 - X"00000000", -- 0000014C - X"00000000", -- 00000150 - X"00000000", -- 00000154 - X"00000000", -- 00000158 - X"00000000", -- 0000015C - X"00000000", -- 00000160 - X"00000000", -- 00000164 - X"00000000", -- 00000168 - X"00000000", -- 0000016C - X"00000000", -- 00000170 - X"00000000", -- 00000174 - X"00000000", -- 00000178 - X"00000000", -- 0000017C - X"401A6800", -- 00000180 - X"3C1BC000", -- 00000184 - X"001AD082", -- 00000188 - X"335A000F", -- 0000018C - X"035BD025", -- 00000190 - X"3C1BA000", -- 00000194 - X"277B0000", -- 00000198 - X"AF7A0000", -- 0000019C - X"401A6800", -- 000001A0 - X"00000000", -- 000001A4 - X"001AD202", -- 000001A8 - X"335A00FF", -- 000001AC - X"1740FFFB", -- 000001B0 - X"00000000", -- 000001B4 - X"401A7000", -- 000001B8 - X"00000000", -- 000001BC - X"03400008", -- 000001C0 - X"42000010", -- 000001C4 - X"40026000", -- 000001C8 - X"03E00008", -- 000001CC - X"00000000", -- 000001D0 - X"40846000", -- 000001D4 - X"03E00008", -- 000001D8 - X"00000000", -- 000001DC - X"40026800", -- 000001E0 - X"03E00008", -- 000001E4 - X"00000000", -- 000001E8 - X"40846800", -- 000001EC - X"03E00008", -- 000001F0 - X"00000000", -- 000001F4 - X"40027800", -- 000001F8 - X"03E00008", -- 000001FC - X"00000000", -- 00000200 - X"3C02A001", -- 00000204 - X"34430004", -- 00000208 - X"8C620000", -- 0000020C - X"00000000", -- 00000210 - X"30420010", -- 00000214 - X"1040FFFC", -- 00000218 - X"3C02A001", -- 0000021C - X"8C420000", -- 00000220 - X"00000000", -- 00000224 - X"00021600", -- 00000228 - X"03E00008", -- 0000022C - X"00021603", -- 00000230 - X"00042600", -- 00000234 - X"3C02A001", -- 00000238 - X"00042603", -- 0000023C - X"34430004", -- 00000240 - X"8C620000", -- 00000244 - X"00000000", -- 00000248 - X"30420002", -- 0000024C - X"1440FFFC", -- 00000250 - X"3C02A001", -- 00000254 - X"AC440000", -- 00000258 - X"03E00008", -- 0000025C - X"00000000", -- 00000260 - X"00042600", -- 00000264 - X"00042603", -- 00000268 - X"2402000A", -- 0000026C - X"1482000A", -- 00000270 - X"3C02A001", -- 00000274 - X"34430004", -- 00000278 - X"8C620000", -- 0000027C - X"00000000", -- 00000280 - X"30420002", -- 00000284 - X"1440FFFC", -- 00000288 - X"3C02A001", -- 0000028C - X"2403000D", -- 00000290 - X"AC430000", -- 00000294 - X"3C02A001", -- 00000298 - X"34430004", -- 0000029C - X"8C620000", -- 000002A0 - X"00000000", -- 000002A4 - X"30420002", -- 000002A8 - X"1440FFFC", -- 000002AC - X"3C02A001", -- 000002B0 - X"AC440000", -- 000002B4 - X"03E00008", -- 000002B8 - X"00000000", -- 000002BC - X"3C02A001", -- 000002C0 - X"34470004", -- 000002C4 - X"00802821", -- 000002C8 - X"2409000A", -- 000002CC - X"3C06A001", -- 000002D0 - X"0BF000C6", -- 000002D4 - X"2408000D", -- 000002D8 - X"14690007", -- 000002DC - X"00000000", -- 000002E0 - X"8CE20000", -- 000002E4 - X"00000000", -- 000002E8 - X"30420002", -- 000002EC - X"1440FFFC", -- 000002F0 - X"00000000", -- 000002F4 - X"ACC80000", -- 000002F8 - X"8CE20000", -- 000002FC - X"00000000", -- 00000300 - X"30420002", -- 00000304 - X"1440FFFC", -- 00000308 - X"00000000", -- 0000030C - X"ACC30000", -- 00000310 - X"24A50001", -- 00000314 - X"80A30000", -- 00000318 - X"00000000", -- 0000031C - X"1460FFEE", -- 00000320 - X"00A41023", -- 00000324 - X"03E00008", -- 00000328 - X"00000000", -- 0000032C - X"00042600", -- 00000330 - X"3C02A001", -- 00000334 - X"00042603", -- 00000338 - X"344A0004", -- 0000033C - X"00003821", -- 00000340 - X"3C09A001", -- 00000344 - X"24080002", -- 00000348 - X"308200FF", -- 0000034C - X"00022902", -- 00000350 - X"00041100", -- 00000354 - X"00022600", -- 00000358 - X"2CA3000A", -- 0000035C - X"00042603", -- 00000360 - X"14600002", -- 00000364 - X"24A60030", -- 00000368 - X"24A60037", -- 0000036C - X"8D420000", -- 00000370 - X"00000000", -- 00000374 - X"30420002", -- 00000378 - X"1440FFFC", -- 0000037C - X"00061600", -- 00000380 - X"00021603", -- 00000384 - X"24E70001", -- 00000388 - X"AD220000", -- 0000038C - X"14E8FFEF", -- 00000390 - X"308200FF", -- 00000394 - X"03E00008", -- 00000398 - X"00000000", -- 0000039C - X"27BDFFE0", -- 000003A0 - X"AFB20018", -- 000003A4 - X"AFB10014", -- 000003A8 - X"AFB00010", -- 000003AC - X"AFBF001C", -- 000003B0 - X"00808821", -- 000003B4 - X"00008021", -- 000003B8 - X"24120004", -- 000003BC - X"00112603", -- 000003C0 - X"0FF000CC", -- 000003C4 - X"26100001", -- 000003C8 - X"1612FFFC", -- 000003CC - X"00118A00", -- 000003D0 - X"8FBF001C", -- 000003D4 - X"8FB20018", -- 000003D8 - X"8FB10014", -- 000003DC - X"8FB00010", -- 000003E0 - X"03E00008", -- 000003E4 - X"27BD0020", -- 000003E8 - X"27BDFFC8", -- 000003EC - X"AFB60028", -- 000003F0 - X"AFBF0034", -- 000003F4 - X"AFBE0030", -- 000003F8 - X"AFB7002C", -- 000003FC - X"AFB50024", -- 00000400 - X"AFB40020", -- 00000404 - X"AFB3001C", -- 00000408 - X"AFB20018", -- 0000040C - X"AFB10014", -- 00000410 - X"AFB00010", -- 00000414 - X"00801021", -- 00000418 - X"10A00002", -- 0000041C - X"00C0B021", -- 00000420 - X"00002021", -- 00000424 - X"00409821", -- 00000428 - X"3C02A001", -- 0000042C - X"00E09021", -- 00000430 - X"0080A821", -- 00000434 - X"345E0004", -- 00000438 - X"00E0A021", -- 0000043C - X"3C17A001", -- 00000440 - X"0FF000E8", -- 00000444 - X"02A02021", -- 00000448 - X"3C04BFC0", -- 0000044C - X"0FF000B0", -- 00000450 - X"2484169C", -- 00000454 - X"02608821", -- 00000458 - X"0BF00128", -- 0000045C - X"00008021", -- 00000460 - X"12400009", -- 00000464 - X"00000000", -- 00000468 - X"82240000", -- 0000046C - X"0FF000CC", -- 00000470 - X"2652FFFF", -- 00000474 - X"3C04BFC0", -- 00000478 - X"0FF000B0", -- 0000047C - X"24841774", -- 00000480 - X"0BF00128", -- 00000484 - X"26310001", -- 00000488 - X"3C04BFC0", -- 0000048C - X"0FF000B0", -- 00000490 - X"248416A0", -- 00000494 - X"0BF0012C", -- 00000498 - X"3C04BFC0", -- 0000049C - X"0216102A", -- 000004A0 - X"1440FFEF", -- 000004A4 - X"26100001", -- 000004A8 - X"3C04BFC0", -- 000004AC - X"0FF000B0", -- 000004B0 - X"248416A0", -- 000004B4 - X"02602821", -- 000004B8 - X"0BF00155", -- 000004BC - X"00002021", -- 000004C0 - X"1280001E", -- 000004C4 - X"00000000", -- 000004C8 - X"90A30000", -- 000004CC - X"00000000", -- 000004D0 - X"2462FFE0", -- 000004D4 - X"304200FF", -- 000004D8 - X"2C420060", -- 000004DC - X"14400003", -- 000004E0 - X"00031E00", -- 000004E4 - X"2403002E", -- 000004E8 - X"00031E00", -- 000004EC - X"00031E03", -- 000004F0 - X"2402000A", -- 000004F4 - X"14620007", -- 000004F8 - X"00000000", -- 000004FC - X"8FC20000", -- 00000500 - X"00000000", -- 00000504 - X"30420002", -- 00000508 - X"1440FFFC", -- 0000050C - X"2402000D", -- 00000510 - X"AEE20000", -- 00000514 - X"8FC20000", -- 00000518 - X"00000000", -- 0000051C - X"30420002", -- 00000520 - X"1440FFFC", -- 00000524 - X"00000000", -- 00000528 - X"AEE30000", -- 0000052C - X"2694FFFF", -- 00000530 - X"24840001", -- 00000534 - X"0BF00155", -- 00000538 - X"24A50001", -- 0000053C - X"3C04BFC0", -- 00000540 - X"0FF000B0", -- 00000544 - X"24841774", -- 00000548 - X"0BF00159", -- 0000054C - X"3C04BFC0", -- 00000550 - X"0096102A", -- 00000554 - X"1440FFDA", -- 00000558 - X"00000000", -- 0000055C - X"3C04BFC0", -- 00000560 - X"0FF000B0", -- 00000564 - X"248416C8", -- 00000568 - X"02B6A821", -- 0000056C - X"1640FFB4", -- 00000570 - X"02769821", -- 00000574 - X"8FBF0034", -- 00000578 - X"8FBE0030", -- 0000057C - X"8FB7002C", -- 00000580 - X"8FB60028", -- 00000584 - X"8FB50024", -- 00000588 - X"8FB40020", -- 0000058C - X"8FB3001C", -- 00000590 - X"8FB20018", -- 00000594 - X"8FB10014", -- 00000598 - X"8FB00010", -- 0000059C - X"03E00008", -- 000005A0 - X"27BD0038", -- 000005A4 - X"00C03821", -- 000005A8 - X"00A03021", -- 000005AC - X"0BF000FB", -- 000005B0 - X"24050001", -- 000005B4 - X"8C840000", -- 000005B8 - X"3C020070", -- 000005BC - X"34420070", -- 000005C0 - X"3C0300FF", -- 000005C4 - X"AC820000", -- 000005C8 - X"346300FF", -- 000005CC - X"8C820000", -- 000005D0 - X"AC830000", -- 000005D4 - X"03E00008", -- 000005D8 - X"00000000", -- 000005DC - X"27BDFFF8", -- 000005E0 - X"AC850000", -- 000005E4 - X"24820008", -- 000005E8 - X"0BF0017F", -- 000005EC - X"24830020", -- 000005F0 - X"A0400000", -- 000005F4 - X"24420001", -- 000005F8 - X"1443FFFD", -- 000005FC - X"00000000", -- 00000600 - X"24020001", -- 00000604 - X"AC820004", -- 00000608 - X"03E00008", -- 0000060C - X"27BD0008", -- 00000610 - X"8C870000", -- 00000614 - X"3C020098", -- 00000618 - X"34420098", -- 0000061C - X"ACE20000", -- 00000620 - X"3C0200FF", -- 00000624 - X"344200FF", -- 00000628 - X"ACE20000", -- 0000062C - X"3C020090", -- 00000630 - X"34420090", -- 00000634 - X"ACE20000", -- 00000638 - X"00804021", -- 0000063C - X"94E4009C", -- 00000640 - X"24030002", -- 00000644 - X"24020020", -- 00000648 - X"AD030008", -- 0000064C - X"AD03001C", -- 00000650 - X"AD020018", -- 00000654 - X"3084FFFF", -- 00000658 - X"0BF0019D", -- 0000065C - X"00001821", -- 00000660 - X"8D020008", -- 00000664 - X"00000000", -- 00000668 - X"00021040", -- 0000066C - X"AD020008", -- 00000670 - X"0064102B", -- 00000674 - X"1440FFFA", -- 00000678 - X"24630001", -- 0000067C - X"94E200AC", -- 00000680 - X"94E300A8", -- 00000684 - X"3042FFFF", -- 00000688 - X"8D04001C", -- 0000068C - X"3063FFFF", -- 00000690 - X"00021200", -- 00000694 - X"00432825", -- 00000698 - X"AD040014", -- 0000069C - X"0BF001AE", -- 000006A0 - X"00001821", -- 000006A4 - X"8D020014", -- 000006A8 - X"00000000", -- 000006AC - X"00021040", -- 000006B0 - X"AD020014", -- 000006B4 - X"0065102B", -- 000006B8 - X"1440FFFA", -- 000006BC - X"24630001", -- 000006C0 - X"94E300B8", -- 000006C4 - X"94E600B4", -- 000006C8 - X"94E200C0", -- 000006CC - X"94E400BC", -- 000006D0 - X"8D05001C", -- 000006D4 - X"3042FFFF", -- 000006D8 - X"3084FFFF", -- 000006DC - X"00021200", -- 000006E0 - X"00441025", -- 000006E4 - X"00052A00", -- 000006E8 - X"00A20018", -- 000006EC - X"3063FFFF", -- 000006F0 - X"30C6FFFF", -- 000006F4 - X"00031A00", -- 000006F8 - X"00661825", -- 000006FC - X"24630001", -- 00000700 - X"AD030010", -- 00000704 - X"3C0300FF", -- 00000708 - X"346300FF", -- 0000070C - X"00001021", -- 00000710 - X"00002812", -- 00000714 - X"AD05000C", -- 00000718 - X"ACE30000", -- 0000071C - X"03E00008", -- 00000720 - X"00000000", -- 00000724 - X"8C820008", -- 00000728 - X"8C860000", -- 0000072C - X"00021082", -- 00000730 - X"00A2102B", -- 00000734 - X"14400004", -- 00000738 - X"3C030090", -- 0000073C - X"3C028010", -- 00000740 - X"03E00008", -- 00000744 - X"34420002", -- 00000748 - X"8C820010", -- 0000074C - X"00000000", -- 00000750 - X"2442FFFF", -- 00000754 - X"00021400", -- 00000758 - X"00A21024", -- 0000075C - X"24420002", -- 00000760 - X"34630090", -- 00000764 - X"00021080", -- 00000768 - X"ACC30000", -- 0000076C - X"00C21021", -- 00000770 - X"8C430000", -- 00000774 - X"3C020001", -- 00000778 - X"34420001", -- 0000077C - X"00621824", -- 00000780 - X"3C0200FF", -- 00000784 - X"344200FF", -- 00000788 - X"ACC20000", -- 0000078C - X"03E00008", -- 00000790 - X"0003102B", -- 00000794 - X"8C820008", -- 00000798 - X"00A01821", -- 0000079C - X"00021082", -- 000007A0 - X"00A2102B", -- 000007A4 - X"8C850000", -- 000007A8 - X"14400003", -- 000007AC - X"3C028010", -- 000007B0 - X"0BF0020C", -- 000007B4 - X"34430002", -- 000007B8 - X"8C820010", -- 000007BC - X"00000000", -- 000007C0 - X"2442FFFF", -- 000007C4 - X"00021400", -- 000007C8 - X"00621024", -- 000007CC - X"00021080", -- 000007D0 - X"00A22021", -- 000007D4 - X"3C020020", -- 000007D8 - X"34420020", -- 000007DC - X"AC820000", -- 000007E0 - X"3C0200D0", -- 000007E4 - X"344200D0", -- 000007E8 - X"AC820000", -- 000007EC - X"3C020080", -- 000007F0 - X"34430080", -- 000007F4 - X"8C860000", -- 000007F8 - X"00000000", -- 000007FC - X"00C31024", -- 00000800 - X"1443FFFC", -- 00000804 - X"3C02002A", -- 00000808 - X"3442002A", -- 0000080C - X"00C21024", -- 00000810 - X"10400003", -- 00000814 - X"00001821", -- 00000818 - X"3C029010", -- 0000081C - X"00C21825", -- 00000820 - X"3C0200FF", -- 00000824 - X"344200FF", -- 00000828 - X"AC820000", -- 0000082C - X"03E00008", -- 00000830 - X"00601021", -- 00000834 - X"8C820008", -- 00000838 - X"00A01821", -- 0000083C - X"00021082", -- 00000840 - X"00A2102B", -- 00000844 - X"8C850000", -- 00000848 - X"14400003", -- 0000084C - X"3C028010", -- 00000850 - X"0BF00234", -- 00000854 - X"34430002", -- 00000858 - X"8C820010", -- 0000085C - X"00000000", -- 00000860 - X"2442FFFF", -- 00000864 - X"00021400", -- 00000868 - X"00621024", -- 0000086C - X"00021080", -- 00000870 - X"00A22021", -- 00000874 - X"3C020060", -- 00000878 - X"34420060", -- 0000087C - X"AC820000", -- 00000880 - X"3C020001", -- 00000884 - X"34420001", -- 00000888 - X"AC820000", -- 0000088C - X"3C020080", -- 00000890 - X"34430080", -- 00000894 - X"8C860000", -- 00000898 - X"00000000", -- 0000089C - X"00C31024", -- 000008A0 - X"1443FFFC", -- 000008A4 - X"3C020038", -- 000008A8 - X"34420038", -- 000008AC - X"00C21024", -- 000008B0 - X"10400003", -- 000008B4 - X"00001821", -- 000008B8 - X"3C029010", -- 000008BC - X"00C21825", -- 000008C0 - X"3C0200FF", -- 000008C4 - X"344200FF", -- 000008C8 - X"AC820000", -- 000008CC - X"03E00008", -- 000008D0 - X"00601021", -- 000008D4 - X"8C820008", -- 000008D8 - X"00A01821", -- 000008DC - X"00021082", -- 000008E0 - X"00A2102B", -- 000008E4 - X"8C850000", -- 000008E8 - X"14400003", -- 000008EC - X"3C028010", -- 000008F0 - X"0BF0025C", -- 000008F4 - X"34430002", -- 000008F8 - X"8C820010", -- 000008FC - X"00000000", -- 00000900 - X"2442FFFF", -- 00000904 - X"00021400", -- 00000908 - X"00621024", -- 0000090C - X"00021080", -- 00000910 - X"00A22021", -- 00000914 - X"3C020060", -- 00000918 - X"34420060", -- 0000091C - X"AC820000", -- 00000920 - X"3C0200D0", -- 00000924 - X"344200D0", -- 00000928 - X"AC820000", -- 0000092C - X"3C020080", -- 00000930 - X"34430080", -- 00000934 - X"8C860000", -- 00000938 - X"00000000", -- 0000093C - X"00C31024", -- 00000940 - X"1443FFFC", -- 00000944 - X"3C020038", -- 00000948 - X"34420038", -- 0000094C - X"00C21024", -- 00000950 - X"10400003", -- 00000954 - X"00001821", -- 00000958 - X"3C029010", -- 0000095C - X"00C21825", -- 00000960 - X"3C0200FF", -- 00000964 - X"344200FF", -- 00000968 - X"AC820000", -- 0000096C - X"03E00008", -- 00000970 - X"00601021", -- 00000974 - X"8C820008", -- 00000978 - X"8C840000", -- 0000097C - X"00021082", -- 00000980 - X"00A2102B", -- 00000984 - X"14400003", -- 00000988 - X"3C028010", -- 0000098C - X"0BF0027C", -- 00000990 - X"34430002", -- 00000994 - X"00051080", -- 00000998 - X"00822021", -- 0000099C - X"3C020040", -- 000009A0 - X"34420040", -- 000009A4 - X"AC820000", -- 000009A8 - X"3C020080", -- 000009AC - X"AC860000", -- 000009B0 - X"34430080", -- 000009B4 - X"8C860000", -- 000009B8 - X"00000000", -- 000009BC - X"00C31024", -- 000009C0 - X"1443FFFC", -- 000009C4 - X"3C02001A", -- 000009C8 - X"3442001A", -- 000009CC - X"00C21024", -- 000009D0 - X"10400003", -- 000009D4 - X"00001821", -- 000009D8 - X"3C029010", -- 000009DC - X"00C21825", -- 000009E0 - X"3C0200FF", -- 000009E4 - X"344200FF", -- 000009E8 - X"AC820000", -- 000009EC - X"03E00008", -- 000009F0 - X"00601021", -- 000009F4 - X"8C820008", -- 000009F8 - X"27BDFFE8", -- 000009FC - X"00021082", -- 00000A00 - X"00A2102B", -- 00000A04 - X"AFB40014", -- 00000A08 - X"AFB30010", -- 00000A0C - X"AFB2000C", -- 00000A10 - X"AFB10008", -- 00000A14 - X"AFB00004", -- 00000A18 - X"0080C021", -- 00000A1C - X"8C8E0000", -- 00000A20 - X"14400004", -- 00000A24 - X"00C0A021", -- 00000A28 - X"3C028010", -- 00000A2C - X"0BF002E3", -- 00000A30 - X"34440002", -- 00000A34 - X"8C820010", -- 00000A38 - X"00006821", -- 00000A3C - X"2442FFFF", -- 00000A40 - X"0002CC00", -- 00000A44 - X"3C0200E8", -- 00000A48 - X"345300E8", -- 00000A4C - X"3C020080", -- 00000A50 - X"344F0080", -- 00000A54 - X"3C02001A", -- 00000A58 - X"3446001A", -- 00000A5C - X"3C0200D0", -- 00000A60 - X"345200D0", -- 00000A64 - X"3C0200FF", -- 00000A68 - X"345100FF", -- 00000A6C - X"0BF002E1", -- 00000A70 - X"3C100001", -- 00000A74 - X"01851023", -- 00000A78 - X"00505021", -- 00000A7C - X"00EA102B", -- 00000A80 - X"10400002", -- 00000A84 - X"000C1080", -- 00000A88 - X"00E05021", -- 00000A8C - X"0BF002D7", -- 00000A90 - X"01C25821", -- 00000A94 - X"AD730000", -- 00000A98 - X"8D630000", -- 00000A9C - X"00000000", -- 00000AA0 - X"006F1024", -- 00000AA4 - X"144FFFFC", -- 00000AA8 - X"00661024", -- 00000AAC - X"14400026", -- 00000AB0 - X"3C029010", -- 00000AB4 - X"8F020014", -- 00000AB8 - X"00000000", -- 00000ABC - X"00021882", -- 00000AC0 - X"006A102B", -- 00000AC4 - X"10400002", -- 00000AC8 - X"01404021", -- 00000ACC - X"00604021", -- 00000AD0 - X"2503FFFF", -- 00000AD4 - X"00031400", -- 00000AD8 - X"00431025", -- 00000ADC - X"00052080", -- 00000AE0 - X"000D1880", -- 00000AE4 - X"02834821", -- 00000AE8 - X"AD620000", -- 00000AEC - X"01C42021", -- 00000AF0 - X"0BF002C3", -- 00000AF4 - X"00001821", -- 00000AF8 - X"8D220000", -- 00000AFC - X"25290004", -- 00000B00 - X"AC820000", -- 00000B04 - X"24840004", -- 00000B08 - X"0068102B", -- 00000B0C - X"1440FFFA", -- 00000B10 - X"24630001", -- 00000B14 - X"01A86821", -- 00000B18 - X"00A82821", -- 00000B1C - X"00E83823", -- 00000B20 - X"AD720000", -- 00000B24 - X"8D630000", -- 00000B28 - X"00000000", -- 00000B2C - X"006F1024", -- 00000B30 - X"144FFFFC", -- 00000B34 - X"00661024", -- 00000B38 - X"10400005", -- 00000B3C - X"01485023", -- 00000B40 - X"01485021", -- 00000B44 - X"3C029010", -- 00000B48 - X"0BF002D9", -- 00000B4C - X"00622025", -- 00000B50 - X"AD710000", -- 00000B54 - X"00002021", -- 00000B58 - X"1540FFCE", -- 00000B5C - X"00000000", -- 00000B60 - X"04810007", -- 00000B64 - X"000C1880", -- 00000B68 - X"3C0200FF", -- 00000B6C - X"01C31821", -- 00000B70 - X"344200FF", -- 00000B74 - X"AC620000", -- 00000B78 - X"0BF002E4", -- 00000B7C - X"00801021", -- 00000B80 - X"14E0FFBC", -- 00000B84 - X"00B96024", -- 00000B88 - X"00801021", -- 00000B8C - X"8FB40014", -- 00000B90 - X"8FB30010", -- 00000B94 - X"8FB2000C", -- 00000B98 - X"8FB10008", -- 00000B9C - X"8FB00004", -- 00000BA0 - X"03E00008", -- 00000BA4 - X"27BD0018", -- 00000BA8 - X"27BDFFE0", -- 00000BAC - X"AFBF001C", -- 00000BB0 - X"AC850000", -- 00000BB4 - X"24820008", -- 00000BB8 - X"0BF002F3", -- 00000BBC - X"24830020", -- 00000BC0 - X"A0400000", -- 00000BC4 - X"24420001", -- 00000BC8 - X"1443FFFD", -- 00000BCC - X"00000000", -- 00000BD0 - X"3C021234", -- 00000BD4 - X"34425678", -- 00000BD8 - X"00021E02", -- 00000BDC - X"AFA20010", -- 00000BE0 - X"24020012", -- 00000BE4 - X"14620003", -- 00000BE8 - X"AC800004", -- 00000BEC - X"24020001", -- 00000BF0 - X"AC820004", -- 00000BF4 - X"0FF00185", -- 00000BF8 - X"00000000", -- 00000BFC - X"8FBF001C", -- 00000C00 - X"00000000", -- 00000C04 - X"03E00008", -- 00000C08 - X"27BD0020", -- 00000C0C - X"27BDFFD8", -- 00000C10 - X"30C20003", -- 00000C14 - X"AFB2001C", -- 00000C18 - X"AFBF0024", -- 00000C1C - X"AFB30020", -- 00000C20 - X"AFB10018", -- 00000C24 - X"AFB00014", -- 00000C28 - X"10400004", -- 00000C2C - X"00809021", -- 00000C30 - X"00061082", -- 00000C34 - X"24420001", -- 00000C38 - X"00023080", -- 00000C3C - X"00C59821", -- 00000C40 - X"0BF00324", -- 00000C44 - X"00A08821", -- 00000C48 - X"0FF001CA", -- 00000C4C - X"00000000", -- 00000C50 - X"02402021", -- 00000C54 - X"10400005", -- 00000C58 - X"02002821", -- 00000C5C - X"0FF00236", -- 00000C60 - X"00000000", -- 00000C64 - X"04400011", -- 00000C68 - X"00401821", -- 00000C6C - X"02002821", -- 00000C70 - X"0FF001E6", -- 00000C74 - X"02402021", -- 00000C78 - X"0440000C", -- 00000C7C - X"00401821", -- 00000C80 - X"8E42000C", -- 00000C84 - X"00000000", -- 00000C88 - X"02228821", -- 00000C8C - X"001117C3", -- 00000C90 - X"00021782", -- 00000C94 - X"00511021", -- 00000C98 - X"00028083", -- 00000C9C - X"0233102B", -- 00000CA0 - X"02402021", -- 00000CA4 - X"1440FFE8", -- 00000CA8 - X"02002821", -- 00000CAC - X"8FBF0024", -- 00000CB0 - X"00601021", -- 00000CB4 - X"8FB30020", -- 00000CB8 - X"8FB2001C", -- 00000CBC - X"8FB10018", -- 00000CC0 - X"8FB00014", -- 00000CC4 - X"03E00008", -- 00000CC8 - X"27BD0028", -- 00000CCC - X"30E20003", -- 00000CD0 - X"10400003", -- 00000CD4 - X"00071082", -- 00000CD8 - X"24420001", -- 00000CDC - X"00023880", -- 00000CE0 - X"00052882", -- 00000CE4 - X"0BF0027E", -- 00000CE8 - X"00073882", -- 00000CEC - X"8C820000", -- 00000CF0 - X"00002021", -- 00000CF4 - X"0BF00347", -- 00000CF8 - X"00454021", -- 00000CFC - X"90630000", -- 00000D00 - X"90A20000", -- 00000D04 - X"00000000", -- 00000D08 - X"10620003", -- 00000D0C - X"3C028010", -- 00000D10 - X"03E00008", -- 00000D14 - X"34420003", -- 00000D18 - X"0087102B", -- 00000D1C - X"01041821", -- 00000D20 - X"00C42821", -- 00000D24 - X"1440FFF5", -- 00000D28 - X"24840001", -- 00000D2C - X"03E00008", -- 00000D30 - X"00000000", -- 00000D34 - X"8C82000C", -- 00000D38 - X"00000000", -- 00000D3C - X"14400002", -- 00000D40 - X"00A2001B", -- 00000D44 - X"0007000D", -- 00000D48 - X"00001010", -- 00000D4C - X"0002102B", -- 00000D50 - X"00002812", -- 00000D54 - X"03E00008", -- 00000D58 - X"00A21021", -- 00000D5C - X"8C830010", -- 00000D60 - X"00000000", -- 00000D64 - X"00A3102B", -- 00000D68 - X"14400002", -- 00000D6C - X"00000000", -- 00000D70 - X"2465FFFF", -- 00000D74 - X"8C82000C", -- 00000D78 - X"00000000", -- 00000D7C - X"00A20018", -- 00000D80 - X"00001012", -- 00000D84 - X"03E00008", -- 00000D88 - X"00000000", -- 00000D8C - X"27BDFFE8", -- 00000D90 - X"AFBF0014", -- 00000D94 - X"AFB00010", -- 00000D98 - X"0FF0034E", -- 00000D9C - X"00808021", -- 00000DA0 - X"8E03000C", -- 00000DA4 - X"8FBF0014", -- 00000DA8 - X"00430018", -- 00000DAC - X"8FB00010", -- 00000DB0 - X"00001012", -- 00000DB4 - X"03E00008", -- 00000DB8 - X"27BD0018", -- 00000DBC - X"90830000", -- 00000DC0 - X"00000000", -- 00000DC4 - X"2C620041", -- 00000DC8 - X"14400002", -- 00000DCC - X"2462FFD0", -- 00000DD0 - X"2462FFC9", -- 00000DD4 - X"90840001", -- 00000DD8 - X"304200FF", -- 00000DDC - X"304300FF", -- 00000DE0 - X"2C820041", -- 00000DE4 - X"14400003", -- 00000DE8 - X"00000000", -- 00000DEC - X"0BF0037F", -- 00000DF0 - X"2482FFC9", -- 00000DF4 - X"2482FFD0", -- 00000DF8 - X"304400FF", -- 00000DFC - X"00031100", -- 00000E00 - X"00821025", -- 00000E04 - X"03E00008", -- 00000E08 - X"304200FF", -- 00000E0C - X"10C00094", -- 00000E10 - X"00805021", -- 00000E14 - X"24020003", -- 00000E18 - X"AC820008", -- 00000E1C - X"90A40001", -- 00000E20 - X"00000000", -- 00000E24 - X"2482FFCF", -- 00000E28 - X"304200FF", -- 00000E2C - X"2C420003", -- 00000E30 - X"10400005", -- 00000E34 - X"2482FFC9", -- 00000E38 - X"24020002", -- 00000E3C - X"AD420008", -- 00000E40 - X"0BF003A1", -- 00000E44 - X"2489FFD1", -- 00000E48 - X"304200FF", -- 00000E4C - X"2C420003", -- 00000E50 - X"10400006", -- 00000E54 - X"24020030", -- 00000E58 - X"2402003B", -- 00000E5C - X"00444823", -- 00000E60 - X"24020004", -- 00000E64 - X"0BF003A1", -- 00000E68 - X"AD420008", -- 00000E6C - X"14820004", -- 00000E70 - X"00004821", -- 00000E74 - X"24020001", -- 00000E78 - X"AD420008", -- 00000E7C - X"24090002", -- 00000E80 - X"90A30002", -- 00000E84 - X"00000000", -- 00000E88 - X"2C620041", -- 00000E8C - X"10400003", -- 00000E90 - X"24A40002", -- 00000E94 - X"0BF003A9", -- 00000E98 - X"2462FFD0", -- 00000E9C - X"2462FFC9", -- 00000EA0 - X"90830001", -- 00000EA4 - X"304200FF", -- 00000EA8 - X"304400FF", -- 00000EAC - X"2C620041", -- 00000EB0 - X"10400002", -- 00000EB4 - X"2462FFC9", -- 00000EB8 - X"2462FFD0", -- 00000EBC - X"304300FF", -- 00000EC0 - X"00041100", -- 00000EC4 - X"00621025", -- 00000EC8 - X"304200FF", -- 00000ECC - X"AD420004", -- 00000ED0 - X"AD400000", -- 00000ED4 - X"00405821", -- 00000ED8 - X"00A03021", -- 00000EDC - X"0BF003D5", -- 00000EE0 - X"00003821", -- 00000EE4 - X"90C20004", -- 00000EE8 - X"00000000", -- 00000EEC - X"2443FFC9", -- 00000EF0 - X"2444FFD0", -- 00000EF4 - X"2C420041", -- 00000EF8 - X"10400002", -- 00000EFC - X"306300FF", -- 00000F00 - X"308300FF", -- 00000F04 - X"90C20005", -- 00000F08 - X"306800FF", -- 00000F0C - X"2444FFC9", -- 00000F10 - X"2443FFD0", -- 00000F14 - X"2C420041", -- 00000F18 - X"10400002", -- 00000F1C - X"308400FF", -- 00000F20 - X"306400FF", -- 00000F24 - X"8D430000", -- 00000F28 - X"00081100", -- 00000F2C - X"00821025", -- 00000F30 - X"304200FF", -- 00000F34 - X"00031A00", -- 00000F38 - X"004B2021", -- 00000F3C - X"00431025", -- 00000F40 - X"AD420000", -- 00000F44 - X"308B00FF", -- 00000F48 - X"24E70001", -- 00000F4C - X"24C60002", -- 00000F50 - X"00E9102A", -- 00000F54 - X"1440FFE3", -- 00000F58 - X"25220002", -- 00000F5C - X"8D440004", -- 00000F60 - X"00021040", -- 00000F64 - X"00091827", -- 00000F68 - X"00832021", -- 00000F6C - X"00A21021", -- 00000F70 - X"AD440004", -- 00000F74 - X"AD42000C", -- 00000F78 - X"0BF003F9", -- 00000F7C - X"00003021", -- 00000F80 - X"90E20000", -- 00000F84 - X"00000000", -- 00000F88 - X"2444FFC9", -- 00000F8C - X"2445FFD0", -- 00000F90 - X"2C420041", -- 00000F94 - X"10400002", -- 00000F98 - X"308400FF", -- 00000F9C - X"30A400FF", -- 00000FA0 - X"90E20001", -- 00000FA4 - X"308700FF", -- 00000FA8 - X"2445FFC9", -- 00000FAC - X"2444FFD0", -- 00000FB0 - X"2C420041", -- 00000FB4 - X"14400002", -- 00000FB8 - X"308400FF", -- 00000FBC - X"30A400FF", -- 00000FC0 - X"00071100", -- 00000FC4 - X"00821025", -- 00000FC8 - X"304200FF", -- 00000FCC - X"00661821", -- 00000FD0 - X"004B2021", -- 00000FD4 - X"A0620000", -- 00000FD8 - X"308B00FF", -- 00000FDC - X"24C60001", -- 00000FE0 - X"8D420004", -- 00000FE4 - X"8D43000C", -- 00000FE8 - X"00062040", -- 00000FEC - X"00C2102A", -- 00000FF0 - X"1440FFE3", -- 00000FF4 - X"00643821", -- 00000FF8 - X"90E40000", -- 00000FFC - X"00000000", -- 00001000 - X"2C820041", -- 00001004 - X"10400003", -- 00001008 - X"00E01821", -- 0000100C - X"0BF00407", -- 00001010 - X"2482FFD0", -- 00001014 - X"2482FFC9", -- 00001018 - X"90630001", -- 0000101C - X"304200FF", -- 00001020 - X"304400FF", -- 00001024 - X"2C620041", -- 00001028 - X"10400002", -- 0000102C - X"2462FFC9", -- 00001030 - X"2462FFD0", -- 00001034 - X"304200FF", -- 00001038 - X"00041900", -- 0000103C - X"00431825", -- 00001040 - X"000B1027", -- 00001044 - X"304200FF", -- 00001048 - X"306300FF", -- 0000104C - X"14430004", -- 00001050 - X"00000000", -- 00001054 - X"8D420008", -- 00001058 - X"03E00008", -- 0000105C - X"00000000", -- 00001060 - X"03E00008", -- 00001064 - X"00001021", -- 00001068 - X"00800008", -- 0000106C - X"00000000", -- 00001070 - X"03E00008", -- 00001074 - X"00000000", -- 00001078 - X"3C1A1000", -- 0000107C - X"409A6000", -- 00001080 - X"00800008", -- 00001084 - X"42000010", -- 00001088 - X"03E00008", -- 0000108C - X"00000000", -- 00001090 - X"401A6000", -- 00001094 - X"3C1BFFBF", -- 00001098 - X"377BFFFF", -- 0000109C - X"035BD024", -- 000010A0 - X"3C1B0200", -- 000010A4 - X"035BD025", -- 000010A8 - X"409A6000", -- 000010AC - X"00800008", -- 000010B0 - X"42000010", -- 000010B4 - X"03E00008", -- 000010B8 - X"00000000", -- 000010BC - X"27BDFFD8", -- 000010C0 - X"AFB30020", -- 000010C4 - X"AFB10018", -- 000010C8 - X"AFB00014", -- 000010CC - X"AFBF0024", -- 000010D0 - X"AFB2001C", -- 000010D4 - X"00809821", -- 000010D8 - X"24110073", -- 000010DC - X"24100053", -- 000010E0 - X"0FF00081", -- 000010E4 - X"00000000", -- 000010E8 - X"14510005", -- 000010EC - X"00000000", -- 000010F0 - X"00008021", -- 000010F4 - X"2412000A", -- 000010F8 - X"0BF00449", -- 000010FC - X"2411000D", -- 00001100 - X"1450FFF7", -- 00001104 - X"00000000", -- 00001108 - X"0BF0043E", -- 0000110C - X"00008021", -- 00001110 - X"0FF00081", -- 00001114 - X"A0620000", -- 00001118 - X"10510003", -- 0000111C - X"26100001", -- 00001120 - X"1452FFFB", -- 00001124 - X"02701821", -- 00001128 - X"8FBF0024", -- 0000112C - X"02001021", -- 00001130 - X"8FB30020", -- 00001134 - X"8FB2001C", -- 00001138 - X"8FB10018", -- 0000113C - X"8FB00014", -- 00001140 - X"03E00008", -- 00001144 - X"27BD0028", -- 00001148 - X"27BDFD98", -- 0000114C - X"27A40140", -- 00001150 - X"00002821", -- 00001154 - X"24060100", -- 00001158 - X"AFB20248", -- 0000115C - X"AFB10244", -- 00001160 - X"AFB00240", -- 00001164 - X"3C11A000", -- 00001168 - X"AFBF0264", -- 0000116C - X"AFBE0260", -- 00001170 - X"AFB7025C", -- 00001174 - X"AFB60258", -- 00001178 - X"AFB50254", -- 0000117C - X"AFB40250", -- 00001180 - X"0FF0056B", -- 00001184 - X"AFB3024C", -- 00001188 - X"3C036000", -- 0000118C - X"36220004", -- 00001190 - X"3463B1FF", -- 00001194 - X"AC430000", -- 00001198 - X"3C022000", -- 0000119C - X"27B20020", -- 000011A0 - X"34421000", -- 000011A4 - X"AE220000", -- 000011A8 - X"02402021", -- 000011AC - X"3C05A400", -- 000011B0 - X"8E300000", -- 000011B4 - X"0FF002EB", -- 000011B8 - X"00000000", -- 000011BC - X"04410004", -- 000011C0 - X"00102C02", -- 000011C4 - X"3C04BFC0", -- 000011C8 - X"0BF00494", -- 000011CC - X"248416A4", -- 000011D0 - X"02402021", -- 000011D4 - X"0FF00358", -- 000011D8 - X"30A5007F", -- 000011DC - X"00409021", -- 000011E0 - X"8E220000", -- 000011E4 - X"00000000", -- 000011E8 - X"00021602", -- 000011EC - X"30420008", -- 000011F0 - X"14400044", -- 000011F4 - X"3C11BFC0", -- 000011F8 - X"0FF000B0", -- 000011FC - X"26241758", -- 00001200 - X"3C02A400", -- 00001204 - X"02428021", -- 00001208 - X"8E030000", -- 0000120C - X"3C023149", -- 00001210 - X"3442464A", -- 00001214 - X"10620011", -- 00001218 - X"3C024A46", -- 0000121C - X"34424931", -- 00001220 - X"1062000E", -- 00001224 - X"00000000", -- 00001228 - X"0FF000B0", -- 0000122C - X"26241758", -- 00001230 - X"3C04BFC0", -- 00001234 - X"0FF000B0", -- 00001238 - X"248416CC", -- 0000123C - X"0FF000E8", -- 00001240 - X"02402021", -- 00001244 - X"3C04BFC0", -- 00001248 - X"248416E4", -- 0000124C - X"0FF000B0", -- 00001250 - X"00000000", -- 00001254 - X"0BF0055F", -- 00001258 - X"24020001", -- 0000125C - X"3C04BFC0", -- 00001260 - X"0FF000B0", -- 00001264 - X"248416F0", -- 00001268 - X"0FF000E8", -- 0000126C - X"02402021", -- 00001270 - X"3C04BFC0", -- 00001274 - X"0FF000B0", -- 00001278 - X"24841714", -- 0000127C - X"8E02000C", -- 00001280 - X"8E110004", -- 00001284 - X"00024082", -- 00001288 - X"8E070008", -- 0000128C - X"00002021", -- 00001290 - X"0BF004AA", -- 00001294 - X"00001821", -- 00001298 - X"8CC20000", -- 0000129C - X"00000000", -- 000012A0 - X"ACA20000", -- 000012A4 - X"0088102B", -- 000012A8 - X"00673021", -- 000012AC - X"00712821", -- 000012B0 - X"24840001", -- 000012B4 - X"1440FFF8", -- 000012B8 - X"24630004", -- 000012BC - X"3C04BFC0", -- 000012C0 - X"0FF000B0", -- 000012C4 - X"2484171C", -- 000012C8 - X"3C04BFC0", -- 000012CC - X"0FF000B0", -- 000012D0 - X"24841724", -- 000012D4 - X"8E040004", -- 000012D8 - X"0FF000E8", -- 000012DC - X"00000000", -- 000012E0 - X"3C04BFC0", -- 000012E4 - X"0FF000B0", -- 000012E8 - X"24841758", -- 000012EC - X"3C1A1000", -- 000012F0 - X"409A6000", -- 000012F4 - X"02200008", -- 000012F8 - X"42000010", -- 000012FC - X"0BF0055F", -- 00001300 - X"00001021", -- 00001304 - X"0FF000B0", -- 00001308 - X"26241758", -- 0000130C - X"3C04BFC0", -- 00001310 - X"0FF000B0", -- 00001314 - X"24841730", -- 00001318 - X"3C024000", -- 0000131C - X"3C034010", -- 00001320 - X"AC400000", -- 00001324 - X"24420004", -- 00001328 - X"1443FFFD", -- 0000132C - X"00009821", -- 00001330 - X"3C02BFC0", -- 00001334 - X"245516C8", -- 00001338 - X"3C02BFC0", -- 0000133C - X"2456171C", -- 00001340 - X"3C02BFC0", -- 00001344 - X"245E17D0", -- 00001348 - X"3C02BFC0", -- 0000134C - X"245717F0", -- 00001350 - X"3C04BFC0", -- 00001354 - X"0FF000B0", -- 00001358 - X"24841750", -- 0000135C - X"3C14BFC0", -- 00001360 - X"27B00040", -- 00001364 - X"0FF00430", -- 00001368 - X"02002021", -- 0000136C - X"00403021", -- 00001370 - X"02002821", -- 00001374 - X"27A40010", -- 00001378 - X"0FF00384", -- 0000137C - X"00408821", -- 00001380 - X"00401821", -- 00001384 - X"24020002", -- 00001388 - X"10620005", -- 0000138C - X"24020004", -- 00001390 - X"1462FFEF", -- 00001394 - X"00000000", -- 00001398 - X"0BF004FE", -- 0000139C - X"3C04BFC0", -- 000013A0 - X"8FA50010", -- 000013A4 - X"8FA60014", -- 000013A8 - X"0BF004F3", -- 000013AC - X"00001821", -- 000013B0 - X"8FA2001C", -- 000013B4 - X"00000000", -- 000013B8 - X"00431021", -- 000013BC - X"90420000", -- 000013C0 - X"24630001", -- 000013C4 - X"A0820000", -- 000013C8 - X"8FA20014", -- 000013CC - X"00000000", -- 000013D0 - X"0062102B", -- 000013D4 - X"1440FFF6", -- 000013D8 - X"00652021", -- 000013DC - X"00C51821", -- 000013E0 - X"0263102B", -- 000013E4 - X"10400060", -- 000013E8 - X"02208021", -- 000013EC - X"0BF0055B", -- 000013F0 - X"00609821", -- 000013F4 - X"0FF000B0", -- 000013F8 - X"24841754", -- 000013FC - X"8FA60010", -- 00001400 - X"26470100", -- 00001404 - X"02661823", -- 00001408 - X"27B10020", -- 0000140C - X"3C024A46", -- 00001410 - X"00E32821", -- 00001414 - X"02202021", -- 00001418 - X"34424931", -- 0000141C - X"AFA60144", -- 00001420 - X"AFA3014C", -- 00001424 - X"AFA70148", -- 00001428 - X"0FF00364", -- 0000142C - X"AFA20140", -- 00001430 - X"3C04BFC0", -- 00001434 - X"2484175C", -- 00001438 - X"0FF000B0", -- 0000143C - X"AFA20150", -- 00001440 - X"8FA4014C", -- 00001444 - X"0FF000E8", -- 00001448 - X"00000000", -- 0000144C - X"0FF000B0", -- 00001450 - X"02A02021", -- 00001454 - X"3C04BFC0", -- 00001458 - X"0FF000B0", -- 0000145C - X"24841778", -- 00001460 - X"0FF000E8", -- 00001464 - X"02402021", -- 00001468 - X"0FF000B0", -- 0000146C - X"02A02021", -- 00001470 - X"3C04BFC0", -- 00001474 - X"0FF000B0", -- 00001478 - X"24841794", -- 0000147C - X"8FA40150", -- 00001480 - X"0FF000E8", -- 00001484 - X"00000000", -- 00001488 - X"0FF000B0", -- 0000148C - X"02A02021", -- 00001490 - X"3C04BFC0", -- 00001494 - X"0FF000B0", -- 00001498 - X"248417B0", -- 0000149C - X"8FA6014C", -- 000014A0 - X"02202021", -- 000014A4 - X"24C60100", -- 000014A8 - X"0FF00304", -- 000014AC - X"02402821", -- 000014B0 - X"0440001F", -- 000014B4 - X"00408021", -- 000014B8 - X"0FF000B0", -- 000014BC - X"02C02021", -- 000014C0 - X"0FF000B0", -- 000014C4 - X"03C02021", -- 000014C8 - X"02202021", -- 000014CC - X"02402821", -- 000014D0 - X"27A60140", -- 000014D4 - X"0FF00334", -- 000014D8 - X"24070100", -- 000014DC - X"04400014", -- 000014E0 - X"00408021", -- 000014E4 - X"8FA50148", -- 000014E8 - X"8FA60144", -- 000014EC - X"8FA7014C", -- 000014F0 - X"0FF00334", -- 000014F4 - X"02202021", -- 000014F8 - X"0440000D", -- 000014FC - X"00408021", -- 00001500 - X"0FF000B0", -- 00001504 - X"02C02021", -- 00001508 - X"3C04BFC0", -- 0000150C - X"0FF000B0", -- 00001510 - X"248417E0", -- 00001514 - X"8FA50148", -- 00001518 - X"8FA60144", -- 0000151C - X"8FA7014C", -- 00001520 - X"0FF0033C", -- 00001524 - X"02202021", -- 00001528 - X"0441000A", -- 0000152C - X"00408021", -- 00001530 - X"0FF000B0", -- 00001534 - X"268417C0", -- 00001538 - X"0FF000E8", -- 0000153C - X"02002021", -- 00001540 - X"3C04BFC0", -- 00001544 - X"0FF000B0", -- 00001548 - X"248417CC", -- 0000154C - X"0BF0055B", -- 00001550 - X"00000000", -- 00001554 - X"0FF000B0", -- 00001558 - X"02E02021", -- 0000155C - X"3C02BFC0", -- 00001560 - X"00400008", -- 00001564 - X"00000000", -- 00001568 - X"0601FF7E", -- 0000156C - X"27B00040", -- 00001570 - X"0BF004D6", -- 00001574 - X"3C04BFC0", -- 00001578 - X"8FBF0264", -- 0000157C - X"8FBE0260", -- 00001580 - X"8FB7025C", -- 00001584 - X"8FB60258", -- 00001588 - X"8FB50254", -- 0000158C - X"8FB40250", -- 00001590 - X"8FB3024C", -- 00001594 - X"8FB20248", -- 00001598 - X"8FB10244", -- 0000159C - X"8FB00240", -- 000015A0 - X"03E00008", -- 000015A4 - X"27BD0268", -- 000015A8 - X"2CC20010", -- 000015AC - X"00804821", -- 000015B0 - X"1440002D", -- 000015B4 - X"00804021", -- 000015B8 - X"30870003", -- 000015BC - X"10E0000E", -- 000015C0 - X"24820004", -- 000015C4 - X"00052600", -- 000015C8 - X"00471023", -- 000015CC - X"00042603", -- 000015D0 - X"01201821", -- 000015D4 - X"A0640000", -- 000015D8 - X"24630001", -- 000015DC - X"1462FFFD", -- 000015E0 - X"00000000", -- 000015E4 - X"00071027", -- 000015E8 - X"24C3FFFB", -- 000015EC - X"24440005", -- 000015F0 - X"00623023", -- 000015F4 - X"01244021", -- 000015F8 - X"30A500FF", -- 000015FC - X"01003821", -- 00001600 - X"10A00005", -- 00001604 - X"00A01821", -- 00001608 - X"00051200", -- 0000160C - X"00451025", -- 00001610 - X"00021C00", -- 00001614 - X"00621825", -- 00001618 - X"000610C2", -- 0000161C - X"1040001C", -- 00001620 - X"30C60007", -- 00001624 - X"01002021", -- 00001628 - X"00403821", -- 0000162C - X"24E7FFFF", -- 00001630 - X"AC830000", -- 00001634 - X"AC830004", -- 00001638 - X"14E0FFFC", -- 0000163C - X"24840008", -- 00001640 - X"000210C0", -- 00001644 - X"01023821", -- 00001648 - X"00E02021", -- 0000164C - X"2CC20004", -- 00001650 - X"14400005", -- 00001654 - X"00804021", -- 00001658 - X"ACE30000", -- 0000165C - X"24E40004", -- 00001660 - X"24C6FFFC", -- 00001664 - X"00804021", -- 00001668 - X"10C00007", -- 0000166C - X"00000000", -- 00001670 - X"00051600", -- 00001674 - X"00021603", -- 00001678 - X"24C6FFFF", -- 0000167C - X"A1020000", -- 00001680 - X"14C0FFFD", -- 00001684 - X"25080001", -- 00001688 - X"03E00008", -- 0000168C - X"01201021", -- 00001690 - X"0BF00594", -- 00001694 - X"01002021", -- 00001698 - X"3A200000", -- 0000169C - X"20202000", -- 000016A0 - X"43616E6E", -- 000016A4 - X"6F742066", -- 000016A8 - X"696E6420", -- 000016AC - X"666C6173", -- 000016B0 - X"68206465", -- 000016B4 - X"76696365", -- 000016B8 - X"2E204578", -- 000016BC - X"6974206E", -- 000016C0 - X"6F77210A", -- 000016C4 - X"0A000000", -- 000016C8 - X"496E7661", -- 000016CC - X"6C696420", -- 000016D0 - X"696D6167", -- 000016D4 - X"6520666F", -- 000016D8 - X"756E6420", -- 000016DC - X"61742000", -- 000016E0 - X"2E204162", -- 000016E4 - X"6F72742E", -- 000016E8 - X"0A000000", -- 000016EC - X"426F6F74", -- 000016F0 - X"696E6720", -- 000016F4 - X"6170706C", -- 000016F8 - X"69636174", -- 000016FC - X"696F6E20", -- 00001700 - X"66726F6D", -- 00001704 - X"20666C61", -- 00001708 - X"73682028", -- 0000170C - X"00000000", -- 00001710 - X"292E2E2E", -- 00001714 - X"00000000", -- 00001718 - X"646F6E65", -- 0000171C - X"0A000000", -- 00001720 - X"45786563", -- 00001724 - X"75746520", -- 00001728 - X"61742000", -- 0000172C - X"52656164", -- 00001730 - X"696E6720", -- 00001734 - X"4845582D", -- 00001738 - X"5265636F", -- 0000173C - X"72642066", -- 00001740 - X"726F6D20", -- 00001744 - X"55415254", -- 00001748 - X"2E2E0000", -- 0000174C - X"2E000000", -- 00001750 - X"646F6E65", -- 00001754 - X"0A0A0000", -- 00001758 - X"53697A65", -- 0000175C - X"206F6620", -- 00001760 - X"6170706C", -- 00001764 - X"69636174", -- 00001768 - X"696F6E20", -- 0000176C - X"2020203A", -- 00001770 - X"20000000", -- 00001774 - X"50726F67", -- 00001778 - X"72616D6D", -- 0000177C - X"696E6720", -- 00001780 - X"666C6173", -- 00001784 - X"68206174", -- 00001788 - X"2020203A", -- 0000178C - X"20000000", -- 00001790 - X"4E657874", -- 00001794 - X"20667265", -- 00001798 - X"6520666C", -- 0000179C - X"61736820", -- 000017A0 - X"6F666673", -- 000017A4 - X"6574203A", -- 000017A8 - X"20000000", -- 000017AC - X"466C6173", -- 000017B0 - X"68206572", -- 000017B4 - X"6173652E", -- 000017B8 - X"2E2E0000", -- 000017BC - X"6661696C", -- 000017C0 - X"65642028", -- 000017C4 - X"00000000", -- 000017C8 - X"290A0000", -- 000017CC - X"466C6173", -- 000017D0 - X"68207772", -- 000017D4 - X"6974652E", -- 000017D8 - X"2E2E0000", -- 000017DC - X"466C6173", -- 000017E0 - X"68207665", -- 000017E4 - X"72696679", -- 000017E8 - X"2E2E2E00", -- 000017EC - X"70617373", -- 000017F0 - X"65640A00", -- 000017F4 - X"00000000", -- 000017F8 - X"00000000", -- 000017FC - X"00000000", -- 00001800 - X"00000000", -- 00001804 - X"00000000", -- 00001808 - X"00000000", -- 0000180C - X"00000000", -- 00001810 - X"00000000", -- 00001814 - X"00000000", -- 00001818 - X"00000000", -- 0000181C - X"00000000", -- 00001820 - X"00000000", -- 00001824 - X"00000000", -- 00001828 - X"00000000", -- 0000182C - X"00000000", -- 00001830 - X"00000000", -- 00001834 - X"00000000", -- 00001838 - X"00000000", -- 0000183C - X"00000000", -- 00001840 - X"00000000", -- 00001844 - X"00000000", -- 00001848 - X"00000000", -- 0000184C - X"00000000", -- 00001850 - X"00000000", -- 00001854 - X"00000000", -- 00001858 - X"00000000", -- 0000185C - X"00000000", -- 00001860 - X"00000000", -- 00001864 - X"00000000", -- 00001868 - X"00000000", -- 0000186C - X"00000000", -- 00001870 - X"00000000", -- 00001874 - X"00000000", -- 00001878 - X"00000000", -- 0000187C - X"00000000", -- 00001880 - X"00000000", -- 00001884 - X"00000000", -- 00001888 - X"00000000", -- 0000188C - X"00000000", -- 00001890 - X"00000000", -- 00001894 - X"00000000", -- 00001898 - X"00000000", -- 0000189C - X"00000000", -- 000018A0 - X"00000000", -- 000018A4 - X"00000000", -- 000018A8 - X"00000000", -- 000018AC - X"00000000", -- 000018B0 - X"00000000", -- 000018B4 - X"00000000", -- 000018B8 - X"00000000", -- 000018BC - X"00000000", -- 000018C0 - X"00000000", -- 000018C4 - X"00000000", -- 000018C8 - X"00000000", -- 000018CC - X"00000000", -- 000018D0 - X"00000000", -- 000018D4 - X"00000000", -- 000018D8 - X"00000000", -- 000018DC - X"00000000", -- 000018E0 - X"00000000", -- 000018E4 - X"00000000", -- 000018E8 - X"00000000", -- 000018EC - X"00000000", -- 000018F0 - X"00000000", -- 000018F4 - X"00000000", -- 000018F8 - X"00000000", -- 000018FC - X"00000000", -- 00001900 - X"00000000", -- 00001904 - X"00000000", -- 00001908 - X"00000000", -- 0000190C - X"00000000", -- 00001910 - X"00000000", -- 00001914 - X"00000000", -- 00001918 - X"00000000", -- 0000191C - X"00000000", -- 00001920 - X"00000000", -- 00001924 - X"00000000", -- 00001928 - X"00000000", -- 0000192C - X"00000000", -- 00001930 - X"00000000", -- 00001934 - X"00000000", -- 00001938 - X"00000000", -- 0000193C - X"00000000", -- 00001940 - X"00000000", -- 00001944 - X"00000000", -- 00001948 - X"00000000", -- 0000194C - X"00000000", -- 00001950 - X"00000000", -- 00001954 - X"00000000", -- 00001958 - X"00000000", -- 0000195C - X"00000000", -- 00001960 - X"00000000", -- 00001964 - X"00000000", -- 00001968 - X"00000000", -- 0000196C - X"00000000", -- 00001970 - X"00000000", -- 00001974 - X"00000000", -- 00001978 - X"00000000", -- 0000197C - X"00000000", -- 00001980 - X"00000000", -- 00001984 - X"00000000", -- 00001988 - X"00000000", -- 0000198C - X"00000000", -- 00001990 - X"00000000", -- 00001994 - X"00000000", -- 00001998 - X"00000000", -- 0000199C - X"00000000", -- 000019A0 - X"00000000", -- 000019A4 - X"00000000", -- 000019A8 - X"00000000", -- 000019AC - X"00000000", -- 000019B0 - X"00000000", -- 000019B4 - X"00000000", -- 000019B8 - X"00000000", -- 000019BC - X"00000000", -- 000019C0 - X"00000000", -- 000019C4 - X"00000000", -- 000019C8 - X"00000000", -- 000019CC - X"00000000", -- 000019D0 - X"00000000", -- 000019D4 - X"00000000", -- 000019D8 - X"00000000", -- 000019DC - X"00000000", -- 000019E0 - X"00000000", -- 000019E4 - X"00000000", -- 000019E8 - X"00000000", -- 000019EC - X"00000000", -- 000019F0 - X"00000000", -- 000019F4 - X"00000000", -- 000019F8 - X"00000000", -- 000019FC - X"00000000", -- 00001A00 - X"00000000", -- 00001A04 - X"00000000", -- 00001A08 - X"00000000", -- 00001A0C - X"00000000", -- 00001A10 - X"00000000", -- 00001A14 - X"00000000", -- 00001A18 - X"00000000", -- 00001A1C - X"00000000", -- 00001A20 - X"00000000", -- 00001A24 - X"00000000", -- 00001A28 - X"00000000", -- 00001A2C - X"00000000", -- 00001A30 - X"00000000", -- 00001A34 - X"00000000", -- 00001A38 - X"00000000", -- 00001A3C - X"00000000", -- 00001A40 - X"00000000", -- 00001A44 - X"00000000", -- 00001A48 - X"00000000", -- 00001A4C - X"00000000", -- 00001A50 - X"00000000", -- 00001A54 - X"00000000", -- 00001A58 - X"00000000", -- 00001A5C - X"00000000", -- 00001A60 - X"00000000", -- 00001A64 - X"00000000", -- 00001A68 - X"00000000", -- 00001A6C - X"00000000", -- 00001A70 - X"00000000", -- 00001A74 - X"00000000", -- 00001A78 - X"00000000", -- 00001A7C - X"00000000", -- 00001A80 - X"00000000", -- 00001A84 - X"00000000", -- 00001A88 - X"00000000", -- 00001A8C - X"00000000", -- 00001A90 - X"00000000", -- 00001A94 - X"00000000", -- 00001A98 - X"00000000", -- 00001A9C - X"00000000", -- 00001AA0 - X"00000000", -- 00001AA4 - X"00000000", -- 00001AA8 - X"00000000", -- 00001AAC - X"00000000", -- 00001AB0 - X"00000000", -- 00001AB4 - X"00000000", -- 00001AB8 - X"00000000", -- 00001ABC - X"00000000", -- 00001AC0 - X"00000000", -- 00001AC4 - X"00000000", -- 00001AC8 - X"00000000", -- 00001ACC - X"00000000", -- 00001AD0 - X"00000000", -- 00001AD4 - X"00000000", -- 00001AD8 - X"00000000", -- 00001ADC - X"00000000", -- 00001AE0 - X"00000000", -- 00001AE4 - X"00000000", -- 00001AE8 - X"00000000", -- 00001AEC - X"00000000", -- 00001AF0 - X"00000000", -- 00001AF4 - X"00000000", -- 00001AF8 - X"00000000", -- 00001AFC - X"00000000", -- 00001B00 - X"00000000", -- 00001B04 - X"00000000", -- 00001B08 - X"00000000", -- 00001B0C - X"00000000", -- 00001B10 - X"00000000", -- 00001B14 - X"00000000", -- 00001B18 - X"00000000", -- 00001B1C - X"00000000", -- 00001B20 - X"00000000", -- 00001B24 - X"00000000", -- 00001B28 - X"00000000", -- 00001B2C - X"00000000", -- 00001B30 - X"00000000", -- 00001B34 - X"00000000", -- 00001B38 - X"00000000", -- 00001B3C - X"00000000", -- 00001B40 - X"00000000", -- 00001B44 - X"00000000", -- 00001B48 - X"00000000", -- 00001B4C - X"00000000", -- 00001B50 - X"00000000", -- 00001B54 - X"00000000", -- 00001B58 - X"00000000", -- 00001B5C - X"00000000", -- 00001B60 - X"00000000", -- 00001B64 - X"00000000", -- 00001B68 - X"00000000", -- 00001B6C - X"00000000", -- 00001B70 - X"00000000", -- 00001B74 - X"00000000", -- 00001B78 - X"00000000", -- 00001B7C - X"00000000", -- 00001B80 - X"00000000", -- 00001B84 - X"00000000", -- 00001B88 - X"00000000", -- 00001B8C - X"00000000", -- 00001B90 - X"00000000", -- 00001B94 - X"00000000", -- 00001B98 - X"00000000", -- 00001B9C - X"00000000", -- 00001BA0 - X"00000000", -- 00001BA4 - X"00000000", -- 00001BA8 - X"00000000", -- 00001BAC - X"00000000", -- 00001BB0 - X"00000000", -- 00001BB4 - X"00000000", -- 00001BB8 - X"00000000", -- 00001BBC - X"00000000", -- 00001BC0 - X"00000000", -- 00001BC4 - X"00000000", -- 00001BC8 - X"00000000", -- 00001BCC - X"00000000", -- 00001BD0 - X"00000000", -- 00001BD4 - X"00000000", -- 00001BD8 - X"00000000", -- 00001BDC - X"00000000", -- 00001BE0 - X"00000000", -- 00001BE4 - X"00000000", -- 00001BE8 - X"00000000", -- 00001BEC - X"00000000", -- 00001BF0 - X"00000000", -- 00001BF4 - X"00000000", -- 00001BF8 - X"00000000", -- 00001BFC - X"00000000", -- 00001C00 - X"00000000", -- 00001C04 - X"00000000", -- 00001C08 - X"00000000", -- 00001C0C - X"00000000", -- 00001C10 - X"00000000", -- 00001C14 - X"00000000", -- 00001C18 - X"00000000", -- 00001C1C - X"00000000", -- 00001C20 - X"00000000", -- 00001C24 - X"00000000", -- 00001C28 - X"00000000", -- 00001C2C - X"00000000", -- 00001C30 - X"00000000", -- 00001C34 - X"00000000", -- 00001C38 - X"00000000", -- 00001C3C - X"00000000", -- 00001C40 - X"00000000", -- 00001C44 - X"00000000", -- 00001C48 - X"00000000", -- 00001C4C - X"00000000", -- 00001C50 - X"00000000", -- 00001C54 - X"00000000", -- 00001C58 - X"00000000", -- 00001C5C - X"00000000", -- 00001C60 - X"00000000", -- 00001C64 - X"00000000", -- 00001C68 - X"00000000", -- 00001C6C - X"00000000", -- 00001C70 - X"00000000", -- 00001C74 - X"00000000", -- 00001C78 - X"00000000", -- 00001C7C - X"00000000", -- 00001C80 - X"00000000", -- 00001C84 - X"00000000", -- 00001C88 - X"00000000", -- 00001C8C - X"00000000", -- 00001C90 - X"00000000", -- 00001C94 - X"00000000", -- 00001C98 - X"00000000", -- 00001C9C - X"00000000", -- 00001CA0 - X"00000000", -- 00001CA4 - X"00000000", -- 00001CA8 - X"00000000", -- 00001CAC - X"00000000", -- 00001CB0 - X"00000000", -- 00001CB4 - X"00000000", -- 00001CB8 - X"00000000", -- 00001CBC - X"00000000", -- 00001CC0 - X"00000000", -- 00001CC4 - X"00000000", -- 00001CC8 - X"00000000", -- 00001CCC - X"00000000", -- 00001CD0 - X"00000000", -- 00001CD4 - X"00000000", -- 00001CD8 - X"00000000", -- 00001CDC - X"00000000", -- 00001CE0 - X"00000000", -- 00001CE4 - X"00000000", -- 00001CE8 - X"00000000", -- 00001CEC - X"00000000", -- 00001CF0 - X"00000000", -- 00001CF4 - X"00000000", -- 00001CF8 - X"00000000", -- 00001CFC - X"00000000", -- 00001D00 - X"00000000", -- 00001D04 - X"00000000", -- 00001D08 - X"00000000", -- 00001D0C - X"00000000", -- 00001D10 - X"00000000", -- 00001D14 - X"00000000", -- 00001D18 - X"00000000", -- 00001D1C - X"00000000", -- 00001D20 - X"00000000", -- 00001D24 - X"00000000", -- 00001D28 - X"00000000", -- 00001D2C - X"00000000", -- 00001D30 - X"00000000", -- 00001D34 - X"00000000", -- 00001D38 - X"00000000", -- 00001D3C - X"00000000", -- 00001D40 - X"00000000", -- 00001D44 - X"00000000", -- 00001D48 - X"00000000", -- 00001D4C - X"00000000", -- 00001D50 - X"00000000", -- 00001D54 - X"00000000", -- 00001D58 - X"00000000", -- 00001D5C - X"00000000", -- 00001D60 - X"00000000", -- 00001D64 - X"00000000", -- 00001D68 - X"00000000", -- 00001D6C - X"00000000", -- 00001D70 - X"00000000", -- 00001D74 - X"00000000", -- 00001D78 - X"00000000", -- 00001D7C - X"00000000", -- 00001D80 - X"00000000", -- 00001D84 - X"00000000", -- 00001D88 - X"00000000", -- 00001D8C - X"00000000", -- 00001D90 - X"00000000", -- 00001D94 - X"00000000", -- 00001D98 - X"00000000", -- 00001D9C - X"00000000", -- 00001DA0 - X"00000000", -- 00001DA4 - X"00000000", -- 00001DA8 - X"00000000", -- 00001DAC - X"00000000", -- 00001DB0 - X"00000000", -- 00001DB4 - X"00000000", -- 00001DB8 - X"00000000", -- 00001DBC - X"00000000", -- 00001DC0 - X"00000000", -- 00001DC4 - X"00000000", -- 00001DC8 - X"00000000", -- 00001DCC - X"00000000", -- 00001DD0 - X"00000000", -- 00001DD4 - X"00000000", -- 00001DD8 - X"00000000", -- 00001DDC - X"00000000", -- 00001DE0 - X"00000000", -- 00001DE4 - X"00000000", -- 00001DE8 - X"00000000", -- 00001DEC - X"00000000", -- 00001DF0 - X"00000000", -- 00001DF4 - X"00000000", -- 00001DF8 - X"00000000", -- 00001DFC - X"00000000", -- 00001E00 - X"00000000", -- 00001E04 - X"00000000", -- 00001E08 - X"00000000", -- 00001E0C - X"00000000", -- 00001E10 - X"00000000", -- 00001E14 - X"00000000", -- 00001E18 - X"00000000", -- 00001E1C - X"00000000", -- 00001E20 - X"00000000", -- 00001E24 - X"00000000", -- 00001E28 - X"00000000", -- 00001E2C - X"00000000", -- 00001E30 - X"00000000", -- 00001E34 - X"00000000", -- 00001E38 - X"00000000", -- 00001E3C - X"00000000", -- 00001E40 - X"00000000", -- 00001E44 - X"00000000", -- 00001E48 - X"00000000", -- 00001E4C - X"00000000", -- 00001E50 - X"00000000", -- 00001E54 - X"00000000", -- 00001E58 - X"00000000", -- 00001E5C - X"00000000", -- 00001E60 - X"00000000", -- 00001E64 - X"00000000", -- 00001E68 - X"00000000", -- 00001E6C - X"00000000", -- 00001E70 - X"00000000", -- 00001E74 - X"00000000", -- 00001E78 - X"00000000", -- 00001E7C - X"00000000", -- 00001E80 - X"00000000", -- 00001E84 - X"00000000", -- 00001E88 - X"00000000", -- 00001E8C - X"00000000", -- 00001E90 - X"00000000", -- 00001E94 - X"00000000", -- 00001E98 - X"00000000", -- 00001E9C - X"00000000", -- 00001EA0 - X"00000000", -- 00001EA4 - X"00000000", -- 00001EA8 - X"00000000", -- 00001EAC - X"00000000", -- 00001EB0 - X"00000000", -- 00001EB4 - X"00000000", -- 00001EB8 - X"00000000", -- 00001EBC - X"00000000", -- 00001EC0 - X"00000000", -- 00001EC4 - X"00000000", -- 00001EC8 - X"00000000", -- 00001ECC - X"00000000", -- 00001ED0 - X"00000000", -- 00001ED4 - X"00000000", -- 00001ED8 - X"00000000", -- 00001EDC - X"00000000", -- 00001EE0 - X"00000000", -- 00001EE4 - X"00000000", -- 00001EE8 - X"00000000", -- 00001EEC - X"00000000", -- 00001EF0 - X"00000000", -- 00001EF4 - X"00000000", -- 00001EF8 - X"00000000", -- 00001EFC - X"00000000", -- 00001F00 - X"00000000", -- 00001F04 - X"00000000", -- 00001F08 - X"00000000", -- 00001F0C - X"00000000", -- 00001F10 - X"00000000", -- 00001F14 - X"00000000", -- 00001F18 - X"00000000", -- 00001F1C - X"00000000", -- 00001F20 - X"00000000", -- 00001F24 - X"00000000", -- 00001F28 - X"00000000", -- 00001F2C - X"00000000", -- 00001F30 - X"00000000", -- 00001F34 - X"00000000", -- 00001F38 - X"00000000", -- 00001F3C - X"00000000", -- 00001F40 - X"00000000", -- 00001F44 - X"00000000", -- 00001F48 - X"00000000", -- 00001F4C - X"00000000", -- 00001F50 - X"00000000", -- 00001F54 - X"00000000", -- 00001F58 - X"00000000", -- 00001F5C - X"00000000", -- 00001F60 - X"00000000", -- 00001F64 - X"00000000", -- 00001F68 - X"00000000", -- 00001F6C - X"00000000", -- 00001F70 - X"00000000", -- 00001F74 - X"00000000", -- 00001F78 - X"00000000", -- 00001F7C - X"00000000", -- 00001F80 - X"00000000", -- 00001F84 - X"00000000", -- 00001F88 - X"00000000", -- 00001F8C - X"00000000", -- 00001F90 - X"00000000", -- 00001F94 - X"00000000", -- 00001F98 - X"00000000", -- 00001F9C - X"00000000", -- 00001FA0 - X"00000000", -- 00001FA4 - X"00000000", -- 00001FA8 - X"00000000", -- 00001FAC - X"00000000", -- 00001FB0 - X"00000000", -- 00001FB4 - X"00000000", -- 00001FB8 - X"00000000", -- 00001FBC - X"00000000", -- 00001FC0 - X"00000000", -- 00001FC4 - X"00000000", -- 00001FC8 - X"00000000", -- 00001FCC - X"00000000", -- 00001FD0 - X"00000000", -- 00001FD4 - X"00000000", -- 00001FD8 - X"00000000", -- 00001FDC - X"00000000", -- 00001FE0 - X"00000000", -- 00001FE4 - X"00000000", -- 00001FE8 - X"00000000", -- 00001FEC - X"00000000", -- 00001FF0 - X"00000000", -- 00001FF4 - X"00000000", -- 00001FF8 - X"00000000" -- 00001FFC - ); - -begin - -PROM_READ: - process(clk) - begin - if rising_edge(clk) and ce = '1' then - dout <= word_array(to_integer(addr(12 downto 2))); - end if; - end process; - -end data; diff --git a/lib/CPUs/MIPS/src/bootloader.dis b/lib/CPUs/MIPS/src/bootloader.dis deleted file mode 100644 index 40da0e3..0000000 --- a/lib/CPUs/MIPS/src/bootloader.dis +++ /dev/null @@ -1,1467 +0,0 @@ - -bootloader.elf: file format elf32-bigmips - - -Disassembly of section .init: - -bfc00000 <__entry>: -bfc00000: 3c1d8000 lui sp,0x8000 -bfc00004: 27bdeff0 addiu sp,sp,-4112 -bfc00008: 3c1a1040 lui k0,0x1040 -bfc0000c: 375a000c ori k0,k0,0xc -bfc00010: 409a6000 mtc0 k0,c0_sr -bfc00014: 241a0000 li k0,0 -bfc00018: 409a6800 mtc0 k0,c0_cause -bfc0001c: 401a7800 mfc0 k0,c0_prid -bfc00020: 00000000 nop -bfc00024: 409af800 mtc0 k0,$31 -bfc00028: 42000020 c0 0x20 -bfc0002c: 42000022 c0 0x22 -bfc00030: 3c1abfc0 lui k0,0xbfc0 -bfc00034: 275a005c addiu k0,k0,92 -bfc00038: 0340f809 jalr k0 -bfc0003c: 00000000 nop -bfc00040: 3c1abfc0 lui k0,0xbfc0 -bfc00044: 275a114c addiu k0,k0,4428 -bfc00048: 0340f809 jalr k0 -bfc0004c: 00000000 nop - -bfc00050 <_terminate>: -bfc00050: 00000000 nop -bfc00054: 0bf00014 j bfc00050 <_terminate> -bfc00058: 00000000 nop - -bfc0005c <_init>: -bfc0005c: 3c1aa001 275a0008 241b000d af5b0000 <...'Z..$....[.. -bfc0006c: 03e00008 .... - -Disassembly of section .ktext: - -bfc00180 <_exc_handler>: -bfc00180: 401a6800 mfc0 k0,c0_cause -bfc00184: 3c1bc000 lui k1,0xc000 -bfc00188: 001ad082 srl k0,k0,0x2 -bfc0018c: 335a000f andi k0,k0,0xf -bfc00190: 035bd025 or k0,k0,k1 -bfc00194: 3c1ba000 lui k1,0xa000 -bfc00198: 277b0000 addiu k1,k1,0 -bfc0019c: af7a0000 sw k0,0(k1) -bfc001a0: 401a6800 mfc0 k0,c0_cause -bfc001a4: 00000000 nop -bfc001a8: 001ad202 srl k0,k0,0x8 -bfc001ac: 335a00ff andi k0,k0,0xff -bfc001b0: 1740fffb bnez k0,bfc001a0 <_exc_handler+0x20> -bfc001b4: 00000000 nop -bfc001b8: 401a7000 mfc0 k0,c0_epc -bfc001bc: 00000000 nop -bfc001c0: 03400008 jr k0 -bfc001c4: 42000010 rfe - -Disassembly of section .text: - -bfc001c8 : -bfc001c8: 40026000 mfc0 v0,c0_sr -bfc001cc: 03e00008 jr ra -bfc001d0: 00000000 nop - -bfc001d4 : -bfc001d4: 40846000 mtc0 a0,c0_sr -bfc001d8: 03e00008 jr ra -bfc001dc: 00000000 nop - -bfc001e0 : -bfc001e0: 40026800 mfc0 v0,c0_cause -bfc001e4: 03e00008 jr ra -bfc001e8: 00000000 nop - -bfc001ec : -bfc001ec: 40846800 mtc0 a0,c0_cause -bfc001f0: 03e00008 jr ra -bfc001f4: 00000000 nop - -bfc001f8 : -bfc001f8: 40027800 mfc0 v0,c0_prid -bfc001fc: 03e00008 jr ra -bfc00200: 00000000 nop - -bfc00204 : -bfc00204: 3c02a001 lui v0,0xa001 -bfc00208: 34430004 ori v1,v0,0x4 -bfc0020c: 8c620000 lw v0,0(v1) -bfc00210: 00000000 nop -bfc00214: 30420010 andi v0,v0,0x10 -bfc00218: 1040fffc beqz v0,bfc0020c -bfc0021c: 3c02a001 lui v0,0xa001 -bfc00220: 8c420000 lw v0,0(v0) -bfc00224: 00000000 nop -bfc00228: 00021600 sll v0,v0,0x18 -bfc0022c: 03e00008 jr ra -bfc00230: 00021603 sra v0,v0,0x18 - -bfc00234 : -bfc00234: 00042600 sll a0,a0,0x18 -bfc00238: 3c02a001 lui v0,0xa001 -bfc0023c: 00042603 sra a0,a0,0x18 -bfc00240: 34430004 ori v1,v0,0x4 -bfc00244: 8c620000 lw v0,0(v1) -bfc00248: 00000000 nop -bfc0024c: 30420002 andi v0,v0,0x2 -bfc00250: 1440fffc bnez v0,bfc00244 -bfc00254: 3c02a001 lui v0,0xa001 -bfc00258: ac440000 sw a0,0(v0) -bfc0025c: 03e00008 jr ra -bfc00260: 00000000 nop - -bfc00264 <_putchar>: -bfc00264: 00042600 sll a0,a0,0x18 -bfc00268: 00042603 sra a0,a0,0x18 -bfc0026c: 2402000a li v0,10 -bfc00270: 1482000a bne a0,v0,bfc0029c <_putchar+0x38> -bfc00274: 3c02a001 lui v0,0xa001 -bfc00278: 34430004 ori v1,v0,0x4 -bfc0027c: 8c620000 lw v0,0(v1) -bfc00280: 00000000 nop -bfc00284: 30420002 andi v0,v0,0x2 -bfc00288: 1440fffc bnez v0,bfc0027c <_putchar+0x18> -bfc0028c: 3c02a001 lui v0,0xa001 -bfc00290: 2403000d li v1,13 -bfc00294: ac430000 sw v1,0(v0) -bfc00298: 3c02a001 lui v0,0xa001 -bfc0029c: 34430004 ori v1,v0,0x4 -bfc002a0: 8c620000 lw v0,0(v1) -bfc002a4: 00000000 nop -bfc002a8: 30420002 andi v0,v0,0x2 -bfc002ac: 1440fffc bnez v0,bfc002a0 <_putchar+0x3c> -bfc002b0: 3c02a001 lui v0,0xa001 -bfc002b4: ac440000 sw a0,0(v0) -bfc002b8: 03e00008 jr ra -bfc002bc: 00000000 nop - -bfc002c0 : -bfc002c0: 3c02a001 lui v0,0xa001 -bfc002c4: 34470004 ori a3,v0,0x4 -bfc002c8: 00802821 move a1,a0 -bfc002cc: 2409000a li t1,10 -bfc002d0: 3c06a001 lui a2,0xa001 -bfc002d4: 0bf000c6 j bfc00318 -bfc002d8: 2408000d li t0,13 -bfc002dc: 14690007 bne v1,t1,bfc002fc -bfc002e0: 00000000 nop -bfc002e4: 8ce20000 lw v0,0(a3) -bfc002e8: 00000000 nop -bfc002ec: 30420002 andi v0,v0,0x2 -bfc002f0: 1440fffc bnez v0,bfc002e4 -bfc002f4: 00000000 nop -bfc002f8: acc80000 sw t0,0(a2) -bfc002fc: 8ce20000 lw v0,0(a3) -bfc00300: 00000000 nop -bfc00304: 30420002 andi v0,v0,0x2 -bfc00308: 1440fffc bnez v0,bfc002fc -bfc0030c: 00000000 nop -bfc00310: acc30000 sw v1,0(a2) -bfc00314: 24a50001 addiu a1,a1,1 -bfc00318: 80a30000 lb v1,0(a1) -bfc0031c: 00000000 nop -bfc00320: 1460ffee bnez v1,bfc002dc -bfc00324: 00a41023 subu v0,a1,a0 -bfc00328: 03e00008 jr ra -bfc0032c: 00000000 nop - -bfc00330 : -bfc00330: 00042600 sll a0,a0,0x18 -bfc00334: 3c02a001 lui v0,0xa001 -bfc00338: 00042603 sra a0,a0,0x18 -bfc0033c: 344a0004 ori t2,v0,0x4 -bfc00340: 00003821 move a3,zero -bfc00344: 3c09a001 lui t1,0xa001 -bfc00348: 24080002 li t0,2 -bfc0034c: 308200ff andi v0,a0,0xff -bfc00350: 00022902 srl a1,v0,0x4 -bfc00354: 00041100 sll v0,a0,0x4 -bfc00358: 00022600 sll a0,v0,0x18 -bfc0035c: 2ca3000a sltiu v1,a1,10 -bfc00360: 00042603 sra a0,a0,0x18 -bfc00364: 14600002 bnez v1,bfc00370 -bfc00368: 24a60030 addiu a2,a1,48 -bfc0036c: 24a60037 addiu a2,a1,55 -bfc00370: 8d420000 lw v0,0(t2) -bfc00374: 00000000 nop -bfc00378: 30420002 andi v0,v0,0x2 -bfc0037c: 1440fffc bnez v0,bfc00370 -bfc00380: 00061600 sll v0,a2,0x18 -bfc00384: 00021603 sra v0,v0,0x18 -bfc00388: 24e70001 addiu a3,a3,1 -bfc0038c: ad220000 sw v0,0(t1) -bfc00390: 14e8ffef bne a3,t0,bfc00350 -bfc00394: 308200ff andi v0,a0,0xff -bfc00398: 03e00008 jr ra -bfc0039c: 00000000 nop - -bfc003a0 : -bfc003a0: 27bdffe0 addiu sp,sp,-32 -bfc003a4: afb20018 sw s2,24(sp) -bfc003a8: afb10014 sw s1,20(sp) -bfc003ac: afb00010 sw s0,16(sp) -bfc003b0: afbf001c sw ra,28(sp) -bfc003b4: 00808821 move s1,a0 -bfc003b8: 00008021 move s0,zero -bfc003bc: 24120004 li s2,4 -bfc003c0: 00112603 sra a0,s1,0x18 -bfc003c4: 0ff000cc jal bfc00330 -bfc003c8: 26100001 addiu s0,s0,1 -bfc003cc: 1612fffc bne s0,s2,bfc003c0 -bfc003d0: 00118a00 sll s1,s1,0x8 -bfc003d4: 8fbf001c lw ra,28(sp) -bfc003d8: 8fb20018 lw s2,24(sp) -bfc003dc: 8fb10014 lw s1,20(sp) -bfc003e0: 8fb00010 lw s0,16(sp) -bfc003e4: 03e00008 jr ra -bfc003e8: 27bd0020 addiu sp,sp,32 - -bfc003ec : -bfc003ec: 27bdffc8 addiu sp,sp,-56 -bfc003f0: afb60028 sw s6,40(sp) -bfc003f4: afbf0034 sw ra,52(sp) -bfc003f8: afbe0030 sw s8,48(sp) -bfc003fc: afb7002c sw s7,44(sp) -bfc00400: afb50024 sw s5,36(sp) -bfc00404: afb40020 sw s4,32(sp) -bfc00408: afb3001c sw s3,28(sp) -bfc0040c: afb20018 sw s2,24(sp) -bfc00410: afb10014 sw s1,20(sp) -bfc00414: afb00010 sw s0,16(sp) -bfc00418: 00801021 move v0,a0 -bfc0041c: 10a00002 beqz a1,bfc00428 -bfc00420: 00c0b021 move s6,a2 -bfc00424: 00002021 move a0,zero -bfc00428: 00409821 move s3,v0 -bfc0042c: 3c02a001 lui v0,0xa001 -bfc00430: 00e09021 move s2,a3 -bfc00434: 0080a821 move s5,a0 -bfc00438: 345e0004 ori s8,v0,0x4 -bfc0043c: 00e0a021 move s4,a3 -bfc00440: 3c17a001 lui s7,0xa001 -bfc00444: 0ff000e8 jal bfc003a0 -bfc00448: 02a02021 move a0,s5 -bfc0044c: 3c04bfc0 lui a0,0xbfc0 -bfc00450: 0ff000b0 jal bfc002c0 -bfc00454: 2484169c addiu a0,a0,5788 -bfc00458: 02608821 move s1,s3 -bfc0045c: 0bf00128 j bfc004a0 -bfc00460: 00008021 move s0,zero -bfc00464: 12400009 beqz s2,bfc0048c -bfc00468: 00000000 nop -bfc0046c: 82240000 lb a0,0(s1) -bfc00470: 0ff000cc jal bfc00330 -bfc00474: 2652ffff addiu s2,s2,-1 -bfc00478: 3c04bfc0 lui a0,0xbfc0 -bfc0047c: 0ff000b0 jal bfc002c0 -bfc00480: 24841774 addiu a0,a0,6004 -bfc00484: 0bf00128 j bfc004a0 -bfc00488: 26310001 addiu s1,s1,1 -bfc0048c: 3c04bfc0 lui a0,0xbfc0 -bfc00490: 0ff000b0 jal bfc002c0 -bfc00494: 248416a0 addiu a0,a0,5792 -bfc00498: 0bf0012c j bfc004b0 -bfc0049c: 3c04bfc0 lui a0,0xbfc0 -bfc004a0: 0216102a slt v0,s0,s6 -bfc004a4: 1440ffef bnez v0,bfc00464 -bfc004a8: 26100001 addiu s0,s0,1 -bfc004ac: 3c04bfc0 lui a0,0xbfc0 -bfc004b0: 0ff000b0 jal bfc002c0 -bfc004b4: 248416a0 addiu a0,a0,5792 -bfc004b8: 02602821 move a1,s3 -bfc004bc: 0bf00155 j bfc00554 -bfc004c0: 00002021 move a0,zero -bfc004c4: 1280001e beqz s4,bfc00540 -bfc004c8: 00000000 nop -bfc004cc: 90a30000 lbu v1,0(a1) -bfc004d0: 00000000 nop -bfc004d4: 2462ffe0 addiu v0,v1,-32 -bfc004d8: 304200ff andi v0,v0,0xff -bfc004dc: 2c420060 sltiu v0,v0,96 -bfc004e0: 14400003 bnez v0,bfc004f0 -bfc004e4: 00031e00 sll v1,v1,0x18 -bfc004e8: 2403002e li v1,46 -bfc004ec: 00031e00 sll v1,v1,0x18 -bfc004f0: 00031e03 sra v1,v1,0x18 -bfc004f4: 2402000a li v0,10 -bfc004f8: 14620007 bne v1,v0,bfc00518 -bfc004fc: 00000000 nop -bfc00500: 8fc20000 lw v0,0(s8) -bfc00504: 00000000 nop -bfc00508: 30420002 andi v0,v0,0x2 -bfc0050c: 1440fffc bnez v0,bfc00500 -bfc00510: 2402000d li v0,13 -bfc00514: aee20000 sw v0,0(s7) -bfc00518: 8fc20000 lw v0,0(s8) -bfc0051c: 00000000 nop -bfc00520: 30420002 andi v0,v0,0x2 -bfc00524: 1440fffc bnez v0,bfc00518 -bfc00528: 00000000 nop -bfc0052c: aee30000 sw v1,0(s7) -bfc00530: 2694ffff addiu s4,s4,-1 -bfc00534: 24840001 addiu a0,a0,1 -bfc00538: 0bf00155 j bfc00554 -bfc0053c: 24a50001 addiu a1,a1,1 -bfc00540: 3c04bfc0 lui a0,0xbfc0 -bfc00544: 0ff000b0 jal bfc002c0 -bfc00548: 24841774 addiu a0,a0,6004 -bfc0054c: 0bf00159 j bfc00564 -bfc00550: 3c04bfc0 lui a0,0xbfc0 -bfc00554: 0096102a slt v0,a0,s6 -bfc00558: 1440ffda bnez v0,bfc004c4 -bfc0055c: 00000000 nop -bfc00560: 3c04bfc0 lui a0,0xbfc0 -bfc00564: 0ff000b0 jal bfc002c0 -bfc00568: 248416c8 addiu a0,a0,5832 -bfc0056c: 02b6a821 addu s5,s5,s6 -bfc00570: 1640ffb4 bnez s2,bfc00444 -bfc00574: 02769821 addu s3,s3,s6 -bfc00578: 8fbf0034 lw ra,52(sp) -bfc0057c: 8fbe0030 lw s8,48(sp) -bfc00580: 8fb7002c lw s7,44(sp) -bfc00584: 8fb60028 lw s6,40(sp) -bfc00588: 8fb50024 lw s5,36(sp) -bfc0058c: 8fb40020 lw s4,32(sp) -bfc00590: 8fb3001c lw s3,28(sp) -bfc00594: 8fb20018 lw s2,24(sp) -bfc00598: 8fb10014 lw s1,20(sp) -bfc0059c: 8fb00010 lw s0,16(sp) -bfc005a0: 03e00008 jr ra -bfc005a4: 27bd0038 addiu sp,sp,56 - -bfc005a8 : -bfc005a8: 00c03821 move a3,a2 -bfc005ac: 00a03021 move a2,a1 -bfc005b0: 0bf000fb j bfc003ec -bfc005b4: 24050001 li a1,1 - -bfc005b8 : -bfc005b8: 8c840000 lw a0,0(a0) -bfc005bc: 3c020070 lui v0,0x70 -bfc005c0: 34420070 ori v0,v0,0x70 -bfc005c4: 3c0300ff lui v1,0xff -bfc005c8: ac820000 sw v0,0(a0) -bfc005cc: 346300ff ori v1,v1,0xff -bfc005d0: 8c820000 lw v0,0(a0) -bfc005d4: ac830000 sw v1,0(a0) -bfc005d8: 03e00008 jr ra -bfc005dc: 00000000 nop - -bfc005e0 : -bfc005e0: 27bdfff8 addiu sp,sp,-8 -bfc005e4: ac850000 sw a1,0(a0) -bfc005e8: 24820008 addiu v0,a0,8 -bfc005ec: 0bf0017f j bfc005fc -bfc005f0: 24830020 addiu v1,a0,32 -bfc005f4: a0400000 sb zero,0(v0) -bfc005f8: 24420001 addiu v0,v0,1 -bfc005fc: 1443fffd bne v0,v1,bfc005f4 -bfc00600: 00000000 nop -bfc00604: 24020001 li v0,1 -bfc00608: ac820004 sw v0,4(a0) -bfc0060c: 03e00008 jr ra -bfc00610: 27bd0008 addiu sp,sp,8 - -bfc00614 : -bfc00614: 8c870000 lw a3,0(a0) -bfc00618: 3c020098 lui v0,0x98 -bfc0061c: 34420098 ori v0,v0,0x98 -bfc00620: ace20000 sw v0,0(a3) -bfc00624: 3c0200ff lui v0,0xff -bfc00628: 344200ff ori v0,v0,0xff -bfc0062c: ace20000 sw v0,0(a3) -bfc00630: 3c020090 lui v0,0x90 -bfc00634: 34420090 ori v0,v0,0x90 -bfc00638: ace20000 sw v0,0(a3) -bfc0063c: 00804021 move t0,a0 -bfc00640: 94e4009c lhu a0,156(a3) -bfc00644: 24030002 li v1,2 -bfc00648: 24020020 li v0,32 -bfc0064c: ad030008 sw v1,8(t0) -bfc00650: ad03001c sw v1,28(t0) -bfc00654: ad020018 sw v0,24(t0) -bfc00658: 3084ffff andi a0,a0,0xffff -bfc0065c: 0bf0019d j bfc00674 -bfc00660: 00001821 move v1,zero -bfc00664: 8d020008 lw v0,8(t0) -bfc00668: 00000000 nop -bfc0066c: 00021040 sll v0,v0,0x1 -bfc00670: ad020008 sw v0,8(t0) -bfc00674: 0064102b sltu v0,v1,a0 -bfc00678: 1440fffa bnez v0,bfc00664 -bfc0067c: 24630001 addiu v1,v1,1 -bfc00680: 94e200ac lhu v0,172(a3) -bfc00684: 94e300a8 lhu v1,168(a3) -bfc00688: 3042ffff andi v0,v0,0xffff -bfc0068c: 8d04001c lw a0,28(t0) -bfc00690: 3063ffff andi v1,v1,0xffff -bfc00694: 00021200 sll v0,v0,0x8 -bfc00698: 00432825 or a1,v0,v1 -bfc0069c: ad040014 sw a0,20(t0) -bfc006a0: 0bf001ae j bfc006b8 -bfc006a4: 00001821 move v1,zero -bfc006a8: 8d020014 lw v0,20(t0) -bfc006ac: 00000000 nop -bfc006b0: 00021040 sll v0,v0,0x1 -bfc006b4: ad020014 sw v0,20(t0) -bfc006b8: 0065102b sltu v0,v1,a1 -bfc006bc: 1440fffa bnez v0,bfc006a8 -bfc006c0: 24630001 addiu v1,v1,1 -bfc006c4: 94e300b8 lhu v1,184(a3) -bfc006c8: 94e600b4 lhu a2,180(a3) -bfc006cc: 94e200c0 lhu v0,192(a3) -bfc006d0: 94e400bc lhu a0,188(a3) -bfc006d4: 8d05001c lw a1,28(t0) -bfc006d8: 3042ffff andi v0,v0,0xffff -bfc006dc: 3084ffff andi a0,a0,0xffff -bfc006e0: 00021200 sll v0,v0,0x8 -bfc006e4: 00441025 or v0,v0,a0 -bfc006e8: 00052a00 sll a1,a1,0x8 -bfc006ec: 00a20018 mult a1,v0 -bfc006f0: 3063ffff andi v1,v1,0xffff -bfc006f4: 30c6ffff andi a2,a2,0xffff -bfc006f8: 00031a00 sll v1,v1,0x8 -bfc006fc: 00661825 or v1,v1,a2 -bfc00700: 24630001 addiu v1,v1,1 -bfc00704: ad030010 sw v1,16(t0) -bfc00708: 3c0300ff lui v1,0xff -bfc0070c: 346300ff ori v1,v1,0xff -bfc00710: 00001021 move v0,zero -bfc00714: 00002812 mflo a1 -bfc00718: ad05000c sw a1,12(t0) -bfc0071c: ace30000 sw v1,0(a3) -bfc00720: 03e00008 jr ra -bfc00724: 00000000 nop - -bfc00728 : -bfc00728: 8c820008 lw v0,8(a0) -bfc0072c: 8c860000 lw a2,0(a0) -bfc00730: 00021082 srl v0,v0,0x2 -bfc00734: 00a2102b sltu v0,a1,v0 -bfc00738: 14400004 bnez v0,bfc0074c -bfc0073c: 3c030090 lui v1,0x90 -bfc00740: 3c028010 lui v0,0x8010 -bfc00744: 03e00008 jr ra -bfc00748: 34420002 ori v0,v0,0x2 -bfc0074c: 8c820010 lw v0,16(a0) -bfc00750: 00000000 nop -bfc00754: 2442ffff addiu v0,v0,-1 -bfc00758: 00021400 sll v0,v0,0x10 -bfc0075c: 00a21024 and v0,a1,v0 -bfc00760: 24420002 addiu v0,v0,2 -bfc00764: 34630090 ori v1,v1,0x90 -bfc00768: 00021080 sll v0,v0,0x2 -bfc0076c: acc30000 sw v1,0(a2) -bfc00770: 00c21021 addu v0,a2,v0 -bfc00774: 8c430000 lw v1,0(v0) -bfc00778: 3c020001 lui v0,0x1 -bfc0077c: 34420001 ori v0,v0,0x1 -bfc00780: 00621824 and v1,v1,v0 -bfc00784: 3c0200ff lui v0,0xff -bfc00788: 344200ff ori v0,v0,0xff -bfc0078c: acc20000 sw v0,0(a2) -bfc00790: 03e00008 jr ra -bfc00794: 0003102b sltu v0,zero,v1 - -bfc00798 : -bfc00798: 8c820008 lw v0,8(a0) -bfc0079c: 00a01821 move v1,a1 -bfc007a0: 00021082 srl v0,v0,0x2 -bfc007a4: 00a2102b sltu v0,a1,v0 -bfc007a8: 8c850000 lw a1,0(a0) -bfc007ac: 14400003 bnez v0,bfc007bc -bfc007b0: 3c028010 lui v0,0x8010 -bfc007b4: 0bf0020c j bfc00830 -bfc007b8: 34430002 ori v1,v0,0x2 -bfc007bc: 8c820010 lw v0,16(a0) -bfc007c0: 00000000 nop -bfc007c4: 2442ffff addiu v0,v0,-1 -bfc007c8: 00021400 sll v0,v0,0x10 -bfc007cc: 00621024 and v0,v1,v0 -bfc007d0: 00021080 sll v0,v0,0x2 -bfc007d4: 00a22021 addu a0,a1,v0 -bfc007d8: 3c020020 lui v0,0x20 -bfc007dc: 34420020 ori v0,v0,0x20 -bfc007e0: ac820000 sw v0,0(a0) -bfc007e4: 3c0200d0 lui v0,0xd0 -bfc007e8: 344200d0 ori v0,v0,0xd0 -bfc007ec: ac820000 sw v0,0(a0) -bfc007f0: 3c020080 lui v0,0x80 -bfc007f4: 34430080 ori v1,v0,0x80 -bfc007f8: 8c860000 lw a2,0(a0) -bfc007fc: 00000000 nop -bfc00800: 00c31024 and v0,a2,v1 -bfc00804: 1443fffc bne v0,v1,bfc007f8 -bfc00808: 3c02002a lui v0,0x2a -bfc0080c: 3442002a ori v0,v0,0x2a -bfc00810: 00c21024 and v0,a2,v0 -bfc00814: 10400003 beqz v0,bfc00824 -bfc00818: 00001821 move v1,zero -bfc0081c: 3c029010 lui v0,0x9010 -bfc00820: 00c21825 or v1,a2,v0 -bfc00824: 3c0200ff lui v0,0xff -bfc00828: 344200ff ori v0,v0,0xff -bfc0082c: ac820000 sw v0,0(a0) -bfc00830: 03e00008 jr ra -bfc00834: 00601021 move v0,v1 - -bfc00838 : -bfc00838: 8c820008 lw v0,8(a0) -bfc0083c: 00a01821 move v1,a1 -bfc00840: 00021082 srl v0,v0,0x2 -bfc00844: 00a2102b sltu v0,a1,v0 -bfc00848: 8c850000 lw a1,0(a0) -bfc0084c: 14400003 bnez v0,bfc0085c -bfc00850: 3c028010 lui v0,0x8010 -bfc00854: 0bf00234 j bfc008d0 -bfc00858: 34430002 ori v1,v0,0x2 -bfc0085c: 8c820010 lw v0,16(a0) -bfc00860: 00000000 nop -bfc00864: 2442ffff addiu v0,v0,-1 -bfc00868: 00021400 sll v0,v0,0x10 -bfc0086c: 00621024 and v0,v1,v0 -bfc00870: 00021080 sll v0,v0,0x2 -bfc00874: 00a22021 addu a0,a1,v0 -bfc00878: 3c020060 lui v0,0x60 -bfc0087c: 34420060 ori v0,v0,0x60 -bfc00880: ac820000 sw v0,0(a0) -bfc00884: 3c020001 lui v0,0x1 -bfc00888: 34420001 ori v0,v0,0x1 -bfc0088c: ac820000 sw v0,0(a0) -bfc00890: 3c020080 lui v0,0x80 -bfc00894: 34430080 ori v1,v0,0x80 -bfc00898: 8c860000 lw a2,0(a0) -bfc0089c: 00000000 nop -bfc008a0: 00c31024 and v0,a2,v1 -bfc008a4: 1443fffc bne v0,v1,bfc00898 -bfc008a8: 3c020038 lui v0,0x38 -bfc008ac: 34420038 ori v0,v0,0x38 -bfc008b0: 00c21024 and v0,a2,v0 -bfc008b4: 10400003 beqz v0,bfc008c4 -bfc008b8: 00001821 move v1,zero -bfc008bc: 3c029010 lui v0,0x9010 -bfc008c0: 00c21825 or v1,a2,v0 -bfc008c4: 3c0200ff lui v0,0xff -bfc008c8: 344200ff ori v0,v0,0xff -bfc008cc: ac820000 sw v0,0(a0) -bfc008d0: 03e00008 jr ra -bfc008d4: 00601021 move v0,v1 - -bfc008d8 : -bfc008d8: 8c820008 lw v0,8(a0) -bfc008dc: 00a01821 move v1,a1 -bfc008e0: 00021082 srl v0,v0,0x2 -bfc008e4: 00a2102b sltu v0,a1,v0 -bfc008e8: 8c850000 lw a1,0(a0) -bfc008ec: 14400003 bnez v0,bfc008fc -bfc008f0: 3c028010 lui v0,0x8010 -bfc008f4: 0bf0025c j bfc00970 -bfc008f8: 34430002 ori v1,v0,0x2 -bfc008fc: 8c820010 lw v0,16(a0) -bfc00900: 00000000 nop -bfc00904: 2442ffff addiu v0,v0,-1 -bfc00908: 00021400 sll v0,v0,0x10 -bfc0090c: 00621024 and v0,v1,v0 -bfc00910: 00021080 sll v0,v0,0x2 -bfc00914: 00a22021 addu a0,a1,v0 -bfc00918: 3c020060 lui v0,0x60 -bfc0091c: 34420060 ori v0,v0,0x60 -bfc00920: ac820000 sw v0,0(a0) -bfc00924: 3c0200d0 lui v0,0xd0 -bfc00928: 344200d0 ori v0,v0,0xd0 -bfc0092c: ac820000 sw v0,0(a0) -bfc00930: 3c020080 lui v0,0x80 -bfc00934: 34430080 ori v1,v0,0x80 -bfc00938: 8c860000 lw a2,0(a0) -bfc0093c: 00000000 nop -bfc00940: 00c31024 and v0,a2,v1 -bfc00944: 1443fffc bne v0,v1,bfc00938 -bfc00948: 3c020038 lui v0,0x38 -bfc0094c: 34420038 ori v0,v0,0x38 -bfc00950: 00c21024 and v0,a2,v0 -bfc00954: 10400003 beqz v0,bfc00964 -bfc00958: 00001821 move v1,zero -bfc0095c: 3c029010 lui v0,0x9010 -bfc00960: 00c21825 or v1,a2,v0 -bfc00964: 3c0200ff lui v0,0xff -bfc00968: 344200ff ori v0,v0,0xff -bfc0096c: ac820000 sw v0,0(a0) -bfc00970: 03e00008 jr ra -bfc00974: 00601021 move v0,v1 - -bfc00978 : -bfc00978: 8c820008 lw v0,8(a0) -bfc0097c: 8c840000 lw a0,0(a0) -bfc00980: 00021082 srl v0,v0,0x2 -bfc00984: 00a2102b sltu v0,a1,v0 -bfc00988: 14400003 bnez v0,bfc00998 -bfc0098c: 3c028010 lui v0,0x8010 -bfc00990: 0bf0027c j bfc009f0 -bfc00994: 34430002 ori v1,v0,0x2 -bfc00998: 00051080 sll v0,a1,0x2 -bfc0099c: 00822021 addu a0,a0,v0 -bfc009a0: 3c020040 lui v0,0x40 -bfc009a4: 34420040 ori v0,v0,0x40 -bfc009a8: ac820000 sw v0,0(a0) -bfc009ac: 3c020080 lui v0,0x80 -bfc009b0: ac860000 sw a2,0(a0) -bfc009b4: 34430080 ori v1,v0,0x80 -bfc009b8: 8c860000 lw a2,0(a0) -bfc009bc: 00000000 nop -bfc009c0: 00c31024 and v0,a2,v1 -bfc009c4: 1443fffc bne v0,v1,bfc009b8 -bfc009c8: 3c02001a lui v0,0x1a -bfc009cc: 3442001a ori v0,v0,0x1a -bfc009d0: 00c21024 and v0,a2,v0 -bfc009d4: 10400003 beqz v0,bfc009e4 -bfc009d8: 00001821 move v1,zero -bfc009dc: 3c029010 lui v0,0x9010 -bfc009e0: 00c21825 or v1,a2,v0 -bfc009e4: 3c0200ff lui v0,0xff -bfc009e8: 344200ff ori v0,v0,0xff -bfc009ec: ac820000 sw v0,0(a0) -bfc009f0: 03e00008 jr ra -bfc009f4: 00601021 move v0,v1 - -bfc009f8 : -bfc009f8: 8c820008 lw v0,8(a0) -bfc009fc: 27bdffe8 addiu sp,sp,-24 -bfc00a00: 00021082 srl v0,v0,0x2 -bfc00a04: 00a2102b sltu v0,a1,v0 -bfc00a08: afb40014 sw s4,20(sp) -bfc00a0c: afb30010 sw s3,16(sp) -bfc00a10: afb2000c sw s2,12(sp) -bfc00a14: afb10008 sw s1,8(sp) -bfc00a18: afb00004 sw s0,4(sp) -bfc00a1c: 0080c021 move t8,a0 -bfc00a20: 8c8e0000 lw t6,0(a0) -bfc00a24: 14400004 bnez v0,bfc00a38 -bfc00a28: 00c0a021 move s4,a2 -bfc00a2c: 3c028010 lui v0,0x8010 -bfc00a30: 0bf002e3 j bfc00b8c -bfc00a34: 34440002 ori a0,v0,0x2 -bfc00a38: 8c820010 lw v0,16(a0) -bfc00a3c: 00006821 move t5,zero -bfc00a40: 2442ffff addiu v0,v0,-1 -bfc00a44: 0002cc00 sll t9,v0,0x10 -bfc00a48: 3c0200e8 lui v0,0xe8 -bfc00a4c: 345300e8 ori s3,v0,0xe8 -bfc00a50: 3c020080 lui v0,0x80 -bfc00a54: 344f0080 ori t7,v0,0x80 -bfc00a58: 3c02001a lui v0,0x1a -bfc00a5c: 3446001a ori a2,v0,0x1a -bfc00a60: 3c0200d0 lui v0,0xd0 -bfc00a64: 345200d0 ori s2,v0,0xd0 -bfc00a68: 3c0200ff lui v0,0xff -bfc00a6c: 345100ff ori s1,v0,0xff -bfc00a70: 0bf002e1 j bfc00b84 -bfc00a74: 3c100001 lui s0,0x1 -bfc00a78: 01851023 subu v0,t4,a1 -bfc00a7c: 00505021 addu t2,v0,s0 -bfc00a80: 00ea102b sltu v0,a3,t2 -bfc00a84: 10400002 beqz v0,bfc00a90 -bfc00a88: 000c1080 sll v0,t4,0x2 -bfc00a8c: 00e05021 move t2,a3 -bfc00a90: 0bf002d7 j bfc00b5c -bfc00a94: 01c25821 addu t3,t6,v0 -bfc00a98: ad730000 sw s3,0(t3) -bfc00a9c: 8d630000 lw v1,0(t3) -bfc00aa0: 00000000 nop -bfc00aa4: 006f1024 and v0,v1,t7 -bfc00aa8: 144ffffc bne v0,t7,bfc00a9c -bfc00aac: 00661024 and v0,v1,a2 -bfc00ab0: 14400026 bnez v0,bfc00b4c -bfc00ab4: 3c029010 lui v0,0x9010 -bfc00ab8: 8f020014 lw v0,20(t8) -bfc00abc: 00000000 nop -bfc00ac0: 00021882 srl v1,v0,0x2 -bfc00ac4: 006a102b sltu v0,v1,t2 -bfc00ac8: 10400002 beqz v0,bfc00ad4 -bfc00acc: 01404021 move t0,t2 -bfc00ad0: 00604021 move t0,v1 -bfc00ad4: 2503ffff addiu v1,t0,-1 -bfc00ad8: 00031400 sll v0,v1,0x10 -bfc00adc: 00431025 or v0,v0,v1 -bfc00ae0: 00052080 sll a0,a1,0x2 -bfc00ae4: 000d1880 sll v1,t5,0x2 -bfc00ae8: 02834821 addu t1,s4,v1 -bfc00aec: ad620000 sw v0,0(t3) -bfc00af0: 01c42021 addu a0,t6,a0 -bfc00af4: 0bf002c3 j bfc00b0c -bfc00af8: 00001821 move v1,zero -bfc00afc: 8d220000 lw v0,0(t1) -bfc00b00: 25290004 addiu t1,t1,4 -bfc00b04: ac820000 sw v0,0(a0) -bfc00b08: 24840004 addiu a0,a0,4 -bfc00b0c: 0068102b sltu v0,v1,t0 -bfc00b10: 1440fffa bnez v0,bfc00afc -bfc00b14: 24630001 addiu v1,v1,1 -bfc00b18: 01a86821 addu t5,t5,t0 -bfc00b1c: 00a82821 addu a1,a1,t0 -bfc00b20: 00e83823 subu a3,a3,t0 -bfc00b24: ad720000 sw s2,0(t3) -bfc00b28: 8d630000 lw v1,0(t3) -bfc00b2c: 00000000 nop -bfc00b30: 006f1024 and v0,v1,t7 -bfc00b34: 144ffffc bne v0,t7,bfc00b28 -bfc00b38: 00661024 and v0,v1,a2 -bfc00b3c: 10400005 beqz v0,bfc00b54 -bfc00b40: 01485023 subu t2,t2,t0 -bfc00b44: 01485021 addu t2,t2,t0 -bfc00b48: 3c029010 lui v0,0x9010 -bfc00b4c: 0bf002d9 j bfc00b64 -bfc00b50: 00622025 or a0,v1,v0 -bfc00b54: ad710000 sw s1,0(t3) -bfc00b58: 00002021 move a0,zero -bfc00b5c: 1540ffce bnez t2,bfc00a98 -bfc00b60: 00000000 nop -bfc00b64: 04810007 bgez a0,bfc00b84 -bfc00b68: 000c1880 sll v1,t4,0x2 -bfc00b6c: 3c0200ff lui v0,0xff -bfc00b70: 01c31821 addu v1,t6,v1 -bfc00b74: 344200ff ori v0,v0,0xff -bfc00b78: ac620000 sw v0,0(v1) -bfc00b7c: 0bf002e4 j bfc00b90 -bfc00b80: 00801021 move v0,a0 -bfc00b84: 14e0ffbc bnez a3,bfc00a78 -bfc00b88: 00b96024 and t4,a1,t9 -bfc00b8c: 00801021 move v0,a0 -bfc00b90: 8fb40014 lw s4,20(sp) -bfc00b94: 8fb30010 lw s3,16(sp) -bfc00b98: 8fb2000c lw s2,12(sp) -bfc00b9c: 8fb10008 lw s1,8(sp) -bfc00ba0: 8fb00004 lw s0,4(sp) -bfc00ba4: 03e00008 jr ra -bfc00ba8: 27bd0018 addiu sp,sp,24 - -bfc00bac : -bfc00bac: 27bdffe0 addiu sp,sp,-32 -bfc00bb0: afbf001c sw ra,28(sp) -bfc00bb4: ac850000 sw a1,0(a0) -bfc00bb8: 24820008 addiu v0,a0,8 -bfc00bbc: 0bf002f3 j bfc00bcc -bfc00bc0: 24830020 addiu v1,a0,32 -bfc00bc4: a0400000 sb zero,0(v0) -bfc00bc8: 24420001 addiu v0,v0,1 -bfc00bcc: 1443fffd bne v0,v1,bfc00bc4 -bfc00bd0: 00000000 nop -bfc00bd4: 3c021234 lui v0,0x1234 -bfc00bd8: 34425678 ori v0,v0,0x5678 -bfc00bdc: 00021e02 srl v1,v0,0x18 -bfc00be0: afa20010 sw v0,16(sp) -bfc00be4: 24020012 li v0,18 -bfc00be8: 14620003 bne v1,v0,bfc00bf8 -bfc00bec: ac800004 sw zero,4(a0) -bfc00bf0: 24020001 li v0,1 -bfc00bf4: ac820004 sw v0,4(a0) -bfc00bf8: 0ff00185 jal bfc00614 -bfc00bfc: 00000000 nop -bfc00c00: 8fbf001c lw ra,28(sp) -bfc00c04: 00000000 nop -bfc00c08: 03e00008 jr ra -bfc00c0c: 27bd0020 addiu sp,sp,32 - -bfc00c10 : -bfc00c10: 27bdffd8 addiu sp,sp,-40 -bfc00c14: 30c20003 andi v0,a2,0x3 -bfc00c18: afb2001c sw s2,28(sp) -bfc00c1c: afbf0024 sw ra,36(sp) -bfc00c20: afb30020 sw s3,32(sp) -bfc00c24: afb10018 sw s1,24(sp) -bfc00c28: afb00014 sw s0,20(sp) -bfc00c2c: 10400004 beqz v0,bfc00c40 -bfc00c30: 00809021 move s2,a0 -bfc00c34: 00061082 srl v0,a2,0x2 -bfc00c38: 24420001 addiu v0,v0,1 -bfc00c3c: 00023080 sll a2,v0,0x2 -bfc00c40: 00c59821 addu s3,a2,a1 -bfc00c44: 0bf00324 j bfc00c90 -bfc00c48: 00a08821 move s1,a1 -bfc00c4c: 0ff001ca jal bfc00728 -bfc00c50: 00000000 nop -bfc00c54: 02402021 move a0,s2 -bfc00c58: 10400005 beqz v0,bfc00c70 -bfc00c5c: 02002821 move a1,s0 -bfc00c60: 0ff00236 jal bfc008d8 -bfc00c64: 00000000 nop -bfc00c68: 04400011 bltz v0,bfc00cb0 -bfc00c6c: 00401821 move v1,v0 -bfc00c70: 02002821 move a1,s0 -bfc00c74: 0ff001e6 jal bfc00798 -bfc00c78: 02402021 move a0,s2 -bfc00c7c: 0440000c bltz v0,bfc00cb0 -bfc00c80: 00401821 move v1,v0 -bfc00c84: 8e42000c lw v0,12(s2) -bfc00c88: 00000000 nop -bfc00c8c: 02228821 addu s1,s1,v0 -bfc00c90: 001117c3 sra v0,s1,0x1f -bfc00c94: 00021782 srl v0,v0,0x1e -bfc00c98: 00511021 addu v0,v0,s1 -bfc00c9c: 00028083 sra s0,v0,0x2 -bfc00ca0: 0233102b sltu v0,s1,s3 -bfc00ca4: 02402021 move a0,s2 -bfc00ca8: 1440ffe8 bnez v0,bfc00c4c -bfc00cac: 02002821 move a1,s0 -bfc00cb0: 8fbf0024 lw ra,36(sp) -bfc00cb4: 00601021 move v0,v1 -bfc00cb8: 8fb30020 lw s3,32(sp) -bfc00cbc: 8fb2001c lw s2,28(sp) -bfc00cc0: 8fb10018 lw s1,24(sp) -bfc00cc4: 8fb00014 lw s0,20(sp) -bfc00cc8: 03e00008 jr ra -bfc00ccc: 27bd0028 addiu sp,sp,40 - -bfc00cd0 : -bfc00cd0: 30e20003 andi v0,a3,0x3 -bfc00cd4: 10400003 beqz v0,bfc00ce4 -bfc00cd8: 00071082 srl v0,a3,0x2 -bfc00cdc: 24420001 addiu v0,v0,1 -bfc00ce0: 00023880 sll a3,v0,0x2 -bfc00ce4: 00052882 srl a1,a1,0x2 -bfc00ce8: 0bf0027e j bfc009f8 -bfc00cec: 00073882 srl a3,a3,0x2 - -bfc00cf0 : -bfc00cf0: 8c820000 lw v0,0(a0) -bfc00cf4: 00002021 move a0,zero -bfc00cf8: 0bf00347 j bfc00d1c -bfc00cfc: 00454021 addu t0,v0,a1 -bfc00d00: 90630000 lbu v1,0(v1) -bfc00d04: 90a20000 lbu v0,0(a1) -bfc00d08: 00000000 nop -bfc00d0c: 10620003 beq v1,v0,bfc00d1c -bfc00d10: 3c028010 lui v0,0x8010 -bfc00d14: 03e00008 jr ra -bfc00d18: 34420003 ori v0,v0,0x3 -bfc00d1c: 0087102b sltu v0,a0,a3 -bfc00d20: 01041821 addu v1,t0,a0 -bfc00d24: 00c42821 addu a1,a2,a0 -bfc00d28: 1440fff5 bnez v0,bfc00d00 -bfc00d2c: 24840001 addiu a0,a0,1 -bfc00d30: 03e00008 jr ra -bfc00d34: 00000000 nop - -bfc00d38 : -bfc00d38: 8c82000c lw v0,12(a0) -bfc00d3c: 00000000 nop -bfc00d40: 14400002 bnez v0,bfc00d4c -bfc00d44: 00a2001b divu zero,a1,v0 -bfc00d48: 0007000d break 0x7 -bfc00d4c: 00001010 mfhi v0 -bfc00d50: 0002102b sltu v0,zero,v0 -bfc00d54: 00002812 mflo a1 -bfc00d58: 03e00008 jr ra -bfc00d5c: 00a21021 addu v0,a1,v0 - -bfc00d60 : -bfc00d60: 8c830010 lw v1,16(a0) -bfc00d64: 00000000 nop -bfc00d68: 00a3102b sltu v0,a1,v1 -bfc00d6c: 14400002 bnez v0,bfc00d78 -bfc00d70: 00000000 nop -bfc00d74: 2465ffff addiu a1,v1,-1 -bfc00d78: 8c82000c lw v0,12(a0) -bfc00d7c: 00000000 nop -bfc00d80: 00a20018 mult a1,v0 -bfc00d84: 00001012 mflo v0 -bfc00d88: 03e00008 jr ra -bfc00d8c: 00000000 nop - -bfc00d90 : -bfc00d90: 27bdffe8 addiu sp,sp,-24 -bfc00d94: afbf0014 sw ra,20(sp) -bfc00d98: afb00010 sw s0,16(sp) -bfc00d9c: 0ff0034e jal bfc00d38 -bfc00da0: 00808021 move s0,a0 -bfc00da4: 8e03000c lw v1,12(s0) -bfc00da8: 8fbf0014 lw ra,20(sp) -bfc00dac: 00430018 mult v0,v1 -bfc00db0: 8fb00010 lw s0,16(sp) -bfc00db4: 00001012 mflo v0 -bfc00db8: 03e00008 jr ra -bfc00dbc: 27bd0018 addiu sp,sp,24 - -bfc00dc0 : -bfc00dc0: 90830000 lbu v1,0(a0) -bfc00dc4: 00000000 nop -bfc00dc8: 2c620041 sltiu v0,v1,65 -bfc00dcc: 14400002 bnez v0,bfc00dd8 -bfc00dd0: 2462ffd0 addiu v0,v1,-48 -bfc00dd4: 2462ffc9 addiu v0,v1,-55 -bfc00dd8: 90840001 lbu a0,1(a0) -bfc00ddc: 304200ff andi v0,v0,0xff -bfc00de0: 304300ff andi v1,v0,0xff -bfc00de4: 2c820041 sltiu v0,a0,65 -bfc00de8: 14400003 bnez v0,bfc00df8 -bfc00dec: 00000000 nop -bfc00df0: 0bf0037f j bfc00dfc -bfc00df4: 2482ffc9 addiu v0,a0,-55 -bfc00df8: 2482ffd0 addiu v0,a0,-48 -bfc00dfc: 304400ff andi a0,v0,0xff -bfc00e00: 00031100 sll v0,v1,0x4 -bfc00e04: 00821025 or v0,a0,v0 -bfc00e08: 03e00008 jr ra -bfc00e0c: 304200ff andi v0,v0,0xff - -bfc00e10 : -bfc00e10: 10c00094 beqz a2,bfc01064 -bfc00e14: 00805021 move t2,a0 -bfc00e18: 24020003 li v0,3 -bfc00e1c: ac820008 sw v0,8(a0) -bfc00e20: 90a40001 lbu a0,1(a1) -bfc00e24: 00000000 nop -bfc00e28: 2482ffcf addiu v0,a0,-49 -bfc00e2c: 304200ff andi v0,v0,0xff -bfc00e30: 2c420003 sltiu v0,v0,3 -bfc00e34: 10400005 beqz v0,bfc00e4c -bfc00e38: 2482ffc9 addiu v0,a0,-55 -bfc00e3c: 24020002 li v0,2 -bfc00e40: ad420008 sw v0,8(t2) -bfc00e44: 0bf003a1 j bfc00e84 -bfc00e48: 2489ffd1 addiu t1,a0,-47 -bfc00e4c: 304200ff andi v0,v0,0xff -bfc00e50: 2c420003 sltiu v0,v0,3 -bfc00e54: 10400006 beqz v0,bfc00e70 -bfc00e58: 24020030 li v0,48 -bfc00e5c: 2402003b li v0,59 -bfc00e60: 00444823 subu t1,v0,a0 -bfc00e64: 24020004 li v0,4 -bfc00e68: 0bf003a1 j bfc00e84 -bfc00e6c: ad420008 sw v0,8(t2) -bfc00e70: 14820004 bne a0,v0,bfc00e84 -bfc00e74: 00004821 move t1,zero -bfc00e78: 24020001 li v0,1 -bfc00e7c: ad420008 sw v0,8(t2) -bfc00e80: 24090002 li t1,2 -bfc00e84: 90a30002 lbu v1,2(a1) -bfc00e88: 00000000 nop -bfc00e8c: 2c620041 sltiu v0,v1,65 -bfc00e90: 10400003 beqz v0,bfc00ea0 -bfc00e94: 24a40002 addiu a0,a1,2 -bfc00e98: 0bf003a9 j bfc00ea4 -bfc00e9c: 2462ffd0 addiu v0,v1,-48 -bfc00ea0: 2462ffc9 addiu v0,v1,-55 -bfc00ea4: 90830001 lbu v1,1(a0) -bfc00ea8: 304200ff andi v0,v0,0xff -bfc00eac: 304400ff andi a0,v0,0xff -bfc00eb0: 2c620041 sltiu v0,v1,65 -bfc00eb4: 10400002 beqz v0,bfc00ec0 -bfc00eb8: 2462ffc9 addiu v0,v1,-55 -bfc00ebc: 2462ffd0 addiu v0,v1,-48 -bfc00ec0: 304300ff andi v1,v0,0xff -bfc00ec4: 00041100 sll v0,a0,0x4 -bfc00ec8: 00621025 or v0,v1,v0 -bfc00ecc: 304200ff andi v0,v0,0xff -bfc00ed0: ad420004 sw v0,4(t2) -bfc00ed4: ad400000 sw zero,0(t2) -bfc00ed8: 00405821 move t3,v0 -bfc00edc: 00a03021 move a2,a1 -bfc00ee0: 0bf003d5 j bfc00f54 -bfc00ee4: 00003821 move a3,zero -bfc00ee8: 90c20004 lbu v0,4(a2) -bfc00eec: 00000000 nop -bfc00ef0: 2443ffc9 addiu v1,v0,-55 -bfc00ef4: 2444ffd0 addiu a0,v0,-48 -bfc00ef8: 2c420041 sltiu v0,v0,65 -bfc00efc: 10400002 beqz v0,bfc00f08 -bfc00f00: 306300ff andi v1,v1,0xff -bfc00f04: 308300ff andi v1,a0,0xff -bfc00f08: 90c20005 lbu v0,5(a2) -bfc00f0c: 306800ff andi t0,v1,0xff -bfc00f10: 2444ffc9 addiu a0,v0,-55 -bfc00f14: 2443ffd0 addiu v1,v0,-48 -bfc00f18: 2c420041 sltiu v0,v0,65 -bfc00f1c: 10400002 beqz v0,bfc00f28 -bfc00f20: 308400ff andi a0,a0,0xff -bfc00f24: 306400ff andi a0,v1,0xff -bfc00f28: 8d430000 lw v1,0(t2) -bfc00f2c: 00081100 sll v0,t0,0x4 -bfc00f30: 00821025 or v0,a0,v0 -bfc00f34: 304200ff andi v0,v0,0xff -bfc00f38: 00031a00 sll v1,v1,0x8 -bfc00f3c: 004b2021 addu a0,v0,t3 -bfc00f40: 00431025 or v0,v0,v1 -bfc00f44: ad420000 sw v0,0(t2) -bfc00f48: 308b00ff andi t3,a0,0xff -bfc00f4c: 24e70001 addiu a3,a3,1 -bfc00f50: 24c60002 addiu a2,a2,2 -bfc00f54: 00e9102a slt v0,a3,t1 -bfc00f58: 1440ffe3 bnez v0,bfc00ee8 -bfc00f5c: 25220002 addiu v0,t1,2 -bfc00f60: 8d440004 lw a0,4(t2) -bfc00f64: 00021040 sll v0,v0,0x1 -bfc00f68: 00091827 nor v1,zero,t1 -bfc00f6c: 00832021 addu a0,a0,v1 -bfc00f70: 00a21021 addu v0,a1,v0 -bfc00f74: ad440004 sw a0,4(t2) -bfc00f78: ad42000c sw v0,12(t2) -bfc00f7c: 0bf003f9 j bfc00fe4 -bfc00f80: 00003021 move a2,zero -bfc00f84: 90e20000 lbu v0,0(a3) -bfc00f88: 00000000 nop -bfc00f8c: 2444ffc9 addiu a0,v0,-55 -bfc00f90: 2445ffd0 addiu a1,v0,-48 -bfc00f94: 2c420041 sltiu v0,v0,65 -bfc00f98: 10400002 beqz v0,bfc00fa4 -bfc00f9c: 308400ff andi a0,a0,0xff -bfc00fa0: 30a400ff andi a0,a1,0xff -bfc00fa4: 90e20001 lbu v0,1(a3) -bfc00fa8: 308700ff andi a3,a0,0xff -bfc00fac: 2445ffc9 addiu a1,v0,-55 -bfc00fb0: 2444ffd0 addiu a0,v0,-48 -bfc00fb4: 2c420041 sltiu v0,v0,65 -bfc00fb8: 14400002 bnez v0,bfc00fc4 -bfc00fbc: 308400ff andi a0,a0,0xff -bfc00fc0: 30a400ff andi a0,a1,0xff -bfc00fc4: 00071100 sll v0,a3,0x4 -bfc00fc8: 00821025 or v0,a0,v0 -bfc00fcc: 304200ff andi v0,v0,0xff -bfc00fd0: 00661821 addu v1,v1,a2 -bfc00fd4: 004b2021 addu a0,v0,t3 -bfc00fd8: a0620000 sb v0,0(v1) -bfc00fdc: 308b00ff andi t3,a0,0xff -bfc00fe0: 24c60001 addiu a2,a2,1 -bfc00fe4: 8d420004 lw v0,4(t2) -bfc00fe8: 8d43000c lw v1,12(t2) -bfc00fec: 00062040 sll a0,a2,0x1 -bfc00ff0: 00c2102a slt v0,a2,v0 -bfc00ff4: 1440ffe3 bnez v0,bfc00f84 -bfc00ff8: 00643821 addu a3,v1,a0 -bfc00ffc: 90e40000 lbu a0,0(a3) -bfc01000: 00000000 nop -bfc01004: 2c820041 sltiu v0,a0,65 -bfc01008: 10400003 beqz v0,bfc01018 -bfc0100c: 00e01821 move v1,a3 -bfc01010: 0bf00407 j bfc0101c -bfc01014: 2482ffd0 addiu v0,a0,-48 -bfc01018: 2482ffc9 addiu v0,a0,-55 -bfc0101c: 90630001 lbu v1,1(v1) -bfc01020: 304200ff andi v0,v0,0xff -bfc01024: 304400ff andi a0,v0,0xff -bfc01028: 2c620041 sltiu v0,v1,65 -bfc0102c: 10400002 beqz v0,bfc01038 -bfc01030: 2462ffc9 addiu v0,v1,-55 -bfc01034: 2462ffd0 addiu v0,v1,-48 -bfc01038: 304200ff andi v0,v0,0xff -bfc0103c: 00041900 sll v1,a0,0x4 -bfc01040: 00431825 or v1,v0,v1 -bfc01044: 000b1027 nor v0,zero,t3 -bfc01048: 304200ff andi v0,v0,0xff -bfc0104c: 306300ff andi v1,v1,0xff -bfc01050: 14430004 bne v0,v1,bfc01064 -bfc01054: 00000000 nop -bfc01058: 8d420008 lw v0,8(t2) -bfc0105c: 03e00008 jr ra -bfc01060: 00000000 nop -bfc01064: 03e00008 jr ra -bfc01068: 00001021 move v0,zero - -bfc0106c : -bfc0106c: 00800008 jr a0 -bfc01070: 00000000 nop -bfc01074: 03e00008 jr ra -bfc01078: 00000000 nop - -bfc0107c : -bfc0107c: 3c1a1000 lui k0,0x1000 -bfc01080: 409a6000 mtc0 k0,c0_sr -bfc01084: 00800008 jr a0 -bfc01088: 42000010 rfe -bfc0108c: 03e00008 jr ra -bfc01090: 00000000 nop - -bfc01094 : -bfc01094: 401a6000 mfc0 k0,c0_sr -bfc01098: 3c1bffbf lui k1,0xffbf -bfc0109c: 377bffff ori k1,k1,0xffff -bfc010a0: 035bd024 and k0,k0,k1 -bfc010a4: 3c1b0200 lui k1,0x200 -bfc010a8: 035bd025 or k0,k0,k1 -bfc010ac: 409a6000 mtc0 k0,c0_sr -bfc010b0: 00800008 jr a0 -bfc010b4: 42000010 rfe -bfc010b8: 03e00008 jr ra -bfc010bc: 00000000 nop - -bfc010c0 : -bfc010c0: 27bdffd8 addiu sp,sp,-40 -bfc010c4: afb30020 sw s3,32(sp) -bfc010c8: afb10018 sw s1,24(sp) -bfc010cc: afb00014 sw s0,20(sp) -bfc010d0: afbf0024 sw ra,36(sp) -bfc010d4: afb2001c sw s2,28(sp) -bfc010d8: 00809821 move s3,a0 -bfc010dc: 24110073 li s1,115 -bfc010e0: 24100053 li s0,83 -bfc010e4: 0ff00081 jal bfc00204 -bfc010e8: 00000000 nop -bfc010ec: 14510005 bne v0,s1,bfc01104 -bfc010f0: 00000000 nop -bfc010f4: 00008021 move s0,zero -bfc010f8: 2412000a li s2,10 -bfc010fc: 0bf00449 j bfc01124 -bfc01100: 2411000d li s1,13 -bfc01104: 1450fff7 bne v0,s0,bfc010e4 -bfc01108: 00000000 nop -bfc0110c: 0bf0043e j bfc010f8 -bfc01110: 00008021 move s0,zero -bfc01114: 0ff00081 jal bfc00204 -bfc01118: a0620000 sb v0,0(v1) -bfc0111c: 10510003 beq v0,s1,bfc0112c -bfc01120: 26100001 addiu s0,s0,1 -bfc01124: 1452fffb bne v0,s2,bfc01114 -bfc01128: 02701821 addu v1,s3,s0 -bfc0112c: 8fbf0024 lw ra,36(sp) -bfc01130: 02001021 move v0,s0 -bfc01134: 8fb30020 lw s3,32(sp) -bfc01138: 8fb2001c lw s2,28(sp) -bfc0113c: 8fb10018 lw s1,24(sp) -bfc01140: 8fb00014 lw s0,20(sp) -bfc01144: 03e00008 jr ra -bfc01148: 27bd0028 addiu sp,sp,40 - -bfc0114c

: -bfc0114c: 27bdfd98 addiu sp,sp,-616 -bfc01150: 27a40140 addiu a0,sp,320 -bfc01154: 00002821 move a1,zero -bfc01158: 24060100 li a2,256 -bfc0115c: afb20248 sw s2,584(sp) -bfc01160: afb10244 sw s1,580(sp) -bfc01164: afb00240 sw s0,576(sp) -bfc01168: 3c11a000 lui s1,0xa000 -bfc0116c: afbf0264 sw ra,612(sp) -bfc01170: afbe0260 sw s8,608(sp) -bfc01174: afb7025c sw s7,604(sp) -bfc01178: afb60258 sw s6,600(sp) -bfc0117c: afb50254 sw s5,596(sp) -bfc01180: afb40250 sw s4,592(sp) -bfc01184: 0ff0056b jal bfc015ac -bfc01188: afb3024c sw s3,588(sp) -bfc0118c: 3c036000 lui v1,0x6000 -bfc01190: 36220004 ori v0,s1,0x4 -bfc01194: 3463b1ff ori v1,v1,0xb1ff -bfc01198: ac430000 sw v1,0(v0) -bfc0119c: 3c022000 lui v0,0x2000 -bfc011a0: 27b20020 addiu s2,sp,32 -bfc011a4: 34421000 ori v0,v0,0x1000 -bfc011a8: ae220000 sw v0,0(s1) -bfc011ac: 02402021 move a0,s2 -bfc011b0: 3c05a400 lui a1,0xa400 -bfc011b4: 8e300000 lw s0,0(s1) -bfc011b8: 0ff002eb jal bfc00bac -bfc011bc: 00000000 nop -bfc011c0: 04410004 bgez v0,bfc011d4 -bfc011c4: 00102c02 srl a1,s0,0x10 -bfc011c8: 3c04bfc0 lui a0,0xbfc0 -bfc011cc: 0bf00494 j bfc01250 -bfc011d0: 248416a4 addiu a0,a0,5796 -bfc011d4: 02402021 move a0,s2 -bfc011d8: 0ff00358 jal bfc00d60 -bfc011dc: 30a5007f andi a1,a1,0x7f -bfc011e0: 00409021 move s2,v0 -bfc011e4: 8e220000 lw v0,0(s1) -bfc011e8: 00000000 nop -bfc011ec: 00021602 srl v0,v0,0x18 -bfc011f0: 30420008 andi v0,v0,0x8 -bfc011f4: 14400044 bnez v0,bfc01308 -bfc011f8: 3c11bfc0 lui s1,0xbfc0 -bfc011fc: 0ff000b0 jal bfc002c0 -bfc01200: 26241758 addiu a0,s1,5976 -bfc01204: 3c02a400 lui v0,0xa400 -bfc01208: 02428021 addu s0,s2,v0 -bfc0120c: 8e030000 lw v1,0(s0) -bfc01210: 3c023149 lui v0,0x3149 -bfc01214: 3442464a ori v0,v0,0x464a -bfc01218: 10620011 beq v1,v0,bfc01260 -bfc0121c: 3c024a46 lui v0,0x4a46 -bfc01220: 34424931 ori v0,v0,0x4931 -bfc01224: 1062000e beq v1,v0,bfc01260 -bfc01228: 00000000 nop -bfc0122c: 0ff000b0 jal bfc002c0 -bfc01230: 26241758 addiu a0,s1,5976 -bfc01234: 3c04bfc0 lui a0,0xbfc0 -bfc01238: 0ff000b0 jal bfc002c0 -bfc0123c: 248416cc addiu a0,a0,5836 -bfc01240: 0ff000e8 jal bfc003a0 -bfc01244: 02402021 move a0,s2 -bfc01248: 3c04bfc0 lui a0,0xbfc0 -bfc0124c: 248416e4 addiu a0,a0,5860 -bfc01250: 0ff000b0 jal bfc002c0 -bfc01254: 00000000 nop -bfc01258: 0bf0055f j bfc0157c -bfc0125c: 24020001 li v0,1 -bfc01260: 3c04bfc0 lui a0,0xbfc0 -bfc01264: 0ff000b0 jal bfc002c0 -bfc01268: 248416f0 addiu a0,a0,5872 -bfc0126c: 0ff000e8 jal bfc003a0 -bfc01270: 02402021 move a0,s2 -bfc01274: 3c04bfc0 lui a0,0xbfc0 -bfc01278: 0ff000b0 jal bfc002c0 -bfc0127c: 24841714 addiu a0,a0,5908 -bfc01280: 8e02000c lw v0,12(s0) -bfc01284: 8e110004 lw s1,4(s0) -bfc01288: 00024082 srl t0,v0,0x2 -bfc0128c: 8e070008 lw a3,8(s0) -bfc01290: 00002021 move a0,zero -bfc01294: 0bf004aa j bfc012a8 -bfc01298: 00001821 move v1,zero -bfc0129c: 8cc20000 lw v0,0(a2) -bfc012a0: 00000000 nop -bfc012a4: aca20000 sw v0,0(a1) -bfc012a8: 0088102b sltu v0,a0,t0 -bfc012ac: 00673021 addu a2,v1,a3 -bfc012b0: 00712821 addu a1,v1,s1 -bfc012b4: 24840001 addiu a0,a0,1 -bfc012b8: 1440fff8 bnez v0,bfc0129c -bfc012bc: 24630004 addiu v1,v1,4 -bfc012c0: 3c04bfc0 lui a0,0xbfc0 -bfc012c4: 0ff000b0 jal bfc002c0 -bfc012c8: 2484171c addiu a0,a0,5916 -bfc012cc: 3c04bfc0 lui a0,0xbfc0 -bfc012d0: 0ff000b0 jal bfc002c0 -bfc012d4: 24841724 addiu a0,a0,5924 -bfc012d8: 8e040004 lw a0,4(s0) -bfc012dc: 0ff000e8 jal bfc003a0 -bfc012e0: 00000000 nop -bfc012e4: 3c04bfc0 lui a0,0xbfc0 -bfc012e8: 0ff000b0 jal bfc002c0 -bfc012ec: 24841758 addiu a0,a0,5976 -bfc012f0: 3c1a1000 lui k0,0x1000 -bfc012f4: 409a6000 mtc0 k0,c0_sr -bfc012f8: 02200008 jr s1 -bfc012fc: 42000010 rfe -bfc01300: 0bf0055f j bfc0157c -bfc01304: 00001021 move v0,zero -bfc01308: 0ff000b0 jal bfc002c0 -bfc0130c: 26241758 addiu a0,s1,5976 -bfc01310: 3c04bfc0 lui a0,0xbfc0 -bfc01314: 0ff000b0 jal bfc002c0 -bfc01318: 24841730 addiu a0,a0,5936 -bfc0131c: 3c024000 lui v0,0x4000 -bfc01320: 3c034010 lui v1,0x4010 -bfc01324: ac400000 sw zero,0(v0) -bfc01328: 24420004 addiu v0,v0,4 -bfc0132c: 1443fffd bne v0,v1,bfc01324 -bfc01330: 00009821 move s3,zero -bfc01334: 3c02bfc0 lui v0,0xbfc0 -bfc01338: 245516c8 addiu s5,v0,5832 -bfc0133c: 3c02bfc0 lui v0,0xbfc0 -bfc01340: 2456171c addiu s6,v0,5916 -bfc01344: 3c02bfc0 lui v0,0xbfc0 -bfc01348: 245e17d0 addiu s8,v0,6096 -bfc0134c: 3c02bfc0 lui v0,0xbfc0 -bfc01350: 245717f0 addiu s7,v0,6128 -bfc01354: 3c04bfc0 lui a0,0xbfc0 -bfc01358: 0ff000b0 jal bfc002c0 -bfc0135c: 24841750 addiu a0,a0,5968 -bfc01360: 3c14bfc0 lui s4,0xbfc0 -bfc01364: 27b00040 addiu s0,sp,64 -bfc01368: 0ff00430 jal bfc010c0 -bfc0136c: 02002021 move a0,s0 -bfc01370: 00403021 move a2,v0 -bfc01374: 02002821 move a1,s0 -bfc01378: 27a40010 addiu a0,sp,16 -bfc0137c: 0ff00384 jal bfc00e10 -bfc01380: 00408821 move s1,v0 -bfc01384: 00401821 move v1,v0 -bfc01388: 24020002 li v0,2 -bfc0138c: 10620005 beq v1,v0,bfc013a4 -bfc01390: 24020004 li v0,4 -bfc01394: 1462ffef bne v1,v0,bfc01354 -bfc01398: 00000000 nop -bfc0139c: 0bf004fe j bfc013f8 -bfc013a0: 3c04bfc0 lui a0,0xbfc0 -bfc013a4: 8fa50010 lw a1,16(sp) -bfc013a8: 8fa60014 lw a2,20(sp) -bfc013ac: 0bf004f3 j bfc013cc -bfc013b0: 00001821 move v1,zero -bfc013b4: 8fa2001c lw v0,28(sp) -bfc013b8: 00000000 nop -bfc013bc: 00431021 addu v0,v0,v1 -bfc013c0: 90420000 lbu v0,0(v0) -bfc013c4: 24630001 addiu v1,v1,1 -bfc013c8: a0820000 sb v0,0(a0) -bfc013cc: 8fa20014 lw v0,20(sp) -bfc013d0: 00000000 nop -bfc013d4: 0062102b sltu v0,v1,v0 -bfc013d8: 1440fff6 bnez v0,bfc013b4 -bfc013dc: 00652021 addu a0,v1,a1 -bfc013e0: 00c51821 addu v1,a2,a1 -bfc013e4: 0263102b sltu v0,s3,v1 -bfc013e8: 10400060 beqz v0,bfc0156c -bfc013ec: 02208021 move s0,s1 -bfc013f0: 0bf0055b j bfc0156c -bfc013f4: 00609821 move s3,v1 -bfc013f8: 0ff000b0 jal bfc002c0 -bfc013fc: 24841754 addiu a0,a0,5972 -bfc01400: 8fa60010 lw a2,16(sp) -bfc01404: 26470100 addiu a3,s2,256 -bfc01408: 02661823 subu v1,s3,a2 -bfc0140c: 27b10020 addiu s1,sp,32 -bfc01410: 3c024a46 lui v0,0x4a46 -bfc01414: 00e32821 addu a1,a3,v1 -bfc01418: 02202021 move a0,s1 -bfc0141c: 34424931 ori v0,v0,0x4931 -bfc01420: afa60144 sw a2,324(sp) -bfc01424: afa3014c sw v1,332(sp) -bfc01428: afa70148 sw a3,328(sp) -bfc0142c: 0ff00364 jal bfc00d90 -bfc01430: afa20140 sw v0,320(sp) -bfc01434: 3c04bfc0 lui a0,0xbfc0 -bfc01438: 2484175c addiu a0,a0,5980 -bfc0143c: 0ff000b0 jal bfc002c0 -bfc01440: afa20150 sw v0,336(sp) -bfc01444: 8fa4014c lw a0,332(sp) -bfc01448: 0ff000e8 jal bfc003a0 -bfc0144c: 00000000 nop -bfc01450: 0ff000b0 jal bfc002c0 -bfc01454: 02a02021 move a0,s5 -bfc01458: 3c04bfc0 lui a0,0xbfc0 -bfc0145c: 0ff000b0 jal bfc002c0 -bfc01460: 24841778 addiu a0,a0,6008 -bfc01464: 0ff000e8 jal bfc003a0 -bfc01468: 02402021 move a0,s2 -bfc0146c: 0ff000b0 jal bfc002c0 -bfc01470: 02a02021 move a0,s5 -bfc01474: 3c04bfc0 lui a0,0xbfc0 -bfc01478: 0ff000b0 jal bfc002c0 -bfc0147c: 24841794 addiu a0,a0,6036 -bfc01480: 8fa40150 lw a0,336(sp) -bfc01484: 0ff000e8 jal bfc003a0 -bfc01488: 00000000 nop -bfc0148c: 0ff000b0 jal bfc002c0 -bfc01490: 02a02021 move a0,s5 -bfc01494: 3c04bfc0 lui a0,0xbfc0 -bfc01498: 0ff000b0 jal bfc002c0 -bfc0149c: 248417b0 addiu a0,a0,6064 -bfc014a0: 8fa6014c lw a2,332(sp) -bfc014a4: 02202021 move a0,s1 -bfc014a8: 24c60100 addiu a2,a2,256 -bfc014ac: 0ff00304 jal bfc00c10 -bfc014b0: 02402821 move a1,s2 -bfc014b4: 0440001f bltz v0,bfc01534 -bfc014b8: 00408021 move s0,v0 -bfc014bc: 0ff000b0 jal bfc002c0 -bfc014c0: 02c02021 move a0,s6 -bfc014c4: 0ff000b0 jal bfc002c0 -bfc014c8: 03c02021 move a0,s8 -bfc014cc: 02202021 move a0,s1 -bfc014d0: 02402821 move a1,s2 -bfc014d4: 27a60140 addiu a2,sp,320 -bfc014d8: 0ff00334 jal bfc00cd0 -bfc014dc: 24070100 li a3,256 -bfc014e0: 04400014 bltz v0,bfc01534 -bfc014e4: 00408021 move s0,v0 -bfc014e8: 8fa50148 lw a1,328(sp) -bfc014ec: 8fa60144 lw a2,324(sp) -bfc014f0: 8fa7014c lw a3,332(sp) -bfc014f4: 0ff00334 jal bfc00cd0 -bfc014f8: 02202021 move a0,s1 -bfc014fc: 0440000d bltz v0,bfc01534 -bfc01500: 00408021 move s0,v0 -bfc01504: 0ff000b0 jal bfc002c0 -bfc01508: 02c02021 move a0,s6 -bfc0150c: 3c04bfc0 lui a0,0xbfc0 -bfc01510: 0ff000b0 jal bfc002c0 -bfc01514: 248417e0 addiu a0,a0,6112 -bfc01518: 8fa50148 lw a1,328(sp) -bfc0151c: 8fa60144 lw a2,324(sp) -bfc01520: 8fa7014c lw a3,332(sp) -bfc01524: 0ff0033c jal bfc00cf0 -bfc01528: 02202021 move a0,s1 -bfc0152c: 0441000a bgez v0,bfc01558 -bfc01530: 00408021 move s0,v0 -bfc01534: 0ff000b0 jal bfc002c0 -bfc01538: 268417c0 addiu a0,s4,6080 -bfc0153c: 0ff000e8 jal bfc003a0 -bfc01540: 02002021 move a0,s0 -bfc01544: 3c04bfc0 lui a0,0xbfc0 -bfc01548: 0ff000b0 jal bfc002c0 -bfc0154c: 248417cc addiu a0,a0,6092 -bfc01550: 0bf0055b j bfc0156c -bfc01554: 00000000 nop -bfc01558: 0ff000b0 jal bfc002c0 -bfc0155c: 02e02021 move a0,s7 -bfc01560: 3c02bfc0 lui v0,0xbfc0 -bfc01564: 00400008 jr v0 -bfc01568: 00000000 nop -bfc0156c: 0601ff7e bgez s0,bfc01368 -bfc01570: 27b00040 addiu s0,sp,64 -bfc01574: 0bf004d6 j bfc01358 -bfc01578: 3c04bfc0 lui a0,0xbfc0 -bfc0157c: 8fbf0264 lw ra,612(sp) -bfc01580: 8fbe0260 lw s8,608(sp) -bfc01584: 8fb7025c lw s7,604(sp) -bfc01588: 8fb60258 lw s6,600(sp) -bfc0158c: 8fb50254 lw s5,596(sp) -bfc01590: 8fb40250 lw s4,592(sp) -bfc01594: 8fb3024c lw s3,588(sp) -bfc01598: 8fb20248 lw s2,584(sp) -bfc0159c: 8fb10244 lw s1,580(sp) -bfc015a0: 8fb00240 lw s0,576(sp) -bfc015a4: 03e00008 jr ra -bfc015a8: 27bd0268 addiu sp,sp,616 - -bfc015ac : -bfc015ac: 2cc20010 sltiu v0,a2,16 -bfc015b0: 00804821 move t1,a0 -bfc015b4: 1440002d bnez v0,bfc0166c -bfc015b8: 00804021 move t0,a0 -bfc015bc: 30870003 andi a3,a0,0x3 -bfc015c0: 10e0000e beqz a3,bfc015fc -bfc015c4: 24820004 addiu v0,a0,4 -bfc015c8: 00052600 sll a0,a1,0x18 -bfc015cc: 00471023 subu v0,v0,a3 -bfc015d0: 00042603 sra a0,a0,0x18 -bfc015d4: 01201821 move v1,t1 -bfc015d8: a0640000 sb a0,0(v1) -bfc015dc: 24630001 addiu v1,v1,1 -bfc015e0: 1462fffd bne v1,v0,bfc015d8 -bfc015e4: 00000000 nop -bfc015e8: 00071027 nor v0,zero,a3 -bfc015ec: 24c3fffb addiu v1,a2,-5 -bfc015f0: 24440005 addiu a0,v0,5 -bfc015f4: 00623023 subu a2,v1,v0 -bfc015f8: 01244021 addu t0,t1,a0 -bfc015fc: 30a500ff andi a1,a1,0xff -bfc01600: 01003821 move a3,t0 -bfc01604: 10a00005 beqz a1,bfc0161c -bfc01608: 00a01821 move v1,a1 -bfc0160c: 00051200 sll v0,a1,0x8 -bfc01610: 00451025 or v0,v0,a1 -bfc01614: 00021c00 sll v1,v0,0x10 -bfc01618: 00621825 or v1,v1,v0 -bfc0161c: 000610c2 srl v0,a2,0x3 -bfc01620: 1040001c beqz v0,bfc01694 -bfc01624: 30c60007 andi a2,a2,0x7 -bfc01628: 01002021 move a0,t0 -bfc0162c: 00403821 move a3,v0 -bfc01630: 24e7ffff addiu a3,a3,-1 -bfc01634: ac830000 sw v1,0(a0) -bfc01638: ac830004 sw v1,4(a0) -bfc0163c: 14e0fffc bnez a3,bfc01630 -bfc01640: 24840008 addiu a0,a0,8 -bfc01644: 000210c0 sll v0,v0,0x3 -bfc01648: 01023821 addu a3,t0,v0 -bfc0164c: 00e02021 move a0,a3 -bfc01650: 2cc20004 sltiu v0,a2,4 -bfc01654: 14400005 bnez v0,bfc0166c -bfc01658: 00804021 move t0,a0 -bfc0165c: ace30000 sw v1,0(a3) -bfc01660: 24e40004 addiu a0,a3,4 -bfc01664: 24c6fffc addiu a2,a2,-4 -bfc01668: 00804021 move t0,a0 -bfc0166c: 10c00007 beqz a2,bfc0168c -bfc01670: 00000000 nop -bfc01674: 00051600 sll v0,a1,0x18 -bfc01678: 00021603 sra v0,v0,0x18 -bfc0167c: 24c6ffff addiu a2,a2,-1 -bfc01680: a1020000 sb v0,0(t0) -bfc01684: 14c0fffd bnez a2,bfc0167c -bfc01688: 25080001 addiu t0,t0,1 -bfc0168c: 03e00008 jr ra -bfc01690: 01201021 move v0,t1 -bfc01694: 0bf00594 j bfc01650 -bfc01698: 01002021 move a0,t0 diff --git a/lib/CPUs/MIPS/src/core/.directory_history b/lib/CPUs/MIPS/src/core/.directory_history deleted file mode 100644 index 1dd52df..0000000 --- a/lib/CPUs/MIPS/src/core/.directory_history +++ /dev/null @@ -1,12 +0,0 @@ -VHDL/lib/CPUs/MIPS/src/core/dcache.vhd -VHDL/lib/CPUs/MIPS/src/core/mips_dcache.vhd -VHDL/lib/CPUs/MIPS/src/core/icache.vhd -VHDL/lib/CPUs/MIPS/src/core/mips_icache.vhd -VHDL/lib/CPUs/MIPS/src/core/mips_biu.vhd - -VHDL/lib/CPUs/MIPS/src/core/mips_bui.vhd -VHDL/lib/CPUs/MIPS/src/core/mips_biu.vhd -VHDL/lib/CPUs/MIPS/src/core/mips_dcache.vhd - -VHDL/lib/CPUs/MIPS/src/core/mips_icache.vhd - diff --git a/lib/CPUs/MIPS/src/core/dcache.vhd b/lib/CPUs/MIPS/src/core/dcache.vhd deleted file mode 100644 index 85d1639..0000000 --- a/lib/CPUs/MIPS/src/core/dcache.vhd +++ /dev/null @@ -1,513 +0,0 @@ --------------------------------------------------------------------------- --- Project: JIPS, a portable 32-bit RISC CPU written in VHDL --- This file: JIPS top file --- --- Copyright (C) 2008 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -library work; -use work.mips_types.all; - -ENTITY dcache IS - Generic - ( - cache_size : natural := 2048; -- words - line_size : natural := 8 -- words - ); - Port - ( - RST_I : in STD_LOGIC; - CLK_I : in STD_LOGIC; - ACK_I : in STD_LOGIC; - SRDY_I : in STD_LOGIC; - MRDY_O : out STD_LOGIC; - ADDR_O : out word_t; - DAT_I : in word_t; - STB_O : out STD_LOGIC; - CYC_O : out STD_LOGIC; - ctrl : in cache_ctrl_t; - cpu_en : in STD_LOGIC; - cpu_we : in STD_LOGIC; - cpu_be : in unsigned(3 downto 0); - cpu_addr : in word_t; - cpu_din : in word_t; - cpu_dout : out word_t; - cpu_busy : out STD_LOGIC - ); -END dcache; - -ARCHITECTURE behavior OF dcache IS - - -COMPONENT dpram_2w2r2c_ra is - GENERIC - ( - addr_width : integer := 3; - data_width : integer := 8 - ); - PORT - ( - clk_a : in STD_LOGIC; - clk_b : in STD_LOGIC; - en_a : in STD_LOGIC; - en_b : in STD_LOGIC; - we_a : in STD_LOGIC; - we_b : in STD_LOGIC; - addr_a : in unsigned (addr_width-1 downto 0); - addr_b : in unsigned (addr_width-1 downto 0); - din_a : in unsigned (data_width-1 downto 0); - din_b : in unsigned (data_width-1 downto 0); - dout_a : out unsigned (data_width-1 downto 0); - dout_b : out unsigned (data_width-1 downto 0) - ); -END COMPONENT; - - constant addr_width : natural := 32; - constant word_index_width : natural := lg2(line_size); - constant cache_index_width : natural := lg2(cache_size) - word_index_width; - constant tag_width : natural := addr_width - word_index_width - cache_index_width - 2; - constant tag_parity_width : natural := 3; - constant tag_ram_data_width : natural := 1 + tag_parity_width + tag_width; - constant tag_ram_addr_width : natural := cache_index_width; - - subtype tag_ram_data_t is unsigned (tag_ram_data_width-1 downto 0); - - type dcache_entry_t is record - valid : std_logic; - tv_p : unsigned(tag_parity_width-1 downto 0); - tag : unsigned(tag_width-1 downto 0); - end record; - - function to_dcache_entry(x : tag_ram_data_t) return dcache_entry_t is - variable result : dcache_entry_t; - begin - result.valid := x(0); - result.tv_p := x(3 downto 1); - result.tag := x(tag_width+3 downto 4); - - return result; - end to_dcache_entry; - - function to_tag_ram_data(x : dcache_entry_t) return tag_ram_data_t is - variable result : tag_ram_data_t; - begin - result(0) := x.valid; - result(3 downto 1) := x.tv_p; - result(tag_width+3 downto 4) := x.tag; - - return result; - end to_tag_ram_data; - - type cache_state_t is (init, ready, invalidate, flush, mem_request, mem_access, mem_data, rd_cache); - signal s, sn : cache_state_t; - - signal cache_req : std_logic; - signal cache_ack : std_logic; - signal cache_busy : std_logic; - signal cache_hit : std_logic; - signal tag_match : std_logic; - signal cache_hit_inv : std_logic; - signal tag_match_inv : std_logic; - - signal request_addr : unsigned(addr_width-1 downto 0); - signal fill_addr : unsigned(addr_width-1 downto 0); - - signal cache_index_inv : unsigned(cache_index_width-1 downto 0); - signal tag_inv : unsigned(tag_width-1 downto 0); - signal tag_reg_inv : unsigned(tag_width-1 downto 0); - - signal cache_entry_in : dcache_entry_t; - signal cache_entry_out : dcache_entry_t; - signal cache_entry_out_inv : dcache_entry_t; - signal cpu_data_ram_addr : unsigned(lg2(cache_size)-1 downto 0); - signal cpu_data_ram_dout : word_t; - signal cpu_data_reg : word_t; - signal cpu_be_reg : unsigned(3 downto 0); - signal cpu_we_reg : std_logic; - signal ctrl_data_ram_addr : unsigned(lg2(cache_size)-1 downto 0); - signal ctrl_data_ram_we : unsigned(3 downto 0); - signal cpu_data_ram_we : unsigned(3 downto 0); - signal cpu_we2 : std_logic; - - signal tag_ram_addr_rd : unsigned(cache_index_width-1 downto 0); - signal tag_ram_dout : tag_ram_data_t; - signal tag_ram_dout_inv : tag_ram_data_t; - signal tag_ram_addr_wr : unsigned(cache_index_width-1 downto 0); - signal tag_ram_din : tag_ram_data_t; - signal tag_ram_we : std_logic; - - signal fill_count : natural range 0 to 2**word_index_width-1; - signal fill_count_en : std_logic; - signal fill_count_rdy : std_logic; - signal flush_count : natural range 0 to 2**cache_index_width-1; - signal flush_count_rst : std_logic; - signal flush_count_en : std_logic; - signal flush_count_rdy : std_logic; - signal request_count : natural range 0 to 2**word_index_width-1; - signal request_count_en : std_logic; - signal request_count_rdy : std_logic; - signal was_miss : std_logic; - signal invalidate_all : std_logic; - signal invalidate_ack : std_logic; - signal invalidate_en : std_logic; - signal invalidate_req : std_logic; - signal cpu_hit_we : std_logic; - signal instant_raw : std_logic; - signal hit_cache_index : unsigned(cache_index_width-1 downto 0); - - alias cpu_word_index is cpu_addr(word_index_width+1 downto 2); - alias cpu_cache_index is cpu_addr(cache_index_width+word_index_width+1 downto word_index_width+2); - alias cpu_tag is cpu_addr(tag_width+cache_index_width+word_index_width+1 downto cache_index_width+word_index_width+2); - - alias fill_word_index is fill_addr(word_index_width+1 downto 2); - alias fill_cache_index is fill_addr(cache_index_width+word_index_width+1 downto word_index_width+2); - alias fill_tag is fill_addr(tag_width+cache_index_width+word_index_width+1 downto cache_index_width+word_index_width+2); - - alias req_word_index is request_addr(word_index_width+1 downto 2); - alias req_cache_index is request_addr(cache_index_width+word_index_width+1 downto word_index_width+2); - alias req_tag is request_addr(tag_width+cache_index_width+word_index_width+1 downto cache_index_width+word_index_width+2); - -begin - - cache_index_inv <= ctrl.inv_addr(cache_index_width+word_index_width+1 downto word_index_width+2); - tag_inv <= ctrl.inv_addr(tag_width+cache_index_width+word_index_width+1 downto cache_index_width+word_index_width+2); - - cpu_hit_we <= cpu_we2 and cache_hit; - -fill_address_register: - process(CLK_I) - begin - if rising_edge(CLK_I) then - if fill_count_en = '1' then - if ACK_I = '1' then - fill_word_index <= fill_word_index + 1; - end if; - elsif cache_busy = '0' then - fill_addr <= cpu_addr(addr_width-1 downto 2) & "00"; - end if; - end if; - end process; - -request_address_register: - process(CLK_I) - begin - if rising_edge(CLK_I) then - if request_count_en = '1'then - if SRDY_I = '1' then - req_word_index <= req_word_index + 1; - end if; - elsif cache_busy = '0' then - request_addr <= cpu_addr(addr_width-1 downto 2) & "00"; - end if; - end if; - end process; - -cpu_request_register: - process(CLK_I) - begin - if rising_edge(CLK_I) then - if RST_I = '1' then - cpu_we_reg <= '0'; - cache_req <= '0'; - elsif cpu_en = '1' then - if cache_busy = '0' then - cpu_we2 <= cpu_we; - cache_req <= '1'; - cpu_data_reg <= cpu_din; - cpu_be_reg <= cpu_be; - cpu_we_reg <= cpu_we; - if cpu_we = '1' then - hit_cache_index <= cpu_cache_index; - end if; - end if; - elsif cache_ack = '1' then - cache_req <= '0'; - cpu_we2 <= '0'; - end if; - end if; - end process; - -instant_raw_logic: - process(CLK_I) - begin - if rising_edge(CLK_I) then - instant_raw <= '0'; - if cpu_word_index = fill_word_index and cpu_cache_index = hit_cache_index then - instant_raw <= cpu_hit_we and cpu_en and not cpu_we; - end if; - end if; - end process; - -inst_tag_ram : dpram_2w2r2c_ra - GENERIC MAP - ( - addr_width => tag_ram_addr_width, - data_width => tag_ram_data_width - ) - PORT MAP - ( - clk_a => CLK_I, - clk_b => CLK_I, - en_a => '1', - en_b => '1', - we_a => tag_ram_we, - we_b => '0', - addr_a => tag_ram_addr_wr, - addr_b => tag_ram_addr_rd, - din_a => tag_ram_din, - din_b => tag_ram_din, - dout_a => tag_ram_dout_inv, - dout_b => tag_ram_dout - ); - -gen_data_ram: - for i in 0 to 3 generate - begin - - inst_data_ram : dpram_2w2r2c_ra - GENERIC MAP - ( - addr_width => lg2(cache_size), - data_width => word_t'length/4 - ) - PORT MAP - ( - clk_a => CLK_I, - clk_b => CLK_I, - en_a => '1', - en_b => '1', - we_a => cpu_data_ram_we(i), - we_b => ctrl_data_ram_we(i), - addr_a => ctrl_data_ram_addr, - addr_b => cpu_data_ram_addr, - din_a => cpu_data_reg(8*(i+1)-1 downto 8*i), - din_b => DAT_I(8*(i+1)-1 downto 8*i), - dout_a => open, - dout_b => cpu_data_ram_dout(8*(i+1)-1 downto 8*i) - ); - end generate; - - - -cache_invalidate_request: - process(CLK_I) - begin - if rising_edge(CLK_I) then - if RST_I = '1' or ctrl.inv_all = '1' or ctrl.inv_at = '1' then - invalidate_req <= '1'; - invalidate_all <= ctrl.inv_all or RST_I; - tag_reg_inv <= tag_inv; - elsif invalidate_ack = '1' then - invalidate_req <= '0'; - invalidate_all <= '0'; - end if; - end if; - end process; - -cache_state_next: - process(CLK_I) - begin - if rising_edge(CLK_I) then - if RST_I = '1' then - s <= init; - else - s <= sn; - end if; - end if; - end process; - - MRDY_O <= fill_count_en; - ADDR_O <= request_addr; - - cpu_busy <= cache_busy; - cpu_dout <= cpu_data_ram_dout; - - tag_match <= '1' when fill_tag = cache_entry_out.tag else '0'; - cache_hit <= tag_match and cache_entry_out.valid; - tag_match_inv <= '1' when tag_reg_inv = cache_entry_out_inv.tag else '0'; - cache_hit_inv <= tag_match_inv and cache_entry_out_inv.valid; - tag_ram_din <= to_tag_ram_data(cache_entry_in); - tag_ram_addr_wr <= to_unsigned(flush_count, cache_index_width) when invalidate_en = '1' else fill_cache_index; - tag_ram_addr_rd <= cpu_cache_index when (was_miss = '0' and instant_raw = '0') else fill_cache_index; - - cache_entry_out <= to_dcache_entry(tag_ram_dout); - cache_entry_out_inv <= to_dcache_entry(tag_ram_dout_inv); - - cpu_data_ram_addr <= (cpu_cache_index & cpu_word_index) when (was_miss = '0' and instant_raw = '0' and fill_count_en = '0') else (fill_cache_index & fill_word_index); - ctrl_data_ram_addr <= fill_cache_index & fill_word_index; - ctrl_data_ram_we <= (others => fill_count_en and ACK_I); - cpu_data_ram_we <= cpu_be_reg when (cpu_hit_we = '1') else (others => '0'); - -cache_state: - process(s, cache_req, instant_raw, cache_hit, cache_hit_inv, flush_count_rdy, fill_count_rdy, request_count_rdy, fill_tag, SRDY_I, cpu_we_reg, invalidate_req, invalidate_all) - begin - cache_busy <= cache_req; - cache_ack <= '0'; - tag_ram_we <= '0'; - flush_count_en <= '0'; - flush_count_rst <= '0'; - invalidate_en <= '0'; - request_count_en <= '0'; - fill_count_en <= '0'; - CYC_O <= '0'; - STB_O <= '0'; - was_miss <= '0'; - invalidate_ack <= '0'; - - cache_entry_in.tv_p <= (others => '0'); - cache_entry_in.tag <= fill_tag; - cache_entry_in.valid <= '0'; - sn <= s; - - case s is - when init => - sn <= ready; - when ready => - if invalidate_req = '1' then - sn <= invalidate; - invalidate_en <= '1'; - else - if cache_req = '1' then - if cache_hit = '0' and cpu_we_reg = '0' then - sn <= mem_request; - CYC_O <= '1'; - else - cache_busy <= instant_raw; - cache_ack <= not instant_raw; - end if; - end if; - end if; - when invalidate => - sn <= rd_cache; - invalidate_en <= '1'; - invalidate_ack <= '1'; - if invalidate_all = '1' then - sn <= flush; - flush_count_rst <= '1'; - elsif cache_hit_inv = '1' then - tag_ram_we <= '1'; - cache_entry_in.valid <= '0'; - cache_entry_in.tag <= (others => '0'); - sn <= rd_cache; - end if; - - when flush => - flush_count_en <= '1'; - invalidate_en <= '1'; - tag_ram_we <= '1'; - cache_entry_in.valid <= '0'; - cache_entry_in.tag <= (others => '0'); - if flush_count_rdy = '1' then - tag_ram_we <= '0'; - sn <= rd_cache; - end if; - when mem_request => - CYC_O <= '1'; - if SRDY_I = '1' then - sn <= mem_access; - end if; - when mem_access => - fill_count_en <= '1'; - request_count_en <= '1'; - CYC_O <= '1'; - STB_O <= '1'; - if request_count_rdy = '1' then - STB_O <= '0'; - sn <= mem_data; - end if; - when mem_data => - CYC_O <= '1'; - fill_count_en <= '1'; - if fill_count_rdy = '1' then - tag_ram_we <= '1'; - cache_entry_in.valid <= '1'; - sn <= rd_cache; - end if; - when rd_cache => - was_miss <= '1'; - sn <= ready; - - when others => - sn <= ready; - end case; - - end process; - -flush_counter: - process(CLK_I) - begin - if rising_edge(CLK_I) then - if ctrl.inv_at = '1' then - flush_count <= to_integer(cache_index_inv); - elsif flush_count_rst = '1' then - flush_count_rdy <= '0'; - flush_count <= 2**cache_index_width-1; - elsif flush_count_en = '1' then - if flush_count /= 0 then - flush_count <= flush_count - 1; - else - flush_count_rdy <= '1'; - end if; - end if; - end if; - end process; - -request_counter: - process(CLK_I) - begin - if rising_edge(CLK_I) then - if request_count_en = '0' then - request_count_rdy <= '0'; - request_count <= 2**word_index_width-1; - else - if SRDY_I = '1' then - if request_count /= 0 then - request_count <= request_count - 1; - else - request_count_rdy <= '1'; - end if; - end if; - end if; - end if; - end process; - -fill_counter: - process(CLK_I) - begin - if rising_edge(CLK_I) then - if fill_count_en = '0' then - fill_count_rdy <= '0'; - fill_count <= 2**word_index_width-1; - else - if ACK_I = '1' then - if fill_count /= 0 then - fill_count <= fill_count - 1; - else - fill_count_rdy <= '1'; - end if; - end if; - end if; - end if; - end process; - -end behavior; diff --git a/lib/CPUs/MIPS/src/core/icache.vhd b/lib/CPUs/MIPS/src/core/icache.vhd deleted file mode 100644 index 259952a..0000000 --- a/lib/CPUs/MIPS/src/core/icache.vhd +++ /dev/null @@ -1,488 +0,0 @@ --------------------------------------------------------------------------- --- Project: JIPS, a portable 32-bit RISC CPU written in VHDL --- This file: JIPS top file --- --- Copyright (C) 2008 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -library work; -use work.mips_types.all; - -ENTITY icache IS - Generic - ( - cache_size : natural := 2048; -- words - line_size : natural := 8 -- words - ); - Port - ( - RST_I : in STD_LOGIC; - CLK_I : in STD_LOGIC; - ACK_I : in STD_LOGIC; - SRDY_I : in STD_LOGIC; - MRDY_O : out STD_LOGIC; - ADDR_O : out word_t; - DAT_I : in word_t; - STB_O : out STD_LOGIC; - CYC_O : out STD_LOGIC; - ctrl : in cache_ctrl_t; - cpu_en : in STD_LOGIC; - cpu_addr : in word_t; - cpu_dout : out word_t; - cpu_busy : out STD_LOGIC - ); -END icache; - -ARCHITECTURE behavior OF icache IS - -COMPONENT dpram_1w1r2c_ra - GENERIC - ( - addr_width : integer := 3; - data_width : integer := 8 - ); - PORT ( - clk_a : in STD_LOGIC; - clk_b : in STD_LOGIC; - en_a : in STD_LOGIC; - en_b : in STD_LOGIC; - we_a : in STD_LOGIC; - addr_a : in unsigned (addr_width-1 downto 0); - addr_b : in unsigned (addr_width-1 downto 0); - din_a : in unsigned (data_width-1 downto 0); - dout_b : out unsigned (data_width-1 downto 0) - ); -END COMPONENT; - -COMPONENT dpram_2w2r2c_ra is - GENERIC - ( - addr_width : integer := 3; - data_width : integer := 8 - ); - PORT - ( - clk_a : in STD_LOGIC; - clk_b : in STD_LOGIC; - en_a : in STD_LOGIC; - en_b : in STD_LOGIC; - we_a : in STD_LOGIC; - we_b : in STD_LOGIC; - addr_a : in unsigned (addr_width-1 downto 0); - addr_b : in unsigned (addr_width-1 downto 0); - din_a : in unsigned (data_width-1 downto 0); - din_b : in unsigned (data_width-1 downto 0); - dout_a : out unsigned (data_width-1 downto 0); - dout_b : out unsigned (data_width-1 downto 0) - ); -END COMPONENT; - - constant addr_width : natural := 32; - constant word_index_width : natural := lg2(line_size); - constant cache_index_width : natural := lg2(cache_size) - word_index_width; - constant tag_width : natural := addr_width - word_index_width - cache_index_width - 2; - constant tag_parity_width : natural := 3; - constant tag_ram_data_width : natural := 1 + tag_parity_width + tag_width; - constant tag_ram_addr_width : natural := cache_index_width; - - subtype tag_ram_data_t is unsigned (tag_ram_data_width-1 downto 0); - - type icache_entry_t is record - valid : std_logic; - tv_p : unsigned(tag_parity_width-1 downto 0); - tag : unsigned(tag_width-1 downto 0); - end record; - - function to_icache_entry(x : tag_ram_data_t) return icache_entry_t is - variable result : icache_entry_t; - begin - result.valid := x(0); - result.tv_p := x(3 downto 1); - result.tag := x(tag_width+3 downto 4); - - return result; - end to_icache_entry; - - function to_tag_ram_data(x : icache_entry_t) return tag_ram_data_t is - variable result : tag_ram_data_t; - begin - result(0) := x.valid; - result(3 downto 1) := x.tv_p; - result(tag_width+3 downto 4) := x.tag; - - return result; - end to_tag_ram_data; - - type cache_state_t is (init, ready, invalidate, flush, mem_request, mem_access, mem_data, rd_cache, upd_cache); - signal s, sn : cache_state_t; - - signal cache_req : std_logic; - signal cache_ack : std_logic; - signal cache_busy : std_logic; - signal cache_miss : std_logic; - signal tag_match : std_logic; - signal cache_miss_inv : std_logic; - signal tag_match_inv : std_logic; - signal request_addr : unsigned(addr_width-1 downto 0); - signal fill_addr : unsigned(addr_width-1 downto 0); - - signal cache_index_inv : unsigned(cache_index_width-1 downto 0); - signal tag_inv : unsigned(tag_width-1 downto 0); - signal tag_reg_inv : unsigned(tag_width-1 downto 0); - - signal cache_entry_in : icache_entry_t; - signal cache_entry_out : icache_entry_t; - signal cache_entry_out_inv : icache_entry_t; - signal data_ram_addr_rd : unsigned(lg2(cache_size)-1 downto 0); - signal data_ram_data_rd : word_t; - signal data_ram_addr_wr : unsigned(lg2(cache_size)-1 downto 0); - signal data_ram_data_wr : word_t; - signal data_ram_we : std_logic; - - signal tag_ram_addr_rd : unsigned(cache_index_width-1 downto 0); - signal tag_ram_data_rd : tag_ram_data_t; - signal tag_ram_data_rd_inv : tag_ram_data_t; - signal tag_ram_addr_wr : unsigned(cache_index_width-1 downto 0); - signal tag_ram_data_wr : tag_ram_data_t; - signal tag_ram_we : std_logic; - - signal fill_count : natural range 0 to 2**word_index_width-1; - signal fill_count_en : std_logic; - signal fill_count_rdy : std_logic; - signal flush_count : natural range 0 to 2**cache_index_width-1; - signal flush_count_rst : std_logic; - signal flush_count_en : std_logic; - signal flush_count_rdy : std_logic; - signal request_count : natural range 0 to 2**word_index_width-1; - signal request_count_en : std_logic; - signal request_count_rdy : std_logic; - signal ram_read_en : std_logic; - signal was_miss : std_logic; - signal invalidate_all : std_logic; - signal invalidate_ack : std_logic; - signal invalidate_en : std_logic; - signal invalidate_req : std_logic; - - alias cpu_word_index is cpu_addr(word_index_width+1 downto 2); - alias cpu_cache_index is cpu_addr(cache_index_width+word_index_width+1 downto word_index_width+2); - alias cpu_tag is cpu_addr(tag_width+cache_index_width+word_index_width+1 downto cache_index_width+word_index_width+2); - - alias fill_word_index is fill_addr(word_index_width+1 downto 2); - alias fill_cache_index is fill_addr(cache_index_width+word_index_width+1 downto word_index_width+2); - alias fill_tag is fill_addr(tag_width+cache_index_width+word_index_width+1 downto cache_index_width+word_index_width+2); - - alias req_word_index is request_addr(word_index_width+1 downto 2); - alias req_cache_index is request_addr(cache_index_width+word_index_width+1 downto word_index_width+2); - alias req_tag is request_addr(tag_width+cache_index_width+word_index_width+1 downto cache_index_width+word_index_width+2); - -begin - - ram_read_en <= cpu_en or was_miss; - cache_index_inv <= ctrl.inv_addr(cache_index_width+word_index_width+1 downto word_index_width+2); - tag_inv <= ctrl.inv_addr(tag_width+cache_index_width+word_index_width+1 downto cache_index_width+word_index_width+2); - - -fill_address_register: - process(CLK_I) - begin - if rising_edge(CLK_I) then - if fill_count_en = '1' then - if ACK_I = '1' then - fill_word_index <= fill_word_index + 1; - end if; - elsif cache_busy = '0' then - fill_addr <= cpu_addr(addr_width-1 downto 2) & "00"; - end if; - end if; - end process; - -request_address_register: - process(CLK_I) - begin - if rising_edge(CLK_I) then - if request_count_en = '1'then - if SRDY_I = '1' then - req_word_index <= req_word_index + 1; - end if; - elsif cache_busy = '0' then - request_addr <= cpu_addr(addr_width-1 downto 2) & "00"; - end if; - end if; - end process; - -cpu_request_register: - process(CLK_I) - begin - if rising_edge(CLK_I) then - if RST_I = '1' then - cache_req <= '0'; - elsif cpu_en = '1' then - if cache_busy = '0' then - cache_req <= '1'; - end if; - elsif cache_ack = '1' then - cache_req <= '0'; - end if; - end if; - end process; - -cache_invalidate_request: - process(CLK_I) - begin - if rising_edge(CLK_I) then - if RST_I = '1' or ctrl.inv_all = '1' or ctrl.inv_at = '1' then - invalidate_req <= '1'; - invalidate_all <= ctrl.inv_all or RST_I; - tag_reg_inv <= tag_inv; - elsif invalidate_ack = '1' then - invalidate_req <= '0'; - invalidate_all <= '0'; - end if; - end if; - end process; - -inst_tag_ram : dpram_2w2r2c_ra - GENERIC MAP - ( - addr_width => tag_ram_addr_width, - data_width => tag_ram_data_width - ) - PORT MAP - ( - clk_a => CLK_I, - clk_b => CLK_I, - en_a => '1', - en_b => ram_read_en, - we_a => tag_ram_we, - we_b => '0', - addr_a => tag_ram_addr_wr, - addr_b => tag_ram_addr_rd, - din_a => tag_ram_data_wr, - din_b => tag_ram_data_wr, - dout_a => tag_ram_data_rd_inv, - dout_b => tag_ram_data_rd - ); - -inst_data_ram : dpram_1w1r2c_ra - GENERIC MAP - ( - addr_width => lg2(cache_size), - data_width => word_t'length - ) - PORT MAP - ( - clk_a => CLK_I, - clk_b => CLK_I, - en_a => '1', - en_b => ram_read_en, - we_a => data_ram_we, - addr_a => data_ram_addr_wr, - addr_b => data_ram_addr_rd, - din_a => data_ram_data_wr, - dout_b => data_ram_data_rd - ); - -cache_state_next: - process(CLK_I) - begin - if rising_edge(CLK_I) then - if RST_I = '1' then - s <= init; - else - s <= sn; - end if; - end if; - end process; - - MRDY_O <= fill_count_en; - ADDR_O <= fill_tag & fill_cache_index & req_word_index & "00"; - - cpu_busy <= cache_busy; - cpu_dout <= data_ram_data_rd; - - cache_entry_out <= to_icache_entry(tag_ram_data_rd); - tag_match <= '1' when fill_tag = cache_entry_out.tag else '0'; - cache_miss <= not (tag_match and cache_entry_out.valid); - - cache_entry_out_inv <= to_icache_entry(tag_ram_data_rd_inv); - tag_match_inv <= '1' when tag_reg_inv = cache_entry_out_inv.tag else '0'; - cache_miss_inv <= not (tag_match_inv and cache_entry_out_inv.valid); - - tag_ram_data_wr <= to_tag_ram_data(cache_entry_in); - tag_ram_addr_wr <= to_unsigned(flush_count, cache_index_width) when invalidate_en = '1' else fill_cache_index; - tag_ram_addr_rd <= cpu_cache_index when was_miss = '0' else fill_cache_index; - data_ram_addr_rd <= (cpu_cache_index & cpu_word_index) when was_miss = '0' else (fill_cache_index & fill_word_index); - data_ram_addr_wr <= fill_cache_index & fill_word_index; - data_ram_data_wr <= DAT_I; - data_ram_we <= fill_count_en and ACK_I; - -cache_state: - process(s, cache_req, cache_miss, cache_miss_inv, flush_count_rdy, fill_count_rdy, request_count_rdy, fill_tag, SRDY_I, invalidate_req, invalidate_all) - begin - cache_busy <= cache_req; - cache_ack <= '0'; - tag_ram_we <= '0'; - flush_count_en <= '0'; - flush_count_rst <= '0'; - invalidate_en <= '0'; - request_count_en <= '0'; - fill_count_en <= '0'; - CYC_O <= '0'; - STB_O <= '0'; - was_miss <= '0'; - invalidate_ack <= '0'; - - cache_entry_in.tv_p <= (others => '0'); - cache_entry_in.tag <= fill_tag; - cache_entry_in.valid <= '0'; - sn <= s; - - case s is - when init => - sn <= ready; - when ready => - if invalidate_req = '1' then - sn <= invalidate; - invalidate_en <= '1'; - elsif cache_req = '1' then - if cache_miss = '1' then - sn <= mem_request; - CYC_O <= '1'; - else - cache_busy <= '0'; - cache_ack <= '1'; - end if; - end if; - when invalidate => - sn <= rd_cache; - invalidate_en <= '1'; - invalidate_ack <= '1'; - if invalidate_all = '1' then - sn <= flush; - flush_count_rst <= '1'; - elsif cache_miss_inv = '0' then - tag_ram_we <= '1'; - cache_entry_in.valid <= '0'; - cache_entry_in.tag <= (others => '0'); - sn <= rd_cache; - end if; - - when flush => - flush_count_en <= '1'; - invalidate_en <= '1'; - tag_ram_we <= '1'; - cache_entry_in.valid <= '0'; - cache_entry_in.tag <= (others => '0'); - if flush_count_rdy = '1' then - tag_ram_we <= '0'; - sn <= rd_cache; - end if; - when mem_request => - CYC_O <= '1'; - if SRDY_I = '1' then - sn <= mem_access; - end if; - when mem_access => - request_count_en <= '1'; - fill_count_en <= '1'; - CYC_O <= '1'; - STB_O <= '1'; - if request_count_rdy = '1' then - STB_O <= '0'; - sn <= mem_data; - end if; - when mem_data => - CYC_O <= '1'; - fill_count_en <= '1'; - if fill_count_rdy = '1' then - tag_ram_we <= '1'; - cache_entry_in.valid <= '1'; - sn <= rd_cache; - end if; - when rd_cache => - was_miss <= '1'; - sn <= ready; - when others => - sn <= ready; - end case; - - end process; - -flush_counter: - process(CLK_I) - begin - if rising_edge(CLK_I) then - if ctrl.inv_at = '1' then - flush_count <= to_integer(cache_index_inv); - elsif flush_count_rst = '1' then - flush_count_rdy <= '0'; - flush_count <= 2**cache_index_width-1; - elsif flush_count_en = '1' then - if flush_count /= 0 then - flush_count <= flush_count - 1; - else - flush_count_rdy <= '1'; - end if; - end if; - end if; - end process; - -request_counter: - process(CLK_I) - begin - if rising_edge(CLK_I) then - if request_count_en = '0' then - request_count_rdy <= '0'; - request_count <= 2**word_index_width-1; - else - if SRDY_I = '1' then - if request_count /= 0 then - request_count <= request_count - 1; - else - request_count_rdy <= '1'; - end if; - end if; - end if; - end if; - end process; - -fill_counter: - process(CLK_I) - begin - if rising_edge(CLK_I) then - if fill_count_en = '0' then - fill_count_rdy <= '0'; - fill_count <= 2**word_index_width-1; - else - if ACK_I = '1' then - if fill_count /= 0 then - fill_count <= fill_count - 1; - else - fill_count_rdy <= '1'; - end if; - end if; - end if; - end if; - end process; - -end behavior; diff --git a/lib/CPUs/MIPS/src/core/mips_alu.vhd b/lib/CPUs/MIPS/src/core/mips_alu.vhd deleted file mode 100644 index a64b5a4..0000000 --- a/lib/CPUs/MIPS/src/core/mips_alu.vhd +++ /dev/null @@ -1,184 +0,0 @@ --------------------------------------------------------------------------- --- Project: JIPS, a portable 32-bit RISC CPU written in VHDL --- This file: The arithmetic logic unit --- --- Copyright (C) 2008 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.mips_types.all; - -entity alu is - Generic - ( - data_width : integer := 8 - ); - Port - ( - op1_in : in unsigned (data_width-1 downto 0); - op2_in : in unsigned (data_width-1 downto 0); - op2_shifted : in unsigned (data_width-1 downto 0); - ctrl : in alu_ctrl_t; - result : out unsigned (data_width-1 downto 0); - flags : out alu_flags_t - ); -end alu; - -architecture Behavioral of alu is - - signal sum_res : unsigned (data_width-1 downto 0); - signal and_res : unsigned (data_width-1 downto 0); - signal xor_res : unsigned (data_width-1 downto 0); - signal nor_res : unsigned (data_width-1 downto 0); - signal or_res : unsigned (data_width-1 downto 0); - signal eq, sa, sb, sr, c, z : STD_LOGIC; - signal lts, ltu : STD_LOGIC; - --------------------------------------------------------------------------- -begin - - eq <= '1' when op1_in = op2_in else '0' after 3 ns; - sa <= op1_in(op1_in'left); - sb <= op2_in(op2_in'left); - sr <= sum_res(sum_res'left); - z <= '1' when op1_in = (data_width-1 downto 0 => '0') else '0' after 2 ns; - - flags.uvf <= (not ctrl.add) and ((sa and (not sb) and (not sr)) or ((not sa) and sb and sr)); - flags.ovf <= ctrl.add and ((sa and sb and (not sr)) or ((not sa) and (not sb) and sr)); --- lts <= (not eq) and (((not c) and sa and sb) or (((not sr) and sa) or (sa and (not sb)) or (sr and (not sb)))); - lts <= not eq and ((not c and sa) or (not sb and sa) or (not sb and sr)); - - ltu <= (not eq) and (not c); - flags.lts <= lts; - flags.ltu <= ltu; - flags.c <= c; - --------------------------------------------------------------------------- -proc_op_and: - process(op1_in, op2_in) - variable x1, x2 : unsigned (data_width-1 downto 0); - begin - x1 := op1_in; - x2 := op2_in; - - and_res <= (x1 and x2) after 1 ns; - - end process; - --------------------------------------------------------------------------- -proc_proc_xor: - process(op1_in, op2_in) - variable x1, x2 : unsigned (data_width-1 downto 0); - begin - x1 := op1_in; - x2 := op2_in; - - xor_res <= (x1 xor x2) after 2 ns; - - end process; - --------------------------------------------------------------------------- -proc_proc_nor: - process(op1_in, op2_in) - variable x1, x2 : unsigned (data_width-1 downto 0); - begin - x1 := op1_in; - x2 := op2_in; - - nor_res <= (x1 nor x2) after 1 ns; - - end process; - --------------------------------------------------------------------------- -proc_proc_or: - process(op1_in, op2_in) - variable x1, x2 : unsigned (data_width-1 downto 0); - begin - x1 := op1_in; - x2 := op2_in; - - or_res <= (x1 or x2) after 1 ns; - - end process; - --------------------------------------------------------------------------- -proc_alu_out: - process(ctrl, sum_res, and_res, xor_res, nor_res, or_res, op2_shifted, lts, ltu) - begin - - result <= sum_res; - - case ctrl.outsel is - - when alu_adder => - result <= sum_res; - - when alu_and => - result <= and_res; - - when alu_xor => - result <= xor_res; - - when alu_nor => - result <= nor_res; - - when alu_or => - result <= or_res; - - when alu_shift2 => - result <= op2_shifted; - - when alu_ltu => - result <= (data_width-1 downto 1 => '0') & ltu; - - when alu_lts => - result <= (data_width-1 downto 1 => '0') & lts; - - when others => null; - - end case; - - end process; - --------------------------------------------------------------------------- -alu_addsub: - process(op1_in, op2_in, ctrl) - variable sum : unsigned(data_width+1 downto 0); - variable op1, op2 : unsigned(data_width+1 downto 0); - begin - - op1 := '0' & op1_in & not ctrl.add; - if (ctrl.add = '1') then - op2 := '0' & op2_in & '0'; - else - op2 := '0' & not op2_in & '1'; - end if; - sum := op1 + op2; - - -- Form sum + carry - sum_res <= unsigned(sum(data_width downto 1)) after 4 ns; - c <= sum(sum'left) after 4 ns; - - end process; - --------------------------------------------------------------------------- -end Behavioral; diff --git a/lib/CPUs/MIPS/src/core/mips_bcu.vhd b/lib/CPUs/MIPS/src/core/mips_bcu.vhd deleted file mode 100644 index 51b5ed7..0000000 --- a/lib/CPUs/MIPS/src/core/mips_bcu.vhd +++ /dev/null @@ -1,52 +0,0 @@ --------------------------------------------------------------------------- --- Project: JIPS, a portable 32-bit RISC CPU written in VHDL --- This file: The arithmetic logic unit --- --- Copyright (C) 2008 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.mips_types.all; - -entity bcu is - Generic - ( - data_width : integer := 8 - ); - Port - ( - op1_in : in unsigned (data_width-1 downto 0); - op2_in : in unsigned (data_width-1 downto 0); - flags : out bcu_flags_t - ); -end bcu; - -architecture Behavioral of bcu is - --------------------------------------------------------------------------- -begin - - flags.eq <= '1' when op1_in = op2_in else '0' after 3 ns; - flags.ltz <= op1_in(op1_in'left) after 1 ns; - --------------------------------------------------------------------------- -end Behavioral; diff --git a/lib/CPUs/MIPS/src/core/mips_bui.vhd b/lib/CPUs/MIPS/src/core/mips_bui.vhd deleted file mode 100644 index e2aae9f..0000000 --- a/lib/CPUs/MIPS/src/core/mips_bui.vhd +++ /dev/null @@ -1,552 +0,0 @@ --------------------------------------------------------------------------- --- Project: JIPS, a portable 32-bit RISC CPU written in VHDL --- This file: JIPS top file --- --- Copyright (C) 2008 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -library work; -use work.mips_types.all; - -entity biu is - Generic - ( - icache_size : natural := 2048; -- words - icache_line : natural := 8; -- words - dcache_size : natural := 2048; -- words - dcache_line : natural := 8 -- words - ); - Port - ( - RST_I : in STD_LOGIC; - CLK_I : in STD_LOGIC; - ACK_I : in STD_LOGIC; - SRDY_I : in STD_LOGIC; - ADDR_O : out unsigned(31 downto 0); - DAT_I : in unsigned(31 downto 0); - DAT_O : out unsigned(31 downto 0); - WE_O : out STD_LOGIC; - SEL_O : out unsigned(3 downto 0); - CYC_O : out STD_LOGIC; - STB_O : out STD_LOGIC; - MRDY_O : out STD_LOGIC; - cop0_ctrl_in : in cop0_ctrl_out_t; - cpu_clk : in STD_LOGIC; - cpu_imem_err : out STD_LOGIC; - cpu_imem_rdy : out STD_LOGIC; - cpu_imem_en : in STD_LOGIC; - cpu_imem_addr : in word_t; - cpu_imem_din : out word_t; - cpu_dmem_err : out STD_LOGIC; - cpu_dmem_rdy : out STD_LOGIC; - cpu_dmem_en : in STD_LOGIC; - cpu_dmem_we : in STD_LOGIC; - cpu_dmem_be : in unsigned(3 downto 0); - cpu_dmem_dout : in word_t; - cpu_dmem_din : out word_t; - cpu_dmem_addr : in word_t - ); -end biu; - -architecture behavior of biu is - - COMPONENT icache - GENERIC - ( - cache_size : natural; -- words - line_size : natural -- words - ); - PORT - ( - RST_I : in STD_LOGIC; - CLK_I : in STD_LOGIC; - ACK_I : in STD_LOGIC; - SRDY_I : in STD_LOGIC; - MRDY_O : out STD_LOGIC; - ADDR_O : out word_t; - DAT_I : in word_t; - STB_O : out STD_LOGIC; - CYC_O : out STD_LOGIC; - ctrl : in cache_ctrl_t; - cpu_en : in STD_LOGIC; - cpu_addr : in word_t; - cpu_dout : out word_t; - cpu_busy : out STD_LOGIC - ); - END COMPONENT; - - COMPONENT dcache - GENERIC - ( - cache_size : natural; -- words - line_size : natural -- words - ); - PORT - ( - RST_I : in STD_LOGIC; - CLK_I : in STD_LOGIC; - ACK_I : in STD_LOGIC; - SRDY_I : in STD_LOGIC; - MRDY_O : out STD_LOGIC; - ADDR_O : out word_t; - DAT_I : in word_t; - STB_O : out STD_LOGIC; - CYC_O : out STD_LOGIC; - ctrl : in cache_ctrl_t; - cpu_en : in STD_LOGIC; - cpu_we : in STD_LOGIC; - cpu_be : in unsigned(3 downto 0); - cpu_addr : in word_t; - cpu_din : in word_t; - cpu_dout : out word_t; - cpu_busy : out STD_LOGIC - ); - END COMPONENT; - - type bus_state_t is (init, ready, icache_bus_access, dcache_bus_access, write_bus, read_bus, read_finish); - - signal s, sn : bus_state_t; - signal bus_idle : std_logic; - signal busy : std_logic; - signal dmem_be : unsigned(3 downto 0); - signal dcache_dout : word_t; - signal dcache_mem_gnt : std_logic; - signal icache_mem_gnt : std_logic; - signal dmem_mem_wr_gnt : std_logic; - signal dmem_mem_rd_gnt : std_logic; - signal dcache_busy : std_logic; - signal icache_busy : std_logic; - signal CYC_O_icache : std_logic; - signal CYC_O_dcache : std_logic; - signal CYC_O_dmem_rd : std_logic; - signal CYC_O_dmem_wr : std_logic; - signal SRDY_I_icache : std_logic; - signal SRDY_I_dcache : std_logic; - signal MRDY_O_icache : std_logic; - signal MRDY_O_dcache : std_logic; - signal ADDR_O_icache : word_t; - signal ADDR_O_dcache : word_t; - signal ADDR_O_dmem_rd : word_t; - signal ADDR_O_dmem_wr : word_t; - signal STB_O_icache : std_logic; - signal STB_O_dcache : std_logic; - signal STB_O_dmem_rd : std_logic; - signal STB_O_dmem_wr : std_logic; - signal DAT_I_dmem_rd : word_t; - signal DAT_O_dmem_wr : word_t; - signal SEL_O_dmem_wr : unsigned(3 downto 0); - signal SEL_O_dmem_rd : unsigned(3 downto 0); - signal dcached : std_logic; - signal dcache_en2 : std_logic; - signal dcache_en : std_logic; - signal uncached_access : std_logic; - signal ACK : std_logic; - signal DAT : unsigned(31 downto 0); - - type timeout_cnt_t is range 0 to 1E5-1; - signal bus_timeout_cnt : timeout_cnt_t; - signal bus_timeout : std_logic; - - signal bout_fifo_din : unsigned(68 downto 0); - signal bout_fifo_dout : unsigned(68 downto 0); - signal bout_fifo_re : std_logic; - signal bout_fifo_we : std_logic; - signal bout_fifo_full : std_logic; - signal bout_fifo_empty : std_logic; - signal bout_rdy : std_logic; - - signal bin_fifo_din : unsigned(31 downto 0); - signal bin_fifo_dout : unsigned(31 downto 0); - signal bin_fifo_re : std_logic; - signal bin_fifo_we : std_logic; - signal bin_fifo_full : std_logic; - signal bin_fifo_empty : std_logic; - - alias bout_fifo_addr_in is bout_fifo_din(31 downto 0); - alias bout_fifo_data_in is bout_fifo_din(63 downto 32); - alias bout_fifo_sel_in is bout_fifo_din(67 downto 64); - alias bout_fifo_we_in is bout_fifo_din(68); - alias bout_fifo_addr_out is bout_fifo_dout(31 downto 0); - alias bout_fifo_data_out is bout_fifo_dout(63 downto 32); - alias bout_fifo_sel_out is bout_fifo_dout(67 downto 64); - alias bout_fifo_we_out is bout_fifo_dout(68); - - signal write_fifo_din : unsigned(67 downto 0); - signal write_fifo_dout : unsigned(67 downto 0); - signal write_fifo_re : std_logic; - signal write_fifo_we : std_logic; - signal write_fifo_full : std_logic; - signal write_fifo_empty : std_logic; - - alias write_fifo_addr_in is write_fifo_din(31 downto 0); - alias write_fifo_data_in is write_fifo_din(63 downto 32); - alias write_fifo_sel_in is write_fifo_din(67 downto 64); - alias write_fifo_addr_out is write_fifo_dout(31 downto 0); - alias write_fifo_data_out is write_fifo_dout(63 downto 32); - alias write_fifo_sel_out is write_fifo_dout(67 downto 64); - - signal read_cycle : std_logic; - -begin - -read_cyc_register: - process(cpu_clk) - begin - if rising_edge(cpu_clk) then - if RST_I = '1' then - read_cycle <= '0'; - else - read_cycle <= (dmem_mem_rd_gnt and CYC_O_dmem_rd) - or (dcache_mem_gnt and CYC_O_dcache) - or (icache_mem_gnt and CYC_O_icache); - end if; - end if; - end process; - - MRDY_O <= not bin_fifo_full; - CYC_O <= not bout_fifo_empty or read_cycle; - STB_O <= not bout_fifo_empty; - ADDR_O <= bout_fifo_addr_out; - DAT_O <= bout_fifo_data_out; - SEL_O <= bout_fifo_sel_out; - WE_O <= bout_fifo_we_out; - - cpu_imem_rdy <= not icache_busy after 4.5 ns; - busy <= CYC_O_dmem_rd or dcache_busy or (write_fifo_full); - cpu_dmem_rdy <= not busy after 4.5 ns; - -inst_icache : icache - GENERIC MAP - ( - cache_size => icache_size, -- words - line_size => icache_line -- words - ) - PORT MAP - ( - CLK_I => cpu_clk, - RST_I => RST_I, - STB_O => STB_O_icache, - CYC_O => CYC_O_icache, - ADDR_O => ADDR_O_icache, - MRDY_O => MRDY_O_icache, - DAT_I => DAT, - ACK_I => ACK, - SRDY_I => SRDY_I_icache, - ctrl => cop0_ctrl_in.icache, - cpu_en => cpu_imem_en, - cpu_addr => cpu_imem_addr, - cpu_dout => cpu_imem_din, - cpu_busy => icache_busy - ); - - SRDY_I_icache <= bout_rdy and icache_mem_gnt; - -inst_dcache : dcache - GENERIC MAP - ( - cache_size => dcache_size, -- words - line_size => dcache_line -- words - ) - PORT MAP - ( - CLK_I => cpu_clk, - RST_I => RST_I, - CYC_O => CYC_O_dcache, - STB_O => STB_O_dcache, - ADDR_O => ADDR_O_dcache, - MRDY_O => MRDY_O_dcache, - DAT_I => DAT, - ACK_I => ACK, - SRDY_I => SRDY_I_dcache, - ctrl => cop0_ctrl_in.dcache, - cpu_en => dcache_en, - cpu_we => cpu_dmem_we, - cpu_be => cpu_dmem_be, - cpu_addr => cpu_dmem_addr, - cpu_din => cpu_dmem_dout, - cpu_dout => dcache_dout, - cpu_busy => dcache_busy - ); - - SRDY_I_dcache <= bout_rdy and dcache_mem_gnt; - - dcached <= '1' when cpu_dmem_addr(31 downto 29) /= "101" else '0'; - cpu_dmem_din <= dcache_dout when uncached_access = '0' else DAT_I_dmem_rd; - dcache_en <= dcached and cpu_dmem_en and dcache_en2; -- or write_fifo_full); - --- Instantiate synchronous FIFO -inst_bin_fifo: entity work.fifo_async - GENERIC MAP - ( - addr_width => 4, - data_width => 32, - do_last_read_update => true - ) - PORT MAP - ( - rst => RST_I, - clk_w => CLK_I, - clk_r => cpu_clk, - we => bin_fifo_we, - re => bin_fifo_re, - fifo_full => bin_fifo_full, - fifo_empty => bin_fifo_empty, - fifo_afull => open, - fifo_aempty => open, - data_w => bin_fifo_din, - data_r => bin_fifo_dout - ); - - bin_fifo_din <= DAT_I; - DAT <= bin_fifo_dout; - ACK <= not bin_fifo_empty; - bin_fifo_we <= ACK_I; - bin_fifo_re <= dmem_mem_rd_gnt or MRDY_O_icache or MRDY_O_dcache; - --- Instantiate synchronous FIFO -inst_bout_fifo: entity work.fifo_async - GENERIC MAP - ( - addr_width => 4, - data_width => 69, - do_last_read_update => false - ) - PORT MAP - ( - rst => RST_I, - clk_w => cpu_clk, - clk_r => CLK_I, - we => bout_fifo_we, - re => bout_fifo_re, - fifo_full => bout_fifo_full, - fifo_empty => bout_fifo_empty, - fifo_afull => open, - fifo_aempty => open, - data_w => bout_fifo_din, - data_r => bout_fifo_dout - ); - bout_rdy <= not bout_fifo_full; - bout_fifo_re <= SRDY_I and not bin_fifo_full; - - bout_fifo_we <= STB_O_dmem_wr or STB_O_dmem_rd or STB_O_dcache or STB_O_icache; - - bout_fifo_data_in <= DAT_O_dmem_wr when dmem_mem_wr_gnt = '1' else (others => '-'); - - bout_fifo_addr_in <= ADDR_O_dmem_wr when dmem_mem_wr_gnt = '1' else - ADDR_O_dmem_rd when dmem_mem_rd_gnt = '1' else - ADDR_O_dcache when dcache_mem_gnt = '1' else - ADDR_O_icache when icache_mem_gnt = '1' else (others => '-'); - - bout_fifo_sel_in <= SEL_O_dmem_wr when dmem_mem_wr_gnt = '1' else - SEL_O_dmem_rd when dmem_mem_rd_gnt = '1' else (others => '1'); - - bout_fifo_we_in <= '1' when dmem_mem_wr_gnt = '1' else '0'; - --- Instantiate synchronous FIFO -inst_write_fifo: entity work.fifo_sync - GENERIC MAP - ( - addr_width => 4, - data_width => 68, - do_last_read_update => true - ) - PORT MAP - ( - rst => RST_I, - clk => cpu_clk, - we => write_fifo_we, - re => write_fifo_re, - fifo_full => write_fifo_full, - fifo_empty => write_fifo_empty, - fifo_afull => open, - fifo_aempty => open, - data_w => write_fifo_din, - data_r => write_fifo_dout - ); - - CYC_O_dmem_wr <= not write_fifo_empty; - DAT_O_dmem_wr <= write_fifo_data_out; - ADDR_O_dmem_wr <= write_fifo_addr_out; - SEL_O_dmem_wr <= write_fifo_sel_out; - - write_fifo_data_in <= cpu_dmem_dout; - write_fifo_addr_in <= cpu_dmem_addr; - write_fifo_sel_in <= cpu_dmem_be; - write_fifo_re <= STB_O_dmem_wr; - write_fifo_we <= cpu_dmem_en and not busy and cpu_dmem_we; - -dmem_rd_flags: - process(cpu_clk) - begin - if rising_edge(cpu_clk) then - uncached_access <= '0'; - if RST_I = '1' then - CYC_O_dmem_rd <= '0'; - dcache_en2 <= '1'; - else - if ACK = '1' and dmem_mem_rd_gnt = '1' then - uncached_access <= '1'; - CYC_O_dmem_rd <= '0'; - dcache_en2 <= '1'; - end if; - if cpu_dmem_en = '1' and busy = '0' and cpu_dmem_we = '0' then - if dcached = '0' then - CYC_O_dmem_rd <= '1'; - dcache_en2 <= '0'; - end if; - end if; - end if; - end if; - end process; - -dmem_rd_data: - process(cpu_clk) - begin - if rising_edge(cpu_clk) then - if RST_I = '1' then - DAT_I_dmem_rd <= (others => '0'); - elsif ACK = '1' and CYC_O_dmem_rd = '1' then - DAT_I_dmem_rd <= DAT; - end if; - end if; - end process; - -dmem_rd_regs: - process(cpu_clk) - begin - if rising_edge(cpu_clk) then - if cpu_dmem_en = '1' and busy = '0' then - ADDR_O_dmem_rd <= cpu_dmem_addr; - SEL_O_dmem_rd <= cpu_dmem_be; - end if; - end if; - end process; - -bus_state_next: - process(cpu_clk) - begin - if rising_edge(cpu_clk) then - if RST_I = '1' then - s <= init; - else - s <= sn; - end if; - end if; - end process; - -bus_state: - process(s, CYC_O_icache, CYC_O_dcache, CYC_O_dmem_wr, CYC_O_dmem_rd, bout_rdy, ACK) - begin - - icache_mem_gnt <= '0'; - dcache_mem_gnt <= '0'; - dmem_mem_rd_gnt <= '0'; - dmem_mem_wr_gnt <= '0'; - STB_O_dmem_rd <= '0'; - STB_O_dmem_wr <= '0'; - bus_idle <= '0'; - sn <= s; - case s is - when init => - sn <= ready; - when ready => - bus_idle <= '1'; - if CYC_O_dmem_wr = '1' then - sn <= write_bus; - elsif CYC_O_dmem_rd = '1' then - sn <= read_bus; - elsif CYC_O_icache = '1' then - sn <= icache_bus_access; - elsif CYC_O_dcache = '1' then - sn <= dcache_bus_access; - end if; - when icache_bus_access => - icache_mem_gnt <= '1'; - if CYC_O_icache = '0' then - sn <= ready; - end if; - when dcache_bus_access => - dcache_mem_gnt <= '1'; - if CYC_O_dcache = '0' then - sn <= ready; - end if; - when write_bus => - dmem_mem_wr_gnt <= '1'; - if CYC_O_dmem_wr = '1' then - if bout_rdy = '1' then - STB_O_dmem_wr <= '1'; - end if; - else - sn <= ready; - end if; - when read_bus => - dmem_mem_rd_gnt <= '1'; - if bout_rdy = '1' then - STB_O_dmem_rd <= '1'; - sn <= read_finish; - end if; - when read_finish => - dmem_mem_rd_gnt <= '1'; - if ACK = '1' then - sn <= ready; - end if; - when others => - sn <= ready; - end case; - - end process; - -bus_timeout_counter: - process(cpu_clk) - begin - if rising_edge(cpu_clk) then - if bus_idle = '0' then - if bus_timeout_cnt /= 0 then - bus_timeout_cnt <= bus_timeout_cnt - 1; - else - bus_timeout <= '1'; - end if; - else - bus_timeout_cnt <= timeout_cnt_t'high; - bus_timeout <= '0'; - end if; - end if; - end process; - -bus_err: - process(cpu_clk) - begin - if rising_edge(cpu_clk) then - if RST_I = '1' then - cpu_imem_err <= '0'; - cpu_dmem_err <= '0'; - elsif bus_timeout = '1' then - cpu_imem_err <= icache_mem_gnt; - cpu_dmem_err <= dcache_mem_gnt or dmem_mem_wr_gnt or dmem_mem_rd_gnt; - end if; - end if; - end process; - -------------------------------------------------------------------- - -end behavior; diff --git a/lib/CPUs/MIPS/src/core/mips_cop.vhd b/lib/CPUs/MIPS/src/core/mips_cop.vhd deleted file mode 100644 index af898eb..0000000 --- a/lib/CPUs/MIPS/src/core/mips_cop.vhd +++ /dev/null @@ -1,546 +0,0 @@ --------------------------------------------------------------------------- --- Project: JIPS, a portable 32-bit RISC CPU written in VHDL --- This file: The arithmetic logic unit --- --- Copyright (C) 2008 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.mips_types.all; -use work.mips_instr.all; - -entity cop is - Generic - ( - icache_size : natural := 2048; -- words - icache_line : natural := 8; -- words - dcache_size : natural := 2048; -- words - dcache_line : natural := 8 -- words - ); - Port - ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - eb : in STD_LOGIC; - int : in unsigned(5 downto 0); - nmi : in STD_LOGIC; - ir_en : in STD_LOGIC; - ir : in word_t; - ctrl_in : in cop0_ctrl_in_t; - ctrl_out : out cop0_ctrl_out_t; - din : in word_t; - dout : out word_t - ); -end cop; - -architecture Behavioral of cop is - - signal epc : word_t; - signal cause : word_t; - signal status : word_t; - signal imem_addr : word_t; - signal imem_addr_we : STD_LOGIC; - signal BadVAddr : word_t; - signal exc_code : unsigned(4 downto 0); - signal test_reg : word_t; - signal test_reg_we : STD_LOGIC; - signal stat_reg_we : STD_LOGIC; - signal eflags_reg_we : STD_LOGIC; - signal epc_reg_we : STD_LOGIC; - signal code_reg_we : STD_LOGIC; - signal ip_reg_we : STD_LOGIC; - signal bd : STD_LOGIC; - signal sw_int : unsigned(1 downto 0); - signal ip : unsigned(7 downto 0); - signal im : unsigned(7 downto 0); - signal status_save : STD_LOGIC; - signal status_rest : STD_LOGIC; - signal eflags : exc_flags_t; - signal EB_reg : STD_LOGIC; - signal icache_info : unsigned(7 downto 0); - signal dcache_info : unsigned(7 downto 0); - signal reg_rptr : reg_ptr_t; - signal reg_wptr : reg_ptr_t; - signal inject_exc : STD_LOGIC; - signal latch_vect_en : STD_LOGIC; - signal int_nmi : STD_LOGIC; - signal nmi_asserted : std_logic; - - type cop_pipe_t is record - opc : opcode_t; - RFE : std_logic; - CO : std_logic; - reg_ptr : reg_ptr_t; - rs : reg_ptr_t; - rd : reg_ptr_t; - rt : reg_ptr_t; - func : func_t; - we : std_logic; - re : std_logic; - cs : std_logic; - end record; - - signal cop_pipe_ID : cop_pipe_t; - signal cop_pipe_EX : cop_pipe_t; - - function eval_int(ip : unsigned) return STD_LOGIC is - variable result : STD_LOGIC; - begin - result := '0'; - for i in ip'range loop - result := result or ip(i); - end loop; - - return result; - end eval_int; - - type exc_state_t is (exc_idle, exc_pipe_flush, exc_commit, exc_inject, exc_enter, exc_leave, exc_left); - signal exc_state, exc_staten : exc_state_t; - --------------------------------------------------------------------------- -begin - - icache_info <= "00" & to_unsigned(lg2(icache_line), 3) & to_unsigned(lg2(icache_size)-8, 3); - dcache_info <= "00" & to_unsigned(lg2(dcache_line), 3) & to_unsigned(lg2(dcache_size)-8, 3); - cop_pipe_ID.cs <= ir_en; - cop_pipe_ID.opc <= extract_opc(ir); - cop_pipe_ID.rs <= extract_rs(ir); - cop_pipe_ID.rd <= extract_rd(ir); - cop_pipe_ID.rt <= extract_rt(ir); - cop_pipe_ID.func <= extract_func(ir); - cop_pipe_ID.CO <= ir(25); - cop_pipe_ID.re <= cop_pipe_ID.cs when (cop_pipe_ID.opc = "111000" or (cop_pipe_ID.opc = "010000" and cop_pipe_ID.rs = "00000")) else '0'; - cop_pipe_ID.we <= cop_pipe_ID.cs when (cop_pipe_ID.opc = "110000" or (cop_pipe_ID.opc = "010000" and cop_pipe_ID.rs = "00100")) else '0'; - cop_pipe_ID.RFE <= cop_pipe_ID.cs when (cop_pipe_ID.CO = '1' and cop_pipe_ID.func = "010000") else '0'; - ctrl_out.EB <= EB_reg xor (status(25) and status(1)); - ctrl_out.user_mode <= status(1); - ctrl_out.exc_inject <= inject_exc or rst; - cop_pipe_ID.reg_ptr <= cop_pipe_ID.rd when cop_pipe_ID.opc = "010000" else cop_pipe_ID.rt; - - im <= status(15 downto 8); - cause <= bd & (30 downto 16 => '0') & ip & '0' & exc_code & "00"; - - eflags.Ov <= ctrl_in.events.alu_ovf or ctrl_in.events.alu_uvf; - eflags.DAdEL <= ctrl_in.events.data_load_err; - eflags.DAdES <= ctrl_in.events.data_store_err; - eflags.IAdEL <= ctrl_in.events.inst_load_err; - eflags.IAdEK <= ctrl_in.events.inst_priv_addr and status(1); - eflags.Sys <= ctrl_in.events.syscall; - eflags.Bp <= ctrl_in.events.break; - eflags.RI <= ctrl_in.events.illegal; - eflags.Int <= ctrl_in.events.int; - --- NMI/RST transition detector -proc_nmi_transition: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - int_nmi <= '0'; - nmi_asserted <= '0'; - elsif latch_vect_en = '1' then - int_nmi <= '0'; - elsif nmi_asserted = '1' then - if nmi = '0' then - nmi_asserted <= '0'; - int_nmi <= '1'; - end if; - elsif nmi = '1' then - nmi_asserted <= '1'; - end if; - end if; - end process; - - --- Main exception FSM -proc_exc_state: - process(exc_state, ctrl_in, cop_pipe_ID) - begin - - ctrl_out.exc_commit <= '0'; - ctrl_out.exc_pending <= '0'; - ctrl_out.exc_exit <= '0'; - epc_reg_we <= '0'; - code_reg_we <= '0'; - status_save <= '0'; - status_rest <= '0'; - inject_exc <= '0'; - imem_addr_we <= '0'; - latch_vect_en <= '0'; - - exc_staten <= exc_state; - - case exc_state is - - when exc_idle => - if cop_pipe_ID.RFE = '1' then - exc_staten <= exc_leave; - ctrl_out.exc_exit <= '1'; - ctrl_out.exc_commit <= '1'; - elsif ctrl_in.exc_req = '1' then - exc_staten <= exc_pipe_flush; - imem_addr_we <= '1'; - end if; - - when exc_pipe_flush => - ctrl_out.exc_pending <= '1'; - ctrl_out.exc_commit <= '1'; - if ctrl_in.exc_ack = '1' then - exc_staten <= exc_commit; - end if; - - when exc_commit => - latch_vect_en <= '1'; - ctrl_out.exc_pending <= '1'; - ctrl_out.exc_commit <= '1'; - if ctrl_in.sdu.ID_stall = '0' then - exc_staten <= exc_inject; - end if; - - when exc_inject => - ctrl_out.exc_pending <= '1'; - ctrl_out.exc_commit <= '1'; - code_reg_we <= '1'; - status_save <= '1'; - epc_reg_we <= '1'; - inject_exc <= '1'; - exc_staten <= exc_enter; - - when exc_enter => - ctrl_out.exc_pending <= '1'; - exc_staten <= exc_idle; - - when exc_leave => - exc_staten <= exc_left; - status_rest <= '1'; - ctrl_out.exc_exit <= '1'; - ctrl_out.exc_commit <= '1'; - - when exc_left => - exc_staten <= exc_idle; - - when others => - exc_staten <= exc_idle; - - end case; - end process; - -proc_exc_state_next: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - exc_state <= exc_idle; - else - exc_state <= exc_staten; - end if; - end if; - end process; - --- Endian switch sampled at hard reset -sample_endian: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - EB_reg <= eb; - end if; - end if; - end process; - --- Sample imem_addr for later use -exception_last_imem_addr: - process(clk) - begin - if rising_edge(clk) then - if imem_addr_we = '1' then - imem_addr <= ctrl_in.imem_addr; - end if; - end if; - end process; - --- EPC reg and BD-bit write -cop_exception_epc_write: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - bd <= '0'; - epc <= (others => '0'); - elsif epc_reg_we = '1' then - bd <= '0'; - epc <= ctrl_in.epc_mem; - if ctrl_in.bd_wb = '1' then - bd <= '1'; - epc <= ctrl_in.epc_wb; - end if; - end if; - end if; - end process; - --- BadVaddr and exception code write -cop_exception_map: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - exc_code <= (others => '0'); - BadVAddr <= (others => '0'); - elsif code_reg_we = '1' then - if eflags.Ov = '1' then - exc_code <= "01100"; - elsif eflags.Sys = '1' then - exc_code <= "01000"; - elsif eflags.Bp = '1' then - exc_code <= "01001"; - elsif eflags.RI = '1' then - exc_code <= "01010"; - elsif eflags.IAdEL = '1' then - exc_code <= "00100"; - BadVAddr <= imem_addr; - elsif eflags.IAdEK = '1' then - exc_code <= "00100"; - BadVAddr <= imem_addr; - elsif eflags.DAdEL = '1' then - exc_code <= "00100"; - BadVAddr <= ctrl_in.dmem_addr; - elsif eflags.DAdES = '1' then - exc_code <= "00101"; - BadVAddr <= ctrl_in.dmem_addr; - elsif eflags.Int = '1' then - exc_code <= "00000"; - end if; - end if; - end if; - end process; - - ctrl_out.icache.inv_addr <= test_reg; - ctrl_out.dcache.inv_addr <= test_reg; - --- Custom I/D-Cache operations: invalidate all/line -cop_cache_op: - process(clk) - begin - if rising_edge(clk) then - ctrl_out.icache.inv_at <= '0'; - ctrl_out.icache.inv_all <= '0'; - ctrl_out.dcache.inv_at <= '0'; - ctrl_out.dcache.inv_all <= '0'; - if cop_pipe_ID.cs = '1' and cop_pipe_ID.CO = '1' then - case cop_pipe_ID.func is - when "100000" => - ctrl_out.icache.inv_all <= '1'; - when "100001" => - ctrl_out.icache.inv_at <= '1'; - when "100010" => - ctrl_out.dcache.inv_all <= '1'; - when "100011" => - ctrl_out.dcache.inv_at <= '1'; - - when others => null; - end case; - end if; - end if; - end process; - --- IP register write and signalling Int to pipeline -cop_ip_reg_write: - process(clk) - variable ip_v : unsigned(7 downto 0); - variable ipm_v : unsigned(7 downto 0); - begin - if rising_edge(clk) then - if rst = '1' then - sw_int <= (others => '0'); - elsif ctrl_in.sdu.WB_nop = '0' then - if ip_reg_we = '1' then - sw_int <= din(9 downto 8); - end if; - end if; - ip_v := (int & sw_int); - ipm_v := ip_v and im; - ip <= ip_v; - ctrl_out.int <= (eval_int(ipm_v) and status(0)); - ctrl_out.NMI <= int_nmi; - end if; - end process; - --- Exception vector dispatch -cop_exc_vector: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - ctrl_out.exc_vec <= X"BFC00000"; - elsif latch_vect_en = '1' then - if ctrl_in.events.nmi = '1' then - ctrl_out.exc_vec <= X"BFC00000"; - else - ctrl_out.exc_vec <= X"80000080"; - if status(22) = '1' then - ctrl_out.exc_vec <= X"BFC00180"; - end if; - end if; - end if; - end if; - end process; - --- Cop pipeline -cop_pipe: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - cop_pipe_EX.cs <= '0'; - cop_pipe_EX.we <= '0'; - cop_pipe_EX.re <= '0'; - elsif ctrl_in.sdu.stall_all = '0' then - cop_pipe_EX <= cop_pipe_ID; - if cop_pipe_ID.we = '1' then - reg_wptr <= cop_pipe_ID.reg_ptr; - end if; - if cop_pipe_ID.re = '1' then - reg_rptr <= cop_pipe_ID.reg_ptr; - end if; - end if; - end if; - end process; - --- COP Register read -cop_register_read: - process(reg_rptr, BadVAddr, status, cause, epc, dcache_info, icache_info, test_reg) - variable reg : word_t; - begin - - case reg_rptr is - when "01000" => -- BadVAddr - reg := BadVAddr; - - when "01100" => -- Status - reg := status; - - when "01101" => -- Cause - reg := cause; - - when "01110" => -- EPC (Exception Program Counter) - reg := epc; - - when "01111" => -- PRId (Processor Revision Register) - reg := dcache_info & icache_info & X"02" & to_unsigned(REVISION ,8); - - when "11111" => -- test_reg - reg := test_reg; - - when others => - reg := (others => '-'); - - end case; - - dout <= reg after 2 ns; - - end process; - --- COP Register write strobe generation -cop_we_gen: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - test_reg_we <= '0'; - stat_reg_we <= '0'; - ip_reg_we <= '0'; - elsif ctrl_in.sdu.stall_all = '0' then - test_reg_we <= '0'; - stat_reg_we <= '0'; - ip_reg_we <= '0'; - if cop_pipe_EX.we = '1' then - - case reg_wptr is - - when "01100" => - stat_reg_we <= '1'; -- not status(1) or status(28); - when "01101" => - ip_reg_we <= '1'; -- not status(1) or status(28); - when "11111" => - test_reg_we <= '1'; -- not status(1) or status(28); - when others => null; - - end case; - - end if; - end if; - end if; - end process; - --- COP Test Register -cop_test_reg_write: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - test_reg <= (others => '0'); - elsif ctrl_in.sdu.WB_nop = '0' then - if test_reg_we = '1' then - test_reg <= din; - end if; - end if; - end if; - end process; - --- COP Status Register -cop_status_reg_write: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - status <= X"00600000"; - elsif status_save = '1' then - if ctrl_in.events.nmi = '0' then - status(5 downto 4) <= status(3 downto 2); - status(3 downto 2) <= status(1 downto 0); - else - status(22) <= '1'; - end if; - status(1 downto 0) <= "00"; - elsif status_rest = '1' then - status(1 downto 0) <= status(3 downto 2); - status(3 downto 2) <= status(5 downto 4); - elsif ctrl_in.sdu.WB_nop = '0' then - if stat_reg_we = '1' then - if status(1) = '0' then - status(0) <= din(0); -- IEc - status(1) <= din(1); -- KUc - status(2) <= din(2); -- IEp - status(3) <= din(3); -- KUp - status(4) <= din(4); -- IEo - status(5) <= din(5); -- KUo - end if; - status(15 downto 8) <= din(15 downto 8); -- IM - status(22) <= din(22); -- BEV - status(25) <= din(25); -- RE - end if; - end if; - end if; - end process; - --------------------------------------------------------------------------- -end Behavioral; diff --git a/lib/CPUs/MIPS/src/core/mips_instr.vhd b/lib/CPUs/MIPS/src/core/mips_instr.vhd deleted file mode 100644 index cdb6115..0000000 --- a/lib/CPUs/MIPS/src/core/mips_instr.vhd +++ /dev/null @@ -1,1062 +0,0 @@ --------------------------------------------------------------------------- --- Project: JIPS, a portable 32-bit RISC CPU written in VHDL --- This file: Types, constants and functions for JCPU --- --- Copyright (C) 2008 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -library work; -use work.mips_types.all; - --------------------------------------------------------------------------- -package mips_instr is - - function extract_opc(instr : word_t) return opcode_t; - function extract_rs(instr : word_t) return reg_ptr_t; - function extract_rt(instr : word_t) return reg_ptr_t; - function extract_rd(instr : word_t) return reg_ptr_t; - function extract_shamt(instr : word_t) return shamt_t; - function extract_func(instr : word_t) return func_t; - function extract_simm32(instr : word_t) return word_t; - function extract_uimm16(instr : word_t) return word_t; - function extract_jimm32(instr, pc : word_t) return word_t; - function extract_bimm18(instr, pc : word_t) return word_t; - function decode_op(instr : word_t) return op_t; - function ctrl_lines_default return ctrl_lines_t; - function opcode_ctrl_lines(instr : word_t) return ctrl_lines_t; - -end mips_instr; - --------------------------------------------------------------------------- -library work; -use work.mips_types.all; - -package body mips_instr is - - function extract_opc(instr : word_t) return opcode_t is - variable result : opcode_t; - begin - result := instr(31 downto 26); - - return result; - - end extract_opc; - - function extract_rs(instr : word_t) return reg_ptr_t is - variable result : reg_ptr_t; - begin - result := instr(25 downto 21); - - return result; - - end extract_rs; - - function extract_rt(instr : word_t) return reg_ptr_t is - variable result : reg_ptr_t; - begin - result := instr(20 downto 16); - - return result; - - end extract_rt; - - function extract_rd(instr : word_t) return reg_ptr_t is - variable result : reg_ptr_t; - begin - result := instr(15 downto 11); - - return result; - - end extract_rd; - - function extract_shamt(instr : word_t) return shamt_t is - variable result : shamt_t; - begin - result := instr(10 downto 6); - - return result; - - end extract_shamt; - - function extract_func(instr : word_t) return func_t is - variable result : func_t; - begin - result := instr(5 downto 0); - - return result; - - end extract_func; - - function extract_simm32(instr : word_t) return word_t is - variable result : word_t; - begin - result := (31 downto 16 => instr(15)) & instr(15 downto 0); - - return result; - - end extract_simm32; - - function extract_uimm16(instr : word_t) return word_t is - variable result : word_t; - begin - result := (31 downto 16 => '0') & instr(15 downto 0); - - return result; - - end extract_uimm16; - - function extract_jimm32(instr, pc : word_t) return word_t is - variable result : word_t; - begin - result := pc(31 downto 28) & instr(25 downto 0) & "00"; - - return result; - - end extract_jimm32; - - function extract_bimm18(instr, pc : word_t) return word_t is - variable result : word_t; - begin - result := (31 downto 18 => instr(15)) & instr(15 downto 0) & "00"; - - return result; - - end extract_bimm18; - - function decode_op(instr : word_t) return op_t is - variable result : op_t; - variable opc : natural range 0 to 63; - variable func : natural range 0 to 63; - variable rt : natural range 0 to 31; - variable rs : natural range 0 to 31; - - begin - - opc := to_integer(extract_opc(instr)); - func := to_integer(extract_func(instr)); - rt := to_integer(extract_rt(instr)); - rs := to_integer(extract_rs(instr)); - - result := op_illegal; - - case opc is - - when 0 => - case func is - - when 0 => - result := op_sll; - - when 2 => - result := op_srl; - - when 3 => - result := op_sra; - - when 4 => - result := op_sllv; - - when 6 => - result := op_srlv; - - when 7 => - result := op_srav; - - when 8 => - result := op_jr; - - when 9 => - result := op_jalr; - - when 12 => - result := op_syscall; - - when 13 => - result := op_break; - - when 16 => - result := op_mfhi; - - when 17 => - result := op_mthi; - - when 18 => - result := op_mflo; - - when 19 => - result := op_mtlo; - - when 24 => - result := op_mult; - - when 25 => - result := op_multu; - - when 26 => - result := op_div; - - when 27 => - result := op_divu; - - when 32 => - result := op_add; - - when 33 => - result := op_addu; - - when 34 => - result := op_sub; - - when 35 => - result := op_subu; - - when 36 => - result := op_and; - - when 37 => - result := op_or; - - when 38 => - result := op_xor; - - when 39 => - result := op_nor; - - when 42 => - result := op_slt; - - when 43 => - result := op_sltu; - - when others => null; -- undef - - end case; - - when 1 => - case rt is - - when 0 => - result := op_bltz; - - when 1 => - result := op_bgez; - - when 16 => - result := op_bltzal; - - when 17 => - result := op_bgezal; - - when others => null; -- undef - - end case; - - when 2 => - result := op_j; - - when 3 => - result := op_jal; - - when 4 => - result := op_beq; - - when 5 => - result := op_bne; - - when 6 => - result := op_blez; - - when 7 => - result := op_bgtz; - - when 8 => - result := op_addi; - - when 9 => - result := op_addiu; - - when 10 => - result := op_slti; - - when 11 => - result := op_sltiu; - - when 12 => - result := op_andi; - - when 13 => - result := op_ori; - - when 14 => - result := op_xori; - - when 15 => - result := op_lui; - - when 16 => - result := op_cop0; - case rs is - when 0 => - result := op_mfc0; - when 2 => - result := op_cfc0; -- illegal - when 4 => - result := op_mtc0; - when 6 => - result := op_ctc0; -- illegal - when 8 => - case rt is - when 0 => - result := op_bcf0; -- illegal - when 1 => - result := op_bct0; -- illegal - - when others => null; -- undef - end case; - - when others => null; -- undef - - end case; - - when 17 => - result := op_cop1; - case rs is - when 0 => - result := op_mfc1; - when 2 => - result := op_cfc1; - when 4 => - result := op_mtc1; - when 6 => - result := op_ctc1; - when 8 => - case rt is - when 0 => - result := op_bcf1; - when 1 => - result := op_bct1; - - when others => null; -- undef - end case; - - when others => null; -- undef - - end case; - - when 18 => - result := op_cop2; - case rs is - when 0 => - result := op_mfc2; - when 2 => - result := op_cfc2; - when 4 => - result := op_mtc2; - when 6 => - result := op_ctc2; - when 8 => - case rt is - when 0 => - result := op_bcf2; - when 1 => - result := op_bct2; - - when others => null; -- undef - end case; - - when others => null; -- undef - - end case; - - when 19 => - result := op_cop3; - case rs is - when 0 => - result := op_mfc3; - when 2 => - result := op_cfc3; - when 4 => - result := op_mtc3; - when 6 => - result := op_ctc3; - when 8 => - case rt is - when 0 => - result := op_bcf3; - when 1 => - result := op_bct3; - - when others => null; -- undef - end case; - - when others => null; -- undef - - end case; - - when 32 => - result := op_lb; - - when 33 => - result := op_lh; - - when 34 => - result := op_lwl; - - when 35 => - result := op_lw; - - when 36 => - result := op_lbu; - - when 37 => - result := op_lhu; - - when 38 => - result := op_lwr; - - when 40 => - result := op_sb; - - when 41 => - result := op_sh; - - when 42 => - result := op_swl; - - when 43 => - result := op_sw; - - when 46 => - result := op_swr; - - when 48 => - result := op_lwc0; -- illegal - - when 49 => - result := op_lwc1; - - when 50 => - result := op_lwc2; - - when 51 => - result := op_lwc3; - - when 56 => - result := op_swc0; -- illegal - - when 57 => - result := op_swc1; - - when 58 => - result := op_swc2; - - when 59 => - result := op_swc3; - - when others => null; -- undef - - end case; - - return result; - - end decode_op; - - function ctrl_lines_default return ctrl_lines_t is - variable result : ctrl_lines_t; - begin - result.cop_instr_en := '0'; - result.cop_read := '0'; - result.jump := '0'; - result.jump_long := '0'; - result.branch := '0'; - result.bc_src := bc_eq_ne; - result.bc_not := '0'; - result.alu.outsel := alu_adder; - result.alu.add := '1'; - result.alu.shift_right := '0'; - result.alu.shift_arith := '0'; - result.shamt2_srcsel := sa_src_imm; - result.alu.op1_src := alu_src_reg; - result.alu.op2_src := alu_src_reg; - result.imm_src := src_imm16; - result.reg_write := '0'; - result.dmem_we := '0'; - result.dmem_en := '0'; - result.wptr_srcsel := wptr_src_imm; - result.reg_link := '0'; - result.shift_offset := "00"; - result.shift_byp := '1'; - result.byte_en_byp := '1'; - result.sign_ext_byp := '1'; - result.word4_en := '0'; - result.word2_en := '0'; - result.align_left := '0'; - result.load_signed := '0'; - result.mul_access := '0'; - result.mul_hilo_we := '0'; - result.mul_start := '0'; - result.mul_s_un := '0'; - result.mul_mul_divn := '0'; - result.mul_hilo_sel := '1'; - result.exc_break := '0'; - result.exc_syscall := '0'; - result.exc_illegal := '0'; - result.except_en := '0'; - result.alu_exc_en := '0'; - - return result; - - end ctrl_lines_default; - - function opcode_ctrl_lines(instr : word_t) return ctrl_lines_t is - variable result : ctrl_lines_t; - variable opc : integer range 0 to 2**opcode_t'length-1; - variable func : integer range 0 to 2**func_t'length-1; - variable rt : integer range 0 to 2**reg_ptr_t'length-1; - variable rs : integer range 0 to 2**reg_ptr_t'length-1; - begin - - result := ctrl_lines_default; - opc := to_integer(extract_opc(instr)); - func := to_integer(extract_func(instr)); - rt := to_integer(extract_rt(instr)); - rs := to_integer(extract_rs(instr)); - - case opc is --- SPECIAL - when 0 => - case func is - - -- when op_add => - when 32 => - result.alu.outsel := alu_adder; - result.alu.add := '1'; - result.alu.op1_src := alu_src_reg; - result.alu.op2_src := alu_src_reg; - result.reg_write := '1'; - result.alu_exc_en := '1'; - - -- when op_addu => - when 33 => - result.alu.outsel := alu_adder; - result.alu.add := '1'; - result.alu.op1_src := alu_src_reg; - result.alu.op2_src := alu_src_reg; - result.reg_write := '1'; - - -- when op_and => - when 36 => - result.alu.outsel := alu_and; - result.alu.op1_src := alu_src_reg; - result.alu.op2_src := alu_src_reg; - result.reg_write := '1'; - - -- when op_break => - when 13 => - result.exc_break := '1'; - result.except_en := '1'; - - -- when op_div => - when 26 => - result.mul_access := '1'; - result.mul_start := '1'; - result.mul_s_un := '1'; - result.mul_mul_divn := '0'; - - -- when op_divu => - when 27 => - result.mul_access := '1'; - result.mul_start := '1'; - result.mul_s_un := '0'; - result.mul_mul_divn := '0'; - - -- when op_jalr => - when 9 => - result.jump_long := '1'; - result.wptr_srcsel := wptr_src_imm; - result.reg_write := '1'; - result.reg_link := '1'; - - -- when op_jr => - when 8 => - result.jump_long := '1'; - - -- when op_mfhi => - when 16 => - result.reg_write := '1'; - result.mul_access := '1'; - result.mul_hilo_sel := '1'; - - -- when op_mflo => - when 18 => - result.reg_write := '1'; - result.mul_access := '1'; - result.mul_hilo_sel := '0'; - - -- when op_mthi => - when 17 => - result.mul_hilo_we := '1'; - result.mul_hilo_sel := '1'; - - -- when op_mtlo => - when 19 => - result.mul_hilo_we := '1'; - result.mul_hilo_sel := '0'; - - -- when op_mult => - when 24 => - result.mul_access := '1'; - result.mul_start := '1'; - result.mul_s_un := '1'; - result.mul_mul_divn := '1'; - - -- when op_multu => - when 25 => - result.mul_access := '1'; - result.mul_start := '1'; - result.mul_s_un := '0'; - result.mul_mul_divn := '1'; - - -- when op_or => - when 37 => - result.alu.outsel := alu_or; - result.alu.op1_src := alu_src_reg; - result.alu.op2_src := alu_src_reg; - result.reg_write := '1'; - - -- when op_nor => - when 39 => - result.alu.outsel := alu_nor; - result.alu.op1_src := alu_src_reg; - result.alu.op2_src := alu_src_reg; - result.reg_write := '1'; - - -- when op_sll => - when 0 => - result.alu.op2_src := alu_src_reg; - result.alu.outsel := alu_shift2; - result.alu.shift_right := '0'; - result.shamt2_srcsel := sa_src_imm; - result.reg_write := '1'; - - -- when op_sllv => - when 4 => - result.alu.op2_src := alu_src_reg; - result.alu.outsel := alu_shift2; - result.alu.shift_right := '0'; - result.shamt2_srcsel := sa_src_reg; - result.reg_write := '1'; - - -- when op_slt => - when 42 => - result.alu.outsel := alu_lts; - result.alu.add := '0'; - result.alu.op1_src := alu_src_reg; - result.alu.op2_src := alu_src_reg; - result.reg_write := '1'; - - -- when op_sltu => - when 43 => - result.alu.outsel := alu_ltu; - result.alu.add := '0'; - result.alu.op1_src := alu_src_reg; - result.alu.op2_src := alu_src_reg; - result.reg_write := '1'; - - -- when op_sra => - when 3 => - result.alu.op2_src := alu_src_reg; - result.alu.outsel := alu_shift2; - result.alu.shift_right := '1'; - result.alu.shift_arith := '1'; - result.shamt2_srcsel := sa_src_imm; - result.reg_write := '1'; - - -- when op_srav => - when 7 => - result.alu.op2_src := alu_src_reg; - result.alu.outsel := alu_shift2; - result.alu.shift_right := '1'; - result.alu.shift_arith := '1'; - result.shamt2_srcsel := sa_src_reg; - result.reg_write := '1'; - - -- when op_srl => - when 2 => - result.alu.op2_src := alu_src_reg; - result.alu.outsel := alu_shift2; - result.alu.shift_right := '1'; - result.alu.shift_arith := '0'; - result.shamt2_srcsel := sa_src_imm; - result.reg_write := '1'; - - -- when op_srlv => - when 6 => - result.alu.op2_src := alu_src_reg; - result.alu.outsel := alu_shift2; - result.alu.shift_right := '1'; - result.alu.shift_arith := '0'; - result.shamt2_srcsel := sa_src_reg; - result.reg_write := '1'; - - -- when op_sub => - when 34 => - result.alu.outsel := alu_adder; - result.alu.add := '0'; - result.alu.op1_src := alu_src_reg; - result.alu.op2_src := alu_src_reg; - result.reg_write := '1'; - result.alu_exc_en := '1'; - - -- when op_subu => - when 35 => - result.alu.outsel := alu_adder; - result.alu.add := '0'; - result.alu.op1_src := alu_src_reg; - result.alu.op2_src := alu_src_reg; - result.reg_write := '1'; - - -- when op_syscall => - when 12 => - result.exc_syscall := '1'; - result.except_en := '1'; - - -- when op_xor => - when 38 => - result.alu.outsel := alu_xor; - result.alu.op1_src := alu_src_reg; - result.alu.op2_src := alu_src_reg; - result.reg_write := '1'; - - when others => - result.exc_illegal := '1'; - - end case; - --- REGIMM - when 1 => - case rt is - - -- when op_bgez => - when 1 => - result.branch := '1'; - result.bc_src := bc_ltz_gez; - result.bc_not := '1'; - - -- when op_bgezal => - when 17 => - result.branch := '1'; - result.bc_src := bc_ltz_gez; - result.bc_not := '1'; - result.wptr_srcsel := wptr_src_const; - result.reg_write := '1'; - result.reg_link := '1'; - - -- when op_bltz => - when 0 => - result.branch := '1'; - result.bc_src := bc_ltz_gez; - result.bc_not := '0'; - - -- when op_bltzal => - when 16 => - result.branch := '1'; - result.bc_src := bc_ltz_gez; - result.bc_not := '0'; - result.wptr_srcsel := wptr_src_const; - result.reg_write := '1'; - result.reg_link := '1'; - - when others => - result.exc_illegal := '1'; - - end case; - --- when COPz => - when 16 | 17 | 18 | 19 => - result.cop_instr_en := '1'; - case rs is - when 0 => -- MFCz - result.cop_read := '1'; - result.reg_write := '1'; - when 2 => -- CFCz - result.cop_read := '1'; - result.reg_write := '1'; - - when others => null; -- undef - - end case; - - --- when op_addi => - when 8 => - result.imm_src := src_imm32; - result.alu.outsel := alu_adder; - result.alu.add := '1'; - result.alu.op1_src := alu_src_reg; - result.alu.op2_src := alu_src_imm; - result.reg_write := '1'; - result.alu_exc_en := '1'; - --- when op_addiu => - when 9 => - result.imm_src := src_imm32; - result.alu.outsel := alu_adder; - result.alu.add := '1'; - result.alu.op1_src := alu_src_reg; - result.alu.op2_src := alu_src_imm; - result.reg_write := '1'; - --- when op_andi => - when 12 => - result.imm_src := src_imm16; - result.alu.outsel := alu_and; - result.alu.op1_src := alu_src_reg; - result.alu.op2_src := alu_src_imm; - result.reg_write := '1'; - --- when op_beq => - when 4 => - result.branch := '1'; - result.bc_src := bc_eq_ne; - result.bc_not := '0'; - --- when op_bgtz => - when 7 => - result.branch := '1'; - result.bc_src := bc_lez_gtz; - result.bc_not := '1'; - --- when op_blez => - when 6 => - result.branch := '1'; - result.bc_src := bc_lez_gtz; - result.bc_not := '0'; - --- when op_bne => - when 5 => - result.branch := '1'; - result.bc_src := bc_eq_ne; - result.bc_not := '1'; - --- when op_j => - when 2 => - result.jump := '1'; - --- when op_jal => - when 3 => - result.jump := '1'; - result.wptr_srcsel := wptr_src_const; - result.reg_write := '1'; - result.reg_link := '1'; - --- when op_lb => - when 32 => - result.imm_src := src_imm32; - result.dmem_en := '1'; - result.reg_write := '1'; - result.shift_byp := '0'; - result.byte_en_byp := '1'; - result.sign_ext_byp := '0'; - result.load_signed := '1'; - result.word4_en := '1'; - --- when op_lbu => - when 36 => - result.imm_src := src_imm32; - result.dmem_en := '1'; - result.reg_write := '1'; - result.shift_byp := '0'; - result.byte_en_byp := '1'; - result.sign_ext_byp := '0'; - result.load_signed := '0'; - result.word4_en := '1'; - --- when op_lh => - when 33 => - result.imm_src := src_imm32; - result.dmem_en := '1'; - result.reg_write := '1'; - result.shift_byp := '0'; - result.sign_ext_byp := '0'; - result.byte_en_byp := '1'; - result.load_signed := '1'; - result.word2_en := '1'; - result.except_en := '1'; - --- when op_lhu => - when 37 => - result.imm_src := src_imm32; - result.dmem_en := '1'; - result.reg_write := '1'; - result.shift_byp := '0'; - result.sign_ext_byp := '0'; - result.byte_en_byp := '1'; - result.load_signed := '0'; - result.word2_en := '1'; - result.except_en := '1'; - --- when op_lui => - when 15 => - result.imm_src := src_imm16_high; - result.alu.op1_src := alu_src_reg; - result.alu.op2_src := alu_src_imm; - result.alu.outsel := alu_adder; - result.reg_write := '1'; - result.alu.add := '1'; - --- when op_lw => - when 35 => --- result.imm_src := src_imm32; - result.dmem_en := '1'; - result.reg_write := '1'; - result.except_en := '1'; - --- when op_lwcz => - when 48 | 49 | 50 | 51 => --- result.imm_src := src_imm32; - result.dmem_en := '1'; - result.except_en := '1'; - result.cop_instr_en := '1'; - --- when op_lwl => - when 34 => --- result.imm_src := src_imm32; - result.dmem_en := '1'; - result.reg_write := '1'; - result.shift_byp := '0'; - result.byte_en_byp := '0'; - result.shift_offset := "01"; - result.align_left := '1'; - --- when op_lwr => - when 38 => --- result.imm_src := src_imm32; - result.dmem_en := '1'; - result.reg_write := '1'; - result.shift_byp := '0'; - result.byte_en_byp := '0'; - result.shift_offset := "00"; - result.align_left := '0'; - --- when op_ori => - when 13 => - result.imm_src := src_imm16; - result.alu.outsel := alu_or; - result.alu.op1_src := alu_src_reg; - result.alu.op2_src := alu_src_imm; - result.reg_write := '1'; - --- when op_sb => - when 40 => - result.dmem_en := '1'; - result.dmem_we := '1'; --- result.imm_src := src_imm32; - result.shift_byp := '0'; - result.byte_en_byp := '0'; - result.word4_en := '1'; - --- when op_sh => - when 41 => - result.dmem_en := '1'; - result.dmem_we := '1'; --- result.imm_src := src_imm32; - result.shift_byp := '0'; - result.byte_en_byp := '0'; - result.word2_en := '1'; - result.except_en := '1'; - --- when op_slti => - when 10 => - result.alu.outsel := alu_lts; - result.alu.add := '0'; - result.alu.op1_src := alu_src_reg; - result.alu.op2_src := alu_src_imm; - result.imm_src := src_imm32; - result.reg_write := '1'; - --- when op_sltiu => - when 11 => - result.alu.outsel := alu_ltu; - result.alu.add := '0'; - result.alu.op1_src := alu_src_reg; - result.alu.op2_src := alu_src_imm; - result.imm_src := src_imm32; - result.reg_write := '1'; - --- when op_sw => - when 43 => - result.dmem_en := '1'; - result.dmem_we := '1'; --- result.imm_src := src_imm32; - result.except_en := '1'; - --- when op_swcz => - when 56 | 57 | 58 | 59 => - result.dmem_en := '1'; - result.dmem_we := '1'; --- result.imm_src := src_imm32; - result.except_en := '1'; - result.cop_instr_en := '1'; - result.cop_read := '1'; - --- when op_swl => - when 42 => - result.dmem_en := '1'; - result.dmem_we := '1'; --- result.imm_src := src_imm32; - result.shift_byp := '0'; - result.byte_en_byp := '0'; - result.shift_offset := "01"; - --- when op_swr => - when 46 => - result.dmem_en := '1'; - result.dmem_we := '1'; --- result.imm_src := src_imm32; - result.shift_byp := '0'; - result.byte_en_byp := '0'; - result.align_left := '1'; - --- when op_xori => - when 14 => - result.imm_src := src_imm16; - result.alu.outsel := alu_xor; - result.alu.op1_src := alu_src_reg; - result.alu.op2_src := alu_src_imm; - result.reg_write := '1'; - - when others => - result.exc_illegal := '1'; - - end case; - - return result; - - end opcode_ctrl_lines; - -end mips_instr; - --------------------------------------------------------------------------- --------------------------------------------------------------------------- - diff --git a/lib/CPUs/MIPS/src/core/mips_muldiv.vhd b/lib/CPUs/MIPS/src/core/mips_muldiv.vhd deleted file mode 100644 index efce36b..0000000 --- a/lib/CPUs/MIPS/src/core/mips_muldiv.vhd +++ /dev/null @@ -1,454 +0,0 @@ --------------------------------------------------------------------------- --- Project: JIPS, a portable 32-bit RISC CPU written in VHDL --- This file: The arithmetic logic unit --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.mips_types.all; - -entity muldiv is - Port - ( - rst : in std_logic; - clk : in std_logic; - hilo_we : in std_logic; - din_hi : in word_t; - din_lo : in word_t; - mul_divn : in std_logic; - start : in std_logic; - s_un : in std_logic; - hilo_sel : in std_logic; - busy : out std_logic; - dout : out word_t - ); -end muldiv; - -architecture Behavioral of muldiv is - - subtype pprod_t is unsigned (39 downto 0); - subtype prod_t is unsigned (63 downto 0); - subtype byte_t is unsigned (7 downto 0); - - type pprod_array_t is array (natural range <>) of pprod_t; - type word_array_t is array (natural range <>) of word_t; - type byte_array_t is array (natural range <>) of byte_t; - - signal pprod : pprod_array_t(0 to 3); - signal sign1 : std_logic; - signal sign2 : std_logic; - signal s1_r : std_logic; - signal s2_r : std_logic; - signal sr_r : std_logic; - signal cy : unsigned (3 downto 0); - signal mul_start : std_logic; - signal mul_en : std_logic; - signal sum_en : std_logic; - signal pre_sum_vld : std_logic; - signal pp_reg : unsigned (63 downto 8); - signal pre_const : word_array_t(0 to 1); - signal result : prod_t; - signal add_op1 : unsigned (39 downto 0); - signal add_op2 : unsigned (39 downto 0); - signal add_res : unsigned (39 downto 0); - signal ppadd_op1 : word_array_t(0 to 3); - signal ppadd_op2 : word_array_t(0 to 3); - signal ppadd_res : word_array_t(0 to 3); - signal ppadd_cyi : unsigned (3 downto 0); - signal ppadd_cyo : unsigned (3 downto 0); - - signal pp_op1_r : word_t; - signal pp_op1 : word_t; - signal pp_op2 : word_t; - signal pp_op2_r : byte_array_t(0 to 3); - signal bsy : std_logic; - - signal div_add_res : unsigned (32 downto 0); - signal div_add_op1 : unsigned (32 downto 0); - signal div_add_op2 : unsigned (32 downto 0); - signal div_add_cyi : std_logic; - signal div_qbit : std_logic; - signal div_start : std_logic; - signal div_en : std_logic; - - signal div_A : unsigned (32 downto 0); - signal div_M : unsigned (32 downto 0); - signal div_M_n : unsigned (32 downto 0); - signal div_Q : word_t; - - type md_state_t is (md_rdy, mul_pre1, mul_pre2, mul_pp, mul_sum, div_process, div_post1, div_post2, div_post3); - signal s, sn : md_state_t; - signal cycle_cnt : natural range 0 to 31; - signal cycle_cnt_preset : natural range 0 to 31; - signal cycle_cnt_load : std_logic; - signal div_fin_en : unsigned (2 downto 0); - --------------------------------------------------------------------------- -begin --- 9A0CD0570B88D78 - - busy <= bsy; - - sign1 <= din_hi(din_hi'left) and s_un; - sign2 <= din_lo(din_lo'left) and s_un; - pp_op1 <= not din_hi when sign1 = '1' else din_hi; - pp_op2 <= not din_lo when sign2 = '1' else din_lo; - --------------------------------------------------------------------------- -md_state: - process(s, start, mul_divn, cycle_cnt) - begin - - bsy <= '1'; - cycle_cnt_load <= '0'; - cycle_cnt_preset <= 7; - - mul_en <= '0'; - div_en <= '0'; - sum_en <= '0'; - pre_sum_vld <= '0'; - mul_start <= '0'; - div_start <= '0'; - div_fin_en <= "000"; - sn <= s; - case s is - when md_rdy => - bsy <= '0'; - if start = '1' then - if mul_divn = '1' then - sn <= mul_pre1; - cycle_cnt_load <= '1'; - cycle_cnt_preset <= 7; - mul_start <= '1'; - else - sn <= div_process; - cycle_cnt_load <= '1'; - cycle_cnt_preset <= 31; - div_start <= '1'; - end if; - end if; - when mul_pre1 => - pre_sum_vld <= '1'; - mul_en <= '1'; - sn <= mul_pre2; - when mul_pre2 => - pre_sum_vld <= '1'; - mul_en <= '1'; - sn <= mul_pp; - when mul_pp => - mul_en <= '1'; - if cycle_cnt = 0 then - cycle_cnt_load <= '1'; - cycle_cnt_preset <= 3; - sn <= mul_sum; - end if; - when mul_sum => - sum_en <= '1'; - if cycle_cnt = 0 then - bsy <= '0'; - sn <= md_rdy; - end if; - when div_process => - div_en <= '1'; - if cycle_cnt = 0 then - sn <= div_post1; - end if; - when div_post1 => - div_fin_en <= "001"; - sn <= div_post2; - when div_post2 => - div_fin_en <= "010"; - sn <= div_post3; - when div_post3 => - div_fin_en <= "100"; - sn <= md_rdy; - bsy <= '0'; - when others => - sn <= md_rdy; - end case; - - end process; - -md_state_next: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - s <= md_rdy; - else - s <= sn; - end if; - end if; - end process; - -md_cycle_cnt: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - cycle_cnt <= 0; - elsif cycle_cnt_load = '1' then - cycle_cnt <= cycle_cnt_preset; - elsif cycle_cnt /= 0 then - cycle_cnt <= cycle_cnt - 1; - end if; - end if; - end process; - -proc_out_reg: - process(hilo_sel, result) - begin - if hilo_sel = '1' then - dout <= result(63 downto 32); - else - dout <= result(31 downto 0); - end if; - end process; - -proc_in_reg: - process(clk) - variable pre_cond : unsigned(1 downto 0); - begin - if rising_edge(clk) then - if mul_start = '1' or div_start = '1' then - pp_op1_r <= pp_op1; - pre_const(0) <= (others => '0'); - pre_const(1) <= (others => '0'); - pre_cond := (din_hi(din_hi'left) and s_un) & (din_lo(din_lo'left) and s_un); - s1_r <= pre_cond(1); - s2_r <= pre_cond(0); - sr_r <= pre_cond(0) xor pre_cond(1); - case pre_cond is - when "01" => - pre_const(0) <= din_hi; - pre_const(1) <= X"FFFF_FFFF"; - when "10" => - pre_const(0) <= X"0000_0000"; - pre_const(1) <= X"FFFF_FFFF"; - when "11" => - pre_const(0) <= not din_hi; - pre_const(1) <= X"0000_0001"; - when others => null; - end case; - elsif pre_sum_vld = '1' then - pre_const(0) <= pre_const(1); - end if; - end if; - end process; - -proc_mul_sr: - process(clk) - begin - if rising_edge(clk) then - if mul_start = '1' then - for i in 0 to 3 loop - cy(i) <= '0'; - pprod(i) <= ppadd_res(i) & X"00"; - end loop; - elsif mul_en = '1' then - for i in 0 to 3 loop - cy(i) <= ppadd_cyo(i); - pprod(i) <= ppadd_res(i) & pprod(i)(8 downto 1); - end loop; - elsif sum_en = '1' then - for i in 1 to 3 loop - pprod(i-1) <= pprod(i); - end loop; - end if; - end if; - end process; - -gen_mul32x8pp: - for i in 0 to 3 generate - begin - - pp_adder_mux: - process(mul_start, pp_op1, pp_op2, pp_op1_r, pp_op2_r(i), s1_r, sign1, pprod(i), cy(i)) - variable v2 : unsigned(7 downto 0); - begin - ppadd_cyi(i) <= '0'; - ppadd_op1(i) <= (others => '0'); - if mul_start = '1' then - ppadd_op2(i) <= (others => '0'); - v2 := pp_op2(8*(i+1)-1 downto 8*i); - if v2(0) = '1' then - ppadd_cyi(i) <= sign1; - ppadd_op1(i) <= pp_op1; - end if; - else - ppadd_op2(i) <= cy(i) & pprod(i)(39 downto 9); - v2 := pp_op2_r(i); - if v2(0) = '1' then - ppadd_cyi(i) <= s1_r; - ppadd_op1(i) <= pp_op1_r; - end if; - end if; - end process; - - pp_adder: - process(ppadd_op1(i), ppadd_op2(i), ppadd_cyi(i)) - variable sum_pp : unsigned(33 downto 0); - begin - sum_pp := ('0' & ppadd_op1(i) & ppadd_cyi(i)) + ('0' & ppadd_op2(i) & ppadd_cyi(i)); - ppadd_res(i) <= sum_pp(sum_pp'left-1 downto 1); - ppadd_cyo(i) <= sum_pp(sum_pp'left); - end process; - - proc_mul_ctrl: - process(clk) - begin - if rising_edge(clk) then - if mul_start = '1' then - pp_op2_r(i) <= '0' & pp_op2(8*(i+1)-1 downto 8*i+1); - elsif mul_en = '1' then - pp_op2_r(i) <= '0' & pp_op2_r(i)(7 downto 1); - end if; - end if; - end process; - - end generate; - -comb_mul_adder: - process(add_op1, add_op2) - variable sum_mul : unsigned(39 downto 0); - begin - sum_mul := (add_op1) + (add_op2); - add_res <= sum_mul(sum_mul'left downto 0); - end process; - -comb_mul_adder_mux: - process(pre_const, pre_sum_vld, pp_reg, pprod, sr_r) - variable s_ext : std_logic; - begin - if pre_sum_vld = '1' then - add_op1 <= pp_reg(63 downto 24); - add_op2 <= pre_const(0) & X"00"; - else - s_ext := pp_reg(63) and sr_r; - add_op1 <= (7 downto 0 => s_ext) & pp_reg(63 downto 32); - add_op2 <= pprod(0); - end if; - end process; - -comb_mul: - process(clk) - variable tmp : prod_t; - begin - if rising_edge(clk) then - if mul_start = '1' then - pp_reg <= (others => '0'); - elsif pre_sum_vld = '1' then - pp_reg <= add_res & X"0000"; - elsif sum_en = '1' then - tmp := add_res & pp_reg(31 downto 8); - pp_reg <= tmp(63 downto 8); - result <= tmp; - if sr_r = '1' then - result <= not tmp; - end if; - elsif div_fin_en(1) = '1' then - result(63 downto 32) <= div_A(31 downto 0); - if s1_r = '1' then - result(63 downto 32) <= div_add_res(31 downto 0); - end if; - elsif div_fin_en(2) = '1' then - result(31 downto 0) <= div_Q; - if sr_r = '1' then - result(31 downto 0) <= div_add_res(31 downto 0); - end if; - elsif hilo_we = '1' then - if hilo_sel = '1' then - result(63 downto 32) <= din_hi; - else - result(31 downto 0) <= din_hi; - end if; - end if; - end if; - end process; - -div_adder: - process(div_add_op1, div_add_op2, div_add_cyi) - variable sum_div : unsigned(33 downto 0); - begin - sum_div := (div_add_op1 & div_add_cyi) + (div_add_op2 & div_add_cyi); - div_add_res <= sum_div(sum_div'left downto 1); - end process; - -div_adder_mux: - process(div_start, div_en, div_fin_en, div_A, div_Q, pp_op1, sign1, s1_r, s2_r, sr_r, div_qbit, div_M, div_M_n) - begin - - div_add_cyi <= s2_r xor div_qbit; - div_add_op1 <= div_A(31 downto 0) & div_Q(31); - div_add_op2 <= (others => '0'); - if div_start = '1' then - div_add_op1 <= '0' & pp_op1; - div_add_cyi <= sign1; - elsif div_en = '1' then - div_add_op2 <= div_M; - if div_qbit = '1' then - div_add_op2 <= div_M_n; - end if; - elsif div_fin_en(0) = '1' then - div_add_op2 <= div_M; - div_add_cyi <= s2_r; - div_add_op1 <= '0' & div_A(31 downto 0); - elsif div_fin_en(1) = '1' then - div_add_cyi <= s1_r; - div_add_op1 <= '0' & not div_A(31 downto 0); - elsif div_fin_en(2) = '1' then - div_add_cyi <= sr_r; - div_add_op1 <= '0' & not div_Q; - end if; - end process; - -divide: - process(clk) - variable quo : std_logic; - begin - if rising_edge(clk) then - if div_start = '1' then - div_qbit <= '1'; - div_Q <= div_add_res(31 downto 0); - div_A <= (others => '0'); - if sign2 = '1' then - div_M_n <= '1' & din_lo; - div_M <= '0' & not din_lo; - else - div_M_n <= '1' & not din_lo; - div_M <= '0' & din_lo; - end if; - elsif div_en = '1' then - div_qbit <= not div_add_res(32); - div_A <= div_add_res(32 downto 0); - div_Q <= div_Q(30 downto 0) & not div_add_res(32); - elsif div_fin_en(0) = '1' then - if div_A(32) = '1' then - div_A <= '0' & div_add_res(31 downto 0); - end if; - end if; - end if; - end process; - --------------------------------------------------------------------------- -end Behavioral; diff --git a/lib/CPUs/MIPS/src/core/mips_pipeline.vhd b/lib/CPUs/MIPS/src/core/mips_pipeline.vhd deleted file mode 100644 index 38dd440..0000000 --- a/lib/CPUs/MIPS/src/core/mips_pipeline.vhd +++ /dev/null @@ -1,867 +0,0 @@ --------------------------------------------------------------------------- --- Project: JIPS, a portable 32-bit RISC CPU written in VHDL --- This file: The pipeline --- --- Copyright (C) 2008 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -library work; -use work.mips_types.all; -use work.mips_instr.all; - -entity pipeline is - Port - ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - ce : in STD_LOGIC; - imem_err : in STD_LOGIC; - imem_rdy : in STD_LOGIC; - imem_en : out STD_LOGIC; - imem_addr : out word_t; - imem_data : in word_t; - dmem_err : in STD_LOGIC; - dmem_rdy : in STD_LOGIC; - dmem_en : out STD_LOGIC; - dmem_we : out STD_LOGIC; - dmem_be : out unsigned(3 downto 0); - dmem_addr : out word_t; - dmem_din : in word_t; - dmem_dout : out word_t; - cop_ir : out word_t; - cop_ir_en : out STD_LOGIC; - cop_din : in word_t; - cop_dout : out word_t; - c0_ctrl_out : out cop0_ctrl_in_t; - c0_ctrl_in : in cop0_ctrl_out_t - - ); -end pipeline; - -architecture Behavioral of pipeline is - --------------------------------------------------------------------------- - COMPONENT reg_dual is - Generic - ( - addr_width : integer := 3; - data_width : integer := 8 - ); - Port - ( - clk_w : in STD_LOGIC; - en : in STD_LOGIC; - we : in STD_LOGIC; - wptr : in unsigned (addr_width-1 downto 0); - din : in unsigned (data_width-1 downto 0); - rptr_a : in unsigned (addr_width-1 downto 0); - rptr_b : in unsigned (addr_width-1 downto 0); - dout_a : out unsigned (data_width-1 downto 0); - dout_b : out unsigned (data_width-1 downto 0) - ); - END COMPONENT; - --------------------------------------------------------------------------- - COMPONENT shifter is - Generic - ( - data_width : integer - ); - Port - ( - shift_ctrl : in shift_ctrl_t; - din : in unsigned (data_width-1 downto 0); - dout : out unsigned (data_width-1 downto 0) - ); - END COMPONENT; - --------------------------------------------------------------------------- - COMPONENT alu is - Generic - ( - data_width : integer - ); - Port - ( - op1_in : in unsigned (data_width-1 downto 0); - op2_in : in unsigned (data_width-1 downto 0); - op2_shifted : in unsigned (data_width-1 downto 0); - ctrl : in alu_ctrl_t; - result : out unsigned (data_width-1 downto 0); - flags : out alu_flags_t - ); - END COMPONENT; - --------------------------------------------------------------------------- - COMPONENT bcu is - Generic - ( - data_width : integer - ); - Port - ( - op1_in : in unsigned (data_width-1 downto 0); - op2_in : in unsigned (data_width-1 downto 0); - flags : out bcu_flags_t - ); - END COMPONENT; - --------------------------------------------------------------------------- - COMPONENT muldiv is - Port - ( - rst : in std_logic; - clk : in std_logic; - hilo_we : in std_logic; - din_hi : in word_t; - din_lo : in word_t; - mul_divn : in std_logic; - start : in std_logic; - s_un : in std_logic; - hilo_sel : in std_logic; - busy : out std_logic; - dout : out word_t - ); - END COMPONENT; - --------------------------------------------------------------------------- - signal ID_stage : ID_t; - signal EX_stage : EX_t; - signal MEM_stage : MEM_t; - signal WB_stage : WB_t; - signal clk_2, clk_1 : STD_LOGIC; - signal hdu : hdu_t; - signal sdu : sdu_t; - signal reg_a : word_t; - signal reg_b : word_t; - signal branch_ce : STD_LOGIC; - signal cpu_run : STD_LOGIC; - signal alu_result : word_t; - signal mul_result : word_t; - signal mul_busy : STD_LOGIC; - signal EX_events_instr : event_t; - signal EX_events_alu : event_t; - signal EX_events_mem : event_t; - signal EX_events : event_t; - signal MEM_events : event_t; - signal bcu_op_a : word_t; - signal bcu_op_b : word_t; - signal bcu_flags : bcu_flags_t; - signal vaddr : word_t; - signal dmem_src : word_t; - signal stage_rst : unsigned(3 downto 0); - signal pipe_rst : STD_LOGIC; - - signal pc : pc_t; - --------------------------------------------------------------------------- -begin - - clk_1 <= clk; - clk_2 <= not clk; - cpu_run <= ce; - - -- Stall Detection Unit --------------------------------------------------- - sdu.ID_nop <= sdu.imem_dep or c0_ctrl_in.exc_pending or ID_stage.exc or EX_stage.exc or MEM_stage.exc; - sdu.EX_nop <= sdu.mul_dep or ID_stage.nop or ID_stage.exc; - sdu.MEM_nop <= EX_stage.nop or EX_stage.exc; - sdu.WB_nop <= sdu.dmem_dep or MEM_stage.nop; - - sdu.stall_all <= sdu.dmem_dep; - sdu.ID_stall <= sdu.stall_all or sdu.imem_dep or sdu.mul_dep or c0_ctrl_in.exc_exit; - sdu.EX_stall <= sdu.stall_all; - sdu.MEM_stall <= sdu.stall_all; - sdu.WB_stall <= '0'; - - sdu.mul_dep <= ID_stage.ctrl.mul_access and (EX_stage.ctrl.mul_start or mul_busy); - sdu.imem_dep <= not imem_rdy; - sdu.dmem_dep <= not dmem_rdy and MEM_stage.ctrl.dmem_en; - --------------------------------------------------------------------------- - imem_en <= cpu_run and not (sdu.mul_dep or sdu.dmem_dep or c0_ctrl_in.exc_commit); - --------------------------------------------------------------------------- --- Coprocessor assignments --------------------------------------------------------------------------- - c0_ctrl_out.bd_wb <= WB_stage.bd; - c0_ctrl_out.epc_mem <= MEM_stage.pcn; - c0_ctrl_out.epc_wb <= MEM_stage.epc; - c0_ctrl_out.imem_addr <= EX_stage.epc; - c0_ctrl_out.dmem_addr <= MEM_stage.va; - c0_ctrl_out.sdu <= sdu; - c0_ctrl_out.events <= WB_stage.events; - c0_ctrl_out.exc_req <= MEM_stage.exc; - c0_ctrl_out.exc_ack <= WB_stage.exc; - cop_ir <= ID_stage.IR; - cop_ir_en <= ID_stage.ctrl.cop_instr_en; - cop_dout <= dmem_din when MEM_stage.ctrl.dmem_en = '1' else MEM_stage.ex_result; - --------------------------------------------------------------------------- --- Muldiv --------------------------------------------------------------------------- -inst_muldiv: muldiv - PORT MAP - ( - rst => rst, - clk => clk, - hilo_we => EX_stage.ctrl.mul_hilo_we, - din_hi => EX_stage.reg_a, - din_lo => EX_stage.reg_b, - mul_divn => EX_stage.ctrl.mul_mul_divn, - start => EX_stage.ctrl.mul_start, - s_un => EX_stage.ctrl.mul_s_un, - hilo_sel => EX_stage.ctrl.mul_hilo_sel, - busy => mul_busy, - dout => mul_result - ); - --------------------------------------------------------------------------- --- IF stage --------------------------------------------------------------------------- - imem_addr <= pc.curr; - - pipe_rst <= stage_rst(0); - -proc_stage_reset: - process(clk_1) - begin - if rising_edge(clk_1) then - if rst = '1' then - stage_rst <= (others => '1'); - else - stage_rst <= stage_rst(stage_rst'left-1 downto 0) & '0'; - end if; - end if; - end process; - -proc_stage_pc: - process(pc) - begin - if pc.branch_take = '1' then - pc.curr <= pc.pc_branch after 2 ns; - else - pc.curr <= pc.nxt after 2 ns; - end if; - end process; - -proc_stage_pc_branch: - process(clk_1) - begin - if rising_edge(clk_1) then - if sdu.ID_stall = '0' then - pc.pc_branch <= pc.curr + ID_stage.bimm18; - end if; - end if; - end process; - -proc_stage_branch_ce: - process(clk_1) - begin - if rising_edge(clk_1) then - if pipe_rst = '1' then - branch_ce <= '1'; - else - branch_ce <= c0_ctrl_in.exc_pending; - if sdu.ID_stall = '0' and c0_ctrl_in.exc_inject = '0' then - branch_ce <= '1'; - end if; - end if; - end if; - end process; - -proc_stage_pc_next: - process(clk_1) - begin - if rising_edge(clk_1) then - if c0_ctrl_in.exc_inject = '1' then - pc.nxt <= c0_ctrl_in.exc_vec; - elsif sdu.ID_stall = '0' then - pc.last <= pc.curr; - if ID_stage.ctrl.jump = '1' then - pc.nxt <= ID_stage.jimm32; - elsif ID_stage.ctrl.jump_long = '1' then - pc.nxt <= ID_stage.reg_a; - else - pc.nxt <= pc.curr + 4; - end if; - end if; - end if; - end process; - -proc_stage_branch: - process(clk_2) - begin - if rising_edge(clk_2) and branch_ce = '1' then - pc.branch_take <= '0'; - if EX_stage.ctrl.branch = '1' then - - case EX_stage.ctrl.bc_src is - - when bc_eq_ne => - pc.branch_take <= EX_stage.ctrl.bc_not xor bcu_flags.eq; - - when bc_lez_gtz => - pc.branch_take <= EX_stage.ctrl.bc_not xor (bcu_flags.eq or bcu_flags.ltz); - - when bc_ltz_gez => - pc.branch_take <= EX_stage.ctrl.bc_not xor bcu_flags.ltz; - - when others => null; - end case; - end if; - end if; - end process; - --------------------------------------------------------------------------- --- ID stage --------------------------------------------------------------------------- - ID_stage.IR <= to_01(imem_data); - ID_stage.pcn <= pc.curr; - ID_stage.op <= decode_op(ID_stage.IR); - ID_stage.jimm32 <= extract_jimm32(ID_stage.IR, ID_stage.pcn); - ID_stage.bimm18 <= extract_bimm18(ID_stage.IR, ID_stage.pcn); - ID_stage.shamt <= extract_shamt(ID_stage.IR); - ID_stage.reg_a_rptr <= extract_rs(ID_stage.IR); - ID_stage.reg_b_rptr <= extract_rt(ID_stage.IR); - ID_stage.ctrl <= opcode_ctrl_lines(ID_stage.IR) when sdu.ID_nop = '0' else ctrl_lines_default; - ID_stage.reg_write <= ID_stage.ctrl.reg_write; - ID_stage.epc <= pc.last; - ID_stage.exc <= event_is_active(ID_stage.events); -- Todo: works - ID_stage.nop <= sdu.ID_nop; - -proc_ID_except: - process(ID_stage, c0_ctrl_in, pc) - begin - ID_stage.events <= events_clr; - ID_stage.events.inst_load_err <= not c0_ctrl_in.exc_pending and (pc.nxt(1) or pc.nxt(0)); - ID_stage.events.inst_priv_addr <= not c0_ctrl_in.exc_pending and (pc.nxt(word_t'left) and c0_ctrl_in.user_mode); - end process; - -proc_stage_hdu: - process(ID_stage, EX_stage, MEM_stage, WB_stage) - variable read_a, read_b : boolean; - variable raw_a_EX, raw_a_MEM, raw_a_WB : boolean; - variable raw_b_EX, raw_b_MEM, raw_b_WB : boolean; - variable reg_ptr_a : reg_ptr_t; - variable reg_ptr_b : reg_ptr_t; - begin - - reg_ptr_a := ID_stage.reg_a_rptr; - reg_ptr_b := ID_stage.reg_b_rptr; - raw_a_EX := reg_ptr_a = EX_stage.reg_wptr and EX_stage.wreg_we = '1'; - raw_a_MEM := reg_ptr_a = MEM_stage.reg_wptr and MEM_stage.wreg_we = '1'; - raw_a_WB := reg_ptr_a = WB_stage.reg_wptr and WB_stage.wreg_we = '1'; - raw_b_EX := reg_ptr_b = EX_stage.reg_wptr and EX_stage.wreg_we = '1'; - raw_b_MEM := reg_ptr_b = MEM_stage.reg_wptr and MEM_stage.wreg_we = '1'; - raw_b_WB := reg_ptr_b = WB_stage.reg_wptr and WB_stage.wreg_we = '1'; - - hdu.alu_fwd_a_ex <= raw_a_EX after 1 ns; - hdu.alu_fwd_a_mem <= raw_a_MEM after 1 ns; - hdu.alu_fwd_a_wb <= raw_a_WB after 1 ns; - hdu.alu_fwd_b_ex <= raw_b_EX after 1 ns; - hdu.alu_fwd_b_mem <= raw_b_MEM after 1 ns; - hdu.alu_fwd_b_wb <= raw_b_WB after 1 ns; - - end process; - -proc_stage_fwd_a: - process(reg_a, hdu, EX_stage, MEM_stage, WB_stage) - variable data : word_t; - begin - data := reg_a; - if hdu.alu_fwd_a_ex then - data := EX_stage.result; - elsif hdu.alu_fwd_a_mem then - data := MEM_stage.data; - elsif hdu.alu_fwd_a_wb then - data := WB_stage.data; - end if; - - for i in 0 to 31 loop - if data(i) = '1' then - ID_stage.reg_a(i) <= '1' after 2 ns; - else - ID_stage.reg_a(i) <= '0' after 2 ns; - end if; - end loop; - - end process; - -proc_stage_fwd_b: - process(reg_b, hdu, EX_stage, MEM_stage, WB_stage) - variable data : word_t; - begin - data := reg_b; - if hdu.alu_fwd_b_ex then - data := EX_stage.result; - elsif hdu.alu_fwd_b_mem then - data := MEM_stage.data; - elsif hdu.alu_fwd_b_wb then - data := WB_stage.data; - end if; - - for i in 0 to 31 loop - if data(i) = '1' then - ID_stage.reg_b(i) <= '1' after 2 ns; - else - ID_stage.reg_b(i) <= '0' after 2 ns; - end if; - end loop; - - end process; - -proc_imm_mux: - process(ID_stage) - variable data : word_t; - begin - data := extract_uimm16(ID_stage.IR); - - case ID_stage.ctrl.imm_src is - - when src_imm32 => - data := extract_simm32(ID_stage.IR); - - when src_imm16 => - data := extract_uimm16(ID_stage.IR); - - when src_imm16_high => - data := ID_stage.IR(word_t'length/2-1 downto 0) & (word_t'length/2-1 downto 0 => '0'); - - when others => null; - - end case; - - ID_stage.imm <= data after 2 ns; - - end process; - --------------------------------------------------------------------------- -inst_reg_dual: reg_dual - GENERIC MAP - ( - addr_width => reg_ptr_t'length, - data_width => word_t'length - ) - PORT MAP - ( - clk_w => clk_1, - we => WB_stage.wreg_we, - en => '1', - wptr => WB_stage.reg_wptr, - din => WB_stage.data, - rptr_a => ID_stage.reg_a_rptr, - rptr_b => ID_stage.reg_b_rptr, - dout_a => reg_a, - dout_b => reg_b - ); - --------------------------------------------------------------------------- --- EX stage --------------------------------------------------------------------------- - EX_stage.reg_a_rptr <= extract_rs(EX_stage.IR); - EX_stage.reg_b_rptr <= extract_rt(EX_stage.IR); - EX_stage.result <= alu_result when EX_stage.ctrl.mul_access = '0' else mul_result; - -proc_stage_ID_EX_1: - process(clk_1) - begin - if rising_edge(clk_1) then - if stage_rst(1) = '1' then - EX_stage.op <= op_nop; - EX_stage.IR <= (others => '0'); - EX_stage.ctrl <= ctrl_lines_default; - EX_stage.reg_write <= '0'; - EX_stage.epc <= (others => '0'); - EX_stage.pcn <= (others => '0'); - EX_stage.events_in <= events_clr; - elsif sdu.EX_stall = '0' then - EX_stage.reg_a <= ID_stage.reg_a; - EX_stage.reg_b <= ID_stage.reg_b; - EX_stage.events_in <= ID_stage.events; - EX_stage.op <= ID_stage.op; - EX_stage.ctrl <= ID_stage.ctrl; - EX_stage.reg_write <= ID_stage.reg_write; - EX_stage.nop <= sdu.EX_nop; - EX_stage.IR <= ID_stage.IR; - EX_stage.pcn <= ID_stage.pcn; - EX_stage.epc <= ID_stage.epc; - if sdu.EX_nop = '1' then - EX_stage.op <= op_nop; - EX_stage.IR <= (others => '0'); - EX_stage.ctrl <= ctrl_lines_default; - EX_stage.reg_write <= '0'; - end if; - end if; - end if; - end process; - -proc_stage_EX_instr_except: - process(EX_stage) - begin - EX_events_instr <= events_clr; - EX_events_instr.illegal <= EX_stage.ctrl.exc_illegal; - EX_events_instr.break <= EX_stage.ctrl.exc_break; - EX_events_instr.syscall <= EX_stage.ctrl.exc_syscall; - end process; - -proc_stage_EX_alu_except: - process(EX_stage) - begin - EX_events_alu <= events_clr; - if EX_stage.ctrl.alu_exc_en = '1' then - if EX_stage.alu_flags.ovf = '1' then - EX_events_alu.alu_ovf <= '1'; - end if; - if EX_stage.alu_flags.uvf = '1' then - EX_events_alu.alu_uvf <= '1'; - end if; - end if; - end process; - - vaddr <= ID_stage.reg_a + extract_simm32(ID_stage.IR); - -proc_stage_EX_mem_except: - process(clk_1) - begin - if rising_edge(clk_1) then - if pipe_rst = '1' then - dmem_en <= '0'; - elsif sdu.EX_stall = '0' then - EX_events_mem <= events_clr; - dmem_en <= '0'; - if ID_stage.ctrl.dmem_en = '1' then - dmem_en <= '1'; - if ID_stage.ctrl.except_en = '1' then - if ID_stage.ctrl.word2_en = '1' then - if vaddr(0) = '1' then - EX_events_mem.data_load_err <= not ID_stage.ctrl.dmem_we; - EX_events_mem.data_store_err <= ID_stage.ctrl.dmem_we; - dmem_en <= '0'; - end if; - elsif vaddr(1 downto 0) /= "00" then - EX_events_mem.data_load_err <= not ID_stage.ctrl.dmem_we; - EX_events_mem.data_store_err <= ID_stage.ctrl.dmem_we; - dmem_en <= '0'; - end if; - end if; - end if; - end if; - end if; - end process; - -proc_stage_DMEM_ADDR: - process(clk_1) - begin - if rising_edge(clk_1) then - if sdu.EX_stall = '0' then - EX_stage.va <= vaddr; - if c0_ctrl_in.EB = '1' then - if ID_stage.ctrl.word2_en = '0' then - EX_stage.pa_off <= not vaddr(1 downto 0); - else - EX_stage.pa_off <= not vaddr(1) & vaddr(0); - end if; - else - EX_stage.pa_off <= vaddr(1 downto 0); - end if; - end if; - end if; - end process; - dmem_src <= cop_din when EX_stage.ctrl.cop_instr_en = '1' else EX_stage.reg_b; - dmem_be <= store_be(EX_stage.pa_off, EX_stage.ctrl.dmem_en, EX_stage.ctrl.word2_en, EX_stage.ctrl.word4_en, EX_stage.ctrl.align_left, EX_stage.ctrl.shift_byp) after 1 ns; - dmem_we <= EX_stage.ctrl.dmem_we; - dmem_dout <= store_shift(dmem_src, EX_stage.pa_off, EX_stage.ctrl.shift_offset, EX_stage.ctrl.shift_byp) after 1ns; - dmem_addr <= EX_stage.va; - EX_stage.events <= EX_events_instr or EX_events_mem or EX_events_alu or EX_stage.events_in; - EX_stage.exc <= event_is_active(EX_stage.events); - --------------------------------------------------------------------------- -proc_wptr_mux: - process(EX_stage) - variable opclass : opcode_t; - variable reg_wptr : reg_ptr_t; - begin - - opclass := extract_opc(EX_stage.IR); - case opclass is - when "000000" => - reg_wptr := extract_rd(EX_stage.IR); - when others => - reg_wptr := extract_rt(EX_stage.IR); - end case; - - EX_stage.wreg_we <= EX_stage.reg_write after 1 ns; - if reg_wptr = "00000" then - EX_stage.wreg_we <= '0' after 1 ns; - end if; - - EX_stage.reg_wptr <= reg_wptr after 1 ns; - case EX_stage.ctrl.wptr_srcsel is - when wptr_src_imm => - EX_stage.reg_wptr <= reg_wptr after 1 ns; - - when wptr_src_const => - EX_stage.reg_wptr <= to_unsigned(31, reg_ptr_t'length) after 1 ns; - EX_stage.wreg_we <= '1' after 1 ns; - - when others => null; - end case; - - end process; - --------------------------------------------------------------------------- -proc_stage_bcu_op: - process(clk_1) - begin - if rising_edge(clk_1) and sdu.EX_stall = '0' then - bcu_op_a <= ID_stage.reg_a; - bcu_op_b <= ID_stage.reg_b; - end if; - end process; - -EX_stage.alu_op1 <= EX_stage.reg_a; - -alu_op2_mux: - process(clk_1) - variable data : word_t; - begin - - if rising_edge(clk_1) and sdu.EX_stall = '0' then - data := ID_stage.reg_b; - - case ID_stage.ctrl.alu.op2_src is - - when alu_src_reg => - data := ID_stage.reg_b; - - when alu_src_imm => - data := ID_stage.imm; - - when others => null; - - end case; - - EX_stage.alu_op2 <= data; - end if; - - end process; - -shifter_sa_mux: - process(clk_1) - variable data : shamt_t; - variable data_inv : shamt_t; - - begin - if rising_edge(clk_1) and sdu.EX_stall = '0' then - data := ID_stage.reg_a(4 downto 0); - case ID_stage.ctrl.shamt2_srcsel is - - when sa_src_reg => - data := ID_stage.reg_a(4 downto 0); - - when sa_src_imm => - data := ID_stage.shamt; - - when others => null; - - end case; - data_inv := not data + 1; - if ID_stage.ctrl.alu.shift_right = '0' then - EX_stage.shift_ctrl.shamt_rnd <= data_inv after 2 ns; - else - EX_stage.shift_ctrl.shamt_rnd <= data after 2 ns; - end if; - EX_stage.shift_ctrl.shamt_nrm <= data after 1 ns; - EX_stage.shift_ctrl.shift_right <= ID_stage.ctrl.alu.shift_right; - EX_stage.shift_ctrl.shift_arith <= ID_stage.ctrl.alu.shift_arith; - end if; - - end process; - --------------------------------------------------------------------------- -inst_shifter: shifter - GENERIC MAP - ( - data_width => word_t'length - ) - PORT MAP - ( - shift_ctrl => EX_stage.shift_ctrl, - din => EX_stage.reg_b, - dout => EX_stage.alu_op2_s - ); - -inst_alu: alu - GENERIC MAP - ( - data_width => word_t'length - ) - PORT MAP - ( - op1_in => EX_stage.alu_op1, - op2_in => EX_stage.alu_op2, - op2_shifted => EX_stage.alu_op2_s, - ctrl => EX_stage.ctrl.alu, - result => alu_result, - flags => EX_stage.alu_flags - ); - -inst_bcu: bcu - GENERIC MAP - ( - data_width => word_t'length - ) - PORT MAP - ( - op1_in => bcu_op_a, - op2_in => bcu_op_b, - flags => bcu_flags - ); - --------------------------------------------------------------------------- --- MEM stage --------------------------------------------------------------------------- -proc_stage_MEM_n: - process(clk_1) - begin - if rising_edge(clk_1) then - if stage_rst(2) = '1' then - MEM_stage.op <= op_nop; - MEM_stage.wreg_we <= '0'; - MEM_stage.ctrl <= ctrl_lines_default; - MEM_stage.pa_off <= (others => '0'); - MEM_stage.events_in <= events_clr; - elsif sdu.MEM_stall = '0' then - MEM_stage.events_in <= EX_stage.events; - MEM_stage.op <= EX_stage.op; - MEM_stage.wreg_we <= EX_stage.wreg_we; - MEM_stage.ctrl <= EX_stage.ctrl; - if EX_stage.ctrl.dmem_en = '1' then - MEM_stage.va <= EX_stage.va; - end if; - MEM_stage.pa_off <= EX_stage.pa_off; - MEM_stage.reg_wptr <= EX_stage.reg_wptr; - MEM_stage.nop <= sdu.MEM_nop; - if MEM_stage.reg_wptr = EX_stage.reg_wptr then - if (EX_stage.ctrl.dmem_en and MEM_stage.ctrl.dmem_en) = '1' then - MEM_stage.ex_result <= MEM_stage.data; - end if; - else - MEM_stage.ex_result <= EX_stage.reg_b; - end if; - if EX_stage.ctrl.cop_instr_en = '1' then - if EX_stage.ctrl.cop_read = '1' then - MEM_stage.ex_result <= cop_din; - end if; - elsif EX_stage.ctrl.dmem_en = '0' then - MEM_stage.ex_result <= EX_stage.result; - end if; - if sdu.MEM_nop = '1' then - MEM_stage.op <= op_nop; - MEM_stage.wreg_we <= '0'; - MEM_stage.ctrl <= ctrl_lines_default; - else - MEM_stage.pcn <= EX_stage.pcn; - MEM_stage.epc <= EX_stage.epc; - end if; - end if; - end if; - end process; - -proc_stage_MEM_mux: - process(MEM_stage, dmem_din) - variable temp1 : word_t; - variable temp2 : word_t; - variable data : word_t; - variable be : unsigned(3 downto 0); - begin - data := MEM_stage.ex_result; - if MEM_stage.ctrl.reg_link = '1' then - data := MEM_stage.epc + 8; - elsif MEM_stage.ctrl.dmem_en = '1' then - temp1 := load_shift(dmem_din, MEM_stage.pa_off, MEM_stage.ctrl.shift_offset, MEM_stage.ctrl.shift_byp); - temp2 := load_sign_ext(temp1, MEM_stage.ctrl.sign_ext_byp, MEM_stage.ctrl.load_signed, MEM_stage.ctrl.word2_en, MEM_stage.ctrl.word4_en); - be := load_be(MEM_stage.pa_off, MEM_stage.ctrl.align_left, MEM_stage.ctrl.byte_en_byp); - if be(0) = '1' then - data(7 downto 0) := temp2(7 downto 0); - end if; - if be(1) = '1' then - data(15 downto 8) := temp2(15 downto 8); - end if; - if be(2) = '1' then - data(23 downto 16) := temp2(23 downto 16); - end if; - if be(3) = '1' then - data(31 downto 24) := temp2(31 downto 24); - end if; - end if; - MEM_stage.data <= data after 1 ns; - - end process; - -proc_stage_MEM_except: - process(MEM_stage, c0_ctrl_in) - begin - MEM_stage.events <= MEM_stage.events_in; - MEM_stage.events.Int <= c0_ctrl_in.int; - MEM_stage.events.NMI <= c0_ctrl_in.NMI; - end process; - - MEM_stage.exc <= event_is_active(MEM_stage.events); - --------------------------------------------------------------------------- --- WB stage --------------------------------------------------------------------------- -proc_stage_WB_p: - process(clk_1) - begin - if rising_edge(clk_1) then - if stage_rst(3) = '1' then - WB_stage.op <= op_nop; - WB_stage.wreg_we <= '1'; - WB_stage.reg_wptr <= (others => '0'); - WB_stage.data <= (others => '0'); - WB_stage.events <= events_clr; - elsif sdu.WB_stall = '0' then - WB_stage.op <= MEM_stage.op; - WB_stage.wreg_we <= MEM_stage.wreg_we; - WB_stage.reg_wptr <= MEM_stage.reg_wptr; - WB_stage.data <= MEM_stage.data; - WB_stage.exc <= '0'; - if sdu.stall_all = '0' then - WB_stage.exc <= MEM_stage.exc; - if MEM_stage.exc = '1' then - WB_stage.events <= MEM_stage.events; - end if; - end if; - WB_stage.nop <= sdu.WB_nop; - if sdu.WB_nop = '1' then - WB_stage.op <= op_nop; - WB_stage.wreg_we <= '0'; - else - WB_stage.bd <= MEM_stage.ctrl.branch or MEM_stage.ctrl.jump or MEM_stage.ctrl.jump_long; -- Todo: works - end if; - end if; - end if; - end process; - --------------------------------------------------------------------------- -end Behavioral; diff --git a/lib/CPUs/MIPS/src/core/mips_reg.vhd b/lib/CPUs/MIPS/src/core/mips_reg.vhd deleted file mode 100644 index e7b72da..0000000 --- a/lib/CPUs/MIPS/src/core/mips_reg.vhd +++ /dev/null @@ -1,72 +0,0 @@ --------------------------------------------------------------------------- --- Project: JIPS, a portable 32-bit RISC CPU written in VHDL --- This file: On-Chip work registers --- --- Copyright (C) 2008 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.mips_types.all; - -entity reg_dual is - Generic - ( - addr_width : integer := 3; - data_width : integer := 8 - ); - Port ( - clk_w : in STD_LOGIC; - we : in STD_LOGIC; - en : in STD_LOGIC; - wptr : in unsigned (addr_width-1 downto 0); - din : in unsigned (data_width-1 downto 0); - rptr_a : in unsigned (addr_width-1 downto 0); - rptr_b : in unsigned (addr_width-1 downto 0); - dout_a : out unsigned (data_width-1 downto 0); - dout_b : out unsigned (data_width-1 downto 0) - ); -end reg_dual; - -architecture Behavioral of reg_dual is - - constant depth : integer := 2**addr_width; - type mem_t is array (0 to depth-1) of unsigned (data_width-1 downto 0); - - signal reg_mem : mem_t; - -begin - -reg_in: - process(clk_w) - begin - if rising_edge(clk_w) then - if we = '1' and en = '1' then - reg_mem(to_integer(wptr)) <= din; - end if; - end if; - end process; - - dout_a <= reg_mem(to_integer(rptr_a)) after 2 ns; - dout_b <= reg_mem(to_integer(rptr_b)) after 2 ns; - -end Behavioral; - diff --git a/lib/CPUs/MIPS/src/core/mips_shifter.vhd b/lib/CPUs/MIPS/src/core/mips_shifter.vhd deleted file mode 100644 index 7f047ec..0000000 --- a/lib/CPUs/MIPS/src/core/mips_shifter.vhd +++ /dev/null @@ -1,117 +0,0 @@ --------------------------------------------------------------------------- --- Project: JIPS, a portable 32-bit RISC CPU written in VHDL --- This file: The shifter unit --- --- Copyright (C) 2008 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.mips_types.all; - -entity shifter is - Generic - ( - data_width : integer := 8 - ); - Port - ( - shift_ctrl : in shift_ctrl_t; - din : in unsigned (data_width-1 downto 0); - dout : out unsigned (data_width-1 downto 0) - ); -end shifter; - -architecture Behavioral of shifter is - - subtype word_t is unsigned(data_width-1 downto 0); - type word_array_t is array (0 to 5) of word_t; - - signal rot_data : word_array_t; - signal sa_rnd : unsigned (4 downto 0); - signal fill : std_logic; - - type fill_mask_rom_t is array (0 to 2*data_width-1) of unsigned(data_width-1 downto 0); --------------------------------------------------------------------------- -function gen_fill_mask_rom(data_width : natural) return fill_mask_rom_t is - variable result : fill_mask_rom_t; - begin - result(0) := (data_width-1 downto 0 => '0'); - for i in 1 to data_width-1 loop - result(i) := (data_width-1-i downto 0 => '0') & (i-1 downto 0 => '1'); - end loop; - result(data_width) := (data_width-1 downto 0 => '0'); - for i in 1 to data_width-1 loop - result(data_width+i) := (i-1 downto 0 => '1') & (data_width-1-i downto 0 => '0'); - end loop; - return result; - -end gen_fill_mask_rom; - -function rot_stage(x : unsigned; en : std_logic; stage_num : natural) return unsigned is - variable result : unsigned(x'range); - constant sa : natural := 2**stage_num; - begin - if en = '1' then - result := x(sa-1 downto 0) & x(x'left downto sa); - else - result := x; - end if; - return result; - -end rot_stage; - - constant fill_mask_rom : fill_mask_rom_t := gen_fill_mask_rom(data_width); - signal fill_mask : unsigned(data_width-1 downto 0); - signal fill_mask_addr : unsigned(5 downto 0); - signal dout_filled : unsigned (data_width-1 downto 0); - --------------------------------------------------------------------------- -begin - - rot_data(0) <= din; - -gen_rotate_right: - for stage in 0 to 4 generate - begin - rot_data(stage+1) <= rot_stage(rot_data(stage), sa_rnd(stage), stage); - end generate; - - sa_rnd <= shift_ctrl.shamt_rnd; - fill <= shift_ctrl.shift_arith and din(data_width-1); - fill_mask_addr <= shift_ctrl.shift_right & shift_ctrl.shamt_nrm; - fill_mask <= fill_mask_rom(to_integer(fill_mask_addr)); - -proc_fill_neu: - process(fill_mask, fill, rot_data(5)) - begin - if fill = '1' then - dout_filled <= rot_data(5) or fill_mask; - else - dout_filled <= rot_data(5) and not fill_mask; - end if; - end process; - - dout <= dout_filled after 5 ns; - --------------------------------------------------------------------------- -end Behavioral; - diff --git a/lib/CPUs/MIPS/src/core/mips_top.vhd b/lib/CPUs/MIPS/src/core/mips_top.vhd deleted file mode 100644 index 5c90a86..0000000 --- a/lib/CPUs/MIPS/src/core/mips_top.vhd +++ /dev/null @@ -1,308 +0,0 @@ --------------------------------------------------------------------------- --- Project: JIPS, a portable 32-bit RISC CPU written in VHDL --- This file: JIPS top file --- --- Copyright (C) 2008 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -library work; -use work.mips_types.all; - -entity mips_top is - Generic - ( - icache_size : natural := 8192; -- words - icache_line : natural := 8; -- words - dcache_size : natural := 4096; -- words - dcache_line : natural := 8 -- words - ); - Port - ( - debug : out unsigned(1 downto 0); - eb : in STD_LOGIC; - nmi : in STD_LOGIC; - cpu_clk : in STD_LOGIC; - RST_I : in STD_LOGIC; - CLK_I : in STD_LOGIC; - ACK_I : in STD_LOGIC; - SRDY_I : in STD_LOGIC; - ADDR_O : out unsigned(31 downto 0); - DAT_I : in unsigned(31 downto 0); - DAT_O : out unsigned(31 downto 0); - WE_O : out STD_LOGIC; - SEL_O : out unsigned(3 downto 0); - CYC_O : out STD_LOGIC; - STB_O : out STD_LOGIC; - MRDY_O : out STD_LOGIC; - INT : in unsigned (5 downto 0) - ); - -end mips_top; - -architecture rtl of mips_top is - --------------------------------------------------------------------------- --- Pipeline --------------------------------------------------------------------------- - COMPONENT pipeline is - Port - ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - ce : in STD_LOGIC; - imem_err : in STD_LOGIC; - imem_rdy : in STD_LOGIC; - imem_en : out STD_LOGIC; - imem_addr : out word_t; - imem_data : in word_t; - dmem_err : in STD_LOGIC; - dmem_rdy : in STD_LOGIC; - dmem_en : out STD_LOGIC; - dmem_we : out STD_LOGIC; - dmem_be : out unsigned(3 downto 0); - dmem_addr : out word_t; - dmem_din : in word_t; - dmem_dout : out word_t; - cop_ir : out word_t; - cop_ir_en : out STD_LOGIC; - cop_din : in word_t; - cop_dout : out word_t; - c0_ctrl_out : out cop0_ctrl_in_t; - c0_ctrl_in : in cop0_ctrl_out_t - ); - END COMPONENT; - signal imem_err : std_logic; - signal imem_rdy : std_logic; - signal imem_en : std_logic; - signal imem_addr : word_t; - signal imem_din : word_t; - signal dmem_err : std_logic; - signal dmem_rdy : std_logic; - signal dmem_en : std_logic; - signal dmem_we : std_logic; - signal dmem_addr : word_t; - signal dmem_dout : word_t; - signal dmem_din : word_t; - signal dmem_be : unsigned(3 downto 0); - - signal biu_rst : STD_LOGIC; - signal cpu_rst : STD_LOGIC; - signal cpu_run : STD_LOGIC; - - signal pipe_cop_ir : word_t; - signal pipe_cop_ir_en : STD_LOGIC; - signal pipe_cop_din : word_t; - signal pipe_cop_dout : word_t; - signal pipe_c0_ctrl_out : cop0_ctrl_in_t; - signal pipe_c0_ctrl_in : cop0_ctrl_out_t; - --------------------------------------------------------------------------- --- Coprocessor --------------------------------------------------------------------------- - COMPONENT cop is - GENERIC - ( - icache_size : natural; - icache_line : natural; - dcache_size : natural; - dcache_line : natural - ); - Port - ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - nmi : in STD_LOGIC; - eb : in STD_LOGIC; - int : in unsigned (5 downto 0); - ir_en : in STD_LOGIC; - ir : in word_t; - ctrl_in : in cop0_ctrl_in_t; - ctrl_out : out cop0_ctrl_out_t; - din : in word_t; - dout : out word_t - ); - END COMPONENT; - --------------------------------------------------------------------------- --- Bus Interface Unit --------------------------------------------------------------------------- - COMPONENT biu - GENERIC - ( - icache_size : natural; - icache_line : natural; - dcache_size : natural; - dcache_line : natural - ); - PORT - ( - RST_I : in STD_LOGIC; - CLK_I : in STD_LOGIC; - ACK_I : in STD_LOGIC; - SRDY_I : in STD_LOGIC; - ADDR_O : out unsigned(31 downto 0); - DAT_I : in unsigned(31 downto 0); - DAT_O : out unsigned(31 downto 0); - WE_O : out STD_LOGIC; - SEL_O : out unsigned(3 downto 0); - CYC_O : out STD_LOGIC; - STB_O : out STD_LOGIC; - MRDY_O : out STD_LOGIC; - cop0_ctrl_in : in cop0_ctrl_out_t; - cpu_clk : in STD_LOGIC; - cpu_imem_err : out STD_LOGIC; - cpu_imem_rdy : out STD_LOGIC; - cpu_imem_en : in STD_LOGIC; - cpu_imem_addr : in word_t; - cpu_imem_din : out word_t; - cpu_dmem_err : out STD_LOGIC; - cpu_dmem_rdy : out STD_LOGIC; - cpu_dmem_en : in STD_LOGIC; - cpu_dmem_we : in STD_LOGIC; - cpu_dmem_be : in unsigned(3 downto 0); - cpu_dmem_dout : in word_t; - cpu_dmem_din : out word_t; - cpu_dmem_addr : in word_t - ); - END COMPONENT; - -begin - -------------------------------------------------------------------- - debug(0) <= imem_err; - debug(1) <= dmem_err; - - process(CLK_I) - variable reset_delay : unsigned (31 downto 0); - begin - if rising_edge(CLK_I) then - if RST_I = '1' then - reset_delay := (others => '0'); - biu_rst <= '1'; - cpu_rst <= '1'; - cpu_run <= '0'; - else - reset_delay := reset_delay(reset_delay'left-1 downto 0) & '1'; - if reset_delay(20) = '1' then - biu_rst <= '0'; - end if; - if reset_delay(31) = '1' then - cpu_rst <= '0'; - end if; - if reset_delay(16) = '1' then - cpu_run <= '1'; - end if; - end if; - end if; - end process; - -inst_pipeline: pipeline - PORT MAP - ( - rst => cpu_rst, - clk => cpu_clk, - ce => cpu_run, - imem_err => imem_err, - imem_rdy => imem_rdy, - imem_en => imem_en, - imem_addr => imem_addr, - imem_data => imem_din, - dmem_err => dmem_err, - dmem_rdy => dmem_rdy, - dmem_en => dmem_en, - dmem_we => dmem_we, - dmem_be => dmem_be, - dmem_addr => dmem_addr, - dmem_din => dmem_din, - dmem_dout => dmem_dout, - cop_ir => pipe_cop_ir, - cop_ir_en => pipe_cop_ir_en, - cop_din => pipe_cop_din, - cop_dout => pipe_cop_dout, - c0_ctrl_out => pipe_c0_ctrl_out, - c0_ctrl_in => pipe_c0_ctrl_in - ); - -inst_cop: cop - GENERIC MAP - ( - icache_size => icache_size, -- words - icache_line => icache_line, -- words - dcache_size => dcache_size, -- words - dcache_line => dcache_line -- words - ) - PORT MAP - ( - rst => cpu_rst, - clk => cpu_clk, - nmi => nmi, - eb => eb, - int => INT, - ir_en => pipe_cop_ir_en, - ir => pipe_cop_ir, - ctrl_in => pipe_c0_ctrl_out, - ctrl_out => pipe_c0_ctrl_in, - dout => pipe_cop_din, - din => pipe_cop_dout - ); - -inst_biu: biu - GENERIC MAP - ( - icache_size => icache_size, -- words - icache_line => icache_line, -- words - dcache_size => dcache_size, -- words - dcache_line => dcache_line -- words - ) - PORT MAP - ( - RST_I => biu_rst, - CLK_I => CLK_I, - ACK_I => ACK_I, - SRDY_I => SRDY_I, - ADDR_O => ADDR_O, - DAT_I => DAT_I, - DAT_O => DAT_O, - WE_O => WE_O, - SEL_O => SEL_O, - CYC_O => CYC_O, - STB_O => STB_O, - MRDY_O => MRDY_O, - cop0_ctrl_in => pipe_c0_ctrl_in, - cpu_clk => cpu_clk, - cpu_imem_err => imem_err, - cpu_imem_rdy => imem_rdy, - cpu_imem_en => imem_en, - cpu_imem_addr => imem_addr, - cpu_imem_din => imem_din, - cpu_dmem_err => dmem_err, - cpu_dmem_rdy => dmem_rdy, - cpu_dmem_en => dmem_en, - cpu_dmem_we => dmem_we, - cpu_dmem_be => dmem_be, - cpu_dmem_addr => dmem_addr, - cpu_dmem_din => dmem_din, - cpu_dmem_dout => dmem_dout - ); - -end rtl; diff --git a/lib/CPUs/MIPS/src/core/mips_types.vhd b/lib/CPUs/MIPS/src/core/mips_types.vhd deleted file mode 100644 index d861c41..0000000 --- a/lib/CPUs/MIPS/src/core/mips_types.vhd +++ /dev/null @@ -1,673 +0,0 @@ --------------------------------------------------------------------------- --- Project: JIPS, a portable 32-bit RISC CPU written in VHDL --- This file: Types, constants and functions for JIPS --- --- Copyright (C) 2008 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; -use IEEE.MATH_REAL.ALL; - --------------------------------------------------------------------------- -package mips_types is - - -- Revision of the CPU - constant REVISION : integer := 13; - constant WORD_WIDTH : integer := 32; - - --Types - subtype instr_name_t is string(1 to 12); - type instr_name_array_t is array (0 to 63) of instr_name_t; - subtype opcode_t is unsigned (5 downto 0); - subtype word_t is unsigned (WORD_WIDTH-1 downto 0); - subtype reg_ptr_t is unsigned (4 downto 0); - subtype shamt_t is unsigned(4 downto 0); - subtype sa_t is natural range 0 to 63; - subtype func_t is unsigned(5 downto 0); - - type chip_debug_t is record - imem_err : std_logic; - dmem_err : std_logic; - end record; - - type op_t is - ( - op_illegal, - op_nop, - op_sll, - op_srl, - op_sra, - op_sllv, - op_srlv, - op_srav, - op_jr, - op_jalr, - op_syscall, - op_break, - op_mfhi, - op_mthi, - op_mflo, - op_mtlo, - op_mult, - op_multu, - op_div, - op_divu, - op_add, - op_addu, - op_sub, - op_subu, - op_and, - op_or, - op_xor, - op_nor, - op_slt, - op_sltu, - op_bltz, - op_bgez, - op_bltzal, - op_bgezal, - op_j, - op_jal, - op_beq, - op_bne, - op_blez, - op_bgtz, - op_addi, - op_addiu, - op_slti, - op_sltiu, - op_andi, - op_ori, - op_xori, - op_lui, - op_lb, - op_lh, - op_lwl, - op_lw, - op_lbu, - op_lhu, - op_lwr, - op_sb, - op_sh, - op_swl, - op_sw, - op_swr, - op_cop0, - op_cop1, - op_cop2, - op_cop3, - op_mfc0, - op_cfc0, - op_mtc0, - op_ctc0, - op_bcf0, - op_bct0, - op_mfc1, - op_cfc1, - op_mtc1, - op_ctc1, - op_bcf1, - op_bct1, - op_mfc2, - op_cfc2, - op_mtc2, - op_ctc2, - op_bcf2, - op_bct2, - op_mfc3, - op_cfc3, - op_mtc3, - op_ctc3, - op_bcf3, - op_bct3, - op_lwc0, - op_lwc1, - op_lwc2, - op_lwc3, - op_swc0, - op_swc1, - op_swc2, - op_swc3 - ); - - attribute ENUM_ENCODING : string; - - type imm_src_t is (src_imm32, src_imm16, src_imm16_high); - type sa_src_t is (sa_src_reg, sa_src_imm); - type alu_src1_t is (alu_src_reg); - type alu_src2_t is (alu_src_reg, alu_src_imm); - type bc_src_t is (bc_eq_ne, bc_lez_gtz, bc_ltz_gez); - type shift_opsel_t is (shift_sll, shift_srl, shift_sra); - type wptr_src_t is (wptr_src_imm, wptr_src_const); - - type pc_t is record - curr : word_t; - last : word_t; - nxt : word_t; - pc_branch : word_t; - branch_take : std_logic; - end record; - - type alu_outsel_t is - ( - alu_adder, - alu_shift2, - alu_and, - alu_or, - alu_xor, - alu_nor, - alu_ltu, - alu_lts - ); - - type sdu_t is record - imem_dep : STD_LOGIC; - dmem_dep : STD_LOGIC; - mul_dep : STD_LOGIC; - ID_nop : STD_LOGIC; - EX_nop : STD_LOGIC; - MEM_nop : STD_LOGIC; - WB_nop : STD_LOGIC; - ID_stall : STD_LOGIC; - EX_stall : STD_LOGIC; - MEM_stall : STD_LOGIC; - WB_stall : STD_LOGIC; - stall_all : STD_LOGIC; - end record; - - type hdu_t is record - alu_fwd_a_ex : boolean; - alu_fwd_a_mem : boolean; - alu_fwd_a_wb : boolean; - alu_fwd_b_ex : boolean; - alu_fwd_b_mem : boolean; - alu_fwd_b_wb : boolean; - end record; - - type alu_flags_t is record - c : STD_LOGIC; - uvf : STD_LOGIC; - ovf : STD_LOGIC; - ltu : STD_LOGIC; - lts : STD_LOGIC; - end record; - - type bcu_flags_t is record - eq : STD_LOGIC; - ltz : STD_LOGIC; - end record; - - type event_t is record - NMI : STD_LOGIC; - Int : STD_LOGIC; - data_load_err : STD_LOGIC; - data_store_err : STD_LOGIC; - inst_load_err : STD_LOGIC; - inst_priv_addr : STD_LOGIC; - alu_ovf : STD_LOGIC; - alu_uvf : STD_LOGIC; - syscall : STD_LOGIC; - break : STD_LOGIC; - illegal : STD_LOGIC; - end record; - - type exc_flags_t is record - Int : STD_LOGIC; - DAdEL : STD_LOGIC; - DAdES : STD_LOGIC; - IAdEL : STD_LOGIC; - IAdEK : STD_LOGIC; - Ov : STD_LOGIC; - Sys : STD_LOGIC; - Bp : STD_LOGIC; - RI : STD_LOGIC; - IBE : STD_LOGIC; - DBE : STD_LOGIC; - end record; - - type except_t is record - act : STD_LOGIC; - epc : word_t; - cause : word_t; - end record; - - type cache_ctrl_t is record - inv_addr : word_t; - inv_at : STD_LOGIC; - inv_all : STD_LOGIC; - end record; - - type cop0_ctrl_in_t is record - sdu : sdu_t; - events : event_t; - bd_wb : STD_LOGIC; - epc_mem : word_t; - epc_wb : word_t; - imem_addr : word_t; - dmem_addr : word_t; - exc_req : STD_LOGIC; - exc_ack : STD_LOGIC; - end record; - - type cop0_ctrl_out_t is record - EB : STD_LOGIC; - exc_inject : STD_LOGIC; - exc_commit : STD_LOGIC; - exc_pending : STD_LOGIC; - exc_exit : STD_LOGIC; - user_mode : STD_LOGIC; - NMI : STD_LOGIC; - int : STD_LOGIC; - exc_vec : word_t; - icache : cache_ctrl_t; - dcache : cache_ctrl_t; - end record; - - type alu_ctrl_t is record - outsel : alu_outsel_t; - add : STD_LOGIC; - shift_right : STD_LOGIC; - shift_arith : STD_LOGIC; - op1_src : alu_src1_t; - op2_src : alu_src2_t; - end record; - - type shift_ctrl_t is record - shamt_nrm : shamt_t; - shamt_rnd : shamt_t; - shift_right : STD_LOGIC; - shift_arith : STD_LOGIC; - end record; - - type ctrl_lines_t is record - branch : STD_LOGIC; - jump_long : STD_LOGIC; - jump : STD_LOGIC; - bc_not : STD_LOGIC; - bc_src : bc_src_t; - imm_src : imm_src_t; - alu : alu_ctrl_t; - reg_write : STD_LOGIC; - reg_link : STD_LOGIC; - dmem_we : STD_LOGIC; - dmem_en : STD_LOGIC; - shamt2_srcsel : sa_src_t; - wptr_srcsel : wptr_src_t; - cop_instr_en : STD_LOGIC; - cop_read : STD_LOGIC; - shift_offset : unsigned(1 downto 0); - shift_byp : STD_LOGIC; - byte_en_byp : STD_LOGIC; - sign_ext_byp : STD_LOGIC; - word4_en : STD_LOGIC; - word2_en : STD_LOGIC; - align_left : STD_LOGIC; - load_signed : STD_LOGIC; - mul_access : STD_LOGIC; - mul_hilo_we : STD_LOGIC; - mul_mul_divn : STD_LOGIC; - mul_start : STD_LOGIC; - mul_s_un : STD_LOGIC; - mul_hilo_sel : STD_LOGIC; - exc_break : STD_LOGIC; - exc_syscall : STD_LOGIC; - exc_illegal : STD_LOGIC; - except_en : STD_LOGIC; - alu_exc_en : STD_LOGIC; - end record; - - type ID_t is record - nop : STD_LOGIC; - exc : std_logic; - IR : word_t; - op : op_t; - pcn : word_t; - epc : word_t; - jimm32 : word_t; - bimm18 : word_t; - imm : word_t; - shamt : shamt_t; - ctrl : ctrl_lines_t; - reg_write : STD_LOGIC; - reg_a_rptr : reg_ptr_t; - reg_b_rptr : reg_ptr_t; - reg_a : word_t; - reg_b : word_t; - events : event_t; - end record; - - type EX_t is record - nop : STD_LOGIC; - exc : std_logic; - IR : word_t; - op : op_t; - pcn : word_t; - epc : word_t; - reg_a : word_t; - reg_b : word_t; - ctrl : ctrl_lines_t; - shift_ctrl : shift_ctrl_t; - alu_op1 : word_t; - alu_op2 : word_t; - alu_op2_s : word_t; - alu_flags : alu_flags_t; - result : word_t; - reg_write : STD_LOGIC; - wreg_we : STD_LOGIC; - reg_wptr : reg_ptr_t; - reg_a_rptr : reg_ptr_t; - reg_b_rptr : reg_ptr_t; - va : word_t; - pa_off : unsigned(1 downto 0); - events_in : event_t; - events : event_t; - end record; - - type MEM_t is record - nop : STD_LOGIC; - exc : std_logic; - op : op_t; - pcn : word_t; - epc : word_t; - ctrl : ctrl_lines_t; - ex_result : word_t; - reg_wptr : reg_ptr_t; - wreg_we : STD_LOGIC; - data : word_t; - va : word_t; - pa_off : unsigned(1 downto 0); - events_in : event_t; - events : event_t; - end record; - - type WB_t is record - nop : STD_LOGIC; - exc : std_logic; - events : event_t; - op : op_t; - reg_wptr : reg_ptr_t; - wreg_we : STD_LOGIC; - data : word_t; - bd : STD_LOGIC; - end record; - - - type rom_special_t is array (0 to 2**func_t'length-1) of ctrl_lines_t; - type rom_regimm_t is array (0 to 2**reg_ptr_t'length-1) of ctrl_lines_t; - type rom_opcode_t is array (0 to 2**opcode_t'length-1) of ctrl_lines_t; - - function store_shift(x : word_t; va, shift_off : unsigned(1 downto 0); bypass : std_logic) return word_t; - function store_be(va : unsigned(1 downto 0); be_src, word2_en, word4_en, align_left, bypass : std_logic) return unsigned; - function load_shift(x : word_t; va, shift_off : unsigned(1 downto 0); bypass : std_logic) return word_t; - function load_be(va : unsigned(1 downto 0); align_left, bypass : std_logic) return unsigned; - function load_sign_ext(x : word_t; bypass, signed, word2_en, word4_en : std_logic) return word_t; - function events_clr return event_t; - function event_is_active(e : event_t) return std_logic; - function "or" (a, b : event_t) return event_t; - - function lg2(x : natural) return natural; - function po2(x : natural) return natural; - -end mips_types; - --------------------------------------------------------------------------- -package body mips_types is - - function store_shift(x : word_t; va, shift_off : unsigned(1 downto 0); bypass : std_logic) return word_t is - variable stage1 : word_t; - variable result : word_t; - variable sa : unsigned(1 downto 0); - begin - - if bypass = '1' then - sa := "00"; - else - sa := va + shift_off; - end if; - - stage1 := x; - if sa(0) = '1' then - stage1 := x(23 downto 0) & x(31 downto 24); - end if; - result := stage1; - if sa(1) = '1' then - result := stage1(15 downto 0) & stage1(31 downto 16); - end if; - - return result; - end store_shift; - --------------------------------------------------------------------------- - function store_be(va : unsigned(1 downto 0); be_src, word2_en, word4_en, align_left, bypass : std_logic) return unsigned is - variable result : unsigned(3 downto 0); - begin - result := (3 downto 0 => be_src); - if bypass = '0' then - if word2_en = '1' then - case va is - when "00" => - result := "00" & be_src & be_src; - when "10" => - result := be_src & be_src & "00"; - when others => null; - end case; - elsif word4_en = '1' then - case va is - when "00" => - result := "000" & be_src; - when "01" => - result := "00" & be_src & '0'; - when "10" => - result := '0' & be_src & "00"; - when "11" => - result := be_src & "000"; - when others => null; - end case; - elsif align_left = '1' then - case va is - when "00" => - result := be_src & be_src & be_src & be_src; - when "01" => - result := be_src & be_src & be_src & '0'; - when "10" => - result := be_src & be_src & "00"; - when "11" => - result := be_src & "000"; - when others => null; - end case; - else - case va is - when "00" => - result := "000" & be_src; - when "01" => - result := "00" & be_src & be_src; - when "10" => - result := '0' & be_src & be_src & be_src; - when "11" => - result := be_src & be_src & be_src & be_src; - when others => null; - end case; - end if; - end if; - - return result; - - end store_be; - --------------------------------------------------------------------------- - function load_shift(x : word_t; va, shift_off : unsigned(1 downto 0); bypass : std_logic) return word_t is - variable stage1 : word_t; - variable result : word_t; - variable sa : unsigned(1 downto 0); - - begin - if bypass = '1' then - sa := "00"; - else - sa := va + shift_off; - end if; - - stage1 := x; - if sa(0) = '1' then - stage1 := x(7 downto 0) & x(31 downto 8); - end if; - result := stage1; - if sa(1) = '1' then - result := stage1(15 downto 0) & stage1(31 downto 16); - end if; - - return result; - end load_shift; - --------------------------------------------------------------------------- - function load_be(va : unsigned(1 downto 0); align_left, bypass : std_logic) return unsigned is - variable result : unsigned(3 downto 0); - begin - result := (3 downto 0 => '1'); - if bypass = '0' then - if align_left = '1' then - case va is - when "00" => - result := "1000"; - when "01" => - result := "1100"; - when "10" => - result := "1110"; - when "11" => - result := "1111"; - when others => null; - end case; - else - case va is - when "00" => - result := "1111"; - when "01" => - result := "0111"; - when "10" => - result := "0011"; - when "11" => - result := "0001"; - when others => null; - end case; - end if; - end if; - - return result; - - end load_be; - --------------------------------------------------------------------------- - function load_sign_ext(x : word_t; bypass, signed, word2_en, word4_en : std_logic) return word_t is - variable result : word_t; - variable sign : std_logic; - - begin - if bypass = '1' then - result := x; - elsif word2_en = '1' then - sign := signed and x(15); - result := (31 downto 16 => sign) & x(15 downto 0); - else - sign := signed and x(7); - result := (31 downto 8 => sign) & x(7 downto 0); - end if; - - return result; - end load_sign_ext; - --------------------------------------------------------------------------- - function events_clr return event_t is - variable result : event_t; - begin - result.NMI := '0'; - result.Int := '0'; - result.data_load_err := '0'; - result.data_store_err := '0'; - result.inst_load_err := '0'; - result.inst_priv_addr := '0'; - result.alu_ovf := '0'; - result.alu_uvf := '0'; - result.syscall := '0'; - result.break := '0'; - result.illegal := '0'; - - return result; - - end events_clr; - --------------------------------------------------------------------------- - function event_is_active(e : event_t) return std_logic is - variable result : std_logic; - begin - result := '0'; - - result := result or e.NMI; - result := result or e.Int; - result := result or e.data_load_err; - result := result or e.data_store_err; - result := result or e.inst_load_err; - result := result or e.inst_priv_addr; - result := result or e.alu_ovf; - result := result or e.alu_uvf; - result := result or e.syscall; - result := result or e.break; - result := result or e.illegal; - - return result; - - end event_is_active; - --------------------------------------------------------------------------- - function "or" (a, b : event_t) return event_t is - variable result : event_t; - begin - result.NMI := a.NMI or b.NMI; - result.Int := a.Int or b.Int; - result.data_load_err := a.data_load_err or b.data_load_err; - result.data_store_err := a.data_store_err or b.data_store_err; - result.inst_load_err := a.inst_load_err or b.inst_load_err; - result.inst_priv_addr := a.inst_priv_addr or b.inst_priv_addr; - result.alu_ovf := a.alu_ovf or b.alu_ovf; - result.alu_uvf := a.alu_uvf or b.alu_uvf; - result.syscall := a.syscall or b.syscall; - result.break := a.break or b.break; - result.illegal := a.illegal or b.illegal; - - return result; - - end "or"; - --------------------------------------------------------------------------- - function lg2(x : natural) return natural is - begin - return natural(ceil(log2(real(x)))); - end lg2; - --------------------------------------------------------------------------- - function po2(x : natural) return natural is - begin - - return 2**lg2(x); - end po2; - --------------------------------------------------------------------------- -end mips_types; - diff --git a/lib/CPUs/MIPS/src/mips_sys.vhd b/lib/CPUs/MIPS/src/mips_sys.vhd deleted file mode 100644 index 76e3bf5..0000000 --- a/lib/CPUs/MIPS/src/mips_sys.vhd +++ /dev/null @@ -1,341 +0,0 @@ -------------------------------------------------------------------------- --- Project: JIPS, a portable 32-bit RISC CPU written in VHDL --- This file: Testbench for JCPU --- also writes 'opc.lst' for JASM-assembler --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library work; -use work.mips_types.all; -use work.mips_instr.all; -use work.async_types.all; -use work.async_defs.all; - -ENTITY mips_sys IS - GENERIC - ( - ICACHE_SIZE : natural := 512; -- words - DCACHE_SIZE : natural := 512; -- words - SRAM_ADDR_WIDTH : integer := 14; - FLASH_ADDR_WIDTH : integer := 14 - ); - PORT - ( - eb : in std_logic; - nmi : in std_logic; - rst : in std_logic; - clk : in std_logic; - flash_cs_n : out std_logic; - flash_oe_n : out std_logic; - flash_we_n : out std_logic; - flash_be_n : out unsigned(3 downto 0); - sram_cs_n : out std_logic; - sram_we_n : out std_logic; - sram_oe_n : out std_logic; - sram_be_n : out unsigned(3 downto 0); - sram_a : out unsigned(SRAM_ADDR_WIDTH-1 downto 0); - sram_d : inout unsigned(31 downto 0); - flash_a : out unsigned(FLASH_ADDR_WIDTH-1 downto 0); - flash_d : inout unsigned(31 downto 0); - - gpo0 : out unsigned(31 downto 0); - gpo1 : out unsigned(31 downto 0); - gpi0 : in unsigned(31 downto 0); - gpi1 : in unsigned(31 downto 0); - - rx : in std_logic; - tx : out std_logic; - - debug : out unsigned(1 downto 0) - ); -END mips_sys; - -ARCHITECTURE behavior OF mips_sys IS - - -- Master - signal ACK_I : STD_LOGIC := '0'; - signal SRDY_I : STD_LOGIC := '0'; - signal ADDR_O : unsigned(31 downto 0); - signal DAT_I : unsigned(31 downto 0) := (others => '0'); - signal DAT_O : unsigned(31 downto 0); - signal WE_O : STD_LOGIC; - signal SEL_O : unsigned(3 downto 0); - signal CYC_O : STD_LOGIC; - signal STB_O : STD_LOGIC; - signal MRDY_O : STD_LOGIC; - signal INT : unsigned (5 downto 0) := (others => '0'); - - -- Slaves - signal CYC_I_rom : std_logic; - signal ACK_O_rom : std_logic; - signal SRDY_O_rom : std_logic; - signal DAT_O_rom : unsigned(31 downto 0); - - signal CYC_I_flash : std_logic; - signal ACK_O_flash : std_logic; - signal SRDY_O_flash : std_logic; - signal DAT_O_flash : unsigned(31 downto 0); - - signal CYC_I_sram : std_logic; - signal ACK_O_sram : std_logic; - signal SRDY_O_sram : std_logic; - signal DAT_O_sram : unsigned(31 downto 0); - - signal CYC_I_gpio : std_logic; - signal ACK_O_gpio : std_logic; - signal SRDY_O_gpio : std_logic; - signal DAT_O_gpio : unsigned(31 downto 0); - - signal CYC_I_uart : std_logic; - signal ACK_O_uart : std_logic; - signal SRDY_O_uart : std_logic; - signal DAT_O_uart : unsigned(31 downto 0); - - signal int_timer : std_logic; - signal int_uart : std_logic; - - type mem_area_t is (mem_dead, mem_flash, mem_sram, mem_rom, mem_gpio, mem_uart); - signal mem_area : mem_area_t; - -BEGIN - ------------------------------------------------------------------- --- Memory mux ------------------------------------------------------------------- -mem_mux: - process(ADDR_O) - begin - mem_area <= mem_dead; - if ADDR_O(31 downto 28) = X"0" then - mem_area <= mem_flash; - elsif ADDR_O(31 downto 28) = X"A" then - if ADDR_O(27 downto 26) = "00" then - if ADDR_O(18 downto 16) = "000" then - mem_area <= mem_gpio; - elsif ADDR_O(18 downto 16) = "001" then - mem_area <= mem_uart; - end if; - elsif ADDR_O(27 downto 26) = "01" then - mem_area <= mem_flash; - end if; - elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '0') then - mem_area <= mem_rom; - elsif (ADDR_O(31 downto 28) = X"8" or ADDR_O(30) = '1') then - mem_area <= mem_sram; - end if; - end process; - -signal_mux: - process(mem_area, CYC_O) - begin - - CYC_I_uart <= '0'; - CYC_I_gpio <= '0'; - CYC_I_flash <= '0'; - CYC_I_rom <= '0'; - CYC_I_sram <= '0'; - - case mem_area is - - when mem_gpio => - CYC_I_gpio <= CYC_O; - - when mem_uart => - CYC_I_uart <= CYC_O; - - when mem_flash => - CYC_I_flash <= CYC_O; - - when mem_rom => - CYC_I_rom <= CYC_O; - - when mem_sram => - CYC_I_sram <= CYC_O; - - when others => null; - - end case; - - end process; - - SRDY_I <= SRDY_O_flash or SRDY_O_sram or SRDY_O_rom or SRDY_O_uart or SRDY_O_gpio; - ACK_I <= ACK_O_flash or ACK_O_sram or ACK_O_rom or ACK_O_uart or ACK_O_gpio; - DAT_I <= DAT_O_sram when CYC_I_sram = '1' else - DAT_O_rom when CYC_I_rom = '1' else - DAT_O_flash when CYC_I_flash = '1' else - DAT_O_uart when CYC_I_uart = '1' else - DAT_O_gpio when CYC_I_gpio = '1' else X"DEADBEEF"; - - ------------------------------------------------------------------- -inst_mips_top: entity work.mips_top - GENERIC MAP - ( - icache_size => ICACHE_SIZE, -- words - dcache_size => DCACHE_SIZE -- words - ) - PORT MAP - ( - debug => debug, - nmi => nmi, - eb => eb, - cpu_clk => clk, - RST_I => rst, - CLK_I => clk, - ACK_I => ACK_I, - SRDY_I => SRDY_I, - ADDR_O => ADDR_O, - DAT_I => DAT_I, - DAT_O => DAT_O, - WE_O => WE_O, - SEL_O => SEL_O, - CYC_O => CYC_O, - STB_O => STB_O, - MRDY_O => MRDY_O, - INT => INT - ); - INT(1) <= int_uart; - INT(5) <= int_timer; - -inst_rom : entity work.rom_wb - PORT MAP - ( - CLK_I => clk, - RST_I => rst, - CYC_I => CYC_I_rom, - STB_I => STB_O, - ACK_O => ACK_O_rom, - MRDY_I => MRDY_O, - SRDY_O => SRDY_O_rom, - ADDR_I => ADDR_O, - DAT_O => DAT_O_rom - ); - -inst_gpio : entity work.gpio_wb - PORT MAP - ( - CLK_I => clk, - RST_I => rst, - CYC_I => CYC_I_gpio, - STB_I => STB_O, - SEL_I => SEL_O, - WE_I => WE_O, - ACK_O => ACK_O_gpio, - SRDY_O => SRDY_O_gpio, - MRDY_I => MRDY_O, - ADDR_I => ADDR_O, - DAT_I => DAT_O, - DAT_O => DAT_O_gpio, - INT_TIM_O => int_timer, - sys_gpo0 => gpo0, - sys_gpo1 => gpo1, - sys_gpi0 => gpi0, - sys_gpi1 => gpi1 - ); - -inst_flash_port : entity work.async_port_wb - GENERIC MAP - ( - addr_width => FLASH_ADDR_WIDTH, - data_width => 32, - byte_sel_width => 4, - async_timespec => ts_flash - ) - PORT MAP - ( - CLK_I => clk, - RST_I => rst, - CYC_I => CYC_I_flash, - STB_I => STB_O, - WE_I => WE_O, - ACK_O => ACK_O_flash, - SRDY_O => SRDY_O_flash, - MRDY_I => MRDY_O, - SEL_I => SEL_O, - ADDR_I => ADDR_O, - DAT_I => DAT_O, - DAT_O => DAT_O_flash, - page_mode_en => '0', - async_a => flash_a, - async_d => flash_d, - async_cs => flash_cs_n, - async_wr => flash_we_n, - async_rd => flash_oe_n, - async_be => flash_be_n, - async_rst => open - ); - -inst_sram_port : entity work.async_port_wb - GENERIC MAP - ( - addr_width => SRAM_ADDR_WIDTH, - data_width => 32, - byte_sel_width => 4, - async_timespec => ts_sram - ) - PORT MAP - ( - CLK_I => clk, - RST_I => rst, - CYC_I => CYC_I_sram, - STB_I => STB_O, - WE_I => WE_O, - ACK_O => ACK_O_sram, - SRDY_O => SRDY_O_sram, - MRDY_I => MRDY_O, - SEL_I => SEL_O, - ADDR_I => ADDR_O, - DAT_I => DAT_O, - DAT_O => DAT_O_sram, - page_mode_en => '0', - async_a => sram_a, - async_d => sram_d, - async_cs => sram_cs_n, - async_wr => sram_we_n, - async_rd => sram_oe_n, - async_be => sram_be_n, - async_rst => open - ); - -inst_uart : entity work.uart_wb - PORT MAP - ( - CLK_I => clk, - RST_I => rst, - CYC_I => CYC_I_uart, - STB_I => STB_O, - SEL_I => SEL_O, - WE_I => WE_O, - ACK_O => ACK_O_uart, - SRDY_O => SRDY_O_uart, - MRDY_I => MRDY_O, - ADDR_I => ADDR_O, - DAT_I => DAT_O, - DAT_O => DAT_O_uart, - INT_O => int_uart, - ser_rx => rx, - ser_tx => tx - ); - -END; diff --git a/lib/CPUs/MIPS/src/mips_top_syn.vhd b/lib/CPUs/MIPS/src/mips_top_syn.vhd deleted file mode 100644 index c7c99e8..0000000 --- a/lib/CPUs/MIPS/src/mips_top_syn.vhd +++ /dev/null @@ -1,100 +0,0 @@ --------------------------------------------------------------------------- --- Project: JIPS, a portable 32-bit RISC CPU written in VHDL --- This file: JIPS top file --- --- Copyright (C) 2008 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -library work; -use work.mips_types.all; - -entity mips_top is - Generic - ( - icache_size : natural := 8192; -- words - icache_line : natural := 8; -- words - dcache_size : natural := 4096; -- words - dcache_line : natural := 8 -- words - ); - Port - ( - debug : out unsigned(1 downto 0); - eb : in STD_LOGIC; - nmi : in STD_LOGIC; - cpu_clk : in STD_LOGIC; - RST_I : in STD_LOGIC; - CLK_I : in STD_LOGIC; - ACK_I : in STD_LOGIC; - SRDY_I : in STD_LOGIC; - ADDR_O : out unsigned(31 downto 0); - DAT_I : in unsigned(31 downto 0); - DAT_O : out unsigned(31 downto 0); - WE_O : out STD_LOGIC; - SEL_O : out unsigned(3 downto 0); - CYC_O : out STD_LOGIC; - STB_O : out STD_LOGIC; - MRDY_O : out STD_LOGIC; - INT : in unsigned (5 downto 0) - ); - -end mips_top; - -architecture rtl of mips_top is - - signal SEL_O_SLV : STD_LOGIC_VECTOR (3 downto 0); - signal DAT_O_SLV : STD_LOGIC_VECTOR (31 downto 0); - signal ADDR_O_SLV : STD_LOGIC_VECTOR (31 downto 0); - signal DEBUG_SLV : STD_LOGIC_VECTOR (1 downto 0); - -begin - - SEL_O <= unsigned(SEL_O_SLV); - DAT_O <= unsigned(DAT_O_SLV); - ADDR_O <= unsigned(ADDR_O_SLV); - DEBUG <= unsigned(DEBUG_SLV); - -inst_mips_top_syn : entity work.mips_top_syn - PORT MAP - ( - RST_I => RST_I, - eb => eb, - WE_O => WE_O, - CYC_O => CYC_O, - cpu_clk => cpu_clk, - ACK_I => ACK_I, - nmi => nmi, - STB_O => STB_O, - CLK_I => CLK_I, - MRDY_O => MRDY_O, - SRDY_I => SRDY_I, - debug => DEBUG_SLV, - DAT_O => DAT_O_SLV, - SEL_O => SEL_O_SLV, - ADDR_O => ADDR_O_SLV, - DAT_I => STD_LOGIC_VECTOR(DAT_I), - INT => STD_LOGIC_VECTOR(INT) - ); - - - -end rtl; diff --git a/lib/CPUs/MIPS/src/tb_mips_muldiv.vhd b/lib/CPUs/MIPS/src/tb_mips_muldiv.vhd deleted file mode 100644 index ba364eb..0000000 --- a/lib/CPUs/MIPS/src/tb_mips_muldiv.vhd +++ /dev/null @@ -1,332 +0,0 @@ -------------------------------------------------------------------------- --- Project: JIPS, a portable 32-bit RISC CPU written in VHDL --- This file: Testbench for JCPU --- also writes 'opc.lst' for JASM-assembler --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library work; -use work.mips_types.all; -use work.mips_instr.all; - -ENTITY tb_mips_muldiv IS -END tb_mips_muldiv; - -ARCHITECTURE behavior OF tb_mips_muldiv IS - - COMPONENT muldiv is - Port - ( - rst : in std_logic; - clk : in std_logic; - hilo_we : in std_logic; - din_hi : in word_t; - din_lo : in word_t; - mul_divn : in std_logic; - s_un : in std_logic; - start : in std_logic; - hilo_sel : in std_logic; - busy : out std_logic; - dout : out word_t - ); - END COMPONENT; - - constant CLK_PERIOD : time := 10 ns; - signal ENABLE_FAIL_REPORT : boolean := true; - signal rst : std_logic := '1'; - signal clk : std_logic := '1'; - signal busy : std_logic; - signal mul_divn : std_logic := '0'; - signal s_un : std_logic := '1'; - signal hilo_we : std_logic := '0'; - signal start : std_logic := '0'; - signal din_hi : word_t := (others => '-'); - signal din_lo : word_t := (others => '-'); - signal dout : word_t; - signal hilo_sel : std_logic := '0'; - signal md_result : unsigned (2*word_t'length-1 downto 0) := (others => '0'); - signal ref_result : unsigned (2*word_t'length-1 downto 0); - signal ref_hi : unsigned (word_t'length-1 downto 0); - signal rtmp : unsigned (2*word_t'length-1 downto 0); - signal tmp2 : unsigned (word_t'length-1 downto 0); - signal check : std_logic; - - type word_array_t is array (natural range <>) of word_t; - - constant operands : word_array_t(0 to 63) := - ( - X"00000000", - X"00000001", - X"00000010", - X"00000100", - X"00001000", - X"00010000", - X"00100000", - X"01000000", - X"10000000", - X"0000000F", - X"000000FF", - X"00000FFF", - X"0000FFFF", - X"000FFFFF", - X"00FFFFFF", - X"0FFFFFFF", - X"12345678", - X"23456789", - X"7FFFFFFF", - X"80000000", - X"A541B3B9", - X"80000001", - X"80000010", - X"80000100", - X"80001000", - X"80010000", - X"80100000", - X"81000000", - X"87654321", - X"98765432", - X"FFFFFFFF", - X"FFFFFFFE", - X"FFFFFFFD", - X"FFFFFFFB", - X"FFFFFFF7", - X"FFFFFFEF", - X"FFFFFFDF", - X"FFFFFFBF", - X"FFFFFF7F", - X"FFFFFEFF", - X"FFFFFDFF", - X"FFFFFBFF", - X"FFFFF7FF", - X"FFFFEFFF", - X"FFFFDFFF", - X"FFFFBFFF", - X"FFFF7FFF", - X"FFFEFFFF", - X"FFFDFFFF", - X"FFFBFFFF", - X"FFF7FFFF", - X"FFEFFFFF", - X"FFDFFFFF", - X"FFBFFFFF", - X"FF7FFFFF", - X"FEFFFFFF", - X"FDFFFFFF", - X"FBFFFFFF", - X"F7FFFFFF", - X"EFFFFFFF", - X"DFFFFFFF", - X"BFFFFFFF", - X"CFFFFFFF", - X"7FFFFFFF" - ); - -BEGIN - -uut: muldiv - PORT MAP( - rst => rst, - clk => clk, - hilo_we => hilo_we, - din_hi => din_hi, - din_lo => din_lo, - mul_divn => mul_divn, - s_un => s_un, - start => start, - hilo_sel => hilo_sel, - busy => busy, - dout => dout - ); - -CLK_GEN: process - begin - wait for CLK_PERIOD/2; - clk <= not clk; - end process; - -REF_GEN: process - begin - if mul_divn = '0' then - wait until rising_edge(clk) and check = '1'; - if s_un = '1' then - rtmp <= unsigned(signed(md_result(31 downto 0)) * signed(din_lo)); - wait until rising_edge(clk); - tmp2 <= unsigned(signed(rtmp(31 downto 0)) + signed(md_result(63 downto 32))); - wait until rising_edge(clk); - ref_hi <= tmp2(31 downto 0); - else - rtmp <= md_result(31 downto 0) * din_lo; - wait until rising_edge(clk); - tmp2 <= rtmp(31 downto 0) + md_result(63 downto 32); - wait until rising_edge(clk); - ref_hi <= tmp2(31 downto 0); - end if; - wait until rising_edge(clk); - - if din_lo /= X"00000000" then - if ENABLE_FAIL_REPORT then - assert din_hi = ref_hi report "Error on divison" severity failure; - end if; - end if; - else - wait until rising_edge(clk) and check = '1'; - if s_un = '1' then - ref_result <= unsigned(signed(din_hi) * signed(din_lo)); - else - ref_result <= unsigned(din_hi) * unsigned(din_lo); - end if; - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - if ENABLE_FAIL_REPORT then - assert ref_result = md_result report "Error on multiplication" severity failure; - end if; - end if; - - end process; - -STIMULUS: process - - begin - - wait for 3*CLK_PERIOD; - wait until rising_edge(clk); - rst <= '0'; - wait for 2*CLK_PERIOD; - - mul_divn <= '0'; - s_un <= '0'; - for i in 0 to operands'length-1 loop - for j in 0 to operands'length-1 loop - check <= '0'; - wait until rising_edge(clk) and busy = '0'; - din_hi <= operands(i); - din_lo <= operands(j); - start <= '1'; - wait until rising_edge(clk); - start <= '0'; - hilo_sel <= '0'; - - -- Read result - wait until rising_edge(clk) and busy = '0'; - wait until rising_edge(clk); - md_result(31 downto 0) <= dout; - wait until rising_edge(clk); - hilo_sel <= '1'; - wait until rising_edge(clk); - md_result(63 downto 32) <= dout; - check <= '1'; - wait until rising_edge(clk); - check <= '0'; - wait for 8*CLK_PERIOD; - end loop; - end loop; - - s_un <= '1'; - for i in 0 to operands'length-1 loop - for j in 0 to operands'length-1 loop - check <= '0'; - wait until rising_edge(clk) and busy = '0'; - din_hi <= operands(i); - din_lo <= operands(j); - start <= '1'; - wait until rising_edge(clk); - start <= '0'; - hilo_sel <= '0'; - - -- Read result - wait until rising_edge(clk) and busy = '0'; - wait until rising_edge(clk); - md_result(31 downto 0) <= dout; - wait until rising_edge(clk); - hilo_sel <= '1'; - wait until rising_edge(clk); - md_result(63 downto 32) <= dout; - check <= '1'; - wait until rising_edge(clk); - check <= '0'; - wait for 8*CLK_PERIOD; - end loop; - end loop; - - mul_divn <= '1'; - s_un <= '0'; - for i in 0 to operands'length-1 loop - for j in 0 to operands'length-1 loop - check <= '0'; - wait until rising_edge(clk) and busy = '0'; - din_hi <= operands(i); - din_lo <= operands(j); - start <= '1'; - wait until rising_edge(clk); - start <= '0'; - hilo_sel <= '0'; - - -- Read result - wait until rising_edge(clk) and busy = '0'; - wait until rising_edge(clk); - md_result(31 downto 0) <= dout; - wait until rising_edge(clk); - hilo_sel <= '1'; - wait until rising_edge(clk); - md_result(63 downto 32) <= dout; - check <= '1'; - wait until rising_edge(clk); - check <= '0'; - wait for 8*CLK_PERIOD; - end loop; - end loop; - - s_un <= '1'; - for i in 0 to operands'length-1 loop - for j in 0 to operands'length-1 loop - check <= '0'; - wait until rising_edge(clk) and busy = '0'; - din_hi <= operands(i); - din_lo <= operands(j); - start <= '1'; - wait until rising_edge(clk); - start <= '0'; - hilo_sel <= '0'; - - -- Read result - wait until rising_edge(clk) and busy = '0'; - wait until rising_edge(clk); - md_result(31 downto 0) <= dout; - wait until rising_edge(clk); - hilo_sel <= '1'; - wait until rising_edge(clk); - md_result(63 downto 32) <= dout; - check <= '1'; - wait until rising_edge(clk); - check <= '0'; - wait for 8*CLK_PERIOD; - end loop; - end loop; - - wait; - - end process; - -END; diff --git a/lib/CPUs/MIPS/src/tb_mips_sys.vhd b/lib/CPUs/MIPS/src/tb_mips_sys.vhd deleted file mode 100644 index 88479ae..0000000 --- a/lib/CPUs/MIPS/src/tb_mips_sys.vhd +++ /dev/null @@ -1,233 +0,0 @@ -------------------------------------------------------------------------- --- Project: JIPS, a portable 32-bit RISC CPU written in VHDL --- This file: Testbench for JCPU --- also writes 'opc.lst' for JASM-assembler --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library work; -use work.mips_types.all; -use work.mips_instr.all; -use work.async_types.all; -use work.async_defs.all; - -ENTITY tb_mips_sys IS -END tb_mips_sys; - -ARCHITECTURE behavior OF tb_mips_sys IS - - constant CLK_PERIOD : time := 10 ns; - constant ICACHE_SIZE : natural := 512; -- words - constant DCACHE_SIZE : natural := 512; -- words - constant SRAM_ADDR_WIDTH : integer := 17; -- bits - constant FLASH_ADDR_WIDTH : integer := 17; -- bits - - signal debug : unsigned(1 downto 0); - - -- Master - signal nmi : STD_LOGIC := '0'; - signal rst : STD_LOGIC := '1'; - signal clk : STD_LOGIC := '0'; - signal eb : STD_LOGIC := '1'; - - signal flash_cs_n : std_logic; - signal flash_we_n : std_logic; - signal flash_oe_n : std_logic; - signal flash_be_n : unsigned(3 downto 0); - signal sram_cs_n : std_logic; - signal sram_be_n : unsigned(3 downto 0); - signal sram_wr_n : std_logic; - signal sram_oe_n : std_logic; - signal sram_a : unsigned(SRAM_ADDR_WIDTH-1 downto 0); - signal sram_d : unsigned(31 downto 0); - signal flash_a : unsigned(FLASH_ADDR_WIDTH-1 downto 0); - signal flash_d : unsigned(31 downto 0); - - signal gpo0 : unsigned(31 downto 0); - signal gpo1 : unsigned(31 downto 0); - signal gpi0 : unsigned(31 downto 0) := (others => '0'); - signal gpi1 : unsigned(31 downto 0) := (others => '0'); - - signal int_timer : std_logic; - signal int_uart : std_logic; - signal rx : std_logic := '1'; - signal tx : std_logic; - - type word_array_t is array (natural range <>) of unsigned(31 downto 0); - signal sram_data : word_array_t(0 to 2**SRAM_ADDR_WIDTH-1); - signal flash_data : word_array_t(0 to 2**FLASH_ADDR_WIDTH-1); - -BEGIN - ------------------------------------------------------------------- -CLK_GEN: process - begin - wait for CLK_PERIOD/2; - clk <= not clk; - end process; - ------------------------------------------------------------------- -uut : entity work.mips_sys - GENERIC MAP - ( - ICACHE_SIZE => ICACHE_SIZE, -- words - DCACHE_SIZE => DCACHE_SIZE, -- words - SRAM_ADDR_WIDTH => SRAM_ADDR_WIDTH, - FLASH_ADDR_WIDTH => FLASH_ADDR_WIDTH - ) - PORT MAP - ( - eb => eb, - nmi => nmi, - rst => rst, - clk => clk, - flash_cs_n => flash_cs_n, - flash_oe_n => flash_oe_n, - flash_we_n => flash_we_n, - flash_be_n => flash_be_n, - sram_cs_n => sram_cs_n, - sram_we_n => sram_wr_n, - sram_oe_n => sram_oe_n, - sram_be_n => sram_be_n, - sram_a => sram_a, - sram_d => sram_d, - flash_a => flash_a, - flash_d => flash_d, - - gpo0 => gpo0, - gpo1 => gpo1, - gpi0 => gpi0, - gpi1 => gpi1, - - rx => rx, - tx => tx, - - debug => debug - ); - ------------------------------------------------------------------- -SRAM_READ: - process(sram_a, sram_cs_n, sram_oe_n, sram_be_n) - begin - sram_d <= (others => 'Z') after 10 ns; - if sram_oe_n = '0' then - if sram_cs_n = '0' then - if sram_be_n(0) = '0' then - sram_d(7 downto 0) <= sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(7 downto 0) after 10 ns; - end if; - if sram_be_n(1) = '0' then - sram_d(15 downto 8) <= sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(15 downto 8) after 10 ns; - end if; - if sram_be_n(2) = '0' then - sram_d(23 downto 16) <= sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(23 downto 16) after 10 ns; - end if; - if sram_be_n(3) = '0' then - sram_d(31 downto 24) <= sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(31 downto 24) after 10 ns; - end if; - end if; - end if; - end process; - -SRAM_WRITE: - process(sram_wr_n) - begin - if rising_edge(sram_wr_n) then - if sram_cs_n = '0' then - if sram_be_n(0) = '0' then - sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(7 downto 0) <= sram_d(7 downto 0); - end if; - if sram_be_n(1) = '0' then - sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(15 downto 8) <= sram_d(15 downto 8); - end if; - if sram_be_n(2) = '0' then - sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(23 downto 16) <= sram_d(23 downto 16); - end if; - if sram_be_n(3) = '0' then - sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(31 downto 24) <= sram_d(31 downto 24); - end if; - end if; - end if; - end process; - ------------------------------------------------------------------- -FLASH_READ: - process(rst, flash_cs_n, flash_oe_n, flash_a) - type file_t is file of integer; - file load_flash : file_t open read_mode is "hello.flash.bin"; - variable instr : integer; - variable index : natural; - variable temp : signed(31 downto 0); - constant tpd : time := 25 ns; - begin - if rst = '1' then - index := 0; - while not endfile(load_flash) loop - read(load_flash, instr); - temp := to_signed(instr, word_t'length); - flash_data(index) <= unsigned(temp); - index := index + 1; - end loop; - else - flash_d <= (others => 'Z') after tpd; - index := to_integer(flash_a(FLASH_ADDR_WIDTH-1 downto 2)); - if flash_oe_n = '0' then - if flash_cs_n = '0' then - if flash_be_n(0) = '0' then - flash_d(7 downto 0) <= flash_data(index)(7 downto 0) after tpd; - end if; - if flash_be_n(1) = '0' then - flash_d(15 downto 8) <= flash_data(index)(15 downto 8) after tpd; - end if; - if flash_be_n(2) = '0' then - flash_d(23 downto 16) <= flash_data(index)(23 downto 16) after tpd; - end if; - if flash_be_n(3) = '0' then - flash_d(31 downto 24) <= flash_data(index)(31 downto 24) after tpd; - end if; - end if; - end if; - end if; - end process; - ------------------------------------------------------------------- -STIMULUS: process - - begin - - - wait for 3*CLK_PERIOD; - wait until rising_edge(clk); - rst <= '0'; - wait for 778254*CLK_PERIOD; - wait until rising_edge(clk); - nmi <= '0'; - wait for 3000*CLK_PERIOD; - wait until rising_edge(clk); - nmi <= '0'; - - wait; - - end process; - -END; diff --git a/lib/CPUs/MIPS/src/tb_mips_top.vhd b/lib/CPUs/MIPS/src/tb_mips_top.vhd deleted file mode 100644 index c044a61..0000000 --- a/lib/CPUs/MIPS/src/tb_mips_top.vhd +++ /dev/null @@ -1,460 +0,0 @@ -------------------------------------------------------------------------- --- Project: JIPS, a portable 32-bit RISC CPU written in VHDL --- This file: Testbench for JCPU --- also writes 'opc.lst' for JASM-assembler --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library work; -use work.mips_types.all; -use work.mips_instr.all; -use work.async_types.all; -use work.async_defs.all; - -ENTITY tb_mips_top IS -END tb_mips_top; - -ARCHITECTURE behavior OF tb_mips_top IS - - constant SYS_FREQ : real := 100.0; - constant CLK_PERIOD : time := 10 ns; - constant SRAM_ADDR_WIDTH : integer := 17; -- bits - constant FLASH_ADDR_WIDTH : integer := 17; -- bits - - signal debug : chip_debug_t; - - -- Master - signal nmi : STD_LOGIC := '0'; - signal rst : STD_LOGIC := '1'; - signal clk : STD_LOGIC := '0'; - signal eb : STD_LOGIC := '1'; - signal ACK_I : STD_LOGIC := '0'; - signal SRDY_I : STD_LOGIC := '0'; - signal ADDR_O : unsigned(31 downto 0); - signal DAT_I : unsigned(31 downto 0) := (others => '0'); - signal DAT_O : unsigned(31 downto 0); - signal WE_O : STD_LOGIC; - signal SEL_O : unsigned(3 downto 0); - signal CYC_O : STD_LOGIC; - signal STB_O : STD_LOGIC; - signal MRDY_O : STD_LOGIC; - signal INT : unsigned (5 downto 0) := (others => '0'); - - -- Slaves - signal CYC_I_rom : std_logic; - signal ACK_O_rom : std_logic; - signal SRDY_O_rom : std_logic; - signal DAT_O_rom : unsigned(31 downto 0); - - signal CYC_I_flash : std_logic; - signal ACK_O_flash : std_logic; - signal SRDY_O_flash : std_logic; - signal DAT_O_flash : unsigned(31 downto 0); - - signal CYC_I_sram : std_logic; - signal ACK_O_sram : std_logic; - signal SRDY_O_sram : std_logic; - signal DAT_O_sram : unsigned(31 downto 0); - - signal CYC_I_gpio : std_logic; - signal ACK_O_gpio : std_logic; - signal SRDY_O_gpio : std_logic; - signal DAT_O_gpio : unsigned(31 downto 0); - - signal CYC_I_uart : std_logic; - signal ACK_O_uart : std_logic; - signal SRDY_O_uart : std_logic; - signal DAT_O_uart : unsigned(31 downto 0); - - signal flash_cs_n : std_logic; - signal flash_we_n : std_logic; - signal flash_oe_n : std_logic; - signal flash_be_n : unsigned(3 downto 0); - signal sram_cs_n : std_logic; - signal sram_be_n : unsigned(3 downto 0); - signal sram_wr_n : std_logic; - signal sram_oe_n : std_logic; - signal sram_a : unsigned(SRAM_ADDR_WIDTH-1 downto 0); - signal sram_d : unsigned(31 downto 0); - signal flash_a : unsigned(FLASH_ADDR_WIDTH-1 downto 0); - signal flash_d : unsigned(31 downto 0); - signal flash_page_mode_en : std_logic; - - signal gpi_0 : unsigned(31 downto 0); - signal gpo_0 : unsigned(31 downto 0); - - signal int_timer : std_logic; - signal int_uart : std_logic; - signal rx : std_logic := '1'; - signal tx : std_logic; - - type mem_area_t is (mem_dead, mem_flash, mem_sram, mem_rom, mem_gpio, mem_uart); - signal mem_area : mem_area_t; - - type word_array_t is array (natural range <>) of unsigned(31 downto 0); - signal sram_data : word_array_t(0 to 2**SRAM_ADDR_WIDTH-1); - signal flash_data : word_array_t(0 to 2**FLASH_ADDR_WIDTH-1); - -BEGIN - ------------------------------------------------------------------- -CLK_GEN: process - begin - wait for CLK_PERIOD/2; - clk <= not clk; - end process; - ------------------------------------------------------------------- --- Memory mux ------------------------------------------------------------------- -mem_mux: - process(ADDR_O) - begin - mem_area <= mem_dead; - flash_page_mode_en <= '0'; - if ADDR_O(31 downto 28) = X"0" then - mem_area <= mem_flash; - flash_page_mode_en <= '1'; - elsif ADDR_O(31 downto 28) = X"A" then - if ADDR_O(27 downto 26) = "00" then - if ADDR_O(18 downto 16) = "000" then - mem_area <= mem_gpio; - elsif ADDR_O(18 downto 16) = "001" then - mem_area <= mem_uart; - end if; - elsif ADDR_O(27 downto 26) = "01" then - mem_area <= mem_flash; - end if; - elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '0') then - mem_area <= mem_rom; - elsif (ADDR_O(31 downto 28) = X"8" or ADDR_O(30) = '1') then - mem_area <= mem_sram; - end if; - end process; - -signal_mux: - process(mem_area, CYC_O) - begin - - CYC_I_uart <= '0'; - CYC_I_gpio <= '0'; - CYC_I_flash <= '0'; - CYC_I_rom <= '0'; - CYC_I_sram <= '0'; - - case mem_area is - - when mem_gpio => - CYC_I_gpio <= CYC_O; - - when mem_uart => - CYC_I_uart <= CYC_O; - - when mem_flash => - CYC_I_flash <= CYC_O; - - when mem_rom => - CYC_I_rom <= CYC_O; - - when mem_sram => - CYC_I_sram <= CYC_O; - - when others => null; - - end case; - - end process; - - SRDY_I <= SRDY_O_flash or SRDY_O_sram or SRDY_O_rom or SRDY_O_uart or SRDY_O_gpio; - ACK_I <= ACK_O_flash or ACK_O_sram or ACK_O_rom or ACK_O_uart or ACK_O_gpio; - DAT_I <= DAT_O_sram when CYC_I_sram = '1' else - DAT_O_rom when CYC_I_rom = '1' else - DAT_O_flash when CYC_I_flash = '1' else - DAT_O_uart when CYC_I_uart = '1' else - DAT_O_gpio when CYC_I_gpio = '1' else X"DEADBEEF"; - - ------------------------------------------------------------------- -uut: entity work.mips_top - GENERIC MAP - ( - icache_size => 1024, -- words - dcache_size => 1024 -- words - ) - PORT MAP - ( - debug => debug, - eb => eb, - cpu_clk => clk, - RST_I => rst, - CLK_I => clk, - ACK_I => ACK_I, - SRDY_I => SRDY_I, - ADDR_O => ADDR_O, - DAT_I => DAT_I, - DAT_O => DAT_O, - WE_O => WE_O, - SEL_O => SEL_O, - CYC_O => CYC_O, - STB_O => STB_O, - MRDY_O => MRDY_O, - INT => INT, - nmi => nmi - ); - INT(1) <= int_uart; - INT(5) <= int_timer; - -inst_rom : entity work.rom_wb - PORT MAP - ( - CLK_I => clk, - RST_I => rst, - CYC_I => CYC_I_rom, - STB_I => STB_O, - WE_I => WE_O, - ACK_O => ACK_O_rom, - MRDY_I => MRDY_O, - SRDY_O => SRDY_O_rom, - ADDR_I => ADDR_O, - DAT_O => DAT_O_rom - ); - -inst_gpio : entity work.gpio_wb - PORT MAP - ( - CLK_I => clk, - RST_I => rst, - CYC_I => CYC_I_gpio, - STB_I => STB_O, - SEL_I => SEL_O, - WE_I => WE_O, - ACK_O => ACK_O_gpio, - SRDY_O => SRDY_O_gpio, - MRDY_I => MRDY_O, - ADDR_I => ADDR_O, - DAT_I => DAT_O, - DAT_O => DAT_O_gpio, - INT_TIM_O => int_timer, - - sys_gpi_0 => gpi_0, - sys_gpo_0 => gpo_0 - ); - -inst_flash_port : entity work.async_port_wb - GENERIC MAP - ( - f_sysclk => SYS_FREQ, - addr_width => FLASH_ADDR_WIDTH, - data_width => 32, - byte_sel_width => 4, - async_timespec => ts_flash - ) - PORT MAP - ( - CLK_I => clk, - RST_I => rst, - CYC_I => CYC_I_flash, - STB_I => STB_O, - WE_I => WE_O, - ACK_O => ACK_O_flash, - SRDY_O => SRDY_O_flash, - MRDY_I => MRDY_O, - SEL_I => SEL_O, - ADDR_I => ADDR_O, - DAT_I => DAT_O, - DAT_O => DAT_O_flash, - page_mode_en => flash_page_mode_en, - async_a => flash_a, - async_d => flash_d, - async_cs => flash_cs_n, - async_wr => flash_we_n, - async_rd => flash_oe_n, - async_be => flash_be_n, - async_rst => open - ); - -inst_sram_port : entity work.async_port_wb - GENERIC MAP - ( - f_sysclk => SYS_FREQ, - addr_width => SRAM_ADDR_WIDTH, - data_width => 32, - byte_sel_width => 4, - async_timespec => ts_sram - ) - PORT MAP - ( - CLK_I => clk, - RST_I => rst, - CYC_I => CYC_I_sram, - STB_I => STB_O, - WE_I => WE_O, - ACK_O => ACK_O_sram, - SRDY_O => SRDY_O_sram, - MRDY_I => MRDY_O, - SEL_I => SEL_O, - ADDR_I => ADDR_O, - DAT_I => DAT_O, - DAT_O => DAT_O_sram, - page_mode_en => '0', - async_a => sram_a, - async_d => sram_d, - async_cs => sram_cs_n, - async_wr => sram_wr_n, - async_rd => sram_oe_n, - async_be => sram_be_n, - async_rst => open - ); - -inst_uart : entity work.uart_wb - GENERIC MAP - ( - simulate_tx => true - ) - PORT MAP - ( - CLK_I => clk, - RST_I => rst, - CYC_I => CYC_I_uart, - STB_I => STB_O, - SEL_I => SEL_O, - WE_I => WE_O, - ACK_O => ACK_O_uart, - SRDY_O => SRDY_O_uart, - MRDY_I => MRDY_O, - ADDR_I => ADDR_O, - DAT_I => DAT_O, - DAT_O => DAT_O_uart, - INT_O => int_uart, - ser_rx => rx, - ser_tx => tx - ); - ------------------------------------------------------------------- -SRAM_READ: - process(sram_a, sram_cs_n, sram_oe_n, sram_be_n) - begin - sram_d <= (others => 'Z') after 10 ns; - if sram_oe_n = '0' then - if sram_cs_n = '0' then - if sram_be_n(0) = '0' then - sram_d(7 downto 0) <= sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(7 downto 0) after 10 ns; - end if; - if sram_be_n(1) = '0' then - sram_d(15 downto 8) <= sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(15 downto 8) after 10 ns; - end if; - if sram_be_n(2) = '0' then - sram_d(23 downto 16) <= sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(23 downto 16) after 10 ns; - end if; - if sram_be_n(3) = '0' then - sram_d(31 downto 24) <= sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(31 downto 24) after 10 ns; - end if; - end if; - end if; - end process; - -SRAM_WRITE: - process(sram_wr_n) - begin - if rising_edge(sram_wr_n) then - if sram_cs_n = '0' then - if sram_be_n(0) = '0' then - sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(7 downto 0) <= sram_d(7 downto 0); - end if; - if sram_be_n(1) = '0' then - sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(15 downto 8) <= sram_d(15 downto 8); - end if; - if sram_be_n(2) = '0' then - sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(23 downto 16) <= sram_d(23 downto 16); - end if; - if sram_be_n(3) = '0' then - sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(31 downto 24) <= sram_d(31 downto 24); - end if; - end if; - end if; - end process; - ------------------------------------------------------------------- -FLASH_READ: - process(rst, flash_cs_n, flash_oe_n, flash_a) - type file_t is file of integer; --- file load_flash : file_t open read_mode is "ucb.elf.flash.bin"; - file load_flash : file_t open read_mode is "test_timer.elf.flash.bin"; --- file load_flash : file_t open read_mode is "test_dcache.flash.bin"; - variable instr : integer; - variable index : natural; - variable temp : signed(31 downto 0); - constant tpd : time := 25 ns; - begin - if rst = '1' then - index := 0; - while not endfile(load_flash) loop - read(load_flash, instr); - temp := to_signed(instr, word_t'length); - flash_data(index) <= unsigned(temp); - index := index + 1; - end loop; - else - flash_d <= (others => 'Z') after tpd; - index := to_integer(flash_a(FLASH_ADDR_WIDTH-1 downto 2)); - if flash_oe_n = '0' then - if flash_cs_n = '0' then - if flash_be_n(0) = '0' then - flash_d(7 downto 0) <= flash_data(index)(7 downto 0) after tpd; - end if; - if flash_be_n(1) = '0' then - flash_d(15 downto 8) <= flash_data(index)(15 downto 8) after tpd; - end if; - if flash_be_n(2) = '0' then - flash_d(23 downto 16) <= flash_data(index)(23 downto 16) after tpd; - end if; - if flash_be_n(3) = '0' then - flash_d(31 downto 24) <= flash_data(index)(31 downto 24) after tpd; - end if; - end if; - end if; - end if; - end process; - ------------------------------------------------------------------- -STIMULUS: process - - begin - - gpi_0 <= X"00000000"; - wait for 3*CLK_PERIOD; - wait until rising_edge(clk); - rst <= '0'; - wait for 778254*CLK_PERIOD; - wait until rising_edge(clk); - nmi <= '0'; - wait for 3000*CLK_PERIOD; - wait until rising_edge(clk); - nmi <= '0'; - - wait; - - end process; - -END; diff --git a/lib/CPUs/MIPS/syn/ise101/constraints/mips_top.xcf b/lib/CPUs/MIPS/syn/ise101/constraints/mips_top.xcf deleted file mode 100644 index 1c877f4..0000000 --- a/lib/CPUs/MIPS/syn/ise101/constraints/mips_top.xcf +++ /dev/null @@ -1,13 +0,0 @@ -# Bus clock nets -NET "CLK_I" TNM_NET = "sys_clk"; -TIMESPEC "TS_clk" = PERIOD "sys_clk" 9.9 ns HIGH 50 %; - -NET "cpu_clk" TNM_NET = "cpu_clk"; -TIMESPEC "TS_cpu_clk" = PERIOD "cpu_clk" 9.9 ns HIGH 50 %; - -BEGIN MODEL biu - INST inst_bin_fifo ram_style = distributed; - INST inst_bout_fifo ram_style = distributed; - INST inst_write_fifo ram_style = distributed; -END; - diff --git a/lib/CPUs/MIPS/syn/ise101/mips_top.prj b/lib/CPUs/MIPS/syn/ise101/mips_top.prj deleted file mode 100644 index ea45b69..0000000 --- a/lib/CPUs/MIPS/syn/ise101/mips_top.prj +++ /dev/null @@ -1,21 +0,0 @@ -vhdl work "../../../../FIFO/src/fifo_ctrl_pkg.vhd" -vhdl work "../../../../FIFO/src/gray_counter.vhd" -vhdl work "../../../../misc/dpram_2w2r.vhd" -vhdl work "../../../../misc/dpram_1w1r.vhd" -vhdl work "../../../../FIFO/src/fifo_sync_ctrl.vhd" -vhdl work "../../../../FIFO/src/fifo_async_ctrl.vhd" -vhdl work "../../src/core/mips_types.vhd" -vhdl work "../../../../FIFO/src/fifo_sync.vhd" -vhdl work "../../../../FIFO/src/fifo_async.vhd" -vhdl work "../../src/core/mips_shifter.vhd" -vhdl work "../../src/core/mips_reg.vhd" -vhdl work "../../src/core/mips_muldiv.vhd" -vhdl work "../../src/core/mips_instr.vhd" -vhdl work "../../src/core/mips_icache.vhd" -vhdl work "../../src/core/mips_dcache.vhd" -vhdl work "../../src/core/mips_bcu.vhd" -vhdl work "../../src/core/mips_alu.vhd" -vhdl work "../../src/core/mips_pipeline.vhd" -vhdl work "../../src/core/mips_cop.vhd" -vhdl work "../../src/core/mips_biu.vhd" -vhdl work "../../src/core/mips_top.vhd" diff --git a/lib/CPUs/MIPS/syn/ise101/mips_top_vhdl.prj b/lib/CPUs/MIPS/syn/ise101/mips_top_vhdl.prj deleted file mode 100644 index 7676319..0000000 --- a/lib/CPUs/MIPS/syn/ise101/mips_top_vhdl.prj +++ /dev/null @@ -1,21 +0,0 @@ -vhdl work "W:\vhdl\lib\FIFO\src\fifo_ctrl_pkg.vhd" -vhdl work "W:\vhdl\lib\FIFO\src\gray_counter.vhd" -vhdl work "W:\vhdl\lib\misc\dpram_2w2r.vhd" -vhdl work "W:\vhdl\lib\misc\dpram_1w1r.vhd" -vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync_ctrl.vhd" -vhdl work "W:\vhdl\lib\FIFO\src\fifo_async_ctrl.vhd" -vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_types.vhd" -vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync.vhd" -vhdl work "W:\vhdl\lib\FIFO\src\fifo_async.vhd" -vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_shifter.vhd" -vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_reg.vhd" -vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_muldiv.vhd" -vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_instr.vhd" -vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_icache.vhd" -vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_dcache.vhd" -vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_bcu.vhd" -vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_alu.vhd" -vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_pipeline.vhd" -vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_cop.vhd" -vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_biu.vhd" -vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_top.vhd" diff --git a/lib/CPUs/MIPS/todo.txt b/lib/CPUs/MIPS/todo.txt deleted file mode 100644 index 551e1a0..0000000 --- a/lib/CPUs/MIPS/todo.txt +++ /dev/null @@ -1,35 +0,0 @@ -2008-10-26 -- Area-Optimierung: DIV und MUL verwenden gleiche Ressourcen -- Area-Optimierung: MUL32x32 primitive für Virtex-4 -- shifter: log shifter besser als built-in sll, srl, sra? Nein (2008-10-27) -- External COP 1..3 interface -- FPU (COP1) -- MMU - -2008-10-27 -- Area vs. speed : Pipeline-stall statt forwarding -- Caches: - Lock-up free cache (refill critical word first then un-lock CPU) (geringer Effekt, zu kompliziert => geringere Zuverlässigkeit) - - 1,2,4-way assoziative - - 2nd-Level cache in System - - Write-back policy - -2008-11-15 -- Bus exceptions IBE DBE (BUI/Cache restart notwendig) - -2009-03-18 -- cache line sizes von 1 word (4 bytes) gibt NULL-vector. Fehler in Berechnung der inedx_widths - -2009-8-8 -- Soft-Reset. Ähnlich wie Exception (Reset/NMI). Speicherung von EPC (done) -- CP_COND - -2009-10-17 -- Soft-reset implemetiert. Register werden wie bei normaler Exception verändert. - TodO: Bei Soft-reset (laut Buch) KUc=0, IEc=0 und BEV=1 initialisieren - -- Uncached write: Geht wie bei cached-write in den Write-Buffer. Folge: Mögliche lange Latenz bis uncached memory-mapped I/O tatsächlich geschieben wird. - Könnte bei IRQ acknowledging Probleme bereiten (z.b. mehrfaches (unötiges) anspringen der ISR, obwohl IRQ schon acknowleded wurde). - Work-around: Nach schreiben von memory-mapped I/O, gleiche Adresse zurücklesen (lesen wartet bis write-buffer leer). - -2010-01-09 -- COP dependency einführen => Pipeline stall, wenn COP Daten nicht verfügbar diff --git a/lib/CPUs/MIPS/tools/Makefile b/lib/CPUs/MIPS/tools/Makefile deleted file mode 100644 index 852df6b..0000000 --- a/lib/CPUs/MIPS/tools/Makefile +++ /dev/null @@ -1,20 +0,0 @@ -CFLAGS=-O2 -CC=gcc -PREFIX=/usr/local -all: romgen ramgen flashgen - -romgen: ./src/romgen.c - $(CC) $(CFLAGS) ./src/romgen.c -lm -o ./romgen - -ramgen: ./src/ramgen.c - $(CC) $(CFLAGS) ./src/ramgen.c -lm -o ./ramgen - -flashgen: ./src/flashgen.c - $(CC) $(CFLAGS) ./src/flashgen.c -lm -o ./flashgen - -install: - cp romgen $(PREFIX)/bin - cp ramgen $(PREFIX)/bin - cp flashgen $(PREFIX)/bin -clean: - rm -rf romgen* ramgen* flashgen* diff --git a/lib/CPUs/MIPS/tools/flashgen.exe b/lib/CPUs/MIPS/tools/flashgen.exe deleted file mode 100644 index da4a7c1bf30a7cb7349ac7322e39dd126ace3567..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 12196 zcmeHNe{fXA9p58IjS?g+QRx(?Pv_!~7GnaJ1D&W>l3=Jo0!h%R;Nz0KB-h-pzPo5_ zu@f3H!%dn_rq&Ma=oCl(;16d?9mGIU521uQ*g?%7GPTpRh4yITG_}-HOSyi&yZe6g zLmj}G4m-2AZ$JCp&-cgM-S^(^t@y?WD`JfKkqZUJMp04<^WXFT^rQLOFYmdQ?Y#QU zn?`+&Z{F0>9Zf4KJ=vv4;!1lYkw|8gHcioc6G}9p)U9k*;>ixJV)pE70+PC^p0P%s zpM7*jU(UY3*eV}m6YQ#@S-u%dSTTe?hdcwhRAv<1I;sOFyU~T0C>U!Jl~-S6+%Luy z(U%CQ50WfICCu1n;=jzPBBS+XpmQ_%M+T9vMhC659HrK&+NX*tA=+`443!U%&O@9ch%dIvqy$Ax3D?8{Bt+^uU~rC8yij@ z^k2^g4wOFf=(_#c4~O^OO7g9vG&!=zA6nDAacch6jKS3Wt`{w-MyO0>FFZm@?!fdF|pIsa9XKMm^Kdc(eWe?8T^i!g! z2@F4*{}=kAIlrX9FN${;q0jKs`TwBWh;C(p{43zi1_M=ZLt#sxn3U#!BCz~MQD*m# z;=*QCzE29QmjYwlTG)L1?>WK4gu|vvDl>r+Fu*33-5?ZD5NAq?_tCJsRDoH8rde<| zgl6H*Gk+%{-y01;hVR?ZJ_NA9GCU?6`#%3jEVhO>^N-{vW_OAv*GIV!Y&gh!c_6Qw1rq0!(y=+ktcW$=?Wl;y&S~Ope=z z% z>rRnlpnGKU+EGt~MHymagr*gO+UK_Y!;7`+I^eAO~jG@Z}uF(beZ}J_( zq(b?2bQ&2UIZB1{cU|=fS3T#dA9B^-bJfRP^&_r&-c^5r*Dd?Dx!Mo7>Qj!oHQ!4R zufgBW*)$HX#%lfBQB>u2Kf`Oq?;|i{wIyFfEj!RpzeAgN%Ywe^!)U4O=S5i=7NO^M zKtr~+bgZ@yBAC1^o4#$VwxNlOG=_Q6RLP4Lg%^QR^vf2F)y~V!CA#^g999@F>ZY#) zC~jK*J2akZHw;Yq$7+MLD2&xE5k(EHfMd1cFpB&(XqLnA6c(h{i-~}q(fO|s!RuAI zfsYEAKaMTsj%ME(<&G{DjxObnR=u5ls-GNqipa797jU@r#4M~ki09CX;x$9PrOiX@ zN+wH&R{4i~7{R^|d^7Gks!!A6C}zg+YhY!qd+3>;JwDn1R|cj^j8zHN5|V!boc2Y! zP`)$l9Dm1L^}~)j>{(}D<3DM=P(JG5E0mw+b(n>>O?u}PC0$=hmp=k}8!Jy&bjBj- z?uxc(f<4~GTGNp(?QVr*U0On^i6&CL8KpBC)9$^7)$4jvSCT0$5lwV)P$^GebNLOw zqVb|c0F%*79ZMP8hWZv8)(7mgt!@g-3;)*`D??V07a-RlHz2P??nB;$Jc7Ihc`NdE zR+kq;q{BTpbtAyYafOF#4)=~C;slc{Q#meDmWks+PcsK+Ci3`l=rY9|f$P>``@ zJ~bLo_3E0M%IIi&c}9CA7E891+}~!jKhgDgG@(Wl8BI?_V!(=uI$|-kUC&gi>awP) zs+6Xy_&9FY@TqopQD=KBnbxRpq^L8cqhBYkJBm7WEz-d>D$&|g)S1?_9;O#{X0%w0 z4HR`gu17Px-vj=*seipcuEozrJ3oB9@DsAGi-jX^4+gxRwO%m zV_HKb(Gk<=9)vGm7Llo{Ks3M`W@X@hpnmm(^^J=b3J|)kq|Yn@eyQ2V6gIby7gm4c%Gk%DI+Q>c-_bFe zd5N{5jXeD`1SnXaV;#u^pXvWK5hL;w5-IZC;ozXk#j=^Ws*p=@Yt9u_!yX|+em#sH zpME5qH->W0EXD01En+t-uy{VAK_kaRs_FB?fduQ^NT>`!mNJsL-^1MKVSd-m6Qo7g zp)0h*!#v_)Zt*ZrxOsvb+(_txRKC^ zhdJkAZt^g{=jI90=b$srdp*oYJj@Lq=5aSqFy%%1DrN* z^)OF+nAduk^KPEtCN~nA@Gz5VfS8rE%}iHTx>&1(F$YtI&3p}a>EgT2f$Eb`&!cf} znc&EUWkRP6Pkpm2hvb#HA{oA$tHeCRLIbJZX6Q1IVAzd>{Dv;`d7*fimw1>DxOsx> z-AHJYhq=m=)b|axFlNn9yUgR)mKKt|Ch?tO}(b9ze^QfztKHX?3Hv1bF zhOUvBa%38jUmWmwx&xhHHZxcCV51ueEpT|+igv+#c2CjF=q)?PwL`|dr=~r=HE73# zw53ntyMlhy`>by}@+mXz@%=WB?>oWa^u5WAglbIRji}OT89*yyi)nA!!Bc(A%@gc* zBcX8*bE$_p>|s9a<_UJYkC8BJ^>vcj3qe!mRAgbYO$p>w5+b$5vNhsc#5!yX}X z>Fs$Q_Jlu%JwoQv+e4$W>0{UeRSnoMddrdDN}~*bSB9Y{1IU8#d*F5{|T9M z#m5*Mm(lm&Gv~8e`c8}UIsFnci~Ed`;G69X4r-r)Ukk|yIijQ&Tir;o#zN%W0l{rNSGeBfjZncT`d3w8`bd3Ls*&vV)B_euJWhQLtm-Cc%=J?hhE9Hp6Ltm@L z+m7J51qdBvlJ5ekCIpGjR0KkAawKCRQ7)s{kO3gXVafbV_Oh6N;X(ETnSc^%5W3#< z$ovjS%Jd6@?C&IlL~DcSRRCheklJph2GeF$OFS0UlL=!*5xwq~GM0t(rEWz-RcY^4 zB|4j5^j&2ks@zKLhcSGAgSUN)%Y<#c`X#d!pC1D`0%=S8^FVeukX=B;vq_PjjsdYe zRpo~5h(r5v$WWp}Tz-JUSjS`|dgRe=X`cfm3? zmWj1)A7LkU4G1$Zh-_P-`5PL6Ln;5XS{u9WpmV z=77mV%vC@p9LRk@awejR;{-P0;8_6~GSTv@lMsi^eO$&qF9v~t#@6d8AX7j{RNRZ_ zaJkcg{2a(h2eKE)r~`S22prlcfEcSft&sdMgdK5sK_3UkGev0sJdnc<<{N>~=(aqq z213a~mH`UcnJncq;_zT2`*Mmp zL&A`hos657lB*OR6VU`5OQszjMdSEKfJy^OuxsrZayAl+b|vCCH03CQugcYh-wD_K zkoVI(9=*^2;I~@_MXhz*Yp%&S))dh(1cig`raMO68aKviF3fYXT1UXreDNHU1F?#~ zPejFpQW4ha!6lfqqkX*L2YMy!2S#*&c^oWJAjuq$mFulzZpiW?e>w)NobUW+YS os78p2&jrg-JDq6rs=4sobZEif1?Wp20pRm6V-8&5k~r%BA8kC!rvLx| diff --git a/lib/CPUs/MIPS/tools/flashgen_big.exe b/lib/CPUs/MIPS/tools/flashgen_big.exe deleted file mode 100644 index 6837b3dcd8adce731cf1b781e0b42f8b3cd08091..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 12301 zcmeHNeQcH089%qZ=tYX$j80g_vTJhdbivxf<$|W$uC$dh3sh*)Dfsrb_icOE`?Y&- z5gleFg~gk$TN7u3nJ&2S2g&?{WT*wnEW#)n+z3{qnOi!B@nXB!ZA_UXbie0(yq^Ws zfMyFPIrqHhcb@Y*&-0v*_q^xaRre3FQpT7UacYXOA*2){{P*HNy(qr^>-(=~duP6O zUvSrL#OG%a{*B*C3W4`ej7IwWB<6(i>HHiiEKyk@1~p+%Cof zqAn3o9R!((OoXw=i2rjAm3e)09&Mf_`$!?Om5i~30BdTk%*LYmC}RzT2M|fuGDJ&= zu&PL9TP{aXgnp{%#~pfE)o^88@Nt_XkfAoOx66WW*p6Jy{l9vkrSNXwgs<<^MW!_GnAMpk!{Sj8Y6VNM%2JHcS{i}Q% z3$GTA9z5yadJ?M&J2*Cf=JCR-2S27f)|i8*k)L_=&_Mns2Kn*x^e}MX8{}i;H;%tQ zu*s5Nzpih>-@nn<-&0mt5G=lrW(x<$uN`=vP~k(xKSYzQ@b10q*KM6xFq1KuUR;4mRXl;8AzDicbwOYC zFn+xQ+lwDgO%=Ss;u|RJd(`Kd^V45KqQAcEMHYy#{*1SJw1E?d#(0SC{K0)q6%Qx}d8RV!O z6vc9mOiBb*iX|L53uGT@x1YPdG3b*{Z-#?NcWBdqa(XtcSPKCcBl=@zb{)#B*V+aID|g zAMs9&pzoFCU0R*w%?*Xg;tZIIr)o zlOq^)P*;w@F+8IR`gimB6V~+f=BY)J9f5(v@b>xpb@n0_dQb*`ZU5t(ZKJSiq}IC|N%io)r+CiyH#labw(Kj&75aMV zw|^TiSy;Rwf|9C9o|Knk(R*eOS}4@|M`|}i1e2Q;ayO6EHVku-#yvb~+R2mVL7oKt zs8=W*shwX{PIL=;IULCFq^^|`J~3GFhcupQxAaYTM`}Z~XpGb@6G;uNxFfZZ2$JG1 zv@D0?Su9vD`-p({1jTO>!OPXdeIHNdPmV0-h8A8Q;)X64hA!uZR-Y(5-b)5NPGp6? zOBn1wJqzoSSg+Uj_xRWKZ!8-x>%Yg_@4*Q6{KHdn``g(`T0F(f7pSJs=BFx#YfEPM-fL6#}FqFDV&w57wxKWrQ5iTXa(A;#|VXz^sGC#!3jd=_Odl(a_^iF7;3eNfW=aOXqulon6r^=vAd z09INWOC+@RY`#jXus8))RQ@#>(6F@LMrz3jGV#!+>Bg4 zo6xykB^JBx@vPAEtJ1Nagx(NM#S%L8LFDp9;hE}6cmuoAdo7QdT7Y-%_u=UREmQJm4%G)XgsJ>3j(NiDNcf% zp^{!a01qRc$2+{!quxxFeC8>6`h09cyqFbXl=mtbq>QaVq|Gs}MF6`WaVMfc)Iu<6 zAj)>p7U}%262=yw+zg+_c0Z~K+s*pwNuB;s9*v+aeh#FHd5RUKjr_A7B;?|2SS+35 z>qF8&44oxX>bcd%L7B^?GjYWbdwE;ak0_;&kRiM7Lk(20gv+ImYHLi{&cqp5aOncL zl*U`BLYB}+gbfMRIgxNVoGfMJ8Q!FexzWY^mXjw$OSP@7@E#X42~eLJ8ZK>iF^@TU zLR*|j_^6B7?_v(Qn1`J_p$$$XyxGMZa52}on2$PnLNO;29&|BRxtQsM1EA@jCGR+S zLiAB*lL;SiF-Kg?4KC(UCr>EjM8b6PAls5-qshfw=VCtYOQyv)UX*vS)Wbt2(yF6Nys z=2jQ;gp()qm=g(47|bYQKS12WnJ>PE3mMEoPZR3Tr>aKyY@@|z)K?Fxcjz_YUMCVBbust4m?JLcV@{q>mlFx^Fql!q z$jU+07btNCWtWhlkvYRD@~L(^0o10xovwF?_;-jqKY>0%=F02yCiL0!3G@*%S6-j@ zpwI9p&_~EzS$)*lIL`G!TWSqoy3jQ;hoHB8HZ?nuFx^c^897hKOlId75L4ef0r2n< zWwf4mwSLaoR%nM4346_2@+)Z+GV&`a+ReWL0LajliY5s%c{=i4J*jS-@Bp=2QB+n; zH@}>AO(!GoqXS^R(A<&x@I~dSbq_r`R#CYJIBUp|p7tPlLO%!0t+>cnB=KCxKWc1z zj<$!Mx|q(=c6#Mq&@Q=;qB}n!Gu!SQ~tcb8WWLo2LKP|tPCi- z44!8pVPg(8IFWEbdCag~@LK14m5cd+lP7ea6A5oHnT6*=KXJ+|nRFscV@6vjVl)Ox zXMl*BJfLfZQRXScJUORmHjo@+w@5_PB4inmNjXpHJdYn3vR;nRE`ElO% zT1ABn?eZv?-dF_0^dXhCkPLW)KAN7|6wjtpYDEzQNhxD$_#+#lX>?+%5uL@ZpNYzf zSsuWOuYTp{U0fz&sr4JlZ2IRFAjiRMw*DrNJvQVt$=G`EV<4ubnmXnMi8)&4%S98S z(yJ9f)H+5eV~YtvYPP-{NCXH~7BZ{p(dY|J9)phom8W6ypjv#(knNhrPnx6lK7G)} z15TD91i|#iBS1_IY4qaQn*|KJ#JM|anut7ZZ?*ZS0G?h`M(d!zn2`|{yPkl|Q6LbL zmi`Kenw7%#=YUW!WsU;bZA0E98HmdNbX@%rhC@g}SrWGN`sCSBJy$;AR8*>v7TCq%>yMRzIk%xhd0s*SQ} z{V|bWxN5y%Lo|6ov(u*GA0T6{03c+42cq8iLg#BS2JN=b1M-&9dIfUYz46p4+-udY zZC;m;X7fE6#*eqH`Sx^b6Aiw2G_`mU)ADJpE#7GXI}btWMW)i=6=U zlWjd|Ot*vidQ>!(uT-S^VhGMIlZSaUjyIXVw93%wl zn%Ar~ca4xSWwM}|97f+|8>QHfW!fYGH5E8c`UER5SH#bz2iIqijUin2rkin+iTKB@9 zt6yEmRZxm|>CueUAfZUcO2$>o$b}7WmUs$=rE@lm;z|7VK%)UA*!A{285>Q+J5x#A z&Tun-rdqETCJ_Gc}wd4RCq@T3Ip2>b5!0OH|p9L>e*S% zyJo4rc=gGFSk1Q}aWSDZ_%&uNKp%0XdiPw{tQD*XLf0YBLiWmxf?G#*;AA(t@Dc@M4WhF69>)D* z%qRL10rf$Wg{XuWdxH2s=Tw^2yR*=FlKdls$X9a4lzgnAxilRKXTyxu5$;1KTZ@rR zDa6V`r7f8ZK_U7nqaSDLVP(UmQNhQ34nc-=-e{Et->?8Awp=Z*%=;D=397suzcAwQPkBQue>0%h4h>op`1;or zZO$FdjUGJZ-F6DA3OhKyc+ThCJfE%E1%LT&Eg#PtI&lKkqPs=1|I|13W-F>jD)=D+A!@Py~4 zm3JQ9diIFtCf0k{`_RLi59K~m{6jR^a_`>1al^LBC36^q>-k$Ssq(+Z&k(I8xf*{_ z`7nMx1AY0Arl)frfBpqD_C8+Zn*Wm@K%&34__xd#V*TBo+$O&#SLM%pU{&96?#TS@ zKPQSR|G=~PkI@&+`4!XrqG+EReFmP&{|nW6bX(}pzYN}7z+Zj>3LE`Jq%{Au!1CKf znL9Lu3zJp(ZYj_#1xC2Fu=%z>bAks5hfQTvX8pxrfK4p7RVbh!&XyD(pkbfa2ebML zX2IPcnuRx0)bZuB2m?JCLi;#T-z2Z&dOr_X-xTUFqVF6^5ws&bboU(TI|JzMBYp3q zSbd~#f&}4w5xn(q+n}uuM09Ofxx~*Mxq})4{`@MG1NzzW;fEg9HXq9GMzudw{K{8g z(eH3AJj;Tx#$Sxlxd8s;{{fs6q9gAn#!J4FI1!2c<&YvPz(jYr6*!ll_=C_V?h|gx z#F%M_-9b0|ORzGg5=WX@pdEKyYm#zJ2Xzn!-%9la@pma^l# zShx_2+H-rLAy@4ksqTgdCNIlnZXKzv+sQ@h2YJ!Z!;8igFZ^Eg%ehCY7kd{H-I8Vw z`xAIf6fc=c~THnpjjL%x1E*Y}$O_!YKb(n=G3%$dNlCH0%%SRyH!b&ow zZLx5sqqHTOV2`x0rcAh9zstw5c0J*%iY8KBSzlW;rhoGWR+~;I)4pU%Pec>#9Q2iB zZn(UnYZCvH5y0drq{vFfcA>t*gmnWuZ>krB<%Q?lj4ed=AumO)LasyJgxrn19eEIW z2l7tj-N<{84e_ot>NRiRmZ2=UGBElSTdti->|zal}5idTu0n(X+0caI+bYcbhl-6y_2Qg zZCO1QW4-RSN7B(O?{}{!UeMp{iRsTb2;OoPh0-|g#lZe}O zyM==)SITDMiXb<0T{Dj;Wsi^{zaBsjbTFkWWslM|tbAu;56oY=1Rqf>m1Bu zcAh}Wjs$6ELh6!Zqs+lv<6u5+=Lyi;gVpAp4(5=9d6R=VZ|4bYwHgQK>=9)Ybmui)0R=%q>p>naZ zP$3n&lrDt?LUttRQMwAx%9Mk7g@gI9ohQ(2M}pfO%smd~W(V`6ohR^w9SKern9;<( zhdjucFTI8f8Ct^|(0?&?Eu{Z!v=kNks|$5^#%J5t7Qe&OJ?I3pjrAu`Z%2YlEuK;& z1oO9Js=U?V`(AKZeQ&TM z!K#Aq%8LdEGwmQ-cq&fYc>+ClBsk_^Zgwz-9L&e;Jb?~765LT>MiV11Q|exz#h#R3 zLWZJ>VPi{I>h2Kj?~!{xg*`&%>f7@c>>2zN_6V7)Z_j(MXXmG|N61`Vd(_z2!|j1C zwT4$Nb&Sj**ln2wfkrzLq_YbtBj@R`!EFBmV(NRx2Od7(3)-^|?dR>f0z2$T&|~zH zUrA$-kzYySPW}}DK&FmFI8Knk)0XY%N_1j}2dLGHQRT%<^ULnnOfvF3+6U%~u59A@ zzHFh=?xHK(Dk|Rr&J|?HPHU3y^MRiM=3ZRlE0TCF79TY>K1bgJ&s@r8={voGUDPij zQ`xOXf@_{NIH>&>{8~mv$Pp#I*l9-sRR$vG4gj8vS?N=LshLvoJR~g4fjT=9^r?sy zd>6dt`A(;!7M_X&cAmfkb|kpTU>1G_er%Vin6e|4k%BHXF&cwpGeBfbZqS8bjIj%` zNX{vm4J60dZ4wc^2w4H-xSXf7pT{>0Su;oQCPN~Oj!xCvjzGRcJYM0uKsqEdoty}y zSIQX3GhD{U|05)1UIaq%Gh|N4UW5vn(+=b#AZiyv$Z%1MJzg}ZRaD5(TOK7N8q0tf zF{HL8k^zsfN7EBqqUmHpttf&ZE@cc0e`rB8jdpA`qBHsRQ_)#5%MDoZ)vw~bi_3&e zy?!H^jrhC<eE|@) zs?!R|k5HHoJq<4ckWtSRp}hvkF$;485L(I%n>&C|GLT1si~#|;^x{WAX#FveUpRWb zWI;4}K+|Kf@Q;u&RsayPzX4HCd|~tT7=u>d7Xdk0&|ZR?c7HUn2IpGU>l-&@!|7~S zit+7jbGL_DLO5qTCLU z8QS`$wT-LS)M^bIYMW}-Y3pn2*Hvrvt2Z=af}z=LW(y*s(c3L<1Og-kY8uzAH{=s> z^f4U+qLz(i4Ec*6`Dt1v`k1aI+eo;zlgA_~bXXhGdPYxg(Yf|`_`Aupmg#EAJetYs zaczs9&P0<5X*x{ojv2b)3?Weq($Sg8c5+8Wn^;*i`;lKL02#croBLioaxW$r4S#v1G>LQ8bRf9%wY61iRjvC1=C2XnP`#(^-xp_?ldh z_?@ub4|zWe=dhO>0Q`2#plH>Wd(Abe^HUKWB`6$hEx4oV#<)?(#xT#yYMeDo^Tnf2 z4#aZ)3KA6)N<&;D<_6p&Zj^j7BMvwmn<+l>;XraUfE;l~2-P8RfwFK0E|D3Bh;=rI zdm&GlWjFbTB5U%P+Zga!4lfqqk&sKpIBi1}CW65v?2mLstY|og+D}VH8;)ceeEuHw2 tfF4`EObZhgp9_YgW;)U4RCD>cY0-lJCD6w|0>I~CwlHvoOX5ET{|4eZ2J!#^ diff --git a/lib/CPUs/MIPS/tools/ramgen.exe b/lib/CPUs/MIPS/tools/ramgen.exe deleted file mode 100644 index 9fe37512eaccbaadeff021643bdba15031e3b85b..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 22930 zcmeHP4|H5rnSW^p$b{4eEl{!OBP2AzHe}LiTGAFKolI#UZ9_6CRa##sGcU>5$;>!2 z>7U&e%Sq!h#<<-B=U5e7JmM}Z;P&jPI!%$Lv}@2u-e|(E zxF|}J7rwY(Vf|7RmA54TYJ)>ucwvj8j1&GJ`KZt6J2H^Dk@`mpQD3PumP1uKw$!I0 zp-c$fx*8P?IIqE};F_DTj!`5 z`Qf?Q`$jW2DRaK*dfx-CYgXO*FS}m-j_Vp_=y>J5AKQE^``gi{7Z5-2?%D7R99#kF zLPFhLkZu8{f_W)reFmGsl zR>x^q_0Vxwc2~9Q2*oHE4u6%OY^pBH&jt6X-M>0SbXfaWy|a}H*mvsGz|`r@XHE_L zih7X+=V6M@=y3&FUyk18KaEI0<+1Bgk)!t6V09UF3LIAxN5A06QEZ{ka4ycVm^fB* z4r);jp8QQz_EzWCk@=`WC%A7eIRah^i!l>+{%AbkKv3Y3e z)N?Cwj0=t&#;QQiy~Ob)aEt`zV}u_lfdWwR=!Me552I=gQ}a0PsOS01pytT#`MJCx zfO9=GEz3`l4BX@@J)9La`5y@)?CYZPgiz!V1;a6B(sr0M$a=a24f9tMht)vM0xmzo z+Zv`k{XQFKMb6JT%W`XElZ}ohkE6**;0*Qh#>-gi?6IS-&!W-KMbPLj*2OAng`OOG zfN;n=p!sYff^X~~h@R7=GLe4^L>idfhl*G>57vCE)D3{xaiskIQXuw@OZL(^O=djdEhI%BSNX`i|KS0qQJZRcF2Q{ zOdBSayk`QHkT<~^N_nC)PwrMy&s=@gM;`COJH3Ie!6GAgSn$XTEe}b$`CBw>_D4sQ`n_Y=oY=ZN02zBn{xQob!X?3&W}Ldpw-@kPNgwxo!r zdE(ePA0 zCC|;>4Gy_F&&g#8*KLE)TCKIYE3lSAWI zyz<|_o1PvTFMZ`-UqgDbuREvG(vKve>;9=txD_b^nIS{Kn8u^S&s~_FChU4rZhm!+ z@(HTR|AYv`IaE^?@egGvt*FkiEP|?^K{d}J4x`HRUC-$wwCXaahw3A&B?0STG)s37 z>aj7(C6FkH)!D3GW@EmNn1>HS1zS>KK$oMw?h&eIAw#4Vv`_Pi`~sR{G(g~~#i7|q zEx!FM8qE3DFkN_VF+7f27CKHnMYpFPIe@>Xo+1v@Conh3Fu-HU#`VBrfq*Ul6bM*E z02eq|vhjKaI8Z)B$%b?7WXZ-U&S3<&L!w0v^QXWYA6gEd`g_Sin<7&;uGd$IW7vVI zQ`x#c8wt!gs-eKk79sS2l!fvvfw@fxVtOB9OQ8t1;9#rZe8G_`Hg#AQ^BN{M3u!ZE zF)x8*WV0TegR`7-ntA+Z$sfqw_i@gP+C<*L zvMu-@n>Ex`=*6nC z5tf?pf%t1`x|ld9BJ8KOVte&<(QM{4@eK-yG{Q3u!jC1#jDwKl9L6B*r!t&{+n7&{ z{EblM{^OM4$OMY*h@tT_EP;Y=iv;R-XwEq;In+sxS$6IRlsnyu+==gJx^o^(9OO?& zC?}#M>I}*wgJmO|DG?~kO_Dj_?W4nMUgyE%6>0$WVBq{C1Uu|Q4dqV{BI7}NWj=+u z57o$@Cg$w@Dyr=H4K<=zbTfEH7zC9n2=JKayZk{64Fi-gtN(|TGnju$nhdW1kmrZi zL`y<{AN6&QP(4L8nnmfzfXBaPBEm3`F&Kg3uC{k zh{x7~JO46bKH9o+o#62NmYAtOaQPTjAE9dUIYJey5Li%sgsLBg(Z`AY zl%OA4ga*!Ra*8-cBsLtS0Qad5ZfB?k*Miria z?nBif6>?ZQh?q5ZWcVyK3&PFdbpWd5F@z6c{vRPbM-5OTd4b4BxUw)+%)d;!>#qts zl08ONm(et>A+4COSFW9&p3V=VjPQeDT*iA)kt^60=TAT~&`ew7(ed5ce;Yblwvt|f zq$=-!g|0(xWf5J^y;64+_u0wp^CM*=KG*al_`5OB@x*#wcJK`ZsqE$pWG#wBi=hFY zWaA0;Y-j;V%JkLGZ}BPjPmPn^XdT&fb&g^@QK`I4+*?Ll3i3*)L(Z34g`=QOXYOp}!-0SNvZ! z9-s>!)cgo}o`2WSlxxE8r8R59zl>j2&>M^izt4wD{xL{qjy9@azzc`%%7mHg2hpS}fB zJ<9eTrM+!cXG`Zt)V4q%u)JL9?h3Hm`mSKB*1rCZHoxZaG$=wlI#CBM zQH9t3N?={EE%*_&Cat!0l`HO!L@I+zElzhhw$<%!rcVJ>0~vs*(2LU}iNOrj;Gz!3 z)6u@T9;vN~sFB3>cqXAX)KR*D_S=p2MY))aP$ZI)QfA^JtVlF|DK>W<5CiL4(MjB} z7wRpY{xxmEfIryX8KAzeUo9;F%y1%}&V=F_HKHdo{c5us4`l{Zp_tmdQmu&q0zB!# zp3Kgqu5M4HB3eepcN8-!={6ZdsZ?kuXJ@x+ZG#HK)I{pkM6bXS_%I$Mrs>O!W?my3 zH?J&LRCUoJwPsoUvW+wz8>`rDm9o%6?$P_A@p7fJWv$kEPczu?p+{Ixr)x2+Y#`j* zLaAt|C#GYBBl-?YKU1N2pRO|1m4 z1)c?JreB9>Hr8$dz7iePqVbI0r>AOZa4n9}SVtq|X29F^+J-tC4CrpMLoGw9t6ggP zliR&wr3w$Q(m0Y1b)vmiRF55%e8-OKSt5a#)k$0{%?j4&0CQqBE|yrHCIieyw4yC` zpcU%2*dy^8y>&*fZB!0OQ&5FbECyp0rakCRxB_aZ#HK|cl}e=4L{g7qT-Dwv+@dDU z#&FR)c9g?uH$+qTmS&N+S-msZa);WU2u1W1D&DE1+#PLb&{lP?z5@+JIs;vSpa4mwGZu_aoq8(U7FD1t&@P&$^_XnRq9l_Of|PBr5EBns zU2ED_OIhjuXs?h4eR<7AWd&QMw`3wwLl)Xn#YJ0oceJ(y142>Z9t424qUxf}gRRne zGm(V!Tx!gW9F4Q_ahjHSbGiHDnNXh=i)a*jDL@RS^^`{AQfu5Ti0Qpp^!Q>e`6-~F zBHowjr&(c;krmibj0%%~krA{StW7cTs41qPm^l{M?YgMKDAF8EN0W(WI4fVe)LJxR zt|8|yp|C-~m5n1jo3B%DTBSI!|OtM=>X(%DqFLootwY$7L8BJf(Ai|+#KNA+4FohD_0c&QwENVL{2cheGJ8HnOT zQeLjaqCKflYNy)0uC1$WE!I?s7KQo^{=`5s5!d6HbbTlWmu9&m&+Vi%k!D*{Y~+`A z9-cAVSPFP##w-(2)skV+7_)rLfh#lix7CJc+%q^&(k# zN9TGZ*MXK+q}MEGli8QqtoEW=FO3QVxu+Am5o?leagK$CUvAeaac6VYntxk(MTio) zw5&i>EzHZ^#g&w894UH3U0of84Oxw(8@ki{py|hQX`>1&0I|Mpd;s2v)$AQO%5PLx zV;%JON0aF=a$5D)dJkyt0P>j@|J`;|Wm&egEoeTjjia>!pwYfPgwQg>{xg63u zVxdfLA~k@FX_e}y4O=;-Lmllc!PVbZ{+3nk0j;I;jxP1y7*Z{@iojN)sP_jN7}Vq8ohzFf*ip3^xF)r#(aY)TF4fa$+zMt87aKIs5_SvPQg&BG8v0W@GGL^m zNIDa7rd>bwgGfK`wRK1I9N~a5s$t%)VKafO$JT@I31}-BON6&FAli{2Pe~8PGBcoM zLa9DV52<~%kX!BV3b4#M2%7|gnlu)futBYsMThM+Gl?YnElDIsL!t+EK|g3@kc6`_ zDBk%@D5-`9Gx%XeMh|DSaDND?RDs@XThJO<-O}A2Waha8z^yF1SKC^p81`hLN^YsT zHde`sXhdyf_t6y3-Db31Qibs}gUwKcb`lY8kZ2?fZ7+eqcOIJHb;2-RFecji4%HYN zmTI&3$-@MHlGHWG}{%F=19e1>lw%tg( zF*LLmldD|9v6CuWF*Rx2l<6pJe3+f2O*PmJzHJO;)nfl*Omrrz=rklxwBciCU>~?5 z_;{RGRpYJqZsd=gfIb5@o0Nlb>m(_^C~r8HK;k46mxU5On zZ|jfXf~}6Yqd2Q{r$c>uvx+#44Ys;MY?bhk<2H3gd~l$iEmkV6c?eBvPc)OhjoFRH z=}+nKZ85cZxJOYAp!}GHb^x@wA(O{>Hy?EiaW2EziZh6F6V85|yKwHu`54Y8aUR6^ zG|uBVpT~I;=OoT4oELB^kX3`O(S+BWt4lPjwRpUtB{M11JuxekNkkRpTeHGQ(Gy|f|Mjf!&c5x@ID2B5!jo9g zN=qZLm=;cD8Z>QnhsTq|23qXQlu&7JGKC<}3%(xQ4`#wjm|fFKq!cS{D5B_e)fHuH zX>VHBw<@X9-i#iLDMO{b+bO7#+`C)@h7Oxt1NuNXxs&MoUCG3Dy15KcLdi!iOB*u3 zaT%rqB0aIpvh?-t6093*6OqA~zJ{&HEnwL4?ws6Wo_bgbGJMKh$hj-fxh~MYxRDbf z_s_>4Yyp=*C{a{pR!MQVYppzr{PiLcsX=K8xj`uvjia8u7cq+9G4JJ_{M90rsdXuS z3FCrKW^g+d&c*odR!h>!-n^z|H0^D}soT(RDS7@7#mluyp9$fK?8|OIQ3$s>? zay$KfucXKcui^(roJaPZ%Oaf@T?4kDOLDyV5^s|fl0~V49b#&DA_39Rwt!tAwUF=K&Iaz+L0e9Kz`MU;&>xYO4DNn$i4#PJq5^9P8{zpC#C6R0dhwH@wK^Pd0zqYX9|!nIB~oWI4MmR3XmTyK;Bh=oOj}Q>0=+e&d(PhA1FZH zQGk5biQ~;UDNV-8Trr4z8lea zzicHbOI%VPN%1};rAtcFJfjuie}w+bBU@g4-Qhg6?$9@#Xka;hKg%P9a2&Fy9r$Pt zLd;cWX@{Y+wEWYkx6K_dt)MnaQ>$SO5|qTrk&E|~c<#r!he-#Ik+T{4lx#r#@4x1% zqIJ={PQ=v%1%2OG(D&oOvGvp&bW)l&8GV;l9WOxMSAhJ66UX}*C#8wfDj{9ye4+q3 zWAcbqX3~k{rSY)!qUq@ZohJ*B_ZA?Zcj9>WI4Mn&1~RG?nvv%ja&b?P7UMkR^OsRG z+wpdMUPViutJ@%q!c%mI9|K-;4lA!0S!9fl6-aL| zTZuj6&%wj@jJ=_)Y)=G&IQr>L3GPjt-c0{sd@G)JnX*JoSR;FZ8t3s&%^k58G|q(p zX6F*RbHry6e=4Ph#rDg>K93qWgl0eFp85*l%w!)qf`7!mdmo3IyzfPH7JZ+0>Ao*L zAU&Z3zh8D7{|EhQBo$b{q=zqg(n;~IFe$?8s1+T?{&Z=(?3aO)L%j{zyT(arS|%-K z_G!1-O`Y23fh2Dxe|PnIWgaV<2mI?;K4f;xZ0#oF382M5g@6?3bp| zQ*Dg|Sgb*rj!DtP18Scki|Rhlczl*tv}>_w$RDdKTWqbK0nb^maeXxLh+DPsd=ETN z8$7sCUIvA)deS$34T{}9vqkVlg|OjupvZVgR7I&J9*mG_jisRYK%@%J zq0-P0mS>OpPnZ;qJ(CaFeWS~U15CUDpubi-CqOYZq*;I$11nZ32ZtTQR%CB*@m zLo!7AW#PEVqxI51?xRjv`t@n>oB_q``{zKBvzzz*YoNSpi#d@N4l_PCAmGf*zrD8B?nJ_q2fUIRtuew=a@Z6FK{HSr>8 zpRHdX1dm)nsPF8>l=7&J=XUVO^@}5~2W8Tx&%K~fNHlwz289ljvKN#*C{R@N^lw0+ zsAW?AuAtSkHi{-*cb&IsNWa~-#{~Mlx6CfM&hMp%H-Gbwd(~^30@vY;3$mmLU9^E{9KB4WZQY9w;3Ec&9FL>p^C9YaD28uE2k_FHQMr!n1v48K z$KZ&;r61z3*V>oz1~&FmE5B{vnI!oNnwv^8^6rF1aE1zO7{Zng%eV2Uv!j}?@P+z( zO%z_~VcANQPdxHEtj_!;xu(I&5i1*pk1>b^93zJ}lf|qh)(64PvKDGXepWC75Gdck z8}PzS1B;A8N#kln_Z-FWKRc0H|IkJZ)M?%|w8J3tpgVU4wQMdf&kMa?QbP8V8p+^&l)hwSgW zf8O5&T5a7w$9K-ld-uEF{e9p4?sxC^-S^&P{l`X>VntCrI436+C66l|0rvOufA*mI zJs&#s9_4`ddpG5an!a~axI3Oz)0tFPCeouuBgtecr*`OSrZ=g^lWN1pR<$P;)2n99 zDymwTcoiQj~G!n&O#7Ggc@!fN3ty892+ui3`(?%Ak|pXu__z zC`y_aJl|DVzZ6B~Z3%$d;1CyH*s3U_g#SlAs&e|y9AtJ=|41R~D|N7V2v2)i9e~WC`xM$VOs@~uE zet2%y$Z+n%%It4>u6@As{x!FLx9|0Dd)}|~pD4fYe>?olLgEMBJ)4fe!4;q` zCe+5rcgdC1`&1Y7z;!3@R73 zj~@a?U??>Aa4G2hqcfUc@>KMn@C=44JTM$}>8D#NN(vR=KE3-j82Yu&SxOm9dp`dj zRG#iR|5E#z(>&asd= zEptwe&k@J-lH>X*IG!MmuY+T#eIE4l96bTTT~M%u6jVt(?hj6Y%7z5QnNn+7*th}1 zVCUw!&Ii1EfrsXKHgIIW8$cz7!uP2L&Lz$AAv_h!f=nQ=HfoowUkd9rLakzn+!_4b^FOg9Sn>b3@LGpQKZ!)v+nVn!RJWjY|$Z1Xe zY0hCN-+}VV_VL-ngTRCe!#gjYyK#is>oFkqAE%*YI=;v`cSmV9G(ZNKj`ZT@gJp(8 z6XfC=7>97{uVA%LN+Uc3`mJwfzf9oyrv*5gkpVu%!TY|<=l{y~Gh?9%;48ahLa7h3 zW>P27tbsKhJ9mP9kR}37{a`o0Qcr1AwEx2ocSXJ0Jjwkg|NUq$h0O$ zz}TVk<5anvR~oK#J(c|xhsYTD9>Nz>s_-ak`cEwOjo$Zht^Ii6eqsdBq3xW>GZZKz z$Jx%=m_Kn&CLdNicdCE1_?4G0PEPXiYRjvz1ugomd(UsdtyuEOHX{T|-Z=1`3zL(C zn}ksj3Gx&lsHX5iQeYsDYKjV9FF|QlMV>_ks=fq%9u*Fw%J-b_rK4;W75yJ#EeZH5 zU^GjAMPiO0qVRwSBKmGt@3b+0jF<-wKm`_UWXv(3??nBgN2&fW*&ahjQG)XBfCv@P z6e9rw4;8nEFf)>s!SV@>Lkas z0ckEc5RmdLSfZOyl*OdN-%wMyf1U*-UQ_s_z%yqW+#U+EW#@Y{Sw9a^EaGuU&a5DB zW?1Aw&MBkTRI#Ys(PS$%A$2HflJTHu;T(uV1LP_cla5l}#A4FX`52pZZ1`Ao0(;>o z0YF=(I$z&trf`Fg)40td4wMhwgx1bz>!}0BIjlZ3l9-s>IVwSABN>tEZ4newuSpU| zKsCCGC)$$Ri-I|s;Q>364jkti9@%LmQA3@NnAKXHI|US zn3v1)3#7hmg1{OOwU4lFkQ~!S;tO6o=8Gt=WHWyD@FRfb=BIdk6N|@rN9sYS74GBZ6_Ar~@7)Kdb zOAb>AloRLkw6t5sEk|V;qFAh!6X^{H=bfC>jO;QMD4gV+Wo%Jp`dh}H#p@d-2aDJ6 zKQ?QK6?(CFeUYM<>;rQ{cqLn8!NKD7PbjE`<{n~knpP(fxC?hna11}6Di-l9X#c$c zpHe{oil`SQgTcc7L--s_(yOIwa?9~C~%+h@RfFf5TA$5SZ;Har6qhI zx~OTEz-dKDQ(IaOu)4e^Bp$+A;##iq)NGa1Y1%=!L2@9DyM~Dk!UbAXEx!38mEkPh z*a zL`l>cl!tmthT16+KrA40V0ecI*1gFWk3~W~GSE-yejtDv%AX!Y#)I_A+*KbzHS(vi z+55hNDtmrIjc6_U1bBuR1eKZy@VM_ezPF}ffD&f)Y8&&1hPdtI=5vH9q7Yb6{bi~ir)rcBb)(uDEcX+~5pb+z9o*eJ6q?sR zT0S_i0^J?nu88L$+;p^gvql0A#zwV448uPGYG{C!FbUU!y?lsap{JyCe%_h@pXa9y zp?zN>QyuvT)RRjVO@qSq;9!RNC`zocG#k3M6F7yd1P2)w7NBL~aiYIU9)vC*T!NO) zZ1N;=JTEx%7+V+iCF1xxIQE_(Htj5ZN_Y9!8t86<=;sFrq#J0(DSCY{3@iW zY=2Q0K`*eqz{4+=y5f0NVK+#H613=lvuO5T--1&Ao5e%-duH#u8uu{W@S_D9k8c+K z3*L^77G}Q6Zc6f=U_h=>g{y_k{7fRUaVh)*YTS7CthC0HOeC6yV)bsqI@F|e7a2@oMTDYgRmp#cq7ilKU z3t~ur3_1YKQ8FGP-aYtl{l`jH(iDz5MU<-`~q zh7AX6LN5}~1jBLeM^d551qaY*WQ6$Wm|XC>qkPIyKJO?i5qtYlNBxVA@)<|@f}>n; zl+QZK`yJ(zj&h!r&Hj08`kBvf%V5uemuBxfg6=Z=7A!lkCzkN*6w;g&_>uV6d9w(ZL_(Sx49Kj;>)H_5E=0 z!9CQ02MKJj{|X&0e`V(6k)}9(MC5 zAHzq1sJwT9SjRcp9GYub26V^H(?YW-F9O-i$^|hsmfDfbrPS(00Pr@aGC5o-aeAYPZIa)RMm*lAJ{4V2yxHE4 z+^)2)?nq@~T293~=;;IjC6?;V5e_a>vq2Q;6xz@LW8j9pFs*M1u4@d3g5kE75ZP$s zT4^cBH-$$snaD1#0=rc!t5tMzL2Qwl>J<6`5^bWXWHuK`<~Wfv*I5bxsasvDsOpj> z>Vg$jD>jn_HqU3b^OeOGa&ybZ^;%1)zM-yE>Cn64NpRvFd{ob7D`Cq;C<-#k^~O8Z zOgtM;c4>O7OJ^KvBpFkqy1H6j=v%1fx^+M>US=$H)oP1gmARA_Pv-P4JyS_TYZ=O# zMT^*AdUe3XJ88`5PUwOnm6%CGnM^99rqX&6dZ?Z8gbq5Bx#S%?N@2K7@eJOxFY(u@ zcZTclP@7Vbn4Uq!J9U(LyM zE>*?RXi}?7$=SRF) z=}A2kkDBU|m9*fx`o;~Up^uzwQzX%=lMiS090yRd@tjWX9MiYQqk5IvoXTe79T>yy z#G9>CD}9S=7B5vX#QsI-pJ^1xB&!7Lo7p@Pwuz*3y&0Xkw5-A8Ok;j_VqsFl_01|~ zOD>a2BrtkjZ$nG)E{g>h3#&re27D`_W-te`IUW8bK%fWKuNJklHyO>vG4FuU5^4>F z1xO~FvtYF7)Kl4ZN(EX&O`>U5PspZhrZPDZNZAexG4YVqx~_4pl$Gs{cM56Hm)BfY zR=7cWOD+~SWT7opT()Ifb3=VNBor0yK>%ngsxI3++#sDd7fVUcrN+$2@gy4`r)ilt zmwG>ui*#v;m_`c(Eg!vEJ)_aMR2p{+6MAP(1_8-WYcnd6UAb(G(MpnqmrynPaKjp^GYvBF({UJe{h8v+}i5twbZ{8gl*;3L6Am**L{fevsxI@eD9@D;7? zW0H+k8cK-u+O}MKOH0%7>=g|n99s4>Ww8lUC}kbFR3#gnD_V;+de^MwQpsYol;NQ% zn}0h4m~7VYgc+H1Xu=Q>LDpDRTA-zOeC{QZQIb;+PEGu z6{1CZa%D}dTs%8io@HZk@yM)BCR(Z`4`3&pY%ZoHQeE*V8OYK;D&r71 zVWw)C~Jw?sffk@&X>3jIshNqB{rlntEB2KiS5S1Xd#nq$w|}WAP;HOukK1hi;6unf!rR z-!{Gglv(D@h)VCkQF^nw7V#|D9ZzSY$W7H-t9+on1ISC30H-z8n?a6EDb_9FU=wni zNDtexY%7h%)CxVhy%JlD=GNfG=Fp-oTRP&&EnAYg(kyQl&FW;)s$4WtTAD=5Y&rt8 zI3_&u&APg%)Vi+jBc+hmoQUK)Q<)xQK5Nuq1ld_Br8Uh>_2IP}Th?nJYr*<8O(Ctm z<&IYMz64Sxbv}WuMpeyxb$(|?|MOlw8QrzIwwfLD+ktCR=hyf-UF}nSHO8%A263rD z^DSeype<*2^GU;CMn@)#v=YfjjQJP2XD}>yNU~7nFz+u=V6xO7%$b{8ug)BO3*Ulu8 z=(i-17!8R&*aiKdkwG%e#$f8s=OSq}(woD_(>Xnw)1uuGq(m;gS$f|PT3g@N6lUhR z1HcU|OII5kq!_kaoiDdWt()h|ig-+|VfXP2&%vg(U0Q|lG=t4hgmwfmZjg8^3T>}| zz;_Uu;B~?GY}4UW8?pJy^sI1r>kgHt5vC}Gxe3~?F#&i@mKFm(irW))9-!_JF z{?cF#COVTfxL|d7Kw;Dv(u%b1qIgD#W!~T#5F_ zly{4wX;|knIx=dKy$t0ZEWC98D@E(1;8BbBTx*Lo#9=(b(9*dK>b@}}l1s%E<>?tw zq~WP3@&9^8bXV7oc#=Ik%OE2Mt++UrNNCYau3FR9Hv4>OY?8(1Q;8IJrZZR|I>Fb0 z``%nsiLz@}i4`LXM`DUjS6xxI6?bNJeVdXg?#$_lgwkK!xq}uwl6#k@$IxMmr$_IJ zrgstjVNW`>gKn+@lu+`~tFng7Z(fC|f+#>NGc0|*y9hC5eJa+Q(ATkOT@Qw>@6O3B z=Bt90AS0m6ft;hj=f5nqt2*t{~i7vi=V=XAZ$ zS|i(aJSu-o^5BYBnm9-BEe&hMD7WM9NqnuyDRRP3yiZbO-?=Q(dHEbg`KYaTZ>R5g zvn~40#M}PJUw;vC2F~K5yRWq|pnw&lgY5IS(1Mh>T8ZHq0C7EKP^8Wyf>K;W-(%R1 zcS>hMZNfRqWKHc+QXkGk{o0HczrX)n)`sGjb}D`mMD{6G_;27Umal_J$=?jhvI8jD zDEr_Afbx;pCW`({_)PXNc(Q-9b=soi4qU0U^| z3wgwae9?*H|E!ZzOKFvmE_5DuA?HjU5oN}mIDQ%rTQ6##ap^qaLf+>>o^ay$_c$rF z;|4OS6q=Fb!qerw(qf#4eEuqGVLRTA&#P$3b9EbpQFsb>oyq*t4*#Gdh&;Ng45&d4^lCjvnn-Sid(_a;tfuDdt64bQtw zSz=AtEPH_(=kZR>9bx&JIS|0?Tts({^;xVx1-7^nLD?`@Vd?^n@b(TGVm;5A>^sRABv*9=_~JC&jKA(ytORWKDdUYT_PGI+QxHcw@ydm`n05wPxsxiOA=jB9XBB0Sfvn-3 zbUc$v%5{k2bcj|aGUZ2Rzch`WYHK9GVhzf4Oo}ERP&XU0sP69=Pr%ZOb}beS`D1k@ zZEJM|JZHhi_0hy5?rIy)^Wb^L;K7aZGf;TclfLn5Q0(@ZB^F;)2pir2id+wgswkDj zgAp>Vu^f~Dh*ZIOf^=(mf+k)fsD_5HJbTnXZc;S%Og>`wjaC~DF!2U}{#xyv0>#vj zW&vIlC?h5^duyR66DCExq~N)_w8s6wIcf4}o%D~ps1ufceFi*dKr#FN5GZnX^S(a; z%Ih{B_8&}al;^>7z(%2;q>=H2XNp%8Jm;4ho(Io_t<@W#jM^wyLp9RQoRxou;zb+J zM?l$cP&7DwjJ($vFH|Y3z$3E)%t7%=h3E59pH1K~*B@#X1LY*HxS%r{e@UZ^8dfEq zELB37so`gdVw3(w#$%lq-vEV7WVSj8ipS=MW1zeU9%{_T;uLOA*eJgM<${g!Dk$I>@>N%>XKfTszV4Dw571gsegYo*ns5;mnO$&eypJB< z7}lUx^FcX}E0!d&QenOqC(r`Z)#AC622Ky zH1QIV-WlR$q@|=qQ$0PYWMGA&#Zp>2tM}rP(dq4@rls}x(iOED{taI)-lKCe*3yiD zm(J*<&Qd3##!2uw38aRG?=8ZO>qA;|YpAVZBR zdm^7mWiRwOFs!=ueGn_4Q%YCRzcgqGfDClG&hxGun!WZiEm?*r`$Fh|;pLpbTh|c^axu(I&F)JH}k1>bn<1tFtZ=-}EoS -#include -#include -#include - -#define INT8 char -#define INT16 short -#define INT32 long -#define UINT8 unsigned char -#define UINT16 unsigned short -#define UINT32 unsigned long -#define INT int -#define UINT unsigned int -#define FLOAT32 float -#define FLOAT64 double - -#define SDRAM_BASE 0x40000000 -#define FLASH_OFFSET 0x00000000 - -#define MAGIC_EB 0x4A464931 // "JFI1" in big-endian; -#define MAGIC_EL 0x3149464A // "JFI1" in little-endian; - -UINT32 conv_endian32(UINT32 src) -{ - UINT32 dst; - - dst = (0xFF000000 & (src << 24)) - | (0x00FF0000 & (src << 8)) - | (0x0000FF00 & (src >> 8)) - | (0x000000FF & (src >> 24)); - - return dst; -}; - -// -------------------------------------------------------------- -typedef struct _sflash_img_hdr_t -{ - UINT32 magic; - UINT32 target_addr; - UINT32 img_offset; - UINT32 img_size; - UINT32 hdr_next; - UINT8 img_name[128]; - UINT8 res[108]; - -} flash_img_hdr_t; - -// -------------------------------------------------------------- -void basename(char *pSrc, char *pDst) -{ - int i, size; - - size = strlen(pSrc); - - while(pSrc[size] != '.') - size--; - - for (i=0; i < size; i++) - pDst[i] = pSrc[i]; - - pDst[i] = 0; - -} - -// -------------------------------------------------------------- -int main(int argc, char *argv[]) -{ - char *pFilenameIn; - char name_flash[1024]; - char name_prj[1024]; - char *pBuf; - UINT32 *pBuf32; - flash_img_hdr_t img_hdr = {0}; - - FILE *pFile; - int filesize; - long start, end; - int i; - - if (argc < 2) - { - fprintf(stderr, "Usage: flashgen [-{EL|EB}]\n"); - return 1; - } - - pFilenameIn = argv[1]; - pFile = fopen(pFilenameIn, "rb"); - if (!pFile) - { - fprintf(stderr, "Error opening file %s\n", pFilenameIn); - return 1; - } - - basename(pFilenameIn, name_prj); - sprintf(name_flash, "%s.flash.bin", name_prj); - - // determine filesize - fseek(pFile, 0, SEEK_SET); - start = ftell(pFile); - fseek(pFile, 0, SEEK_END); - end = ftell(pFile); - fseek(pFile, 0, SEEK_SET); - filesize = (end-start); - - pBuf = (char*)malloc(filesize); - fread(pBuf, 1, filesize, pFile); - - fclose(pFile); - - pFile = fopen(name_flash, "wb"); - if (!pFile) - { - fprintf(stderr, "Error opening file %s\n", name_flash); - return 1; - } - - img_hdr.magic = MAGIC_EL; - img_hdr.target_addr = SDRAM_BASE; - img_hdr.img_size = filesize; - img_hdr.img_offset = FLASH_OFFSET + sizeof(flash_img_hdr_t); - img_hdr.hdr_next = FLASH_OFFSET; - - if (argc == 3) - { - if ((argv[2][0] == '-') && (toupper(argv[2][1]) == 'E') && (toupper(argv[2][2]) == 'B')) - { - img_hdr.magic = MAGIC_EB; - pBuf32 = (UINT32*)pBuf; - for (i=0; i < filesize/4; i ++) - pBuf32[i] = conv_endian32(pBuf32[i]); - } - } - fwrite(&img_hdr, sizeof(flash_img_hdr_t), 1, pFile); - fwrite(pBuf, 1, filesize, pFile); - - fclose(pFile); - - return 0; -} - diff --git a/lib/CPUs/MIPS/tools/src/ramgen.c b/lib/CPUs/MIPS/tools/src/ramgen.c deleted file mode 100644 index 8f61118..0000000 --- a/lib/CPUs/MIPS/tools/src/ramgen.c +++ /dev/null @@ -1,385 +0,0 @@ -#include -#include -#include -#include - -#define ARCH_NAME "data" -#define ENT_NAME "ram" -#define JTAG_ADDR_WIDTH 16 - -// -------------------------------------------------------------- -void basename(char *pSrc, char *pDst) -{ - int i, size; - - size = strlen(pSrc); - - while(pSrc[size] != '.') - size--; - - for (i=0; i < size; i++) - pDst[i] = pSrc[i]; - - pDst[i] = 0; - -} - -int SaveRAM(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data) -{ - FILE *pFileIn, *pFileOut; - long start, end; - int i, word, filesize, romsize; - - pFileIn = fopen(pFilenameIn, "rb"); - if (!pFileIn) - { - fprintf(stderr, "Error opening file %s\n", pFilenameIn); - return 1; - } - - pFileOut = fopen(pFilenameOut, "wb"); - if (!pFileOut) - { - fprintf(stderr, "Error opening file %s\n", pFilenameOut); - return 1; - } - - fseek(pFileIn, 0, SEEK_SET); - start = ftell(pFileIn); - fseek(pFileIn, 0, SEEK_END); - end = ftell(pFileIn); - fseek(pFileIn, 0, SEEK_SET); - - filesize = (end-start); - romsize = (int)pow(2, nbits_addr+2); - - // ------------------------------------------------------------------------- - // Header - - // ------------------------------------------------------------------------- - fprintf(pFileOut, "LIBRARY IEEE;\n"); - fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n"); - fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n"); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME); - fprintf(pFileOut, "\tPort\n"); - fprintf(pFileOut, "\t(\n"); - fprintf(pFileOut, "\t\tclk\t\t: in STD_LOGIC;\n"); - fprintf(pFileOut, "\t\tce\t\t: in STD_LOGIC;\n"); - fprintf(pFileOut, "\t\twe\t\t: in unsigned(%d downto 0);\n", nbits_data/8-1); - fprintf(pFileOut, "\t\taddr\t\t: in unsigned(%d downto 0);\n", nbits_data-1); - fprintf(pFileOut, "\t\tdin\t\t: in unsigned(%d downto 0);\n", nbits_data-1); - fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1); - fprintf(pFileOut, "\t);\n"); - fprintf(pFileOut, "END %s;\n", ENT_NAME); - fprintf(pFileOut, "\n"); - - - fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "\tconstant depth : natural := %d;\n", romsize/4); - fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1); - fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1); - - fprintf(pFileOut, "\tsignal sram : word_array_t :=\n"); - fprintf(pFileOut, "\t(\n"); - fprintf(pFileOut, "\n"); - - // ------------------------------------------------------------------------- - // ROM part - // ------------------------------------------------------------------------- - for (i=0; i < filesize; i += sizeof(int)) - { - fread(&word, 1, sizeof(int), pFileIn); - fprintf(pFileOut, "\t\tX\"%8.8X\"", word); - if (i < (romsize-sizeof(int))) - fprintf(pFileOut, ", -- %8.8X\n", i); - else - fprintf(pFileOut, " -- %8.8X\n", i); - } - word = 0; - for (; i < romsize; i += sizeof(int)) - { - fprintf(pFileOut, "\t\tX\"%8.8X\"", word); - if (i < (romsize-sizeof(int))) - fprintf(pFileOut, ", -- %8.8X\n", i); - else - fprintf(pFileOut, " -- %8.8X\n", i); - } - fprintf(pFileOut, "\t);\n"); - fprintf(pFileOut, "\n"); - - // ------------------------------------------------------------------------- - // Trailer - // ------------------------------------------------------------------------- - fprintf(pFileOut, "begin\n", ARCH_NAME); - fprintf(pFileOut, "\n"); - fprintf(pFileOut, "RAM_RW:\n", ARCH_NAME); - fprintf(pFileOut, "\tprocess(clk)\n"); - fprintf(pFileOut, "\tvariable index : natural range 0 to depth-1;\n"); - fprintf(pFileOut, "\tbegin\n"); - fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n"); - fprintf(pFileOut, "\t\t\tindex := to_integer(addr(%d downto 2));\n", nbits_addr+1); - fprintf(pFileOut, "\t\t\tif we(0) = '1' then\n"); - fprintf(pFileOut, "\t\t\t\tsram(index)(7 downto 0)\t\t<= din(7 downto 0);\n"); - fprintf(pFileOut, "\t\t\tend if;\n"); - fprintf(pFileOut, "\t\t\tif we(1) = '1' then\n"); - fprintf(pFileOut, "\t\t\t\tsram(index)(15 downto 8)\t<= din(15 downto 8);\n"); - fprintf(pFileOut, "\t\t\tend if;\n"); - fprintf(pFileOut, "\t\t\tif we(2) = '1' then\n"); - fprintf(pFileOut, "\t\t\t\tsram(index)(23 downto 16)\t<= din(23 downto 16);\n"); - fprintf(pFileOut, "\t\t\tend if;\n"); - fprintf(pFileOut, "\t\t\tif we(3) = '1' then\n"); - fprintf(pFileOut, "\t\t\t\tsram(index)(31 downto 24)\t\t<= din(31 downto 24);\n"); - fprintf(pFileOut, "\t\t\tend if;\n"); - fprintf(pFileOut, "\t\t\tdout <= sram(index);\n"); - fprintf(pFileOut, "\t\tend if;\n"); - fprintf(pFileOut, "\tend process;\n"); - fprintf(pFileOut, "\n"); - fprintf(pFileOut, "end %s;\n", ARCH_NAME); - - return 0; -} - -int SaveRAM_V4LD(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data) -{ - FILE *pFileIn, *pFileOut; - long start, end; - int i, word, filesize, romsize; - - char tpl[] = {"--------------------------------------------------------------------------\n-- Virtex-4: JTAG Loader\n--------------------------------------------------------------------------\n\ti00_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_clk1,\n I => bs_clk0\n\t);\n\t\n\ti01_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_update1,\n I => bs_update0\n\t);\n\n\tBSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 \n\tgeneric map\n\t(\n\t\tJTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)\n\t)\n\tport map \n\t(\n\t\tCAPTURE => bs_capture, -- CAPTURE output from TAP controller\n\t\tDRCK => bs_clk0, -- Data register output for USER functions\n\t\tRESET => bs_rst, -- Reset output from TAP controller\n\t\tSEL => bs_sel, -- USER active output\n\t\tSHIFT => bs_shift, -- SHIFT output from TAP controller\n\t\tTDI => bs_tdi, -- TDI output from TAP controller\n\t\tUPDATE => bs_update0, -- UPDATE output from TAP controller\n\t\tTDO => bs_tdo -- Data input for USER function\n\t);\n\n\tjtag_ld_addr <= user_regi(user_regi'left downto jtag_ld_dout'length);\n\tjtag_ld_din <= user_regi(jtag_ld_dout'length-1 downto 0);\n\tjtag_ld_clk <= bs_update1;\n\tjtag_ld_we <= bs_sel;\n\t\nsipo:\n\tprocess (bs_rst, bs_clk1, bs_tdi, bs_shift)\n\tbegin\n\t\tif bs_rst = '1' then\n\t\t\tuser_regi <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_regi <= bs_tdi & user_regi(user_regi'left downto 1);\n\t\t\tend if;\n\t\tend if;\n\tend process;\t\n\npiso:\n\tprocess (bs_rst, bs_clk1, bs_shift, user_rego)\n\tbegin\n\t\tbs_tdo <= user_rego(0);\n\t\tif bs_rst = '1' then\n\t\t\tuser_rego <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_rego <= user_rego(0) & user_rego(user_rego'left downto 1);\n\t\t\telse\n\t\t\t\tuser_rego <= (user_rego'left downto jtag_ld_dout'length => '0') & jtag_ld_dout;\t\n\t\n\t\t\tend if;\n\t\tend if;\n\tend process;\n\n"}; - - pFileIn = fopen(pFilenameIn, "rb"); - if (!pFileIn) - { - fprintf(stderr, "Error opening file %s\n", pFilenameIn); - return 1; - } - - pFileOut = fopen(pFilenameOut, "wb"); - if (!pFileOut) - { - fprintf(stderr, "Error opening file %s\n", pFilenameOut); - return 1; - } - - fseek(pFileIn, 0, SEEK_SET); - start = ftell(pFileIn); - fseek(pFileIn, 0, SEEK_END); - end = ftell(pFileIn); - fseek(pFileIn, 0, SEEK_SET); - - filesize = (end-start); - romsize = (int)pow(2, nbits_addr+2); - - // ------------------------------------------------------------------------- - // Header - - // ------------------------------------------------------------------------- - fprintf(pFileOut, "LIBRARY IEEE;\n"); - fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n"); - fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n"); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "library UNISIM;\n"); - fprintf(pFileOut, "use UNISIM.VComponents.all;\n"); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME); - fprintf(pFileOut, "\tPort\n"); - fprintf(pFileOut, "\t(\n"); - fprintf(pFileOut, "\t\tclk\t\t: in STD_LOGIC;\n"); - fprintf(pFileOut, "\t\tce\t\t: in STD_LOGIC;\n"); - fprintf(pFileOut, "\t\taddr\t\t: in unsigned(%d downto 0);\n", nbits_data-1); - fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1); - fprintf(pFileOut, "\t);\n"); - fprintf(pFileOut, "END %s;\n", ENT_NAME); - fprintf(pFileOut, "\n"); - - - fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1); - fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1); - - fprintf(pFileOut, "\tsignal jtag_ld_clk\t\t: STD_LOGIC;\n"); - fprintf(pFileOut, "\tsignal jtag_ld_we\t\t: STD_LOGIC;\n"); - fprintf(pFileOut, "\tsignal jtag_ld_addr\t\t: unsigned (%d downto 0);\n", JTAG_ADDR_WIDTH-1); - fprintf(pFileOut, "\tsignal jtag_ld_dout\t\t: unsigned (%d downto 0);\n", nbits_data-1); - fprintf(pFileOut, "\tsignal jtag_ld_din\t\t: unsigned (%d downto 0);\n", nbits_data-1); - fprintf(pFileOut, "\tsignal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;\n"); - fprintf(pFileOut, "\tsignal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;\n"); - fprintf(pFileOut, "\tsignal user_regi, user_rego : unsigned (%d downto 0);\n", 31 + JTAG_ADDR_WIDTH); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "\tsignal word_array : word_array_t :=\n"); - fprintf(pFileOut, "\t(\n"); - fprintf(pFileOut, "\n"); - - // ------------------------------------------------------------------------- - // ROM part - // ------------------------------------------------------------------------- - for (i=0; i < filesize; i += sizeof(int)) - { - fread(&word, 1, sizeof(int), pFileIn); - fprintf(pFileOut, "\t\tX\"%8.8X\"", word); - if (i < (romsize-sizeof(int))) - fprintf(pFileOut, ", -- %8.8X\n", i); - else - fprintf(pFileOut, " -- %8.8X\n", i); - } - word = 0; - for (; i < romsize; i += sizeof(int)) - { - fprintf(pFileOut, "\t\tX\"%8.8X\"", word); - if (i < (romsize-sizeof(int))) - fprintf(pFileOut, ", -- %8.8X\n", i); - else - fprintf(pFileOut, " -- %8.8X\n", i); - } - fprintf(pFileOut, "\t);\n"); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "begin\n", ARCH_NAME); - - fprintf(pFileOut, "\n"); - fprintf(pFileOut, "PROM_READ:\n", ARCH_NAME); - fprintf(pFileOut, "\tprocess(clk)\n"); - fprintf(pFileOut, "\tbegin\n"); - fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n"); - fprintf(pFileOut, "\t\t\tdout <= word_array(to_integer(addr(%d downto 2)));\n", nbits_addr+1); - fprintf(pFileOut, "\t\tend if;\n"); - fprintf(pFileOut, "\tend process;\n"); - fprintf(pFileOut, "\n"); - - // ------------------------------------------------------------------------- - // Trailer - // ------------------------------------------------------------------------- - fprintf(pFileOut, "\n"); - fputs(tpl, pFileOut); - - fprintf(pFileOut, "PROM_WRITE:\n", ARCH_NAME); - fprintf(pFileOut, "\tprocess(jtag_ld_clk, jtag_ld_we)\n"); - fprintf(pFileOut, "\tbegin\n"); - fprintf(pFileOut, "\t\tif rising_edge(jtag_ld_clk) then\n"); - fprintf(pFileOut, "\t\t\tif jtag_ld_we = '1' then\n"); - fprintf(pFileOut, "\t\t\t\tword_array(to_integer(jtag_ld_addr(%d downto 0))) <= jtag_ld_din;\n", nbits_addr-1); - fprintf(pFileOut, "\t\t\telse\n"); - fprintf(pFileOut, "\t\t\t\tjtag_ld_dout <= word_array(to_integer(jtag_ld_addr(%d downto 0)));\n", nbits_addr-1); - fprintf(pFileOut, "\t\t\tend if;\n"); - fprintf(pFileOut, "\t\tend if;\n"); - fprintf(pFileOut, "\tend process;\n"); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "end %s;\n", ARCH_NAME); - return 0; -} - -int SaveRAM_TCL(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data) -{ - FILE *pFileIn, *pFileOut; - long start, end; - int i, word, word_addr, filesize, romsize; - char binstr_addr[33]; - char binstr_data[33]; - - char tpl[] = {"# ---------------------------------------------------------------------\n# For Chipscope 9.1\n# ---------------------------------------------------------------------\n# Source JTAG/TCL frame work\ncd $env(CHIPSCOPE)\\\\bin\\\\nt\nsource csejtag.tcl\n\nnamespace import ::chipscope::*\n\n# Platform USB Cable\nset PLATFORM_USB_CABLE_ARGS [list \"port=USB2\" \"frequency=6000000\"]\n# frequency=\"24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000\"\n\n# Create session\nset handle [::chipscope::csejtag_session create 0]\n\n# Open JTAG and lock\nset open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]\nset lock_result [::chipscope::csejtag_target lock $handle 1000]\n\nset devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]\n\n# Get Device ID\nset devtype \"Virtex-4SX\"\nset devid 2\nset irlength [::chipscope::csejtag_tap get_irlength $handle $devid]\nset idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]\n\nset CSE_OP $CSEJTAG_SHIFT_READWRITE\nset CSE_ES $CSEJTAG_RUN_TEST_IDLE\n\n# Write Program\n"}; - - pFileIn = fopen(pFilenameIn, "rb"); - if (!pFileIn) - { - fprintf(stderr, "Error opening file %s\n", pFilenameIn); - return 1; - } - - pFileOut = fopen(pFilenameOut, "wb"); - if (!pFileOut) - { - fprintf(stderr, "Error opening file %s\n", pFilenameOut); - return 1; - } - - fseek(pFileIn, 0, SEEK_SET); - start = ftell(pFileIn); - fseek(pFileIn, 0, SEEK_END); - end = ftell(pFileIn); - fseek(pFileIn, 0, SEEK_SET); - - filesize = (end-start); - romsize = (int)pow(2, nbits_addr+2); - - // ------------------------------------------------------------------------- - // Header - - // ------------------------------------------------------------------------- - fputs(tpl, pFileOut); - - // ------------------------------------------------------------------------- - // ROM part - // ------------------------------------------------------------------------- - fprintf(pFileOut, "# Assembled from %s\n", pFilenameIn); - fprintf(pFileOut, "# ---------------------------------------------------------------\n"); - fprintf(pFileOut, "# Shift the USER2 Instruction (b1111000011) into the Instruction Register of FPGA\n"); - fprintf(pFileOut, "# User 2\n"); - fprintf(pFileOut, "set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength \"3C3\"]\n\n"); - - word_addr = 0; - for (i=0; i < filesize; i += sizeof(int)) - { - fread(&word, 1, sizeof(int), pFileIn); - fprintf(pFileOut, "::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 %d \"%4.4X%8.8X\"\n", nbits_data + JTAG_ADDR_WIDTH, word_addr, word); - word_addr++; - } - fprintf(pFileOut, "\n"); - - // ------------------------------------------------------------------------- - // Trailer - // ------------------------------------------------------------------------- - fprintf(pFileOut, "::chipscope::csejtag_target unlock $handle\n"); - fprintf(pFileOut, "::chipscope::csejtag_target close $handle\n"); - fprintf(pFileOut, "::chipscope::csejtag_session destroy $handle\n"); - fprintf(pFileOut, "exit\n"); - - return 0; -} - -int main(int argc, char *argv[]) -{ - char *pFilenameIn; - char name_prj[1024]; - char name_rom_tcl[1024]; - char name_rom[1024]; - char name_rom_v4ld[1024]; - - FILE *pFileIn; - int filesize, romsize, nbits_addr, nbits_data; - long start, end; - int word, i; - - if (argc < 2) - { - fprintf(stderr, "Usage: ramgen \n"); - return 1; - } - - pFilenameIn = argv[1]; - if (argc == 3) - nbits_addr = atoi(argv[2]); - - - basename(pFilenameIn, name_prj); - sprintf(name_rom, "%s.vhd", name_prj); - sprintf(name_rom_v4ld, "%s_ld.vhd", name_prj); - sprintf(name_rom_tcl, "%s.tcl", name_prj); - - SaveRAM(pFilenameIn, name_rom, ARCH_NAME, ENT_NAME, nbits_addr, 32); -// SaveROM_V4LD(pFilenameIn, name_rom_v4ld, ARCH_NAME, ENT_NAME, nbits_addr, 32); - SaveRAM_TCL(pFilenameIn, name_rom_tcl, ARCH_NAME, ENT_NAME, nbits_addr, 32); - - - return 0; -} - diff --git a/lib/CPUs/MIPS/tools/src/romgen.c b/lib/CPUs/MIPS/tools/src/romgen.c deleted file mode 100644 index f674a6a..0000000 --- a/lib/CPUs/MIPS/tools/src/romgen.c +++ /dev/null @@ -1,428 +0,0 @@ -#include -#include -#include -#include - -#define INT8 char -#define INT16 short -#define INT32 long -#define UINT8 unsigned char -#define UINT16 unsigned short -#define UINT32 unsigned long -#define INT int -#define UINT unsigned int -#define FLOAT32 float -#define FLOAT64 double - -#define ARCH_NAME "data" -#define ENT_NAME "rom" -#define JTAG_ADDR_WIDTH 16 - -UINT32 g_endianess_EB; - -// -------------------------------------------------------------- -UINT32 conv_endian32(UINT32 src) -{ - UINT32 dst; - - dst = (0xFF000000 & (src << 24)) - | (0x00FF0000 & (src << 8)) - | (0x0000FF00 & (src >> 8)) - | (0x000000FF & (src >> 24)); - - return dst; -}; - -UINT32 to_big_endian32(UINT32 src) -{ -#ifndef NATIVE_IS_BIG_ENDIAN - return conv_endian32(src); -#else - return src; -#endif -} - -UINT32 from_big_endian32(UINT32 src) -{ -#ifndef NATIVE_IS_BIG_ENDIAN - return conv_endian32(src); -#else - return src; -#endif -} - -void basename(char *pSrc, char *pDst) -{ - int i, size; - - size = strlen(pSrc); - - while(pSrc[size] != '.') - size--; - - for (i=0; i < size; i++) - pDst[i] = pSrc[i]; - - pDst[i] = 0; - -} - -int SaveROM(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data) -{ - FILE *pFileIn, *pFileOut; - long start, end; - int i, word, filesize, romsize; - - pFileIn = fopen(pFilenameIn, "rb"); - if (!pFileIn) - { - fprintf(stderr, "Error opening file %s\n", pFilenameIn); - return 1; - } - - pFileOut = fopen(pFilenameOut, "wb"); - if (!pFileOut) - { - fprintf(stderr, "Error opening file %s\n", pFilenameOut); - return 1; - } - - fseek(pFileIn, 0, SEEK_SET); - start = ftell(pFileIn); - fseek(pFileIn, 0, SEEK_END); - end = ftell(pFileIn); - fseek(pFileIn, 0, SEEK_SET); - - filesize = (end-start); - romsize = (int)pow(2, nbits_addr+2); - - // ------------------------------------------------------------------------- - // Header - - // ------------------------------------------------------------------------- - fprintf(pFileOut, "LIBRARY IEEE;\n"); - fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n"); - fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n"); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME); - fprintf(pFileOut, "\tPort\n"); - fprintf(pFileOut, "\t(\n"); - fprintf(pFileOut, "\t\tclk\t\t: in STD_LOGIC;\n"); - fprintf(pFileOut, "\t\tce\t\t: in STD_LOGIC;\n"); - fprintf(pFileOut, "\t\taddr\t\t: in unsigned(%d downto 0);\n", nbits_data-1); - fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1); - fprintf(pFileOut, "\t);\n"); - fprintf(pFileOut, "END %s;\n", ENT_NAME); - fprintf(pFileOut, "\n"); - - - fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1); - fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1); - - fprintf(pFileOut, "\tconstant word_array : word_array_t :=\n"); - fprintf(pFileOut, "\t(\n"); - fprintf(pFileOut, "\n"); - - // ------------------------------------------------------------------------- - // ROM part - // ------------------------------------------------------------------------- - for (i=0; i < filesize; i += sizeof(int)) - { - fread(&word, 1, sizeof(int), pFileIn); - if (g_endianess_EB) - fprintf(pFileOut, "\t\tX\"%8.8X\"", to_big_endian32(word)); - else - fprintf(pFileOut, "\t\tX\"%8.8X\"", word); - - if (i < (romsize-sizeof(int))) - fprintf(pFileOut, ", -- %8.8X\n", i); - else - fprintf(pFileOut, " -- %8.8X\n", i); - } - word = 0; - for (; i < romsize; i += sizeof(int)) - { - fprintf(pFileOut, "\t\tX\"%8.8X\"", word); - if (i < (romsize-sizeof(int))) - fprintf(pFileOut, ", -- %8.8X\n", i); - else - fprintf(pFileOut, " -- %8.8X\n", i); - } - fprintf(pFileOut, "\t);\n"); - fprintf(pFileOut, "\n"); - - // ------------------------------------------------------------------------- - // Trailer - // ------------------------------------------------------------------------- - fprintf(pFileOut, "begin\n", ARCH_NAME); - fprintf(pFileOut, "\n"); - fprintf(pFileOut, "PROM_READ:\n", ARCH_NAME); - fprintf(pFileOut, "\tprocess(clk)\n"); - fprintf(pFileOut, "\tbegin\n"); - fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n"); - fprintf(pFileOut, "\t\t\tdout <= word_array(to_integer(addr(%d downto 2)));\n", nbits_addr+1); - fprintf(pFileOut, "\t\tend if;\n"); - fprintf(pFileOut, "\tend process;\n"); - fprintf(pFileOut, "\n"); - fprintf(pFileOut, "end %s;\n", ARCH_NAME); - - return 0; -} - -int SaveROM_V4LD(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data) -{ - FILE *pFileIn, *pFileOut; - long start, end; - int i, word, filesize, romsize; - - char tpl[] = {"--------------------------------------------------------------------------\n-- Virtex-4: JTAG Loader\n--------------------------------------------------------------------------\n\ti00_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_clk1,\n I => bs_clk0\n\t);\n\t\n\ti01_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_update1,\n I => bs_update0\n\t);\n\n\tBSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 \n\tgeneric map\n\t(\n\t\tJTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)\n\t)\n\tport map \n\t(\n\t\tCAPTURE => bs_capture, -- CAPTURE output from TAP controller\n\t\tDRCK => bs_clk0, -- Data register output for USER functions\n\t\tRESET => bs_rst, -- Reset output from TAP controller\n\t\tSEL => bs_sel, -- USER active output\n\t\tSHIFT => bs_shift, -- SHIFT output from TAP controller\n\t\tTDI => bs_tdi, -- TDI output from TAP controller\n\t\tUPDATE => bs_update0, -- UPDATE output from TAP controller\n\t\tTDO => bs_tdo -- Data input for USER function\n\t);\n\n\tjtag_ld_addr <= user_regi(user_regi'left downto jtag_ld_dout'length);\n\tjtag_ld_din <= user_regi(jtag_ld_dout'length-1 downto 0);\n\tjtag_ld_clk <= bs_update1;\n\tjtag_ld_we <= bs_sel;\n\t\nsipo:\n\tprocess (bs_rst, bs_clk1, bs_tdi, bs_shift)\n\tbegin\n\t\tif bs_rst = '1' then\n\t\t\tuser_regi <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_regi <= bs_tdi & user_regi(user_regi'left downto 1);\n\t\t\tend if;\n\t\tend if;\n\tend process;\t\n\npiso:\n\tprocess (bs_rst, bs_clk1, bs_shift, user_rego)\n\tbegin\n\t\tbs_tdo <= user_rego(0);\n\t\tif bs_rst = '1' then\n\t\t\tuser_rego <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_rego <= user_rego(0) & user_rego(user_rego'left downto 1);\n\t\t\telse\n\t\t\t\tuser_rego <= (user_rego'left downto jtag_ld_dout'length => '0') & jtag_ld_dout;\t\n\t\n\t\t\tend if;\n\t\tend if;\n\tend process;\n\n"}; - - pFileIn = fopen(pFilenameIn, "rb"); - if (!pFileIn) - { - fprintf(stderr, "Error opening file %s\n", pFilenameIn); - return 1; - } - - pFileOut = fopen(pFilenameOut, "wb"); - if (!pFileOut) - { - fprintf(stderr, "Error opening file %s\n", pFilenameOut); - return 1; - } - - fseek(pFileIn, 0, SEEK_SET); - start = ftell(pFileIn); - fseek(pFileIn, 0, SEEK_END); - end = ftell(pFileIn); - fseek(pFileIn, 0, SEEK_SET); - - filesize = (end-start); - romsize = (int)pow(2, nbits_addr+2); - - // ------------------------------------------------------------------------- - // Header - - // ------------------------------------------------------------------------- - fprintf(pFileOut, "LIBRARY IEEE;\n"); - fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n"); - fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n"); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "library UNISIM;\n"); - fprintf(pFileOut, "use UNISIM.VComponents.all;\n"); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME); - fprintf(pFileOut, "\tPort\n"); - fprintf(pFileOut, "\t(\n"); - fprintf(pFileOut, "\t\tclk\t\t: in STD_LOGIC;\n"); - fprintf(pFileOut, "\t\tce\t\t: in STD_LOGIC;\n"); - fprintf(pFileOut, "\t\taddr\t\t: in unsigned(%d downto 0);\n", nbits_data-1); - fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1); - fprintf(pFileOut, "\t);\n"); - fprintf(pFileOut, "END %s;\n", ENT_NAME); - fprintf(pFileOut, "\n"); - - - fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1); - fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1); - - fprintf(pFileOut, "\tsignal jtag_ld_clk\t\t: STD_LOGIC;\n"); - fprintf(pFileOut, "\tsignal jtag_ld_we\t\t: STD_LOGIC;\n"); - fprintf(pFileOut, "\tsignal jtag_ld_addr\t\t: unsigned (%d downto 0);\n", JTAG_ADDR_WIDTH-1); - fprintf(pFileOut, "\tsignal jtag_ld_dout\t\t: unsigned (%d downto 0);\n", nbits_data-1); - fprintf(pFileOut, "\tsignal jtag_ld_din\t\t: unsigned (%d downto 0);\n", nbits_data-1); - fprintf(pFileOut, "\tsignal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;\n"); - fprintf(pFileOut, "\tsignal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;\n"); - fprintf(pFileOut, "\tsignal user_regi, user_rego : unsigned (%d downto 0);\n", 31 + JTAG_ADDR_WIDTH); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "\tsignal word_array : word_array_t :=\n"); - fprintf(pFileOut, "\t(\n"); - fprintf(pFileOut, "\n"); - - // ------------------------------------------------------------------------- - // ROM part - // ------------------------------------------------------------------------- - for (i=0; i < filesize; i += sizeof(int)) - { - fread(&word, 1, sizeof(int), pFileIn); - if (g_endianess_EB) - fprintf(pFileOut, "\t\tX\"%8.8X\"", to_big_endian32(word)); - else - fprintf(pFileOut, "\t\tX\"%8.8X\"", word); - - if (i < (romsize-sizeof(int))) - fprintf(pFileOut, ", -- %8.8X\n", i); - else - fprintf(pFileOut, " -- %8.8X\n", i); - } - word = 0; - for (; i < romsize; i += sizeof(int)) - { - fprintf(pFileOut, "\t\tX\"%8.8X\"", word); - if (i < (romsize-sizeof(int))) - fprintf(pFileOut, ", -- %8.8X\n", i); - else - fprintf(pFileOut, " -- %8.8X\n", i); - } - fprintf(pFileOut, "\t);\n"); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "begin\n", ARCH_NAME); - - fprintf(pFileOut, "\n"); - fprintf(pFileOut, "PROM_READ:\n", ARCH_NAME); - fprintf(pFileOut, "\tprocess(clk)\n"); - fprintf(pFileOut, "\tbegin\n"); - fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n"); - fprintf(pFileOut, "\t\t\tdout <= word_array(to_integer(addr(%d downto 2)));\n", nbits_addr+1); - fprintf(pFileOut, "\t\tend if;\n"); - fprintf(pFileOut, "\tend process;\n"); - fprintf(pFileOut, "\n"); - - // ------------------------------------------------------------------------- - // Trailer - // ------------------------------------------------------------------------- - fprintf(pFileOut, "\n"); - fputs(tpl, pFileOut); - - fprintf(pFileOut, "PROM_WRITE:\n", ARCH_NAME); - fprintf(pFileOut, "\tprocess(jtag_ld_clk, jtag_ld_we)\n"); - fprintf(pFileOut, "\tbegin\n"); - fprintf(pFileOut, "\t\tif rising_edge(jtag_ld_clk) then\n"); - fprintf(pFileOut, "\t\t\tif jtag_ld_we = '1' then\n"); - fprintf(pFileOut, "\t\t\t\tword_array(to_integer(jtag_ld_addr(%d downto 0))) <= jtag_ld_din;\n", nbits_addr-1); - fprintf(pFileOut, "\t\t\telse\n"); - fprintf(pFileOut, "\t\t\t\tjtag_ld_dout <= word_array(to_integer(jtag_ld_addr(%d downto 0)));\n", nbits_addr-1); - fprintf(pFileOut, "\t\t\tend if;\n"); - fprintf(pFileOut, "\t\tend if;\n"); - fprintf(pFileOut, "\tend process;\n"); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "end %s;\n", ARCH_NAME); - return 0; -} - -int SaveROM_TCL(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data) -{ - FILE *pFileIn, *pFileOut; - long start, end; - int i, word, word_addr, filesize, romsize; - char binstr_addr[33]; - char binstr_data[33]; - - char tpl[] = - {"# ---------------------------------------------------------------------\n# For Chipscope 10.1\n# ---------------------------------------------------------------------\n# Source JTAG/TCL frame work\nsource $env(CS_PATH)\\\\csejtag.tcl\n\nnamespace import ::chipscope::*\n\n# Platform USB Cable\n# Create session\nset handle [::chipscope::csejtag_session create 0]\n\n# Open JTAG and lock\nset open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 \"port=USB2\" \"frequency=6000000\"]\n# frequency=\"24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000\"\n\nset lock_result [::chipscope::csejtag_target lock $handle 1000]\n\nset devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]\n\n# Get Device ID\nset devtype \"Virtex-4SX\"\nset devid 2\nset irlength [::chipscope::csejtag_tap get_irlength $handle $devid]\nset idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]\n\nset CSE_OP $CSEJTAG_SHIFT_READWRITE\nset CSE_ES $CSEJTAG_RUN_TEST_IDLE\n\n# Write Program\n"}; - - pFileIn = fopen(pFilenameIn, "rb"); - if (!pFileIn) - { - fprintf(stderr, "Error opening file %s\n", pFilenameIn); - return 1; - } - - pFileOut = fopen(pFilenameOut, "wb"); - if (!pFileOut) - { - fprintf(stderr, "Error opening file %s\n", pFilenameOut); - return 1; - } - - fseek(pFileIn, 0, SEEK_SET); - start = ftell(pFileIn); - fseek(pFileIn, 0, SEEK_END); - end = ftell(pFileIn); - fseek(pFileIn, 0, SEEK_SET); - - filesize = (end-start); - romsize = (int)pow(2, nbits_addr+2); - - // ------------------------------------------------------------------------- - // Header - - // ------------------------------------------------------------------------- - fputs(tpl, pFileOut); - - // ------------------------------------------------------------------------- - // ROM part - // ------------------------------------------------------------------------- - fprintf(pFileOut, "# Assembled from %s\n", pFilenameIn); - fprintf(pFileOut, "# ---------------------------------------------------------------\n"); - fprintf(pFileOut, "# Shift the USER1 Instruction (b1111000010) into the Instruction Register of FPGA\n"); - fprintf(pFileOut, "# User 1\n"); - fprintf(pFileOut, "set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength \"3C2\"]\n\n"); - - word_addr = 0; - for (i=0; i < filesize; i += sizeof(int)) - { - fread(&word, 1, sizeof(int), pFileIn); - if (g_endianess_EB) - fprintf(pFileOut, "::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 %d \"%4.4X%8.8X\"\n", nbits_data + JTAG_ADDR_WIDTH, word_addr, to_big_endian32(word)); - else - fprintf(pFileOut, "::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 %d \"%4.4X%8.8X\"\n", nbits_data + JTAG_ADDR_WIDTH, word_addr, word); - word_addr++; - } - fprintf(pFileOut, "\n"); - - // ------------------------------------------------------------------------- - // Trailer - // ------------------------------------------------------------------------- - fprintf(pFileOut, "::chipscope::csejtag_target unlock $handle\n"); - fprintf(pFileOut, "::chipscope::csejtag_target close $handle\n"); - fprintf(pFileOut, "::chipscope::csejtag_session destroy $handle\n"); - fprintf(pFileOut, "exit\n"); - - return 0; -} - -int main(int argc, char *argv[]) -{ - char *pFilenameIn; - char name_prj[1024]; - char name_rom[1024]; - char name_rom_v4ld[1024]; - char name_rom_tcl[1024]; - - FILE *pFileIn; - int filesize, romsize, nbits_addr, nbits_data; - long start, end; - int word, i; - - if (argc < 2) - { - fprintf(stderr, "Usage: romgen [-{EL|EB}]\n"); - return 1; - } - - pFilenameIn = argv[1]; - nbits_addr = atoi(argv[2]); - - g_endianess_EB = 0; - if (argc == 4) - { - if ((argv[3][0] == '-') && (toupper(argv[3][1]) == 'E') && (toupper(argv[3][2]) == 'B')) - g_endianess_EB = 1; - } - - basename(pFilenameIn, name_prj); - sprintf(name_rom, "%s.vhd", name_prj); - sprintf(name_rom_v4ld, "%s_ld.vhd", name_prj); - sprintf(name_rom_tcl, "%s.tcl", name_prj); - - SaveROM(pFilenameIn, name_rom, ARCH_NAME, ENT_NAME, nbits_addr, 32); - SaveROM_V4LD(pFilenameIn, name_rom_v4ld, ARCH_NAME, ENT_NAME, nbits_addr, 32); - SaveROM_TCL(pFilenameIn, name_rom_tcl, ARCH_NAME, ENT_NAME, nbits_addr, 32); - - - return 0; -} - diff --git a/lib/FIFO/sim/tb_fifo_async.fdo b/lib/FIFO/sim/tb_fifo_async.fdo deleted file mode 100644 index c164ab6..0000000 --- a/lib/FIFO/sim/tb_fifo_async.fdo +++ /dev/null @@ -1,16 +0,0 @@ -## NOTE: Do not edit this file. -## -vlib work -vcom -explicit -93 "../src/fifo_ctrl_pkg.vhd" -vcom -explicit -93 "../src/gray_counter.vhd" -vcom -explicit -93 "../../rams/dpram_1w1r2c_ro_sim.vhd" -vcom -explicit -93 "../src/fifo_async_ctrl.vhd" -vcom -explicit -93 "../src/fifo_async.vhd" -vcom -explicit -93 "../src/tb_fifo_async.vhd" -vsim -t 1ps -lib work tb_fifo_async -view wave -do {tb_fifo_async.wdo} -view structure -view signals - -run 5us diff --git a/lib/FIFO/sim/tb_fifo_async.wdo b/lib/FIFO/sim/tb_fifo_async.wdo deleted file mode 100644 index 4b40ab1..0000000 --- a/lib/FIFO/sim/tb_fifo_async.wdo +++ /dev/null @@ -1,39 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_fifo_async/rst -add wave -noupdate -format Logic /tb_fifo_async/clk_w -add wave -noupdate -format Literal -radix hexadecimal /tb_fifo_async/din -add wave -noupdate -format Logic /tb_fifo_async/fifo_full -add wave -noupdate -format Logic /tb_fifo_async/we -add wave -noupdate -format Logic /tb_fifo_async/write_en -add wave -noupdate -format Logic /tb_fifo_async/clk_r -add wave -noupdate -format Literal -radix hexadecimal /tb_fifo_async/dout -add wave -noupdate -format Logic /tb_fifo_async/fifo_empty -add wave -noupdate -format Logic /tb_fifo_async/re -add wave -noupdate -format Logic /tb_fifo_async/read_en -add wave -noupdate -format Logic /tb_fifo_async/fifo_almost_full -add wave -noupdate -format Logic /tb_fifo_async/fifo_almost_empty -add wave -noupdate -format Literal -radix hexadecimal /tb_fifo_async/ref_r -add wave -noupdate -format Logic /tb_fifo_async/uut/inst_fifo_async_ctrl/empty -add wave -noupdate -format Logic /tb_fifo_async/uut/inst_fifo_async_ctrl/full -add wave -noupdate -format Logic /tb_fifo_async/uut/pre_full -add wave -noupdate -format Logic /tb_fifo_async/uut/pre_empty -add wave -noupdate -format Literal /tb_fifo_async/uut/ptr_w -add wave -noupdate -format Literal /tb_fifo_async/uut/ptr_r -add wave -noupdate -format Logic /tb_fifo_async/uut/inst_fifo_async_ctrl/rinc -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {155864 ps} 0} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -update -WaveRestoreZoom {112771 ps} {210880 ps} diff --git a/lib/FIFO/sim/tb_fifo_sync.fdo b/lib/FIFO/sim/tb_fifo_sync.fdo deleted file mode 100644 index 6922e87..0000000 --- a/lib/FIFO/sim/tb_fifo_sync.fdo +++ /dev/null @@ -1,15 +0,0 @@ -## NOTE: Do not edit this file. -## -vlib work -vcom -explicit -93 "../src/fifo_ctrl_pkg.vhd" -vcom -explicit -93 "../../rams/dpram_1w1r2c_ro_sim.vhd" -vcom -explicit -93 "../src/fifo_sync_ctrl.vhd" -vcom -explicit -93 "../src/fifo_sync.vhd" -vcom -explicit -93 "../src/tb_fifo_sync.vhd" -vsim -t 1ps -lib work tb_fifo_sync -view wave -do {tb_fifo_sync.wdo} -view structure -view signals - -run 5us diff --git a/lib/FIFO/sim/tb_fifo_sync.wdo b/lib/FIFO/sim/tb_fifo_sync.wdo deleted file mode 100644 index 6888c72..0000000 --- a/lib/FIFO/sim/tb_fifo_sync.wdo +++ /dev/null @@ -1,31 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_fifo_sync/rst -add wave -noupdate -format Logic /tb_fifo_sync/clk -add wave -noupdate -format Literal -radix hexadecimal /tb_fifo_sync/din -add wave -noupdate -format Logic /tb_fifo_sync/fifo_full -add wave -noupdate -format Logic /tb_fifo_sync/fifo_almost_full -add wave -noupdate -format Logic /tb_fifo_sync/we -add wave -noupdate -format Literal -radix hexadecimal /tb_fifo_sync/dout -add wave -noupdate -format Logic /tb_fifo_sync/fifo_empty -add wave -noupdate -format Logic /tb_fifo_sync/fifo_almost_empty -add wave -noupdate -format Logic /tb_fifo_sync/re -add wave -noupdate -format Logic /tb_fifo_sync/write_en -add wave -noupdate -format Logic /tb_fifo_sync/read_en -add wave -noupdate -format Literal -radix hexadecimal /tb_fifo_sync/ref_r -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {1360023 ps} 0} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -update -WaveRestoreZoom {4760828 ps} {5012588 ps} diff --git a/lib/FIFO/sim/tb_gray_counter.fdo b/lib/FIFO/sim/tb_gray_counter.fdo deleted file mode 100644 index b619f71..0000000 --- a/lib/FIFO/sim/tb_gray_counter.fdo +++ /dev/null @@ -1,13 +0,0 @@ -## NOTE: Do not edit this file. -## -vlib work -vcom -explicit -93 "../src/fifo_ctrl_pkg.vhd" -vcom -explicit -93 "../src/gray_counter.vhd" -vcom -explicit -93 "../src/tb_gray_counter.vhd" -vsim -t 1ps -lib work tb_gray_counter -view wave -do {tb_gray_counter.wdo} -view structure -view signals - -run 1us diff --git a/lib/FIFO/sim/tb_gray_counter.wdo b/lib/FIFO/sim/tb_gray_counter.wdo deleted file mode 100644 index dd0c3c2..0000000 --- a/lib/FIFO/sim/tb_gray_counter.wdo +++ /dev/null @@ -1,29 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_gray_counter/rst -add wave -noupdate -format Logic /tb_gray_counter/ce -add wave -noupdate -format Logic /tb_gray_counter/clk -add wave -noupdate -divider -add wave -noupdate -format Literal /tb_gray_counter/bcnt -add wave -noupdate -divider -add wave -noupdate -format Literal /tb_gray_counter/bnxt -add wave -noupdate -divider -add wave -noupdate -format Literal /tb_gray_counter/gcnt -add wave -noupdate -divider -add wave -noupdate -format Literal /tb_gray_counter/gnxt -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {61919 ps} 0} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -update -WaveRestoreZoom {915144 ps} {1004467 ps} diff --git a/lib/FIFO/src/.directory_history b/lib/FIFO/src/.directory_history deleted file mode 100644 index d1192e2..0000000 --- a/lib/FIFO/src/.directory_history +++ /dev/null @@ -1,8 +0,0 @@ -VHDL/lib/FIFO/src/async_fifo_ctrl.vhd -VHDL/lib/FIFO/src/fifo_async_ctrl.vhd -VHDL/lib/FIFO/src/fifo_async_ctrl.vhd - -VHDL/lib/FIFO/src/fifo_sync_ctrl.vhd - -VHDL/lib/FIFO/src/sync_fifo_ctrl.vhd -VHDL/lib/FIFO/src/fifo_sync_ctrl.vhd diff --git a/lib/FIFO/src/async_fifo_ctrl.vhd b/lib/FIFO/src/async_fifo_ctrl.vhd deleted file mode 100644 index 17733b6..0000000 --- a/lib/FIFO/src/async_fifo_ctrl.vhd +++ /dev/null @@ -1,248 +0,0 @@ -------------------------------------------------------------------------- --- Project: FIFO, generic FIFOs written in VHDL --- Release 1 --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This library is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. --- --- This library is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. --- --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the Free Software --- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA --- --- For questions and ideas, please contact the author at jens@jayfield.org --- ------------------------------------------------------------------------ - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -LIBRARY WORK; -USE WORK.FIFO_CTRL_PKG.ALL; - -entity fifo_async_ctrl is - Generic - ( - addr_width : integer := 3; - almost_full_thresh : integer := 6; - almost_empty_thresh : integer := 2 - ); - Port - ( - rst : in STD_LOGIC; - clk_w : in STD_LOGIC; - clk_r : in STD_LOGIC; - winc : in STD_LOGIC; - rinc : in STD_LOGIC; - ptr_w : out unsigned (addr_width-1 downto 0); - ptr_r : out unsigned (addr_width-1 downto 0); - fifo_pre_full : out STD_LOGIC; - fifo_pre_empty : out STD_LOGIC; - fifo_full : out STD_LOGIC; - fifo_empty : out STD_LOGIC; - fifo_afull : out STD_LOGIC; - fifo_aempty : out STD_LOGIC - ); -end fifo_async_ctrl; - -architecture Behavioral of fifo_async_ctrl is - - signal gcnt_w : unsigned (addr_width downto 0); - signal gcnt2_w : unsigned (addr_width downto 0); - signal bcnt2_aw : unsigned (addr_width downto 0); - signal bcnt_w : unsigned (addr_width downto 0); - signal gnxt_w : unsigned (addr_width downto 0); - signal bnxt_w : unsigned (addr_width downto 0); - signal gcnt_r : unsigned (addr_width downto 0); - signal gcnt2_r : unsigned (addr_width downto 0); - signal bcnt2_ar : unsigned (addr_width downto 0); - signal bcnt_r : unsigned (addr_width downto 0); - signal gnxt_r : unsigned (addr_width downto 0); - signal bnxt_r : unsigned (addr_width downto 0); - - signal pre_empty, pre_full : std_logic; - signal full, empty : std_logic; - - -- synthesis translate_off - signal diffw : signed (addr_width downto 0); - signal diffr : signed (addr_width downto 0); - -- synthesis translate_on - -begin - - ptr_w <= bcnt_w(addr_width-1 downto 0); - ptr_r <= bnxt_r(addr_width-1 downto 0); - fifo_full <= full; - fifo_empty <= empty; - fifo_pre_full <= pre_full; - fifo_pre_empty <= pre_empty; - -proc_write_inhibit: - process(rst, clk_w) - begin - if rst = '1' then - full <= '0'; - elsif rising_edge(clk_w) then - full <= pre_full; - end if; - end process; - -proc_read_inhibit: - process(rst, clk_r) - begin - if rst = '1' then - empty <= '1'; - elsif rising_edge(clk_r) then - empty <= pre_empty; - end if; - end process; - -proc_sync_grptr: - process(clk_w) - variable p1, p2 : unsigned (addr_width downto 0); - begin - if rising_edge(clk_w) then - gcnt2_r <= p2; - p2 := p1; - p1 := gcnt_r; - end if; - end process; - -proc_ptr_gwptr: - process(clk_r) - variable p1, p2 : unsigned (addr_width downto 0); - begin - if rising_edge(clk_r) then - gcnt2_w <= p2; - p2 := p1; - p1 := gcnt_w; - end if; - end process; - -proc_status_full: - process(gnxt_w, gcnt2_r) - begin - if (gnxt_w = (not gcnt2_r(gcnt2_r'left downto gcnt2_r'left-1) & gcnt2_r(gcnt2_r'left-2 downto 0))) then - pre_full <= '1'; - else - pre_full <= '0'; - end if; - end process; - -proc_status_empty: - process(gnxt_r, gcnt2_w) - begin - if (gnxt_r = gcnt2_w) then - pre_empty <= '1'; - else - pre_empty <= '0'; - end if; - end process; - -proc_sync_arptr: - process(clk_w) - variable p1, p2 : unsigned (addr_width downto 0); - begin - if rising_edge(clk_w) then - bcnt2_ar <= p2; - p2 := p1; - p1 := bcnt_r; - end if; - end process; - -proc_ptr_awptr: - process(clk_r) - variable p1, p2 : unsigned (addr_width downto 0); - begin - if rising_edge(clk_r) then - bcnt2_aw <= p2; - p2 := p1; - p1 := bcnt_w; - end if; - end process; - -proc_status_almost_full: - process(rst, clk_w) - variable diff : unsigned (addr_width downto 0); - begin - -- synthesis translate_off - diffw <= signed(diff); - -- synthesis translate_on - if rst = '1' then - fifo_afull <= '0'; - diff := (others => '0'); - elsif rising_edge(clk_w) then - if diff >= almost_full_thresh-1 then - fifo_afull <= '1'; - else - fifo_afull <= '0'; - end if; - diff := unsigned(abs(signed(bnxt_w) - signed(bcnt2_ar))); - end if; - end process; - -proc_status_almost_empty: - process(rst, clk_r) - variable diff : unsigned (addr_width downto 0); - begin - -- synthesis translate_off - diffr <= signed(diff); - -- synthesis translate_on - if rst = '1' then - fifo_aempty <= '1'; - diff := (others => '0'); - elsif rising_edge(clk_r) then - if diff <= almost_empty_thresh+1 then - fifo_aempty <= '1'; - else - fifo_aempty <= '0'; - end if; - diff := unsigned(abs(signed(bcnt2_aw) - signed(bnxt_r))); - end if; - end process; - -inst_gray_counter_w : entity work.gray_counter - generic map - ( - width => addr_width+1, - init_value => 0 - ) - port map - ( - rst => rst, - clk => clk_w, - ce => winc, - bcnt => bcnt_w, - bnxt => bnxt_w, - gcnt => gcnt_w, - gnxt => gnxt_w - ); - -inst_gray_counter_r : entity work.gray_counter - generic map - ( - width => addr_width+1, - init_value => 0 - ) - port map - ( - rst => rst, - clk => clk_r, - ce => rinc, - bcnt => bcnt_r, - bnxt => bnxt_r, - gcnt => gcnt_r, - gnxt => gnxt_r - ); - -end Behavioral; - diff --git a/lib/FIFO/src/fifo_async.vhd b/lib/FIFO/src/fifo_async.vhd deleted file mode 100644 index 35340e7..0000000 --- a/lib/FIFO/src/fifo_async.vhd +++ /dev/null @@ -1,124 +0,0 @@ -------------------------------------------------------------------------- --- Project: FIFO, generic FIFOs written in VHDL --- Release 1 --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This library is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. --- --- This library is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. --- --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the Free Software --- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA --- --- For questions and ideas, please contact the author at jens@jayfield.org --- ------------------------------------------------------------------------ - -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -use work.fifo_ctrl_pkg.all; - -entity fifo_async is - Generic - ( - addr_width : natural := 4; - data_width : natural := 8; - almost_full_thresh : integer := 12; - almost_empty_thresh : integer := 4; - allow_full_writes : boolean := false; - allow_empty_reads : boolean := false; - do_last_read_update : boolean := true - ); - Port - ( - rst : in STD_LOGIC; - clk_w : in STD_LOGIC; - clk_r : in STD_LOGIC; - we : in STD_LOGIC; - re : in STD_LOGIC; - fifo_full : out STD_LOGIC; - fifo_empty : out STD_LOGIC; - fifo_afull : out STD_LOGIC; - fifo_aempty : out STD_LOGIC; - data_w : in unsigned (data_width-1 downto 0); - data_r : out unsigned (data_width-1 downto 0) - ); -end fifo_async; - -architecture Behavioral of fifo_async is - - signal mem_wr_en : STD_LOGIC; - signal mem_rd_en : STD_LOGIC; - signal ptr_w : unsigned (addr_width-1 downto 0); - signal ptr_r : unsigned (addr_width-1 downto 0); - signal full : std_logic; - signal empty : std_logic; - signal pre_full : STD_LOGIC; - signal pre_empty : STD_LOGIC; - signal rinc : std_logic; - -begin - - fifo_full <= full; - fifo_empty <= empty; - - mem_wr_en <= (we and not full) when allow_full_writes = false else we; - rinc <= (re and not empty) when allow_empty_reads = false else re; - mem_rd_en <= not pre_empty when do_last_read_update = false else '1'; - - - inst_fifo_async_ctrl: entity work.fifo_async_ctrl - GENERIC MAP - ( - addr_width => addr_width, - almost_full_thresh => almost_full_thresh, - almost_empty_thresh => almost_empty_thresh - ) - PORT MAP - ( - rst => rst, - clk_w => clk_w, - clk_r => clk_r, - winc => mem_wr_en, - rinc => rinc, - ptr_w => ptr_w, - ptr_r => ptr_r, - fifo_full => full, - fifo_empty => empty, - fifo_pre_full => pre_full, - fifo_pre_empty => pre_empty, - fifo_afull => fifo_afull, - fifo_aempty => fifo_aempty - - ); - -inst_dpram_1w1r2c: entity work.dpram_1w1r2c_ro - GENERIC MAP - ( - addr_width => addr_width, - data_width => data_width - ) - PORT MAP( - clk_a => clk_w, - clk_b => clk_r, - en_a => '1', - en_b => mem_rd_en, - we_a => mem_wr_en, - addr_a => ptr_w, - addr_b => ptr_r, - din_a => data_w, - dout_b => data_r - ); - -end Behavioral; - diff --git a/lib/FIFO/src/fifo_ctrl_pkg.vhd b/lib/FIFO/src/fifo_ctrl_pkg.vhd deleted file mode 100644 index 7404fc2..0000000 --- a/lib/FIFO/src/fifo_ctrl_pkg.vhd +++ /dev/null @@ -1,67 +0,0 @@ -------------------------------------------------------------------------- --- Project: FIFO, generic FIFOs written in VHDL --- Release 1 --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This library is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. --- --- This library is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. --- --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the Free Software --- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA --- --- For questions and ideas, please contact the author at jens@jayfield.org --- ------------------------------------------------------------------------ - -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -package fifo_ctrl_pkg is - - -- Constants - -- Types - - -- Functions - function bin2gray(xb : unsigned) return unsigned; - function gray2bin(xg : unsigned) return unsigned; - -end fifo_ctrl_pkg; - -package body fifo_ctrl_pkg is - - function bin2gray(xb : unsigned) return unsigned is - variable xg : unsigned(xb'left downto xb'right); - begin - - xg(xg'left) := xb(xb'left); - for i in 1 to xb'left loop - xg(xg'left-i) := xb(xb'left-i+1) xor xb(xb'left-i); - end loop; - - return xg; - end bin2gray; - - function gray2bin(xg : unsigned) return unsigned is - variable xb : unsigned(xg'left downto xg'right); - begin - - xb(xb'left) := xg(xg'left); - for i in 1 to xg'left loop - xb(xb'left-i) := xb(xb'left-i+1) xor xg(xg'left-i); - end loop; - - return xb; - end gray2bin; - -end fifo_ctrl_pkg; - diff --git a/lib/FIFO/src/fifo_sync.vhd b/lib/FIFO/src/fifo_sync.vhd deleted file mode 100644 index 5c8d8c8..0000000 --- a/lib/FIFO/src/fifo_sync.vhd +++ /dev/null @@ -1,123 +0,0 @@ -------------------------------------------------------------------------- --- Project: FIFO, generic FIFOs written in VHDL --- Release 1 --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This library is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. --- --- This library is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. --- --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the Free Software --- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA --- --- For questions and ideas, please contact the author at jens@jayfield.org --- ------------------------------------------------------------------------ - -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -use work.fifo_ctrl_pkg.all; - -entity fifo_sync is - Generic - ( - addr_width : natural := 4; - data_width : natural := 8; - almost_full_thresh : integer := 12; - almost_empty_thresh : integer := 4; - allow_full_writes : boolean := false; - allow_empty_reads : boolean := false; - do_last_read_update : boolean := true - - ); - Port - ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - we : in STD_LOGIC; - re : in STD_LOGIC; - fifo_full : out STD_LOGIC; - fifo_empty : out STD_LOGIC; - fifo_afull : out STD_LOGIC; - fifo_aempty : out STD_LOGIC; - data_w : in unsigned (data_width-1 downto 0); - data_r : out unsigned (data_width-1 downto 0) - ); -end fifo_sync; - -architecture Behavioral of fifo_sync is - - signal mem_wr_en : STD_LOGIC; - signal mem_rd_en : STD_LOGIC; - signal ptr_w : unsigned (addr_width-1 downto 0); - signal ptr_r : unsigned (addr_width-1 downto 0); - signal full : STD_LOGIC; - signal empty : std_logic; - signal pre_full : STD_LOGIC; - signal pre_empty : STD_LOGIC; - signal rinc : std_logic; - -begin - - fifo_full <= full; - fifo_empty <= empty; - - mem_wr_en <= (we and not full) when allow_full_writes = false else we; - rinc <= (re and not empty) when allow_empty_reads = false else re; - mem_rd_en <= not pre_empty when do_last_read_update = false else '1'; - - -inst_fifo_sync_ctrl: entity work.fifo_sync_ctrl - GENERIC MAP - ( - addr_width => addr_width, - almost_full_thresh => almost_full_thresh, - almost_empty_thresh => almost_empty_thresh - ) - PORT MAP - ( - rst => rst, - clk => clk, - winc => mem_wr_en, - rinc => rinc, - ptr_w => ptr_w, - ptr_r => ptr_r, - fifo_full => full, - fifo_empty => empty, - fifo_pre_full => pre_full, - fifo_pre_empty => pre_empty, - fifo_afull => fifo_afull, - fifo_aempty => fifo_aempty - - ); - -inst_dpram_1w1r2c: entity work.dpram_1w1r2c_ro - GENERIC MAP - ( - addr_width => addr_width, - data_width => data_width - ) - PORT MAP( - clk_a => clk, - clk_b => clk, - en_a => '1', - en_b => mem_rd_en, - we_a => mem_wr_en, - addr_a => ptr_w, - addr_b => ptr_r, - din_a => data_w, - dout_b => data_r - ); - -end Behavioral; - diff --git a/lib/FIFO/src/fifo_sync_dist.vhd b/lib/FIFO/src/fifo_sync_dist.vhd deleted file mode 100644 index beb89f5..0000000 --- a/lib/FIFO/src/fifo_sync_dist.vhd +++ /dev/null @@ -1,117 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: Dual-ported register file with asynchrous read - --- Copyright (C) 2007 J. Ahrensfeld - --- This library is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. - --- This library is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. - --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the Free Software --- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - --- For questions and ideas, please contact the author at jens@jayfield.org - ------------------------------------------------------------------------ - -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -use work.fifo_ctrl_pkg.all; - -entity fifo_sync_dist is - Generic ( - addr_width : natural := 4; - data_width : natural := 8; - almost_full_thresh : integer := 12; - almost_empty_thresh : integer := 4 - ); - Port - ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - we : in STD_LOGIC; - re : in STD_LOGIC; - fifo_full : out STD_LOGIC; - fifo_empty : out STD_LOGIC; - fifo_afull : out STD_LOGIC; - fifo_aempty : out STD_LOGIC; - data_w : in unsigned (data_width-1 downto 0); - data_r : out unsigned (data_width-1 downto 0) - ); -end fifo_sync_dist; - -architecture Behavioral of fifo_sync_dist is - - signal mem_wr_en : STD_LOGIC; - signal mem_rd_en : STD_LOGIC; - signal ptr_w : unsigned (addr_width-1 downto 0); - signal ptr_r : unsigned (addr_width-1 downto 0); - signal full : STD_LOGIC; - signal empty : STD_LOGIC; - signal almost_full : STD_LOGIC; - signal almost_empty : STD_LOGIC; - signal pre_full : STD_LOGIC; - signal pre_empty : STD_LOGIC; - -begin - - mem_wr_en <= not full; - mem_rd_en <= not pre_empty; - fifo_full <= full; - fifo_empty <= empty; - fifo_afull <= almost_full; - fifo_aempty <= almost_empty; - - inst_fifo_sync_ctrl: entity work.fifo_sync_ctrl - GENERIC MAP - ( - addr_width => addr_width, - almost_full_thresh => almost_full_thresh, - almost_empty_thresh => almost_empty_thresh - ) - PORT MAP - ( - rst => rst, - clk => clk, - we => we, - re => re, - ptr_w => ptr_w, - ptr_r => ptr_r, - fifo_full => full, - fifo_empty => empty, - fifo_pre_full => pre_full, - fifo_pre_empty => pre_empty, - fifo_afull => almost_full, - fifo_aempty => almost_empty - - ); - - inst_dpram_1w1r: entity work.dpram_1w1r_dist - GENERIC MAP ( - addr_width => addr_width, - data_width => data_width - ) - PORT MAP( - clka => clk, - clkb => clk, - en_a => mem_wr_en, - en_b => mem_rd_en, - we_a => we, - addr_a => ptr_w, - addr_b => ptr_r, - din_a => data_w, - dout_b => data_r - ); - -end Behavioral; - diff --git a/lib/FIFO/src/gray_counter.vhd b/lib/FIFO/src/gray_counter.vhd deleted file mode 100644 index 990f15b..0000000 --- a/lib/FIFO/src/gray_counter.vhd +++ /dev/null @@ -1,84 +0,0 @@ -------------------------------------------------------------------------- --- Project: FIFO, generic FIFOs written in VHDL --- Release 1 --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This library is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. --- --- This library is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. --- --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the Free Software --- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA --- --- For questions and ideas, please contact the author at jens@jayfield.org --- ------------------------------------------------------------------------ - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -LIBRARY WORK; -USE WORK.FIFO_CTRL_PKG.ALL; - -entity gray_counter is - Generic ( - width : natural := 3; - init_value : natural := 0 - ); - Port - ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - ce : in STD_LOGIC; - bcnt : out unsigned (width-1 downto 0); - bnxt : out unsigned (width-1 downto 0); - gcnt : out unsigned (width-1 downto 0); - gnxt : out unsigned (width-1 downto 0) - ); -end gray_counter; - -architecture Behavioral of gray_counter is - - signal cntg : unsigned (width-1 downto 0); - signal cntb : unsigned (width-1 downto 0); - signal nxtb : unsigned (width-1 downto 0); - signal nxtg : unsigned (width-1 downto 0); - -begin - - bnxt <= nxtb; - gnxt <= nxtg; - bcnt <= cntb; - gcnt <= cntg; - - process(rst, clk, ce, cntb, nxtb) - begin - if rst = '1' then - cntb <= to_unsigned(init_value, width); - nxtb <= to_unsigned(init_value, width); - nxtg <= to_unsigned(init_value, width); - cntg <= to_unsigned(init_value, width); - else - if rising_edge(clk) then - cntg <= nxtg; - cntb <= nxtb; - end if; - nxtg <= bin2gray(nxtb); - nxtb <= cntb; - if ce = '1' then - nxtb <= cntb + 1; - end if; - end if; - end process; - -end Behavioral; - diff --git a/lib/FIFO/src/sync_fifo_ctrl.vhd b/lib/FIFO/src/sync_fifo_ctrl.vhd deleted file mode 100644 index a198fa1..0000000 --- a/lib/FIFO/src/sync_fifo_ctrl.vhd +++ /dev/null @@ -1,198 +0,0 @@ -------------------------------------------------------------------------- --- Project: FIFO, generic FIFOs written in VHDL --- Release 1 --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This library is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. --- --- This library is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. --- --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the Free Software --- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA --- --- For questions and ideas, please contact the author at jens@jayfield.org --- ------------------------------------------------------------------------ - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -entity fifo_sync_ctrl is - Generic - ( - addr_width : integer := 3; - almost_full_thresh : integer := 6; - almost_empty_thresh : integer := 2 - ); - Port - ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - winc : in STD_LOGIC; - rinc : in STD_LOGIC; - ptr_w : out unsigned (addr_width-1 downto 0); - ptr_r : out unsigned (addr_width-1 downto 0); - fifo_pre_full : out STD_LOGIC; - fifo_pre_empty : out STD_LOGIC; - fifo_full : out STD_LOGIC; - fifo_empty : out STD_LOGIC; - fifo_afull : out STD_LOGIC; - fifo_aempty : out STD_LOGIC - ); -end fifo_sync_ctrl; - -architecture Behavioral of fifo_sync_ctrl is - - signal pW, pW_cnt, pW_next : unsigned (addr_width-1 downto 0); - signal pR, pR_cnt, pR_next : unsigned (addr_width-1 downto 0); - signal empty, full : std_logic; - signal pre_empty, pre_full : std_logic; - signal was_write : std_logic; - signal diff : unsigned (addr_width downto 0); - -begin - - fifo_full <= full; - fifo_empty <= empty; - fifo_pre_full <= pre_full; - fifo_pre_empty <= pre_empty; - - -proc_diff_gen: - process(rst, clk) - begin - if rst = '1' then - diff <= (others => '0'); - elsif rising_edge(clk) then - if winc = '1' and rinc = '0' then - diff <= diff + 1; - elsif winc = '0' and rinc = '1' then - diff <= diff - 1; - end if; - end if; - end process; - -proc_status_almost_full: - process(rst, clk) - begin - if rst = '1' then - fifo_afull <= '0'; - elsif rising_edge(clk) then - if diff >= almost_full_thresh-1 then - fifo_afull <= '1'; - else - fifo_afull <= '0'; - end if; - end if; - end process; - -proc_status_almost_empty: - process(rst, clk) - begin - if rst = '1' then - fifo_aempty <= '1'; - elsif rising_edge(clk) then - if diff <= almost_empty_thresh+1 then - fifo_aempty <= '1'; - else - fifo_aempty <= '0'; - end if; - end if; - end process; - -proc_full_reg: - process(rst, clk) - begin - if rst = '1' then - full <= '0'; - elsif rising_edge(clk) then - full <= pre_full; - end if; - end process; - -proc_empty_reg: - process(rst, clk) - begin - if rst = '1' then - empty <= '1'; - elsif rising_edge(clk) then - empty <= pre_empty; - end if; - end process; - -proc_status_w: - process(was_write, pW_next, pR_next, pW, pR, winc, rinc) - begin - if (pW_next = pR) and (winc = '1' or was_write = '1') then - pre_full <= '1'; - else - pre_full <= '0'; - end if; - if (pR_next = pW) and (rinc = '1' or was_write = '0') then - pre_empty <= '1'; - else - pre_empty <= '0'; - end if; - end process; - -proc_flag_write: - process(rst, clk) - begin - if rst = '1' then - was_write <= '0'; - elsif rising_edge(clk) then - if winc = '1' then - was_write <= '1'; - elsif rinc = '1' then - was_write <= '0'; - end if; - end if; - end process; - -proc_ptr_w: - process(rst, clk, pW, winc) - begin - if rst = '1' then - pW <= to_unsigned(0, addr_width); - pW_next <= to_unsigned(0, addr_width); - elsif rising_edge(clk) then - if winc = '1' then - pW <= pW_next; - end if; - end if; - pW_next <= pW; - if winc = '1' then - pW_next <= pW + 1; - end if; - ptr_w <= pW; - end process; - -proc_ptr_r: - process(rst, clk, pR_next, pR, rinc) - begin - if rst = '1' then - pR <= to_unsigned(0, addr_width); - pR_next <= to_unsigned(0, addr_width); - elsif rising_edge(clk) then - if rinc = '1' then - pR <= pR_next; - end if; - end if; - pR_next <= pR; - if rinc = '1' then - pR_next <= pR + 1; - end if; - ptr_r <= pR_next; - end process; - -end Behavioral; - diff --git a/lib/FIFO/src/tb_fifo_async.vhd b/lib/FIFO/src/tb_fifo_async.vhd deleted file mode 100644 index 31e6b36..0000000 --- a/lib/FIFO/src/tb_fifo_async.vhd +++ /dev/null @@ -1,225 +0,0 @@ -------------------------------------------------------------------------- --- Project: FIFO, generic FIFOs written in VHDL --- Release 1 --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This library is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. --- --- This library is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. --- --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the Free Software --- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA --- --- For questions and ideas, please contact the author at jens@jayfield.org --- ------------------------------------------------------------------------ - -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.MATH_REAL.ALL; -USE IEEE.NUMERIC_STD.ALL; -USE STD.TEXTIO.ALL; - --- LIBRARY WORK; --- USE.YOURLIB.WHATELSE - -ENTITY tb_fifo_async IS -END tb_fifo_async; - -ARCHITECTURE behavior OF tb_fifo_async IS - - --Constants - constant PERIOD_W : time := 10 ns; - constant PERIOD_R : time := 7.5 ns; - constant ADDR_WIDTH : integer := 3; - constant DATA_WIDTH : integer := 8; - - --Inputs - signal rst : STD_LOGIC := '1'; - signal clk_w : STD_LOGIC := '0'; - signal clk_r : STD_LOGIC := '0'; - signal we : STD_LOGIC := '0'; - signal re : STD_LOGIC := '0'; - signal din : unsigned (7 downto 0); - --Outputs - - signal dout : unsigned (7 downto 0); - signal fifo_full : STD_LOGIC; - signal fifo_empty : STD_LOGIC; - signal fifo_almost_full : STD_LOGIC; - signal fifo_almost_empty : STD_LOGIC; - - signal write_en : STD_LOGIC := '0'; - signal read_en : STD_LOGIC := '0'; - - signal ref_r : unsigned (7 downto 0); - -BEGIN - - -- Instantiate the Unit Under Test (UUT) - uut: entity work.fifo_async - GENERIC MAP - ( - addr_width => ADDR_WIDTH, - data_width => DATA_WIDTH, - almost_full_thresh => 6, - almost_empty_thresh => 2, - allow_full_writes => false, - allow_empty_reads => false, - do_last_read_update => false - ) - PORT MAP - ( - rst => rst, - clk_w => clk_w, - clk_r => clk_r, - we => we, - re => re, - data_w => din, - data_r => dout, - fifo_full => fifo_full, - fifo_empty => fifo_empty, - fifo_afull => fifo_almost_full, - fifo_aempty => fifo_almost_empty - - ); - - tb_clk_w : PROCESS - BEGIN - clk_w <= not clk_w; - wait for PERIOD_W/2; - END PROCESS; - - tb_clk_r : PROCESS - BEGIN - clk_r <= not clk_r; - wait for PERIOD_R/2; - END PROCESS; - - tb_write : PROCESS - BEGIN - - -- Wait 100 ns for global reset to finish - wait for 5*PERIOD_W; - rst <= '0'; - wait for 7*PERIOD_W; - write_en <= '1'; - wait for 25*PERIOD_W; - write_en <= '0'; - wait for 7*PERIOD_W; - write_en <= '1'; - wait for 25*PERIOD_W; - write_en <= '0'; - wait for 7*PERIOD_W; - write_en <= '1'; - wait for 1*PERIOD_W; - write_en <= '0'; - wait for 1*PERIOD_W; - write_en <= '1'; - wait for 1*PERIOD_W; - write_en <= '0'; - wait for 3*PERIOD_W; - write_en <= '1'; - wait for 4*PERIOD_W; - write_en <= '0'; - wait for 17*PERIOD_W; - write_en <= '1'; - wait for 55*PERIOD_W; - write_en <= '0'; - wait for 1*PERIOD_W; - write_en <= '1'; - wait for 1*PERIOD_W; - write_en <= '0'; - wait for 3*PERIOD_W; - write_en <= '1'; - wait for 44*PERIOD_W; - write_en <= '0'; - - wait; - - END PROCESS; - - tb_read : PROCESS - BEGIN - - -- Wait 100 ns for global reset to finish - wait for 25*PERIOD_R; - read_en <= '1'; - wait for 25*PERIOD_R; - read_en <= '0'; - wait for 25*PERIOD_R; - read_en <= '1'; - wait for 1*PERIOD_R; - read_en <= '0'; - wait for 5*PERIOD_R; - read_en <= '1'; - wait for 1*PERIOD_R; - read_en <= '0'; - wait for 5*PERIOD_R; - read_en <= '1'; - wait for 1*PERIOD_R; - read_en <= '0'; - wait for 5*PERIOD_R; - read_en <= '1'; - wait for 1*PERIOD_R; - read_en <= '0'; - wait for 5*PERIOD_R; - read_en <= '1'; - wait for 1*PERIOD_R; - read_en <= '0'; - wait for 5*PERIOD_R; - read_en <= '1'; - wait for 1*PERIOD_R; - read_en <= '0'; - wait for 5*PERIOD_R; - read_en <= '1'; - wait for 1*PERIOD_R; - read_en <= '0'; - wait for 7*PERIOD_R; - read_en <= '1'; - wait for 15*PERIOD_R; - read_en <= '0'; - wait; - - END PROCESS; - - we <= write_en; - - tb_w : PROCESS(rst, clk_w) - BEGIN - - if rst = '1' then - din <= (others => '0'); - elsif rising_edge(clk_w) then - if we = '1' and fifo_full = '0' then - din <= din + 1; - end if; - end if; - - END PROCESS; - - re <= read_en; - - tb_r : PROCESS(rst, clk_r) - BEGIN - - if rst = '1' then - ref_r <= (others => '0'); - elsif rising_edge(clk_r) then - if re = '1' and fifo_empty = '0' then - assert ref_r = dout report "FIFO read error!" severity failure; - ref_r <= ref_r + 1; - end if; - end if; - - END PROCESS; - -END behavior; \ No newline at end of file diff --git a/lib/FIFO/src/tb_fifo_sync.vhd b/lib/FIFO/src/tb_fifo_sync.vhd deleted file mode 100644 index f7fb6a5..0000000 --- a/lib/FIFO/src/tb_fifo_sync.vhd +++ /dev/null @@ -1,207 +0,0 @@ -------------------------------------------------------------------------- --- Project: FIFO, generic FIFOs written in VHDL --- Release 1 --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This library is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. --- --- This library is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. --- --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the Free Software --- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA --- --- For questions and ideas, please contact the author at jens@jayfield.org --- ------------------------------------------------------------------------ - -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.MATH_REAL.ALL; -USE IEEE.NUMERIC_STD.ALL; -USE STD.TEXTIO.ALL; - --- LIBRARY WORK; --- USE.YOURLIB.WHATELSE - -ENTITY tb_fifo_sync IS -END tb_fifo_sync; - -ARCHITECTURE behavior OF tb_fifo_sync IS - - --Constants - constant PERIOD : time := 10 ns; - constant ADDR_WIDTH : integer := 3; - constant DATA_WIDTH : integer := 8; - - --Inputs - signal rst : STD_LOGIC := '1'; - signal clk : STD_LOGIC := '0'; - signal we : STD_LOGIC := '0'; - signal re : STD_LOGIC := '0'; - signal din : unsigned (7 downto 0); - --Outputs - - signal dout : unsigned (7 downto 0); - signal fifo_full : STD_LOGIC; - signal fifo_empty : STD_LOGIC; - signal fifo_almost_full : STD_LOGIC; - signal fifo_almost_empty : STD_LOGIC; - - signal write_en : STD_LOGIC := '0'; - signal read_en : STD_LOGIC := '0'; - - signal ref_r : unsigned (7 downto 0) := (others => '0'); - -BEGIN - - -- Instantiate the Unit Under Test (UUT) - uut: entity work.fifo_sync - GENERIC MAP - ( - data_width => DATA_WIDTH, - addr_width => ADDR_WIDTH, - almost_full_thresh => 6, - almost_empty_thresh => 2, - do_last_read_update => false - ) - PORT MAP - ( - rst => rst, - clk => clk, - we => we, - re => re, - data_w => din, - data_r => dout, - fifo_full => fifo_full, - fifo_empty => fifo_empty, - fifo_afull => fifo_almost_full, - fifo_aempty => fifo_almost_empty - - ); - - tb_clk : PROCESS - BEGIN - clk <= not clk; - wait for PERIOD/2; - END PROCESS; - - tb_write : PROCESS - BEGIN - - -- Wait 100 ns for global reset to finish - wait for 5*PERIOD; - rst <= '0'; - wait for 7*PERIOD; - write_en <= '1'; - wait for 25*PERIOD; - write_en <= '0'; - wait for 7*PERIOD; - write_en <= '1'; - wait for 25*PERIOD; - write_en <= '0'; - wait for 7*PERIOD; - write_en <= '1'; - wait for 1*PERIOD; - write_en <= '0'; - wait for 1*PERIOD; - write_en <= '1'; - wait for 1*PERIOD; - write_en <= '0'; - wait for 3*PERIOD; - write_en <= '1'; - wait for 4*PERIOD; - write_en <= '0'; - wait for 17*PERIOD; - write_en <= '1'; - wait for 25*PERIOD; - write_en <= '0'; - - wait; - - END PROCESS; - - tb_read : PROCESS - BEGIN - - -- Wait 100 ns for global reset to finish - wait for 25*PERIOD; - read_en <= '1'; - wait for 25*PERIOD; - read_en <= '0'; - wait for 25*PERIOD; - read_en <= '1'; - wait for 1*PERIOD; - read_en <= '0'; - wait for 5*PERIOD; - read_en <= '1'; - wait for 1*PERIOD; - read_en <= '0'; - wait for 5*PERIOD; - read_en <= '1'; - wait for 1*PERIOD; - read_en <= '0'; - wait for 5*PERIOD; - read_en <= '1'; - wait for 1*PERIOD; - read_en <= '0'; - wait for 5*PERIOD; - read_en <= '1'; - wait for 1*PERIOD; - read_en <= '0'; - wait for 5*PERIOD; - read_en <= '1'; - wait for 1*PERIOD; - read_en <= '0'; - wait for 5*PERIOD; - read_en <= '1'; - wait for 1*PERIOD; - read_en <= '0'; - wait for 7*PERIOD; - read_en <= '1'; - wait for 20*PERIOD; - read_en <= '0'; - - wait; - - END PROCESS; - - we <= write_en and not fifo_full; - - tb_w : PROCESS(rst, clk) - BEGIN - - if rst = '1' then - din <= (others => '0'); - elsif rising_edge(clk) then - if we = '1' then - din <= din + 1; - end if; - end if; - - END PROCESS; - - re <= read_en and not fifo_empty; - - tb_r : PROCESS(rst, clk) - BEGIN - - if rst = '1' then - ref_r <= (others => '0'); - elsif rising_edge(clk) then - if re = '1' then - assert ref_r = dout report "FIFO read error!" severity failure; - ref_r <= ref_r + 1; - end if; - end if; - - END PROCESS; - -END behavior; \ No newline at end of file diff --git a/lib/FIFO/src/tb_gray_counter.vhd b/lib/FIFO/src/tb_gray_counter.vhd deleted file mode 100644 index 1fd241d..0000000 --- a/lib/FIFO/src/tb_gray_counter.vhd +++ /dev/null @@ -1,85 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 17:16:42 13.05.2007 --- Design Name: tb_gray_counter --- Module Name: tb_gray_counter.vhd --- Project Name: gray_counter package --- Target Device: --- Tool versions: --- Description: --- ------------------------------------------------------------------------ --- $Header: /tmp/cvsroot/VHDL/lib/FIFO/src/tb_gray_counter.vhd,v 1.2 2010-02-13 10:50:47 Jens Exp $ ------------------------------------------------------------------------ -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.MATH_REAL.ALL; -USE IEEE.NUMERIC_STD.ALL; -USE STD.TEXTIO.ALL; - -LIBRARY WORK; -USE WORK.FIFO_CTRL_PKG.ALL; - -ENTITY tb_gray_counter IS -END tb_gray_counter; - -ARCHITECTURE behavior OF tb_gray_counter IS - - constant PERIOD : time := 10 ns; - constant WIDTH : integer := 3; - - --Signals - signal gcnt : unsigned (WIDTH-1 downto 0) := to_unsigned(0, WIDTH); - signal bcnt : unsigned (WIDTH-1 downto 0) := to_unsigned(0, WIDTH); - signal gnxt : unsigned (WIDTH-1 downto 0) := to_unsigned(0, WIDTH); - signal bnxt : unsigned (WIDTH-1 downto 0) := to_unsigned(0, WIDTH); - signal rst : STD_LOGIC := '1'; - signal clk : STD_LOGIC := '0'; - signal ce : STD_LOGIC := '0'; - -BEGIN - -inst_gray_counter : entity work.gray_counter - generic map (width => WIDTH) - port map ( - rst => rst, - clk => clk, - ce => ce, - bcnt => bcnt, - bnxt => bnxt, - gcnt => gcnt, - gnxt => gnxt - ); - - tb_clk : PROCESS - BEGIN - clk <= not clk; - wait for PERIOD/2; - END PROCESS; - - tb_counter : PROCESS - - BEGIN - - wait for 4*PERIOD; - rst <= '0'; - wait until rising_edge(clk); - ce <= '1'; - wait for 2*PERIOD; - wait until rising_edge(clk); - ce <= '0'; - wait for 3*PERIOD; - wait until rising_edge(clk); - ce <= '1'; - wait until rising_edge(clk); - ce <= '0'; - wait until rising_edge(clk); - ce <= '1'; - - wait; - - END PROCESS; - -END behavior; \ No newline at end of file diff --git a/lib/JBUS/sim/tb_busmaster_async.fdo b/lib/JBUS/sim/tb_busmaster_async.fdo deleted file mode 100644 index a368bf7..0000000 --- a/lib/JBUS/sim/tb_busmaster_async.fdo +++ /dev/null @@ -1,21 +0,0 @@ -## NOTE: Do not edit this file. -## Autogenerated by ProjNav (creatfdo.tcl) on Thu Jul 06 20:49:07 Westeuropäische Sommerzeit 2006 -## -vlib work -vcom -explicit -93 "../../misc/utils_pkg.vhd" -vcom -explicit -93 "../../rams/dpram_1w1r2c_ra_sim.vhd" -vcom -explicit -93 "../../rams/dpram_1w1r2c_ro_sim.vhd" -vcom -explicit -93 "../../FIFO/src/fifo_ctrl_pkg.vhd" -vcom -explicit -93 "../../FIFO/src/gray_counter.vhd" -vcom -explicit -93 "../../FIFO/src/fifo_async_ctrl.vhd" -vcom -explicit -93 "../../FIFO/src/fifo_async.vhd" -vcom -explicit -93 "../src/busmaster_types.vhd" -vcom -explicit -93 "../src/busmaster_async.vhd" -vcom -explicit -93 "../src/tb_busmaster_async.vhd" -vsim -t 1ps -lib work tb_busmaster_async -view wave -do {tb_busmaster_async.wdo} -view structure -view signals - -run 80us diff --git a/lib/JBUS/sim/tb_busmaster_async.wdo b/lib/JBUS/sim/tb_busmaster_async.wdo deleted file mode 100644 index b45143d..0000000 --- a/lib/JBUS/sim/tb_busmaster_async.wdo +++ /dev/null @@ -1,59 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/clk -add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/rst -add wave -noupdate -divider J-BUS -add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/clk -add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/rst -add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/ack_i -add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/srdy_i -add wave -noupdate -format Literal -radix hexadecimal /tb_busmaster_async/inst_uut/mdat_i -add wave -noupdate -format Literal -radix hexadecimal /tb_busmaster_async/inst_uut/mdat_o -add wave -noupdate -format Literal -radix hexadecimal /tb_busmaster_async/inst_uut/addr_o -add wave -noupdate -format Literal /tb_busmaster_async/inst_uut/sel_o -add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/we_o -add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/cyc_o -add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/stb_o -add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/mrdy_o -add wave -noupdate -divider Busmaster -add wave -noupdate -format Logic /tb_busmaster_async/clk_o -add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/clk -add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/rst -add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/cmd_cycle_finished -add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/cmd_cycle_en -add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/cmd_rdy -add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/cmd_we -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_busmaster_async/inst_uut/cmd_in -add wave -noupdate -format Literal -radix hexadecimal /tb_busmaster_async/din -add wave -noupdate -format Logic /tb_busmaster_async/din_rdy -add wave -noupdate -format Logic /tb_busmaster_async/din_we -add wave -noupdate -format Literal -radix hexadecimal /tb_busmaster_async/inst_uut/dout -add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/dout_vld -add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/dout_re -add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/cycle_busy -add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/cmd_en -add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/cmd_read_en -add wave -noupdate -format Literal /tb_busmaster_async/inst_uut/read_cnt -add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/cyc_o -add wave -noupdate -divider RAM -add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/clk -add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/rst -add wave -noupdate -format Literal /tb_busmaster_async/state -add wave -noupdate -format Literal -radix hexadecimal /tb_busmaster_async/read_reg -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_busmaster_async/ram64 -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {31500000 ps} 0} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -update -WaveRestoreZoom {0 ps} {42 us} diff --git a/lib/JBUS/sim/tb_busmaster_sync.fdo b/lib/JBUS/sim/tb_busmaster_sync.fdo deleted file mode 100644 index 51438b6..0000000 --- a/lib/JBUS/sim/tb_busmaster_sync.fdo +++ /dev/null @@ -1,20 +0,0 @@ -## NOTE: Do not edit this file. -## Autogenerated by ProjNav (creatfdo.tcl) on Thu Jul 06 20:49:07 Westeuropäische Sommerzeit 2006 -## -vlib work -vcom -explicit -93 "../../misc/utils_pkg.vhd" -vcom -explicit -93 "../../rams/dpram_1w1r2c_ra_sim.vhd" -vcom -explicit -93 "../../rams/dpram_1w1r2c_ro_sim.vhd" -vcom -explicit -93 "../../FIFO/src/fifo_ctrl_pkg.vhd" -vcom -explicit -93 "../../FIFO/src/fifo_sync_ctrl.vhd" -vcom -explicit -93 "../../FIFO/src/fifo_sync.vhd" -vcom -explicit -93 "../src/busmaster_types.vhd" -vcom -explicit -93 "../src/busmaster_sync.vhd" -vcom -explicit -93 "../src/tb_busmaster_sync.vhd" -vsim -t 1ps -lib work tb_busmaster_sync -view wave -do {tb_busmaster_sync.wdo} -view structure -view signals - -run 40us diff --git a/lib/JBUS/sim/tb_busmaster_sync.wdo b/lib/JBUS/sim/tb_busmaster_sync.wdo deleted file mode 100644 index e6e10cc..0000000 --- a/lib/JBUS/sim/tb_busmaster_sync.wdo +++ /dev/null @@ -1,54 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_busmaster_sync/inst_uut/clk -add wave -noupdate -format Logic /tb_busmaster_sync/inst_uut/rst -add wave -noupdate -divider J-BUS -add wave -noupdate -format Logic /tb_busmaster_sync/inst_uut/clk -add wave -noupdate -format Logic /tb_busmaster_sync/inst_uut/rst -add wave -noupdate -format Logic /tb_busmaster_sync/inst_uut/ack_i -add wave -noupdate -format Logic /tb_busmaster_sync/inst_uut/srdy_i -add wave -noupdate -format Literal -radix hexadecimal /tb_busmaster_sync/inst_uut/mdat_i -add wave -noupdate -format Literal -radix hexadecimal /tb_busmaster_sync/inst_uut/mdat_o -add wave -noupdate -format Literal -radix hexadecimal /tb_busmaster_sync/inst_uut/addr_o -add wave -noupdate -format Literal /tb_busmaster_sync/inst_uut/sel_o -add wave -noupdate -format Logic /tb_busmaster_sync/inst_uut/we_o -add wave -noupdate -format Logic /tb_busmaster_sync/inst_uut/cyc_o -add wave -noupdate -format Logic /tb_busmaster_sync/inst_uut/stb_o -add wave -noupdate -format Logic /tb_busmaster_sync/inst_uut/mrdy_o -add wave -noupdate -divider Busmaster -add wave -noupdate -format Logic /tb_busmaster_sync/inst_uut/clk -add wave -noupdate -format Logic /tb_busmaster_sync/inst_uut/rst -add wave -noupdate -format Logic /tb_busmaster_sync/inst_uut/cmd_cycle_finished -add wave -noupdate -format Logic /tb_busmaster_sync/inst_uut/cmd_cycle_en -add wave -noupdate -format Logic /tb_busmaster_sync/inst_uut/cmd_rdy -add wave -noupdate -format Logic /tb_busmaster_sync/inst_uut/cmd_we -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_busmaster_sync/inst_uut/cmd_in -add wave -noupdate -format Literal -radix hexadecimal /tb_busmaster_sync/inst_uut/dout -add wave -noupdate -format Logic /tb_busmaster_sync/inst_uut/dout_vld -add wave -noupdate -format Logic /tb_busmaster_sync/inst_uut/dout_re -add wave -noupdate -format Logic /tb_busmaster_sync/inst_uut/cycle_busy -add wave -noupdate -format Logic /tb_busmaster_sync/inst_uut/cmd_en -add wave -noupdate -format Logic /tb_busmaster_sync/inst_uut/cmd_read_en -add wave -noupdate -format Literal /tb_busmaster_sync/inst_uut/read_cnt -add wave -noupdate -divider RAM -add wave -noupdate -format Logic /tb_busmaster_sync/inst_uut/clk -add wave -noupdate -format Logic /tb_busmaster_sync/inst_uut/rst -add wave -noupdate -format Literal /tb_busmaster_sync/state -add wave -noupdate -format Literal -radix hexadecimal /tb_busmaster_sync/read_reg -add wave -noupdate -format Literal -radix hexadecimal /tb_busmaster_sync/ram64 -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {7559494 ps} 0} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -update -WaveRestoreZoom {50 ns} {21050 ns} diff --git a/lib/JBUS/sim/tb_dmac.fdo b/lib/JBUS/sim/tb_dmac.fdo deleted file mode 100644 index ca0cbf8..0000000 --- a/lib/JBUS/sim/tb_dmac.fdo +++ /dev/null @@ -1,21 +0,0 @@ -## NOTE: Do not edit this file. -## Autogenerated by ProjNav (creatfdo.tcl) on Thu Jul 06 20:49:07 Westeuropäische Sommerzeit 2006 -## -vlib work -vcom -explicit -93 "../../misc/utils_pkg.vhd" -vcom -explicit -93 "../../rams/dpram_1w1r2c_ra_sim.vhd" -vcom -explicit -93 "../../rams/dpram_1w1r2c_ro_sim.vhd" -vcom -explicit -93 "../../FIFO/src/fifo_ctrl_pkg.vhd" -vcom -explicit -93 "../../FIFO/src/fifo_sync_ctrl.vhd" -vcom -explicit -93 "../../FIFO/src/fifo_sync.vhd" -vcom -explicit -93 "../src/busmaster_types.vhd" -vcom -explicit -93 "../src/busmaster_sync.vhd" -vcom -explicit -93 "../src/dmac.vhd" -vcom -explicit -93 "../src/tb_dmac.vhd" -vsim -t 1ps -lib work tb_dmac -view wave -do {tb_dmac.wdo} -view structure -view signals - -run 6us diff --git a/lib/JBUS/sim/tb_dmac.wdo b/lib/JBUS/sim/tb_dmac.wdo deleted file mode 100644 index 6f86009..0000000 --- a/lib/JBUS/sim/tb_dmac.wdo +++ /dev/null @@ -1,177 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Literal -radix hexadecimal /tb_dmac/read_reg -add wave -noupdate -format Literal /tb_dmac/dma_master_req -add wave -noupdate -format Literal /tb_dmac/dma_master_gnt -add wave -noupdate -format Literal /tb_dmac/dma_req_rdy -add wave -noupdate -format Literal /tb_dmac/dma_req_en -add wave -noupdate -format Literal -radix hexadecimal /tb_dmac/dma_req_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_dmac/dma_req_num_xfers -add wave -noupdate -format Literal /tb_dmac/dma_req_complete -add wave -noupdate -format Literal /tb_dmac/dma_req_complete_ack -add wave -noupdate -format Logic /tb_dmac/bus_cmd_cycle_finished -add wave -noupdate -format Logic /tb_dmac/bus_cmd_cycle_en -add wave -noupdate -format Logic /tb_dmac/bus_cmd_rdy -add wave -noupdate -format Logic /tb_dmac/bus_cmd_we -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_dmac/bus_cmd -add wave -noupdate -format Literal -radix hexadecimal /tb_dmac/bus_dout -add wave -noupdate -format Logic /tb_dmac/bus_dout_vld -add wave -noupdate -format Logic /tb_dmac/bus_dout_re -add wave -noupdate -format Logic /tb_dmac/bus_din_rdy -add wave -noupdate -format Logic /tb_dmac/bus_din_vld -add wave -noupdate -format Literal -radix hexadecimal /tb_dmac/bus_din -add wave -noupdate -divider Busmaster -add wave -noupdate -format Logic /tb_dmac/inst_busmaster_sync/cmd_we -add wave -noupdate -format Literal -radix hexadecimal /tb_dmac/inst_busmaster_sync/cmd_in -add wave -noupdate -format Literal -radix hexadecimal /tb_dmac/inst_busmaster_sync/din -add wave -noupdate -format Logic /tb_dmac/inst_busmaster_sync/din_rdy -add wave -noupdate -format Logic /tb_dmac/inst_busmaster_sync/din_we -add wave -noupdate -format Literal -radix hexadecimal /tb_dmac/inst_busmaster_sync/dout -add wave -noupdate -format Logic /tb_dmac/inst_busmaster_sync/dout_vld -add wave -noupdate -format Logic /tb_dmac/inst_busmaster_sync/dout_re -add wave -noupdate -format Logic /tb_dmac/inst_busmaster_sync/ack_i -add wave -noupdate -format Logic /tb_dmac/inst_busmaster_sync/srdy_i -add wave -noupdate -format Literal -radix hexadecimal /tb_dmac/inst_busmaster_sync/mdat_i -add wave -noupdate -format Literal -radix hexadecimal /tb_dmac/inst_busmaster_sync/mdat_o -add wave -noupdate -format Literal -radix hexadecimal /tb_dmac/inst_busmaster_sync/addr_o -add wave -noupdate -format Literal /tb_dmac/inst_busmaster_sync/sel_o -add wave -noupdate -format Logic /tb_dmac/inst_busmaster_sync/we_o -add wave -noupdate -format Logic /tb_dmac/inst_busmaster_sync/cyc_o -add wave -noupdate -format Logic /tb_dmac/inst_busmaster_sync/stb_o -add wave -noupdate -format Logic /tb_dmac/inst_busmaster_sync/mrdy_o -add wave -noupdate -format Literal -radix hexadecimal /tb_dmac/inst_busmaster_sync/cmd_fifo_din -add wave -noupdate -format Literal -radix hexadecimal /tb_dmac/inst_busmaster_sync/cmd_fifo_dout -add wave -noupdate -format Logic /tb_dmac/inst_busmaster_sync/cmd_fifo_re -add wave -noupdate -format Logic /tb_dmac/inst_busmaster_sync/cmd_fifo_we -add wave -noupdate -format Logic /tb_dmac/inst_busmaster_sync/cmd_fifo_full -add wave -noupdate -format Logic /tb_dmac/inst_busmaster_sync/cmd_fifo_empty -add wave -noupdate -format Logic /tb_dmac/inst_busmaster_sync/read_fifo_re -add wave -noupdate -format Logic /tb_dmac/inst_busmaster_sync/read_fifo_we -add wave -noupdate -format Logic /tb_dmac/inst_busmaster_sync/read_fifo_full -add wave -noupdate -format Logic /tb_dmac/inst_busmaster_sync/read_fifo_empty -add wave -noupdate -format Logic /tb_dmac/inst_busmaster_sync/write_fifo_re -add wave -noupdate -format Logic /tb_dmac/inst_busmaster_sync/write_fifo_we -add wave -noupdate -format Logic /tb_dmac/inst_busmaster_sync/write_fifo_full -add wave -noupdate -format Logic /tb_dmac/inst_busmaster_sync/write_fifo_empty -add wave -noupdate -format Logic /tb_dmac/inst_busmaster_sync/cycle_busy -add wave -noupdate -format Logic /tb_dmac/inst_busmaster_sync/cmd_en -add wave -noupdate -format Logic /tb_dmac/inst_busmaster_sync/cmd_read_en -add wave -noupdate -format Literal /tb_dmac/inst_busmaster_sync/read_cnt -add wave -noupdate -format Logic /tb_dmac/inst_busmaster_sync/write -add wave -noupdate -divider JBUS -add wave -noupdate -format Logic /tb_dmac/clk_o -add wave -noupdate -format Logic /tb_dmac/rst_o -add wave -noupdate -format Logic /tb_dmac/int_o -add wave -noupdate -format Logic /tb_dmac/cyc_o -add wave -noupdate -format Logic /tb_dmac/stb_o -add wave -noupdate -format Logic /tb_dmac/we_o -add wave -noupdate -format Literal /tb_dmac/sel_o -add wave -noupdate -format Logic /tb_dmac/ack_i -add wave -noupdate -format Logic /tb_dmac/mrdy_o -add wave -noupdate -format Logic /tb_dmac/srdy_i -add wave -noupdate -format Literal -radix hexadecimal /tb_dmac/addr_o -add wave -noupdate -format Literal -radix hexadecimal /tb_dmac/mdat_i -add wave -noupdate -format Literal -radix hexadecimal /tb_dmac/mdat_o -add wave -noupdate -divider {DMA 0} -add wave -noupdate -format Logic /tb_dmac/gen_uut__0/inst_uut/clk -add wave -noupdate -format Logic /tb_dmac/gen_uut__0/inst_uut/rst -add wave -noupdate -format Logic /tb_dmac/gen_uut__0/inst_uut/master_req -add wave -noupdate -format Logic /tb_dmac/gen_uut__0/inst_uut/master_gnt -add wave -noupdate -format Logic /tb_dmac/gen_uut__0/inst_uut/dma_start -add wave -noupdate -format Logic /tb_dmac/gen_uut__0/inst_uut/dma_active -add wave -noupdate -format Logic /tb_dmac/gen_uut__0/inst_uut/dma_end -add wave -noupdate -format Logic /tb_dmac/gen_uut__0/inst_uut/req_rdy -add wave -noupdate -format Logic /tb_dmac/gen_uut__0/inst_uut/req_en -add wave -noupdate -format Logic /tb_dmac/gen_uut__0/inst_uut/req_rw -add wave -noupdate -format Literal -radix hexadecimal /tb_dmac/gen_uut__0/inst_uut/req_addr_start -add wave -noupdate -format Literal -radix hexadecimal /tb_dmac/gen_uut__0/inst_uut/req_num_xfers -add wave -noupdate -format Logic /tb_dmac/gen_uut__0/inst_uut/req_addr_auto_inc -add wave -noupdate -format Logic /tb_dmac/gen_uut__0/inst_uut/req_complete -add wave -noupdate -format Logic /tb_dmac/gen_uut__0/inst_uut/req_complete_ack -add wave -noupdate -format Logic /tb_dmac/gen_uut__0/inst_uut/bus_cyc_complete -add wave -noupdate -format Logic /tb_dmac/gen_uut__0/inst_uut/bus_cmd_rdy -add wave -noupdate -format Logic /tb_dmac/gen_uut__0/inst_uut/bus_cmd_we -add wave -noupdate -format Logic /tb_dmac/gen_uut__0/inst_uut/bus_cmd_cycle_en -add wave -noupdate -format Literal -radix hexadecimal /tb_dmac/gen_uut__0/inst_uut/bus_cmd_out -add wave -noupdate -format Logic /tb_dmac/gen_uut__0/inst_uut/start_en -add wave -noupdate -format Logic /tb_dmac/gen_uut__0/inst_uut/finish_en -add wave -noupdate -format Logic /tb_dmac/gen_uut__0/inst_uut/complete -add wave -noupdate -format Logic /tb_dmac/gen_uut__0/inst_uut/addr_inc_en -add wave -noupdate -format Literal -radix hexadecimal /tb_dmac/gen_uut__0/inst_uut/addr -add wave -noupdate -format Logic /tb_dmac/gen_uut__0/inst_uut/rw -add wave -noupdate -format Logic /tb_dmac/gen_uut__0/inst_uut/req_count_en -add wave -noupdate -format Literal -radix hexadecimal /tb_dmac/gen_uut__0/inst_uut/req_count -add wave -noupdate -format Literal -radix hexadecimal /tb_dmac/gen_uut__0/inst_uut/req_count_next -add wave -noupdate -format Logic /tb_dmac/gen_uut__0/inst_uut/req_count_rdy -add wave -noupdate -format Logic /tb_dmac/gen_uut__0/inst_uut/chunk_count_rst -add wave -noupdate -format Logic /tb_dmac/gen_uut__0/inst_uut/chunk_count_en -add wave -noupdate -format Literal -radix hexadecimal /tb_dmac/gen_uut__0/inst_uut/chunk_count -add wave -noupdate -format Literal -radix hexadecimal /tb_dmac/gen_uut__0/inst_uut/chunk_count_next -add wave -noupdate -format Logic /tb_dmac/gen_uut__0/inst_uut/chunk_count_rdy -add wave -noupdate -format Literal /tb_dmac/gen_uut__0/inst_uut/s -add wave -noupdate -divider {DMA 1} -add wave -noupdate -format Logic /tb_dmac/gen_uut__1/inst_uut/clk -add wave -noupdate -format Logic /tb_dmac/gen_uut__1/inst_uut/rst -add wave -noupdate -format Logic /tb_dmac/gen_uut__1/inst_uut/master_req -add wave -noupdate -format Logic /tb_dmac/gen_uut__1/inst_uut/master_gnt -add wave -noupdate -format Logic /tb_dmac/gen_uut__1/inst_uut/dma_start -add wave -noupdate -format Logic /tb_dmac/gen_uut__1/inst_uut/dma_active -add wave -noupdate -format Logic /tb_dmac/gen_uut__1/inst_uut/dma_end -add wave -noupdate -format Logic /tb_dmac/gen_uut__1/inst_uut/req_rdy -add wave -noupdate -format Logic /tb_dmac/gen_uut__1/inst_uut/req_en -add wave -noupdate -format Logic /tb_dmac/gen_uut__1/inst_uut/req_rw -add wave -noupdate -format Literal -radix hexadecimal /tb_dmac/gen_uut__1/inst_uut/req_addr_start -add wave -noupdate -format Literal -radix hexadecimal /tb_dmac/gen_uut__1/inst_uut/req_num_xfers -add wave -noupdate -format Logic /tb_dmac/gen_uut__1/inst_uut/req_addr_auto_inc -add wave -noupdate -format Logic /tb_dmac/gen_uut__1/inst_uut/req_complete -add wave -noupdate -format Logic /tb_dmac/gen_uut__1/inst_uut/req_complete_ack -add wave -noupdate -format Logic /tb_dmac/gen_uut__1/inst_uut/bus_cyc_complete -add wave -noupdate -format Logic /tb_dmac/gen_uut__1/inst_uut/bus_cmd_rdy -add wave -noupdate -format Logic /tb_dmac/gen_uut__1/inst_uut/bus_cmd_we -add wave -noupdate -format Logic /tb_dmac/gen_uut__1/inst_uut/bus_cmd_cycle_en -add wave -noupdate -format Literal -radix hexadecimal /tb_dmac/gen_uut__1/inst_uut/bus_cmd_out -add wave -noupdate -format Logic /tb_dmac/gen_uut__1/inst_uut/start_en -add wave -noupdate -format Logic /tb_dmac/gen_uut__1/inst_uut/finish_en -add wave -noupdate -format Logic /tb_dmac/gen_uut__1/inst_uut/complete -add wave -noupdate -format Logic /tb_dmac/gen_uut__1/inst_uut/addr_inc_en -add wave -noupdate -format Literal -radix hexadecimal /tb_dmac/gen_uut__1/inst_uut/addr -add wave -noupdate -format Logic /tb_dmac/gen_uut__1/inst_uut/rw -add wave -noupdate -format Logic /tb_dmac/gen_uut__1/inst_uut/req_count_en -add wave -noupdate -format Literal -radix hexadecimal /tb_dmac/gen_uut__1/inst_uut/req_count -add wave -noupdate -format Literal -radix hexadecimal /tb_dmac/gen_uut__1/inst_uut/req_count_next -add wave -noupdate -format Logic /tb_dmac/gen_uut__1/inst_uut/req_count_rdy -add wave -noupdate -format Logic /tb_dmac/gen_uut__1/inst_uut/chunk_count_rst -add wave -noupdate -format Logic /tb_dmac/gen_uut__1/inst_uut/chunk_count_en -add wave -noupdate -format Literal -radix hexadecimal /tb_dmac/gen_uut__1/inst_uut/chunk_count -add wave -noupdate -format Literal -radix hexadecimal /tb_dmac/gen_uut__1/inst_uut/chunk_count_next -add wave -noupdate -format Logic /tb_dmac/gen_uut__1/inst_uut/chunk_count_rdy -add wave -noupdate -format Literal /tb_dmac/gen_uut__1/inst_uut/s -add wave -noupdate -divider {Read FIFO} -add wave -noupdate -format Literal -radix hexadecimal /tb_dmac/data_gen_reg -add wave -noupdate -format Logic /tb_dmac/data_gen_reg_inc -add wave -noupdate -format Literal /tb_dmac/dma_write_source -add wave -noupdate -format Logic /tb_dmac/read_fifo_re -add wave -noupdate -format Logic /tb_dmac/read_fifo_we -add wave -noupdate -format Logic /tb_dmac/read_fifo_full -add wave -noupdate -format Logic /tb_dmac/read_fifo_empty -add wave -noupdate -format Literal -radix hexadecimal /tb_dmac/read_fifo_din -add wave -noupdate -format Literal -radix hexadecimal /tb_dmac/read_fifo_dout -add wave -noupdate -divider RAM -add wave -noupdate -format Literal /tb_dmac/state -add wave -noupdate -format Literal -radix hexadecimal /tb_dmac/ram64 -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {3159968 ps} 0} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -update -WaveRestoreZoom {0 ps} {6300 ns} diff --git a/lib/JBUS/src/busmaster_async.vhd b/lib/JBUS/src/busmaster_async.vhd deleted file mode 100644 index 3c5a90b..0000000 --- a/lib/JBUS/src/busmaster_async.vhd +++ /dev/null @@ -1,277 +0,0 @@ ------------------------------------------------------------------------ --- $Header: /tmp/cvsroot/VHDL/lib/JBUS/src/busmaster_async.vhd,v 1.2 2013-08-04 17:58:37 jens Exp $ ------------------------------------------------------------------------ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -use work.utils_pkg.all; -use work.busmaster_types.all; - ------------------------------------------------------------------- -entity busmaster_async is - Generic - ( - DATA_WIDTH : natural := 32; - FIFO_DEPTH : natural := 4 - ); - Port - ( - clk : in std_logic; - rst : in std_logic; - - cmd_cycle_finished : out std_logic; - cmd_cycle_en : in std_logic; - cmd_rdy : out std_logic; - cmd_we : in std_logic; - - cmd_in : in bm_cmd_t; - - din : in unsigned(DATA_WIDTH-1 downto 0); - din_rdy : out std_logic; - din_we : in std_logic; - - dout : out unsigned(DATA_WIDTH-1 downto 0); - dout_vld : out std_logic; - dout_re : in std_logic; - - -- J-BUS signals - RST_I : in STD_LOGIC; - CLK_I : in STD_LOGIC; - ACK_I : in std_logic; - SRDY_I : in std_logic; - MDAT_I : in unsigned(DATA_WIDTH-1 downto 0); - MDAT_O : out unsigned(DATA_WIDTH-1 downto 0); - ADDR_O : out unsigned(31 downto 0); - SEL_O : out unsigned(DATA_WIDTH/8-1 downto 0); - WE_O : out std_logic; - CYC_O : out std_logic; - STB_O : out std_logic; - MRDY_O : out std_logic - ); - end busmaster_async; - -architecture Behavioral of busmaster_async is - - -- Bus Command FIFO - signal cmd_fifo_din : unsigned(32+DATA_WIDTH/8+1-1 downto 0); - signal cmd_fifo_dout : unsigned(32+DATA_WIDTH/8+1-1 downto 0); - signal cmd_fifo_re : std_logic; - signal cmd_fifo_we : std_logic; - signal cmd_fifo_full : std_logic; - signal cmd_fifo_empty : std_logic; - - -- Bus Read FIFO - signal read_fifo_re : std_logic; - signal read_fifo_we : std_logic; - signal read_fifo_full : std_logic; - signal read_fifo_empty : std_logic; - signal write_fifo_re : std_logic; - signal write_fifo_we : std_logic; - signal write_fifo_full : std_logic; - signal write_fifo_empty : std_logic; - signal cycle_busy : std_logic; - signal cmd_en : std_logic; - signal cmd_read_en : std_logic; - signal read_cnt : integer range 0 to 65535; - signal write : std_logic; - - signal jbus_cycle_busy : std_logic; - - type jbus_state_t is (init, ready, start, wait_finish, finish1, finish2, finish3); - signal jbus_state : jbus_state_t; - signal jbus_state_next : jbus_state_t; - -begin - - cmd_en <= cmd_cycle_en and cmd_we and not cmd_fifo_full; - cmd_read_en <= cmd_en and not cmd_in.rw; - write <= cmd_fifo_dout(32+DATA_WIDTH/8); - - dout_vld <= not read_fifo_empty; - MRDY_O <= not read_fifo_full; - read_fifo_we <= ACK_I and jbus_cycle_busy; - read_fifo_re <= dout_re; - ADDR_O <= cmd_fifo_dout(31 downto 0); - SEL_O <= cmd_fifo_dout(32+DATA_WIDTH/8-1 downto 32); - WE_O <= write; - - cmd_fifo_din <= cmd_in.rw & cmd_in.sel & cmd_in.addr; - - cmd_rdy <= not cmd_fifo_full; - - cmd_fifo_we <= cmd_en; - cmd_fifo_re <= SRDY_I and jbus_cycle_busy; - - din_rdy <= not write_fifo_full; - write_fifo_we <= din_we; - write_fifo_re <= SRDY_I and jbus_cycle_busy and write and not cmd_fifo_empty; - - CYC_O <= jbus_cycle_busy; - STB_O <= not cmd_fifo_empty; - - --- J-Bus domain -proc_JBUS_to_local_cmd_cycle_finished: - process(clk) - begin - if rising_edge(clk) then - cmd_cycle_finished <= not jbus_cycle_busy; - end if; - end process; - -proc_JBUS_cycle: - process(CLK_I) - begin - if rising_edge(CLK_I) then - jbus_cycle_busy <= cycle_busy; - end if; - end process; - -proc_bus_read_counter: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - read_cnt <= 0; - elsif cmd_read_en = '1' and read_fifo_empty = '1' then - read_cnt <= read_cnt + 1; - elsif cmd_read_en = '0' and read_fifo_empty = '0' and dout_re = '1' then - read_cnt <= read_cnt - 1; - end if; - end if; - end process; - -jbus_state_fsm_next: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - jbus_state <= init; - else - jbus_state <= jbus_state_next; - end if; - end if; - end process; - -jbus_state_fsm: - process(jbus_state, cmd_we, cmd_fifo_empty, write_fifo_empty, read_cnt) - begin - - cycle_busy <= '0'; - jbus_state_next <= jbus_state; - - case jbus_state is - - when init => - jbus_state_next <= ready; - - when ready => - if cmd_we = '1' or cmd_fifo_empty = '0' then - jbus_state_next <= start; - end if; - - when start => - cycle_busy <= '1'; - if cmd_fifo_empty = '0' then - jbus_state_next <= wait_finish; - end if; - - when wait_finish => - cycle_busy <= '1'; - if read_cnt = 0 and cmd_fifo_empty = '1' and write_fifo_empty = '1' then - jbus_state_next <= finish1; - end if; - - -- Quick and dirty hack - -- avoid buscycle to finish even if data available, - -- caused by latency of async-FIFO empty flag - when finish1 => - jbus_state_next <= finish2; - - when finish2 => - jbus_state_next <= finish3; - - when finish3 => - jbus_state_next <= ready; - if cmd_fifo_empty = '0' then - jbus_state_next <= wait_finish; - end if; - -- Quick and dirty hack - - when others => - jbus_state_next <= ready; - - end case; - end process; - --- Bus READ FIFO -inst_BM_READ_FIFO: entity work.fifo_async - GENERIC MAP - ( - addr_width => NextExpBaseTwo(FIFO_DEPTH), - data_width => DATA_WIDTH, - do_last_read_update => true - ) - PORT MAP - ( - rst => rst, - clk_r => clk, - clk_w => CLK_I, - we => read_fifo_we, - re => read_fifo_re, - fifo_full => read_fifo_full, - fifo_empty => read_fifo_empty, - fifo_afull => open, - fifo_aempty => open, - data_r => dout, - data_w => MDAT_I - ); - --- Bus WRITE FIFO -inst_BM_WRITE_FIFO: entity work.fifo_async - GENERIC MAP - ( - addr_width => NextExpBaseTwo(FIFO_DEPTH), - data_width => DATA_WIDTH, - do_last_read_update => false - ) - PORT MAP - ( - rst => rst, - clk_r => CLK_I, - clk_w => clk, - we => write_fifo_we, - re => write_fifo_re, - fifo_full => write_fifo_full, - fifo_empty => write_fifo_empty, - fifo_afull => open, - fifo_aempty => open, - data_r => MDAT_O, - data_w => din - ); - --- Bus command FIFO -inst_BM_CMD_FIFO: entity work.fifo_async - GENERIC MAP - ( - addr_width => NextExpBaseTwo(FIFO_DEPTH), - data_width => cmd_fifo_din'length, - do_last_read_update => false - ) - PORT MAP - ( - rst => rst, - clk_r => CLK_I, - clk_w => clk, - we => cmd_fifo_we, - re => cmd_fifo_re, - fifo_full => cmd_fifo_full, - fifo_empty => cmd_fifo_empty, - fifo_afull => open, - fifo_aempty => open, - data_r => cmd_fifo_dout, - data_w => cmd_fifo_din - ); - -end Behavioral; diff --git a/lib/JBUS/src/busmaster_sync.vhd b/lib/JBUS/src/busmaster_sync.vhd deleted file mode 100644 index 406e1d3..0000000 --- a/lib/JBUS/src/busmaster_sync.vhd +++ /dev/null @@ -1,216 +0,0 @@ ------------------------------------------------------------------------ --- $Header: /tmp/cvsroot/VHDL/lib/JBUS/src/busmaster_sync.vhd,v 1.6 2013-08-03 19:31:19 jens Exp $ ------------------------------------------------------------------------ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -use work.utils_pkg.all; -use work.busmaster_types.all; - ------------------------------------------------------------------- -entity busmaster_sync is - Generic - ( - DATA_WIDTH : natural := 32; - FIFO_DEPTH : natural := 4 - ); - Port - ( - clk : in std_logic; - rst : in std_logic; - - cmd_cycle_finished : out std_logic; - cmd_cycle_en : in std_logic; - cmd_rdy : out std_logic; - cmd_we : in std_logic; - - cmd_in : in bm_cmd_t; - - din : in unsigned(DATA_WIDTH-1 downto 0); - din_rdy : out std_logic; - din_we : in std_logic; - - dout : out unsigned(DATA_WIDTH-1 downto 0); - dout_vld : out std_logic; - dout_re : in std_logic; - - -- J-BUS signals - ACK_I : in std_logic; - SRDY_I : in std_logic; - MDAT_I : in unsigned(DATA_WIDTH-1 downto 0); - MDAT_O : out unsigned(DATA_WIDTH-1 downto 0); - ADDR_O : out unsigned(31 downto 0); - SEL_O : out unsigned(DATA_WIDTH/8-1 downto 0); - WE_O : out std_logic; - CYC_O : out std_logic; - STB_O : out std_logic; - MRDY_O : out std_logic - ); - end busmaster_sync; - -architecture Behavioral of busmaster_sync is - - -- Bus Command FIFO - signal cmd_fifo_din : unsigned(32+DATA_WIDTH/8+1-1 downto 0); - signal cmd_fifo_dout : unsigned(32+DATA_WIDTH/8+1-1 downto 0); - signal cmd_fifo_re : std_logic; - signal cmd_fifo_we : std_logic; - signal cmd_fifo_full : std_logic; - signal cmd_fifo_empty : std_logic; - - -- Bus Read FIFO - signal read_fifo_re : std_logic; - signal read_fifo_we : std_logic; - signal read_fifo_full : std_logic; - signal read_fifo_empty : std_logic; - signal write_fifo_re : std_logic; - signal write_fifo_we : std_logic; - signal write_fifo_full : std_logic; - signal write_fifo_empty : std_logic; - signal cycle_busy : std_logic; - signal cmd_en : std_logic; - signal cmd_read_en : std_logic; - signal read_cnt : integer range 0 to 65535; - signal write : std_logic; - -begin - - cmd_en <= cmd_cycle_en and cmd_we and not cmd_fifo_full; - cmd_read_en <= cmd_en and not cmd_in.rw; - write <= cmd_fifo_dout(32+DATA_WIDTH/8); - - dout_vld <= not read_fifo_empty; - MRDY_O <= not read_fifo_full; - read_fifo_we <= ACK_I and cycle_busy; - read_fifo_re <= dout_re; - ADDR_O <= cmd_fifo_dout(31 downto 0); - SEL_O <= cmd_fifo_dout(32+DATA_WIDTH/8-1 downto 32); - WE_O <= write; - - cmd_fifo_din <= cmd_in.rw & cmd_in.sel & cmd_in.addr; - - cmd_rdy <= not cmd_fifo_full; - - cmd_fifo_we <= cmd_en; - cmd_fifo_re <= SRDY_I and cycle_busy; - - din_rdy <= not write_fifo_full; - write_fifo_we <= din_we; - write_fifo_re <= SRDY_I and cycle_busy and write and not cmd_fifo_empty; - - STB_O <= not cmd_fifo_empty; - CYC_O <= cycle_busy; - cmd_cycle_finished <= not cycle_busy; - --- proc_bus_read_counter: --- process(clk) --- begin --- if rising_edge(clk) then --- if rst = '1' then --- read_cnt <= 0; --- elsif cmd_read_en = '1' and read_fifo_we = '0' then --- read_cnt <= read_cnt + 1; --- elsif cmd_read_en = '0' and read_fifo_we = '1' then --- read_cnt <= read_cnt - 1; --- end if; --- end if; --- end process; - -proc_bus_read_counter: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - read_cnt <= 0; - elsif cmd_read_en = '1' and read_fifo_empty = '1' then - read_cnt <= read_cnt + 1; - elsif cmd_read_en = '0' and read_fifo_empty = '0' and dout_re = '1' then - read_cnt <= read_cnt - 1; - end if; - end if; - end process; - -proc_cycle_busy: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - cycle_busy <= '0'; - elsif cmd_cycle_en = '1' then - if cmd_we = '1' then - cycle_busy <= '1'; - end if; - elsif read_cnt = 0 and cmd_fifo_empty = '1' and write_fifo_empty = '1' then - cycle_busy <= '0'; - end if; - end if; - end process; - --- Bus READ FIFO -inst_BM_READ_FIFO: entity work.fifo_sync - GENERIC MAP - ( - addr_width => NextExpBaseTwo(FIFO_DEPTH), - data_width => DATA_WIDTH, - do_last_read_update => true - ) - PORT MAP - ( - rst => rst, - clk => clk, - we => read_fifo_we, - re => read_fifo_re, - fifo_full => read_fifo_full, - fifo_empty => read_fifo_empty, - fifo_afull => open, - fifo_aempty => open, - data_w => MDAT_I, - data_r => dout - ); - --- Bus WRITE FIFO -inst_BM_WRITE_FIFO: entity work.fifo_sync - GENERIC MAP - ( - addr_width => NextExpBaseTwo(FIFO_DEPTH), - data_width => DATA_WIDTH, - do_last_read_update => false - ) - PORT MAP - ( - rst => rst, - clk => clk, - we => write_fifo_we, - re => write_fifo_re, - fifo_full => write_fifo_full, - fifo_empty => write_fifo_empty, - fifo_afull => open, - fifo_aempty => open, - data_w => din, - data_r => MDAT_O - ); - --- Bus command FIFO -inst_BM_CMD_FIFO: entity work.fifo_sync - GENERIC MAP - ( - addr_width => NextExpBaseTwo(FIFO_DEPTH), - data_width => cmd_fifo_din'length, - do_last_read_update => false - ) - PORT MAP - ( - rst => rst, - clk => clk, - we => cmd_fifo_we, - re => cmd_fifo_re, - fifo_full => cmd_fifo_full, - fifo_empty => cmd_fifo_empty, - fifo_afull => open, - fifo_aempty => open, - data_w => cmd_fifo_din, - data_r => cmd_fifo_dout - ); - -end Behavioral; diff --git a/lib/JBUS/src/busmaster_types.vhd b/lib/JBUS/src/busmaster_types.vhd deleted file mode 100644 index db77b3d..0000000 --- a/lib/JBUS/src/busmaster_types.vhd +++ /dev/null @@ -1,31 +0,0 @@ ------------------------------------------------------------------------ --- $Header: /tmp/cvsroot/VHDL/lib/JBUS/src/busmaster_types.vhd,v 1.2 2013-05-27 11:17:51 jens Exp $ ------------------------------------------------------------------------ - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; -use IEEE.MATH_REAL.ALL; - -package busmaster_types is - - -- Constants - - -- Types - - type bm_cmd_t is - record - addr : unsigned(31 downto 0); - sel : unsigned(3 downto 0); - rw : std_logic; - end record; - -end busmaster_types; - - -package body busmaster_types is - - -end busmaster_types; - - diff --git a/lib/JBUS/src/dmac.vhd b/lib/JBUS/src/dmac.vhd deleted file mode 100644 index 0674a36..0000000 --- a/lib/JBUS/src/dmac.vhd +++ /dev/null @@ -1,229 +0,0 @@ ------------------------------------------------------------------------ --- $Header: /tmp/cvsroot/VHDL/lib/JBUS/src/dmac.vhd,v 1.2 2013-05-28 11:23:15 jens Exp $ ------------------------------------------------------------------------ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -use work.utils_pkg.all; -use work.busmaster_types.all; - ------------------------------------------------------------------- -entity dmac is - Generic - ( - DATA_WIDTH : natural := 32; - XFER_CHUNK_SIZE : natural := 512 - ); - Port - ( - clk : in std_logic; - rst : in std_logic; - - master_req : out std_logic; - master_gnt : in std_logic; - - dma_start : out std_logic; - dma_active : out std_logic; - dma_end : out std_logic; - - req_rdy : out std_logic; - req_en : in std_logic; - req_rw : in std_logic; - req_addr_start : in unsigned(31 downto 0); - req_num_xfers : in unsigned(31 downto 0); - req_addr_auto_inc : in std_logic; - - req_complete : out std_logic; - req_complete_ack : in std_logic; - - -- busmaster control - bus_cyc_complete : in std_logic; - bus_cmd_rdy : in std_logic; - bus_cmd_we : out std_logic; - bus_cmd_cycle_en : out std_logic; - - -- busmaster command - bus_cmd_out : out bm_cmd_t - ); - end dmac; - -architecture Behavioral of dmac is - - signal start_en : std_logic; - signal finish_en : std_logic; - signal complete : std_logic; - signal addr_inc_en : std_logic; - signal addr : unsigned(31 downto 0); - signal rw : std_logic; - - signal req_count_en : std_logic; - signal req_count : unsigned(31 downto 0); - signal req_count_next : unsigned(32 downto 0); - signal req_count_rdy : std_logic; - - signal chunk_count_rst : std_logic; - signal chunk_count_en : std_logic; - signal chunk_count : unsigned(31 downto 0); - signal chunk_count_next : unsigned(32 downto 0); - signal chunk_count_rdy : std_logic; - - type state_t is (INIT, READY, START, SETUP, XFER, FINISH, DONE); - signal s, sn : state_t; - -begin - - bus_cmd_out.addr <= addr; - bus_cmd_out.sel <= (others => '1'); - bus_cmd_out.rw <= rw; - req_complete <= complete; - -state_next: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - s <= INIT; - else - s <= sn; - end if; - end if; - end process; - -state: - process(s, req_en, master_gnt, req_count_rdy, chunk_count_rdy, bus_cyc_complete, bus_cmd_rdy) - begin - - bus_cmd_cycle_en <= '0'; - bus_cmd_we <= '0'; - start_en <= '0'; - finish_en <= '0'; - req_count_en <= '0'; - req_rdy <= '0'; - chunk_count_rst <= '0'; - chunk_count_en <= '0'; - master_req <= '0'; - dma_start <= '0'; - dma_active <= '0'; - dma_end <= '0'; - - sn <= s; - case s is - when INIT => - sn <= READY; - - when READY => - req_rdy <= '1'; - if req_en = '1' then - start_en <= '1'; - sn <= SETUP; - end if; - - when SETUP => - dma_start <= '1'; - sn <= START; - - when START => - master_req <= '1'; - chunk_count_rst <= '1'; - if req_count_rdy = '1' then - sn <= READY; - elsif master_gnt = '1' and bus_cyc_complete = '1' then - sn <= XFER; - end if; - - when XFER => - dma_active <= '1'; - master_req <= '1'; - bus_cmd_we <= '1'; - bus_cmd_cycle_en <= '1'; - req_count_en <= bus_cmd_rdy; - chunk_count_en <= bus_cmd_rdy; - if req_count_rdy = '1' then - sn <= FINISH; - elsif chunk_count_rdy = '1' then - sn <= START; - end if; - - when FINISH => - master_req <= '1'; - if bus_cyc_complete = '1' then - sn <= DONE; - finish_en <= '1'; - end if; - - when DONE => - dma_end <= '1'; - sn <= READY; - - when others => - sn <= READY; - - end case; - end process; - -addr_gen: - process(clk) - begin - if rising_edge(clk) then - if start_en = '1' then - rw <= req_rw; - addr <= req_addr_start; - addr_inc_en <= req_addr_auto_inc; - elsif req_count_en = '1' and addr_inc_en = '1' then - addr <= addr + DATA_WIDTH/8; - end if; - end if; - end process; - - req_count_next <= ('0' & req_num_xfers) - 1 when start_en = '1' else ('0' & req_count) - 1; - req_count_rdy <= req_count_next(32); - -req_counter: - process(clk) - begin - if rising_edge(clk) then - if start_en = '1' then - req_count <= req_count_next(31 downto 0); - elsif req_count_en = '1' then - if req_count_rdy = '0' then - req_count <= req_count_next(31 downto 0); - end if; - end if; - end if; - end process; - - chunk_count_next <= to_unsigned(XFER_CHUNK_SIZE, 33) - 1 when chunk_count_rst = '1' else ('0' & chunk_count) - 1; - chunk_count_rdy <= chunk_count_next(32); - -chunk_counter: - process(clk) - begin - if rising_edge(clk) then - if chunk_count_rst = '1' then - chunk_count <= chunk_count_next(31 downto 0); - elsif chunk_count_en = '1' then - if chunk_count_rdy = '0' then - chunk_count <= chunk_count_next(31 downto 0); - end if; - end if; - end if; - end process; - -complete_register: - process(clk) - begin - if rising_edge(clk) then - if start_en = '1' or rst = '1' then - complete <= '0'; - elsif complete = '0' then - if finish_en = '1' then - complete <= '1'; - elsif req_complete_ack = '1' then - complete <= '0'; - end if; - end if; - end if; - end process; - -end Behavioral; diff --git a/lib/JBUS/src/tb_busmaster_async.vhd b/lib/JBUS/src/tb_busmaster_async.vhd deleted file mode 100644 index 353d7d8..0000000 --- a/lib/JBUS/src/tb_busmaster_async.vhd +++ /dev/null @@ -1,451 +0,0 @@ ------------------------------------------------------------------------ --- $Header: /tmp/cvsroot/VHDL/lib/JBUS/src/tb_busmaster_async.vhd,v 1.1 2013-07-21 09:21:30 jens Exp $ ------------------------------------------------------------------------ - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -use work.busmaster_types.all; - -ENTITY tb_busmaster_async IS -END tb_busmaster_async; - -ARCHITECTURE behavior OF tb_busmaster_async IS - - constant DATA_WIDTH : integer := 32; - constant CLK_PERIOD : time := 10 ns; - constant JBUS_CLK_PERIOD : time := 20 ns; - signal clk : std_logic := '1'; - signal rst : std_logic := '1'; - - signal CLK_O : std_logic := '1'; - signal RST_O : std_logic := '1'; - - -- Master - signal INT_O : std_logic; - signal CYC_O : std_logic; - signal STB_O : std_logic; - signal WE_O : std_logic; - signal SEL_O : unsigned(3 downto 0) := (others => '1'); - signal ACK_I : std_logic := '0'; - signal MRDY_O : std_logic := '1'; - signal SRDY_I : std_logic := '0'; - signal ADDR_O : unsigned(31 downto 0) := (others => '-'); - signal MDAT_I_64 : unsigned(63 downto 0) := (others => '-'); - signal MDAT_O_64 : unsigned(63 downto 0) := (others => '-'); - - signal MDAT_I : unsigned(31 downto 0) := (others => '-'); - signal MDAT_O : unsigned(31 downto 0) := (others => '-'); - - signal cmd_cycle_finished : std_logic; - signal cmd_cycle_en : std_logic := '0'; - signal cmd_rdy : std_logic; - signal cmd_we : std_logic := '0'; - - signal cmd_in : bm_cmd_t; - - signal din : unsigned(31 downto 0) := (others => '-'); - signal din_rdy : std_logic; - signal din_we : std_logic := '0'; - - signal dout : unsigned(31 downto 0); - signal dout_vld : std_logic; - signal dout_re : std_logic := '0'; - - signal read_reg : unsigned(31 downto 0) := (others => '-'); - - type state_t is (IDLE, LA_SA, LA_SU, LU_SA, LU_SU, CC_SA, CC_SU); - signal state : state_t := IDLE; - - type ram_t is array (0 to 127) of unsigned(63 downto 0); - - signal ram64 : ram_t := - ( - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - - - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000" - - ); - -BEGIN - - MDAT_I <= MDAT_I_64(31 downto 0); - MDAT_O_64 <= MDAT_O & MDAT_O; - -inst_uut : entity work.busmaster_async - GENERIC MAP - ( - DATA_WIDTH => 32, - FIFO_DEPTH => 2 - ) - PORT MAP - ( - -- System signals - rst => rst, - clk => clk, - - cmd_cycle_finished => cmd_cycle_finished, - cmd_cycle_en => cmd_cycle_en, - cmd_rdy => cmd_rdy, - cmd_we => cmd_we, - cmd_in => cmd_in, - - din => din, - din_rdy => din_rdy, - din_we => din_we, - - dout => dout, - dout_vld => dout_vld, - dout_re => dout_re, - - -- JBUS Master signals - RST_I => RST_O, - CLK_I => CLK_O, - CYC_O => CYC_O, - STB_O => STB_O, - WE_O => WE_O, - SEL_O => SEL_O, - ACK_I => ACK_I, - SRDY_I => SRDY_I, - MRDY_O => MRDY_O, - ADDR_O => ADDR_O, - MDAT_I => MDAT_I, - MDAT_O => MDAT_O - ); - -CLK_GEN: process - begin - wait for CLK_PERIOD/2; - clk <= not clk; - end process; - -JBUS_CLK_GEN: process - begin - wait for JBUS_CLK_PERIOD/2; - CLK_O <= not CLK_O; - end process; - --- Slave - SRDY_I <= CYC_O; - - process(CLK_O) - variable res: unsigned(63 downto 0); - variable ram_data : unsigned(63 downto 0); - begin - if rising_edge(CLK_O) then - if RST_O = '1' then - else - ACK_I <= '0'; - if (CYC_O and STB_O) = '1' then - if WE_O = '0' then - ACK_I <= '1'; - ram_data := ram64(to_integer(ADDR_O(31 downto 3))); - if ADDR_O(2) = '0' then - res := ram_data; - else - res := ram_data(31 downto 0) & ram_data(63 downto 32); - end if; - elsif MRDY_O = '1' then -- WE=1 - ram_data := ram64(to_integer(ADDR_O(31 downto 3))); - ram_data := (others => '-'); - if ADDR_O(2) = '0' then - if SEL_O = "11111111" then - ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64; - elsif SEL_O = "00001111" then - ram64(to_integer(ADDR_O(31 downto 3))) <= ram_data(63 downto 32) & MDAT_O_64(31 downto 0); - elsif SEL_O = "11110000" then - ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64(63 downto 32) & ram_data(31 downto 0); - end if; - else - if SEL_O = "11111111" then - ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64(31 downto 0) & MDAT_O_64(63 downto 32); - elsif SEL_O = "00001111" then - ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64(31 downto 0) & ram_data(31 downto 0); - elsif SEL_O = "11110000" then - ram64(to_integer(ADDR_O(31 downto 3))) <= ram_data(63 downto 32) & MDAT_O_64(63 downto 32); - end if; - end if; - end if; - end if; - if (CYC_O and MRDY_O) = '1' then - MDAT_I_64 <= res; - end if; - end if; - end if; - end process; - - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - read_reg <= X"00000000"; - elsif dout_vld = '1' then - read_reg <= dout; - end if; - end if; - end process; - dout_re <= dout_vld; - --- Master -STIMULUS: process - - variable result : unsigned(31 downto 0); - - procedure cmd_write_single(addr, sel, data : unsigned) is - begin - - din <= data; - din_we <= '1'; - wait until rising_edge(clk) and din_rdy = '1'; - din_we <= '0'; - - cmd_in.rw <= '1'; - cmd_in.sel <= sel; - cmd_in.addr <= addr; - cmd_we <= '1'; - wait until rising_edge(clk) and cmd_rdy = '1'; - cmd_we <= '0'; - - end procedure cmd_write_single; - - procedure cmd_read_single(addr : unsigned) is - begin - - cmd_in.rw <= '0'; - cmd_in.sel <= (others => '0'); - cmd_in.addr <= addr; - cmd_we <= '1'; - wait until rising_edge(clk) and cmd_rdy = '1'; - cmd_we <= '0'; - - end procedure cmd_read_single; - - begin - - wait for 6*CLK_PERIOD; - rst <= '0'; - RST_O <= '0'; - wait for 60*CLK_PERIOD; - wait until rising_edge(clk); - state <= IDLE; - - for i in 0 to 9 loop - - cmd_cycle_en <= '1'; - cmd_write_single(X"0000_0000", "1111", X"1000_ABCD"); - cmd_write_single(X"0000_0008", "1111", X"2000_ABCD"); - cmd_write_single(X"0000_0010", "1111", X"3000_ABCD"); - cmd_write_single(X"0000_0018", "1111", X"4000_ABCD"); - cmd_write_single(X"0000_0020", "1111", X"5000_ABCD"); - cmd_write_single(X"0000_0028", "1111", X"6000_ABCD"); - cmd_write_single(X"0000_0030", "1111", X"7000_ABCD"); - cmd_write_single(X"0000_0038", "1111", X"8000_ABCD"); - cmd_read_single(X"0000_0000"); - cmd_read_single(X"0000_0008"); - cmd_read_single(X"0000_0010"); - cmd_read_single(X"0000_0018"); - cmd_read_single(X"0000_0020"); - cmd_read_single(X"0000_0028"); - cmd_read_single(X"0000_0030"); - cmd_read_single(X"0000_0038"); - cmd_write_single(X"0000_0000", "1111", X"1000_BEEF"); - cmd_read_single(X"0000_0000"); - cmd_write_single(X"0000_0008", "1111", X"2000_BEEF"); - cmd_read_single(X"0000_0008"); - cmd_write_single(X"0000_0010", "1111", X"3000_BEEF"); - cmd_read_single(X"0000_0010"); - cmd_write_single(X"0000_0018", "1111", X"4000_BEEF"); - cmd_read_single(X"0000_0018"); - cmd_write_single(X"0000_0020", "1111", X"5000_BEEF"); - cmd_read_single(X"0000_0020"); - cmd_write_single(X"0000_0028", "1111", X"6000_BEEF"); - cmd_read_single(X"0000_0028"); - cmd_write_single(X"0000_0030", "1111", X"7000_BEEF"); - cmd_read_single(X"0000_0030"); - cmd_write_single(X"0000_0038", "1111", X"8000_BEEF"); - cmd_read_single(X"0000_0038"); - cmd_cycle_en <= '0'; - wait until rising_edge(clk); - wait until rising_edge(clk); - cmd_cycle_en <= '1'; - cmd_write_single(X"0000_0100", "1111", X"1100_ABCD"); - cmd_write_single(X"0000_0108", "1111", X"2200_ABCD"); - cmd_write_single(X"0000_0110", "1111", X"3300_ABCD"); - cmd_write_single(X"0000_0118", "1111", X"4400_ABCD"); - cmd_write_single(X"0000_0120", "1111", X"5500_ABCD"); - cmd_write_single(X"0000_0128", "1111", X"6600_ABCD"); - cmd_write_single(X"0000_0130", "1111", X"7700_ABCD"); - cmd_write_single(X"0000_0138", "1111", X"8800_ABCD"); - cmd_read_single(X"0000_0100"); - cmd_read_single(X"0000_0108"); - cmd_read_single(X"0000_0110"); - cmd_read_single(X"0000_0118"); - cmd_read_single(X"0000_0120"); - cmd_read_single(X"0000_0128"); - cmd_read_single(X"0000_0130"); - cmd_read_single(X"0000_0138"); - cmd_write_single(X"0000_0100", "1111", X"1100_BEEF"); - cmd_read_single(X"0000_0100"); - cmd_write_single(X"0000_0108", "1111", X"2200_BEEF"); - cmd_read_single(X"0000_0108"); - cmd_write_single(X"0000_0110", "1111", X"3300_BEEF"); - cmd_read_single(X"0000_0110"); - cmd_write_single(X"0000_0118", "1111", X"4400_BEEF"); - cmd_read_single(X"0000_0118"); - cmd_write_single(X"0000_0120", "1111", X"5500_BEEF"); - cmd_read_single(X"0000_0120"); - cmd_write_single(X"0000_0128", "1111", X"6600_BEEF"); - cmd_read_single(X"0000_0128"); - cmd_write_single(X"0000_0130", "1111", X"7700_BEEF"); - cmd_read_single(X"0000_0130"); - cmd_write_single(X"0000_0138", "1111", X"8800_BEEF"); - cmd_read_single(X"0000_0138"); - cmd_cycle_en <= '0'; - - wait until rising_edge(clk) and cmd_cycle_finished = '1'; - wait for 60*CLK_PERIOD; - wait until rising_edge(clk); - - end loop; - - state <= IDLE; - - wait; - - end process; - -END; diff --git a/lib/JBUS/src/tb_busmaster_sync.vhd b/lib/JBUS/src/tb_busmaster_sync.vhd deleted file mode 100644 index 1e656f6..0000000 --- a/lib/JBUS/src/tb_busmaster_sync.vhd +++ /dev/null @@ -1,446 +0,0 @@ ------------------------------------------------------------------------ --- $Header: /tmp/cvsroot/VHDL/lib/JBUS/src/tb_busmaster_sync.vhd,v 1.3 2013-07-21 09:10:13 jens Exp $ ------------------------------------------------------------------------ - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -use work.busmaster_types.all; - -ENTITY tb_busmaster_sync IS -END tb_busmaster_sync; - -ARCHITECTURE behavior OF tb_busmaster_sync IS - - constant DATA_WIDTH : integer := 32; - constant CLK_PERIOD : time := 10 ns; - signal CLK_O : std_logic := '1'; - signal RST_O : std_logic := '1'; - - -- Master - signal INT_O : std_logic; - signal CYC_O : std_logic; - signal STB_O : std_logic; - signal WE_O : std_logic; - signal SEL_O : unsigned(3 downto 0) := (others => '1'); - signal ACK_I : std_logic := '0'; - signal MRDY_O : std_logic := '1'; - signal SRDY_I : std_logic := '0'; - signal ADDR_O : unsigned(31 downto 0) := (others => '-'); - signal MDAT_I_64 : unsigned(63 downto 0) := (others => '-'); - signal MDAT_O_64 : unsigned(63 downto 0) := (others => '-'); - - signal MDAT_I : unsigned(31 downto 0) := (others => '-'); - signal MDAT_O : unsigned(31 downto 0) := (others => '-'); - - signal cmd_cycle_finished : std_logic; - signal cmd_cycle_en : std_logic := '0'; - signal cmd_rdy : std_logic; - signal cmd_we : std_logic := '0'; - - signal cmd_in : bm_cmd_t; - - signal din : unsigned(31 downto 0) := (others => '-'); - signal din_rdy : std_logic; - signal din_we : std_logic := '0'; - - signal dout : unsigned(31 downto 0); - signal dout_vld : std_logic; - signal dout_re : std_logic := '0'; - - signal rdy : std_logic := '0'; - signal read_reg : unsigned(31 downto 0) := (others => '-'); - - type state_t is (IDLE, LA_SA, LA_SU, LU_SA, LU_SU, CC_SA, CC_SU); - signal state : state_t := IDLE; - - type ram_t is array (0 to 127) of unsigned(63 downto 0); - - signal ram64 : ram_t := - ( - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - - - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000" - - ); - -BEGIN - - MDAT_I <= MDAT_I_64(31 downto 0); - MDAT_O_64 <= MDAT_O & MDAT_O; - -inst_uut : entity work.busmaster_sync - GENERIC MAP - ( - DATA_WIDTH => 32, - FIFO_DEPTH => 2 - ) - PORT MAP - ( - -- System signals - rst => RST_O, - clk => CLK_O, - - cmd_cycle_finished => cmd_cycle_finished, - cmd_cycle_en => cmd_cycle_en, - cmd_rdy => cmd_rdy, - cmd_we => cmd_we, - cmd_in => cmd_in, - - din => din, - din_rdy => din_rdy, - din_we => din_we, - - dout => dout, - dout_vld => dout_vld, - dout_re => dout_re, - - -- JBUS Master signals - CYC_O => CYC_O, - STB_O => STB_O, - WE_O => WE_O, - SEL_O => SEL_O, - ACK_I => ACK_I, - SRDY_I => SRDY_I, - MRDY_O => MRDY_O, - ADDR_O => ADDR_O, - MDAT_I => MDAT_I, - MDAT_O => MDAT_O - ); - -rdy_GEN: process - begin --- wait for 3*CLK_PERIOD/2; - wait until rising_edge(CLK_O); - rdy <= not rdy; - end process; - -CLK_GEN: process - begin - wait for CLK_PERIOD/2; - CLK_O <= not CLK_O; - end process; - --- Slave - SRDY_I <= CYC_O; - - process(CLK_O) - variable res: unsigned(63 downto 0); - variable ram_data : unsigned(63 downto 0); - begin - if rising_edge(CLK_O) then - if RST_O = '1' then - else - ACK_I <= '0'; - if (CYC_O and STB_O) = '1' then - if WE_O = '0' then - ACK_I <= '1'; - ram_data := ram64(to_integer(ADDR_O(31 downto 3))); - if ADDR_O(2) = '0' then - res := ram_data; - else - res := ram_data(31 downto 0) & ram_data(63 downto 32); - end if; - elsif MRDY_O = '1' then -- WE=1 - ram_data := ram64(to_integer(ADDR_O(31 downto 3))); - ram_data := (others => '-'); - if ADDR_O(2) = '0' then - if SEL_O = "11111111" then - ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64; - elsif SEL_O = "00001111" then - ram64(to_integer(ADDR_O(31 downto 3))) <= ram_data(63 downto 32) & MDAT_O_64(31 downto 0); - elsif SEL_O = "11110000" then - ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64(63 downto 32) & ram_data(31 downto 0); - end if; - else - if SEL_O = "11111111" then - ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64(31 downto 0) & MDAT_O_64(63 downto 32); - elsif SEL_O = "00001111" then - ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64(31 downto 0) & ram_data(31 downto 0); - elsif SEL_O = "11110000" then - ram64(to_integer(ADDR_O(31 downto 3))) <= ram_data(63 downto 32) & MDAT_O_64(63 downto 32); - end if; - end if; - end if; - end if; - if (CYC_O and MRDY_O) = '1' then - MDAT_I_64 <= res; - end if; - end if; - end if; - end process; - - process(CLK_O) - begin - if rising_edge(CLK_O) then - if RST_O = '1' then - read_reg <= X"00000000"; - elsif dout_vld = '1' then - read_reg <= dout; - end if; - end if; - end process; - dout_re <= dout_vld; - --- Master -STIMULUS: process - - variable result : unsigned(31 downto 0); - - procedure cmd_write_single(addr, sel, data : unsigned) is - begin - - din <= data; - din_we <= '1'; - wait until rising_edge(CLK_O) and din_rdy = '1'; - din_we <= '0'; - - cmd_in.rw <= '1'; - cmd_in.sel <= sel; - cmd_in.addr <= addr; - cmd_we <= '1'; - wait until rising_edge(CLK_O) and cmd_rdy = '1'; - cmd_we <= '0'; - - end procedure cmd_write_single; - - procedure cmd_read_single(addr : unsigned) is - begin - - cmd_in.rw <= '0'; - cmd_in.sel <= (others => '0'); - cmd_in.addr <= addr; - cmd_we <= '1'; - wait until rising_edge(CLK_O) and cmd_rdy = '1'; - cmd_we <= '0'; - - end procedure cmd_read_single; - - begin - - wait for 6*CLK_PERIOD; - RST_O <= '0'; - wait for 60*CLK_PERIOD; - wait until rising_edge(CLK_O); - state <= IDLE; - - for i in 0 to 9 loop - - cmd_cycle_en <= '1'; - cmd_write_single(X"0000_0000", "1111", X"1000_ABCD"); - cmd_write_single(X"0000_0008", "1111", X"2000_ABCD"); - cmd_write_single(X"0000_0010", "1111", X"3000_ABCD"); - cmd_write_single(X"0000_0018", "1111", X"4000_ABCD"); - cmd_write_single(X"0000_0020", "1111", X"5000_ABCD"); - cmd_write_single(X"0000_0028", "1111", X"6000_ABCD"); - cmd_write_single(X"0000_0030", "1111", X"7000_ABCD"); - cmd_write_single(X"0000_0038", "1111", X"8000_ABCD"); - cmd_read_single(X"0000_0000"); - cmd_read_single(X"0000_0008"); - cmd_read_single(X"0000_0010"); - cmd_read_single(X"0000_0018"); - cmd_read_single(X"0000_0020"); - cmd_read_single(X"0000_0028"); - cmd_read_single(X"0000_0030"); - cmd_read_single(X"0000_0038"); - cmd_write_single(X"0000_0000", "1111", X"1000_BEEF"); - cmd_read_single(X"0000_0000"); - cmd_write_single(X"0000_0008", "1111", X"2000_BEEF"); - cmd_read_single(X"0000_0008"); - cmd_write_single(X"0000_0010", "1111", X"3000_BEEF"); - cmd_read_single(X"0000_0010"); - cmd_write_single(X"0000_0018", "1111", X"4000_BEEF"); - cmd_read_single(X"0000_0018"); - cmd_write_single(X"0000_0020", "1111", X"5000_BEEF"); - cmd_read_single(X"0000_0020"); - cmd_write_single(X"0000_0028", "1111", X"6000_BEEF"); - cmd_read_single(X"0000_0028"); - cmd_write_single(X"0000_0030", "1111", X"7000_BEEF"); - cmd_read_single(X"0000_0030"); - cmd_write_single(X"0000_0038", "1111", X"8000_BEEF"); - cmd_read_single(X"0000_0038"); - cmd_cycle_en <= '0'; - wait until rising_edge(CLK_O); - wait until rising_edge(CLK_O); - cmd_cycle_en <= '1'; - cmd_write_single(X"0000_0100", "1111", X"1100_ABCD"); - cmd_write_single(X"0000_0108", "1111", X"2200_ABCD"); - cmd_write_single(X"0000_0110", "1111", X"3300_ABCD"); - cmd_write_single(X"0000_0118", "1111", X"4400_ABCD"); - cmd_write_single(X"0000_0120", "1111", X"5500_ABCD"); - cmd_write_single(X"0000_0128", "1111", X"6600_ABCD"); - cmd_write_single(X"0000_0130", "1111", X"7700_ABCD"); - cmd_write_single(X"0000_0138", "1111", X"8800_ABCD"); - cmd_read_single(X"0000_0100"); - cmd_read_single(X"0000_0108"); - cmd_read_single(X"0000_0110"); - cmd_read_single(X"0000_0118"); - cmd_read_single(X"0000_0120"); - cmd_read_single(X"0000_0128"); - cmd_read_single(X"0000_0130"); - cmd_read_single(X"0000_0138"); - cmd_write_single(X"0000_0100", "1111", X"1100_BEEF"); - cmd_read_single(X"0000_0100"); - cmd_write_single(X"0000_0108", "1111", X"2200_BEEF"); - cmd_read_single(X"0000_0108"); - cmd_write_single(X"0000_0110", "1111", X"3300_BEEF"); - cmd_read_single(X"0000_0110"); - cmd_write_single(X"0000_0118", "1111", X"4400_BEEF"); - cmd_read_single(X"0000_0118"); - cmd_write_single(X"0000_0120", "1111", X"5500_BEEF"); - cmd_read_single(X"0000_0120"); - cmd_write_single(X"0000_0128", "1111", X"6600_BEEF"); - cmd_read_single(X"0000_0128"); - cmd_write_single(X"0000_0130", "1111", X"7700_BEEF"); - cmd_read_single(X"0000_0130"); - cmd_write_single(X"0000_0138", "1111", X"8800_BEEF"); - cmd_read_single(X"0000_0138"); - cmd_cycle_en <= '0'; - - wait until rising_edge(CLK_O) and cmd_cycle_finished = '1'; - wait for 60*CLK_PERIOD; - wait until rising_edge(CLK_O); - - end loop; - - state <= IDLE; - - wait; - - end process; - -END; diff --git a/lib/JBUS/src/tb_dmac.vhd b/lib/JBUS/src/tb_dmac.vhd deleted file mode 100644 index e22af1f..0000000 --- a/lib/JBUS/src/tb_dmac.vhd +++ /dev/null @@ -1,540 +0,0 @@ ------------------------------------------------------------------------ --- $Header: /tmp/cvsroot/VHDL/lib/JBUS/src/tb_dmac.vhd,v 1.2 2013-05-28 11:23:15 jens Exp $ ------------------------------------------------------------------------ - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -use work.busmaster_types.all; - -ENTITY tb_dmac IS -END tb_dmac; - -ARCHITECTURE behavior OF tb_dmac IS - - constant CLK_PERIOD : time := 10 ns; - constant DATA_WIDTH : integer := 32; - - constant DMA_NUM_CHANNEL : integer := 2; - constant DMA_CH_WRITE : integer := 0; - constant DMA_CH_READ : integer := 1; - constant DMA_RW_CONF : unsigned(DMA_NUM_CHANNEL-1 downto 0) := "01"; - - signal CLK_O : std_logic := '1'; - signal RST_O : std_logic := '1'; - - -- Master - signal CYC_O : std_logic; - signal STB_O : std_logic; - signal WE_O : std_logic; - signal SEL_O : unsigned(3 downto 0) := (others => '1'); - signal ACK_I : std_logic := '0'; - signal MRDY_O : std_logic := '1'; - signal SRDY_I : std_logic := '0'; - signal ADDR_O : unsigned(31 downto 0) := (others => '-'); - signal MDAT_I_64 : unsigned(63 downto 0) := (others => '-'); - signal MDAT_O_64 : unsigned(63 downto 0) := (others => '-'); - - signal MDAT_I : unsigned(31 downto 0) := (others => '-'); - signal MDAT_O : unsigned(31 downto 0) := (others => '-'); - - -- DMA controller - signal dma_master_req : unsigned(DMA_NUM_CHANNEL-1 downto 0); - signal dma_master_gnt : unsigned(DMA_NUM_CHANNEL-1 downto 0) := (others => '0'); - signal dma_req_rdy : unsigned(DMA_NUM_CHANNEL-1 downto 0); - signal dma_req_en : unsigned(DMA_NUM_CHANNEL-1 downto 0) := (others => '0'); - signal dma_req_addr_auto_inc : unsigned(DMA_NUM_CHANNEL-1 downto 0); - type array32_t is array (0 to DMA_NUM_CHANNEL-1) of unsigned(31 downto 0); - signal dma_req_addr : array32_t; - signal dma_req_num_xfers : array32_t; - - signal dma_req_complete : unsigned(DMA_NUM_CHANNEL-1 downto 0); - signal dma_req_complete_ack : unsigned(DMA_NUM_CHANNEL-1 downto 0) := (others => '0'); - - signal dma_start : unsigned(DMA_NUM_CHANNEL-1 downto 0); - signal dma_active : unsigned(DMA_NUM_CHANNEL-1 downto 0); - signal dma_end : unsigned(DMA_NUM_CHANNEL-1 downto 0); - signal dma_bus_cmd_cycle_finished : unsigned(DMA_NUM_CHANNEL-1 downto 0); - signal dma_bus_cmd_cycle_en : unsigned(DMA_NUM_CHANNEL-1 downto 0) := (others => '0'); - signal dma_bus_cmd_rdy : unsigned(DMA_NUM_CHANNEL-1 downto 0); - signal dma_bus_cmd_we : unsigned(DMA_NUM_CHANNEL-1 downto 0) := (others => '0'); - type array_bus_cmd_t is array (0 to DMA_NUM_CHANNEL-1) of bm_cmd_t; - signal dma_bus_cmd : array_bus_cmd_t; - - signal arb_idx : natural range 0 to DMA_NUM_CHANNEL-1; - - -- BUS Master controller - signal bus_din_re : std_logic; - signal bus_cmd_cycle_finished : std_logic; - signal bus_cmd_cycle_en : std_logic := '0'; - signal bus_cmd_rdy : std_logic; - signal bus_cmd_we : std_logic := '0'; - signal bus_cmd : bm_cmd_t; - - signal bus_din_rdy : std_logic; - signal bus_din_vld : std_logic := '0'; - signal bus_din : unsigned(DATA_WIDTH-1 downto 0) := (others => '-'); - - signal bus_dout : unsigned(31 downto 0); - signal bus_dout_vld : std_logic; - signal bus_dout_re : std_logic := '0'; - - signal rdy : std_logic := '0'; - signal read_reg : unsigned(31 downto 0) := (others => '-'); - - signal data_gen_reg : unsigned(31 downto 0) := (others => '-'); - signal data_gen_reg_inc : std_logic; - signal data_req : std_logic; - - type dma_write_source_t is (DATA_GEN, READ_FIFO); - signal dma_write_source : dma_write_source_t := DATA_GEN; - - -- Read FIFO - signal read_fifo_re : std_logic; - signal read_fifo_we : std_logic; - signal read_fifo_full : std_logic; - signal read_fifo_empty : std_logic; - signal read_fifo_din : unsigned(31 downto 0); - signal read_fifo_dout : unsigned(31 downto 0); - - type state_t is (IDLE, LA_SA, LA_SU, LU_SA, LU_SU, CC_SA, CC_SU); - signal state : state_t := IDLE; - - type ram_t is array (0 to 127) of unsigned(63 downto 0); - - signal ram64 : ram_t := - ( - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - - - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000" - - ); - -BEGIN - - MDAT_I <= MDAT_I_64(31 downto 0); - MDAT_O_64 <= MDAT_O & MDAT_O; - -arbiter_proc: - process(CLK_O) - begin - if rising_edge(CLK_O) then - if RST_O = '1' then - dma_master_gnt <= (others => '0'); - arb_idx <= 0; - elsif dma_master_req(arb_idx) = '0' then - if arb_idx /= DMA_NUM_CHANNEL-1 then - arb_idx <= arb_idx + 1; - else - arb_idx <= 0; - end if; - else - dma_master_gnt <= (others => '0'); - dma_master_gnt(arb_idx) <= '1'; - end if; - end if; - end process; - -arbiter_mux: - process(dma_master_gnt, dma_bus_cmd, dma_bus_cmd_we, dma_bus_cmd_cycle_en) - variable v_bus_cmd_we : std_logic; - variable v_bus_cmd_cycle_en : std_logic; - begin - v_bus_cmd_we := '0'; - v_bus_cmd_cycle_en := '0'; - for i in 0 to DMA_NUM_CHANNEL-1 loop - v_bus_cmd_we := v_bus_cmd_we or dma_bus_cmd_we(i); - v_bus_cmd_cycle_en := v_bus_cmd_cycle_en or dma_bus_cmd_cycle_en(i); - if dma_master_gnt(i) = '1' then - bus_cmd <= dma_bus_cmd(i); - end if; - end loop; - bus_cmd_we <= v_bus_cmd_we; - bus_cmd_cycle_en <= v_bus_cmd_cycle_en; -end process; - - -gen_uut: -for i in 0 to DMA_NUM_CHANNEL-1 generate - - dma_bus_cmd_cycle_finished(i) <= bus_cmd_cycle_finished; - dma_bus_cmd_rdy(i) <= bus_cmd_rdy; - - inst_uut : entity work.dmac - Generic map - ( - DATA_WIDTH => 32, - XFER_CHUNK_SIZE => 8 - ) - Port map - ( - clk => CLK_O, - rst => RST_O, - - master_req => dma_master_req(i), - master_gnt => dma_master_gnt(i), - - req_rdy => dma_req_rdy(i), - req_en => dma_req_en(i), - req_rw => DMA_RW_CONF(i), - req_addr_auto_inc => dma_req_addr_auto_inc(i), - req_addr_start => dma_req_addr(i), - req_num_xfers => dma_req_num_xfers(i), - - req_complete => dma_req_complete(i), - req_complete_ack => dma_req_complete_ack(i), - - dma_start => dma_start(i), - dma_active => dma_active(i), - dma_end => dma_end(i), - - -- busmaster control - bus_cyc_complete => dma_bus_cmd_cycle_finished(i), - bus_cmd_rdy => dma_bus_cmd_rdy(i), - bus_cmd_we => dma_bus_cmd_we(i), - bus_cmd_cycle_en => dma_bus_cmd_cycle_en(i), - - -- busmaster command - bus_cmd_out => dma_bus_cmd(i) - ); - -end generate; - --- Read buffer -inst_DMA_READ_FIFO: entity work.fifo_sync - GENERIC MAP - ( - addr_width => 10, - data_width => DATA_WIDTH, - do_last_read_update => true - ) - PORT MAP - ( - rst => RST_O, - clk => CLK_O, - we => read_fifo_we, - re => read_fifo_re, - fifo_full => read_fifo_full, - fifo_empty => read_fifo_empty, - fifo_afull => open, - fifo_aempty => open, - data_w => read_fifo_din, - data_r => read_fifo_dout - ); - -inst_busmaster_sync : entity work.busmaster_sync - GENERIC MAP - ( - DATA_WIDTH => DATA_WIDTH, - FIFO_DEPTH => 4 - ) - PORT MAP - ( - -- System signals - rst => RST_O, - clk => CLK_O, - - cmd_cycle_finished => bus_cmd_cycle_finished, - cmd_cycle_en => bus_cmd_cycle_en, - - cmd_rdy => bus_cmd_rdy, - cmd_we => bus_cmd_we, - cmd_in => bus_cmd, - - din_rdy => bus_din_rdy, - din_we => bus_din_vld, - din => bus_din, - - dout => bus_dout, - dout_vld => bus_dout_vld, - dout_re => bus_dout_re, - - -- JBUS Master signals - CYC_O => CYC_O, - STB_O => STB_O, - WE_O => WE_O, - SEL_O => SEL_O, - ACK_I => ACK_I, - SRDY_I => SRDY_I, - MRDY_O => MRDY_O, - ADDR_O => ADDR_O, - MDAT_I => MDAT_I, - MDAT_O => MDAT_O - ); - -rdy_GEN: process - begin --- wait for 3*CLK_PERIOD/2; - wait until rising_edge(CLK_O); - rdy <= not rdy; - end process; - -CLK_GEN: process - begin - wait for CLK_PERIOD/2; - CLK_O <= not CLK_O; - end process; - --- Slave - SRDY_I <= CYC_O; - - bus_dout_re <= '1' when dma_write_source = DATA_GEN else not read_fifo_full; - bus_din_vld <= dma_active(DMA_CH_WRITE) when dma_write_source = DATA_GEN else (dma_active(DMA_CH_WRITE) and not read_fifo_empty); - bus_din <= data_gen_reg when dma_write_source = DATA_GEN else read_fifo_dout; - data_gen_reg_inc <= (bus_din_rdy and dma_active(DMA_CH_WRITE)) when dma_write_source = DATA_GEN else '0'; - read_fifo_re <= (bus_din_rdy and dma_active(DMA_CH_WRITE)) when dma_write_source = READ_FIFO else '0'; - read_fifo_we <= bus_dout_vld; - read_fifo_din <= bus_dout; - - process(CLK_O) - begin - if rising_edge(CLK_O) then - if RST_O = '1' then - data_gen_reg <= X"BEEF_0000"; - elsif data_gen_reg_inc = '1' then - data_gen_reg <= data_gen_reg + X"0000_0004"; - end if; - end if; - end process; - - - process(CLK_O) - variable res: unsigned(63 downto 0); - variable ram_data : unsigned(63 downto 0); - begin - if rising_edge(CLK_O) then - if RST_O = '1' then - else - ACK_I <= '0'; - if (CYC_O and STB_O) = '1' then - if WE_O = '0' then - ACK_I <= '1'; - ram_data := ram64(to_integer(ADDR_O(31 downto 3))); - if ADDR_O(2) = '0' then - res := ram_data; - else - res := ram_data(31 downto 0) & ram_data(63 downto 32); - end if; - else -- WE=1 - ram_data := ram64(to_integer(ADDR_O(31 downto 3))); - -- ram_data := (others => '-'); - if ADDR_O(2) = '0' then - if SEL_O = "11111111" then - ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64; - elsif SEL_O = "00001111" then - ram64(to_integer(ADDR_O(31 downto 3))) <= ram_data(63 downto 32) & MDAT_O_64(31 downto 0); - elsif SEL_O = "11110000" then - ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64(63 downto 32) & ram_data(31 downto 0); - end if; - else - if SEL_O = "11111111" then - ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64(31 downto 0) & MDAT_O_64(63 downto 32); - elsif SEL_O = "00001111" then - ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64(31 downto 0) & ram_data(31 downto 0); - elsif SEL_O = "11110000" then - ram64(to_integer(ADDR_O(31 downto 3))) <= ram_data(63 downto 32) & MDAT_O_64(63 downto 32); - end if; - end if; - end if; - end if; - MDAT_I_64 <= res; - end if; - end if; - end process; - - process(CLK_O) - begin - if rising_edge(CLK_O) then - if RST_O = '1' then - read_reg <= X"00000000"; - elsif bus_dout_vld = '1' then - read_reg <= bus_dout; - end if; - end if; - end process; - - --- Master -STIMULUS: process - - procedure dma_wait_xfer_complete(ch : integer) is - begin - - dma_req_complete_ack(ch) <= '1'; - - wait until rising_edge(CLK_O) and dma_req_complete(ch) = '1'; - dma_req_complete_ack(ch) <= '0'; - - end procedure dma_wait_xfer_complete; - - procedure dma_request(ch : integer; addr_start, num_xfers : unsigned) is - begin - - dma_req_addr_auto_inc(ch) <= '1'; - dma_req_addr(ch) <= addr_start; - dma_req_num_xfers(ch) <= num_xfers; - - dma_req_en(ch) <= '1'; - - wait until rising_edge(CLK_O) and dma_req_rdy(ch) = '1'; - dma_req_en(ch) <= '0'; - - end procedure dma_request; - - begin - - wait for 6*CLK_PERIOD; - RST_O <= '0'; - wait for 60*CLK_PERIOD; - wait until rising_edge(CLK_O); - state <= IDLE; - - dma_request(DMA_CH_WRITE, X"00000000", X"00000040"); --- dma_wait_xfer_complete(DMA_CH_WRITE); - dma_request(DMA_CH_READ, X"00000000", X"00000040"); - dma_wait_xfer_complete(DMA_CH_READ); - dma_write_source <= READ_FIFO; - dma_request(DMA_CH_WRITE, X"00000100", X"00000040"); --- dma_wait_xfer_complete(DMA_CH_WRITE); - - state <= IDLE; - - wait; - - end process; - -END; diff --git a/lib/PCK_FIO-1.16/PCK_FIO.html b/lib/PCK_FIO-1.16/PCK_FIO.html deleted file mode 100644 index 8b8c8c5..0000000 --- a/lib/PCK_FIO-1.16/PCK_FIO.html +++ /dev/null @@ -1,297 +0,0 @@ - - - - - - VHDL package for formatted file output - - - - -
- -PCK_FIO - VHDL package for  formatted file output -

-

-

-Contents

-Usage -
The file output function 'fo' -
Format specifiers -
Special characters -
Things to watch out for -
Methodology notes -
Parametrization -
Test bench -
Known limitations and problems -
Author -

-

-

-Usage

-PCK_FIO is a VHDL package that defines  fprint, a function -for formatted file output. -

After installing the package you can call fprint as follows: -

  fprint(F, L, Format, fo(Expr_1), fo(Expr_2), ... fo(Expr_n));
-where F is the filehandle and L is the line variable. -

The argument Format is the format string, which consists of ``normal'' -substrings which are copied verbatim, and format specifiers, starting with -'%'. -A typical format string looks as follows: -

   "Arg1 = %6r, Arg2 = %10d, Arg3 = %-5r\n"
-The remaining arguments are the expressions whose results you want to write -to the file, embedded in fo function calls. There can be 0 to -32 of such arguments. The expressions can be of any type for which an fo -function exists. String expressions can also be called directly. -

-

-

-The file output function 'fo'

-The fo (file output) functions do the trick. They -return a tagged string representation that is meaningful to format specifiers. -Here are some examples: -
  fo (signed'("1100"))   returns "S:1100" 
-  fo (unsigned'("1100")) returns "U:1100" 
-  fo (TRUE)              returns "L:T"
-  fo (127)               returns "I:127"
-The internal behavior of fo is irrelevant to the typical user. -

The fo function is currently overloaded as follows: -

  function fo (Arg: unsigned)          return string;
-  function fo (Arg: signed)            return string;
-  function fo (Arg: std_logic_vector)  return string;
-  function fo (Arg: std_ulogic_vector) return string;
-  function fo (Arg: bit_vector)        return string;
-  function fo (Arg: integer)           return string;
-  function fo (Arg: std_ulogic)        return string;
-  function fo (Arg: bit)               return string;
-  function fo (Arg: boolean)           return string; 
-  function fo (Arg: character)         return string;
-  function fo (Arg: string)            return string;
-  function fo (Arg: time)              return string;
- -
-
- -

-Format specifiers

-The general format of a format specifier is: -
   %[-][n]c
-The optional - sign specifies left justified output; default is -right justified. -

The optional number n specifies a field-width. If it is not specified, -fprint -does something reasonable. -

c is the conversion specifier. Currently the following conversion -specifiers are supported: -

-
-r
- -
-reasonable output format (inspired by Synopsys VSS)
- -
Prints the ``most reasonable'' representation e.g. hex for -unsigned, signed and other bit-like vectors (not preferred for integers)
- -
-b
- -
-bit-oriented output
- -
-d
- -
-decimal output
- -
-s
- -
-string output (e.g. in combination with 'IMAGE for enum types)
- -
-q
- -
-``qualified'' string output (shows internal representation from fo)
- -
-{}
- -
-Iteration operator, used as follows:
- -
-%n{<format-string>}
- -
In this case, n is the iteration count and is mandatory. Iteration -can be nested.
- -
-

-Special characters

-To print a double-quote,  use '""' in the format string (VHDL -convention). To print the special characters, '\', and '%', -escape them with '\'. To prevent '{' and '}' -from being interpreted as opening and closing brackets in iteration strings, -escape them with '\'. -

A newline is specified in the format string by '\n'. -

-

-

-Things to notice

-The fprint function expands into VHDL write and writeline -commands. As in plain VHDL, nothing will be written to the output file -until a writeline is given. Therefore, don't forget to include -'\n' -commands in the format string, or it ``will not work''. -

The preferred format specifier for integers is, naturally, %d. -This calls the VHDL write for integers. If you specify a field -width that is too small, the field will automatically be expanded. If you -use %r for integers, the field is not expanded automatically, which -means that some digits are simply thrown away. This may sometimes be useful -but it is also dangerous. Look at the test bench output for differences -between %d and %r output. -

When using the %d format specifier, the VHDL constraints for -the allowed integer range apply. -

In VHDL, signed/unsigned types have been standardized only relatively -recently, in the package IEEE.numeric_std. The lack of a standard -has caused (and is causing) portability issues. The most popular non-standard -package that defines signed/unsigned is IEEE.std_logic_arith from -Synopsys. PCK_FIO has been developed with this latter package, and still -refers to this package by default. However, PCK_FIO  works with -IEEE.numeric_std -as well. To use IEEE.numeric_std, replace the reference to IEEE.std_logic_arith -in the source code.  This needs to be done consistently in a design -database (e.g. in the PCK_FIO test bench as well). -

-

-

-Methodology notes

-The obvious application for fprint is in test benches, to produce -output files that trace the simulation behavior. -

Another interesting application for fprint is to produce info, -warning and error messages in your models. As it can take arguments, fprint -is much better suited for this task than VHDL's assert or report -statements. Actually fprint produces its own (few) warning messages. -

An advanced usage is the generation of test vectors in a specific format. -Instead of using the fo functions, you can write your own set -of functions that return the symbols of a specific test format in a way -that is understandable to the fprint format specifiers. As an -example, when a high output value should be represented using the symbol -'H' it suffices to write a conversion function that returns "B:H" and call -it in combination with the %b format specifier. -

-

-

-Parametrization

-Prefix and postfix strings for bit-oriented and hex-oriented output are -parameterizable in the packages to accommodate different output styles. -The settings in the distribution are such that hex output is indicated -by the prefix '0x', while  bit output prefix and postfix are empty -strings. -

You can adapt the output style by modifying the following constants -in the package header: -

   -- prefix string for hex output -
  -- VHDL style:    "X""" -
  -- Verilog style: "h'" -
  -- C style:       "0x" -
  constant FIO_h_PRE:  string := "0x"; -

  -- postfix string for hex output -
  -- VHDL style:    """" -
  constant FIO_h_POST: string := ""; -

  -- prefix string for bit vector output -
  -- VHDL style:    "B""" -
  -- Verilog style: "b'" -
  constant FIO_bv_PRE:  string := ""; -

  -- postfix string for bit vector output -
  -- VHDL style:    """" -
  constant FIO_bv_POST: string := ""; -

  -- prefix string for bit output -
  -- VHDL style:    "'" -
  -- Verilog style: "b'" -
  constant FIO_b_PRE:  string := ""; -

  -- postfix string for bit output -
  -- VHDL style:    "'" -
  constant FIO_b_POST: string := ""; -

-

-

-Test bench

-Included in the distribution is a file TB_PCK_FIO.vhd with a test -bench for the PCK_FIO package. The file PCK_FIO.out.gold contains -the expected output. If you run the test bench it should produce the file -PCK_FIO.out -that should be identical to PCK_FIO.out.gold. The source files -should be analyzed in a VHDL library EASICS_PACKAGES. -

A good way to understand fprint is to inspect the test bench -and what it produces. -

-

-

-Known limitations and problems

-This VHDL package is an implementation of a flexible concept. It is likely -to be extended and modified in the future. Backward compatibility is not -guaranteed. Therefore, it is not recommended to give this package the status -of a company-wide standard package (or even worse, a VHDL standard package). -Rather, it should be linked with a particular project (and it can be regarded -as a standard package within that project). -

PCK_FIO is written in standard VHDL Std1076-1987. Nevertheless, some -simulators/versions have problems with the package. The following is an -overview of currently known issues: -
  -

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
SimulatorPCK_FIO handling
Synopsys VSS 3.5 and earlierIncorrect (all zero) output in compiled mode
Synopsys VSS 97.01OK
Mentor quickhdlOK
Modeltech modelsimOK
Cadence LeapfrogShould work with 4.4.1 -
Mysterious problems have been reported - please run the test bench -and report problems
PCK_FIO and various simulators/versions
- -

Although the package name suggests file IO, it only does file output. -

-

-

-Author

-Jan Decaluwe -

-

- - diff --git a/lib/PCK_FIO-1.16/PCK_FIO.out.gold b/lib/PCK_FIO-1.16/PCK_FIO.out.gold deleted file mode 100644 index dcd183e..0000000 --- a/lib/PCK_FIO-1.16/PCK_FIO.out.gold +++ /dev/null @@ -1,206 +0,0 @@ -PCK_FIO.out: TESTBENCH OUTPUT FOR PCK_FIO ------------------------------------------ - -This is the result of running the PCK_FIO testbench. -This file should be compared with PCK_FIO.out.gold, which is -the reference output. Any difference indicates a portability -issue or a simulator non-compliance or bug. - - --------------------- --- Basic features -- --------------------- - --- First some auxiliary declarations -> file RESULT: text is out "PCK_FIO.out"; -> variable L: line; -> variable BoolTrue: boolean := TRUE; -> variable BoolFalse: boolean := FALSE; -> variable IntPos: integer := 5678; -> variable BigIntPos: integer := 12345678; -> variable IntNeg: integer := -8765; -> variable BigIntNeg: integer := -87654321; -> variable Uns: unsigned(6 downto 0) := unsigned'("1010010"); -> variable Unk: unsigned(6 downto 0) := unsigned'("1X10Z10"); -> variable Std: std_logic_vector(6 downto 0) := std_logic_vector'("0010010"); -> variable SigPos: signed(6 downto 0) := signed'("0010010"); -> variable SigNeg: signed(6 downto 0) := signed'("1010010"); -> variable BitX: std_logic := 'X'; -> variable Bit1: std_logic := '1'; -> variable Bit0: std_logic := '0'; - - --- fprint call with no arguments -> fprint(RESULT, L, "No arguments.\n);" -No arguments. - --- Special characters need to be escaped -> fprint(RESULT, L, "Special characters: \% \\ " \n"); -Special characters: % \ " - --- Various format specifiers interprete the same object differently -> fprint(RESULT, L, "Format specifiers: %r %d %b %q\n);" -> fo(Uns), fo(Uns), fo(Uns), fo(Uns) -> ); -Format specifiers: 0x52 82 1010010 U:1010010 - --- Format string can be shortened by using the iteration specifier -> fprint(RESULT, L, "Iteration specifier: %4{%r }\n);" -> fo(Uns), fo(SigPos), fo(SigNeg), fo(Std) -> ); -Iteration specifier: 0x52 0x12 0x52 0x12 - ------------------------------------- --- Support for bit-oriented types -- ------------------------------------- - --- Reasonable format -> fprint(RESULT, L, "Reasonable format: %9{%r }\n", -> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk), -> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) -> ); -Reasonable format: 0x12 0x52 0x12 0x52 0x?? 1 X T F - --- Decimal format -> fprint(RESULT, L, "Decimal format: %7{%d }\n", -> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk), -> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) -> ); -Decimal format: 18 82 18 -46 -1 1 -1 1 0 - --- Bit format -> fprint(RESULT, L, "Bit format: %7{%b }\n", -> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk), -> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) -> ); -Bit format: 0010010 1010010 0010010 1010010 1X10Z10 1 X 1 0 - - --- Alignment --- Template of the call: ( stands for the format specifier) - -> fprint(RESULT, L, "Bitvectors with : %4{|}\n", -> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg) -> ); - --- Results of the call with various format specifiers - -Bitvectors with %1r: 0x52|0x12|0x12|0x52| -Bitvectors with %2r: 0x52|0x12|0x12|0x52| -Bitvectors with %3r: 0x52|0x12|0x12|0x52| -Bitvectors with %4r: 0x52|0x12|0x12|0x52| -Bitvectors with %5r: 0x52| 0x12| 0x12| 0x52| -Bitvectors with %6r: 0x52| 0x12| 0x12| 0x52| -Bitvectors with %7r: 0x52| 0x12| 0x12| 0x52| -Bitvectors with %8r: 0x52| 0x12| 0x12| 0x52| -Bitvectors with %9r: 0x52| 0x12| 0x12| 0x52| - -Bitvectors with %-1r: 0x52|0x12|0x12|0x52| -Bitvectors with %-2r: 0x52|0x12|0x12|0x52| -Bitvectors with %-3r: 0x52|0x12|0x12|0x52| -Bitvectors with %-4r: 0x52|0x12|0x12|0x52| -Bitvectors with %-5r: 0x52 |0x12 |0x12 |0x52 | -Bitvectors with %-6r: 0x52 |0x12 |0x12 |0x52 | -Bitvectors with %-7r: 0x52 |0x12 |0x12 |0x52 | -Bitvectors with %-8r: 0x52 |0x12 |0x12 |0x52 | -Bitvectors with %-9r: 0x52 |0x12 |0x12 |0x52 | - -Bitvectors with %1d: 82|18|18|-46| -Bitvectors with %2d: 82|18|18|-46| -Bitvectors with %3d: 82| 18| 18|-46| -Bitvectors with %4d: 82| 18| 18| -46| -Bitvectors with %5d: 82| 18| 18| -46| -Bitvectors with %6d: 82| 18| 18| -46| -Bitvectors with %7d: 82| 18| 18| -46| -Bitvectors with %8d: 82| 18| 18| -46| -Bitvectors with %9d: 82| 18| 18| -46| - -Bitvectors with %-1d: 82|18|18|-46| -Bitvectors with %-2d: 82|18|18|-46| -Bitvectors with %-3d: 82 |18 |18 |-46| -Bitvectors with %-4d: 82 |18 |18 |-46 | -Bitvectors with %-5d: 82 |18 |18 |-46 | -Bitvectors with %-6d: 82 |18 |18 |-46 | -Bitvectors with %-7d: 82 |18 |18 |-46 | -Bitvectors with %-8d: 82 |18 |18 |-46 | -Bitvectors with %-9d: 82 |18 |18 |-46 | - - -------------------------------- --- Support for integer types -- -------------------------------- - - --- Template of the call: ( stands for the format specifier) - -> fprint(RESULT, L, "Integers with : %4{|}\n", -> fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) -> ); - --- Results of the call with various format specifiers - -Integers with %5d: 5678|-8765|12345678|-87654321| -Integers with %6d: 5678| -8765|12345678|-87654321| -Integers with %7d: 5678| -8765|12345678|-87654321| -Integers with %8d: 5678| -8765|12345678|-87654321| -Integers with %9d: 5678| -8765| 12345678|-87654321| -Integers with %10d: 5678| -8765| 12345678| -87654321| - -Integers with %-5d: 5678 |-8765|12345678|-87654321| -Integers with %-6d: 5678 |-8765 |12345678|-87654321| -Integers with %-7d: 5678 |-8765 |12345678|-87654321| -Integers with %-8d: 5678 |-8765 |12345678|-87654321| -Integers with %-9d: 5678 |-8765 |12345678 |-87654321| -Integers with %-10d: 5678 |-8765 |12345678 |-87654321 | - -Integers with %5r: 5678|-8765| 5678|-4321| -Integers with %6r: 5678|- 8765| 45678|-54321| -Integers with %7r: 5678|- 8765| 345678|-654321| -Integers with %8r: 5678|- 8765| 2345678|-7654321| -Integers with %9r: 5678|- 8765| 12345678|-87654321| -Integers with %10r: 5678|- 8765| 12345678|- 87654321| - -Integers with %-5r: 5678|-8765| 1234|-8765| -Integers with %-6r: 5678 |-8765 | 12345|-87654| -Integers with %-7r: 5678 |-8765 | 123456|-876543| -Integers with %-8r: 5678 |-8765 | 1234567|-8765432| -Integers with %-9r: 5678 |-8765 | 12345678|-87654321| -Integers with %-10r: 5678 |-8765 | 12345678 |-87654321 | - - ----------------------- --- Support for time -- ----------------------- --- For portability reasons, time is converted --- into an integer value (of nanoseconds) -> wait for 648 ns -> fprint (RESULT, L, "The time is now %d ns\n", fo(now)); -The time is now 648 ns - ----------------------------------------- --- Erroneous calls and error messages -- ----------------------------------------- - --- Less arguments than formats specifiers -> fprint(RESULT, L, "%d %d %d %d \n", fo(Uns), fo(Std)); -82 18 -** Warning: FIO_PrintLastValue: Format specifier beyond last argument -** in format string: "%d %d %d %d \n" -** ------^ - --- Unsupported format specifier -> fprint(RESULT, L, "%r %v %r %r\n", fo(Uns), fo(Std), fo(Uns), fo(Std)); -0x52 -** Warning: FIO_PrintArg: Unexpected format specifier 'v' -** in format string: "%r %v %r %r\n" -** ----^ -** Assuming 'q' to proceed: V:0010010 0x52 0x12 - - ----------------------------------------- --- Things you wouldn't expect to work -- ----------------------------------------- - --- Nested iteration -> fprint(RESULT, L, "%3{<<%3{_END_}>>}\n"); -<<_END__END__END_>><<_END__END__END_>><<_END__END__END_>> diff --git a/lib/PCK_FIO-1.16/PCK_FIO.vhd b/lib/PCK_FIO-1.16/PCK_FIO.vhd deleted file mode 100644 index e635721..0000000 --- a/lib/PCK_FIO-1.16/PCK_FIO.vhd +++ /dev/null @@ -1,919 +0,0 @@ ----- File: PCK_FIO.vhd ----- ----- PCK_FIO: a VHDL package for C-style formatted file output ----- Copyright (C) 1995, 1999 Easics NV ----- ----- This program is free software; you can redistribute it and/or modify ----- it under the terms of the GNU General Public License as published by ----- the Free Software Foundation; either version 1, or (at your option) ----- any later version. ----- ----- This program is distributed in the hope that it will be useful, ----- but WITHOUT ANY WARRANTY; without even the implied warranty of ----- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ----- GNU General Public License for more details. ----- ----- You should have received a copy of the GNU General Public License ----- along with this program; if not, write to the Free Software ----- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. ----- ----- For suggestions, bug reports, enhancement requests, and info about ----- our design services, you can contact us at the following address: ----- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium ----- tel.: +32 16 395 600 fax : +32 16 395 619 ----- e-mail: jand@easics.be (Jan Decaluwe) ----- ----- ----- Revision history: ----- ----- $Source: /tmp/cvsroot/VHDL/lib/PCK_FIO-1.16/PCK_FIO.vhd,v $ ----- $Revision: 1.2 $ ----- $Log: not supported by cvs2svn $ ----- Revision 1.1 2008/08/23 08:20:28 Jens ----- Initial import ----- ----- Revision 1.16 1999/04/21 08:28:46 jand ----- Tested with IEEE.numeric_std ----- Small patch for Leapfrog ----- ----- Revision 1.14 1997/07/14 10:16:04 jand ----- prefix/postfix for bits/bitvectors set to empty strings by default ----- ----- Revision 1.13 1997/07/11 17:42:57 jand ----- Corrected Easics address ----- ----- Revision 1.12 1997/07/11 17:38:49 jand ----- Improved prefix/postfix support ----- ----- Revision 1.11 1995/11/15 13:46:02 jand ----- Catched integer'low value in fo for integers ----- ----- Revision 1.10 1995/08/11 16:42:26 jand ----- Reimplemented FIO_FormatExpand as a procedure in an attempt to ----- avoid memory leakage problems in VSS ----- ----- Revision 1.9 1995/08/09 13:47:51 jand ----- Removed array of line trick in fprint for less memory, less ----- CPU time, and more conservatism in general ----- Rearranged FIO_PrintValue call so that fprint remains concise ----- ----- Revision 1.8 1995/08/09 10:32:27 jand ----- Removed fprint_flat to have a single call level ----- Added explicit deallocators of line variables (has strong influence ----- on memory usage in VSS - and possibly CPU time) ----- Redefined 'fo' for type time to make it more portable ----- ----- Revision 1.7 1995/08/07 08:56:04 jand ----- Improved conciseness of fprint argument handling through array of line type ----- ----- Revision 1.6 1995/08/04 18:19:13 jand ----- Increase # arguments from 16 to 32 ----- Corrected bug within fprint 's call to Arg16 ----- Added support for bit format specifier 'b' ----- ----- Revision 1.5 1995/08/02 10:22:37 jand ----- Release 1.1 under GNU ----- ----- Revision 1.4 1995/08/01 11:15:52 jand ----- Added escaping during iteration string read ----- ----- Revision 1.3 1995/08/01 08:23:47 jand ----- Many improvements in robustness, conciseness and coding style ----- ----- Revision 1.2 1995/07/30 16:15:43 jand ----- Improved robustness for release to the world ----- ----- Revision 1.1 1995/07/30 14:21:30 jand ----- Initial revision ----- - -use STD.TEXTIO.all; - -library IEEE; -use IEEE.std_logic_1164.all; --- signed/unsigned definition: use either std_logic_arith or numeric_std -use IEEE.std_logic_arith.all; -- the Synopsys one --- use IEEE.numeric_std.all; - -package PCK_FIO is - - -- prefix string for hex output - -- VHDL style: "X""" - -- Verilog style: "h'" - -- C style: "0x" - constant FIO_h_PRE: string := ""; - - -- postfix string for hex output - -- VHDL style: """" - constant FIO_h_POST: string := ""; - - -- prefix string for bit vector output - -- VHDL style: "B""" - -- Verilog style: "b'" - constant FIO_bv_PRE: string := ""; - - -- postfix string for bit vector output - -- VHDL style: """" - constant FIO_bv_POST: string := ""; - - -- prefix string for bit output - -- VHDL style: "'" - -- Verilog style: "b'" - constant FIO_b_PRE: string := ""; - - -- postfix string for bit output - -- VHDL style: "'" - constant FIO_b_POST: string := ""; - - -- digit width for the string representation of integers - constant FIO_d_WIDTH: integer := 10; - - -- bit width for the string representation of integers - constant FIO_b_WIDTH: integer := 32; - - -- definition of the NIL string (default value for fprint arguments) - -- fprint stops consuming arguments at the first NIL argument - constant FIO_NIL: string := "\"; - - procedure fprint - (F: out text; - L: inout line; - Format: in string; - A1 , A2 , A3 , A4 , A5 , A6 , A7 , A8 : in string := FIO_NIL; - A9 , A10, A11, A12, A13, A14, A15, A16: in string := FIO_NIL; - A17, A18, A19, A20, A21, A22, A23, A24: in string := FIO_NIL; - A25, A26, A27, A28, A29, A30, A31, A32: in string := FIO_NIL - ); - - function fo (Arg: unsigned) return string; - function fo (Arg: signed) return string; - function fo (Arg: std_logic_vector) return string; - function fo (Arg: std_ulogic_vector) return string; - function fo (Arg: bit_vector) return string; - function fo (Arg: integer) return string; - function fo (Arg: std_ulogic) return string; - function fo (Arg: bit) return string; - function fo (Arg: boolean) return string; - function fo (Arg: character) return string; - function fo (Arg: string) return string; - function fo (Arg: time) return string; - - procedure FIO_FormatExpand (FMT: inout line; - Format: in string; - StartPointer: in positive); - -end PCK_FIO; - - -package body PCK_FIO is - - - -------------------------- - -- FIO Warnings support -- - -------------------------- - - procedure FIO_Warning_Fsbla (F: out text; - L: inout line; - Format: in string; - Pointer: in positive) is - begin - fprint (F, L, "\n** Warning: FIO_PrintLastValue: " & - "Format specifier beyond last argument\n"); - fprint (F, L, "** in format string: ""%s""\n", Format); - fprint (F, L, "** "); - for i in 1 to Pointer-1 loop - fprint (F, L, "-"); - end loop; - fprint (F, L, "^\n"); - end FIO_Warning_Fsbla; - - procedure FIO_Warning_Ufs (F: out text; - L: inout line; - Format: in string; - Pointer: in positive; - Char: in character) is - begin - fprint (F, L, "\n** Warning: FIO_PrintArg: " & - "Unexpected format specifier '%r'\n", - fo(Char)); - fprint (F, L, "** in format string: ""%s""\n", Format) ; - fprint (F, L, "** "); - for i in 1 to Pointer-1 loop - fprint (F, L, "-"); - end loop; - fprint (F, L, "^\n** Assuming 'q' to proceed: "); - end FIO_Warning_Ufs; - - - ---------------------------------- - -- bit conversion support -- - ---------------------------------- - - type T_bit_map is array(bit) of character; - - constant C_BIT_MAP: T_bit_map - := ('0', '1'); - - ---------------------------------- - -- std_logic conversion support -- - ---------------------------------- - - type T_std_logic_map is array(std_ulogic) of character; - - constant C_STD_LOGIC_MAP: T_std_logic_map - := ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-'); - - ------------------------------ - -- Digit conversion support -- - ------------------------------ - - -- types & constants - - subtype S_digit_chars is character range '0' to '9'; - subtype S_digits is integer range 0 to 9 ; - - type T_digit_chars_map is array(S_digit_chars) of S_digits; - - constant C_DIGIT_CHARS_MAP: T_digit_chars_map - := (0, 1, 2, 3, 4, 5, 6, 7, 8, 9); - - type T_digits_map is array(S_digits) of S_digit_chars; - - constant C_DIGITS_MAP: T_digits_map - := ('0', '1', '2', '3', '4', '5', '6', '7', '8', '9'); - - - -------------------------------- - -- Decimal conversion support -- - -------------------------------- - - function U_To_d (Arg: string) return integer is - constant Argument: string(Arg'length downto 1) := Arg; - variable Result: integer := 0; - begin - for i in Argument'range loop - case Argument(i) is when '1' => Result := 2**(i-1) + Result; - when '0' => null; - when others => return(-1); - end case; - end loop; - return (Result); - end U_To_d; - - function S_To_d (Arg: string) return integer is - constant Argument: string(Arg'length downto 1) := Arg; - variable Result: integer := 0; - begin - case Argument(Argument'left) is - when '1' => Result := - 2**(Argument'left-1); - when '0' => Result := 0; - when others => return (integer'low); - end case; - for i in Argument'left-1 downto 1 loop - case Argument(i) is when '1' => Result := 2**(i-1) + Result; - when '0' => null; - when others => return(integer'low); - end case; - end loop; - return (Result); - end S_To_d; - - function I_To_d (Arg: string(1 to FIO_d_WIDTH+1)) return integer is - constant Sign: character := Arg(1); - constant Value: string(Arg'length-1 downto 1) := Arg(2 to Arg'length); - variable Char: character; - variable Result: integer := 0; - begin - Result := 0; - for i in Value'range loop - Result := Result * 10; - Char := Value(i); - if (Char /= ' ') then - Result := Result + C_DIGIT_CHARS_MAP(Char); - end if; - end loop; - case Sign is when '-' => return(-Result); - when others => return(Result); - end case; - end I_To_d; - - function B_To_d (Arg: string(1 to 1)) return integer is - begin - case Arg is when "1" => return(1); - when "0" => return(0); - when others => return(-1); - end case; - end B_To_d; - - function L_To_d (Arg: string(1 to 1)) return integer is - begin - case Arg is when "T" => return(1); - when others => return(0); - end case; - end L_To_d; - - - - ---------------------------- - -- Hex conversion support -- - ---------------------------- - - -- Constants & types - - constant C_HEX_CHARS: string(1 to 17) := "0123456789ABCDEF?"; - - -- Function to return Hex index of a nibble - - function U_To_h_Index(Arg: string(4 downto 1)) return integer is - variable Index: integer := 0; - begin - for i in Arg'range loop - case Arg(i) is when '1' => Index := 2**(i-1) + Index; - when '0' => null; - when others => return (17); - end case; - end loop; - return (Index+1); - end U_To_h_Index; - - -- Hex conversion - - function U_To_h (Arg: string) return string is - variable Result: string((Arg'length-1)/4 +1 downto 1); - variable ExtArg: string(Result'length*4 downto 1) := (others => '0'); - begin - ExtArg(Arg'length downto 1) := Arg; - for i in Result'range loop - Result(i) := C_HEX_CHARS(U_To_h_Index( ExtArg(i*4 downto i*4 -3) )); - end loop; - return (FIO_h_PRE & Result & FIO_h_POST); - end U_To_h; - - - - ---------------------------- - -- Bit conversion support -- - ---------------------------- - - function L_To_b (Arg: string(1 to 1)) return string is - variable Result: string(1 to 1); - begin - case Arg is when "T" => Result := "1"; - when others => Result := "0"; - end case; - return(FIO_b_PRE & Result & FIO_b_POST); - end L_To_b; - - - function I_To_b (Arg: string(1 to FIO_d_WIDTH+1); - Justified: side; - Width: integer) return string is - - variable IntValue: integer := I_To_d(Arg); - variable BitValue: string(1 to FIO_b_WIDTH) := (others => ' '); - variable Sign: character := ' '; - constant Blanks: string(1 to FIO_b_WIDTH) := (others => ' '); - variable BitWidth: integer range 0 to FIO_b_WIDTH; - variable MsPos: integer range 1 to BitValue'length; - variable BitValueExtended: string(1 to 2*FIO_b_WIDTH); - - begin - - if (IntValue < 0) then - Sign := '-'; - IntValue := -IntValue; - end if; - - for i in BitValue'reverse_range loop - BitValue(i) := C_DIGITS_MAP(IntValue mod 2); - IntValue := IntValue / 2; - exit when (IntValue = 0); - end loop; - - BitValueExtended := BitValue & Blanks; - - if (Width = 0) or (Width > FIO_b_WIDTH+1) then - BitWidth := FIO_b_WIDTH; - else - BitWidth := Width-1; - end if; - - if (Justified = RIGHT) then - return (FIO_bv_PRE & - Sign & BitValue(BitValue'length-BitWidth+1 to BitValue'length) & - FIO_bv_POST); - else - for i in BitValue'range loop - if BitValue(i) /= ' ' then - MSPos := i; - exit; - end if; - end loop; - return (FIO_bv_PRE & - Sign & BitValueExtended(MSPos to MSPos+BitWidth-1) & - FIO_bv_POST); - end if; - - end I_To_b; - - - ----------------------------------- - -- Reasonable conversion support -- - ----------------------------------- - - function I_To_r (Arg: string(1 to FIO_d_WIDTH+1); - Justified: side; - Width: integer) return string is - constant Value: string(1 to FIO_d_WIDTH) := Arg(2 to FIO_d_WIDTH+1); - constant Sign: character := Arg(1); - constant Blanks: string(1 to FIO_d_WIDTH) := (others => ' '); - variable IntWidth: integer range 0 to FIO_d_WIDTH; - variable MsPos: integer range 1 to Value'length; - variable ValueExtended: string(1 to 2*FIO_d_WIDTH) := Value & Blanks; - begin - if (Width = 0) or (Width > FIO_d_WIDTH+1) then - IntWidth := FIO_d_WIDTH; - else - IntWidth := Width-1; - end if; - if (Justified = RIGHT) then - return (Sign & Value(Value'length-IntWidth+1 to Value'length)); - else - for i in Value'range loop - if Value(i) /= ' ' then - MSPos := i; - exit; - end if; - end loop; - return (Sign & ValueExtended(MSPos to MSPos+IntWidth-1)); - end if; - end I_To_r; - - - ------------------------------------------- - -- Reasonable output conversion function -- - ------------------------------------------- - - function ReasonableOutput (Arg: string; - Justified: side; - Width: integer) return string is - constant Argument: string(1 to Arg'length) := Arg; - constant TypeSpec: string (1 to 2) := Argument(1 to 2); - constant Value: string(1 to Arg'length-2) := Argument(3 to Arg'length); - begin - case TypeSpec is - when "U:" | "S:" | "V:" => - return U_To_h(Value); - when "I:" => - return I_To_r(Value, Justified, Width); - when "B:" | "L:" | "C:" => - return Value; - when others => - return Argument; - end case; - - end ReasonableOutput; - - - ------------------------------------ - -- Bit output conversion function -- - ------------------------------------ - - function BitOutput (Arg: string; - Justified: side; - Width: integer) return string is - constant Argument: string(1 to Arg'length) := Arg; - constant TypeSpec: string (1 to 2) := Argument(1 to 2); - constant Value: string(1 to Arg'length-2) := Argument(3 to Arg'length); - begin - case TypeSpec is - when "U:" | "S:" | "V:" => - return (FIO_bv_PRE & Value & FIO_bv_POST); - when "B:" => - -- Value(1 to 1) instead of Value for LeapFrog - return (FIO_b_PRE & Value(1 to 1) & FIO_b_POST); - when "I:" => - return I_To_b(Value, Justified, Width); - when "L:" => - -- Value(1 to 1) instead of Value for LeapFrog - return L_To_b(Value(1 to 1)); - when others => - return Argument; - end case; - - end BitOutput; - - - ------------------------------------------- - -- Decimal output conversion function -- - ------------------------------------------- - - function DecimalOutput (Arg: string) return integer is - constant Argument: string(1 to Arg'length) := Arg; - constant TypeSpec: string (1 to 2) := Argument(1 to 2); - constant Value: string(1 to Arg'length-2) := Argument(3 to Arg'length); - begin - case TypeSpec is - when "U:"| "V:" => - return U_To_d(Value); - when "S:" => - return S_To_d(Value); - when "I:" => - return I_To_d(Value); - when "B:" => - return B_To_d(Value); - when "L:" => - return L_To_d(Value); - when others => - return integer'low; - end case; - - end DecimalOutput; - - - ---------------------------- - -- Atomic print functions -- - ---------------------------- - - function FIO_EOS (Format: in string; - Pointer: in integer) - return boolean is - begin - return (Pointer > Format'length); - end FIO_EOS; - - - -- Atomic value print function - - procedure FIO_PrintValue (F: out text; - L: inout line; - Format: in string; - Pointer: inout integer; - Last: in boolean := FALSE) is - variable Char: character; - begin - while (not FIO_EOS(Format, Pointer)) loop - Char := Format(Pointer); - case Char is - when '\' => - Pointer := Pointer + 1; - exit when (FIO_EOS(Format, Pointer)); - Char := Format(Pointer); - case Char is when 'n' => writeline(F, L); - when others => write(L, Char); - end case; - when '%' => - if Last then - FIO_Warning_Fsbla(F, L, Format, Pointer); - end if; - Pointer := Pointer + 1; - exit; - when others => - write(L, char); - end case; - Pointer := Pointer + 1; - end loop; - end FIO_PrintValue; - - - ---- Atomic argument print function - - procedure FIO_PrintArg (F: out text; - L: inout line; - Format: in string; - Pointer: inout integer; - Arg: in string) is - variable Char: character; - variable Justified: side; - variable Width: integer; - begin - - FIO_PrintValue(F, L, Format, Pointer); - - Justified := RIGHT; - Width := 0; - while (not FIO_EOS(Format, Pointer)) loop - Char := Format(Pointer); - case Char is - when '-' => - Justified := LEFT; - Pointer := Pointer + 1; - when '0' to '9' => - Width := Width*10 + C_DIGIT_CHARS_MAP(Char); - Pointer := Pointer + 1; - when 'r' => - write(L, ReasonableOutput(Arg, Justified, Width), Justified, Width); - Pointer := Pointer + 1; - exit; - when 'b' => - write(L, BitOutput(Arg, Justified, Width), Justified, Width); - Pointer := Pointer + 1; - exit; - when 'd' => - write(L, DecimalOutput(Arg), Justified, Width); - Pointer := Pointer + 1; - exit; - when 'q' | 's' => - write(L, Arg, Justified, Width); - Pointer := Pointer + 1; - exit; - when others => - FIO_Warning_Ufs(F, L, Format, Pointer, Char); - write(L, Arg, Justified, Width); - Pointer := Pointer + 1; - exit; - end case; - end loop; - end FIO_PrintArg; - - - ----------------------------------------------------- - -- The format string iteration expansion procedure -- - ----------------------------------------------------- - - procedure FIO_FormatExpand (FMT: inout line; - Format: in string; - StartPointer: in positive) is - - variable Pointer: positive := StartPointer; - variable TokenStart: positive; - variable IterStringStart: positive; - variable IterStringEnd: positive; - variable IterCount: natural; - variable OpenBrackets: natural; - variable L: line; - - begin - - FORMAT_SEARCH: while not FIO_EOS(Format, Pointer) loop - - case Format(Pointer) is - - -- look for format specifier - when '%' => - - -- initialize iteration token search - TokenStart := Pointer; - IterCount := 0; - Pointer := Pointer + 1; - - -- start iteration token search - TOKEN_READ: while not FIO_EOS(Format, Pointer) loop - - case Format(Pointer) is - - -- read iteration counter - when '0' to '9' => - IterCount := IterCount*10 + C_DIGIT_CHARS_MAP(Format(Pointer)); - Pointer := Pointer + 1; - - -- expect open bracket - when '{' => - - -- initialize iteration string read - OpenBrackets := 1; - IterStringStart := Pointer + 1; - Pointer := Pointer + 1; - -- quit prematurely when iteration count is 0 - next FORMAT_SEARCH when (IterCount = 0); - - -- start iteration string read - ITER_STRING_READ: while not FIO_EOS(Format, Pointer) loop - - case Format(Pointer) is - -- keep track of open brackets - when '{' => - OpenBrackets := OpenBrackets + 1; - Pointer := Pointer + 1; - -- when closing bracket is found, process iteration string - when '}' => - OpenBrackets := OpenBrackets - 1; - if (OpenBrackets = 0) then - IterStringEnd := Pointer-1; - if (TokenStart /= 1) then - write(L, Format(1 to TokenStart-1)); - end if; - for i in 1 to IterCount loop - write(L, Format(IterStringStart to IterStringEnd)); - end loop; - if (IterStringEnd /= Format'length) then - write(L, Format(IterStringEnd+2 to Format'length)); - end if; - -- call expansion procedure recursively on expanded format - FIO_FormatExpand(FMT, L.all, TokenStart); - deallocate(L); - return; - end if; - Pointer := Pointer + 1; - -- skip escaped characters - when '\' => - Pointer := Pointer + 2; - -- read iteration string - when others => - Pointer := Pointer + 1; - - end case; - - end loop ITER_STRING_READ; - - -- stop iteration token search when no opening bracket found - when others => - Pointer := Pointer + 1; - next FORMAT_SEARCH; - - end case; - - end loop TOKEN_READ; - - -- skip escaped characters - when '\' => - Pointer := Pointer + 2; - - -- read other characters - when others => - Pointer := Pointer + 1; - - end case; - - end loop FORMAT_SEARCH; - - write(FMT, Format); - deallocate(L); - - end FIO_FormatExpand; - - - - -------------------------- - -- The fprint procedure -- - -------------------------- - - procedure fprint - (F: out text; - L: inout line; - Format: in string; - A1 , A2 , A3 , A4 , A5 , A6 , A7 , A8 : in string := FIO_NIL; - A9 , A10, A11, A12, A13, A14, A15, A16: in string := FIO_NIL; - A17, A18, A19, A20, A21, A22, A23, A24: in string := FIO_NIL; - A25, A26, A27, A28, A29, A30, A31, A32: in string := FIO_NIL - ) is - - variable Pointer: integer; - variable FMT: line; - - begin - - Pointer := 1; - - FIO_FormatExpand (FMT, Format, Format'low); - - if (A1 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A1 ); - if (A2 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A2 ); - if (A3 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A3 ); - if (A4 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A4 ); - if (A5 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A5 ); - if (A6 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A6 ); - if (A7 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A7 ); - if (A8 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A8 ); - if (A9 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A9 ); - if (A10 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A10); - if (A11 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A11); - if (A12 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A12); - if (A13 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A13); - if (A14 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A14); - if (A15 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A15); - if (A16 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A16); - if (A17 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A17); - if (A18 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A18); - if (A19 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A19); - if (A20 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A20); - if (A21 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A21); - if (A22 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A22); - if (A23 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A23); - if (A24 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A24); - if (A25 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A25); - if (A26 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A26); - if (A27 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A27); - if (A28 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A28); - if (A29 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A29); - if (A30 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A30); - if (A31 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A31); - if (A32 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A32); - end if; end if; end if; end if; end if; end if; end if; end if; - end if; end if; end if; end if; end if; end if; end if; end if; - end if; end if; end if; end if; end if; end if; end if; end if; - end if; end if; end if; end if; end if; end if; end if; end if; - - FIO_PrintValue(F, L, FMT.all, Pointer, Last => TRUE); - - deallocate(FMT); - - end fprint; - - - ------------------------------------------- - -- Formatted output conversion functions -- - ------------------------------------------- - - function fo (Arg: unsigned) return string is - constant Argument: unsigned(1 to Arg'length) := Arg; - variable Result: string(1 to Arg'length); - begin - for i in Argument'range loop - Result(i) := C_STD_LOGIC_MAP(Argument(i)); - end loop; - return ("U:" & Result); - end fo; - - function fo (Arg: signed) return string is - constant Argument: signed(1 to Arg'length) := Arg; - variable Result: string(1 to Arg'length); - begin - for i in Argument'range loop - Result(i) := C_STD_LOGIC_MAP(Argument(i)); - end loop; - return ("S:" & Result); - end fo; - - function fo (Arg: std_logic_vector) return string is - constant Argument: std_logic_vector(1 to Arg'length) := Arg; - variable Result: string(1 to Arg'length); - begin - for i in Argument'range loop - Result(i) := C_STD_LOGIC_MAP(Argument(i)); - end loop; - return ("V:" & Result); - end fo; - - function fo (Arg: std_ulogic_vector) return string is - constant Argument: std_ulogic_vector(1 to Arg'length) := Arg; - variable Result: string(1 to Arg'length); - begin - for i in Argument'range loop - Result(i) := C_STD_LOGIC_MAP(Argument(i)); - end loop; - return ("V:" & Result); - end fo; - - function fo (Arg: bit_vector) return string is - constant Argument: bit_vector(1 to Arg'length) := Arg; - variable Result: string(1 to Arg'length); - begin - for i in Argument'range loop - Result(i) := C_BIT_MAP(Argument(i)); - end loop; - return ("V:" & Result); - end fo; - - function fo (Arg: integer) return string is - variable Argument: integer := Arg; - variable Result: string(1 to FIO_d_WIDTH) := (others => ' '); - variable Sign: character := ' '; - begin - if (Argument < 0) and (Argument /= integer'low) then - Sign := '-'; - Argument := -Argument; - end if; - for i in Result'reverse_range loop - Result(i) := C_DIGITS_MAP(Argument mod 10); - Argument := Argument / 10; - exit when (Argument = 0); - end loop; - return ("I:" & Sign & Result); - end fo; - - function fo (Arg: std_ulogic) return string is - begin - return ("B:" & C_STD_LOGIC_MAP(Arg)); - end fo; - - function fo (Arg: bit) return string is - begin - return ("B:" & C_BIT_MAP(Arg)); - end fo; - - function fo (Arg: boolean) return string is - begin - if (ARG = TRUE) then - return ("L:T"); - else - return ("L:F"); - end if; - end fo; - - function fo (Arg: character) return string is - begin - return ("C:" & Arg); - end fo; - - function fo (Arg: string) return string is - begin - return Arg; - end fo; - - function fo (Arg: time) return string is - begin - return fo (integer (Arg / 1 ns)); - end fo; - -end PCK_FIO; diff --git a/lib/PCK_FIO-1.16/README b/lib/PCK_FIO-1.16/README deleted file mode 100644 index 4af4c99..0000000 --- a/lib/PCK_FIO-1.16/README +++ /dev/null @@ -1,72 +0,0 @@ -# $Id: README,v 1.1 2008-08-23 08:20:28 Jens Exp $ -# $Log: not supported by cvs2svn $ -# Revision 1.3 1999/04/21 08:08:35 jand -# Tested with IEEE.numeric_std -# Small patch for Leapfrog -# -# - - PCK_FIO, Version 1.16 - Copyright (C) 1995, 1999 Easics NV - ----- PCK_FIO: a VHDL package for C-style formatted file output ----- Copyright (C) 1995, 1999 Easics NV ----- ----- This program is free software; you can redistribute it and/or modify ----- it under the terms of the GNU General Public License as published by ----- the Free Software Foundation; either version 1, or (at your option) ----- any later version. ----- ----- This program is distributed in the hope that it will be useful, ----- but WITHOUT ANY WARRANTY; without even the implied warranty of ----- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ----- GNU General Public License for more details. ----- ----- You should have received a copy of the GNU General Public License ----- along with this program; if not, write to the Free Software ----- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. ----- ----- For suggestions, bug reports, enhancement requests, and info about ----- our design services, you can contact us at the following address: ----- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium ----- tel.: +32 16 395 600 fax : +32 16 395 619 ----- e-mail: jand@easics.be (Jan Decaluwe) ----- - -Contents --------- - -This distribution contains the following files: - - PCK_FIO.vhd: VHDL source of the PCK_FIO package - TB_PCK_FIO.vhd: VHDL source of the testbench for package PCK_FIO - PCK_FIO.out.gold: Certified test bench output - PCK_FIO.html: Manual for PCK_FIO in html format - README: This file - - -Installation ------------- - -To install PCK_FIO, define a VHDL library called EASICS_PACKAGES, and -analyze the VHDL file PCK_FIO.vhd into this library. - -To install the test bench, analyze TB_PCK_FIO.vhd into the same library. - -If you want to use IEEE.numeric_std instead of IEEE.std_logic_arith, you need -to edit the source code of the package and the test bench and replace the -package use clause. PCK_FIO works with either of these packages. - -To install the documentation, point your web browser to the file PCK_FIO.html -and bookmark it. - - -Installation check ------------------- - -After installing the test bench, you should run it. The corresponding VHDL -design unit is EASICS_PACKAGES.TBE_PCK_FIO(TB). - -Simulating the test bench should create a file called PCK_FIO.out. This file -should be identical to PCK_FIO.out.gold. Any difference indicates a portability -issue or a simulator non-compliance or bug. diff --git a/lib/PCK_FIO-1.16/TB_PCK_FIO.vhd b/lib/PCK_FIO-1.16/TB_PCK_FIO.vhd deleted file mode 100644 index c64d045..0000000 --- a/lib/PCK_FIO-1.16/TB_PCK_FIO.vhd +++ /dev/null @@ -1,504 +0,0 @@ ----- File: TB_PCK_FIO.vhd ----- ----- TBC_PCK_FIO: a test bench for the PCK_FIO package. ----- Copyright (C) 1995, 1999 Easics NV ----- ----- This program is free software; you can redistribute it and/or modify ----- it under the terms of the GNU General Public License as published by ----- the Free Software Foundation; either version 1, or (at your option) ----- any later version. ----- ----- This program is distributed in the hope that it will be useful, ----- but WITHOUT ANY WARRANTY; without even the implied warranty of ----- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ----- GNU General Public License for more details. ----- ----- You should have received a copy of the GNU General Public License ----- along with this program; if not, write to the Free Software ----- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. ----- ----- For suggestions, bug reports, enhancement requests, and info about ----- our design services, you can contact us at the following address: ----- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium ----- tel.: +32 16 395 600 fax : +32 16 396 619 ----- e-mail: jand@easics.be (Jan Decaluwe) ----- ----- ----- $Source: /tmp/cvsroot/VHDL/lib/PCK_FIO-1.16/TB_PCK_FIO.vhd,v $ ----- $Revision: 1.1 $ ----- $Log: not supported by cvs2svn $ ----- Revision 1.7 1999/04/21 08:23:53 jand ----- Tested with IEEE.numeric_std ----- Small patch for Leapfrog ----- ----- Revision 1.3 1998/09/29 10:09:44 vhdl ----- to EASICS_PACKAGES ----- ----- Revision 1.2 1998/09/29 09:17:51 vhdl ----- library EASICS_PACKAGES; ----- ----- Revision 1.1 1998/09/29 09:15:44 vhdl ----- Initial revision ----- - - -library IEEE; -use IEEE.std_logic_1164.all; --- signed/unsigned definition: use either std_logic_arith or numeric_std -use IEEE.std_logic_arith.all; -- the Synopsys one --- use IEEE.numeric_std.all; - -use STD.TEXTIO.all; - -library EASICS_PACKAGES; -use EASICS_PACKAGES.PCK_FIO.all; - -entity TBE_PCK_FIO is - -end TBE_PCK_FIO; - -architecture TB of TBE_PCK_FIO is - -begin - -USAGE: process - - file RESULT: text is out "PCK_FIO.out"; - variable L: line; - variable Pointer: integer; - variable BoolTrue: boolean := TRUE; - variable BoolFalse: boolean := FALSE; - variable IntPos: integer := 5678; - variable BigIntPos: integer := 12345678; - variable IntNeg: integer := -8765; - variable BigIntNeg: integer := -87654321; - variable Uns: unsigned(6 downto 0) := unsigned'("1010010"); - variable Unk: unsigned(6 downto 0) := unsigned'("1X10Z10"); - variable Std: std_logic_vector(6 downto 0) := std_logic_vector'("0010010"); - variable SigPos: signed(6 downto 0) := signed'("0010010"); - variable SigNeg: signed(6 downto 0) := signed'("1010010"); - variable BitX: std_logic := 'X'; - variable Bit1: std_logic := '1'; - variable Bit0: std_logic := '0'; - - variable parameter_1: integer := 1234; - variable parameter_2: integer := 2345; - variable parameter_3: integer := 4567; - - -begin - -fprint(RESULT, L, - "PCK_FIO.out: TESTBENCH OUTPUT FOR PCK_FIO\n" & - "-----------------------------------------\n\n" & - "This is the result of running the PCK_FIO testbench.\n" & - "This file should be compared with PCK_FIO.out.gold, which is\n" & - "the reference output. Any difference indicates a portability\n" & - "issue or a simulator non-compliance or bug.\n\n" - ); - - -fprint(RESULT, L, - "\n--------------------\n" & - "-- Basic features --\n" & - "--------------------\n\n" - ); - -fprint(RESULT, L, - "-- First some auxiliary declarations\n" - ); - -fprint(RESULT, L, - "> file RESULT: text is out ""PCK_FIO.out"";\n" & - "> variable L: line;\n" & - "> variable BoolTrue: boolean := TRUE;\n" & - "> variable BoolFalse: boolean := FALSE;\n" & - "> variable IntPos: integer := 5678;\n" & - "> variable BigIntPos: integer := 12345678;\n" & - "> variable IntNeg: integer := -8765;\n" & - "> variable BigIntNeg: integer := -87654321;\n" & - "> variable Uns: unsigned(6 downto 0) := unsigned'(""1010010"");\n" & - "> variable Unk: unsigned(6 downto 0) := unsigned'(""1X10Z10"");\n" & - "> variable Std: std_logic_vector(6 downto 0) := std_logic_vector'(""0010010"");\n" & - "> variable SigPos: signed(6 downto 0) := signed'(""0010010"");\n" & - "> variable SigNeg: signed(6 downto 0) := signed'(""1010010"");\n" & - "> variable BitX: std_logic := 'X';\n" & - "> variable Bit1: std_logic := '1';\n" & - "> variable Bit0: std_logic := '0';\n" -); - - -fprint(RESULT, L, - "\n\n-- fprint call with no arguments\n" & - "> fprint(RESULT, L, ""No arguments.\\n);""\n" - ); -fprint(RESULT, L, "No arguments.\n"); - - -fprint(RESULT, L, - "\n-- Special characters need to be escaped\n" & - "> fprint(RESULT, L, ""Special characters: \\\% \\\\ "" \\n"");\n" - ); - -fprint(RESULT, L, "Special characters: \% \\ "" \n"); - - -fprint(RESULT, L, - "\n-- Various format specifiers interprete the same object differently\n" & - "> fprint(RESULT, L, ""Format specifiers: \%r \%d \%b \%q\\n);""\n" & - "> fo(Uns), fo(Uns), fo(Uns), fo(Uns)\n" & - "> );\n" - ); - -fprint(RESULT, L, "Format specifiers: %r %d %b %q\n", - fo(Uns), fo(Uns), fo(Uns), fo(Uns) - ); - -fprint(RESULT, L, - "\n-- Format string can be shortened by using the iteration specifier\n" & - "> fprint(RESULT, L, ""Iteration specifier: \%4{\%r }\\n);""\n" & - "> fo(Uns), fo(SigPos), fo(SigNeg), fo(Std)\n" & - "> );\n" - ); - -fprint(RESULT, L, "Iteration specifier: %4{%r }\n", - fo(Uns), fo(SigPos), fo(SigNeg), fo(Std) - ); - - -fprint(RESULT, L, - "\n------------------------------------\n" & - "-- Support for bit-oriented types --\n" & - "------------------------------------\n" - ); - -fprint (RESULT, L, "\n-- Reasonable format\n" & - "> fprint(RESULT, L, ""Reasonable format: \%9{\%r }\\n"",\n" & - "> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),\n" & - "> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) \n" & - "> );\n" - ); - - -fprint(RESULT, L, "Reasonable format: %9{%r }\n", - fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk), - fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) - ); - -fprint (RESULT, L, "\n-- Decimal format\n" & - "> fprint(RESULT, L, ""Decimal format: \%7{\%d }\\n"",\n" & - "> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),\n" & - "> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) \n" & - "> );\n" - ); - - -fprint(RESULT, L, "Decimal format: %9{%d }\n", - fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk), - fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) - ); - -fprint (RESULT, L, "\n-- Bit format\n" & - "> fprint(RESULT, L, ""Bit format: \%7{\%b }\\n"",\n" & - "> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),\n" & - "> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) \n" & - "> );\n" - ); - - -fprint(RESULT, L, "Bit format: %9{%b }\n", - fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk), - fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) - ); - -fprint(RESULT, L, - "\n\n" & - "-- Alignment\n-- Template of the call: ( stands for the format specifier)\n" - ); - - -fprint(RESULT, L, "\n" & - "> fprint(RESULT, L, ""Bitvectors with : \%4{|}\\n"",\n" & - "> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg)\n" & - - "> );\n" - ); - -fprint(RESULT, L, - "\n" & - "-- Results of the call with various format specifiers\n\n" - ); - -fprint(RESULT, L, "Bitvectors with \%1r: %4{%1r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%2r: %4{%2r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%3r: %4{%3r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%4r: %4{%4r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%5r: %4{%5r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%6r: %4{%6r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%7r: %4{%7r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%8r: %4{%8r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%9r: %4{%9r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "\n"); -fprint(RESULT, L, "Bitvectors with \%-1r: %4{%-1r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-2r: %4{%-2r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-3r: %4{%-3r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-4r: %4{%-4r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-5r: %4{%-5r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-6r: %4{%-6r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-7r: %4{%-7r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-8r: %4{%-8r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-9r: %4{%-9r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "\n"); -fprint(RESULT, L, "Bitvectors with \%1d: %4{%1d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%2d: %4{%2d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%3d: %4{%3d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%4d: %4{%4d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%5d: %4{%5d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%6d: %4{%6d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%7d: %4{%7d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%8d: %4{%8d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%9d: %4{%9d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "\n"); -fprint(RESULT, L, "Bitvectors with \%-1d: %4{%-1d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-2d: %4{%-2d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-3d: %4{%-3d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-4d: %4{%-4d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-5d: %4{%-5d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-6d: %4{%-6d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-7d: %4{%-7d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-8d: %4{%-8d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-9d: %4{%-9d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "\n"); - - - -fprint(RESULT, L, - "\n-------------------------------\n" & - "-- Support for integer types --\n" & - "-------------------------------\n" - ); - -fprint(RESULT, L, - "\n\n" & - "-- Template of the call: ( stands for the format specifier)\n" - ); - - -fprint(RESULT, L, "\n" & - "> fprint(RESULT, L, ""Integers with : \%4{|}\\n"",\n" & - "> fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)\n" & - - "> );\n" - ); - -fprint(RESULT, L, - "\n" & - "-- Results of the call with various format specifiers\n\n" - ); - - -fprint(RESULT, L, "Integers with \%5d: %4{%5d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%6d: %4{%6d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%7d: %4{%7d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%8d: %4{%8d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%9d: %4{%9d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%10d: %4{%10d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "\n"); -fprint(RESULT, L, "Integers with \%-5d: %4{%-5d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-6d: %4{%-6d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-7d: %4{%-7d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-8d: %4{%-8d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-9d: %4{%-9d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-10d: %4{%-10d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "\n"); -fprint(RESULT, L, "Integers with \%5r: %4{%5r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%6r: %4{%6r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%7r: %4{%7r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%8r: %4{%8r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%9r: %4{%9r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%10r: %4{%10r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "\n"); -fprint(RESULT, L, "Integers with \%-5r: %4{%-5r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-6r: %4{%-6r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-7r: %4{%-7r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-8r: %4{%-8r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-9r: %4{%-9r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-10r: %4{%-10r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "\n"); - - -fprint(RESULT, L, - "\n----------------------\n" & - "-- Support for time --\n" & - "----------------------\n" - ); - -fprint (RESULT, L, "-- For portability reasons, time is converted \n" & - "-- into an integer value (of nanoseconds)\n" - ); -fprint (RESULT, L, "> wait for 648 ns\n"); -fprint (RESULT, L, "> fprint (RESULT, L, ""The time is now \%d ns\\n"", fo(now));\n"); - -wait for 648 ns; - -fprint (RESULT, L, "The time is now %d ns\n", fo(now)); - - -fprint(RESULT, L, - "\n----------------------------------------\n" & - "-- Erroneous calls and error messages --\n" & - "----------------------------------------\n" - ); - -fprint(RESULT, L, "\n-- Less arguments than formats specifiers\n" & - "> fprint(RESULT, L, ""\%d \%d \%d \%d \\n"", fo(Uns), fo(Std));\n" - ); - -fprint(RESULT, L, "%d %d %d %d \n", fo(Uns), fo(Std)); - -fprint(RESULT, L, "\n"); - -fprint(RESULT, L, "-- Unsupported format specifier\n" & - "> fprint(RESULT, L, ""\%r \%v \%r \%r\\n"", " & - "fo(Uns), fo(Std), fo(Uns), fo(Std));\n" - ); - -fprint(RESULT, L, "%r %v %r %r\n", fo(Uns), fo(Std), fo(Uns), fo(Std)); - -fprint(RESULT, L, "\n"); - -fprint(RESULT, L, - "\n----------------------------------------\n" & - "-- Things you wouldn't expect to work --\n" & - "----------------------------------------\n" - ); - -fprint(RESULT, L, "\n-- Nested iteration\n"); -fprint(RESULT, L, "> fprint(RESULT, L, ""\%3{<<\%3{_END_}>>}\\n"");\n"); -fprint(RESULT, L, "%3{<<%3{_END_}>>}\n"); - -wait; - -end process USAGE; - -end TB; diff --git a/lib/PCK_FIO-2002.7/CHANGES b/lib/PCK_FIO-2002.7/CHANGES deleted file mode 100644 index b755a56..0000000 --- a/lib/PCK_FIO-2002.7/CHANGES +++ /dev/null @@ -1,86 +0,0 @@ ----- $Id: CHANGES,v 1.1 2008-08-23 08:20:28 Jens Exp $ ----- ----- PCK_FIO: a VHDL package for C-style formatted file output ----- Copyright (C) 1995, 2001 Easics NV ----- ----- This library is free software; you can redistribute it and/or ----- modify it under the terms of the GNU Lesser General Public ----- License as published by the Free Software Foundation; either ----- version 2.1 of the License, or (at your option) any later version. ----- ----- This library is distributed in the hope that it will be useful, ----- but WITHOUT ANY WARRANTY; without even the implied warranty of ----- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ----- Lesser General Public License for more details. ----- ----- You should have received a copy of the GNU Lesser General Public ----- License along with this library; if not, write to the Free Software ----- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----- ----- For suggestions, bug reports, enhancement requests, and info about ----- our design services, you can contact us at the following address: ----- http://www.easics.com ----- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium ----- tel.: +32 16 395 600 fax : +32 16 395 619 ----- e-mail: jand@easics.be (Jan Decaluwe) ----- - - -Changes from version 1.16 to version 2002.07 -============================================ - -PCK_FIO is now distributed under the GNU Lesser General Public Licencse -instead of the ordinary GPL, to better reflect intended usage. - -Cosmetic changes in source code to correct some typos in the testbench output. -A new testbench is also supplied. - -The package now uses IEEE.numeric_std as default. - -URL http://www.easics.com has been made part of address. - -Changed syntax in the PCK_FIO package and its testbench to support VHDL-1993. -Because of backwards-incompatibility, it has been necessary to supply -different sets of files for 1987 and 1993. - -Split the packages into a separate file for the header and a -separate file for the body (in compliance with Easics' guidelines). - -These changes resulted in the files: - -Files for VHDL-1993: --------------------- - PCK_FIO_1993.vhd : the source code of the header file for the package - PCK_FIO_1993_BODY.vhd: the source code of the body of the package - TB_PCK_FIO_1993.vhd: the testbench for the package - -Files for VHDL-1987: --------------------- - PCK_FIO_1987.vhd: the source code of the header file for the package - PCK_FIO_1987_BODY.vhd: the source code of the body of the package - TB_PCK_FIO_1987.vhd: the testbench for the package - -Updated README and PCK_FIO.html to support these changes. - -Adapted package files to support NUL termination of strings. -fo(Arg: string) now prints the string until the first NUL. -Several examples of its use are demonstrated in the supplied testbenches. - -Made cosmetic changes to code to improve readability. - -Acknowledgment --------------- -These changes have been implemented by Peter Geens. - - - - - - - - - - - - - diff --git a/lib/PCK_FIO-2002.7/PCK_FIO.html b/lib/PCK_FIO-2002.7/PCK_FIO.html deleted file mode 100644 index 6b5fc72..0000000 --- a/lib/PCK_FIO-2002.7/PCK_FIO.html +++ /dev/null @@ -1,339 +0,0 @@ - - - - - - VHDL package for formatted file output - - - - -
-

-Name

-PCK_FIO - VHDL package for  formatted file output -

-

-

-Contents

-Usage -
The file output function 'fo' -
Format specifiers -
Special characters -
Things to watch out for -
Methodology notes -
Parametrization -
Test bench -
Known limitations and problems -
Author -

-

-

-Usage

-PCK_FIO is a VHDL package that defines  fprint, a function -for formatted file output. -

After installing the package you can call fprint as follows: -

  fprint(F, L, Format, fo(Expr_1), fo(Expr_2), ... fo(Expr_n));
-where F is the filehandle and L is the line variable. -

The argument Format is the format string, which consists of ``normal'' -substrings which are copied verbatim, and format specifiers, starting with -'%'. -A typical format string looks as follows: -

   "Arg1 = %6r, Arg2 = %10d, Arg3 = %-5r\n"
-The remaining arguments are the expressions whose results you want to write -to the file, embedded in fo function calls. There can be 0 to -32 of such arguments. The expressions can be of any type for which an fo -function exists. String expressions can also be called directly. -

-

-

-The file output function 'fo'

-The fo (file output) functions do the trick. They -return a tagged string representation that is meaningful to format specifiers. -Here are some examples: -
  fo (signed'("1100"))   returns "S:1100" 
-  fo (unsigned'("1100")) returns "U:1100" 
-  fo (TRUE)              returns "L:T"
-  fo (127)               returns "I:127"
-The internal behavior of fo is irrelevant to the typical user. -
  -
The fo function is currently overloaded as follows:
- -
  function fo (Arg: unsigned)          return string;
-  function fo (Arg: signed)            return string;
-  function fo (Arg: std_logic_vector)  return string;
-  function fo (Arg: std_ulogic_vector) return string;
-  function fo (Arg: bit_vector)        return string;
-  function fo (Arg: integer)           return string;
-  function fo (Arg: std_ulogic)        return string;
-  function fo (Arg: bit)               return string;
-  function fo (Arg: boolean)           return string; 
-  function fo (Arg: character)         return string;
-  function fo (Arg: string)            return string;
-  function fo (Arg: time)              return string;
- -


To support null-terminated strings, the function fo(Arg: -string) processes Arg up to the first NUL character, -if any. If you want the whole string to be outputted you can just enter -the string as a direct argument in fprint.  See also the -examples in the testbench. -

-
- -

-Format specifiers

-The general format of a format specifier is: -
   %[-][n]c
-The optional - sign specifies left justified output; default is -right justified. -

The optional number n specifies a field-width. If it is not specified, -fprint -does something reasonable. -

c is the conversion specifier. Currently the following conversion -specifiers are supported: -

-
-r
- -
-reasonable output format (inspired by Synopsys VSS)
- -
Prints the ``most reasonable'' representation e.g. hex for -unsigned, signed and other bit-like vectors (not preferred for integers)
- -
-b
- -
-bit-oriented output
- -
-d
- -
-decimal output
- -
-s
- -
-string output (e.g. in combination with 'IMAGE for enum types)
- -
-q
- -
-``qualified'' string output (shows internal representation from fo)
- -
-{}
- -
-Iteration operator, used as follows:
- -
-%n{<format-string>}
- -
In this case, n is the iteration count and is mandatory. Iteration -can be nested.
- -
-

-Special characters

-To print a double quote,  use '""' in the format string (VHDL -convention). To print the special characters, '\', and '%', -escape them with '\'. To prevent '{' and '}' -from being interpreted as opening and closing brackets in iteration strings, -escape them with '\'. -

A newline is specified in the format string by '\n'. -

-

-

-Things to notice

-The fprint function expands into VHDL write and writeline -commands. As in plain VHDL, nothing will be written to the output file -until a writeline is given. Therefore, don't forget to include -'\n' -commands in the format string, or it ``will not work''. -

The preferred format specifier for integers is, naturally, %d. -This calls the VHDL write for integers. If you specify a field -width that is too small, the field will automatically be expanded. If you -use %r for integers, the field is not expanded automatically, which -means that some digits are simply thrown away. This may sometimes be useful -but it is also dangerous. Look at the test bench output for differences -between %d and %r output. -

When using the %d format specifier, the VHDL constraints for -the allowed integer range apply. -

In VHDL, signed/unsigned types have been standardized only relatively -recently, in the package IEEE.numeric_std. The lack of a standard -has caused (and is causing) portability issues. The most popular non-standard -package that defines signed/unsigned is IEEE.std_logic_arith from -Synopsys. PCK_FIO works with both packages,  but refers to the standard -package IEEE.numeric_std by default. To use IEEE.std_logic_arith -instead, replace the reference to IEEE.numeric_std in the source -code.  This needs to be done consistently in a design database (e.g. -in the PCK_FIO test bench as well). -

-

-

-Methodology notes

-The obvious application for fprint is in test benches, to produce -output files that trace the simulation behavior. -

Another interesting application for fprint is to produce info, -warning and error messages in your models. As it can take arguments, fprint -is much better suited for this task than VHDL's assert or report -statements. Actually fprint produces its own (few) warning messages. -

An advanced usage is the generation of test vectors in a specific format. -Instead of using the fo functions, you can write your own set -of functions that return the symbols of a specific test format in a way -that is understandable to the fprint format specifiers. As an -example, when a high output value should be represented using the symbol -'H' it suffices to write a conversion function that returns "B:H" and call -it in combination with the %b format specifier. -

-

-

-Parametrization

-Prefix and postfix strings for bit-oriented and hex-oriented output are -parameterizable in the packages to accommodate different output styles. -The settings in the distribution are such that hex output is indicated -by the prefix '0x', while  bit output prefix and postfix are empty -strings. -

You can adapt the output style by modifying the following constants -in the package header: -

   -- prefix string for hex output -
  -- VHDL style:    "X""" -
  -- Verilog style: "h'" -
  -- C style:       "0x" -
  constant FIO_h_PRE:  string := "0x"; -

  -- postfix string for hex output -
  -- VHDL style:    """" -
  constant FIO_h_POST: string := ""; -

  -- prefix string for bit vector output -
  -- VHDL style:    "B""" -
  -- Verilog style: "b'" -
  constant FIO_bv_PRE:  string := ""; -

  -- postfix string for bit vector output -
  -- VHDL style:    """" -
  constant FIO_bv_POST: string := ""; -

  -- prefix string for bit output -
  -- VHDL style:    "'" -
  -- Verilog style: "b'" -
  constant FIO_b_PRE:  string := ""; -

  -- postfix string for bit output -
  -- VHDL style:    "'" -
  constant FIO_b_POST: string := ""; -

-

-

-Test bench

-Included in the distribution are the files TB_PCK_FIO_1987.vhd and -TB_PCK_FIO_1993 with a test bench,depending on the standard you're -running, for the PCK_FIO package. The file PCK_FIO.out.gold contains -the expected output. If you run the test bench it should produce the file -PCK_FIO.out -that should be identical to PCK_FIO.out.gold. The source files -should be analyzed in a VHDL library EASICS_PACKAGES. -

A good way to understand fprint is to inspect the test bench -and what it produces. -

-

-

-Known limitations and problems

-This VHDL package is an implementation of a flexible concept. It is likely -to be extended and modified in the future. Backward compatibility is not -guaranteed. Therefore, it is not recommended to give this package the status -of a company wide standard package (or even worse, a VHDL standard package). -Rather, it should be linked with a particular project (and it can be regarded -as a standard package within that project). -

PCK_FIO is available in either standard VHDL Std1076-1987 or standard -VHDL Std1076-1993. Nevertheless, some simulators/versions have problems -with the package. The following is an overview of currently known issues: -
  -

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
PCK_FIO_1987 and various simulators/versions
SimulatorPCK_FIO_1987
Synopsys VSS 3.5 and earlierIncorrect (all zero) output in compiled mode
Synopsys VSS 97.01OK
Synopsys VSS/Scirocco 2000.02Incorrect output in compiled mode, interpreted mode works
Mentor quickhdlOK
Modeltech modelsimOK
Cadence LeapfrogShould work with 4.4.1 -
Mysterious problems have been reported - please run the test bench -and report problems
- -
  -
- - - - - - - - - - - - - - - - - - - - - - - - - -
PCK_FIO_1993 and various simulators/versions
SimulatorPCK_FIO_1993
Synopsys VSS/Scirocco 2000.02Compile errors due to improper handling of files by Synopsys
Synopsys VSS/Scirocco 2000.06works fine
Modeltech modelsim 5.4c and higherOK
- -

Although the package name suggests file IO, it only does file output. -

-

-

-Author

-Jan Decaluwe -

-

- - diff --git a/lib/PCK_FIO-2002.7/PCK_FIO.out.gold b/lib/PCK_FIO-2002.7/PCK_FIO.out.gold deleted file mode 100644 index 3fcfe4c3ee52eaf461a691b4b3eca59aa1cc34dc..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 8979 zcmd5?ZExa8628y;iV{*T$qGl1SBA@FmCPi%(M6ePLS{#&(MARu;vHkNw#kbo```De z>TcWMb^@n6-63KcQ%`lhc9*Mj{r;bK7au?E#Ph62{qvjt+4V?OH96NxmINI zwbTArg~?4e%9*6u=q`*W!SL=u4H0?E5-tA@$yltaWH-SicZ6FxefKp6xz*ob;I_?K zkbSj!Z;u$^0mzzM9T%vIOf(k5c*Md7Gza@0;{j zy1Ko@wfW)v0-3@oOye17GaC9~s27(gCO?_Xrz*-M{p9y8oqR32Y*F*7M6vTN;<#A2 zC46sYY8dz-4eyc5!%QV9MG6ZT0u1Y!N{9YTjX1rl{HxF&ecPaK->6A?Iu`{9@Vm_Y z1q(ntPiY({Qy=RKi!u&a1Wt`)mZ(h0>YMsldE&uuh_`%w%))24SQpFOdbE+y#)vis zwDCIxYXMh%jpHrk+ja}m)C_VM4C$Dp{dBNP-CZ)FMz=jP5?w7oyLyO44Cckgkz@*4 zO@n8er*^XmpuDWBg-P71eykEg+5I2T_m7nn)hVcz#u(XT#@T4Qtgdq+QMmoo*`;E{ zy1x3t?|tl{tf~q7sUHP1-o&tx)NDc}j==LC%=l3psgl(UyCSiu=gKFRkU4PFNuDX} zvfvg(Mj&@KAu0;a+lT;UDmY1G@@CIF+&FHfv1BKI;~X}kI=xq7C*1ymY-izuF~@v@ ztrmZwO4D*~LP{ zY}9Bz9pF2P%F;S(TxQ}{FR<(~cAY5+#UqA5%)`v4@Z)qoUE;>8Hdg8y9pCcIuG2I1 zetFww`xTpko3&Uep=*Y0h@1J0%U;RUL6CWI5@5IE&FOhoU$HJTWRuWm<)?8Z)h6;D zyNx?SD`Z$s-@UngIH|o~a+vxjt?e@b(hUUX{i5Z#dxA-PC?lzTIXNS~F%d%OZ zfBu;|^p)_Oq&MIX*l-c5Y~WgxEYiRpM?bKazPi2qukEoca;Gc%a+kdQL-IPXfn3_! z2r%}m1}J{l$`Ag(l`o5H>h8QGS^nP9#l8eZhu9vRE2klzG`OzhFTCnuZ$|kg+maNZ zJ=!`RrzhAi{b(fRo2*khii(gDiRZlW}gKIMe`h#KJ(ZZm@XNf(y{% zNaLA7)uSEmPIPx)I$eHam3LWWcNL;N>2rV;ff4`JFx%Jt5GE8#xzx}eXj&E!=3~C* zT0?(m=ncRi%tsC8$YLzWqU>i4uAAd>phZ|wiMLIcLEjbF0$iYrk;Yfu=B?y6Zzach z;yFBiBLehajntmF4unEwE}(UXrudGDHKDySy&E9T6M&)3KLq0jiT5%9Pb$*df@r!Lj>#y86hJ%)1`7$CnS{+!dB^tQ~ zw6vTU>>A+mdScNAPOB)~X_pqHoPp&~u+Vpm(Uz^|8EZ41*08o`%q=(rL?)TTg4g`y z8GCD_g|3J-1~=Foydv6I+@cG3fj9TuA?6vA=L||5N-Rn|WFc7!R9&c&oWK~1o3VRV zQ>a=1@gd6#$)U`Pci_g@LNx~&ls?OO@eXTnd7)YW4KnvEW_Qn76sje#L9Y@RopxU7 zmKhihMLc_Q$H-8PXTyYjWUb4y+i?Y8%_~mTRPdSztiSD7*BZ~-S4V{Vxk}YEj$K zX6g&Hpi2k4ID6(URoWtfqLGN>q6dW|f)V#F`BVf)I^65kr^i6sHQ* zqm*}`M_>0e=y1PF`gB$wA1#~@_0dbT6GibOACW{U9~+<@vV|MmGFBbbe zNzke1$80{mLd!WCk;1)%rs!__lhs>!Jg2lMF1an9AAh0y0ITTs1Ddb-F_OFe05$Ws z)iyu*;r0U5Mpc9|vhmYT^oyTx*Stsgr-Qp|K7+gT)9edd9`}}xnsBD`3?EPkl3YCI z!tHt69x;c0&0Gi!Acv5l&Rl+JJO3(bLrmQgRim7p)wV`ioP0gV`B&o9b@8~%XfKaq zZskuCnBq24Pned&(kf-8pv{L(t%*zH1!3wGM#^~JulmvJVqqv-$tahvMCo=NRT>t<8 diff --git a/lib/PCK_FIO-2002.7/PCK_FIO_1987.vhd b/lib/PCK_FIO-2002.7/PCK_FIO_1987.vhd deleted file mode 100644 index d4cf8e6..0000000 --- a/lib/PCK_FIO-2002.7/PCK_FIO_1987.vhd +++ /dev/null @@ -1,105 +0,0 @@ ----- $Id: PCK_FIO_1987.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $ ----- ----- PCK_FIO: a VHDL package for C-style formatted file output ----- Copyright (C) 1995, 2001 Easics NV ----- ----- This library is free software; you can redistribute it and/or ----- modify it under the terms of the GNU Lesser General Public ----- License as published by the Free Software Foundation; either ----- version 2.1 of the License, or (at your option) any later version. ----- ----- This library is distributed in the hope that it will be useful, ----- but WITHOUT ANY WARRANTY; without even the implied warranty of ----- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ----- Lesser General Public License for more details. ----- ----- You should have received a copy of the GNU Lesser General Public ----- License along with this library; if not, write to the Free Software ----- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----- ----- For suggestions, bug reports, enhancement requests, and info about ----- our design services, you can contact us at the following address: ----- http://www.easics.com ----- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium ----- tel.: +32 16 395 600 fax : +32 16 395 619 ----- e-mail: jand@easics.be (Jan Decaluwe) ----- - -use STD.TEXTIO.all; - -library IEEE; -use IEEE.std_logic_1164.all; --- signed/unsigned definition: use either std_logic_arith or numeric_std --- use IEEE.std_logic_arith.all; -- the Synopsys one -use IEEE.numeric_std.all; - -package PCK_FIO is - - -- prefix string for hex output - -- VHDL style: "X""" - -- Verilog style: "h'" - -- C style: "0x" - constant FIO_h_PRE: string := "0x"; - - -- postfix string for hex output - -- VHDL style: """" - constant FIO_h_POST: string := ""; - - -- prefix string for bit vector output - -- VHDL style: "B""" - -- Verilog style: "b'" - constant FIO_bv_PRE: string := ""; - - -- postfix string for bit vector output - -- VHDL style: """" - constant FIO_bv_POST: string := ""; - - -- prefix string for bit output - -- VHDL style: "'" - -- Verilog style: "b'" - constant FIO_b_PRE: string := ""; - - -- postfix string for bit output - -- VHDL style: "'" - constant FIO_b_POST: string := ""; - - -- digit width for the string representation of integers - constant FIO_d_WIDTH: integer := 10; - - -- bit width for the string representation of integers - constant FIO_b_WIDTH: integer := 32; - - -- definition of the NIL string (default value for fprint arguments) - -- fprint stops consuming arguments at the first NIL argument - constant FIO_NIL: string := "\"; - - - procedure fprint - (F: out text; - L: inout line; - Format: in string; - A1 , A2 , A3 , A4 , A5 , A6 , A7 , A8 : in string := FIO_NIL; - A9 , A10, A11, A12, A13, A14, A15, A16: in string := FIO_NIL; - A17, A18, A19, A20, A21, A22, A23, A24: in string := FIO_NIL; - A25, A26, A27, A28, A29, A30, A31, A32: in string := FIO_NIL - ); - - function fo (Arg: unsigned) return string; - function fo (Arg: signed) return string; - function fo (Arg: std_logic_vector) return string; - function fo (Arg: std_ulogic_vector) return string; - function fo (Arg: bit_vector) return string; - function fo (Arg: integer) return string; - function fo (Arg: std_ulogic) return string; - function fo (Arg: bit) return string; - function fo (Arg: boolean) return string; - function fo (Arg: character) return string; - function fo (Arg: string) return string; - function fo (Arg: time) return string; - - procedure FIO_FormatExpand (FMT: inout line; - Format: in string; - StartPointer: in positive); - -end PCK_FIO; - diff --git a/lib/PCK_FIO-2002.7/PCK_FIO_1987_BODY.vhd b/lib/PCK_FIO-2002.7/PCK_FIO_1987_BODY.vhd deleted file mode 100644 index 44e42cf..0000000 --- a/lib/PCK_FIO-2002.7/PCK_FIO_1987_BODY.vhd +++ /dev/null @@ -1,821 +0,0 @@ ----- $Id: PCK_FIO_1987_BODY.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $ ----- ----- PCK_FIO: a VHDL package for C-style formatted file output ----- Copyright (C) 1995, 2001 Easics NV ----- ----- This library is free software; you can redistribute it and/or ----- modify it under the terms of the GNU Lesser General Public ----- License as published by the Free Software Foundation; either ----- version 2.1 of the License, or (at your option) any later version. ----- ----- This library is distributed in the hope that it will be useful, ----- but WITHOUT ANY WARRANTY; without even the implied warranty of ----- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ----- Lesser General Public License for more details. ----- ----- You should have received a copy of the GNU Lesser General Public ----- License along with this library; if not, write to the Free Software ----- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----- ----- For suggestions, bug reports, enhancement requests, and info about ----- our design services, you can contact us at the following address: ----- http://www.easics.com ----- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium ----- tel.: +32 16 395 600 fax : +32 16 395 619 ----- e-mail: jand@easics.be (Jan Decaluwe) ----- - - -package body PCK_FIO is - - -------------------------- - -- FIO Warnings support -- - -------------------------- - - procedure FIO_Warning_Fsbla (F: out text; - L: inout line; - Format: in string; - Pointer: in positive) is - begin - fprint (F, L, "\n** Warning: FIO_PrintLastValue: " & - "Format specifier beyond last argument\n"); - fprint (F, L, "** in format string: ""%s""\n", Format); - fprint (F, L, "** "); - for i in 1 to Pointer-1 loop - fprint (F, L, "-"); - end loop; - fprint (F, L, "^\n"); - end FIO_Warning_Fsbla; - - procedure FIO_Warning_Ufs (F: out text; - L: inout line; - Format: in string; - Pointer: in positive; - Char: in character) is - begin - fprint (F, L, "\n** Warning: FIO_PrintArg: " & - "Unexpected format specifier '%r'\n", - fo(Char)); - fprint (F, L, "** in format string: ""%s""\n", Format) ; - fprint (F, L, "** "); - for i in 1 to Pointer-1 loop - fprint (F, L, "-"); - end loop; - fprint (F, L, "^\n** Assuming 'q' to proceed: "); - end FIO_Warning_Ufs; - - - ---------------------------------- - -- bit conversion support -- - ---------------------------------- - - type T_bit_map is array(bit) of character; - - constant C_BIT_MAP: T_bit_map - := ('0', '1'); - - ---------------------------------- - -- std_logic conversion support -- - ---------------------------------- - - type T_std_logic_map is array(std_ulogic) of character; - - constant C_STD_LOGIC_MAP: T_std_logic_map - := ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-'); - - ------------------------------ - -- Digit conversion support -- - ------------------------------ - - -- types & constants - - subtype S_digit_chars is character range '0' to '9'; - subtype S_digits is integer range 0 to 9 ; - - type T_digit_chars_map is array(S_digit_chars) of S_digits; - - constant C_DIGIT_CHARS_MAP: T_digit_chars_map - := (0, 1, 2, 3, 4, 5, 6, 7, 8, 9); - - type T_digits_map is array(S_digits) of S_digit_chars; - - constant C_DIGITS_MAP: T_digits_map - := ('0', '1', '2', '3', '4', '5', '6', '7', '8', '9'); - - - -------------------------------- - -- Decimal conversion support -- - -------------------------------- - - -- unsigned to decimal - - function U_To_d (Arg: string) return integer is - constant Argument: string(Arg'length downto 1) := Arg; - variable Result: integer := 0; - begin - for i in Argument'range loop - case Argument(i) is when '1' => Result := 2**(i-1) + Result; - when '0' => null; - when others => return(-1); - end case; - end loop; - return (Result); - end U_To_d; - - -- signed to decimal - - function S_To_d (Arg: string) return integer is - constant Argument: string(Arg'length downto 1) := Arg; - variable Result: integer := 0; - begin - case Argument(Argument'left) is - when '1' => Result := - 2**(Argument'left-1); - when '0' => Result := 0; - when others => return (integer'low); - end case; - for i in Argument'left-1 downto 1 loop - case Argument(i) is when '1' => Result := 2**(i-1) + Result; - when '0' => null; - when others => return(integer'low); - end case; - end loop; - return (Result); - end S_To_d; - - -- string to decimal - - function I_To_d (Arg: string(1 to FIO_d_WIDTH+1)) return integer is - constant Sign: character := Arg(1); - constant Value: string(Arg'length-1 downto 1) := Arg(2 to Arg'length); - variable Char: character; - variable Result: integer := 0; - begin - Result := 0; - for i in Value'range loop - Result := Result * 10; - Char := Value(i); - if (Char /= ' ') then - Result := Result + C_DIGIT_CHARS_MAP(Char); - end if; - end loop; - case Sign is when '-' => return(-Result); - when others => return(Result); - end case; - end I_To_d; - - -- boolean (0,1) to decimal - - function B_To_d (Arg: string(1 to 1)) return integer is - begin - case Arg is when "1" => return(1); - when "0" => return(0); - when others => return(-1); - end case; - end B_To_d; - - -- boolean (T,F) to decimal - - function L_To_d (Arg: string(1 to 1)) return integer is - begin - case Arg is when "T" => return(1); - when others => return(0); - end case; - end L_To_d; - - - - ---------------------------- - -- Hex conversion support -- - ---------------------------- - - -- Constants & types - - constant C_HEX_CHARS: string(1 to 17) := "0123456789ABCDEF?"; - - -- Function to return Hex index of a nibble - - function U_To_h_Index(Arg: string(4 downto 1)) return integer is - variable Index: integer := 0; - begin - for i in Arg'range loop - case Arg(i) is when '1' => Index := 2**(i-1) + Index; - when '0' => null; - when others => return (17); - end case; - end loop; - return (Index+1); - end U_To_h_Index; - - -- Hex conversion - - function U_To_h (Arg: string) return string is - variable Result: string((Arg'length-1)/4 +1 downto 1); - variable ExtArg: string(Result'length*4 downto 1) := (others => '0'); - begin - ExtArg(Arg'length downto 1) := Arg; - for i in Result'range loop - Result(i) := C_HEX_CHARS(U_To_h_Index( ExtArg(i*4 downto i*4 -3) )); - end loop; - return (FIO_h_PRE & Result & FIO_h_POST); - end U_To_h; - - - - ---------------------------- - -- Bit conversion support -- - ---------------------------- - - function L_To_b (Arg: string(1 to 1)) return string is - variable Result: string(1 to 1); - begin - case Arg is when "T" => Result := "1"; - when others => Result := "0"; - end case; - return(FIO_b_PRE & Result & FIO_b_POST); - end L_To_b; - - - function I_To_b (Arg: string(1 to FIO_d_WIDTH+1); - Justified: side; - Width: integer) return string is - - variable IntValue: integer := I_To_d(Arg); - variable BitValue: string(1 to FIO_b_WIDTH) := (others => ' '); - variable Sign: character := ' '; - constant Blanks: string(1 to FIO_b_WIDTH) := (others => ' '); - variable BitWidth: integer range 0 to FIO_b_WIDTH; - variable MsPos: integer range 1 to BitValue'length; - variable BitValueExtended: string(1 to 2*FIO_b_WIDTH); - - begin - - if (IntValue < 0) then - Sign := '-'; - IntValue := -IntValue; - end if; - - for i in BitValue'reverse_range loop - BitValue(i) := C_DIGITS_MAP(IntValue mod 2); - IntValue := IntValue / 2; - exit when (IntValue = 0); - end loop; - - BitValueExtended := BitValue & Blanks; - - if (Width = 0) or (Width > FIO_b_WIDTH+1) then - BitWidth := FIO_b_WIDTH; - else - BitWidth := Width-1; - end if; - - if (Justified = RIGHT) then - return (FIO_bv_PRE & - Sign & BitValue(BitValue'length-BitWidth+1 to BitValue'length) & - FIO_bv_POST); - else - for i in BitValue'range loop - if BitValue(i) /= ' ' then - MSPos := i; - exit; - end if; - end loop; - return (FIO_bv_PRE & - Sign & BitValueExtended(MSPos to MSPos+BitWidth-1) & - FIO_bv_POST); - end if; - - end I_To_b; - - - ----------------------------------- - -- Reasonable conversion support -- - ----------------------------------- - - function I_To_r (Arg: string(1 to FIO_d_WIDTH+1); - Justified: side; - Width: integer) return string is - constant Value: string(1 to FIO_d_WIDTH) := Arg(2 to FIO_d_WIDTH+1); - constant Sign: character := Arg(1); - constant Blanks: string(1 to FIO_d_WIDTH) := (others => ' '); - variable IntWidth: integer range 0 to FIO_d_WIDTH; - variable MsPos: integer range 1 to Value'length; - variable ValueExtended: string(1 to 2*FIO_d_WIDTH) := Value & Blanks; - begin - if (Width = 0) or (Width > FIO_d_WIDTH+1) then - IntWidth := FIO_d_WIDTH; - else - IntWidth := Width-1; - end if; - if (Justified = RIGHT) then - return (Sign & Value(Value'length-IntWidth+1 to Value'length)); - else - for i in Value'range loop - if Value(i) /= ' ' then - MSPos := i; - exit; - end if; - end loop; - return (Sign & ValueExtended(MSPos to MSPos+IntWidth-1)); - end if; - end I_To_r; - - - ------------------------------------------- - -- Reasonable output conversion function -- - ------------------------------------------- - - function ReasonableOutput (Arg: string; - Justified: side; - Width: integer) return string is - constant Argument: string(1 to Arg'length) := Arg; - constant TypeSpec: string (1 to 2) := Argument(1 to 2); - constant Value: string(1 to Arg'length-2) := Argument(3 to Arg'length); - begin - case TypeSpec is - when "U:" | "S:" | "V:" => - return U_To_h(Value); - when "I:" => - return I_To_r(Value, Justified, Width); - when "B:" | "L:" | "C:" => - return Value; - when others => - return Argument; - end case; - - end ReasonableOutput; - - - ------------------------------------ - -- Bit output conversion function -- - ------------------------------------ - - function BitOutput (Arg: string; - Justified: side; - Width: integer) return string is - constant Argument: string(1 to Arg'length) := Arg; - constant TypeSpec: string (1 to 2) := Argument(1 to 2); - constant Value: string(1 to Arg'length-2) := Argument(3 to Arg'length); - begin - case TypeSpec is - when "U:" | "S:" | "V:" => - return (FIO_bv_PRE & Value & FIO_bv_POST); - when "B:" => - -- Value(1 to 1) instead of Value for LeapFrog - return (FIO_b_PRE & Value(1 to 1) & FIO_b_POST); - when "I:" => - return I_To_b(Value, Justified, Width); - when "L:" => - -- Value(1 to 1) instead of Value for LeapFrog - return L_To_b(Value(1 to 1)); - when others => - return Argument; - end case; - - end BitOutput; - - - ------------------------------------------- - -- Decimal output conversion function -- - ------------------------------------------- - - function DecimalOutput (Arg: string) return integer is - constant Argument: string(1 to Arg'length) := Arg; - constant TypeSpec: string (1 to 2) := Argument(1 to 2); - constant Value: string(1 to Arg'length-2) := Argument(3 to Arg'length); - begin - case TypeSpec is - when "U:"| "V:" => - return U_To_d(Value); - when "S:" => - return S_To_d(Value); - when "I:" => - return I_To_d(Value); - when "B:" => - return B_To_d(Value); - when "L:" => - return L_To_d(Value); - when others => - return integer'low; - end case; - - end DecimalOutput; - - - ---------------------------- - -- Atomic print functions -- - ---------------------------- - - -- test for end of format string - - function FIO_EOS (Format: in string; - Pointer: in integer) - return boolean is - begin - return (Pointer > Format'length); - end FIO_EOS; - - - -- Atomic value print function - - procedure FIO_PrintValue (F: out text; - L: inout line; - Format: in string; - Pointer: inout integer; - Last: in boolean := FALSE) is - variable Char: character; - begin - while (not FIO_EOS(Format, Pointer)) loop - Char := Format(Pointer); - case Char is - when '\' => - Pointer := Pointer + 1; - exit when (FIO_EOS(Format, Pointer)); - Char := Format(Pointer); - case Char is when 'n' => writeline(F, L); - when others => write(L, Char); - end case; - when '%' => - if Last then - FIO_Warning_Fsbla(F, L, Format, Pointer); - end if; - Pointer := Pointer + 1; - exit; - when others => - write(L, char); - end case; - Pointer := Pointer + 1; - end loop; - end FIO_PrintValue; - - - ---- Atomic argument print function - - procedure FIO_PrintArg (F: out text; - L: inout line; - Format: in string; - Pointer: inout integer; - Arg: in string) is - variable Char: character; - variable Justified: side; - variable Width: integer; - begin - - FIO_PrintValue(F, L, Format, Pointer); - - Justified := RIGHT; - Width := 0; - while (not FIO_EOS(Format, Pointer)) loop - Char := Format(Pointer); - case Char is - when '-' => - Justified := LEFT; - Pointer := Pointer + 1; - when '0' to '9' => - Width := Width*10 + C_DIGIT_CHARS_MAP(Char); - Pointer := Pointer + 1; - when 'r' => - write(L, ReasonableOutput(Arg, Justified, Width), Justified, Width); - Pointer := Pointer + 1; - exit; - when 'b' => - write(L, BitOutput(Arg, Justified, Width), Justified, Width); - Pointer := Pointer + 1; - exit; - when 'd' => - write(L, DecimalOutput(Arg), Justified, Width); - Pointer := Pointer + 1; - exit; - when 'q' | 's' => - write(L, Arg, Justified, Width); - Pointer := Pointer + 1; - exit; - when others => - FIO_Warning_Ufs(F, L, Format, Pointer, Char); - write(L, Arg, Justified, Width); - Pointer := Pointer + 1; - exit; - end case; - end loop; - end FIO_PrintArg; - - - ----------------------------------------------------- - -- The format string iteration expansion procedure -- - ----------------------------------------------------- - - procedure FIO_FormatExpand (FMT: inout line; - Format: in string; - StartPointer: in positive) is - - variable Pointer: positive := StartPointer; - variable TokenStart: positive; - variable IterStringStart: positive; - variable IterStringEnd: positive; - variable IterCount: natural; - variable OpenBrackets: natural; - variable L: line; - - begin - - FORMAT_SEARCH: while not FIO_EOS(Format, Pointer) loop - - case Format(Pointer) is - - -- look for format specifier - when '%' => - - -- initialize iteration token search - TokenStart := Pointer; - IterCount := 0; - Pointer := Pointer + 1; - - -- start iteration token search - TOKEN_READ: while not FIO_EOS(Format, Pointer) loop - - case Format(Pointer) is - - -- read iteration counter - when '0' to '9' => - IterCount := IterCount*10 + C_DIGIT_CHARS_MAP(Format(Pointer)); - Pointer := Pointer + 1; - - -- expect open bracket - when '{' => - - -- initialize iteration string read - OpenBrackets := 1; - IterStringStart := Pointer + 1; - Pointer := Pointer + 1; - -- quit prematurely when iteration count is 0 - next FORMAT_SEARCH when (IterCount = 0); - - -- start iteration string read - ITER_STRING_READ: while not FIO_EOS(Format, Pointer) loop - - case Format(Pointer) is - -- keep track of open brackets - when '{' => - OpenBrackets := OpenBrackets + 1; - Pointer := Pointer + 1; - -- when closing bracket is found, process iteration string - when '}' => - OpenBrackets := OpenBrackets - 1; - if (OpenBrackets = 0) then - IterStringEnd := Pointer-1; - if (TokenStart /= 1) then - write(L, Format(1 to TokenStart-1)); - end if; - for i in 1 to IterCount loop - write(L, Format(IterStringStart to IterStringEnd)); - end loop; - if (IterStringEnd /= Format'length) then - write(L, Format(IterStringEnd+2 to Format'length)); - end if; - -- call expansion procedure recursively on expanded format - FIO_FormatExpand(FMT, L.all, TokenStart); - deallocate(L); - return; - end if; - Pointer := Pointer + 1; - -- skip escaped characters - when '\' => - Pointer := Pointer + 2; - -- read iteration string - when others => - Pointer := Pointer + 1; - - end case; - - end loop ITER_STRING_READ; - - -- stop iteration token search when no opening bracket found - when others => - Pointer := Pointer + 1; - next FORMAT_SEARCH; - - end case; - - end loop TOKEN_READ; - - -- skip escaped characters - when '\' => - Pointer := Pointer + 2; - - -- read other characters - when others => - Pointer := Pointer + 1; - - end case; - - end loop FORMAT_SEARCH; - - write(FMT, Format); - deallocate(L); - - end FIO_FormatExpand; - - - - -------------------------- - -- The fprint procedure -- - -------------------------- - - procedure fprint - (F: out text; - L: inout line; - Format: in string; - A1 , A2 , A3 , A4 , A5 , A6 , A7 , A8 : in string := FIO_NIL; - A9 , A10, A11, A12, A13, A14, A15, A16: in string := FIO_NIL; - A17, A18, A19, A20, A21, A22, A23, A24: in string := FIO_NIL; - A25, A26, A27, A28, A29, A30, A31, A32: in string := FIO_NIL - ) is - - variable Pointer: integer; - variable FMT: line; - - begin - - Pointer := 1; - - FIO_FormatExpand (FMT, Format, Format'low); - - if (A1 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A1 ); - if (A2 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A2 ); - if (A3 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A3 ); - if (A4 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A4 ); - if (A5 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A5 ); - if (A6 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A6 ); - if (A7 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A7 ); - if (A8 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A8 ); - if (A9 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A9 ); - if (A10 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A10); - if (A11 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A11); - if (A12 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A12); - if (A13 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A13); - if (A14 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A14); - if (A15 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A15); - if (A16 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A16); - if (A17 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A17); - if (A18 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A18); - if (A19 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A19); - if (A20 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A20); - if (A21 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A21); - if (A22 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A22); - if (A23 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A23); - if (A24 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A24); - if (A25 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A25); - if (A26 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A26); - if (A27 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A27); - if (A28 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A28); - if (A29 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A29); - if (A30 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A30); - if (A31 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A31); - if (A32 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A32); - end if; end if; end if; end if; end if; end if; end if; end if; - end if; end if; end if; end if; end if; end if; end if; end if; - end if; end if; end if; end if; end if; end if; end if; end if; - end if; end if; end if; end if; end if; end if; end if; end if; - - FIO_PrintValue(F, L, FMT.all, Pointer, Last => TRUE); - - deallocate(FMT); - - end fprint; - - - ------------------------------------------- - -- Formatted output conversion functions -- - ------------------------------------------- - - function fo (Arg: unsigned) return string is - constant Argument: unsigned(1 to Arg'length) := Arg; - variable Result: string(1 to Arg'length); - begin - for i in Argument'range loop - Result(i) := C_STD_LOGIC_MAP(Argument(i)); - end loop; - return ("U:" & Result); - end fo; - - function fo (Arg: signed) return string is - constant Argument: signed(1 to Arg'length) := Arg; - variable Result: string(1 to Arg'length); - begin - for i in Argument'range loop - Result(i) := C_STD_LOGIC_MAP(Argument(i)); - end loop; - return ("S:" & Result); - end fo; - - function fo (Arg: std_logic_vector) return string is - constant Argument: std_logic_vector(1 to Arg'length) := Arg; - variable Result: string(1 to Arg'length); - begin - for i in Argument'range loop - Result(i) := C_STD_LOGIC_MAP(Argument(i)); - end loop; - return ("V:" & Result); - end fo; - - function fo (Arg: std_ulogic_vector) return string is - constant Argument: std_ulogic_vector(1 to Arg'length) := Arg; - variable Result: string(1 to Arg'length); - begin - for i in Argument'range loop - Result(i) := C_STD_LOGIC_MAP(Argument(i)); - end loop; - return ("V:" & Result); - end fo; - - function fo (Arg: bit_vector) return string is - constant Argument: bit_vector(1 to Arg'length) := Arg; - variable Result: string(1 to Arg'length); - begin - for i in Argument'range loop - Result(i) := C_BIT_MAP(Argument(i)); - end loop; - return ("V:" & Result); - end fo; - - function fo (Arg: integer) return string is - variable Argument: integer := Arg; - variable Result: string(1 to FIO_d_WIDTH) := (others => ' '); - variable Sign: character := ' '; - begin - if (Argument < 0) and (Argument /= integer'low) then - Sign := '-'; - Argument := -Argument; - end if; - for i in Result'reverse_range loop - Result(i) := C_DIGITS_MAP(Argument mod 10); - Argument := Argument / 10; - exit when (Argument = 0); - end loop; - return ("I:" & Sign & Result); - end fo; - - function fo (Arg: std_ulogic) return string is - begin - return ("B:" & C_STD_LOGIC_MAP(Arg)); - end fo; - - function fo (Arg: bit) return string is - begin - return ("B:" & C_BIT_MAP(Arg)); - end fo; - - function fo (Arg: boolean) return string is - begin - if (ARG = TRUE) then - return ("L:T"); - else - return ("L:F"); - end if; - end fo; - - function fo (Arg: character) return string is - begin - return ("C:" & Arg); - end fo; - - -- auxilary function fgets(Arg: string) - -- gives index until first NUL - -- reads string from 1 to Arg'length - function fgets (Arg: string) return integer is - variable index: integer := Arg'length; - begin - for i in 1 to Arg'length loop - if Arg(i) = NUL then - index := i - 1; - exit; - else - null; - end if; - end loop; - return index; - end fgets; - - function fo (Arg: string) return string is - begin - return Arg(1 to fgets(Arg)); - end fo; - - function fo (Arg: time) return string is - begin - return fo (integer (Arg / 1 ns)); - end fo; - -end PCK_FIO; - - - - - - - - - - - - - diff --git a/lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd b/lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd deleted file mode 100644 index 9df893e..0000000 --- a/lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd +++ /dev/null @@ -1,108 +0,0 @@ ----- $Id: PCK_FIO_1993.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $ ----- ----- PCK_FIO: a VHDL package for C-style formatted file output ----- Copyright (C) 1995, 2001 Easics NV ----- ----- This library is free software; you can redistribute it and/or ----- modify it under the terms of the GNU Lesser General Public ----- License as published by the Free Software Foundation; either ----- version 2.1 of the License, or (at your option) any later version. ----- ----- This library is distributed in the hope that it will be useful, ----- but WITHOUT ANY WARRANTY; without even the implied warranty of ----- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ----- Lesser General Public License for more details. ----- ----- You should have received a copy of the GNU Lesser General Public ----- License along with this library; if not, write to the Free Software ----- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----- ----- For suggestions, bug reports, enhancement requests, and info about ----- our design services, you can contact us at the following address: ----- http://www.easics.com ----- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium ----- tel.: +32 16 395 600 fax : +32 16 395 619 ----- e-mail: jand@easics.be (Jan Decaluwe) ----- - - -use STD.TEXTIO.all; - -library IEEE; -use IEEE.std_logic_1164.all; --- signed/unsigned definition: use either std_logic_arith or numeric_std --- use IEEE.std_logic_arith.all; -- the Synopsys one -use IEEE.numeric_std.all; - -package PCK_FIO is - - - -- prefix string for hex output - -- VHDL style: "X""" - -- Verilog style: "h'" - -- C style: "0x" - constant FIO_h_PRE: string := "0x"; - - -- postfix string for hex output - -- VHDL style: """" - constant FIO_h_POST: string := ""; - - -- prefix string for bit vector output - -- VHDL style: "B""" - -- Verilog style: "b'" - constant FIO_bv_PRE: string := ""; - - -- postfix string for bit vector output - -- VHDL style: """" - constant FIO_bv_POST: string := ""; - - -- prefix string for bit output - -- VHDL style: "'" - -- Verilog style: "b'" - constant FIO_b_PRE: string := ""; - - -- postfix string for bit output - -- VHDL style: "'" - constant FIO_b_POST: string := ""; - - -- digit width for the string representation of integers - constant FIO_d_WIDTH: integer := 10; - - -- bit width for the string representation of integers - constant FIO_b_WIDTH: integer := 32; - - -- definition of the NIL string (default value for fprint arguments) - -- fprint stops consuming arguments at the first NIL argument - constant FIO_NIL: string := "\"; - - procedure fprint - (file F: text; - L: inout line; - Format: in string; - A1 , A2 , A3 , A4 , A5 , A6 , A7 , A8 : in string := FIO_NIL; - A9 , A10, A11, A12, A13, A14, A15, A16: in string := FIO_NIL; - A17, A18, A19, A20, A21, A22, A23, A24: in string := FIO_NIL; - A25, A26, A27, A28, A29, A30, A31, A32: in string := FIO_NIL - ); - - function fo (Arg: unsigned) return string; - function fo (Arg: signed) return string; - function fo (Arg: std_logic_vector) return string; - function fo (Arg: std_ulogic_vector) return string; - function fo (Arg: bit_vector) return string; - function fo (Arg: integer) return string; - function fo (Arg: std_ulogic) return string; - function fo (Arg: bit) return string; - function fo (Arg: boolean) return string; - function fo (Arg: character) return string; - function fo (Arg: string) return string; - function fo (Arg: time) return string; - - procedure FIO_FormatExpand (FMT: inout line; - Format: in string; - StartPointer: in positive); - -end PCK_FIO; - - - diff --git a/lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd b/lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd deleted file mode 100644 index 3d123f0..0000000 --- a/lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd +++ /dev/null @@ -1,814 +0,0 @@ ----- $Id: PCK_FIO_1993_BODY.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $ ----- ----- PCK_FIO: a VHDL package for C-style formatted file output ----- Copyright (C) 1995, 2001 Easics NV ----- ----- This library is free software; you can redistribute it and/or ----- modify it under the terms of the GNU Lesser General Public ----- License as published by the Free Software Foundation; either ----- version 2.1 of the License, or (at your option) any later version. ----- ----- This library is distributed in the hope that it will be useful, ----- but WITHOUT ANY WARRANTY; without even the implied warranty of ----- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ----- Lesser General Public License for more details. ----- ----- You should have received a copy of the GNU Lesser General Public ----- License along with this library; if not, write to the Free Software ----- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----- ----- For suggestions, bug reports, enhancement requests, and info about ----- our design services, you can contact us at the following address: ----- http://www.easics.com ----- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium ----- tel.: +32 16 395 600 fax : +32 16 395 619 ----- e-mail: jand@easics.be (Jan Decaluwe) ----- - - - package body PCK_FIO is - - -------------------------- - -- FIO Warnings support -- - -------------------------- - - procedure FIO_Warning_Fsbla (file F: text; - L: inout line; - Format: in string; - Pointer: in positive) is - begin - fprint (F, L, "\n** Warning: FIO_PrintLastValue: " & - "Format specifier beyond last argument\n"); - fprint (F, L, "** in format string: ""%s""\n", Format); - fprint (F, L, "** "); - for i in 1 to Pointer-1 loop - fprint (F, L, "-"); - end loop; - fprint (F, L, "^\n"); - end FIO_Warning_Fsbla; - - procedure FIO_Warning_Ufs (file F: text; - L: inout line; - Format: in string; - Pointer: in positive; - Char: in character) is - begin - fprint (F, L, "\n** Warning: FIO_PrintArg: " & - "Unexpected format specifier '%r'\n", - fo(Char)); - fprint (F, L, "** in format string: ""%s""\n", Format) ; - fprint (F, L, "** "); - for i in 1 to Pointer-1 loop - fprint (F, L, "-"); - end loop; - fprint (F, L, "^\n** Assuming 'q' to proceed: "); - end FIO_Warning_Ufs; - - - ---------------------------------- - -- bit conversion support -- - ---------------------------------- - - type T_bit_map is array(bit) of character; - - constant C_BIT_MAP: T_bit_map - := ('0', '1'); - - ---------------------------------- - -- std_logic conversion support -- - ---------------------------------- - - type T_std_logic_map is array(std_ulogic) of character; - - constant C_STD_LOGIC_MAP: T_std_logic_map - := ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-'); - - ------------------------------ - -- Digit conversion support -- - ------------------------------ - - -- types & constants - - subtype S_digit_chars is character range '0' to '9'; - subtype S_digits is integer range 0 to 9 ; - - type T_digit_chars_map is array(S_digit_chars) of S_digits; - - constant C_DIGIT_CHARS_MAP: T_digit_chars_map - := (0, 1, 2, 3, 4, 5, 6, 7, 8, 9); - - type T_digits_map is array(S_digits) of S_digit_chars; - - constant C_DIGITS_MAP: T_digits_map - := ('0', '1', '2', '3', '4', '5', '6', '7', '8', '9'); - - - -------------------------------- - -- Decimal conversion support -- - -------------------------------- - - -- unsigned to decimal - - function U_To_d (Arg: string) return integer is - constant Argument: string(Arg'length downto 1) := Arg; - variable Result: integer := 0; - begin - for i in Argument'range loop - case Argument(i) is when '1' => Result := 2**(i-1) + Result; - when '0' => null; - when others => return(-1); - end case; - end loop; - return (Result); - end U_To_d; - - -- signed to decimal - - function S_To_d (Arg: string) return integer is - constant Argument: string(Arg'length downto 1) := Arg; - variable Result: integer := 0; - begin - case Argument(Argument'left) is - when '1' => Result := - 2**(Argument'left-1); - when '0' => Result := 0; - when others => return (integer'low); - end case; - for i in Argument'left-1 downto 1 loop - case Argument(i) is when '1' => Result := 2**(i-1) + Result; - when '0' => null; - when others => return(integer'low); - end case; - end loop; - return (Result); - end S_To_d; - - -- string to decimal - - function I_To_d (Arg: string(1 to FIO_d_WIDTH+1)) return integer is - constant Sign: character := Arg(1); - constant Value: string(Arg'length-1 downto 1) := Arg(2 to Arg'length); - variable Char: character; - variable Result: integer := 0; - begin - Result := 0; - for i in Value'range loop - Result := Result * 10; - Char := Value(i); - if (Char /= ' ') then - Result := Result + C_DIGIT_CHARS_MAP(Char); - end if; - end loop; - case Sign is when '-' => return(-Result); - when others => return(Result); - end case; - end I_To_d; - - -- boolean (0,1) to decimal - - function B_To_d (Arg: string(1 to 1)) return integer is - begin - case Arg is when "1" => return(1); - when "0" => return(0); - when others => return(-1); - end case; - end B_To_d; - - -- boolean (T,F) to decimal - - function L_To_d (Arg: string(1 to 1)) return integer is - begin - case Arg is when "T" => return(1); - when others => return(0); - end case; - end L_To_d; - - - - ---------------------------- - -- Hex conversion support -- - ---------------------------- - - -- Constants & types - - constant C_HEX_CHARS: string(1 to 17) := "0123456789ABCDEF?"; - - -- Function to return Hex index of a nibble - - function U_To_h_Index(Arg: string(4 downto 1)) return integer is - variable Index: integer := 0; - begin - for i in Arg'range loop - case Arg(i) is when '1' => Index := 2**(i-1) + Index; - when '0' => null; - when others => return (17); - end case; - end loop; - return (Index+1); - end U_To_h_Index; - - -- Hex conversion - - function U_To_h (Arg: string) return string is - variable Result: string((Arg'length-1)/4 +1 downto 1); - variable ExtArg: string(Result'length*4 downto 1) := (others => '0'); - begin - ExtArg(Arg'length downto 1) := Arg; - for i in Result'range loop - Result(i) := C_HEX_CHARS(U_To_h_Index( ExtArg(i*4 downto i*4 -3) )); - end loop; - return (FIO_h_PRE & Result & FIO_h_POST); - end U_To_h; - - - - ---------------------------- - -- Bit conversion support -- - ---------------------------- - - function L_To_b (Arg: string(1 to 1)) return string is - variable Result: string(1 to 1); - begin - case Arg is when "T" => Result := "1"; - when others => Result := "0"; - end case; - return(FIO_b_PRE & Result & FIO_b_POST); - end L_To_b; - - - function I_To_b (Arg: string(1 to FIO_d_WIDTH+1); - Justified: side; - Width: integer) return string is - - variable IntValue: integer := I_To_d(Arg); - variable BitValue: string(1 to FIO_b_WIDTH) := (others => ' '); - variable Sign: character := ' '; - constant Blanks: string(1 to FIO_b_WIDTH) := (others => ' '); - variable BitWidth: integer range 0 to FIO_b_WIDTH; - variable MsPos: integer range 1 to BitValue'length; - variable BitValueExtended: string(1 to 2*FIO_b_WIDTH); - - begin - - if (IntValue < 0) then - Sign := '-'; - IntValue := -IntValue; - end if; - - for i in BitValue'reverse_range loop - BitValue(i) := C_DIGITS_MAP(IntValue mod 2); - IntValue := IntValue / 2; - exit when (IntValue = 0); - end loop; - - BitValueExtended := BitValue & Blanks; - - if (Width = 0) or (Width > FIO_b_WIDTH+1) then - BitWidth := FIO_b_WIDTH; - else - BitWidth := Width-1; - end if; - - if (Justified = RIGHT) then - return (FIO_bv_PRE & - Sign & BitValue(BitValue'length-BitWidth+1 to BitValue'length) & - FIO_bv_POST); - else - for i in BitValue'range loop - if BitValue(i) /= ' ' then - MSPos := i; - exit; - end if; - end loop; - return (FIO_bv_PRE & - Sign & BitValueExtended(MSPos to MSPos+BitWidth-1) & - FIO_bv_POST); - end if; - - end I_To_b; - - - ----------------------------------- - -- Reasonable conversion support -- - ----------------------------------- - - function I_To_r (Arg: string(1 to FIO_d_WIDTH+1); - Justified: side; - Width: integer) return string is - constant Value: string(1 to FIO_d_WIDTH) := Arg(2 to FIO_d_WIDTH+1); - constant Sign: character := Arg(1); - constant Blanks: string(1 to FIO_d_WIDTH) := (others => ' '); - variable IntWidth: integer range 0 to FIO_d_WIDTH; - variable MsPos: integer range 1 to Value'length; - variable ValueExtended: string(1 to 2*FIO_d_WIDTH) := Value & Blanks; - begin - if (Width = 0) or (Width > FIO_d_WIDTH+1) then - IntWidth := FIO_d_WIDTH; - else - IntWidth := Width-1; - end if; - if (Justified = RIGHT) then - return (Sign & Value(Value'length-IntWidth+1 to Value'length)); - else - for i in Value'range loop - if Value(i) /= ' ' then - MSPos := i; - exit; - end if; - end loop; - return (Sign & ValueExtended(MSPos to MSPos+IntWidth-1)); - end if; - end I_To_r; - - - ------------------------------------------- - -- Reasonable output conversion function -- - ------------------------------------------- - - function ReasonableOutput (Arg: string; - Justified: side; - Width: integer) return string is - constant Argument: string(1 to Arg'length) := Arg; - constant TypeSpec: string (1 to 2) := Argument(1 to 2); - constant Value: string(1 to Arg'length-2) := Argument(3 to Arg'length); - begin - case TypeSpec is - when "U:" | "S:" | "V:" => - return U_To_h(Value); - when "I:" => - return I_To_r(Value, Justified, Width); - when "B:" | "L:" | "C:" => - return Value; - when others => - return Argument; - end case; - - end ReasonableOutput; - - - ------------------------------------ - -- Bit output conversion function -- - ------------------------------------ - - function BitOutput (Arg: string; - Justified: side; - Width: integer) return string is - constant Argument: string(1 to Arg'length) := Arg; - constant TypeSpec: string (1 to 2) := Argument(1 to 2); - constant Value: string(1 to Arg'length-2) := Argument(3 to Arg'length); - begin - case TypeSpec is - when "U:" | "S:" | "V:" => - return (FIO_bv_PRE & Value & FIO_bv_POST); - when "B:" => - -- Value(1 to 1) instead of Value for LeapFrog - return (FIO_b_PRE & Value(1 to 1) & FIO_b_POST); - when "I:" => - return I_To_b(Value, Justified, Width); - when "L:" => - -- Value(1 to 1) instead of Value for LeapFrog - return L_To_b(Value(1 to 1)); - when others => - return Argument; - end case; - - end BitOutput; - - - ------------------------------------------- - -- Decimal output conversion function -- - ------------------------------------------- - - function DecimalOutput (Arg: string) return integer is - constant Argument: string(1 to Arg'length) := Arg; - constant TypeSpec: string (1 to 2) := Argument(1 to 2); - constant Value: string(1 to Arg'length-2) := Argument(3 to Arg'length); - begin - case TypeSpec is - when "U:"| "V:" => - return U_To_d(Value); - when "S:" => - return S_To_d(Value); - when "I:" => - return I_To_d(Value); - when "B:" => - return B_To_d(Value); - when "L:" => - return L_To_d(Value); - when others => - return integer'low; - end case; - - end DecimalOutput; - - - ---------------------------- - -- Atomic print functions -- - ---------------------------- - - -- test for end of format string - - function FIO_EOS (Format: in string; - Pointer: in integer) - return boolean is - begin - return (Pointer > Format'length); - end FIO_EOS; - - - -- Atomic value print function - - procedure FIO_PrintValue (file F: text; - L: inout line; - Format: in string; - Pointer: inout integer; - Last: in boolean := FALSE) is - variable Char: character; - begin - while (not FIO_EOS(Format, Pointer)) loop - Char := Format(Pointer); - case Char is - when '\' => - Pointer := Pointer + 1; - exit when (FIO_EOS(Format, Pointer)); - Char := Format(Pointer); - case Char is when 'n' => writeline(F, L); - when others => write(L, Char); - end case; - when '%' => - if Last then - FIO_Warning_Fsbla(F, L, Format, Pointer); - end if; - Pointer := Pointer + 1; - exit; - when others => - write(L, char); - end case; - Pointer := Pointer + 1; - end loop; - end FIO_PrintValue; - - - ---- Atomic argument print function - - procedure FIO_PrintArg (file F: text; - L: inout line; - Format: in string; - Pointer: inout integer; - Arg: in string) is - variable Char: character; - variable Justified: side; - variable Width: integer; - - begin - - FIO_PrintValue(F, L, Format, Pointer); - - Justified := RIGHT; - Width := 0; - while (not FIO_EOS(Format, Pointer)) loop - Char := Format(Pointer); - case Char is - when '-' => - Justified := LEFT; - Pointer := Pointer + 1; - when '0' to '9' => - Width := Width*10 + C_DIGIT_CHARS_MAP(Char); - Pointer := Pointer + 1; - when 'r' => - write(L, ReasonableOutput(Arg, Justified, Width), Justified, Width); - Pointer := Pointer + 1; - exit; - when 'b' => - write(L, BitOutput(Arg, Justified, Width), Justified, Width); - Pointer := Pointer + 1; - exit; - when 'd' => - write(L, DecimalOutput(Arg), Justified, Width); - Pointer := Pointer + 1; - exit; - when 'q' | 's' => - write(L, Arg, Justified, Width); - Pointer := Pointer + 1; - exit; - when others => - FIO_Warning_Ufs(F, L, Format, Pointer, Char); - write(L, Arg, Justified, Width); - Pointer := Pointer + 1; - exit; - end case; - end loop; - end FIO_PrintArg; - - - ----------------------------------------------------- - -- The format string iteration expansion procedure -- - ----------------------------------------------------- - - procedure FIO_FormatExpand (FMT: inout line; - Format: in string; - StartPointer: in positive) is - - variable Pointer: positive := StartPointer; - variable TokenStart: positive; - variable IterStringStart: positive; - variable IterStringEnd: positive; - variable IterCount: natural; - variable OpenBrackets: natural; - variable L: line; - - begin - - FORMAT_SEARCH: while not FIO_EOS(Format, Pointer) loop - - case Format(Pointer) is - - -- look for format specifier - when '%' => - - -- initialize iteration token search - TokenStart := Pointer; - IterCount := 0; - Pointer := Pointer + 1; - - -- start iteration token search - TOKEN_READ: while not FIO_EOS(Format, Pointer) loop - - case Format(Pointer) is - - -- read iteration counter - when '0' to '9' => - IterCount := IterCount*10 + C_DIGIT_CHARS_MAP(Format(Pointer)); - Pointer := Pointer + 1; - - -- expect open bracket - when '{' => - - -- initialize iteration string read - OpenBrackets := 1; - IterStringStart := Pointer + 1; - Pointer := Pointer + 1; - -- quit prematurely when iteration count is 0 - next FORMAT_SEARCH when (IterCount = 0); - - -- start iteration string read - ITER_STRING_READ: while not FIO_EOS(Format, Pointer) loop - - case Format(Pointer) is - -- keep track of open brackets - when '{' => - OpenBrackets := OpenBrackets + 1; - Pointer := Pointer + 1; - -- when closing bracket is found, process iteration string - when '}' => - OpenBrackets := OpenBrackets - 1; - if (OpenBrackets = 0) then - IterStringEnd := Pointer-1; - if (TokenStart /= 1) then - write(L, Format(1 to TokenStart-1)); - end if; - for i in 1 to IterCount loop - write(L, Format(IterStringStart to IterStringEnd)); - end loop; - if (IterStringEnd /= Format'length) then - write(L, Format(IterStringEnd+2 to Format'length)); - end if; - -- call expansion procedure recursively on expanded format - FIO_FormatExpand(FMT, L.all, TokenStart); - deallocate(L); - return; - end if; - Pointer := Pointer + 1; - -- skip escaped characters - when '\' => - Pointer := Pointer + 2; - -- read iteration string - when others => - Pointer := Pointer + 1; - - end case; - - end loop ITER_STRING_READ; - - -- stop iteration token search when no opening bracket found - when others => - Pointer := Pointer + 1; - next FORMAT_SEARCH; - - end case; - - end loop TOKEN_READ; - - -- skip escaped characters - when '\' => - Pointer := Pointer + 2; - - -- read other characters - when others => - Pointer := Pointer + 1; - - end case; - - end loop FORMAT_SEARCH; - - write(FMT, Format); - deallocate(L); - - end FIO_FormatExpand; - - - - -------------------------- - -- The fprint procedure -- - -------------------------- - - procedure fprint - (file F: text; - L: inout line; - Format: in string; - A1 , A2 , A3 , A4 , A5 , A6 , A7 , A8 : in string := FIO_NIL; - A9 , A10, A11, A12, A13, A14, A15, A16: in string := FIO_NIL; - A17, A18, A19, A20, A21, A22, A23, A24: in string := FIO_NIL; - A25, A26, A27, A28, A29, A30, A31, A32: in string := FIO_NIL - ) is - - variable Pointer: integer; - variable FMT: line; - - begin - - Pointer := 1; - - FIO_FormatExpand (FMT, Format, Format'low); - - if (A1 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A1 ); - if (A2 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A2 ); - if (A3 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A3 ); - if (A4 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A4 ); - if (A5 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A5 ); - if (A6 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A6 ); - if (A7 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A7 ); - if (A8 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A8 ); - if (A9 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A9 ); - if (A10 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A10); - if (A11 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A11); - if (A12 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A12); - if (A13 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A13); - if (A14 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A14); - if (A15 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A15); - if (A16 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A16); - if (A17 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A17); - if (A18 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A18); - if (A19 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A19); - if (A20 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A20); - if (A21 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A21); - if (A22 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A22); - if (A23 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A23); - if (A24 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A24); - if (A25 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A25); - if (A26 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A26); - if (A27 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A27); - if (A28 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A28); - if (A29 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A29); - if (A30 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A30); - if (A31 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A31); - if (A32 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A32); - end if; end if; end if; end if; end if; end if; end if; end if; - end if; end if; end if; end if; end if; end if; end if; end if; - end if; end if; end if; end if; end if; end if; end if; end if; - end if; end if; end if; end if; end if; end if; end if; end if; - - FIO_PrintValue(F, L, FMT.all, Pointer, Last => TRUE); - - deallocate(FMT); - - end fprint; - - - ------------------------------------------- - -- Formatted output conversion functions -- - ------------------------------------------- - - function fo (Arg: unsigned) return string is - constant Argument: unsigned(1 to Arg'length) := Arg; - variable Result: string(1 to Arg'length); - begin - for i in Argument'range loop - Result(i) := C_STD_LOGIC_MAP(Argument(i)); - end loop; - return ("U:" & Result); - end fo; - - function fo (Arg: signed) return string is - constant Argument: signed(1 to Arg'length) := Arg; - variable Result: string(1 to Arg'length); - begin - for i in Argument'range loop - Result(i) := C_STD_LOGIC_MAP(Argument(i)); - end loop; - return ("S:" & Result); - end fo; - - function fo (Arg: std_logic_vector) return string is - constant Argument: std_logic_vector(1 to Arg'length) := Arg; - variable Result: string(1 to Arg'length); - begin - for i in Argument'range loop - Result(i) := C_STD_LOGIC_MAP(Argument(i)); - end loop; - return ("V:" & Result); - end fo; - - function fo (Arg: std_ulogic_vector) return string is - constant Argument: std_ulogic_vector(1 to Arg'length) := Arg; - variable Result: string(1 to Arg'length); - begin - for i in Argument'range loop - Result(i) := C_STD_LOGIC_MAP(Argument(i)); - end loop; - return ("V:" & Result); - end fo; - - function fo (Arg: bit_vector) return string is - constant Argument: bit_vector(1 to Arg'length) := Arg; - variable Result: string(1 to Arg'length); - begin - for i in Argument'range loop - Result(i) := C_BIT_MAP(Argument(i)); - end loop; - return ("V:" & Result); - end fo; - - function fo (Arg: integer) return string is - variable Argument: integer := Arg; - variable Result: string(1 to FIO_d_WIDTH) := (others => ' '); - variable Sign: character := ' '; - begin - if (Argument < 0) and (Argument /= integer'low) then - Sign := '-'; - Argument := -Argument; - end if; - for i in Result'reverse_range loop - Result(i) := C_DIGITS_MAP(Argument mod 10); - Argument := Argument / 10; - exit when (Argument = 0); - end loop; - return ("I:" & Sign & Result); - end fo; - - function fo (Arg: std_ulogic) return string is - begin - return ("B:" & C_STD_LOGIC_MAP(Arg)); - end fo; - - function fo (Arg: bit) return string is - begin - return ("B:" & C_BIT_MAP(Arg)); - end fo; - - function fo (Arg: boolean) return string is - begin - if (ARG = TRUE) then - return ("L:T"); - else - return ("L:F"); - end if; - end fo; - - function fo (Arg: character) return string is - begin - return ("C:" & Arg); - end fo; - - -- auxilary function fgets(Arg :string) - -- returns index of first NUL in Arg or if no NUL is present just Arg'length - -- goes through Arg from 1 to Arg'length - function fgets (Arg: string) return integer is - variable index: integer := Arg'length; - begin - for i in 1 to Arg'length loop - if Arg(i) = NUL then - index := i - 1; - exit; - else - null; - end if; - end loop; - return index; - end fgets; - - -- returns the Arg string until the first NUL was encountered - -- if fo is used on a string with NUL in it it will stop reading the rest - -- of the string, even if a larger field width has been supplied. fo will - -- then just pad the remaining characters with blanco's - function fo (Arg: string) return string is - begin - return Arg(1 to fgets(Arg)); - end fo; - - function fo (Arg: time) return string is - begin - return fo (integer (Arg / 1 ns)); - end fo; - -end PCK_FIO; - diff --git a/lib/PCK_FIO-2002.7/README b/lib/PCK_FIO-2002.7/README deleted file mode 100644 index b16c6c5..0000000 --- a/lib/PCK_FIO-2002.7/README +++ /dev/null @@ -1,88 +0,0 @@ ----- $Id: README,v 1.1 2008-08-23 08:20:28 Jens Exp $ ----- ----- PCK_FIO: a VHDL package for C-style formatted file output ----- Copyright (C) 1995, 2001 Easics NV ----- ----- This library is free software; you can redistribute it and/or ----- modify it under the terms of the GNU Lesser General Public ----- License as published by the Free Software Foundation; either ----- version 2.1 of the License, or (at your option) any later version. ----- ----- This library is distributed in the hope that it will be useful, ----- but WITHOUT ANY WARRANTY; without even the implied warranty of ----- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ----- Lesser General Public License for more details. ----- ----- You should have received a copy of the GNU Lesser General Public ----- License along with this library; if not, write to the Free Software ----- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----- ----- For suggestions, bug reports, enhancement requests, and info about ----- our design services, you can contact us at the following address: ----- http://www.easics.com ----- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium ----- tel.: +32 16 395 600 fax : +32 16 395 619 ----- e-mail: jand@easics.be (Jan Decaluwe) ----- - -Version 2002.07 -=============== - -Contents -======== - -This distribution contains the following files: - - PCK_FIO_1987.vhd: VHDL-87 source of the header of the PCK_FIO package - PCK_FIO_1987_BODY.vhd: VHDL-87 source of the body of the PCK_FIO package - PCK_FIO_1993.vhd: VHDL-93 source of the header of the PCK_FIO package - PCK_FIO_1993_BODY.vhd: VHDL-93 source of the body of the PCK_FIO package - TB_PCK_FIO_1987.vhd: VHDL-87 source of the testbench for package PCK_FIO - TB_PCK_FIO_1993.vhd: VHDL-93 source of the testbench for package PCK_FIO - PCK_FIO.out.gold: Certified test bench output - PCK_FIO.html: Manual for PCK_FIO in html format - README: This file - - -Installation -============ - -VHDL-1987 ---------- -To install PCK_FIO, define a VHDL library called EASICS_PACKAGES, and -analyze the VHDL file PCK_FIO_1987.vhd and PCK_FIO_1987_BODY.vhd into this library. - -To install the test bench, analyze TB_PCK_FIO_1987.vhd into the same library. - -VHDL-1993 ---------- -To install PCK_FIO, define a VHDL library called EASICS_PACKAGES, and -analyze the VHDL file PCK_FIO_1993.vhd and PCK_FIO_1993_BODY.vhd into this library. - -To install the test bench, analyze TB_PCK_FIO_1993.vhd into the same library. - -Numeric packages ----------------- -If you want to use IEEE.std_logic_arith instead of IEEE.numeric_std, you need -to edit the source code of the package, both header and body, and the test bench -and replace the package use clause. PCK_FIO works with either of these packages. - -Documentation -------------- -To install the documentation, put the file point PCK_FIO.html in a path of -your choosing, point your web browser to it, and bookmark it. - - -Installation check -================== - -After installing the test bench, you should run it. The corresponding VHDL -design unit is EASICS_PACKAGES.TBE_PCK_FIO(TB). - -Simulating the test bench should create a file called PCK_FIO.out. This file -should be identical to PCK_FIO.out.gold. Any difference indicates a portability -issue or a simulator non-compliance or bug. - - - - diff --git a/lib/PCK_FIO-2002.7/TB_PCK_FIO_1987.vhd b/lib/PCK_FIO-2002.7/TB_PCK_FIO_1987.vhd deleted file mode 100644 index 2e18ff4..0000000 --- a/lib/PCK_FIO-2002.7/TB_PCK_FIO_1987.vhd +++ /dev/null @@ -1,531 +0,0 @@ ----- $Id: TB_PCK_FIO_1987.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $ ----- ----- PCK_FIO: a VHDL package for C-style formatted file output ----- Copyright (C) 1995, 2001 Easics NV ----- ----- This library is free software; you can redistribute it and/or ----- modify it under the terms of the GNU Lesser General Public ----- License as published by the Free Software Foundation; either ----- version 2.1 of the License, or (at your option) any later version. ----- ----- This library is distributed in the hope that it will be useful, ----- but WITHOUT ANY WARRANTY; without even the implied warranty of ----- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ----- Lesser General Public License for more details. ----- ----- You should have received a copy of the GNU Lesser General Public ----- License along with this library; if not, write to the Free Software ----- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----- ----- For suggestions, bug reports, enhancement requests, and info about ----- our design services, you can contact us at the following address: ----- http://www.easics.com ----- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium ----- tel.: +32 16 395 600 fax : +32 16 395 619 ----- e-mail: jand@easics.be (Jan Decaluwe) ----- - - -library IEEE; -use IEEE.std_logic_1164.all; --- signed/unsigned definition: use either std_logic_arith or numeric_std --- use IEEE.std_logic_arith.all; -- the Synopsys one - use IEEE.numeric_std.all; - -use STD.TEXTIO.all; - -library EASICS_PACKAGES; -use EASICS_PACKAGES.PCK_FIO.all; - -entity TBE_PCK_FIO is - -end TBE_PCK_FIO; - -architecture TB of TBE_PCK_FIO is - -begin - -USAGE: process - - file RESULT: text is out "PCK_FIO.out"; - variable L: line; - variable Pointer: integer; - variable BoolTrue: boolean := TRUE; - variable BoolFalse: boolean := FALSE; - variable IntPos: integer := 5678; - variable BigIntPos: integer := 12345678; - variable IntNeg: integer := -8765; - variable BigIntNeg: integer := -87654321; - variable Uns: unsigned(6 downto 0) := unsigned'("1010010"); - variable Unk: unsigned(6 downto 0) := unsigned'("1X10Z10"); - variable Std: std_logic_vector(6 downto 0) := std_logic_vector'("0010010"); - variable SigPos: signed(6 downto 0) := signed'("0010010"); - variable SigNeg: signed(6 downto 0) := signed'("1010010"); - variable BitX: std_logic := 'X'; - variable Bit1: std_logic := '1'; - variable Bit0: std_logic := '0'; - - variable parameter_1: integer := 1234; - variable parameter_2: integer := 2345; - variable parameter_3: integer := 4567; - - constant TempString: string :="ABC" & NUL & "DEF"; -begin - -fprint(RESULT, L, - "PCK_FIO.out: TESTBENCH OUTPUT FOR PCK_FIO\n" & - "-----------------------------------------\n\n" & - "This is the result of running the PCK_FIO testbench.\n" & - "This file should be compared with PCK_FIO.out.gold, which is\n" & - "the reference output. Any difference indicates a portability\n" & - "issue or a simulator non-compliance or bug.\n\n" - ); - - -fprint(RESULT, L, - "\n--------------------\n" & - "-- Basic features --\n" & - "--------------------\n\n" - ); - -fprint(RESULT, L, - "-- First some auxiliary declarations\n" - ); - -fprint(RESULT, L, - "> file RESULT: text is out ""PCK_FIO.out"";\n" & - "> variable L: line;\n" & - "> variable BoolTrue: boolean := TRUE;\n" & - "> variable BoolFalse: boolean := FALSE;\n" & - "> variable IntPos: integer := 5678;\n" & - "> variable BigIntPos: integer := 12345678;\n" & - "> variable IntNeg: integer := -8765;\n" & - "> variable BigIntNeg: integer := -87654321;\n" & - "> variable Uns: unsigned(6 downto 0) := unsigned'(""1010010"");\n" & - "> variable Unk: unsigned(6 downto 0) := unsigned'(""1X10Z10"");\n" & - "> variable Std: std_logic_vector(6 downto 0) := std_logic_vector'(""0010010"");\n" & - "> variable SigPos: signed(6 downto 0) := signed'(""0010010"");\n" & - "> variable SigNeg: signed(6 downto 0) := signed'(""1010010"");\n" & - "> variable BitX: std_logic := 'X';\n" & - "> variable Bit1: std_logic := '1';\n" & - "> variable Bit0: std_logic := '0';\n" & - "> constant TempString: string := ""ABC"" & NUL & ""DEF"";\n" -); - - -fprint(RESULT, L, - "\n\n-- fprint call with no arguments\n" & - "> fprint(RESULT, L, ""No arguments.\\n"");\n" - ); -fprint(RESULT, L, "No arguments.\n"); - - -fprint(RESULT, L, - "\n-- Special characters need to be escaped\n" & - "> fprint(RESULT, L, ""Special characters: \\\% \\\\ "" \\n"");\n" - ); - -fprint(RESULT, L, "Special characters: \% \\ "" \n"); - - -fprint(RESULT, L, - "\n-- Various format specifiers interprete the same object differently\n" & - "> fprint(RESULT, L, ""Format specifiers: \%r \%d \%b \%q\\n"",\n" & - "> fo(Uns), fo(Uns), fo(Uns), fo(Uns)\n" & - "> );\n" - ); - -fprint(RESULT, L, "Format specifiers: %r %d %b %q\n", - fo(Uns), fo(Uns), fo(Uns), fo(Uns) - ); - -fprint(RESULT, L, - "\n-- Format string can be shortened by using the iteration specifier\n" & - "> fprint(RESULT, L, ""Iteration specifier: \%4{\%r }\\n"",\n" & - "> fo(Uns), fo(SigPos), fo(SigNeg), fo(Std)\n" & - "> );\n" - ); - -fprint(RESULT, L, "Iteration specifier: %4{%r }\n", - fo(Uns), fo(SigPos), fo(SigNeg), fo(Std) - ); -fprint(RESULT, L, - "\n-------------------------------\n"& - "--Testing string manipulation--\n"& - "-------------------------------\n"); -fprint(RESULT, L, "--testing done using the string TempString : " & """ABC""" - & " & NUL & ""DEF""\n"); --- temp_string: string:="ABC"&NUL&"DEF" --- test for detecting NUL in string -fprint(RESULT, L, "\n--test for NUL ending in strings\n"); -fprint(RESULT, L, "> fprint(RESULT, L, fo(TempString));\n"); -fprint(RESULT, L, fo(TempString)); - --- direct inclusion of string in fprint should give whole string -fprint(RESULT, L, "\n--same without fo,so without NUL testing\n"); -fprint(RESULT, L, "> fprint(RESULT, L, TempString);\n"); -fprint(RESULT, L, TempString & "\n"); - --- influence of given width - -fprint(RESULT, L, "\n--if there are less characters in the given string then" - & " in the width fo will\n"& - "-- pad the remaining with blanco's according to the given justification\n"); -fprint(RESULT, L, "\n--with specified width, justified right,using fo\n"); -fprint(RESULT, L, "> fprint(RESULT, L, ""\%5s"", fo(TempString));\n"); -fprint(RESULT, L, "%5s", fo(TempString)); -fprint(RESULT, L, "\n--with specified width, justified left, using fo\n"); -fprint(RESULT, L, "> fprint(RESULT, L, ""\%-5s"", fo(TempString));\n"); -fprint(RESULT, L, "%-5s",fo(TempString)); -fprint(RESULT, L, "\n--with specified width without fo\n"); -fprint(RESUlT, L, "> fprint(RESULT, L, ""\%9s"", TempString);\n"); -fprint(RESULT, L, "%9s", TempString); -fprint(RESULT, L, "\n\n-- if the width is smaller then the number" & - " of characters in the string fprint\n" & - "-- will output the string with the minimum of characters needed\n"); -fprint(RESULT, L, "\n--with specified width,using fo\n"); -fprint(RESULT, L, "> fprint(RESULT, L, ""\%2s"", fo(TempString));\n"); -fprint(RESULT, L, "%2s",fo(TempString)); -fprint(RESULT, L, "\n--with specified width without fo\n"); -fprint(RESUlT, L, "> fprint(RESULT, L, ""\%4s"", TempString);\n"); -fprint(RESULT, L, "%4s", TempString); - - -fprint(RESULT, L, - "\n\n------------------------------------\n" & - "-- Support for bit-oriented types --\n" & - "------------------------------------\n" - ); - -fprint (RESULT, L, "\n-- Reasonable format\n" & - "> fprint(RESULT, L, ""Reasonable format: \%9{\%r }\\n"",\n" & - "> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),\n" & - "> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) \n" & - "> );\n" - ); - - -fprint(RESULT, L, "Reasonable format: %9{%r }\n", - fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk), - fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) - ); - -fprint (RESULT, L, "\n-- Decimal format\n" & - "> fprint(RESULT, L, ""Decimal format: \%7{\%d }\\n"",\n" & - "> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),\n" & - "> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) \n" & - "> );\n" - ); - - -fprint(RESULT, L, "Decimal format: %9{%d }\n", - fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk), - fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) - ); - -fprint (RESULT, L, "\n-- Bit format\n" & - "> fprint(RESULT, L, ""Bit format: \%7{\%b }\\n"",\n" & - "> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),\n" & - "> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) \n" & - "> );\n" - ); - - -fprint(RESULT, L, "Bit format: %9{%b }\n", - fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk), - fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) - ); - -fprint(RESULT, L, - "\n\n" & - "-- Alignment\n-- Template of the call: ( stands for the format specifier)\n" - ); - - -fprint(RESULT, L, "\n" & - "> fprint(RESULT, L, ""Bitvectors with : \%4{|}\\n"",\n" & - "> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg)\n" & - - "> );\n" - ); - -fprint(RESULT, L, - "\n" & - "-- Results of the call with various format specifiers\n\n" - ); - -fprint(RESULT, L, "Bitvectors with \%1r: %4{%1r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%2r: %4{%2r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%3r: %4{%3r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%4r: %4{%4r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%5r: %4{%5r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%6r: %4{%6r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%7r: %4{%7r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%8r: %4{%8r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%9r: %4{%9r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "\n"); -fprint(RESULT, L, "Bitvectors with \%-1r: %4{%-1r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-2r: %4{%-2r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-3r: %4{%-3r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-4r: %4{%-4r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-5r: %4{%-5r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-6r: %4{%-6r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-7r: %4{%-7r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-8r: %4{%-8r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-9r: %4{%-9r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "\n"); -fprint(RESULT, L, "Bitvectors with \%1d: %4{%1d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%2d: %4{%2d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%3d: %4{%3d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%4d: %4{%4d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%5d: %4{%5d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%6d: %4{%6d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%7d: %4{%7d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%8d: %4{%8d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%9d: %4{%9d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "\n"); -fprint(RESULT, L, "Bitvectors with \%-1d: %4{%-1d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-2d: %4{%-2d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-3d: %4{%-3d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-4d: %4{%-4d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-5d: %4{%-5d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-6d: %4{%-6d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-7d: %4{%-7d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-8d: %4{%-8d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-9d: %4{%-9d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "\n"); - - - -fprint(RESULT, L, - "\n-------------------------------\n" & - "-- Support for integer types --\n" & - "-------------------------------\n" - ); - -fprint(RESULT, L, - "\n\n" & - "-- Template of the call: ( stands for the format specifier)\n" - ); - - -fprint(RESULT, L, "\n" & - "> fprint(RESULT, L, ""Integers with : \%4{|}\\n"",\n" & - "> fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)\n" & - - "> );\n" - ); - -fprint(RESULT, L, - "\n" & - "-- Results of the call with various format specifiers\n\n" - ); - - -fprint(RESULT, L, "Integers with \%5d: %4{%5d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%6d: %4{%6d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%7d: %4{%7d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%8d: %4{%8d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%9d: %4{%9d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%10d: %4{%10d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "\n"); -fprint(RESULT, L, "Integers with \%-5d: %4{%-5d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-6d: %4{%-6d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-7d: %4{%-7d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-8d: %4{%-8d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-9d: %4{%-9d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-10d: %4{%-10d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "\n"); -fprint(RESULT, L, "Integers with \%5r: %4{%5r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%6r: %4{%6r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%7r: %4{%7r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%8r: %4{%8r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%9r: %4{%9r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%10r: %4{%10r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "\n"); -fprint(RESULT, L, "Integers with \%-5r: %4{%-5r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-6r: %4{%-6r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-7r: %4{%-7r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-8r: %4{%-8r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-9r: %4{%-9r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-10r: %4{%-10r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "\n"); - - -fprint(RESULT, L, - "\n----------------------\n" & - "-- Support for time --\n" & - "----------------------\n" - ); - -fprint (RESULT, L, "-- For portability reasons, time is converted \n" & - "-- into an integer value (of nanoseconds)\n" - ); -fprint (RESULT, L, "> wait for 648 ns\n"); -fprint (RESULT, L, "> fprint (RESULT, L, ""The time is now \%d ns\\n"", fo(now));\n"); - -wait for 648 ns; - -fprint (RESULT, L, "The time is now %d ns\n", fo(now)); - - -fprint(RESULT, L, - "\n----------------------------------------\n" & - "-- Erroneous calls and error messages --\n" & - "----------------------------------------\n" - ); - -fprint(RESULT, L, "\n-- Less arguments than formats specifiers\n" & - "> fprint(RESULT, L, ""\%d \%d \%d \%d \\n"", fo(Uns), fo(Std));\n" - ); - -fprint(RESULT, L, "%d %d %d %d \n", fo(Uns), fo(Std)); - -fprint(RESULT, L, "\n"); - -fprint(RESULT, L, "-- Unsupported format specifier\n" & - "> fprint(RESULT, L, ""\%r \%v \%r \%r\\n"", " & - "fo(Uns), fo(Std), fo(Uns), fo(Std));\n" - ); - -fprint(RESULT, L, "%r %v %r %r\n", fo(Uns), fo(Std), fo(Uns), fo(Std)); - -fprint(RESULT, L, "\n"); - -fprint(RESULT, L, - "\n----------------------------------------\n" & - "-- Things you wouldn't expect to work --\n" & - "----------------------------------------\n" - ); - -fprint(RESULT, L, "\n-- Nested iteration\n"); -fprint(RESULT, L, "> fprint(RESULT, L, ""\%3{<<\%3{_END_}>>}\\n"");\n"); -fprint(RESULT, L, "%3{<<%3{_END_}>>}\n"); - -wait; - -end process USAGE; - -end TB; - - diff --git a/lib/PCK_FIO-2002.7/TB_PCK_FIO_1993.vhd b/lib/PCK_FIO-2002.7/TB_PCK_FIO_1993.vhd deleted file mode 100644 index 0386a11..0000000 --- a/lib/PCK_FIO-2002.7/TB_PCK_FIO_1993.vhd +++ /dev/null @@ -1,536 +0,0 @@ ----- $Id: TB_PCK_FIO_1993.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $ ----- ----- PCK_FIO: a VHDL package for C-style formatted file output ----- Copyright (C) 1995, 2001 Easics NV ----- ----- This library is free software; you can redistribute it and/or ----- modify it under the terms of the GNU Lesser General Public ----- License as published by the Free Software Foundation; either ----- version 2.1 of the License, or (at your option) any later version. ----- ----- This library is distributed in the hope that it will be useful, ----- but WITHOUT ANY WARRANTY; without even the implied warranty of ----- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ----- Lesser General Public License for more details. ----- ----- You should have received a copy of the GNU Lesser General Public ----- License along with this library; if not, write to the Free Software ----- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----- ----- For suggestions, bug reports, enhancement requests, and info about ----- our design services, you can contact us at the following address: ----- http://www.easics.com ----- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium ----- tel.: +32 16 395 600 fax : +32 16 395 619 ----- e-mail: jand@easics.be (Jan Decaluwe) ----- - - -library IEEE; -use IEEE.std_logic_1164.all; --- signed/unsigned definition: use either std_logic_arith or numeric_std --- use IEEE.std_logic_arith.all; -- the Synopsys one -use IEEE.numeric_std.all; - -use STD.TEXTIO.all; - -library EASICS_PACKAGES; -use EASICS_PACKAGES.PCK_FIO.all; - -entity TBE_PCK_FIO is - -end TBE_PCK_FIO; - -architecture TB of TBE_PCK_FIO is - -begin - -USAGE: process - - file RESULT: text open write_mode is "PCK_FIO.out"; - variable L: line; - variable Pointer: integer; - variable BoolTrue: boolean := TRUE; - variable BoolFalse: boolean := FALSE; - variable IntPos: integer := 5678; - variable BigIntPos: integer := 12345678; - variable IntNeg: integer := -8765; - variable BigIntNeg: integer := -87654321; - variable Uns: unsigned(6 downto 0) := unsigned'("1010010"); - variable Unk: unsigned(6 downto 0) := unsigned'("1X10Z10"); - variable Std: std_logic_vector(6 downto 0) := std_logic_vector'("0010010"); - variable SigPos: signed(6 downto 0) := signed'("0010010"); - variable SigNeg: signed(6 downto 0) := signed'("1010010"); - variable BitX: std_logic := 'X'; - variable Bit1: std_logic := '1'; - variable Bit0: std_logic := '0'; - - variable parameter_1: integer := 1234; - variable parameter_2: integer := 2345; - variable parameter_3: integer := 4567; - - constant TempString: string :="ABC" & NUL & "DEF"; -begin - -fprint(RESULT, L, - "PCK_FIO.out: TESTBENCH OUTPUT FOR PCK_FIO\n" & - "-----------------------------------------\n\n" & - "This is the result of running the PCK_FIO testbench.\n" & - "This file should be compared with PCK_FIO.out.gold, which is\n" & - "the reference output. Any difference indicates a portability\n" & - "issue or a simulator non-compliance or bug.\n\n" - ); - - -fprint(RESULT, L, - "\n--------------------\n" & - "-- Basic features --\n" & - "--------------------\n\n" - ); - -fprint(RESULT, L, - "-- First some auxiliary declarations\n" - ); - -fprint(RESULT, L, - "> file RESULT: text is out ""PCK_FIO.out"";\n" & - "> variable L: line;\n" & - "> variable BoolTrue: boolean := TRUE;\n" & - "> variable BoolFalse: boolean := FALSE;\n" & - "> variable IntPos: integer := 5678;\n" & - "> variable BigIntPos: integer := 12345678;\n" & - "> variable IntNeg: integer := -8765;\n" & - "> variable BigIntNeg: integer := -87654321;\n" & - "> variable Uns: unsigned(6 downto 0) := unsigned'(""1010010"");\n" & - "> variable Unk: unsigned(6 downto 0) := unsigned'(""1X10Z10"");\n" & - "> variable Std: std_logic_vector(6 downto 0) := std_logic_vector'(""0010010"");\n" & - "> variable SigPos: signed(6 downto 0) := signed'(""0010010"");\n" & - "> variable SigNeg: signed(6 downto 0) := signed'(""1010010"");\n" & - "> variable BitX: std_logic := 'X';\n" & - "> variable Bit1: std_logic := '1';\n" & - "> variable Bit0: std_logic := '0';\n" & - "> constant TempString: string := ""ABC"" & NUL & ""DEF"";\n" -); - - -fprint(RESULT, L, - "\n\n-- fprint call with no arguments\n" & - "> fprint(RESULT, L, ""No arguments.\\n"");\n" - ); -fprint(RESULT, L, "No arguments.\n"); - - -fprint(RESULT, L, - "\n-- Special characters need to be escaped\n" & - "> fprint(RESULT, L, ""Special characters: \\\% \\\\ "" \\n"");\n" - ); - -fprint(RESULT, L, "Special characters: \% \\ "" \n"); - - -fprint(RESULT, L, - "\n-- Various format specifiers interprete the same object differently\n" & - "> fprint(RESULT, L, ""Format specifiers: \%r \%d \%b \%q\\n"",\n" & - "> fo(Uns), fo(Uns), fo(Uns), fo(Uns)\n" & - "> );\n" - ); - -fprint(RESULT, L, "Format specifiers: %r %d %b %q\n", - fo(Uns), fo(Uns), fo(Uns), fo(Uns) - ); - -fprint(RESULT, L, - "\n-- Format string can be shortened by using the iteration specifier\n" & - "> fprint(RESULT, L, ""Iteration specifier: \%4{\%r }\\n"",\n" & - "> fo(Uns), fo(SigPos), fo(SigNeg), fo(Std)\n" & - "> );\n" - ); - -fprint(RESULT, L, "Iteration specifier: %4{%r }\n", - fo(Uns), fo(SigPos), fo(SigNeg), fo(Std) - ); -fprint(RESULT, L, - "\n-------------------------------\n"& - "--Testing string manipulation--\n"& - "-------------------------------\n"); -fprint(RESULT, L, "--testing done using the string TempString : " & """ABC""" - & " & NUL & ""DEF""\n"); --- TempString: string:="ABC" & NUL & "DEF" --- test for detecting NUL in string -fprint(RESULT, L ,"\n--test for NUL ending in strings\n"); -fprint(RESULT, L, "> fprint(RESULT, L, fo(TempString));\n"); -fprint(RESULT, L, fo(TempString)); - --- direct inclusion of string in fprint should give whole string -fprint(RESULT, L, "\n--same without fo,so without NUL testing\n"); -fprint(RESULT, L, "> fprint(RESULT, L, TempString);\n"); -fprint(RESULT, L, TempString & "\n"); - --- influence of given width - -fprint(RESULT, L, "\n--if there are less characters in the given string then in the width fo will\n"& - "-- pad the remaining with blanco's according to the given justification\n"); -fprint(RESULT, L, "\n--with specified width, justified right,using fo\n"); -fprint(RESULT, L, "> fprint(RESULT, L, ""\%5s"", fo(TempString));\n"); -fprint(RESULT, L, "%5s", fo(TempString)); -fprint(RESULT, L, "\n--with specified width, justified left, using fo\n"); -fprint(RESULT, L, "> fprint(RESULT, L, ""\%-5s"", fo(TempString));\n"); -fprint(RESULT, L, "%-5s", fo(TempString)); -fprint(RESULT, L, "\n--with specified width without fo\n"); -fprint(RESUlT, L, "> fprint(RESULT, L, ""\%9s"", TempString);\n"); -fprint(RESULT, L, "%9s", TempString); -fprint(RESULT, L, "\n\n-- if the width is smaller then the number of characters in the string fprint\n"& - "-- will output the string with the minimum of characters needed\n"); -fprint(RESULT, L, "\n--with specified width,using fo\n"); -fprint(RESULT, L, "> fprint(RESULT, L, ""\%2s"", fo(TempString));\n"); -fprint(RESULT, L, "%2s", fo(TempString)); -fprint(RESULT, L, "\n--with specified width without fo\n"); -fprint(RESUlT, L, "> fprint(RESULT, L, ""\%4s"", TempString);\n"); -fprint(RESULT, L, "%4s", TempString); - -fprint(RESULT, L, - "\n\n------------------------------------\n" & - "-- Support for bit-oriented types --\n" & - "------------------------------------\n" - ); - -fprint (RESULT, L, "\n-- Reasonable format\n" & - "> fprint(RESULT, L, ""Reasonable format: \%9{\%r }\\n"",\n" & - "> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),\n" & - "> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) \n" & - "> );\n" - ); - - -fprint(RESULT, L, "Reasonable format: %9{%r }\n", - fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk), - fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) - ); - -fprint (RESULT, L, "\n-- Decimal format\n" & - "> fprint(RESULT, L, ""Decimal format: \%7{\%d }\\n"",\n" & - "> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),\n" & - "> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) \n" & - "> );\n" - ); - - -fprint(RESULT, L, "Decimal format: %9{%d }\n", - fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk), - fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) - ); - -fprint (RESULT, L, "\n-- Bit format\n" & - "> fprint(RESULT, L, ""Bit format: \%7{\%b }\\n"",\n" & - "> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),\n" & - "> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) \n" & - "> );\n" - ); - - -fprint(RESULT, L, "Bit format: %9{%b }\n", - fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk), - fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) - ); - -fprint(RESULT, L, - "\n\n" & - "-- Alignment\n-- Template of the call: ( stands for the format specifier)\n" - ); - - -fprint(RESULT, L, "\n" & - "> fprint(RESULT, L, ""Bitvectors with : \%4{|}\\n"",\n" & - "> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg)\n" & - "> );\n" - ); - -fprint(RESULT, L, - "\n" & - "-- Results of the call with various format specifiers\n\n" - ); - -fprint(RESULT, L, "Bitvectors with \%1r: %4{%1r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%2r: %4{%2r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%3r: %4{%3r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%4r: %4{%4r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%5r: %4{%5r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%6r: %4{%6r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%7r: %4{%7r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%8r: %4{%8r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%9r: %4{%9r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "\n"); -fprint(RESULT, L, "Bitvectors with \%-1r: %4{%-1r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-2r: %4{%-2r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-3r: %4{%-3r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-4r: %4{%-4r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-5r: %4{%-5r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-6r: %4{%-6r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-7r: %4{%-7r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-8r: %4{%-8r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-9r: %4{%-9r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "\n"); -fprint(RESULT, L, "Bitvectors with \%1d: %4{%1d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%2d: %4{%2d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%3d: %4{%3d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%4d: %4{%4d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%5d: %4{%5d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%6d: %4{%6d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%7d: %4{%7d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%8d: %4{%8d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%9d: %4{%9d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "\n"); -fprint(RESULT, L, "Bitvectors with \%-1d: %4{%-1d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-2d: %4{%-2d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-3d: %4{%-3d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-4d: %4{%-4d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-5d: %4{%-5d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-6d: %4{%-6d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-7d: %4{%-7d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-8d: %4{%-8d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-9d: %4{%-9d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "\n"); - - - -fprint(RESULT, L, - "\n-------------------------------\n" & - "-- Support for integer types --\n" & - "-------------------------------\n" - ); - -fprint(RESULT, L, - "\n\n" & - "-- Template of the call: ( stands for the format specifier)\n" - ); - - -fprint(RESULT, L, "\n" & - "> fprint(RESULT, L, ""Integers with : \%4{|}\\n"",\n" & - "> fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)\n" & - - "> );\n" - ); - -fprint(RESULT, L, - "\n" & - "-- Results of the call with various format specifiers\n\n" - ); - - -fprint(RESULT, L, "Integers with \%5d: %4{%5d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%6d: %4{%6d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%7d: %4{%7d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%8d: %4{%8d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%9d: %4{%9d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%10d: %4{%10d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "\n"); -fprint(RESULT, L, "Integers with \%-5d: %4{%-5d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-6d: %4{%-6d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-7d: %4{%-7d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-8d: %4{%-8d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-9d: %4{%-9d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-10d: %4{%-10d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "\n"); -fprint(RESULT, L, "Integers with \%5r: %4{%5r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%6r: %4{%6r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%7r: %4{%7r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%8r: %4{%8r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%9r: %4{%9r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%10r: %4{%10r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "\n"); -fprint(RESULT, L, "Integers with \%-5r: %4{%-5r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-6r: %4{%-6r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-7r: %4{%-7r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-8r: %4{%-8r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-9r: %4{%-9r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-10r: %4{%-10r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "\n"); - - -fprint(RESULT, L, - "\n----------------------\n" & - "-- Support for time --\n" & - "----------------------\n" - ); - -fprint (RESULT, L, "-- For portability reasons, time is converted \n" & - "-- into an integer value (of nanoseconds)\n" - ); -fprint (RESULT, L, "> wait for 648 ns\n"); -fprint (RESULT, L, "> fprint (RESULT, L, ""The time is now \%d ns\\n"", fo(now));\n"); - -wait for 648 ns; - -fprint (RESULT, L, "The time is now %d ns\n", fo(now)); - - -fprint(RESULT, L, - "\n----------------------------------------\n" & - "-- Erroneous calls and error messages --\n" & - "----------------------------------------\n" - ); - -fprint(RESULT, L, "\n-- Less arguments than formats specifiers\n" & - "> fprint(RESULT, L, ""\%d \%d \%d \%d \\n"", fo(Uns), fo(Std));\n" - ); - -fprint(RESULT, L, "%d %d %d %d \n", fo(Uns), fo(Std)); - -fprint(RESULT, L, "\n"); - -fprint(RESULT, L, "-- Unsupported format specifier\n" & - "> fprint(RESULT, L, ""\%r \%v \%r \%r\\n"", " & - "fo(Uns), fo(Std), fo(Uns), fo(Std));\n" - ); - -fprint(RESULT, L, "%r %v %r %r\n", fo(Uns), fo(Std), fo(Uns), fo(Std)); - -fprint(RESULT, L, "\n"); - -fprint(RESULT, L, - "\n----------------------------------------\n" & - "-- Things you wouldn't expect to work --\n" & - "----------------------------------------\n" - ); - -fprint(RESULT, L, "\n-- Nested iteration\n"); -fprint(RESULT, L, "> fprint(RESULT, L, ""\%3{<<\%3{_END_}>>}\\n"");\n"); -fprint(RESULT, L, "%3{<<%3{_END_}>>}\n"); - -wait; - -end process USAGE; - -end TB; - - - - - - - - - - - diff --git a/lib/PCK_FIO-2002.7/msMakefile.TBE_PCK_FIO_TB.1987 b/lib/PCK_FIO-2002.7/msMakefile.TBE_PCK_FIO_TB.1987 deleted file mode 100644 index c5a4a92..0000000 --- a/lib/PCK_FIO-2002.7/msMakefile.TBE_PCK_FIO_TB.1987 +++ /dev/null @@ -1,34 +0,0 @@ -### msMakefile generated by vma on Thu Oct 4 17:33:56 CEST 2001 - -ANALYZER = vcom -quiet -nologo -ANALYZER_C = vcom -quiet -nologo -all : \ - bin/tbe_pck_fio/tb.dat \ - bin/tbe_pck_fio/_primary.dat - -# Prerequisites for architecture EASICS_PACKAGES.TBE_PCK_FIO(TB) -# Prerequisites for entity EASICS_PACKAGES.TBE_PCK_FIO - -bin/tbe_pck_fio/tb.dat \ -bin/tbe_pck_fio/_primary.dat : \ - bin/pck_fio/body.dat \ - bin/pck_fio/_primary.dat \ - TB_PCK_FIO_1987.vhd - ${ANALYZER_C} -work EASICS_PACKAGES TB_PCK_FIO_1987.vhd - - -# Prerequisites for package body EASICS_PACKAGES.PCK_FIO() - -bin/pck_fio/body.dat : \ - bin/pck_fio/_primary.dat \ - PCK_FIO_1987_BODY.vhd - ${ANALYZER_C} -work EASICS_PACKAGES PCK_FIO_1987_BODY.vhd - - -# Prerequisites for package declaration EASICS_PACKAGES.PCK_FIO - -bin/pck_fio/_primary.dat : \ - PCK_FIO_1987.vhd - ${ANALYZER} -work EASICS_PACKAGES PCK_FIO_1987.vhd - - diff --git a/lib/PCK_FIO-2002.7/msMakefile.TBE_PCK_FIO_TB.1993 b/lib/PCK_FIO-2002.7/msMakefile.TBE_PCK_FIO_TB.1993 deleted file mode 100644 index 0f9a351..0000000 --- a/lib/PCK_FIO-2002.7/msMakefile.TBE_PCK_FIO_TB.1993 +++ /dev/null @@ -1,34 +0,0 @@ -### msMakefile generated by vma on Thu Oct 4 17:32:23 CEST 2001 - -ANALYZER = vcom -quiet -nologo -93 -ANALYZER_C = vcom -quiet -nologo -93 -all : \ - bin/tbe_pck_fio/tb.dat \ - bin/tbe_pck_fio/_primary.dat - -# Prerequisites for architecture EASICS_PACKAGES.TBE_PCK_FIO(TB) -# Prerequisites for entity EASICS_PACKAGES.TBE_PCK_FIO - -bin/tbe_pck_fio/tb.dat \ -bin/tbe_pck_fio/_primary.dat : \ - bin/pck_fio/body.dat \ - bin/pck_fio/_primary.dat \ - TB_PCK_FIO_1993.vhd - ${ANALYZER_C} -work EASICS_PACKAGES TB_PCK_FIO_1993.vhd - - -# Prerequisites for package body EASICS_PACKAGES.PCK_FIO() - -bin/pck_fio/body.dat : \ - bin/pck_fio/_primary.dat \ - PCK_FIO_1993_BODY.vhd - ${ANALYZER_C} -work EASICS_PACKAGES PCK_FIO_1993_BODY.vhd - - -# Prerequisites for package declaration EASICS_PACKAGES.PCK_FIO - -bin/pck_fio/_primary.dat : \ - PCK_FIO_1993.vhd - ${ANALYZER} -work EASICS_PACKAGES PCK_FIO_1993.vhd - - diff --git a/lib/SDRAM/ddr_sdr_v1_4/doc/SDRAM_CTRL.vsd b/lib/SDRAM/ddr_sdr_v1_4/doc/SDRAM_CTRL.vsd deleted file mode 100644 index 63a59d46f0cd074664c7a375cfe1b6845dc03ed2..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 71680 zcmeFYcU08e+cvs04MbpQ(nK>fMJ$61U?(F*5S1Xs_NbwVilP|-d&vl>Sc3(8ERTa= z_t9X(ZV<$-L9n+0Y$$3*5JW|C_UP|j@3+2l&N}b;^Q?8UxQ4lBc4qHn?|t9bT~f(e z*X%y#TnqlUBM^u|yU+p1{+G{1@ICThvK0V6|B>4TLHMtaec>A@{{P4SNAAEcILqL3D&Lhp>RKgpfnPB>=1;Y#?kQ>>xTp*h4r#I6^o!PP(ZjsxIwr>ctChUbc5&);RVqH!W*I|L@$Wm5Pcw&5XN=)Uoc*WAN~=fS3u93NZ^}HUtTwftUl429XYt0WlY19>jcz1rQ4%7C|hASOT#WVi^Plp@oQs zzeK__74XVu!~bc&&wyY24-b2|V*YEXi{Lpn&c;^&N`JrpzLkI8!B-#IE#K6MH<7-^ zPyRH6_bLUBJq3;-1R@EJe-^w4#*zHb4i_LojQvYsbL0R2$yvs(!;BLG4=J2EW1q9& zOc<|yIP7~W97)>mPcnXw%y_^5?+!26KLWoLL;O$sSHZSENB;bx^#63-|L?}r|3BAn z?Av(!`PKjD*Fxi<;V~v9J%vk#XL;B|)Wg~E3M}vvmOpy<8 zF;Du>d7q|y_#$?E-w3Zv}AY z&K+>##0eg3-@e@yuDz+k)Tv<9s8K*gsZ_w(*{CIqhjAv2hXe?Y@Rouq9L(`~E||(| zf8fBW!JtRrJ~L}DOo3}yF*GeDA+-m%i1e1dhKgjMRP>{_$WA4;iA|Z6ETk(Uljkd< z$+5E%X7>QDy+xKP5hW6hg;zOc6%eO`S+NayKF@{s~9QYFUCwwmHVoG+0`VkGB9*xP0^)WyCE$wp#b>~|wbfU_vTSsdVC z`orRfphZBWc&j+iWUDx;8NQsCZxx&7OFHCB;>_|T9rGpT`4S5#SmsOQ`4X#qiFLkY zuT8$hb{@LH$|MRT90u*d3M9;36y`2I6y`1obC-s>%fj4E3}K2Y^tCP3wHx>)gzt0D z?2IGvTkT3cM5P`V#ig!+qF=(f?)wFhFDe3)McD!vCE5c%A_W5QLso$+V5I=ofE7^T zZw~AS&B`88%5o5hEY;}SthxiAxIVsF71#!=P3RspAIS#NP}lk zTlzurF%7Jq5d}}%^QOfGJs9BAMRmcqiS;=V(9PZly&r@gkjjgI>jgi|Hgh*3xe^fX zYadn$CnxXHD&L(@iHe7aTqYLxzAfqia#s0TTYxcDAXe1LT#Tv3`nDCK0kY>@z)1OI zxdyKDx#q+D*V#UljPyN-3Ak3Od4ciR1oUL*RbU+A^UpA8fCOA$?_;NmQg6l95$Cbu zF^|OMA`lRq7iIxO)&QA>Q;`T5ARCD6!i(`T{67A6)Qs^f#M7c8F!fVn3EDnBx2+@D zg@k*>*X5eUoa*?0u`2TQ)IObFPmS#v-9AIqK119-ZIy{%mj%r#{G-NBS<0jv;eZ9R1B58Xzzm2VP5ErT=y!Am8yAu7NA8l zB39fV|0XW zjxI}A9qrnk0Rxy3%p`_n)-YEuo$)wjqb@$Uh(K8{b|70ugz;K+uIdW&@X+bxSBJkJ zh>&W*6m}k)!)|B)Wv{W7Y#j^EFo|3Sw~_;_oO9&7IY~HM8RxF!j&bGO1MVFMMEcFl zUPh^3D2vdaNjL?-tHbJ=3_Y#?TYpG@L4SKZ;_*!XNiXQFd3QdL@2Ce|^fURTJk9Us zPw;p7N4)8K{wL3k@pKS+2!n)C0w9D%LY9yxG_huKTe+tk4B|#{r-d8BGvU+MU!e^K zQ^>OV0099|MW<^>frMlrEO~aakd~69h$7Q7gqWnX6itRA3Vt#>BN=i6bYxU)-+|8s zVVF^cJrscz3aF@fLtE2xq4mr3OHh$PtyTZ7Sx@obe*Rh}S9_ZX^tD%C77V_GwGWoE z!^~C$?T(u7wFiroNq}j~mtIrl3*-R#@Wt}G!CRKsz7ZgKW}?BeU5L0nRMu_^M6yK5 z3veAVNd%n8H1VP-C+d)>0J{*$*GSk(`pE=r0+PtJKo64Fg06_&yRVO=ApCt}mWhoS znEUd5qoTHz}=pkLkoOn>xTKJ9g+F#gdEAL)>h3r(6y^*tspgYllPZL$ZICb zXUnznP4b=MbwK=cerpHI4LL|FZ6YA8zeYD0qLY)RXCw)?05**I^OOP1u=VO{|dF(smn3dCv-sz5d=l z-Q^Y5Vkf~qcM-FOZ$I_Fma*beKdGLV`6J)h5UCLUdy2&1fm?$?++Yye8ztb844BmZ zK)xFguyneuajwoF^-aRCn%}b}{K9&fjQZ36cWl`20W`d693p)`Oj?JHp4`z4@^n#8 zllD1aFEZCm6ewGUh{I&La=`aV#5`WL&VUxtiVpF}O zgC6nXfmkH%1Q3aI1dx~jDIAKm2-xgJ;9@iZO+frjBo+MJTfgYd3u77nvp!a4`_F2PXqDt^yvwjWTDUWRE?|q z03X4}2ecOfUqqh`IwL#UAuaoM07-2{AT9S=64c2W4nG03H(BK&-)u$StcJa9HtmKa z0rNC)1g=SGyNlu=!UA_Uv+o9}$jWTfAcff5YM=rMG_g@4z_VANe1fu<>l9bh?#q-O zJx=cIX=&0i4WuE16s4!yYZS<9SEO{j)!M_L=9}W=H$~1j#Y7gGJr}UL9ms4#6?4*n z0`c&aj+R-Ps1E|vwb<0Fhg(3XtZqdwa1iu_vfF?|-TPyuJ>*{61kBxS0k#I4-nRg& z!M3rW3Ty+rlb@h*2IRQ_)jiz( zS3# zW3yVJZZKH9Z|wLJxL89!Pz3in_~imuGf+c!OW28DPA<=dSFMi!>({Y~ zCP=37Yt!e3?~9%b#`C10s{pxrDq@0M=Al=*u)%Nxgb2W;O@<6K13!VR!GJ-cDmml; zX7&UQ4TcaEcr6!X$eKZt(efmC@&Ehr-%RuTbx6^qe~DlI67kSQHGTJ0svVPsh#Cz1 zmo9Rpe5jncCbSAc@)Y@pFJlJ^6aT}Nh4hIbDbrFi67;Ek=B1~L&EgPLsy!qUIRR%m zE5C9NHs2p7{~=!}pBSTCn4Xb5YqR7C=+yqcu}yd{NTdWWhCH`HW?-KR{=LudOLkDZ zQ}7nrthQ1gmAg2K`7hHzhso$V^i?b64F(|IVBbM2%nmN>5=7`^)Ed=`z?YB)gTc@y zfd8wXX%{}fZC(V18P&aHEr2#a%o|3Ez2$(19QzM<{RaMp+;te7MRu)m7Kb^D6@q$L z?r&r8^Afi1k1^2gj)KNumuxDqsvje-fEQ=91wa(B(4@To0*aaI(hd2O*!c}HI4t158ng$|s#fj*B(>_jCAW?zZ zAP22~AzrRBGn=!{lC#dzvkp!+Lrqb;Mypz|)ZsJI0r9RdJL}x>tOJeudm6Bi@ZLkb zqV9F9Mb0|IzqB)*3>|EDbT>1yd_4kHn9V?|xuS#d!;trl(&Mh;({9qpiwdaw%6rrT zS!%bhiq2haJ9M!II{?cfr=c>~G!2M(utPKrsOB#=cs5p{S5PCf%c zeLFW80jy5lsv@(VkofW+Nx152fL`{rpz$)qS0T zNsjMuw>?&?`+ARnvhNn3&#U_m1RZmHgMfLT9N!3Fk>eX(16KFlIswRYd=q=XRx@q^ z>m1*-f8pCjV3KW)ZzizI@m=%D0MFe7>~nm#1BcH!zJDo!xaata5RZ~v72)-c zA+x%lQ6XNXDx}AC)icDqQib$R@C*IBYU7Di|3wE*KeH5+95VnI4P;YJ!nt*n;47 ziseDb&>Yx4C^r}h{ySI{lB;?q3O%3_4J%fO!b;AlMB$|>(eUdk(X5C{m1x9cm1txQ zY%;1|C5kktM0iQ7N)!cxMWaoFMeC!jf<-Zo!LxyDkZ4w%SFmV|Pq1ig|KMk$aq3{v z`0!xSgp#OW(O=_&MHAzLMYASN4;D?<1dE6Tut~f&Sd@?xEJ`fN4HhN+9W0)bs}j#j zKA;j$Emn!Aol!j#PcK!8Q?9GTGfFB|;+c5jqT3`MYb)?BY(@jRbk@q9QI@d91OC?u9>CX{HROEeKs2rAJGEYbLuXuP4|R-$n((b$w|%t|z)L?xOZ$Z1W0 z_CtU+t}a0PG(cMwpuGu&vH257ejXg39D*FYgNK)WbFn--v*0foc> z?SuerbbvMj3PAzdfdN|I0IfF^+yb=D0a}{?tyzF}lqf*^1Dw{BXg`#|eoC}YOSDxb z+M7@)E76`S(H<|+9)dz)iFSL5c2kLV4HPmWxHz0lutnZW8HJ?o%W3m-BD{u8;sllrH+hROZ4 zjK|cImmx=qvI}K4PP1DG%r8xSz@^vpsMv@1*Uey!JbmE|rQAzS98mFbXRW zM+X)TFJz&G$Og-;eI%djz)_Iu-WQS?r=0ty6CfkGxOF*Gu~oCWpkKFx%->FH!MLXd z4?><6_&hCe@lcz9xYg4ju`BRe;MeDgw7vGnAHw)u!2S@{#yD)GRG8{Br~j7H{+=O~ z`LDlO4F|&y#uX#O58CLCd}ILkPa6Z`jtx0jlMG)@99hBMI*D^e zizS8od=AurNd+WuG&`Fhq|7!8CTC})QDkZ=bVO42`83W(23L1@4xp#+>lrtstfIJ} z1~D0Y)zNyZC=pR9z}sT10A!ks7HPJpBg=K0bpt#Wvw=G9T~p^1e?JE7u5;xNb?M#* zDt_tYN6uAD>COz;9hq1*pb8nCSSAXsLgJWd%nj!3wWa#~3^>c&VqP#jGr!z~bz(;% zwW1m@VDq@XFziCkLSZmyio*V;aH0oiYIL)RYjfPL3@EvMb;NlP`Xu>S=#w2U?i{~; zd)ui2Pt?iB20XdQHuAM>)9LWxpmNT(D#a3R!`b|?W$J4S(XdB(jC?6 z(yk{3b;*PyV-7#CcRt-*SK2I7zu@+M%W>BhH<#I#HJ`LS+w887D;8UiN-XOyih5c& zS+CKrECOd+H1g7KN1psGzombnZ#ojS;ER~=#Cz0=eM$=Ydxqa?8F6}pg{%bJ{AFJP zv~kD!cSwdPw1`Ew+ip7yGH^pYZs>&@92>u$%xNp}9uN`|tuTq2zEHs>^Yi)De2x#m z3cCBu-6-61>@>_Z`{&Hkr}#i?xE8i)$04JUuZqT&wS;( zffKGfqvo2&&lSw#C9e}jz(haSB7Sbi3m#(aLTlN5LpOWq_LX}Cp7zk%sN1bS8qO)a zPb2AlLqz3Hh zac7z0+|_ug&5fJaC&qLsavKv zbJTzL?0@+v$KGg2>`&JY;d6?WWlC^g`BvGgG{ab;5B7zK_HW&Md9uoFlhhddq>Zu9 zG%VZyV7}9`z?`hh@ji~`*9}0u;*#Ikyzk}e6;4Gdc``Ae^IQA6Z92W#b+bj#8J)*a zt=pzoo6EQM-28rflVx<}Qy%#TxWx^VfDa%6PsfwUIO-sNe&}wpfy{n|H;**=Nm3{we=?!XjuF=P|VH_>J;|*MPK~yBUT1G9kC+*yA%j2+L;WS6pPn%&KwU@O>1?0Z(UuM$l1yIa?h>%u8H zoo`vokpS?oNg~(LympYethMjmIWLqdC;M1VNe*%*K`%0pj3QquJ+P@%C3zbMUr7UAL)sC8DSPTE zK9MN6ifaiCl}T+`YBxU|h6GaQ&Qc^ync|vOLS3hxQXdz0B(OPHTNai#IBI|O`;38z z!(r?q#$mOAyOMuk<~Znz``|&i^{#R8o?D2t3>>V)|HcpD7x1G*DdA0Ar9dR{ff`6y z()omjxKE9t3reX)^iAS9@p+QXoCVS49HIjj3*~E#R^WL(+Vp)%pl(n6 zHTe@cXpsMs%TZTUg@&SIQ5#0G7!6@W!%OeIo>Rr3mr+oS+BVWxU0di1i891MSBPAd z;`fgNUFTHUywX(1xB**!1{4Bcb$z#}I^@F@0bEetRTeXatOT>ij`0JrvXPkOXkC(S zt}buzhYY!qzgz)2-7#Ic4!jzi(EL%?uIsONWBeGpE9h(}vU3wnWfs6t>rQ3|4{G`2 ztP8tZu4a$Od$ITAAcsw4x5}N+Ecp=h0(+Mo_<54KpJ{BuG#QMmhIn%$X2>JBiQMel zAD7)l&Q(14n>)l^;O=rYTqCFcv*2F{BlU8*$U@OJJ;dMlwG-Yb_oAi60t+4C7g1(yB zIa7A)rC;7_Jt7Lt2mH-B;o7Fm#w?FIkf$3|+mu-QA8+LoLV z;?k4TjN3XmtxpcMo%)vo-nO@?)|Zrln(lrG5~vyaQ(e{SaV}ANqm_tSeKOXqG0E#q zHBzUdL+P<}3cZ+KPwQxKjGoFqpnD9+uk@5$suStj>~!6Bbb?`wW8*rxJbkR_kg0h3 zXuY5C1}rIh{$Rif>*lZ%{aQ9|yi^B>ri-ukZHgBzLSb#w%x~b@tBpV2>wfAim|rZ< z1v83|hBq&>xW!EQD7#%uG1FGY-2XT7x6%Q@xgVK!#)@^ja8x>g9l?SXJjpI+Jp!kL z{(hv*2^RcO`t?E|xxl4x4^gn5`++Xxx+))V4EGwHsw}NU*C;#aJL{7u?D>?0;EaSA zeX@SO{?ejOTlK96_2>1Xb-y_oGW~slGu?~sz<1_*^BAul%_s45d2e(ZKM@th`+yg* zIYD=LJ>N}t!gpW5uzbZn|FOCVu+Kk3CkA6TZUi|&Jz`b`@7v@}T-=xw6c+>h$8HS% zYr;w4s_`bs|JQMsA-XUo3B1FTelqNh5u^1Ku-N<&Whb}>!||eBIQxahu%)r#L|E0 z0rnhj0IO(yA54wqJab6E(y#4dp7PFZ+kY~;@V_-e0e(F6Yvr?Hnta!+MR}S$x3BW?2$_F332fW@ zJc-@cZFF?uyQ0xWa~eTClk+9I(Dp>r{=bTx&V5=wG60%>|TI$v)|pVQBvLujpDE#g!4-S}N}F;@tFw z@96JzM_tUojZQsvLv$+!n-jZ6m71BX2^`MtNP#>kAgchMw`AYo=41Cp-SdD%&Hkh~P z$79d1f>2DrG<+ssw%)pWeMWG?w3GZ*{xRQWd*@cZ)l9&32|Ir~r{Xs@8tKUI$BHHk z8X;2vTZDbW8R4ezT-d7w^3X$y`|80NZP5u#Is^XR?>sSgeSvdamgLSs#A!@{Tnwg9 zd%e3YdSlYhnD2#~NULL@E&5{8Khva1_VuF6 zOVoghl!IhpcaOLBk*np=9T&p=^QdP-mk$RNL1l^$`?DlKUa>y?lfra`*U-@^Oo=Jvy=bCJgpFiM_0VIn|Z2)Bz@zYAbC%x^5N|O>t+I!Wh2V<)*J&4Ex&3nhu8`&lF2Kp@P0v1#P zHwjf|WI6Tp54x2L)B`JKQNBtasz(Id)+;(60o3ctbS?Y>p^o1vxG;T~ALIx-{9r~} zY99rfnld{%J&BpitYXTpMWFkc-){ZCB@@u!{&f>0WgS@1gB`?x5KykL12;ec(~8JX+VGg4n}Lgg7L&cSq5_YDc#Z3ek-vt3>`SP9NSVVZkb z_afU_-dDJX9H{3W^EZXAdLR8$WvqUxzE+VgUm@QrfAMd9(|0+fWDczSp8S=(Sq@B4 zC$uLz1jW$=G#y=mg6~lwK0<72&_VP(dIz;Fg8?tst84t*(QZC#{5vbf;C0xBgw!C5 zn3=)L%Pfg=2_Q9SK#bGaxxv_kTxFs1q*8lTX^wqRwkiK56qqmOYFMaWtN%yOJkNyw zm)KNtMgLG=um7Q+m~6*`ZoCSQ;3x8XHrU6X$?lQ{Ht+@fasCRQ56SFP0VYVYsp-N2 zDpt5n6$@*GO_bV>UPkq&UkfdQsfCqt0S1k5T5`H^1!YIe|32*IK=y!)g?S!{{x)>E z17?$25^N%yW1{n*dr3Yd>&YJ^xOmAt_ufg{!d_G$6-6Z)H^5YS0bNHeVr29#rjY_= zOeF0^=P+h$2GfVlq`z*VO)V@u46le8R<>ADN8?-K#ECcdJIDFX{tEcdx3iuDSlmr~32Ls~570p~nC1N=`Fse2`A8 zAZ9X?*z?34VmAMUSScofhlLK+_0^3^jm7?u!tuJ9Ik$(qbdg7p7J00wswBhf3&`+vm(4lyCeqkV`2By zpP^uGlO!%nIH%k%oE7Sna44tLii``7ojzdH^(1MAS7U1%{Xtm$5f)}bD^TYp$KTRSRtM?v=Y>&mdQ zMobOKFb=~7EuLO2>2LdaQIH!Lslm3PV3d+j&QWG5^OXCQ8se4`6cQcx?$_Aw;WA~I zBj!D*ZT7=Y^XgzpLs#0mbHn_<{0g5SALq?&a?1lmOn81?UoKO#`EJ%B-#NO{%TU<4 zdCAttS%uqSfueZ07^rP=PrMUpLj8p+e&x0-+d*!|Z+!APK%JxPJh+!j-a0f2Unv>w zNCR(rFda$9(`j@zolhU2!8zKaa$$k@{oTg{^x^vcTeX+=yXCWcRl2_l*u7DZmswoP z>kGduFF0|?w;y-8FW7xNu{`M7p%c?@e!|>&e;&Nkeb-@37e>jv<6@X(W@z|LtHsQE zM#tzEe|2a?_^Zrg<^$8lSh5P%mjxm07pKz@3etLB{a-#ASN z{bixI9@B>d?-IP`I{p-|NOEwkPg_%7OKJMMh}7!G+aE|Q#w-!*yAaCpGo?pJGv3?qCACz4$3EZvJzA3a93h2 z9!k_3y{pirc6XITTC(e$8fBwWf^A>a%L5C*+QP9Z<`W?q*c**}$@DiSy?I1A?Bq{c}jdF+KDpzfxWwuK4cI%#oUWVjoH_)Gsq?61`-roPRcU|9bS+; ziBP$hfJ5${lU)npEuzL!Db!*L%%Um!J+*?dpbs+NsXH)ePb=xoOedCN2C%E?9klwQ zlHG8heoME~_5=IG>R(UQFL>UXD9wH7vbI7F-KDky{c*j~x&WhjG3UGTKKvtHEZ>3A zEU2+4UG~}^>Rsz$RjwO1^LyVss11GC&b*7csxEsQQ&G*!K}>~#7aw^9EWY?xJ*@Vt zc58g39{}GQM6c=|1y-AWFa}<`_$+IILDx0HPGKHXI-RW&UJDt#soYr(lmgq+_g|D-wzfib^FsNAZD4JOZ1l0@6rAsE^Ox4c zZjKYRh~7`&Qn_VZE?3B% z=QjQ28fVWEy*Q&^^*zw$_K)hPdwta|Ot{zPc0;8&*iWkB2JUbfW0gIyruTaz$sWu{ z@_}+6G@JLy=W+ZTe;c~tHGCs)CxM(n5nJ}Lmk=mK2_Uf@#4Q%q3+2jVLb+hO44hMU z&$t}jESSih+Ejy z1Zuj|_W@e}4)x`3Cb`Y80x&!EpCpAECJy|RJL1gKW0g~t3zTb=V5jn^az0U|JV-be zF&fuBxsNhCVqGxhpcTU0=6RVSAx+jaKi`BXw7n+}9C2^lnKY;3@ig3l$;X2Z;HqM(jQWn=Oghx6`8ng1o8i2% zfQonnwMp^y!bWM1sIsWef$l*MqDRpLJ%=G{e#E7jO$oAs8ej2 zOT~eC54G3!#`}FZ6<>61?^0F46ESeTR(C^;B^QS#&|OQ3M-F}VhARP`{Z{Xzk}=Xn@KiZn)~t1i@F)a>J6kb0eTUIkA_tr zc`$~UPH5P51lUD9XrEU3{_E_zN}`VVN&p%8j_a*=p;nR)_(SA(9^{in}4o6_o%^zZJf`UK9{0EkR_QLlS_lgHkvt!e?qL7$7rcLGS(~_-f zP#2%HT^A&@5W27e|_u?yhT`FRpD;x`74qk5DKQ zXPGoK9W-my0||^6c<}>yEkBvp@Ls6P7JeTe4h9XvMqvcDY|db#KV&LdiGjbdL)ZoE zX{U!+J$6v|lK_a^Vigjy!z~I=#D6CM?9d75PC`bAFmIw82JDFlER7gRSYey6Hf0H> z*+-lqZW2ekD}!U+6Q;kTnKK6Gq5ILZ=q(rQPt0#Y{3{eRqb5qHUbjPiltD_P(gX{X z!OK>v$7ZaLKBP28)Pa#byvACvcOv-&G4v^CUZi9P_vhW`s zJv0b6jm4+p3q}lC1!KsEaoCwL&rqxBRr&x2@9^)qQ!jR|8{tO`BgPS62GQl{LQUU2 z+RUAVF`EIZh}VSCBa0^A(eucTI*>>zb(hG$$!2=Ku9n`R1C69HG8Hh~j~YgeqvnsS z4O~R6qjpiZTwqkk1jhJfhTnM=%BdGPzPA(IogP4speNDa?xq%ij`!1#)39Xw1YJQt zqHpNHGhL|eDVw5eXXA8k+%X+ktE*>caQE2_+#B6Dod+%p2p=2TgBiq(VirdHFw|e< zIllIT9se2Dt;&sM#wLQ3&{G&909;5A(uEbmR-qSrUYN{k^oAdXH(yuQL6)(#ZpFqQ zKP09dB=_>)rqoJ-6=H9)=V1@oo(BWv^Q`tf5RH|KW#2N8m37Ld6|Yu{fR9iBg}<5x zeWPC`{J1S2n+-nKg8pwz+rP+x7`??_>HZl3nR)@IBVc6a3 zPtkyb0_=FuQ@lxP$~v>7_&_!a)^GM133hqJ*krO>;9fYxg4=?P{4Up@JBLo>UZUZ! zB3!u#Qitnkgz_XhTltuC{J^zwQyoG^dojjPVR zs>oXXf2ZusQ9$s4=$fcNpWN7~L3wR}PSa zpiy!{K1ZJSoJZ#w3mDe;?2sRk!)o_?<};G(VXimc8}BxVy@ViS=`WzaR( ziKhh3wi8xlI0!L#lKsfxWZrXQ%vSDYXQ!^7G9!1%)PY%GN$v)+fP8vlXvL+X-w|BE z825=6lU4Jxc=c;h6&Og3q$X1uYB776T}d0}frzUqdOLc(9?-}16X^h2J751@pQP`? z=hB7r^WK($c8`a`P)eUF`Zb;1LiZgQYOnLs4b)|spA(g(*(B;RbSrg#>kjEI=)hfF zjjmC5p0j5@aY89y1IE}nh(AASb2UaN|&)tBv-d*pn57Wn?JJ3n|H9ZK%8uZh!NBXsx zinriLW9n*b2%NQP{6hZZdW+9qa%0vKu1>y^H{E_O%)pBTyEeOsUG5vv-}S45g-9V@ z0BJ(DkS`n%&Iz}LJf%Uk?mQPQpnOZQuj$=#>0j9V-} zZDkqvw_L251~1$Yy)B84F%)hmO^z9&E0Q#Or+tsPHNygh``gV*+P|A)yDu7o`eEJh zMJQN@j-ZOsGSnvb5&9nei7r#!x&YVsvrl$Wo}~v1>w0=gv#N$DaV1z)(KdHsl5_>7 zJV6vGPbtAOLMScKsP|mVY*7AE$}!-I1yD<1qQ-($FNkL1^y26)t%IJ z)zv)K4aH;dWV~_}bW(RGtiX*y__`0nPitf$=hJR4A6{H|CH?MNnSQ~q3s>@%{jLoY zU~yO-bet{qtGYnn`F+8!WkozTR?<=1TBH~DR*A9EgZ`SF_;znzI=?qQs{lE*FsXHK zZSCE)E*&aI{QDwp{&8gTi#ejK&uUZ;Y+URz%GIk`u3c+{Ou-$!BoO^w)<^ec0QuP^wK zQsl_xL?@>wX9#A~;KL=b65pLnn_BQun_4h<$oQYyHPr67!(|m~_8qP$ST33mpK+^w z*B8t=ULcyeyYxz)S;^c3FVyqT{w#Gu=AV6Xu?l;013ATovX4`B8`uICh`1~4r4PRzG@RA*9k|Y1LGL>!?hWN) zxGQraW?Xez#^nU3l1Vca*&N8{4shqV+uTdeaGQGH@gAVwKls%1*{=uR%hREl{@(Qc zColPmC)!Q=CB--K=Xm4i5#xS^zTJ0hTrc}~Yb%^P5#0%xouYn+puV%g1c)Q15etd6 z#6QGrT1ywuhI?LxK<{z$Hz7xl8VR}Sj2CG>iG~xlT@qg%Yyi;Lc8OEJ*+25mCa1sR zJM-#Kn$x>YfYJj2TDGHlkxJd(OM#d}hT$pFd>$I*I?XMx2O^%T406j)xM{P){f6z~ zMChoMLE)PF{_fSbcf3E(GNfOefBc5ks#<-JE|LHuQO#PQnRTU z*e0rQ4>ht#eoFpnBo>bsrFr=6EE%HxWUg(8#oNHw71Qv9E~U8e@q5A zj9rZPgfcQyGGSL zN~VZy2@aaFw9DzBC_0TkH@YnCpRA>;ZlxEkDW3E1jkLM7k24XsE#eV4)O^3eX!3X>Eb{gWvp6MtEpO2(nMmRZkCjS@})wk zF%+0i{h?mP)XvhztWJx9)6r6V)y>W(8WecL4OwH^bUjTyu) zx+L9DollHz5NAvr0{kBxqig*>m?;wwV~v5$&(*-v(_F32ysR@8VzsoIHkZF`H*+M^ zsooX?PJ<`+oS9xsAQQzTG8xQDm|>@s zz7d_c?%XVH1h=+t^W8KqB%50^D{4P?mis>VYll!lwA{$<9boya`|C1To0uJBeEPu7 z&O4lIl7PW@B<`#KPdo{a<~LoAZ{ zevjAw7+H~5l%o~%U$uC^1v6&aqp>O2xTuN@ZQ|<{82>~%eaZ{V#TO@|#xhFvYm*E9 z&e@kEhGf4>?6dYAsmc~IjF&ZSi@)$CML@jKPxf}!>z(Y_Hur|@g|6C5Re;quW@`zL!40Yvzu znDJ4PNzrP}=&3QohH56gKDNkHa;ll-e>2hTiVF{KYM*_&ZFpP{el3IfQ+0f?=aVdb z%?emG+1RYDjxn>jwjw19RIacHezM|wOx+5j2cEKgxvXtv5;?Q~8tt_`8#hTW%$c|} z*Z2V1uY&Av@L7(dLq(tki0bD?o%;G9>Svlsrj&M|B|X-}HbW_k*Ui+Z=KGVF@|+ai>{dQUJVN~NVZ=w53wp`;e@n%BoddyG)Tjwfak>AgOlYF?^k zzeu3!b^KIez4D^}zHXH#MD@ZC;WYtT2vgFTG#1On=n~1YCpF89@7+IGMw7fAs2722 z$=6E0$*!F;wR>5Sl6CEr$P*QJdgMLyU|C@Gf%3670Mn0w!i?&ON5{)GPq$l(D&L83 z)znizs1Lg5j1R52RatpS!%U~cC&d~4n%4AQQFZ6e9fwwKZBvDrF(U<{@?T<3np~IN z7mQRAz-TEK!j0jkbBnlj+|2&!u$sdXvhjCX>iUTdZ`9vp>)#;y9yLdryXwX3-h!bv zWTQkpyJ@VAR1V9c8r42xE0YCH0cQJ_p4s?xuiA3!Bba;Jqc724*IV-OANB3}61f}i z$AdB9{FDiNdN0!~&y}^J<@LpT?)tyD^6Tihm*t;ICwG8PHCMo=XpIliS_r7nR{+66 zoG{zp)oP*NaJOZ`ZnEtJIo07$k*T-^yVL(hV_qDvbsc6I1pfByj4P~nSq*m!cefY4 zQ)Hqh44vZ*V0!1&qX}fix`*; zf#vB$8LXJ2U>am5;YqeIU!kvgvD0A382EsgJb9KPsoyc9-`_NFZX!WD;;hD&0in z(t6?~J&5c?Y8TOM^i*1*Bgy5Y^F_PBo|jT)YvyL0C-0EidNSkOc!9L0+^KQ4{Nj1% zBh=PvbwnryerFiw`R}b$1@8S_s&$E~r0S@@@3!XtdqpU;qd_;iKOI3&q$73lx|^^d z3w);6uutiuY=F*6m%+BM1@WviH$%5Xw|SPWZkO+>em=#gbk}rGbYEsn$o;PC2$Njn zY+VVPoi%T<-`Tp3v#qvyN}~3utKY^m3l{cyP^aqm0K9HeKPY5QGJo=3sRr<+H0^6^ z)t~g2G5ZC=xe45r67@rZuV=IP`z+Yc`*3F5ELinAp0^dIa9`(fn`d<%>=>P#Fs09_ zB!$L3#`2z(E=n7vJNYrZkwG}wzk{|OOFu&*d4j-$fA@0D{$qJV13v>TduFsnM zF4te|C+?)pE)u`%XI}|2{pR_d(k`vEer9bJKhH;OwzRLTq%X3h zimK2=?27yU{^sURlRRp9QyKaEZ~c1iy}5Jm?{~iEclPr=-QPYC8B$x5rK{H^rEA@; zin+mcyT0|}F0NjePrLrJN8_&BG2#BDj1XNjpHI1fT8le3l^AMrJ+#m0UkFIb{a1T~ zVa-wPGlSoV44mFn`jjTrmkp-Dx7yD&U)Hxl-|5eVY;mrqXvfxW_3v_`$J56ma$kB{ ztbZHE8Q65gTZUDJO@=QGM-68UHw{JSkEVvHW^ak44snaK{%v5L22PgLldK+!bp-5} zoi#fe3r6-?mFv~JdrZ%vq30Xa)5P?;UZe!4Q0q8U!l@1}@sE|Zwsei1+j&dmh`3Lq z*orPAEuY{bJuY_Q&ZvJ)$=}v;M`V5W>CpO2+L%M9%O#pZ#yy{Wq8loTlJiF1$eu6_ z#He4bq+>%~F}-H83_d>OEz>H~CR2l1sD@3)nipqVFd%T&lfe^Zi_c7y4chlgdy_?| zg>A25W(~~&=3sR04L2v6=b4wAcb-3*mL%D`Q^L0NQLDEuTG3^6<|mzlx1}#$9lvh(qU9faZW)pj z%j~O;TFzQ-TB@h^OKp?drN1VB;owwrs%5b0A}?3hQBVJR0Zq$0Qt)#U>#XQ`I70D? zW4tma*>d2A&1|9C>PWI?s}HMxJ+>(8kArOaZk4vawxza{)&~>d`{~&ZE$29)ZR+^G zu&1MiUdkt_9chj~?3*1!^fCGww`$&A)B?>-9demiBNxni|NuK${iQC&aTq$+;YqmIg!7zh2-RW#pjF?Te1D5<7rz+ zUrpZclN}Rmmche>PQiv>FZk|wzZMPhZN)a3oz>3STuX27Y@f>0d^uGgX4W+9me}}x z`{#D*cEMy(mV+~x9Zd~vuVbyFK>wQIh(66g+z~f?&(|7sh6;sf-Arab32xK709?-!6<6)qNqnYVZreVYQ>krrGv6T8k z;YelUNWP_>y}=LBe-t$)__N{Z;o1C;))v3_Z@e+|$t#gfHug}*v#%$>k#^yWV4A-Ptx&A8Y2v$4>~nUZ`=O-&t4JxxweFiBXqnC*+l z&7@)QJ%dsbe;A-kNjPh2vNI(?X_g+Hi|>z{$t@Z?Yq&&WeVrROv(+M2ZE3=+w##We ze5ILYBJHeVp{Yn8TN_ydEun1J@EGk(?PBday>mb6)>vN+>#>T%Pwc7t+G;Kry+QTX zbw4m`_*!q@*VeLndVMPO0u4<4xTw*}jBM8Q<7E9({rmdQ_5Ze>wC*>sj_qH2cY)1h z$g;g)IA~jEU^5KMZ4K>nY{B-Q449sAep>Z*p**ddp<~zMD z=)a)ui?Nw(T4rkII~xZb`YiLi%ww5FnM`6^bGydAt(WSZ2(pFP24TLMZK`d&J;{F7 zmQ+~XzNV1fuzg)Pz#eE{Sg7Hr6bA8{6#EK03aGu~g+Y}rgL{n-M*ZJy`0*PF7GVtN z%JNA!`b$r*pX6-9DWBQ0-DW}S(sJ3NOl9>_zjfp}ZaT&`SFp)V0%|m*xzj9o)&O}* zVt?sVieAd>*-^C)q)OszZ$H3#%WusLsPTnQD<7ZqY;B7)7Eq(m$6lv{&*l09tfQ<` ztZacbrZAGw z;hB!FW<1$$iBGe3Y~ulayX}q(>U>ABqn z-SAmp(C@y5PmN;96IS$F>7USP#QOueY3F7b-kIDk`lGNFVIPiOHDxbk z=AIn`;*)b*OClnl<4dI~iG^sf+2@=?il- znfr`EncIzQP-b0Iv9VF+O0=4?GkcpZ4Kb~{rFm}HN9{8+$8yVjC1lr)yvm< z9GaP*OcUF^_m4W2bTD|s=}lg5#VAJQcbQQOtW)kCd2<=S-Xn)H8VH9Wa< zw>&WUiT%6NLbQWweQ;slm$%0TCl8R+&f99SJ=vP8m$zk3P43VVpJSUh9`HHDdM|qB z@XjZ8?jCl)_QjzZk&d0`aPj7W*N%Mi#iAdRf(-TBxuN z-x6WK5 z3k7Z2yv9P7AkTfbw$I^rYiXJ|dgs4etFuGOItS7VgBlL`*vY!$a*cxZkmyINvpt^PYXRJ%J$I@ z)yL}BrnL!Pzxd_wrFusBr95|1h|l3k-OuT32FoUO_cBOx2M*c)a`+z+FGaAp+?%Ep zT=+#PM@B`o8sn<0-EdacmYcg(H|mVz+ZwwY2llR7eZuYipOp+MGg{(E6QrpVp}=^{ z$ke8%Ol?iwP5;>`i&?)I>-$EVUN^mIlIQkH^f}xsVTVa|dT6hNpG?v8Bn{6z~5YGme|ed~+t3#(WXpU$u0Kjp_*v#j5#+pF0i z+so>ywh;A7+bZ=`^$1(=8C$rms{Jt9kvFQ<^smcfwx@G3Ti4;S4YdKY&C36Z0&8KwrB0V z?Vs9Mc;Sz>#KJFa%L^OZZ`y_y2A@DSs^F=eexq8A%&+H$n(QK0qB$`=nC4>-bePw(#&YLMB4=}aVnALId!xxO5^)|_7ZgM+gwHDMr9D_U z9*d{awGDZ8rErk;M-0B))`szs{FLvX_gQz1hJ_aKYx$}~U&UhOmO7S!#*R}Bm^zJ_ z(}DXUEG*hG(K6riwq=7wD5F&WRx4BYsU?SWgZtfT(=nCNoF8j=gZ3K+G-&r$>UVF+ z8noMxDoyC|?TlM({@wLvTjrQ)HD1BRw_QKzq3F7=7Yj3oT3@z4rw!1*WnE=`-ZcA5 z>rrdm&pb^^eQNz#t#dJcSd72=c{MYt&FjzipQKJvXB#%EcdA)~h3mrfvo}T-t7&~p zb1m~jWxbRBJ#8(^ciLwxTeWPkrKbLOt*>RRMQ!=U5~`1XSwH3bswZoShxKRlH(IWmdHccy8dv@4yoL`B7FM;SVntbA(@tk*J@-sqgD`vb_0|yv7Hybl zn2&z%4Tebbe#2sO(Qj*)C0$yxE1lXd!q`DAqhI$XD=pic3{y3Jo>%?&40PK4Ja<^P zD@!J=W{%|PT~%xQMg_e4cIRE`16H%0i?X^5%=`)$Ggn8h`*zW_c^?d2urbWJ!Ug^9 z*J$ai%v2jQmMqsSy-h>};&CE2ue@bLs%R`8u^-vSJm(%cS|mibqQu-%_jH|xe6 zPL4gWZS(Z5yEn7G=GoQ+^IY?K>y5y;tltl^DZBq;wwsTeFPbl6uAx^di%Z=7>2do~ zi`+5G@(+i@!nRoo?Gqe7*_SwcQk$m6-+I2<@OdK=#*G`0Ix4l>lvMkT#O0~$Q*X39 zSEUnk%%NGAp@v4*Kx-FkKdWwpb&|E6eT8+TT{0s7w2Un*rWr0HdK{Y@7V^aUQ7^E7 z4`;v7>w|^GzS1`@W_4+zW?yw)SZtK)l}j)7uX3^T7wb6bj+Of}f5|*x-{YufGnrJo zF+*^eZDPD_j_qHzW3RGpw!OBWZN6sC?qhFie~D*3?XTF2o^7dN-P$&uZ-3j)$br_Y zi`9oP6?VBk%E5N%jgAxg4;{&l_w+3ci}m~Z7#xlZ4(a*otI%hauc(G8<3#@P_ zwd{(vwtn>}UGPW4L&G!p%nMBx6@@jH7p4`YSGkZrIOMlpKiBxF=*c17(KgCNUqJm+ zMGc~KG3Q4`>6C0kzdr|)J_zF&CX0m2Buo1r_F36Kd{t;T<0E=RfF;n}n+py1kMbV5 zvu{M}F=w7LhWC47L?qWD6N5-Mcdl%a{a$@elA>OrUZ9_D$W?C~YVM<|VW^^w`p@K6 zT7$N)c2gAJkaz<|se<|7-<(c<^{OHG*9o!8;NY!|ucn`vn2;DVGcGqno2g+V6TISL z5~R|}35R`VCMZp;o=K(Gn?76IA|`ur>zQ5jOqhuHfw{=M&~UBUP&588c-Y8`1KOE zv7pGCwP?!fUM^}=hQliF-wN&mNZGhfc}1<8=kZMaTXB;T7OU>83*(=&D!34Eb#PVk zif;A!ARbHIttfm79M)mzlxs83!6!>g~x?;LlQJAFB; z4m+s6cIIL%Sm-n?EJ*qlYd){AC_sDaN?@Azx@j$I@d@ft+9}!vT1GSacWV!7PiwDf ztLPi*S%5xRAFdy+Pt?!TFW0X}$AEsH{)GOL-Z@R*@SNdhAHyvWbVa<_uh(sz&q~&r z4QFPaMY3q{EJqZu9+LydPYwi|$R8}~^*}R7gX2G#78o_RP0XUeu(@r<-&_I%4#cXx1Bj4PIP!>+tB2+t6#=llnd*##zkqtn0A2 zxSZB3%piT?kDD+yY#7G|^3kIm(YoHF$Md73@n(*72D##}ak?qd4(jhpj?sz+=W`Loh~-YsOKc#d@$H!MEB72le* z4&+$k=v#3T7Tqi1wHP+7Z88fPHavQ~KMMd^S#R@=i=aydGpX)rT}*ty6DlRUB~dbB zGmIL09V}(v$phMekb3y_qN9qoUvh_49oiZsIoFi!Si59)RM9%{NIMqTiDNz*q@xZ^ zHP1BFv<7AL<+jggo_R(SIt(P!5u=zl>s6=U=mE7XZP^&EEgKQ7=^q)b84|5|Ia)IS z7va&GKGB+9(V7rkbcxnHfUOG(A3_bQEbo{z&r}7tXtiFD+WndX?GO(&xk?p zD#s+3i)7$_n+Pt%i*UrMzh2r{mGfo+4Orc3>}k-#jXQork;hk8>(p)3r>?-4y0F=6 z6kLO(LA}9X$5)4^%kh51d=0Rr&5KTDoKlv@`yg@i9N$PStly>~yA1WbO!Y1zHTx24 zU4Ol#Q5CCeYYU2G{u;fuv-a$TtM%Cv1w}Q$WzK7vjy;9AYw9z)hSFT)wF;~1uaR0b399!s)vgvHGm&a0K7skc8aeYCsTszNuCY*iN_)PBj?BJ$^(ZdzJ>=`X?7<^?04UG=mi zsQQ|?H&mFDel6*mqVN((=4yjhFKFKpDfe_i5eSp(uz|sB#p`SVSV?EeF0X%`El!oy z1vjB-ctRC!ML`jmS@~uxgk8#&a))jg6oJ#S{yMfP@2Zs36&B4#24>;eP$tWl7GAm4 za0?rh(ul2*9|0+QLD7>F*{ioL3htdM;9kdjn!x*q|A_aTm;UEx_e z_tac==|%(1ZEekeAi89HQWZ`Cp88KgRp>X7twEkT@-jw!8f;-Iz7ac=Wz<9!7PZ;J zdRMV{b3Ow>re0Wd%P^5uMMUo$gzp3FZ%00{M)@JL0N|H8C{0KXeSc_0Km*O9r7Gs%^7_VZxF;`nuRapcVcf^i391*21w(Ko(cTHw zAz=_?Ga#cD(i!b(P!$pnA^y-!5c<|hBt9R6SS91!AA;URMh9pDgK;}Xy2IfQlKQE}fdBEM$52g0} zWNYzt<0#FCY4Cr)PktaT08g^hXXx*t5K66K5ReJ8p%C&I@(%I@+JA(6lhPG=$6F98 zDc6)-Q_3etrQh@duQr0a`upAT0lJSepE+BArmp?Md!u=T>wfD|`NKhasF*BX6;2)u z-eBod1L%vjo!&+NZ>CVQ#=3zohIA#H=&4snQAn0C9b@b9#`Q3X{<;9N3@0BU;schi)vE4a0seqp>r|$dU&sr*axla*fwHuQwq}&B8@9TsMS}&UA<&oi~L*1?RmQ zCFg_=<;JDoS+C@8Yu-?CemJiSq37s8#5zOqU34GO>f8~kBMdg;1_s)lLg;psM#_Z$ zjFOI0l1Q2OTl_t#Ii4Y%=sn_nM6K&S>0gmHWgr=oP1#V2>>`^ol##M*6^T)jp(J^{ zY@&2RHu;pKW3nmBi&y!0lNcpgUL?Fq!~=hK;qf3i(R;;1d>7&A&a@}K_ij4Uees#n z-==f416UKt5a2oohQ;FHg$T*UNLh+xygWrB{uar=^`7$SQ+$T*Kd5b_N9jX+7u_en zY6%$wy{15^`3RRGgu1vlMKT}yjgc>dOmXRnM_gFZJH+>qZsq-m@+a{SpQGPAs0|cf zblfR#5Z_x`FM7W8eet~Xx9MEOCk1(F6BxY`AhbY8zt2$m$=+1>x$=^V#3vE@)q`GX z2!jyfAI^hhiO?@iQ4bR2(zA3t+zTH(>pJcfM-&hLYu+usx3pdliVyh@=1x2P$AFN2 zA1Ui79WU=F72jWx_>lkjLof25UI+=FF>-(DeCRhu-V5UI(zA3tR3?0G0u;*MWG;Ld z@L?{yD;l37=tuZ~zN-YEBIIuj*r*{z50$^+b*`f+&i;BV~I~KiK0+mlf?l zo1qlpa}c4Bzio#9>_Oe&AOx!fO49#>-~*^#hxmKK)YIw*CKychg9I2S)(;|OezI7( zXVedn&pPV|gpXK17%#6Un-BfQ%Yz{GDs}yU+RfxYO^~2O|H^dRKn{0DHmj;1*C)bghn8VA0}z?Pw1=#LOl!TPBDluNw)l%n1h znZKn$uR2hG+O6#oQvR0aRY#cx{nEVJL+ZHnM4Y?I;mT6}kpEEol>A3*pJs3=@E^}; zpOXJj`;`1gY@ariPJ#cVz;~8GDtG(zW8m`}Z0`gqgpmJql%A7r=FYk5MHT5k8PM+- z^xBH>IzsZFt=x5K2K3v?9fMqV=~-F*hw9hlKVtnlgG-d^q@Gc~CjX)OHTjQNziucU zA?*nL8cLHP4_Cj&>s*JJk0S|qT>Wi1l%o0@re(Y8ZyB7Q%vb6e^*0^#qW&GiN36f; zr1j9l;V08cgCLc={l#PTQ2YYO_XQzU6# z%ODR|{va=O9iHqzgb(%a5I$o64#q2_OT0Xze~0j){vEs3*e~`U zWUKsS%e*|J{DB`k%OAo=EPs}G)svz9BU|DX1gZSx57pnuf5iG*wki?%+oP$!-FdEn zP&80on&~i400VV2?qB*SU1o@5dE{$U*CQ;&x?Y;s2x%5z}Kk1 zVH4~RM~G|(anVN=pz5O%M=IYlMRT zWFuW>yV7Mv;OUy#_AZ73~5UpGTPof=ZP+p<)5JA-*nR2MHoNdD7DbxyIw>zqQ&mn+hLsD7OX zy{LZu2SW0nG_O2G7W7N=`U8^Z((^(5=W(gOX)vdAE?V9@yj8%bBk=Kzxu%3qE9gc36Y9dJm6V5mC%r=uGc4 zTEK2Kls$v64no2wz}rWD5+dqdk@YuPlOls&Z4mk*Bz)R<`^tTwUmI^3#Mh-K{(RT| zH_;YUSO1nZ8Tlo8QaTd#%!htF^vs8jbS~=fS9&&seWllH;aS%q{@xS)Tn)RI0USz4 z?;sTXJVSQUJHs`Xu_DtE;j<8W5k4Cb;vdWRUMSK%l@*^e$lnN`B3C|q z4*8pB%t<1A@=EgIKT7i9eD6Hu!{?;=-hV*yDs?_g{^N^8N%;696#T~z{^J>Aj)YGg z=tch19wGk0f9k-0{NOw7A$2OX|4=!35JnR|c?gAa@+j~*>ax2c^EWCdzkyyguQ^MQVCyuX2*aq0P2`I}hA{GH__=}GBG)H5IY@z66LI?}nQ!(ZuHzMP~oQ9Q)o zyStn$y{?(oeLL4R<0H@${eO`h)-^*u!Z}GKC+bn!4oWxTeTw7exE9AQD%z$#P?T)q z5#k?g;N_7rl0H}&N5bE+4)Y*3A!~OXVm!DTC-J?o!4M1VEz3r zgmf;(N9j1D_z>@tZspS_UgtW*=Ss&X#hE9pMmxm>B8+Y9*;=h?XTrSurCPvHIu{QVe5&xvtg z8L=Az%tY)&KO9!2gTxcCYYCkCK|k^>GeXg~%vFM*pHb2eA)Qxdd|JUN2%okHMSKEP z9VCIOKhtGJ`4-{h3%v**n!_XF(@7Ns{frV{gmivC_=wNoHE!=e2!)=0cySKm@mYkw zl;i<{s$aPFs^i?VsyxUcobTfTRXLnLLO)#l;l4lqPS1(@$)R6!ybnc+lh;MOkJmo7 z`8TZxm;=LTJ-`Bllz(S%^X0x+aV*+bk!g(915AZpGzPpBA(gK>=~UF0=F4@`rI4vE zJ@MyChmW&-h0!!$_9uiTqzTQ`RL`;X|XAj!Pi{xGA5Z^`j#eQm<^Sc+i(>OMWubpXZiPv7t z`8|sHzNaC3?@Q0ewGKz+%tY8t<&2od0##FFC}&)DS7aVQn07=Nl`p9#nQ(SgeWE!J(9HlX8$BAidmvov8?NV7D zLOK`I&tIjn#}yyqb)b3xl`~>JAQG$z%e*|J9zc0C)dMJx7V7~^yr#;tpx+X&rI5;9 z4K5;sKv*SN*3V{fF?`Qi4w|La57@cx?eb*}x_jvc;t*{#@zmX|yi= z5R9h$O)NumP`}yCc}5vZ>(Z%?L+jGTI?h(^v@8SqZRPetPFL#ujpl)ER0#NNLP-9z zNAi&(NBWU#j^bbW&*Pe}Q@LBSoZVz|j8X%$z$!(XLKF>d}Ye5n0>6FO1* zyAJdte00*AxURzKq;()SUH#aV5g*DgsSoZ5>=*mD529cAbIvpR;8sJoy^tM{(-6XE z2X~rV4gGd-dm*P?>8LW|Lv!G$-b!=e#Cofb_k8)U5Yaa((tl_U9MxNCOjfM7V%|08 zF3rb0u%(d7U2i3PsNPEWi1k(nAUXaSoM@{(98c)JUT;qv+2>5u$8XLlg)_4*=;u_EC z$|Cp=12$?%R;;Un^`Bq|btk7ummAbf~Jh42wMRHiFOz<&~fO){i%bEptL z#3x1ghyTp)wKn2$!RIFYhWfW8z)75A#>+cM zc)4fvZxus7nqyWC`iXPQswsk?pHWgQ50cQinEvsot4%_6ckw>;jg~%tP#?KhJ0KL_ zx`L0>95XNIDb6wD<-c%p#c|F{kq0@1^L-pI&*84i_i&TC547 zgZ2=kb85RtIhC_b=}k`WJgX}C#Ovc~u$$e$JyCypwiPZYlyDN~lbnQh9z)`H))IwQ ztneJ?+}g2;RF1ayfA1?M{G#leCC)b&al#hhHzbG>9Q01{jT9E)NB^5z zmZ*#LZ~OM0cJaF3ZwoOaAaVbQh_;lsO}PH^Jwp69l}gatAndFq#?I@ zF5n{E7q0J|LWDO6&k4OIO{B8_+96B$yQru5JuzJ%#g-@{zK6m)f3I|kl$Gc$zPIf4 zo$MEPt`ffEK6}gWICU?39}e%b_7!nuukU29xD%AS?Jd89ljqng?5yN|d&};K^V zI~BR#-m*Ikd5*op&Oh$Ax9pBR_p=#JCV5C-ts$$+{@la=fA?v9`3fc{Ei&= zviDKpEAEuxZhOn`aB(kt9~Hjh&J*soxBQL~o@1}DlY{&1ExQAQ=h!RkjNpEI%kF4! zFMA)A|B5>exZB?HI|SUz-bd%Z0&~B+?Jduu?&HTz3hEd={d_wV2gLR zz2#ZnJ;z>weck=`mSs)9m%We5f3v&wP1pVQmSw@cm%Wdwz9F*Hy4&9Jtg?5rSGfP+H40-SJtTUDb2!6Q>R|C?Fze!u;w z>ct}4qo9}j=4F&;UMy>O#mz$j6M&Nu(Ove|$9$P4Qtt<1GW3+V5E%yD6&JK{hvp!a zX9n~Xdqu`RciUT@Y42|K3it0n&lJVvOLFLfw{{4_LgOw@)UbTCMb8?Tb{wm zQ|uL)mF{Nmqt8zS#-qFGBiw)RvZ_2&k*CDJ$ROlyd&@Kbc#6FuBagf7EzhLmDfWsC zH}1B#JTr~w*efu`xZmEgOfQ~dugJjSZhOl!r`*fl|Fs|NPAn&7zj^n5ut(KLFEWp~ zJFd&KfRwfSzx$#doxK7(hx_d<%c|iy_6lql?zgurONHmyE3ikn-`=vU51wPMz{cQy zd&{yY+{@la)yE~W8@Suv@~i}&Vz0;+;BI@%uk!a4d&SlF?zXr5s`. --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library ieee, work; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -use work.sdram_config.all; -use work.sdram_types.all; - -Library UNISIM; -use UNISIM.vcomponents.all; - -entity clockgen is - generic - ( - read_phaseshift : integer := 0; - frequency_hz : integer := 100E6 - ); - port - ( - -- Clocks and Reset - rst : in std_logic; -- external async reset, low active - clk_in : in std_logic; -- system clock (e.g. 100MHz), from board - clk_fb_in : in std_logic; -- feedback clock - read_clk0_out : out std_logic; -- Clock for DDR-SDRAM data capture, dcm#1 output 0° - read_clk270_out : out std_logic; -- Clock for DDR-SDRAM data capture, dcm#1 output 270° - sys_clk0_out : out std_logic; -- System clock, dcm#0 output 0° - sys_clk270_out : out std_logic; -- System clock, dcm#0 output 270° - locked_out : out std_logic; -- DCM locked status - error_out : out std_logic -- indicates DCM Errors - ); - -end; - -architecture tech of clockgen is - - constant CLKIN_PER : real := real(1000E6/frequency_hz); - - signal locked : unsigned(1 downto 0); - signal dcm_rst : unsigned(1 downto 0); - signal read_clk0 : std_logic; - signal read_clk270 : std_logic; - signal read_clk0_bufg : std_logic; - signal read_clk270_bufg : std_logic; - signal sys_clk0 : std_logic; - signal sys_clk270 : std_logic; - signal sys_clk0_bufg : std_logic; - signal sys_clk270_bufg : std_logic; - signal dcm1_locked, dcm2_locked : unsigned(2 downto 0); - signal cnt_q : unsigned(4 downto 0); - - type STATE_TYPE is (s0, s1, s2, s3, s4); - signal state_q : STATE_TYPE; - -begin - - read_clk0_out <= read_clk0_bufg; - read_clk270_out <= read_clk270_bufg; - sys_clk0_out <= sys_clk0_bufg; - sys_clk270_out <= sys_clk270_bufg; - -bufg11: bufg - port map - ( - o => sys_clk0_bufg, - i => sys_clk0 - ); - -bufg12: bufg - port map ( - o => sys_clk270_bufg, - i => sys_clk270 - ); - -bufg13: bufg - port map - ( - o => read_clk0_bufg, - i => read_clk0 - ); - -bufg14: bufg - port map ( - o => read_clk270_bufg, - i => read_clk270 - ); - - ------------------------------------------------------------------------------------------------------- - -- Clock generation - ------------------------------------------------------------------------------------------------------- - -inst_DCM_BASE_0 : DCM_BASE - generic map ( - CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 - -- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 - CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32 - CLKFX_MULTIPLY => 4, -- Can be any integer from 2 to 32 - CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature - CLKIN_PERIOD => CLKIN_PER, -- Specify period of input clock in ns from 1.25 to 1000.00 - CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift mode of NONE or FIXED - CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X - DCM_AUTOCALIBRATION => TRUE, -- DCM calibrartion circuitry TRUE/FALSE - DCM_PERFORMANCE_MODE => "MAX_SPEED", -- Can be MAX_SPEED or MAX_RANGE - DESKEW_ADJUST => "SOURCE_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or - -- an integer from 0 to 15 - DFS_FREQUENCY_MODE => "LOW", -- LOW or HIGH frequency mode for frequency synthesis - DLL_FREQUENCY_MODE => "LOW", -- LOW, HIGH, or HIGH_SER frequency mode for DLL - DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE - FACTORY_JF => X"F0F0", -- FACTORY JF Values Suggested to be set to X"F0F0" - PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 1023 - STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE - port map ( - CLK0 => sys_clk0, -- 0 degree DCM CLK ouptput - CLK180 => open, -- 180 degree DCM CLK output - CLK270 => sys_clk270, -- 270 degree DCM CLK output - CLK2X => open, -- 2X DCM CLK output - CLK2X180 => open, -- 2X, 180 degree DCM CLK out - CLK90 => open, -- 90 degree DCM CLK output - CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE) - CLKFX => open, -- DCM CLK synthesis out (M/D) - CLKFX180 => open, -- 180 degree CLK synthesis out - LOCKED => locked(0), -- DCM LOCK status output - CLKFB => clk_fb_in, -- DCM clock feedback - CLKIN => clk_in, -- Clock input (from IBUFG, BUFG or DCM) - RST => dcm_rst(0) -- DCM asynchronous reset input - ); - - inst_DCM_BASE_1 : DCM_BASE - generic map ( - CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 - -- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 - CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32 - CLKFX_MULTIPLY => 4, -- Can be any integer from 2 to 32 - CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature - CLKIN_PERIOD => CLKIN_PER, -- Specify period of input clock in ns from 1.25 to 1000.00 - CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift mode of NONE or FIXED - CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X - DCM_AUTOCALIBRATION => TRUE, -- DCM calibrartion circuitry TRUE/FALSE - DCM_PERFORMANCE_MODE => "MAX_SPEED", -- Can be MAX_SPEED or MAX_RANGE - DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or - -- an integer from 0 to 15 - DFS_FREQUENCY_MODE => "LOW", -- LOW or HIGH frequency mode for frequency synthesis - DLL_FREQUENCY_MODE => "LOW", -- LOW, HIGH, or HIGH_SER frequency mode for DLL - DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE - FACTORY_JF => X"F0F0", -- FACTORY JF Values Suggested to be set to X"F0F0" - PHASE_SHIFT => read_phaseshift, -- Amount of fixed phase shift from -255 to 1023 - STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE - port map ( - CLK0 => read_clk0, -- 0 degree DCM CLK ouptput - CLK180 => open, -- 180 degree DCM CLK output - CLK270 => read_clk270, -- 270 degree DCM CLK output - CLK2X => open, -- 2X DCM CLK output - CLK2X180 => open, -- 2X, 180 degree DCM CLK out - CLK90 => open, -- 90 degree DCM CLK output - CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE) - CLKFX => open, -- DCM CLK synthesis out (M/D) - CLKFX180 => open, -- 180 degree CLK synthesis out - LOCKED => locked(1), -- DCM LOCK status output - CLKFB => read_clk0_bufg, -- DCM clock feedback - CLKIN => clk_fb_in, -- Clock input (from IBUFG, BUFG or DCM) - RST => dcm_rst(1) -- DCM asynchronous reset input - ); - - dcm_rst(1) <= not locked(0); - -dcm_fsm: - process(rst, clk_in) - begin - if rst = '1' then - state_q <= s0; - dcm_rst(0) <= '0'; - cnt_q <= "11111"; - error_out <= '0'; - locked_out <= '0'; - dcm1_locked <= (others => '0'); - dcm2_locked <= (others => '0'); - elsif rising_edge(clk_in) then - case state_q is - when s0 => - state_q <= s1; - - when s1 => - cnt_q <= cnt_q - 1; - if cnt_q = 0 then - dcm_rst(0) <= '1'; - state_q <= s2; - end if; - - when s2 => - cnt_q <= cnt_q - 1; - if cnt_q = 0 then - dcm_rst(0) <= '0'; - state_q <= s3; - end if; - - when s3 => - if dcm1_locked(2)='1' and dcm2_locked(2)='1' then - state_q <= s4; - error_out <= '0'; - end if; - - when s4 => - if dcm1_locked(2)='1' and dcm2_locked(2)='1' then - locked_out <= '1'; - else - error_out <= '1'; - end if; - end case; - - -- synchronize 'dcm1_locked' - dcm1_locked <= dcm1_locked(1 downto 0) & locked(0); - dcm2_locked <= dcm2_locked(1 downto 0) & locked(1); - - end if; - end process; - -end architecture tech; - - diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/ddr_phy_virtex4.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/ddr_phy_virtex4.vhd deleted file mode 100644 index f5ab332..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/src/ddr_phy_virtex4.vhd +++ /dev/null @@ -1,389 +0,0 @@ -------------------------------------------------------------------------- --- Project: SDRAM controller --- This file: DDR physical layer (Virtex-4 specific) --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.sdram_config.all; -use work.sdram_types.all; - -Library UNISIM; -use UNISIM.vcomponents.all; - -entity ddr_phy is - Port ( - sys_rst : in STD_LOGIC; - sys_clk0 : in STD_LOGIC; - sys_clk270 : in STD_LOGIC; - u_tag_in : in user_tag_t; - u_tag_rd : out user_tag_t; - u_tag_wr : out user_tag_t; - read_clk : in STD_LOGIC; - phy_ctrl : in phy_ctrl_t; - part_ctrl : in part_ctrl_t; - sdr_data_w : in unsigned(SDR_DATA_WIDTH-1 downto 0); - sdr_dm_wr_in : in unsigned(SDR_DM_WIDTH-1 downto 0); - sdr_dm_rd_in : in unsigned(SDR_DM_WIDTH-1 downto 0); - sdr_dm_rd_out : out unsigned(SDR_DM_WIDTH-1 downto 0); - sdr_data_r : out unsigned(SDR_DATA_WIDTH-1 downto 0); - sdr_data_vld : out STD_LOGIC; - sdr_data_req_w : out STD_LOGIC; - sdr_data_req_r : out STD_LOGIC; - part_clk_p : out STD_LOGIC; - part_clk_n : out STD_LOGIC; - part_dm : out unsigned(DDR_DM_WIDTH-1 downto 0); - part_dqs : inout unsigned(DDR_DQS_WIDTH-1 downto 0); - part_data : inout unsigned(DDR_DATA_WIDTH-1 downto 0); - part_ba : out unsigned(DDR_BANK_WIDTH-1 downto 0); - part_addr : out unsigned(DDR_ADDR_WIDTH-1 downto 0); - part_cs_n : out STD_LOGIC; - part_we_n : out STD_LOGIC; - part_cas_n : out STD_LOGIC; - part_ras_n : out STD_LOGIC; - part_cke : out STD_LOGIC - ); -end ddr_phy; - -architecture tech of ddr_phy is - - signal dqs_drive : std_logic; - signal drive : std_logic; - signal dqs : unsigned(DDR_DQS_WIDTH-1 downto 0); - signal dqs_zen : unsigned(DDR_DQS_WIDTH-1 downto 0); - signal dqs_rst : std_logic; - signal ddr_data_w : unsigned(DDR_DATA_WIDTH-1 downto 0); - signal data_r : unsigned(SDR_DATA_WIDTH-1 downto 0); - signal data_reg_r : unsigned(SDR_DATA_WIDTH-1 downto 0); - signal drive270 : unsigned(DDR_DATA_WIDTH-1 downto 0); - signal part_ctrl_reg : part_ctrl_t; - signal we_reg : std_logic; - signal read_en : std_logic; - - type u_tag_array_t is array (natural range 0 to 4) of user_tag_t; - signal u_tag_pipe : u_tag_array_t; - - type dm_out_array_t is array (natural range 0 to 4) of unsigned(SDR_DM_WIDTH-1 downto 0); - signal dm_out_pipe : dm_out_array_t; - -begin - ------------------------------------------------------------------------------------------------------------------------------------------------- -utag_pipe: - process(sys_rst, sys_clk0) - begin - if rising_edge(sys_clk0) then - for i in u_tag_pipe'length-1 downto 1 loop - u_tag_pipe(i) <= u_tag_pipe(i-1); - end loop; - if phy_ctrl.utag_we = '1' then - u_tag_pipe(0) <= u_tag_in; - end if; - end if; - end process; - -dmout_pipe: - process(sys_rst, sys_clk0) - begin - if rising_edge(sys_clk0) then - for i in dm_out_pipe'length-1 downto 1 loop - dm_out_pipe(i) <= dm_out_pipe(i-1); - end loop; - if phy_ctrl.utag_we = '1' then - dm_out_pipe(0) <= sdr_dm_rd_in; - end if; - end if; - end process; - -WE_REGISTER: - process(sys_rst, sys_clk0) - begin - if sys_rst = '1' then - we_reg <= '0'; - elsif rising_edge(sys_clk0) then - we_reg <= phy_ctrl.we; - end if; - end process; - -DATA_DRIVE_GEN: - process(sys_clk0) - begin - if falling_edge(sys_clk0) then - dqs_rst <= not we_reg; - drive <= we_reg; - end if; - end process; - -DQS_DRIVE_GEN: - process(sys_clk0) - variable p : unsigned(1 downto 0); - begin - if rising_edge(sys_clk0) then - if phy_ctrl.drive_en = '1' then - p := (others => '1'); - else - p := p(p'left-1 downto 0) & '0'; - end if; - end if; - dqs_drive <= p(p'left); - end process; - ------------------------------------------------------------------------------------------------------------------------------------------------- --- SDRAM Clock -ODDR_clk_p : ODDR - generic map - ( - DDR_CLK_EDGE => "OPPOSITE_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE" - INIT => '0', -- Initial value for Q port ('1' or '0') - SRTYPE => "SYNC" -- Reset Type ("ASYNC" or "SYNC") - ) - port map ( - Q => part_clk_p, -- 1-bit DDR output - C => sys_clk0, -- 1-bit clock input - CE => '1', -- 1-bit clock enable input - D1 => '1', -- 1-bit data input (positive edge) - D2 => '0', -- 1-bit data input (negative edge) - R => '0', -- 1-bit reset input - S => '0' -- 1-bit set input - ); - -ODDR_clk_n : ODDR - generic map - ( - DDR_CLK_EDGE => "OPPOSITE_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE" - INIT => '0', -- Initial value for Q port ('1' or '0') - SRTYPE => "SYNC" -- Reset Type ("ASYNC" or "SYNC") - ) - port map ( - Q => part_clk_n, -- 1-bit DDR output - C => sys_clk0, -- 1-bit clock input - CE => '1', -- 1-bit clock enable input - D1 => '0', -- 1-bit data input (positive edge) - D2 => '1', -- 1-bit data input (negative edge) - R => '0', -- 1-bit reset input - S => '0' -- 1-bit set input - ); - ------------------------------------------------------------------------------------------------------------------------------------------------- --- Data OUT DDR-FFs -gen_ddr_data_out: - for n in 0 to DDR_DATA_WIDTH-1 generate - begin - ODDR_data : ODDR - generic map - ( - DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE" - INIT => '0', -- Initial value for Q port ('1' or '0') - SRTYPE => "SYNC" -- Reset Type ("ASYNC" or "SYNC") - ) - port map ( - Q => ddr_data_w(n), -- 1-bit DDR output - C => sys_clk270, -- 1-bit clock input - CE => '1', -- 1-bit clock enable input - D1 => sdr_data_w(n + DDR_DATA_WIDTH), -- 1-bit data input (positive edge) - D2 => sdr_data_w(n), -- 1-bit data input (negative edge) - R => '0', -- 1-bit reset input - S => '0' -- 1-bit set input - ); - end generate gen_ddr_data_out; - --- Sample tristate on clock90 - process (sys_clk270) - begin - if rising_edge(sys_clk270) then - for n in 0 to DDR_DATA_WIDTH-1 loop - drive270(n) <= drive; - end loop; - end if; - end process; - --- Output mux -out_mux_data: - for n in 0 to DDR_DATA_WIDTH-1 generate - part_data(n) <= ddr_data_w(n) when drive270(n) = '1' else 'Z'; - end generate; - ------------------------------------------------------------------------------------------------------------------------------------------------- --- Data-mask OUT DDR-FFs -gen_ddr_dm_out: - for n in 0 to DDR_DM_WIDTH-1 generate - begin - ODDR_dm : ODDR - generic map - ( - DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE" - INIT => '0', -- Initial value for Q port ('1' or '0') - SRTYPE => "SYNC" -- Reset Type ("ASYNC" or "SYNC") - ) - port map ( - Q => part_dm(n), -- 1-bit DDR output - C => sys_clk270, -- 1-bit clock input - CE => '1', -- 1-bit clock enable input - D1 => sdr_dm_wr_in(n + DDR_DM_WIDTH), -- 1-bit data input (positive edge) - D2 => sdr_dm_wr_in(n), -- 1-bit data input (negative edge) - R => '0', -- 1-bit reset input - S => '0' -- 1-bit set input - ); - end generate gen_ddr_dm_out; - ------------------------------------------------------------------------------------------------------------------------------------------------- --- DQS OUT DDR-FFs -gen_dqs_out: - for n in 0 to DDR_DQS_WIDTH-1 generate - begin - ODDR_dqs : ODDR - generic map - ( - DDR_CLK_EDGE => "OPPOSITE_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE" - INIT => '0', -- Initial value for Q port ('1' or '0') - SRTYPE => "SYNC" -- Reset Type ("ASYNC" or "SYNC") - ) - port map ( - Q => dqs(n), -- 1-bit DDR output - C => sys_clk0, -- 1-bit clock input - CE => '1', -- 1-bit clock enable input - D2 => '0', -- 1-bit data input (positive edge) - D1 => '1', -- 1-bit data input (negative edge) - R => dqs_rst, -- 1-bit reset input - S => '0' -- 1-bit set input - ); - end generate gen_dqs_out; - --- Tristate-Control fuer dqs - process (sys_clk0) is - variable zctrl : boolean; - begin - if rising_edge(sys_clk0) then - if dqs_drive = '1' then - zctrl := false; - else - zctrl := true; - end if; - if zctrl then - dqs_zen <= (others => '1'); - else - dqs_zen <= (others => '0'); - end if; - end if; - end process; - --- Tristate-Buffer fuer dqs -gen_out_mux_dqs: - for n in 0 to DDR_DQS_WIDTH-1 generate - part_dqs(n) <= 'Z' when dqs_zen(n)='1' else dqs(n); - end generate gen_out_mux_dqs; - ------------------------------------------------------------------------------------------------------------------------------------------------- - process (sys_rst, sys_clk0) is - begin - if sys_rst = '1' then - part_ctrl_reg.cmd <= COMMAND(SD_DESELECT); - part_ctrl_reg.ba <= (others=>'0'); - part_ctrl_reg.addr <= (others=>'0'); - part_ctrl_reg.cke <= '0'; - elsif rising_edge(sys_clk0) then - part_ctrl_reg <= part_ctrl; - end if; - end process; - - process (sys_clk0) is - begin - if falling_edge(sys_clk0) then - part_ras_n <= part_ctrl_reg.cmd.ras_n; - part_cas_n <= part_ctrl_reg.cmd.cas_n; - part_we_n <= part_ctrl_reg.cmd.we_n; - part_cs_n <= part_ctrl_reg.cmd.cs_n; - part_ba <= part_ctrl_reg.ba; - part_addr <= part_ctrl_reg.addr; - part_cke <= part_ctrl_reg.cke; - end if; - end process; - ------------------------------------------------------------------ --- READ DATA Processing ------------------------------------------------------------------ -gen_ddr_data_in: - for n in 0 to DDR_DATA_WIDTH-1 generate - begin - IDDR_data : IDDR - generic map - ( - DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE", "SAME_EDGE" or "SAME_EDGE_PIPELINED" - INIT_Q1 => '0', -- Initial value of Q1: '0' or '1' - INIT_Q2 => '0', -- Initial value of Q2: '0' or '1' - SRTYPE => "SYNC" -- Set/Reset type: "SYNC" or "ASYNC" - ) - port map - ( - Q1 => data_r(n), -- 1-bit output for positive edge of clock - Q2 => data_r(n + DDR_DATA_WIDTH), -- 1-bit output for negative edge of clock - C => read_clk, -- 1-bit clock input - CE => read_en, -- 1-bit clock enable input - D => part_data(n), -- 1-bit DDR data input - R => '0', -- 1-bit reset - S => '0' -- 1-bit set - ); - end generate; - - -data_sample_stage: - process (sys_clk0) - begin - if falling_edge(sys_clk0) then - data_reg_r <= data_r; - end if; - end process; - -misc_flags_and_data_out: - process (sys_rst, sys_clk0) - variable p : unsigned(3 downto 0); - begin - if sys_rst = '1' then - p := (others => '0'); - read_en <= '0'; - sdr_data_vld <= '0'; - sdr_data_req_w <= '0'; - sdr_data_req_r <= '0'; - elsif rising_edge(sys_clk0) then - sdr_data_r <= data_reg_r; - if p(3) = '1' then - u_tag_rd <= u_tag_pipe(4); - sdr_dm_rd_out <= dm_out_pipe(4); - end if; - if phy_ctrl.we = '1' then - u_tag_wr <= u_tag_pipe(0); - end if; - sdr_data_req_w <= phy_ctrl.we; - sdr_data_req_r <= phy_ctrl.re; - sdr_data_vld <= p(3); - read_en <= p(1); - if phy_ctrl.re = '1' then - p := p(p'left-1 downto 0) & '1'; - else - p := p(p'left-1 downto 0) & '0'; - end if; - end if; - end process; - ------------------------------------------------------------------------------------------- -end tech; diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/fifo_sync.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/fifo_sync.vhd deleted file mode 100644 index 02ad3a7..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/src/fifo_sync.vhd +++ /dev/null @@ -1,111 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: Dual-ported register file with asynchrous read - --- Copyright (C) 2007 J. Ahrensfeld - --- This library is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. - --- This library is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. - --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the Free Software --- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - --- For questions and ideas, please contact the author at jens@jayfield.org - ------------------------------------------------------------------------ - -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -use work.fifo_ctrl_pkg.all; - -entity fifo_sync is - Generic ( - addr_width : natural := 4; - data_width : natural := 8; - almost_full_thresh : integer := 12; - almost_empty_thresh : integer := 4 - ); - Port - ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - we : in STD_LOGIC; - re : in STD_LOGIC; - fifo_full : out STD_LOGIC; - fifo_empty : out STD_LOGIC; - fifo_afull : out STD_LOGIC; - fifo_aempty : out STD_LOGIC; - data_w : in unsigned (data_width-1 downto 0); - data_r : out unsigned (data_width-1 downto 0) - ); -end fifo_sync; - -architecture Behavioral of fifo_sync is - - signal mem_we : STD_LOGIC; - signal ptr_w : unsigned (addr_width-1 downto 0); - signal ptr_r : unsigned (addr_width-1 downto 0); - signal full : STD_LOGIC; - signal empty : STD_LOGIC; - signal almost_full : STD_LOGIC; - signal almost_empty : STD_LOGIC; - -begin - - mem_we <= we; - fifo_full <= full; - fifo_empty <= empty; - fifo_afull <= almost_full; - fifo_aempty <= almost_empty; - - inst_fifo_sync_ctrl: entity work.fifo_sync_ctrl - GENERIC MAP - ( - addr_width => addr_width, - almost_full_thresh => almost_full_thresh, - almost_empty_thresh => almost_empty_thresh - ) - PORT MAP - ( - rst => rst, - clk => clk, - we => we, - re => re, - ptr_w => ptr_w, - ptr_r => ptr_r, - fifo_full => full, - fifo_empty => empty, - fifo_afull => almost_full, - fifo_aempty => almost_empty - - ); - - inst_dpram_1w1r: entity work.dpram_1w1r_dist - GENERIC MAP ( - addr_width => addr_width, - data_width => data_width - ) - PORT MAP( - clka => clk, - clkb => clk, - en_a => '1', - en_b => '1', - we_a => mem_we, - addr_a => ptr_w, - addr_b => ptr_r, - din_a => data_w, - dout_b => data_r - ); - -end Behavioral; - diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/mt46v16m16.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/mt46v16m16.vhd deleted file mode 100644 index 356bb28..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/src/mt46v16m16.vhd +++ /dev/null @@ -1,1320 +0,0 @@ ------------------------------------------------------------------------------------------ --- --- File Name: MT46V16M16.VHD --- Version: 2.1 --- Date: January 14th, 2002 --- Model: Behavioral --- Simulator: NCDesktop - http://www.cadence.com --- ModelSim PE - http://www.model.com --- --- Dependencies: None --- --- Author: Son P. Huynh --- Email: sphuynh@micron.com --- Phone: (208) 368-3825 --- Company: Micron Technology, Inc. --- Part Number: MT46V16M16 (4 Mb x 16 x 4 Banks) --- --- Description: Micron 256 Mb SDRAM DDR (Double Data Rate) --- --- Limitation: Doesn't model internal refresh counter --- --- Note: --- --- Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY --- WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY --- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR --- A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT. --- --- Copyright (c) 1998 Micron Semiconductor Products, Inc. --- All rights researved --- --- Rev Author Date Changes --- --- ---------------------------- ---------- ------------------------------------- --- 2.1 Son P. Huynh 01/14/2002 - Fix Burst_counter --- Micron Technology, Inc. --- --- 2.0 Son P. Huynh 11/08/2001 - Second release --- Micron Technology, Inc. - Rewrote and remove SHARED VARIABLE --- ------------------------------------------------------------------------------------------ - -LIBRARY IEEE; - USE IEEE.STD_LOGIC_1164.ALL; - USE IEEE.STD_LOGIC_UNSIGNED.ALL; - USE IEEE.STD_LOGIC_ARITH.ALL; - -ENTITY MT46V16M16 IS - GENERIC ( -- Timing for -75Z CL2 - tCK : TIME := 7.500 ns; - tCH : TIME := 3.375 ns; -- 0.45*tCK - tCL : TIME := 3.375 ns; -- 0.45*tCK - tDH : TIME := 0.500 ns; - tDS : TIME := 0.500 ns; - tIH : TIME := 0.900 ns; - tIS : TIME := 0.900 ns; - tMRD : TIME := 15.000 ns; - tRAS : TIME := 40.000 ns; - tRAP : TIME := 20.000 ns; - tRC : TIME := 65.000 ns; - tRFC : TIME := 75.000 ns; - tRCD : TIME := 20.000 ns; - tRP : TIME := 20.000 ns; - tRRD : TIME := 15.000 ns; - tWR : TIME := 15.000 ns; - addr_bits : INTEGER := 13; - data_bits : INTEGER := 16; - cols_bits : INTEGER := 9 - ); - PORT ( - Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z'); - Dqs : INOUT STD_LOGIC_VECTOR (1 DOWNTO 0) := "ZZ"; - Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); - Ba : IN STD_LOGIC_VECTOR (1 DOWNTO 0); - Clk : IN STD_LOGIC; - Clk_n : IN STD_LOGIC; - Cke : IN STD_LOGIC; - Cs_n : IN STD_LOGIC; - Ras_n : IN STD_LOGIC; - Cas_n : IN STD_LOGIC; - We_n : IN STD_LOGIC; - Dm : IN STD_LOGIC_VECTOR (1 DOWNTO 0) - ); -END MT46V16M16; - -ARCHITECTURE behave OF MT46V16M16 IS - -- Array for Read pipeline - TYPE Array_Read_cmnd IS ARRAY (8 DOWNTO 0) OF STD_LOGIC; - TYPE Array_Read_bank IS ARRAY (8 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0); - TYPE Array_Read_cols IS ARRAY (8 DOWNTO 0) OF STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0); - - -- Array for Write pipeline - TYPE Array_Write_cmnd IS ARRAY (2 DOWNTO 0) OF STD_LOGIC; - TYPE Array_Write_bank IS ARRAY (2 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0); - TYPE Array_Write_cols IS ARRAY (2 DOWNTO 0) OF STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0); - - -- Array for Auto Precharge - TYPE Array_Read_precharge IS ARRAY (3 DOWNTO 0) OF STD_LOGIC; - TYPE Array_Write_precharge IS ARRAY (3 DOWNTO 0) OF STD_LOGIC; - TYPE Array_Count_precharge IS ARRAY (3 DOWNTO 0) OF INTEGER; - - -- Array for Manual Precharge - TYPE Array_A10_precharge IS ARRAY (8 DOWNTO 0) OF STD_LOGIC; - TYPE Array_Bank_precharge IS ARRAY (8 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0); - TYPE Array_Cmnd_precharge IS ARRAY (8 DOWNTO 0) OF STD_LOGIC; - - -- Array for Burst Terminate - TYPE Array_Cmnd_bst IS ARRAY (8 DOWNTO 0) OF STD_LOGIC; - - -- Array for Memory Access - TYPE Array_ram_type IS ARRAY (2**cols_bits - 1 DOWNTO 0) OF STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0); - TYPE Array_ram_pntr IS ACCESS Array_ram_type; - TYPE Array_ram_stor IS ARRAY (2**addr_bits - 1 DOWNTO 0) OF Array_ram_pntr; - - -- Data pair - SIGNAL Dq_pair : STD_LOGIC_VECTOR (2 * data_bits - 1 DOWNTO 0); - SIGNAL Dm_pair : STD_LOGIC_VECTOR (3 DOWNTO 0); - - -- Mode Register - SIGNAL Mode_reg : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0'); - - -- Command Decode Variables - SIGNAL Active_enable, Aref_enable, Burst_term, Ext_mode_enable : STD_LOGIC := '0'; - SIGNAL Mode_reg_enable, Prech_enable, Read_enable, Write_enable : STD_LOGIC := '0'; - - -- Burst Length Decode Variables - SIGNAL Burst_length_2, Burst_length_4, Burst_length_8, Burst_length_f : STD_LOGIC := '0'; - - -- Cas Latency Decode Variables - SIGNAL Cas_latency_15, Cas_latency_2, Cas_latency_25, Cas_latency_3, Cas_latency_4 : STD_LOGIC := '0'; - - -- Internal Control Signals - SIGNAL Cs_in, Ras_in, Cas_in, We_in : STD_LOGIC := '0'; - - -- System Clock - SIGNAL Sys_clk : STD_LOGIC := '0'; - - -- Dqs buffer - SIGNAL Dqs_out : STD_LOGIC_VECTOR (1 DOWNTO 0) := "ZZ"; - -BEGIN - -- Strip the strength - Cs_in <= To_X01 (Cs_n); - Ras_in <= To_X01 (Ras_n); - Cas_in <= To_X01 (Cas_n); - We_in <= To_X01 (We_n); - - -- Commands Decode - Active_enable <= NOT(Cs_in) AND NOT(Ras_in) AND Cas_in AND We_in; - Aref_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND We_in; - Burst_term <= NOT(Cs_in) AND Ras_in AND Cas_in AND NOT(We_in); - Ext_mode_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in) AND Ba(0) AND NOT(Ba(1)); - Mode_reg_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in) AND NOT(Ba(0)) AND NOT(Ba(1)); - Prech_enable <= NOT(Cs_in) AND NOT(Ras_in) AND Cas_in AND NOT(We_in); - Read_enable <= NOT(Cs_in) AND Ras_in AND NOT(Cas_in) AND We_in; - Write_enable <= NOT(Cs_in) AND Ras_in AND NOT(Cas_in) AND NOT(We_in); - - -- Burst Length Decode - Burst_length_2 <= NOT(Mode_reg(2)) AND NOT(Mode_reg(1)) AND Mode_reg(0); - Burst_length_4 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND NOT(Mode_reg(0)); - Burst_length_8 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND Mode_reg(0); - Burst_length_f <= (Mode_reg(2)) AND Mode_reg(1) AND Mode_reg(0); - - -- CAS Latency Decode - Cas_latency_15 <= Mode_reg(6) AND NOT(Mode_reg(5)) AND (Mode_reg(4)); - Cas_latency_2 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND NOT(Mode_reg(4)); - Cas_latency_25 <= Mode_reg(6) AND Mode_reg(5) AND NOT(Mode_reg(4)); - Cas_latency_3 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND Mode_reg(4); - Cas_latency_4 <= (Mode_reg(6)) AND NOT(Mode_reg(5)) AND NOT(Mode_reg(4)); - - -- Dqs buffer - Dqs <= Dqs_out; - - -- - -- System Clock - -- - int_clk : PROCESS (Clk, Clk_n) - VARIABLE ClkZ, CkeZ : STD_LOGIC := '0'; - begin - IF Clk = '1' AND Clk_n = '0' THEN - ClkZ := '1'; - CkeZ := Cke; - ELSIF Clk = '0' AND Clk_n = '1' THEN - ClkZ := '0'; - END IF; - Sys_clk <= CkeZ AND ClkZ; - END PROCESS; - - -- - -- Main Process - -- - state_register : PROCESS - -- Precharge Variables - VARIABLE Pc_b0, Pc_b1, Pc_b2, Pc_b3 : STD_LOGIC := '0'; - - -- Activate Variables - VARIABLE Act_b0, Act_b1, Act_b2, Act_b3 : STD_LOGIC := '1'; - - -- Data IO variables - VARIABLE Data_in_enable, Data_out_enable : STD_LOGIC := '0'; - - -- Internal address mux variables - VARIABLE Cols_brst : STD_LOGIC_VECTOR (2 DOWNTO 0); - VARIABLE Prev_bank : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"; - VARIABLE Bank_addr : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"; - VARIABLE Cols_addr : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0); - VARIABLE Rows_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); - VARIABLE B0_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); - VARIABLE B1_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); - VARIABLE B2_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); - VARIABLE B3_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); - - -- DLL Reset variables - VARIABLE DLL_enable : STD_LOGIC := '0'; - VARIABLE DLL_reset : STD_LOGIC := '0'; - VARIABLE DLL_done : STD_LOGIC := '0'; - VARIABLE DLL_count : INTEGER := 0; - - -- Timing Check - VARIABLE MRD_chk : TIME := 0 ns; - VARIABLE RFC_chk : TIME := 0 ns; - VARIABLE RRD_chk : TIME := 0 ns; - VARIABLE RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3 : TIME := 0 ns; - VARIABLE RAP_chk0, RAP_chk1, RAP_chk2, RAP_chk3 : TIME := 0 ns; - VARIABLE RC_chk0, RC_chk1, RC_chk2, RC_chk3 : TIME := 0 ns; - VARIABLE RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3 : TIME := 0 ns; - VARIABLE RP_chk0, RP_chk1, RP_chk2, RP_chk3 : TIME := 0 ns; - VARIABLE WR_chk0, WR_chk1, WR_chk2, WR_chk3 : TIME := 0 ns; - - -- Read pipeline variables - VARIABLE Read_cmnd : Array_Read_cmnd; - VARIABLE Read_bank : Array_Read_bank; - VARIABLE Read_cols : Array_Read_cols; - - -- Write pipeline variables - VARIABLE Write_cmnd : Array_Write_cmnd; - VARIABLE Write_bank : Array_Write_bank; - VARIABLE Write_cols : Array_Write_cols; - - -- Auto Precharge variables - VARIABLE Read_precharge : Array_Read_precharge := ('0' & '0' & '0' & '0'); - VARIABLE Write_precharge : Array_Write_precharge := ('0' & '0' & '0' & '0'); - VARIABLE Count_precharge : Array_Count_precharge := ( 0 & 0 & 0 & 0 ); - - -- Manual Precharge variables - VARIABLE A10_precharge : Array_A10_precharge; - VARIABLE Bank_precharge : Array_Bank_precharge; - VARIABLE Cmnd_precharge : Array_Cmnd_precharge; - - -- Burst Terminate variable - VARIABLE Cmnd_bst : Array_Cmnd_bst; - - -- Memory Banks - VARIABLE Bank0 : Array_ram_stor; - VARIABLE Bank1 : Array_ram_stor; - VARIABLE Bank2 : Array_ram_stor; - VARIABLE Bank3 : Array_ram_stor; - - -- Burst Counter - VARIABLE Burst_counter : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0); - - -- Internal Dqs initialize - VARIABLE Dqs_int : STD_LOGIC := '0'; - - -- Data buffer for DM Mask - VARIABLE Data_buf : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z'); - - -- - -- Initialize empty rows - -- - PROCEDURE Init_mem (Bank : STD_LOGIC_VECTOR; Row_index : INTEGER) IS - VARIABLE i, j : INTEGER := 0; - BEGIN - IF Bank = "00" THEN - IF Bank0 (Row_index) = NULL THEN -- Check to see if row empty - Bank0 (Row_index) := NEW Array_ram_type; -- Open new row for access - FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP -- Filled row with zeros - FOR j IN (data_bits - 1) DOWNTO 0 LOOP - Bank0 (Row_index) (i) (j) := '0'; - END LOOP; - END LOOP; - END IF; - ELSIF Bank = "01" THEN - IF Bank1 (Row_index) = NULL THEN - Bank1 (Row_index) := NEW Array_ram_type; - FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP - FOR j IN (data_bits - 1) DOWNTO 0 LOOP - Bank1 (Row_index) (i) (j) := '0'; - END LOOP; - END LOOP; - END IF; - ELSIF Bank = "10" THEN - IF Bank2 (Row_index) = NULL THEN - Bank2 (Row_index) := NEW Array_ram_type; - FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP - FOR j IN (data_bits - 1) DOWNTO 0 LOOP - Bank2 (Row_index) (i) (j) := '0'; - END LOOP; - END LOOP; - END IF; - ELSIF Bank = "11" THEN - IF Bank3 (Row_index) = NULL THEN - Bank3 (Row_index) := NEW Array_ram_type; - FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP - FOR j IN (data_bits - 1) DOWNTO 0 LOOP - Bank3 (Row_index) (i) (j) := '0'; - END LOOP; - END LOOP; - END IF; - END IF; - END; - - -- - -- Burst Counter - -- - PROCEDURE Burst_decode IS - VARIABLE Cols_temp : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0) := (OTHERS => '0'); - BEGIN - -- Advance burst counter - Burst_counter := Burst_counter + 1; - - -- Burst Type - IF Mode_reg (3) = '0' THEN - Cols_temp := Cols_addr + 1; - ELSIF Mode_reg (3) = '1' THEN - Cols_temp (2) := Burst_counter (2) XOR Cols_brst (2); - Cols_temp (1) := Burst_counter (1) XOR Cols_brst (1); - Cols_temp (0) := Burst_counter (0) XOR Cols_brst (0); - END IF; - - -- Burst Length - IF Burst_length_2 = '1' THEN - Cols_addr (0) := Cols_temp (0); - ELSIF Burst_length_4 = '1' THEN - Cols_addr (1 DOWNTO 0) := Cols_temp (1 DOWNTO 0); - ELSIF Burst_length_8 = '1' THEN - Cols_addr (2 DOWNTO 0) := Cols_temp (2 DOWNTO 0); - ELSE - Cols_addr := Cols_temp; - END IF; - - -- Data counter - IF Burst_length_2 = '1' THEN - IF Burst_counter >= 2 THEN - IF Data_in_enable = '1' THEN - Data_in_enable := '0'; - ELSIF Data_out_enable = '1' THEN - Data_out_enable := '0'; - END IF; - END IF; - ELSIF Burst_length_4 = '1' THEN - IF Burst_counter >= 4 THEN - IF Data_in_enable = '1' THEN - Data_in_enable := '0'; - ELSIF Data_out_enable = '1' THEN - Data_out_enable := '0'; - END IF; - END IF; - ELSIF Burst_length_8 = '1' THEN - IF Burst_counter >= 8 THEN - IF Data_in_enable = '1' THEN - Data_in_enable := '0'; - ELSIF Data_out_enable = '1' THEN - Data_out_enable := '0'; - END IF; - END IF; - END IF; - END; - - BEGIN - WAIT ON Sys_clk; - - -- - -- Manual Precharge Pipeline - -- - IF ((Sys_clk'EVENT AND Sys_clk = '0') OR (Sys_clk'EVENT AND Sys_clk = '1')) THEN - -- A10 Precharge Pipeline - A10_precharge(0) := A10_precharge(1); - A10_precharge(1) := A10_precharge(2); - A10_precharge(2) := A10_precharge(3); - A10_precharge(3) := A10_precharge(4); - A10_precharge(4) := A10_precharge(5); - A10_precharge(5) := A10_precharge(6); - A10_precharge(6) := A10_precharge(7); - A10_precharge(7) := A10_precharge(8); - A10_precharge(8) := '0'; - - -- Bank Precharge Pipeline - Bank_precharge(0) := Bank_precharge(1); - Bank_precharge(1) := Bank_precharge(2); - Bank_precharge(2) := Bank_precharge(3); - Bank_precharge(3) := Bank_precharge(4); - Bank_precharge(4) := Bank_precharge(5); - Bank_precharge(5) := Bank_precharge(6); - Bank_precharge(6) := Bank_precharge(7); - Bank_precharge(7) := Bank_precharge(8); - Bank_precharge(8) := "00"; - - -- Command Precharge Pipeline - Cmnd_precharge(0) := Cmnd_precharge(1); - Cmnd_precharge(1) := Cmnd_precharge(2); - Cmnd_precharge(2) := Cmnd_precharge(3); - Cmnd_precharge(3) := Cmnd_precharge(4); - Cmnd_precharge(4) := Cmnd_precharge(5); - Cmnd_precharge(5) := Cmnd_precharge(6); - Cmnd_precharge(6) := Cmnd_precharge(7); - Cmnd_precharge(7) := Cmnd_precharge(8); - Cmnd_precharge(8) := '0'; - - -- Terminate Read if same bank or all banks - IF ((Cmnd_precharge (0) = '1') AND - (Bank_precharge (0) = Bank_addr OR A10_precharge (0) = '1') AND - (Data_out_enable = '1')) THEN - Data_out_enable := '0'; - END IF; - END IF; - - -- - -- Burst Terminate Pipeline - -- - IF ((Sys_clk'EVENT AND Sys_clk = '0') OR (Sys_clk'EVENT AND Sys_clk = '1')) THEN - -- Burst Terminate pipeline - Cmnd_bst (0) := Cmnd_bst (1); - Cmnd_bst (1) := Cmnd_bst (2); - Cmnd_bst (2) := Cmnd_bst (3); - Cmnd_bst (3) := Cmnd_bst (4); - Cmnd_bst (4) := Cmnd_bst (5); - Cmnd_bst (5) := Cmnd_bst (6); - Cmnd_bst (6) := Cmnd_bst (7); - Cmnd_bst (7) := Cmnd_bst (8); - Cmnd_bst (8) := '0'; - - -- Terminate current Read - IF ((Cmnd_bst (0) = '1') AND (Data_out_enable = '1')) THEN - Data_out_enable := '0'; - END IF; - END IF; - - -- - -- Dq and Dqs Drivers - -- - IF ((Sys_clk'EVENT AND Sys_clk = '0') OR (Sys_clk'EVENT AND Sys_clk = '1')) THEN - -- Read Command Pipeline - Read_cmnd (0) := Read_cmnd (1); - Read_cmnd (1) := Read_cmnd (2); - Read_cmnd (2) := Read_cmnd (3); - Read_cmnd (3) := Read_cmnd (4); - Read_cmnd (4) := Read_cmnd (5); - Read_cmnd (5) := Read_cmnd (6); - Read_cmnd (6) := Read_cmnd (7); - Read_cmnd (7) := Read_cmnd (8); - Read_cmnd (8) := '0'; - - -- Read Bank Pipeline - Read_bank (0) := Read_bank (1); - Read_bank (1) := Read_bank (2); - Read_bank (2) := Read_bank (3); - Read_bank (3) := Read_bank (4); - Read_bank (4) := Read_bank (5); - Read_bank (5) := Read_bank (6); - Read_bank (6) := Read_bank (7); - Read_bank (7) := Read_bank (8); - Read_bank (8) := "00"; - - -- Read Column Pipeline - Read_cols (0) := Read_cols (1); - Read_cols (1) := Read_cols (2); - Read_cols (2) := Read_cols (3); - Read_cols (3) := Read_cols (4); - Read_cols (4) := Read_cols (5); - Read_cols (5) := Read_cols (6); - Read_cols (6) := Read_cols (7); - Read_cols (7) := Read_cols (8); - Read_cols (8) := (OTHERS => '0'); - - -- Initialize Read command - IF Read_cmnd (0) = '1' THEN - Data_out_enable := '1'; - Bank_addr := Read_bank (0); - Cols_addr := Read_cols (0); - Cols_brst := Cols_addr (2 DOWNTO 0); - Burst_counter := (OTHERS => '0'); - - -- Row address mux - CASE Bank_addr IS - WHEN "00" => Rows_addr := B0_row_addr; - WHEN "01" => Rows_addr := B1_row_addr; - WHEN "10" => Rows_addr := B2_row_addr; - WHEN OTHERS => Rows_addr := B3_row_addr; - END CASE; - END IF; - - -- Toggle Dqs during Read command - IF Data_out_enable = '1' THEN - Dqs_int := '0'; - IF Dqs_out = "00" THEN - Dqs_out <= "11"; - ELSIF Dqs_out = "11" THEN - Dqs_out <= "00"; - ELSE - Dqs_out <= "00"; - END IF; - ELSIF Data_out_enable = '0' AND Dqs_int = '0' THEN - Dqs_out <= "ZZ"; - END IF; - - -- Initialize Dqs for Read command - IF Read_cmnd (2) = '1' THEN - IF Data_out_enable = '0' THEN - Dqs_int := '1'; - Dqs_out <= "00"; - END IF; - END IF; - - -- Read Latch - IF Data_out_enable = '1' THEN - -- Initialize Memory - Init_mem (Bank_addr, CONV_INTEGER(Rows_addr)); - - -- Output Data - CASE Bank_addr IS - WHEN "00" => Dq <= Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - WHEN "01" => Dq <= Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - WHEN "10" => Dq <= Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - WHEN OTHERS => Dq <= Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - END CASE; - - -- Increase Burst Counter - Burst_decode; - ELSE - Dq <= (OTHERS => 'Z'); - END IF; - END IF; - - -- - -- Write FIFO and DM Mask Logic - -- - IF Sys_clk'EVENT AND Sys_clk = '1' THEN - -- Write command pipeline - Write_cmnd (0) := Write_cmnd (1); - Write_cmnd (1) := Write_cmnd (2); - Write_cmnd (2) := '0'; - - -- Write command pipeline - Write_bank (0) := Write_bank (1); - Write_bank (1) := Write_bank (2); - Write_bank (2) := "00"; - - -- Write column pipeline - Write_cols (0) := Write_cols (1); - Write_cols (1) := Write_cols (2); - Write_cols (2) := (OTHERS => '0'); - - -- Initialize Write command - IF Write_cmnd (0) = '1' THEN - Data_in_enable := '1'; - Bank_addr := Write_bank (0); - Cols_addr := Write_cols (0); - Cols_brst := Cols_addr (2 DOWNTO 0); - Burst_counter := (OTHERS => '0'); - - -- Row address mux - CASE Bank_addr IS - WHEN "00" => Rows_addr := B0_row_addr; - WHEN "01" => Rows_addr := B1_row_addr; - WHEN "10" => Rows_addr := B2_row_addr; - WHEN OTHERS => Rows_addr := B3_row_addr; - END CASE; - END IF; - - -- Write data - IF Data_in_enable = '1' THEN - -- Initialize memory - Init_mem (Bank_addr, CONV_INTEGER(Rows_addr)); - - -- Write first data - IF Dm_pair (1) = '0' OR Dm_pair (0) = '0' THEN - -- Data Buffer - CASE Bank_addr IS - WHEN "00" => Data_buf := Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - WHEN "01" => Data_buf := Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - WHEN "10" => Data_buf := Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - WHEN OTHERS => Data_buf := Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - END CASE; - - -- Perform DM Mask - IF Dm_pair (0) = '0' THEN - Data_buf ( 7 DOWNTO 0) := Dq_pair ( 7 DOWNTO 0); - END IF; - IF Dm_pair (1) = '0' THEN - Data_buf (15 DOWNTO 8) := Dq_pair (15 DOWNTO 8); - END IF; - - -- Write Data - CASE Bank_addr IS - WHEN "00" => Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; - WHEN "01" => Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; - WHEN "10" => Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; - WHEN OTHERS => Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; - END CASE; - END IF; - - -- Increase Burst Counter - Burst_decode; - - -- Write second data - IF Dm_pair (3) = '0' OR Dm_pair (2) = '0' THEN - -- Data Buffer - CASE Bank_addr IS - WHEN "00" => Data_buf := Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - WHEN "01" => Data_buf := Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - WHEN "10" => Data_buf := Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - WHEN OTHERS => Data_buf := Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - END CASE; - - -- Perform DM Mask - IF Dm_pair (2) = '0' THEN - Data_buf ( 7 DOWNTO 0) := Dq_pair (23 DOWNTO 16); - END IF; - IF Dm_pair (3) = '0' THEN - Data_buf (15 DOWNTO 8) := Dq_pair (31 DOWNTO 24); - END IF; - - -- Write Data - CASE Bank_addr IS - WHEN "00" => Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; - WHEN "01" => Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; - WHEN "10" => Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; - WHEN OTHERS => Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; - END CASE; - END IF; - - -- Increase Burst Counter - Burst_decode; - - -- tWR start and tWTR check - IF Dm_pair (3 DOWNTO 2) = "00" OR Dm_pair (1 DOWNTO 0) = "00" THEN - CASE Bank_addr IS - WHEN "00" => WR_chk0 := NOW; - WHEN "01" => WR_chk1 := NOW; - WHEN "10" => WR_chk2 := NOW; - WHEN OTHERS => WR_chk3 := NOW; - END CASE; - - -- tWTR check - ASSERT (Read_enable = '0') - REPORT "tWTR violation during Read" - SEVERITY WARNING; - END IF; - END IF; - END IF; - - -- - -- Auto Precharge Calculation - -- - IF Sys_clk'EVENT AND Sys_clk = '1' THEN - -- Precharge counter - IF Read_precharge (0) = '1' OR Write_precharge (0) = '1' THEN - Count_precharge (0) := Count_precharge (0) + 1; - END IF; - IF Read_precharge (1) = '1' OR Write_precharge (1) = '1' THEN - Count_precharge (1) := Count_precharge (1) + 1; - END IF; - IF Read_precharge (2) = '1' OR Write_precharge (2) = '1' THEN - Count_precharge (2) := Count_precharge (2) + 1; - END IF; - IF Read_precharge (3) = '1' OR Write_precharge (3) = '1' THEN - Count_precharge (3) := Count_precharge (3) + 1; - END IF; - - -- Read with AutoPrecharge Calculation - -- The device start internal precharge when: - -- 1. Meet tRAS requirement - -- 2. BL/2 cycles after command - IF ((Read_precharge(0) = '1') AND (NOW - RAS_chk0 >= tRAS)) THEN - IF ((Burst_length_2 = '1' AND Count_precharge(0) >= 1) OR - (Burst_length_4 = '1' AND Count_precharge(0) >= 2) OR - (Burst_length_8 = '1' AND Count_precharge(0) >= 4)) THEN - Pc_b0 := '1'; - Act_b0 := '0'; - RP_chk0 := NOW; - Read_precharge(0) := '0'; - END IF; - END IF; - IF ((Read_precharge(1) = '1') AND (NOW - RAS_chk1 >= tRAS)) THEN - IF ((Burst_length_2 = '1' AND Count_precharge(1) >= 1) OR - (Burst_length_4 = '1' AND Count_precharge(1) >= 2) OR - (Burst_length_8 = '1' AND Count_precharge(1) >= 4)) THEN - Pc_b1 := '1'; - Act_b1 := '0'; - RP_chk1 := NOW; - Read_precharge(1) := '0'; - END IF; - END IF; - IF ((Read_precharge(2) = '1') AND (NOW - RAS_chk2 >= tRAS)) THEN - IF ((Burst_length_2 = '1' AND Count_precharge(2) >= 1) OR - (Burst_length_4 = '1' AND Count_precharge(2) >= 2) OR - (Burst_length_8 = '1' AND Count_precharge(2) >= 4)) THEN - Pc_b2 := '1'; - Act_b2 := '0'; - RP_chk2 := NOW; - Read_precharge(2) := '0'; - END IF; - END IF; - IF ((Read_precharge(3) = '1') AND (NOW - RAS_chk3 >= tRAS)) THEN - IF ((Burst_length_2 = '1' AND Count_precharge(3) >= 1) OR - (Burst_length_4 = '1' AND Count_precharge(3) >= 2) OR - (Burst_length_8 = '1' AND Count_precharge(3) >= 4)) THEN - Pc_b3 := '1'; - Act_b3 := '0'; - RP_chk3 := NOW; - Read_precharge(3) := '0'; - END IF; - END IF; - - -- Write with AutoPrecharge Calculation - -- The device start internal precharge when: - -- 1. Meet tRAS requirement - -- 2. Two clock after last burst - -- Since tWR is time base, the model will compensate tRP - IF ((Write_precharge(0) = '1') AND (NOW - RAS_chk0 >= tRAS)) THEN - IF ((Burst_length_2 = '1' AND Count_precharge (0) >= 4) OR - (Burst_length_4 = '1' AND Count_precharge (0) >= 5) OR - (Burst_length_8 = '1' AND Count_precharge (0) >= 7)) THEN - Pc_b0 := '1'; - Act_b0 := '0'; - RP_chk0 := NOW - ((2 * tCK) - tWR); - Write_precharge(0) := '0'; - END IF; - END IF; - IF ((Write_precharge(1) = '1') AND (NOW - RAS_chk1 >= tRAS)) THEN - IF ((Burst_length_2 = '1' AND Count_precharge (1) >= 4) OR - (Burst_length_4 = '1' AND Count_precharge (1) >= 5) OR - (Burst_length_8 = '1' AND Count_precharge (1) >= 7)) THEN - Pc_b1 := '1'; - Act_b1 := '0'; - RP_chk1 := NOW - ((2 * tCK) - tWR); - Write_precharge(1) := '0'; - END IF; - END IF; - IF ((Write_precharge(2) = '1') AND (NOW - RAS_chk2 >= tRAS)) THEN - IF ((Burst_length_2 = '1' AND Count_precharge (2) >= 4) OR - (Burst_length_4 = '1' AND Count_precharge (2) >= 5) OR - (Burst_length_8 = '1' AND Count_precharge (2) >= 7)) THEN - Pc_b2 := '1'; - Act_b2 := '0'; - RP_chk2 := NOW - ((2 * tCK) - tWR); - Write_precharge(2) := '0'; - END IF; - END IF; - IF ((Write_precharge(3) = '1') AND (NOW - RAS_chk3 >= tRAS)) THEN - IF ((Burst_length_2 = '1' AND Count_precharge (3) >= 4) OR - (Burst_length_4 = '1' AND Count_precharge (3) >= 5) OR - (Burst_length_8 = '1' AND Count_precharge (3) >= 7)) THEN - Pc_b3 := '1'; - Act_b3 := '0'; - RP_chk3 := NOW - ((2 * tCK) - tWR); - Write_precharge(3) := '0'; - END IF; - END IF; - END IF; - - -- - -- DLL Counter - -- - IF Sys_clk'EVENT AND Sys_clk = '1' THEN - IF (DLL_Reset = '1' AND DLL_done = '0') THEN - DLL_count := DLL_count + 1; - IF (DLL_count >= 200) THEN - DLL_done := '1'; - END IF; - END IF; - END IF; - - -- - -- Control Logic - -- - IF Sys_clk'EVENT AND Sys_clk = '1' THEN - -- Auto Refresh - IF Aref_enable = '1' THEN - -- Auto Refresh to Auto Refresh - ASSERT (NOW - RFC_chk >= tRFC) - REPORT "tRFC violation during Auto Refresh" - SEVERITY WARNING; - - -- Precharge to Auto Refresh - ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND - (NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP)) - REPORT "tRP violation during Auto Refresh" - SEVERITY WARNING; - - -- Precharge to Auto Refresh - ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1') - REPORT "All banks must be Precharge before Auto Refresh" - SEVERITY WARNING; - - -- Record current tRFC time - RFC_chk := NOW; - END IF; - - -- Extended Load Mode Register - IF Ext_mode_enable = '1' THEN - IF (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1') THEN - IF (Addr (0) = '0') THEN - DLL_enable := '1'; - ELSE - DLL_enable := '0'; - END IF; - END IF; - - -- Precharge to EMR - ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1') - REPORT "All bank must be Precharged before Extended Mode Register" - SEVERITY WARNING; - - -- Precharge to EMR - ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND - (NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP)) - REPORT "tRP violation during Extended Load Register" - SEVERITY WARNING; - - -- LMR/EMR to EMR - ASSERT (NOW - MRD_chk >= tMRD) - REPORT "tMRD violation during Extended Mode Register" - SEVERITY WARNING; - - -- Record current tMRD time - MRD_chk := NOW; - END IF; - - -- Load Mode Register - IF Mode_reg_enable = '1' THEN - -- Register mode - Mode_reg <= Addr; - - -- DLL Reset - IF (DLL_enable = '1' AND Addr (8) = '1') THEN - DLL_reset := '1'; - DLL_done := '0'; - DLL_count := 0; - ELSIF (DLL_enable = '1' AND DLL_reset = '0' AND Addr (8) = '0') THEN - ASSERT (FALSE) - REPORT "DLL is ENABLE: DLL RESET is require" - SEVERITY WARNING; - ELSIF (DLL_enable = '0' AND Addr (8) = '1') THEN - ASSERT (FALSE) - REPORT "DLL is DISABLE: DLL RESET will be ignored" - SEVERITY WARNING; - END IF; - - -- Precharge to LMR - ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1') - REPORT "All bank must be Precharged before Load Mode Register" - SEVERITY WARNING; - - -- Precharge to EMR - ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND - (NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP)) - REPORT "tRP violation during Load Mode Register" - SEVERITY WARNING; - - -- LMR/ELMR to LMR - ASSERT (NOW - MRD_chk >= tMRD) - REPORT "tMRD violation during Load Mode Register" - SEVERITY WARNING; - - -- Check for invalid Burst Length - ASSERT ((Addr (2 DOWNTO 0) = "001") OR -- BL = 2 - (Addr (2 DOWNTO 0) = "010") OR -- BL = 4 - (Addr (2 DOWNTO 0) = "011")) -- BL = 8 - REPORT "Invalid Burst Length during Load Mode Register" - SEVERITY WARNING; - - -- Check for invalid CAS Latency - ASSERT ((Addr (6 DOWNTO 4) = "010") OR -- CL = 2.0 - (Addr (6 DOWNTO 4) = "110")) -- CL = 2.5 - REPORT "Invalid CAS Latency during Load Mode Register" - SEVERITY WARNING; - - -- Record current tMRD time - MRD_chk := NOW; - END IF; - - -- Active Block (latch Bank and Row Address) - IF Active_enable = '1' THEN - -- Activate an OPEN bank can corrupt data - ASSERT ((Ba = "00" AND Act_b0 = '0') OR - (Ba = "01" AND Act_b1 = '0') OR - (Ba = "10" AND Act_b2 = '0') OR - (Ba = "11" AND Act_b3 = '0')) - REPORT "Bank is already activated - data can be corrupted" - SEVERITY WARNING; - - -- Activate Bank 0 - IF Ba = "00" AND Pc_b0 = '1' THEN - -- Activate to Activate (same bank) - ASSERT (NOW - RC_chk0 >= tRC) - REPORT "tRC violation during Activate Bank 0" - SEVERITY WARNING; - - -- Precharge to Active - ASSERT (NOW - RP_chk0 >= tRP) - REPORT "tRP violation during Activate Bank 0" - SEVERITY WARNING; - - -- Record Variables for checking violation - Act_b0 := '1'; - Pc_b0 := '0'; - B0_row_addr := Addr; - RC_chk0 := NOW; - RCD_chk0 := NOW; - RAS_chk0 := NOW; - RAP_chk0 := NOW; - END IF; - - -- Activate Bank 1 - IF Ba = "01" AND Pc_b1 = '1' THEN - -- Activate to Activate (same bank) - ASSERT (NOW - RC_chk1 >= tRC) - REPORT "tRC violation during Activate Bank 1" - SEVERITY WARNING; - - -- Precharge to Active - ASSERT (NOW - RP_chk1 >= tRP) - REPORT "tRP violation during Activate Bank 1" - SEVERITY WARNING; - - -- Record Variables for checking violation - Act_b1 := '1'; - Pc_b1 := '0'; - B1_row_addr := Addr; - RC_chk1 := NOW; - RCD_chk1 := NOW; - RAS_chk1 := NOW; - RAP_chk1 := NOW; - END IF; - - -- Activate Bank 2 - IF Ba = "10" AND Pc_b2 = '1' THEN - -- Activate to Activate (same bank) - ASSERT (NOW - RC_chk2 >= tRC) - REPORT "tRC violation during Activate Bank 2" - SEVERITY WARNING; - - -- Precharge to Active - ASSERT (NOW - RP_chk2 >= tRP) - REPORT "tRP violation during Activate Bank 2" - SEVERITY WARNING; - - -- Record Variables for checking violation - Act_b2 := '1'; - Pc_b2 := '0'; - B2_row_addr := Addr; - RC_chk2 := NOW; - RCD_chk2 := NOW; - RAS_chk2 := NOW; - RAP_chk2 := NOW; - END IF; - - -- Activate Bank 3 - IF Ba = "11" AND Pc_b3 = '1' THEN - -- Activate to Activate (same bank) - ASSERT (NOW - RC_chk3 >= tRC) - REPORT "tRC violation during Activate Bank 3" - SEVERITY WARNING; - - -- Precharge to Active - ASSERT (NOW - RP_chk3 >= tRP) - REPORT "tRP violation during Activate Bank 3" - SEVERITY WARNING; - - -- Record Variables for checking violation - Act_b3 := '1'; - Pc_b3 := '0'; - B3_row_addr := Addr; - RC_chk3 := NOW; - RCD_chk3 := NOW; - RAS_chk3 := NOW; - RAP_chk3 := NOW; - END IF; - - -- Activate Bank A to Activate Bank B - IF (Prev_bank /= Ba) THEN - ASSERT (NOW - RRD_chk >= tRRD) - REPORT "tRRD violation during Activate" - SEVERITY WARNING; - END IF; - - -- AutoRefresh to Activate - ASSERT (NOW - RFC_chk >= tRFC) - REPORT "tRFC violation during Activate" - SEVERITY WARNING; - - -- Record Variables for Checking Violation - RRD_chk := NOW; - Prev_bank := Ba; - END IF; - - -- Precharge Block - Consider NOP if bank already precharged or in process of precharging - IF Prech_enable = '1' THEN - -- EMR or LMR to Precharge - ASSERT (NOW - MRD_chk >= tMRD) - REPORT "tMRD violation during Precharge" - SEVERITY WARNING; - - -- Precharge Bank 0 - IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "00")) AND Act_b0 = '1') THEN - Act_b0 := '0'; - Pc_b0 := '1'; - RP_chk0 := NOW; - - -- Activate to Precharge bank 0 - ASSERT (NOW - RAS_chk0 >= tRAS) - REPORT "tRAS violation during Precharge" - SEVERITY WARNING; - - -- tWR violation check for Write - ASSERT (NOW - WR_chk0 >= tWR) - REPORT "tWR violation during Precharge" - SEVERITY WARNING; - END IF; - - -- Precharge Bank 1 - IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "01")) AND Act_b1 = '1') THEN - Act_b1 := '0'; - Pc_b1 := '1'; - RP_chk1 := NOW; - - -- Activate to Precharge - ASSERT (NOW - RAS_chk1 >= tRAS) - REPORT "tRAS violation during Precharge" - SEVERITY WARNING; - - -- tWR violation check for Write - ASSERT (NOW - WR_chk1 >= tWR) - REPORT "tWR violation during Precharge" - SEVERITY WARNING; - END IF; - - -- Precharge Bank 2 - IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "10")) AND Act_b2 = '1') THEN - Act_b2 := '0'; - Pc_b2 := '1'; - RP_chk2 := NOW; - - -- Activate to Precharge - ASSERT (NOW - RAS_chk2 >= tRAS) - REPORT "tRAS violation during Precharge" - SEVERITY WARNING; - - -- tWR violation check for Write - ASSERT (NOW - WR_chk2 >= tWR) - REPORT "tWR violation during Precharge" - SEVERITY WARNING; - END IF; - - -- Precharge Bank 3 - IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "11")) AND Act_b3 = '1') THEN - Act_b3 := '0'; - Pc_b3 := '1'; - RP_chk3 := NOW; - - -- Activate to Precharge - ASSERT (NOW - RAS_chk3 >= tRAS) - REPORT "tRAS violation during Precharge" - SEVERITY WARNING; - - -- tWR violation check for Write - ASSERT (NOW - WR_chk3 >= tWR) - REPORT "tWR violation during Precharge" - SEVERITY WARNING; - END IF; - - -- Pipeline for READ - IF CAS_latency_15 = '1' THEN - A10_precharge (3) := Addr(10); - Bank_precharge (3) := Ba; - Cmnd_precharge (3) := '1'; - ELSIF CAS_latency_2 = '1' THEN - A10_precharge (4) := Addr(10); - Bank_precharge (4) := Ba; - Cmnd_precharge (4) := '1'; - ELSIF CAS_latency_25 = '1' THEN - A10_precharge (5) := Addr(10); - Bank_precharge (5) := Ba; - Cmnd_precharge (5) := '1'; - ELSIF CAS_latency_3 = '1' THEN - A10_precharge (6) := Addr(10); - Bank_precharge (6) := Ba; - Cmnd_precharge (6) := '1'; - ELSIF CAS_latency_4 = '1' THEN - A10_precharge (8) := Addr(10); - Bank_precharge (8) := Ba; - Cmnd_precharge (8) := '1'; - END IF; - END IF; - - -- Burst Terminate - IF Burst_term = '1' THEN - -- Pipeline for Read - IF CAS_latency_15 = '1' THEN - Cmnd_bst (3) := '1'; - ELSIF CAS_latency_2 = '1' THEN - Cmnd_bst (4) := '1'; - ELSIF CAS_latency_25 = '1' THEN - Cmnd_bst (5) := '1'; - ELSIF CAS_latency_3 = '1' THEN - Cmnd_bst (6) := '1'; - ELSIF CAS_latency_4 = '1' THEN - Cmnd_bst (8) := '1'; - END IF; - - -- Terminate Write - ASSERT (Data_in_enable = '0') - REPORT "It's illegal to Burst Terminate a Write" - SEVERITY WARNING; - - -- Terminate Read with Auto Precharge - ASSERT (Read_precharge (0) = '0' AND Read_precharge (1) = '0' AND - Read_precharge (2) = '0' AND Read_precharge (3) = '0') - REPORT "It's illegal to Burst Terminate a Read with Auto Precharge" - SEVERITY WARNING; - END IF; - - -- Read Command - IF Read_enable = '1' THEN - -- CAS Latency Pipeline - IF Cas_latency_15 = '1' THEN - Read_cmnd (3) := '1'; - Read_bank (3) := Ba; - Read_cols (3) := Addr (8 DOWNTO 0); - ELSIF Cas_latency_2 = '1' THEN - Read_cmnd (4) := '1'; - Read_bank (4) := Ba; - Read_cols (4) := Addr (8 DOWNTO 0); - ELSIF Cas_latency_25 = '1' THEN - Read_cmnd (5) := '1'; - Read_bank (5) := Ba; - Read_cols (5) := Addr (8 DOWNTO 0); - ELSIF Cas_latency_3 = '1' THEN - Read_cmnd (6) := '1'; - Read_bank (6) := Ba; - Read_cols (6) := Addr (8 DOWNTO 0); - ELSIF Cas_latency_4 = '1' THEN - Read_cmnd (8) := '1'; - Read_bank (8) := Ba; - Read_cols (8) := Addr (8 DOWNTO 0); - END IF; - - -- Write to Read: Terminate Write Immediately - IF Data_in_enable = '1' THEN - Data_in_enable := '0'; - END IF; - - -- Interrupting a Read with Auto Precharge (same bank only) - ASSERT (Read_precharge(CONV_INTEGER(Ba)) = '0') - REPORT "It's illegal to interrupt a Read with Auto Precharge" - SEVERITY WARNING; - - -- Activate to Read - ASSERT ((Ba = "00" AND Act_b0 = '1') OR - (Ba = "01" AND Act_b1 = '1') OR - (Ba = "10" AND Act_b2 = '1') OR - (Ba = "11" AND Act_b3 = '1')) - REPORT "Bank is not Activated for Read" - SEVERITY WARNING; - - -- Activate to Read without Auto Precharge - IF Addr (10) = '0' THEN - ASSERT ((Ba = "00" AND NOW - RCD_chk0 >= tRCD) OR - (Ba = "01" AND NOW - RCD_chk1 >= tRCD) OR - (Ba = "10" AND NOW - RCD_chk2 >= tRCD) OR - (Ba = "11" AND NOW - RCD_chk3 >= tRCD)) - REPORT "tRCD violation during Read" - SEVERITY WARNING; - END IF; - - -- Activate to Read with Auto Precharge - IF Addr (10) = '1' THEN - ASSERT ((Ba = "00" AND NOW - RAP_chk0 >= tRAP) OR - (Ba = "01" AND NOW - RAP_chk1 >= tRAP) OR - (Ba = "10" AND NOW - RAP_chk2 >= tRAP) OR - (Ba = "11" AND NOW - RAP_chk3 >= tRAP)) - REPORT "tRAP violation during Read" - SEVERITY WARNING; - END IF; - - -- Auto precharge - IF Addr (10) = '1' THEN - Read_precharge (Conv_INTEGER(Ba)) := '1'; - Count_precharge (Conv_INTEGER(Ba)) := 0; - END IF; - - -- DLL Check - IF (DLL_reset = '1') THEN - ASSERT (DLL_done = '1') - REPORT "DLL RESET not complete" - SEVERITY WARNING; - END IF; - END IF; - - -- Write Command - IF Write_enable = '1' THEN - -- Pipeline for Write - Write_cmnd (2) := '1'; - Write_bank (2) := Ba; - Write_cols (2) := Addr (8 DOWNTO 0); - - -- Interrupting a Write with Auto Precharge (same bank only) - ASSERT (Write_precharge(CONV_INTEGER(Ba)) = '0') - REPORT "It's illegal to interrupt a Write with Auto Precharge" - SEVERITY WARNING; - - -- Activate to Write - ASSERT ((Ba = "00" AND Act_b0 = '1') OR - (Ba = "01" AND Act_b1 = '1') OR - (Ba = "10" AND Act_b2 = '1') OR - (Ba = "11" AND Act_b3 = '1')) - REPORT "Bank is not Activated for Write" - SEVERITY WARNING; - - -- Activate to Write - ASSERT ((Ba = "00" AND NOW - RCD_chk0 >= tRCD) OR - (Ba = "01" AND NOW - RCD_chk1 >= tRCD) OR - (Ba = "10" AND NOW - RCD_chk2 >= tRCD) OR - (Ba = "11" AND NOW - RCD_chk3 >= tRCD)) - REPORT "tRCD violation during Write" - SEVERITY WARNING; - - -- Auto precharge - IF Addr (10) = '1' THEN - Write_precharge (Conv_INTEGER(Ba)) := '1'; - Count_precharge (Conv_INTEGER(Ba)) := 0; - END IF; - END IF; - END IF; - END PROCESS; - - -- - -- Dqs Receiver - -- - dqs_rcvrs : PROCESS - VARIABLE Dm_temp : STD_LOGIC_VECTOR (1 DOWNTO 0); - VARIABLE Dq_temp : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0); - BEGIN - WAIT ON Dqs; - -- Latch data at posedge Dqs - IF Dqs'EVENT AND Dqs (1) = '1' AND Dqs (0) = '1' THEN - Dq_temp := Dq; - Dm_temp := Dm; - END IF; - -- Latch data at negedge Dqs - IF Dqs'EVENT AND Dqs (1) = '0' AND Dqs (0) = '0' THEN - Dq_pair <= (Dq & Dq_temp); - Dm_pair <= (Dm & Dm_temp); - END IF; - END PROCESS; - - -- - -- Setup timing checks - -- - Setup_check : PROCESS - BEGIN - WAIT ON Sys_clk; - IF Sys_clk'EVENT AND Sys_clk = '1' THEN - ASSERT(Cke'LAST_EVENT >= tIS) - REPORT "CKE Setup time violation -- tIS" - SEVERITY WARNING; - ASSERT(Cs_n'LAST_EVENT >= tIS) - REPORT "CS# Setup time violation -- tIS" - SEVERITY WARNING; - ASSERT(Cas_n'LAST_EVENT >= tIS) - REPORT "CAS# Setup time violation -- tIS" - SEVERITY WARNING; - ASSERT(Ras_n'LAST_EVENT >= tIS) - REPORT "RAS# Setup time violation -- tIS" - SEVERITY WARNING; - ASSERT(We_n'LAST_EVENT >= tIS) - REPORT "WE# Setup time violation -- tIS" - SEVERITY WARNING; - ASSERT(Addr'LAST_EVENT >= tIS) - REPORT "ADDR Setup time violation -- tIS" - SEVERITY WARNING; - ASSERT(Ba'LAST_EVENT >= tIS) - REPORT "BA Setup time violation -- tIS" - SEVERITY WARNING; - END IF; - END PROCESS; - - -- - -- Hold timing checks - -- - Hold_check : PROCESS - BEGIN - WAIT ON Sys_clk'DELAYED (tIH); - IF Sys_clk'DELAYED (tIH) = '1' THEN - ASSERT(Cke'LAST_EVENT >= tIH) - REPORT "CKE Hold time violation -- tIH" - SEVERITY WARNING; - ASSERT(Cs_n'LAST_EVENT >= tIH) - REPORT "CS# Hold time violation -- tIH" - SEVERITY WARNING; - ASSERT(Cas_n'LAST_EVENT >= tIH) - REPORT "CAS# Hold time violation -- tIH" - SEVERITY WARNING; - ASSERT(Ras_n'LAST_EVENT >= tIH) - REPORT "RAS# Hold time violation -- tIH" - SEVERITY WARNING; - ASSERT(We_n'LAST_EVENT >= tIH) - REPORT "WE# Hold time violation -- tIH" - SEVERITY WARNING; - ASSERT(Addr'LAST_EVENT >= tIH) - REPORT "ADDR Hold time violation -- tIH" - SEVERITY WARNING; - ASSERT(Ba'LAST_EVENT >= tIH) - REPORT "BA Hold time violation -- tIH" - SEVERITY WARNING; - END IF; - END PROCESS; - -END behave; diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/reset_virtex4.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/reset_virtex4.vhd deleted file mode 100644 index 4f799c5..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/src/reset_virtex4.vhd +++ /dev/null @@ -1,111 +0,0 @@ -------------------------------------------------------------------------- --- Project: SDRAM controller --- This file: Reset generator (Virtex-4 specific) --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -Library UNISIM; -use UNISIM.vcomponents.all; - -entity reset is - port - ( - clk : in std_logic; - rst_in : in std_logic; - rst_out : out std_logic - ); -end; - -architecture tech of reset is - - signal rst : std_logic; - signal shift_pipe : std_logic_vector(3 downto 0); - attribute KEEP : string; - attribute KEEP of shift_pipe : signal is "TRUE"; - -begin - - rst <= shift_pipe(0); - -bufg_reset: bufg - port map - ( - o => rst_out, - i => rst - ); - -fdp0: fdp - generic map - ( - init => '1' - ) - port map - ( - d => rst_in, - c => clk, - pre => '0', - q => shift_pipe(3) - ); - -fdp1: fdp - generic map - ( - init => '1' - ) - port map - ( - - d => shift_pipe(3), - c => clk, - pre => '0', - q => shift_pipe(2) - ); - -fdp2: fdp - generic map - ( - init => '1' - ) - port map - ( - d => shift_pipe(2), - c => clk, - pre => '0', - q => shift_pipe(1) - ); - -fdp3: fdp - generic map - ( - init => '1' - ) - port map - ( - - d => shift_pipe(1), - c => clk, - pre => '0', - q => shift_pipe(0) - ); - -end tech; diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/sdram_cmd.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/sdram_cmd.vhd deleted file mode 100644 index a50b6e8..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/src/sdram_cmd.vhd +++ /dev/null @@ -1,269 +0,0 @@ -------------------------------------------------------------------------- --- Project: SDRAM controller --- This file: SDRAM command controller --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.sdram_config.all; -use work.sdram_types.all; - -entity sdram_cmd is - Generic (BL : natural := 2); - Port ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - enable : in STD_LOGIC; - u_tag_in : in user_tag_t; - u_tag_out : out user_tag_t; - phy_ctrl : out phy_ctrl_t; - cmd : in sdr_cmd_t; - cmd_we : in STD_LOGIC; - cmd_ack : out STD_LOGIC; - col_addr : in col_addr_t; - mode_word : in mode_word_t; - sdr_cmd_ctrl : out sdr_cmd_lines_t; - sdr_addr : out sdr_addr_t; - sdr_ba : out sdr_ba_t - ); -end sdram_cmd; - -architecture behaviour of sdram_cmd is - - signal st_sdr, st_sdr_next : sdr_state_t; - - signal cc_preset : natural range 0 to 10; - signal cc_load_en : std_logic; - signal cycle_finished : std_logic; - - signal burst_preset : natural range 0 to 3; - signal burst_load_en : std_logic; - signal burst_finished : std_logic; - -begin - - u_tag_out <= u_tag_in; - ------------------------------------------------------------------------------------------- - -fsm_sdr_state: - process (st_sdr, cmd, cmd_we, cycle_finished, burst_finished, mode_word, enable, col_addr) - begin - st_sdr_next <= st_sdr; - sdr_cmd_ctrl <= COMMAND(SD_NOP); - - cc_load_en <= '0'; - cc_preset <= TIMING(cmd); - burst_load_en <= '0'; - cmd_ack <= '0'; - burst_preset <= BL/2-1; - phy_ctrl.re <= '0'; - phy_ctrl.drive_en <= '0'; - phy_ctrl.we <= '0'; - phy_ctrl.utag_we <= '0'; - sdr_addr <= mode_word(sdr_addr_t'left downto sdr_addr_t'right); - sdr_ba <= mode_word(mode_word_t'left downto mode_word_t'left-1); - - case st_sdr is - when PWR_DOWN => - sdr_cmd_ctrl <= COMMAND(SD_DESELECT); - if enable = '1' then - st_sdr_next <= IDLE; - end if; - - when PRECHARGE => - if cycle_finished = '1' then - st_sdr_next <= IDLE; - end if; - - when MODE => - if cycle_finished = '1' then - st_sdr_next <= IDLE; - end if; - - when IDLE => - if cmd_we = '1' then - cmd_ack <= '1'; - cc_load_en <= '1'; - cc_preset <= TIMING(cmd); - sdr_cmd_ctrl <= COMMAND(cmd); - case cmd is - when SD_PRE => - st_sdr_next <= PRECHARGE; - sdr_addr(BIT_PRE_ALL) <= mode_word(BIT_PRE_ALL); - when SD_LMR => - st_sdr_next <= MODE; - when SD_ACT => - st_sdr_next <= ROW_ACT; - when SD_AR => - st_sdr_next <= AUTO_REF; - when others => null; - end case; - end if; - - when ROW_ACT => - if cycle_finished = '1' then - if cmd_we = '1' then - cmd_ack <= '1'; - burst_load_en <= '1'; - cc_load_en <= '1'; - cc_preset <= TIMING(cmd); - sdr_cmd_ctrl <= COMMAND(cmd); - case cmd is - when SD_PRE => - st_sdr_next <= PRECHARGE; - when SD_READ => - phy_ctrl.utag_we <= '1'; - st_sdr_next <= READ; - sdr_addr(col_addr_t'range) <= col_addr; - when SD_WRITE => - phy_ctrl.utag_we <= '1'; - phy_ctrl.drive_en <= '1'; - st_sdr_next <= WRITE; - sdr_addr(col_addr_t'range) <= col_addr; - when others => null; - end case; - end if; - end if; - - when WRITE => - phy_ctrl.drive_en <= '1'; - phy_ctrl.we <= '1'; - if burst_finished = '1' then - if cmd_we = '1' and cmd = SD_WRITE then - sdr_addr(col_addr_t'range) <= col_addr; - cmd_ack <= '1'; - burst_load_en <= '1'; - sdr_cmd_ctrl <= COMMAND(cmd); - phy_ctrl.utag_we <= '1'; - else - phy_ctrl.drive_en <= '0'; - cc_load_en <= '1'; - cc_preset <= TIMING(SD_WRITE)+1; - st_sdr_next <= ROW_ACT; - end if; - end if; - - when READ => - phy_ctrl.re <= '1'; - if burst_finished = '1' then - if cmd_we = '1' and cmd = SD_READ then - sdr_addr(col_addr_t'range) <= col_addr; - cmd_ack <= '1'; - burst_load_en <= '1'; - sdr_cmd_ctrl <= COMMAND(cmd); - phy_ctrl.utag_we <= '1'; - else - cc_load_en <= '1'; - cc_preset <= TIMING(SD_READ); - st_sdr_next <= ROW_ACT; - end if; - end if; - - when WRITE_A => -- not implemented yet - cmd_ack <= '1'; - st_sdr_next <= IDLE; - - when READ_A => -- not implemented yet - cmd_ack <= '1'; - st_sdr_next <= IDLE; - - when BURST_STOP => -- not implemented yet - cmd_ack <= '1'; - st_sdr_next <= IDLE; - - when SELF_REF => -- not implemented yet - cmd_ack <= '1'; - st_sdr_next <= IDLE; - - when PRE_PWR_DOWN => -- not implemented yet - cmd_ack <= '1'; - st_sdr_next <= IDLE; - - when ACT_PWR_DOWN => -- not implemented yet - cmd_ack <= '1'; - st_sdr_next <= IDLE; - - when AUTO_REF => - if cycle_finished = '1' then - st_sdr_next <= IDLE; - end if; - - when others => - st_sdr_next <= IDLE; - end case; - - end process; - -fsm_sdr_state_next: - process (rst, clk) - begin - if rst = '1' then - st_sdr <= PWR_DOWN; - elsif rising_edge(clk) then - st_sdr <= st_sdr_next; - end if; - end process; - ------------------------------------------------------------------------------------------- -cycle_counter: - process (rst, clk) - variable cycle_cnt : natural range 0 to 10; - begin - if rst = '1' then - cycle_cnt := 0; - cycle_finished <= '0'; - elsif rising_edge(clk) then - cycle_finished <= '0'; - if cc_load_en = '1' then - cycle_cnt := cc_preset; - elsif cycle_cnt /= 0 then - cycle_cnt := cycle_cnt - 1; - else - cycle_finished <= '1'; - end if; - end if; - end process; - ------------------------------------------------------------------------------------------- -burst_counter: - process (rst, clk) - variable burst_cnt : natural range 0 to 3; - begin - if rst = '1' then - burst_cnt := 0; - elsif rising_edge(clk) then - burst_finished <= '0'; - if burst_load_en = '1' then - burst_cnt := burst_preset; - elsif burst_cnt /= 0 then - burst_cnt := burst_cnt - 1; - end if; - if burst_cnt = 0 then - burst_finished <= '1'; - end if; - end if; - end process; - ------------------------------------------------------------------------------------------- -end behaviour; diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/sdram_config.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/sdram_config.vhd deleted file mode 100644 index b62e085..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/src/sdram_config.vhd +++ /dev/null @@ -1,74 +0,0 @@ -------------------------------------------------------------------------- --- Project: SDRAM controller --- This file: User SDRAM component adjustments --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -package sdram_config is - - constant DDR_DATA_WIDTH : positive := 16; -- External DDR-SDRAM Module data bus width - constant DDR_ADDR_WIDTH : positive := 13; -- number of address lines to DDR-SDRAM Device/Module - constant DDR_BANK_WIDTH : positive := 2; -- Number of BANK address lines of external DDR-SDRAM - constant DDR_ROW_ADDR_WIDTH : positive := 13; -- - constant DDR_COL_ADDR_WIDTH : positive := 9; -- - - constant LMR_REG_BASE : natural := 0; - constant LMR_REG_EXTENDED : natural := 1; - constant LMR_OP_NORMAL : natural := 0; - constant LMR_OP_RES_DLL : natural := 2; - constant LMR_BT_SEQ : natural := 0; - constant LMR_BT_ILVD : natural := 1; - constant LMR_BL2 : natural := 1; - constant LMR_BL4 : natural := 2; - constant LMR_BL8 : natural := 3; - constant LMR_CL2 : natural := 2; - constant LMR_CL3 : natural := 3; - constant LMR_CL2_5 : natural := 6; - - -- DDR SDRAM Hardware defined constants - constant BIT_AUTO_PRE : positive := 10; -- bit-position in column address for auto precharge (see Data Sheet) - constant BIT_PRE_ALL : positive := 10; -- bit-position in column address for precharge all (see Data Sheet) - constant ENABLE_PRE_ALL : std_logic := '1'; - constant ENABLE_AUTO_PRE : std_logic := '0'; - - -- DDR-SDR TIMING constants ------------------------------------------------------------------ - -- After REFRESH_CLOCKS a refresh cycle is necessary, 64ms / 8192 = max every 7.8125 us refesh - constant REFRESH_INTERVAL : real := 7.8125; -- us - - -- These values are for your SDRAM part (see datasheet) - constant TCAS : positive := 2; -- CAS latency [clocks] - constant TRP : positive := 2; -- precharge command period - constant TRAS : positive := 4; -- active to precharge delay - constant TRFC : positive := 8; -- auto refresh command period - constant TMRD : positive := 2; -- load mode register command cylce time - constant TRCD : positive := 2; -- active to read or write delay ! - constant TWR : positive := 2; -- write recovery time - - constant PWR_UP_WAIT : natural := 1; -- µs - - subtype user_tag_t is unsigned(3 downto 0); - - ---------------------------------------------------------------------------------------------- - -end sdram_config; diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl.vhd deleted file mode 100644 index dbb5b80..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl.vhd +++ /dev/null @@ -1,487 +0,0 @@ -------------------------------------------------------------------------- --- Project: SDRAM controller --- This file: SDRAM main controller and user I/F --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.sdram_config.all; -use work.sdram_types.all; -use work.utils_pkg.all; - -entity sdram_ctrl is - Generic - ( - f_sysclk : natural := 100E6; - BL : natural := 2 - ); - Port ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - u_busy : out STD_LOGIC; - u_tag_in : in user_tag_t; - u_tag_out : out user_tag_t; - u_addr : in user_addr_t; - u_cmd : in user_cmd_t; - u_cmd_we : in STD_LOGIC; - col_addr : out col_addr_t; - sdr_cmd_busy : in STD_LOGIC; - sdr_cmd : out sdr_cmd_t; - sdr_cmd_we : out STD_LOGIC; - sdr_mode : out mode_word_t; - sdr_cke : out STD_LOGIC - ); -end sdram_ctrl; - -architecture behaviour of sdram_ctrl is - - constant LMR_BURST_LEN : natural := NextExpBaseTwo(BL); - - type ctrl_state_t is (RESET, POWER_WAIT, INIT, INIT_WAIT, USER_READY, USER_WRITE_PRE, USER_WRITE_ACT, USER_WRITE, USER_READ_PRE, USER_READ_ACT, USER_READ, REFRESH); - signal st_ctrl, st_ctrl_next : ctrl_state_t; - - constant PWR_UP_CLOCK_INTERVAL : natural := PWR_UP_WAIT*(f_sysclk/1E6); - signal pwr_up_cnt : natural range 0 to PWR_UP_CLOCK_INTERVAL-1; - signal pwr_up_cnt_rst : std_logic; - signal pwr_up_finished : std_logic; - - signal cycle_cnt : natural range 0 to 255; - signal cc_preset : natural range 0 to 255; - signal cc_load_en : std_logic; - signal cycle_finished : std_logic; - - signal seq_cnt : natural range 0 to 31; - signal seq_rst_en : std_logic; - signal seq_cnt_en : std_logic; - - constant REFRESH_CLOCK_INTERVAL : natural := natural(REFRESH_INTERVAL*real(f_sysclk)/1.0E6); - signal refresh_cnt : natural range 0 to REFRESH_CLOCK_INTERVAL-1; - signal refresh_request : std_logic; - signal refresh_cnt_rst : std_logic; - - signal addr_reg_load_en : std_logic; - - signal u_tag_reg : user_tag_t; - signal bank_addr_reg : bank_addr_t; - signal row_addr_reg : row_addr_t; - signal col_addr_reg : col_addr_t; - - signal u_bank_addr : bank_addr_t; - signal u_row_addr : row_addr_t; - signal u_col_addr : col_addr_t; - - signal act_request : std_logic; - signal act_request_set : std_logic; - signal act_request_clr : std_logic; - - type init_seq_rom_t is array (0 to 14) of init_seq_t; - - constant init_seq_rom : init_seq_rom_t := - ( - ( - cmd => SD_NOP, - mode_word => (others => '0'), - wait_cycle => 0 - ), - ( - cmd => SD_PRE, - mode_word => "000010000000000", - wait_cycle => 0 - ), - ( - cmd => SD_NOP, - mode_word => (others => '0'), - wait_cycle => 0 - ), - ( - cmd => SD_LMR, - mode_word => to_unsigned(LMR_REG_EXTENDED, 2) & "0000000000010", - wait_cycle => 0 - ), - ( - cmd => SD_NOP, - mode_word => (others => '0'), - wait_cycle => 0 - ), - ( - cmd => SD_LMR, - mode_word => to_unsigned(LMR_REG_BASE, 2) & to_unsigned(LMR_OP_RES_DLL, 6) & to_unsigned(LMR_CL2, 3) & '0' & to_unsigned(LMR_BURST_LEN, 3), - wait_cycle => 200 - ), - ( - cmd => SD_NOP, - mode_word => (others => '0'), - wait_cycle => 0 - ), - ( - cmd => SD_PRE, - mode_word => "000010000000000", - wait_cycle => 0 - ), - ( - cmd => SD_NOP, - mode_word => (others => '0'), - wait_cycle => 0 - ), - ( - cmd => SD_AR, - mode_word => (others => '0'), - wait_cycle => 0 - ), - ( - cmd => SD_NOP, - mode_word => (others => '0'), - wait_cycle => 0 - ), - ( - cmd => SD_AR, - mode_word => (others => '0'), - wait_cycle => 0 - ), - ( - cmd => SD_NOP, - mode_word => (others => '0'), - wait_cycle => 0 - ), - ( - cmd => SD_LMR, - mode_word => to_unsigned(LMR_REG_BASE, 2) & to_unsigned(LMR_OP_NORMAL, 6) & to_unsigned(LMR_CL2, 3) & '0' & to_unsigned(LMR_BURST_LEN, 3), - wait_cycle => 200 - ), - ( - cmd => SD_NOP, - mode_word => (others => '0'), - wait_cycle => 0 - ) - - ); - -begin - - u_row_addr <= u_addr(user_addr_t'left downto user_addr_t'left-row_addr_t'length+1); - u_bank_addr <= u_addr(user_addr_t'left-row_addr_t'length downto user_addr_t'left-row_addr_t'length-bank_addr_t'length+1); - u_col_addr <= u_addr(user_addr_t'left-row_addr_t'length-bank_addr_t'length downto 0); - ------------------------------------------------------------------------------------------- -fsm_ctrl_state: - process (st_ctrl, u_tag_in, u_tag_reg, u_cmd, u_cmd_we, sdr_cmd_busy, pwr_up_finished, seq_cnt, cycle_finished, u_bank_addr, u_row_addr, bank_addr_reg, row_addr_reg, u_col_addr, col_addr_reg, refresh_request, act_request) - begin - - u_busy <= '1'; - pwr_up_cnt_rst <= '0'; - cc_preset <= init_seq_rom(seq_cnt).wait_cycle; - cc_load_en <= '0'; - sdr_cmd <= init_seq_rom(seq_cnt).cmd; - sdr_cmd_we <= '0'; - sdr_mode <= bank_addr_reg & row_addr_reg; - col_addr <= col_addr_reg; - sdr_cke <= '1'; - seq_cnt_en <= '0'; - seq_rst_en <= '0'; - addr_reg_load_en <= '0'; - refresh_cnt_rst <= '0'; - act_request_set <= '0'; - act_request_clr <= '0'; - u_tag_out <= u_tag_reg; - - st_ctrl_next <= st_ctrl; - case st_ctrl is - when RESET => - sdr_cke <= '0'; - pwr_up_cnt_rst <= '1'; - st_ctrl_next <= POWER_WAIT; - - when POWER_WAIT => - sdr_cke <= '0'; - if pwr_up_finished = '1' then - seq_rst_en <= '1'; - st_ctrl_next <= INIT; - end if; - - when INIT => - sdr_mode <= init_seq_rom(seq_cnt).mode_word; - sdr_cmd <= init_seq_rom(seq_cnt).cmd; - cc_preset <= init_seq_rom(seq_cnt).wait_cycle; - if seq_cnt = init_seq_rom_t'high then - act_request_set <= '1'; - refresh_cnt_rst <= '1'; - st_ctrl_next <= USER_READY; - elsif sdr_cmd_busy = '0' then - cc_load_en <= '1'; - sdr_cmd_we <= '1'; - st_ctrl_next <= INIT_WAIT; - end if; - - when INIT_WAIT => - if sdr_cmd_busy = '0' and cycle_finished = '1' then - seq_cnt_en <= '1'; - st_ctrl_next <= INIT; - end if; - - when USER_READY => - if sdr_cmd_busy = '0' then - if refresh_request = '1' then - sdr_mode(BIT_PRE_ALL) <= '1'; - sdr_cmd_we <= '1'; - sdr_cmd <= SD_PRE; - st_ctrl_next <= REFRESH; - else - u_busy <= '0'; - if u_cmd_we = '1' then - case u_cmd is - when UCMD_NOP => - sdr_cmd <= SD_NOP; - when UCMD_LMR => - sdr_cmd <= SD_NOP; - when UCMD_WRITE => - col_addr <= u_col_addr; - u_tag_out <= u_tag_in; - sdr_mode(BIT_AUTO_PRE) <= ENABLE_AUTO_PRE; - addr_reg_load_en <= '1'; - act_request_clr <= '1'; - sdr_cmd <= SD_WRITE; - if (u_row_addr /= row_addr_reg) or act_request = '1' then - st_ctrl_next <= USER_WRITE_PRE; - elsif (u_bank_addr /= bank_addr_reg) then - if ENABLE_PRE_ALL = '1' then - st_ctrl_next <= USER_WRITE_ACT; - else - st_ctrl_next <= USER_WRITE_PRE; - end if; - elsif sdr_cmd_busy = '0' then - sdr_cmd_we <= '1'; - else - st_ctrl_next <= USER_WRITE; - end if; - when UCMD_READ => - col_addr <= u_col_addr; - u_tag_out <= u_tag_in; - sdr_mode(BIT_AUTO_PRE) <= ENABLE_AUTO_PRE; - addr_reg_load_en <= '1'; - act_request_clr <= '1'; - sdr_cmd <= SD_READ; - if (u_row_addr /= row_addr_reg) or act_request = '1' then - st_ctrl_next <= USER_READ_PRE; - elsif (u_bank_addr /= bank_addr_reg) then - if ENABLE_PRE_ALL = '1' then - st_ctrl_next <= USER_READ_ACT; - else - st_ctrl_next <= USER_READ_PRE; - end if; - elsif sdr_cmd_busy = '0' then - sdr_cmd_we <= '1'; - else - st_ctrl_next <= USER_READ; - end if; - when others => null; - end case; - end if; - end if; - end if; - - when USER_WRITE_PRE => - sdr_cmd <= SD_PRE; - sdr_mode(BIT_PRE_ALL) <= ENABLE_PRE_ALL; - if sdr_cmd_busy = '0' then - sdr_cmd_we <= '1'; - st_ctrl_next <= USER_WRITE_ACT; - end if; - - when USER_WRITE_ACT => - sdr_cmd <= SD_ACT; - if sdr_cmd_busy = '0' then - sdr_cmd_we <= '1'; - st_ctrl_next <= USER_WRITE; - end if; - - when USER_WRITE => - sdr_cmd <= SD_WRITE; - sdr_mode(BIT_AUTO_PRE) <= ENABLE_AUTO_PRE; - if sdr_cmd_busy = '0' then - sdr_cmd_we <= '1'; - st_ctrl_next <= USER_READY; - end if; - - when USER_READ_PRE => - sdr_cmd <= SD_PRE; - sdr_mode(BIT_PRE_ALL) <= ENABLE_PRE_ALL; - if sdr_cmd_busy = '0' then - sdr_cmd_we <= '1'; - st_ctrl_next <= USER_READ_ACT; - end if; - - when USER_READ_ACT => - sdr_cmd <= SD_ACT; - if sdr_cmd_busy = '0' then - sdr_cmd_we <= '1'; - st_ctrl_next <= USER_READ; - end if; - - when USER_READ => - sdr_cmd <= SD_READ; - sdr_mode(BIT_AUTO_PRE) <= ENABLE_AUTO_PRE; - if sdr_cmd_busy = '0' then - sdr_cmd_we <= '1'; - st_ctrl_next <= USER_READY; - end if; - - when REFRESH => - sdr_cmd <= SD_AR; - if sdr_cmd_busy = '0' then - sdr_cmd_we <= '1'; - st_ctrl_next <= USER_READY; - refresh_cnt_rst <= '1'; - act_request_set <= '1'; - end if; - - when others => - st_ctrl_next <= RESET; - end case; - - end process; - -fsm_ctrl_state_next: - process (rst, clk) - begin - if rst = '1' then - st_ctrl <= RESET; - elsif rising_edge(clk) then - st_ctrl <= st_ctrl_next; - end if; - end process; - ------------------------------------------------------------------------------------------- -act_request_register: - process (rst, clk) - begin - if rst = '1' then - act_request <= '1'; - elsif rising_edge(clk) then - if act_request_set = '1' then - act_request <= '1'; - elsif act_request_clr = '1' then - act_request <= '0'; - end if; - end if; - end process; - ------------------------------------------------------------------------------------------- -user_addr_register: - process (rst, clk) - begin - if rst = '1' then - bank_addr_reg <= (others => '0'); - row_addr_reg <= (others => '0'); - col_addr_reg <= (others => '0'); - u_tag_reg <= (others => '0'); - elsif rising_edge(clk) then - if addr_reg_load_en = '1' then - bank_addr_reg <= u_bank_addr; - row_addr_reg <= u_row_addr; - col_addr_reg <= u_col_addr; - u_tag_reg <= u_tag_in; - end if; - end if; - end process; - ------------------------------------------------------------------------------------------- -power_up_counter: - process (rst, clk) - begin - if rst = '1' then - pwr_up_cnt <= 0; - pwr_up_finished <= '0'; - elsif rising_edge(clk) then - pwr_up_finished <= '0'; - if pwr_up_cnt_rst = '1' then - pwr_up_cnt <= PWR_UP_CLOCK_INTERVAL-1; - else - if pwr_up_cnt /= 0 then - pwr_up_cnt <= pwr_up_cnt - 1; - else - pwr_up_finished <= '1'; - end if; - end if; - end if; - end process; - - ------------------------------------------------------------------------------------------- -refresh_counter: - process (rst, clk) - begin - if rst = '1' then - refresh_cnt <= 0; - refresh_request <= '0'; - elsif rising_edge(clk) then - refresh_request <= '0'; - if refresh_cnt_rst = '1' then - refresh_cnt <= REFRESH_CLOCK_INTERVAL-1; - else - if refresh_cnt /= 0 then - refresh_cnt <= refresh_cnt - 1; - else - refresh_request <= '1'; - end if; - end if; - end if; - end process; - ------------------------------------------------------------------------------------------- -cycle_counter: - process (rst, clk) - begin - if rst = '1' then - cycle_cnt <= 0; - cycle_finished <= '0'; - elsif rising_edge(clk) then - cycle_finished <= '0'; - if cc_load_en = '1' then - cycle_cnt <= cc_preset; - elsif cycle_cnt /= 0 then - cycle_cnt <= cycle_cnt - 1; - else - cycle_finished <= '1'; - end if; - end if; - end process; - ------------------------------------------------------------------------------------------- -seq_counter: - process (rst, clk) - begin - if rst = '1' then - seq_cnt <= 0; - elsif rising_edge(clk) then - if seq_rst_en = '1' then - seq_cnt <= 0; - elsif seq_cnt_en = '1' then - if seq_cnt /= init_seq_rom_t'high then - seq_cnt <= seq_cnt + 1; - end if; - end if; - end if; - end process; - ------------------------------------------------------------------------------------------- -end behaviour; diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl_frontend.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl_frontend.vhd deleted file mode 100644 index 268636e..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl_frontend.vhd +++ /dev/null @@ -1,293 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: cpu_embedded using cpu_core and rom --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.fifo_ctrl_pkg.all; -use work.sdram_config.all; -use work.sdram_types.all; - -entity sdram_ctrl_frontend is - Generic - ( - BL : natural := 2; - f_sysclk : natural := 100E6; - read_phaseshift : integer := 0; - fifo_depth : integer := 4 - ); - Port - ( - sys_rst_in : in STD_LOGIC; - sys_clk_in : in STD_LOGIC; - sys_rst_out : out STD_LOGIC; - sys_clk_out : out STD_LOGIC; - sys_clk_fb : in STD_LOGIC; - - -- User interface - busy : out STD_LOGIC; - en : in STD_LOGIC; - r_wn : in STD_LOGIC; - be : in unsigned(SDR_DM_WIDTH-1 downto 0); - addr : in user_addr_t; - din : in unsigned(SDR_DATA_WIDTH-1 downto 0); - dout : out unsigned(SDR_DATA_WIDTH-1 downto 0); - dout_re : in STD_LOGIC; - dout_vld : out STD_LOGIC; - - -- SDRAM signals - sd_clk_p : out STD_LOGIC; - sd_clk_n : out STD_LOGIC; - sd_cke : out STD_LOGIC; - sd_cs_n : out STD_LOGIC; - sd_cas_n : out STD_LOGIC; - sd_ras_n : out STD_LOGIC; - sd_we_n : out STD_LOGIC; - sd_addr : out sdr_addr_t; - sd_ba : out sdr_ba_t; - sd_dm : out unsigned(DDR_DM_WIDTH-1 downto 0); - sd_dqs : inout unsigned(DDR_DQS_WIDTH-1 downto 0); - sd_data : inout unsigned(DDR_DATA_WIDTH-1 downto 0) - - ); -end sdram_ctrl_frontend; - -architecture struct of sdram_ctrl_frontend is - - -- Number of user data words for simulation - signal rst_out : std_logic; - signal clk_out : std_logic; - - signal u_addr : user_addr_t; - signal u_tag_in : user_tag_t; - signal u_tag_rd : user_tag_t; - signal u_tag_wr : user_tag_t; - signal u_cmd : user_cmd_t; - signal u_cmd_we : std_logic; - signal u_busy : std_logic; - signal u_data_w : unsigned(SDR_DATA_WIDTH-1 downto 0); - signal u_dm_wr_in : unsigned(SDR_DM_WIDTH-1 downto 0); - signal u_dm_rd_in : unsigned(SDR_DM_WIDTH-1 downto 0); - signal u_dm_rd_out : unsigned(SDR_DM_WIDTH-1 downto 0); - signal u_data_r : unsigned(SDR_DATA_WIDTH-1 downto 0); - signal u_data_vld : std_logic; - signal u_req_wr : std_logic; - signal rdy : std_logic; - - constant CAT_FIFO_WIDTH : integer := user_cmd_t'length + user_tag_t'length + DDR_ROW_ADDR_WIDTH + DDR_BANK_WIDTH + DDR_COL_ADDR_WIDTH + SDR_DM_WIDTH; - signal cat_fifo_din : unsigned(CAT_FIFO_WIDTH-1 downto 0); - signal cat_fifo_dout : unsigned(CAT_FIFO_WIDTH-1 downto 0); - signal cat_fifo_re : std_logic; - signal cat_fifo_we : std_logic; - signal cat_fifo_full : std_logic; - signal cat_fifo_empty : std_logic; --- signal cat_fifo_almost_full : std_logic; --- signal cat_fifo_almost_empty : std_logic; - - signal write_fifo_din : unsigned(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto 0); - signal write_fifo_dout : unsigned(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto 0); - signal write_fifo_re : std_logic; - signal write_fifo_we : std_logic; - signal write_fifo_full : std_logic; - signal write_fifo_empty : std_logic; --- signal write_fifo_almost_full : std_logic; --- signal write_fifo_almost_empty : std_logic; - - signal read_fifo_din : unsigned(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto 0); - signal read_fifo_dout : unsigned(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto 0); - signal read_fifo_re : std_logic; - signal read_fifo_we : std_logic; - signal read_fifo_full : std_logic; - signal read_fifo_empty : std_logic; --- signal read_fifo_almost_full : std_logic; --- signal read_fifo_almost_empty : std_logic; - - alias cmd_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-1 downto CAT_FIFO_WIDTH-user_cmd_t'length); - alias tag_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-user_cmd_t'length-1 downto CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length); - alias addr_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length-1 downto SDR_DM_WIDTH); - alias dm_rd_fifo_in is cat_fifo_din(SDR_DM_WIDTH-1 downto 0); - alias cmd_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-1 downto CAT_FIFO_WIDTH-user_cmd_t'length); - alias tag_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-user_cmd_t'length-1 downto CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length); - alias addr_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length-1 downto SDR_DM_WIDTH); - alias dm_rd_fifo_out is cat_fifo_dout(SDR_DM_WIDTH-1 downto 0); - - alias write_fifo_dm_in is write_fifo_din(write_fifo_din'length-1 downto write_fifo_din'length-SDR_DM_WIDTH); - alias write_fifo_data_in is write_fifo_din(write_fifo_din'length-SDR_DM_WIDTH-1 downto 0); - alias write_fifo_dm_out is write_fifo_dout(write_fifo_dout'length-1 downto write_fifo_dout'length-SDR_DM_WIDTH); - alias write_fifo_data_out is write_fifo_dout(write_fifo_dout'length-SDR_DM_WIDTH-1 downto 0); - - alias read_fifo_dm_in is read_fifo_din(read_fifo_din'length-1 downto read_fifo_din'length-SDR_DM_WIDTH); - alias read_fifo_data_in is read_fifo_din(read_fifo_din'length-SDR_DM_WIDTH-1 downto 0); - alias read_fifo_dm_out is read_fifo_dout(read_fifo_dout'length-1 downto read_fifo_dout'length-SDR_DM_WIDTH); - alias read_fifo_data_out is read_fifo_dout(read_fifo_dout'length-SDR_DM_WIDTH-1 downto 0); - -begin - - -- Instantiate synchronous FIFO - inst_cat_fifo: entity work.fifo_sync - GENERIC MAP - ( - addr_width => fifo_depth, - data_width => CAT_FIFO_WIDTH - ) - PORT MAP - ( - rst => rst_out, - clk => clk_out, - we => cat_fifo_we, - re => cat_fifo_re, - fifo_full => cat_fifo_full, - fifo_empty => cat_fifo_empty, - fifo_afull => open, - fifo_aempty => open, - data_w => cat_fifo_din, - data_r => cat_fifo_dout - ); - - -- Instantiate synchronous FIFO - inst_write_fifo: entity work.fifo_sync - GENERIC MAP - ( - addr_width => fifo_depth, - data_width => 2*DDR_DATA_WIDTH + SDR_DM_WIDTH - ) - PORT MAP - ( - rst => rst_out, - clk => clk_out, - we => write_fifo_we, - re => write_fifo_re, - fifo_full => write_fifo_full, - fifo_empty => write_fifo_empty, - fifo_afull => open, - fifo_aempty => open, - data_w => write_fifo_din, - data_r => write_fifo_dout - ); - - -- Instantiate synchronous FIFO - inst_read_fifo: entity work.fifo_sync - GENERIC MAP - ( - addr_width => fifo_depth, - data_width => 2*DDR_DATA_WIDTH + SDR_DM_WIDTH - ) - PORT MAP - ( - rst => rst_out, - clk => clk_out, - we => read_fifo_we, - re => read_fifo_re, - fifo_full => read_fifo_full, - fifo_empty => read_fifo_empty, - fifo_afull => open, - fifo_aempty => open, - data_w => read_fifo_din, - data_r => read_fifo_dout - ); - - -- DDR SDRAM Controller Core - inst_sdram_ctrl : entity work.sdram_ctrl_top - Generic map - ( - BL => BL, - read_phaseshift => read_phaseshift, - f_sysclk => f_sysclk - ) - Port map - ( - - sys_rst_in => sys_rst_in, - sys_clk_in => sys_clk_in, - - sys_rst_out => rst_out, - sys_clk_out => clk_out, - sys_clk_fb => sys_clk_fb, - - -- User interface - u_data_vld => u_data_vld, - u_data_req_w => u_req_wr, - u_data_req_r => open, - u_tag_in => u_tag_in, - u_tag_rd => u_tag_rd, - u_tag_wr => u_tag_wr, - u_busy => u_busy, - u_addr => u_addr, - u_cmd => u_cmd, - u_cmd_we => u_cmd_we, - u_data_wr => u_data_w, - u_data_rd => u_data_r, - u_dm_wr_in => u_dm_wr_in, - u_dm_rd_in => u_dm_rd_in, - u_dm_rd_out => u_dm_rd_out, - - -- SDRAM signals - sd_clk_p => sd_clk_p, - sd_clk_n => sd_clk_n, - sd_cke => sd_cke, - sd_cs_n => sd_cs_n, - sd_cas_n => sd_cas_n, - sd_ras_n => sd_ras_n, - sd_we_n => sd_we_n, - sd_addr => sd_addr, - sd_ba => sd_ba, - sd_dm => sd_dm, - sd_dqs => sd_dqs, - sd_data => sd_data - - ); - ------------------------------------------------------------------------------------------- - sys_rst_out <= rst_out; - sys_clk_out <= clk_out; - busy <= not rdy; - rdy <= not (cat_fifo_full or write_fifo_full or read_fifo_full); - write_fifo_we <= en and not r_wn and rdy; - write_fifo_data_in <= din; - write_fifo_dm_in <= not be; - cat_fifo_we <= en and rdy; - cmd_fifo_in <= UCMD_WRITE when r_wn = '0' else UCMD_READ; - addr_fifo_in <= addr; - dm_rd_fifo_in <= not be; - tag_fifo_in <= (others=>'0'); - dout <= read_fifo_data_out; - dout_vld <= not read_fifo_empty; - - u_cmd_we <= (not cat_fifo_empty) and (not u_busy); - u_cmd <= cmd_fifo_out; - u_addr <= addr_fifo_out; - u_dm_rd_in <= dm_rd_fifo_out; - u_dm_wr_in <= write_fifo_dm_out; - u_tag_in <= tag_fifo_out; - - write_fifo_re <= u_req_wr and (not write_fifo_empty); - cat_fifo_re <= u_cmd_we; - u_data_w <= write_fifo_data_out; - read_fifo_re <= (not read_fifo_empty) and dout_re; - read_fifo_we <= u_data_vld; - read_fifo_data_in <= u_data_r; - read_fifo_dm_in <= u_dm_rd_out; - - -end architecture struct; diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl_top.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl_top.vhd deleted file mode 100644 index 19768a4..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl_top.vhd +++ /dev/null @@ -1,289 +0,0 @@ -------------------------------------------------------------------------- --- Project: SDRAM controller --- This file: Top-level put all together --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.sdram_config.all; -use work.sdram_types.all; - -entity sdram_ctrl_top is - Generic - ( - BL : natural := 2; - f_sysclk : natural := 100E6; - read_phaseshift : integer := 0 - ); - Port - ( - sys_rst_in : in STD_LOGIC; - sys_clk_in : in STD_LOGIC; - sys_rst_out : out STD_LOGIC; - sys_clk_out : out STD_LOGIC; - sys_clk_fb : in STD_LOGIC; - - -- User interface - u_data_vld : out STD_LOGIC; - u_data_req_w : out STD_LOGIC; - u_data_req_r : out STD_LOGIC; - u_busy : out STD_LOGIC; - u_tag_in : in user_tag_t; - u_tag_rd : out user_tag_t; - u_tag_wr : out user_tag_t; - u_addr : in user_addr_t; - u_cmd : in user_cmd_t; - u_cmd_we : in STD_LOGIC; - u_data_wr : in unsigned(SDR_DATA_WIDTH-1 downto 0); - u_dm_wr_in : in unsigned(SDR_DM_WIDTH-1 downto 0); - u_dm_rd_in : in unsigned(SDR_DM_WIDTH-1 downto 0); - u_dm_rd_out : out unsigned(SDR_DM_WIDTH-1 downto 0); - u_data_rd : out unsigned(SDR_DATA_WIDTH-1 downto 0); - - -- SDRAM signals - sd_clk_p : out STD_LOGIC; - sd_clk_n : out STD_LOGIC; - sd_cke : out STD_LOGIC; - sd_cs_n : out STD_LOGIC; - sd_cas_n : out STD_LOGIC; - sd_ras_n : out STD_LOGIC; - sd_we_n : out STD_LOGIC; - sd_addr : out sdr_addr_t; - sd_ba : out sdr_ba_t; - sd_dm : out unsigned(DDR_DM_WIDTH-1 downto 0); - sd_dqs : inout unsigned(DDR_DQS_WIDTH-1 downto 0); - sd_data : inout unsigned(DDR_DATA_WIDTH-1 downto 0) - - ); -end sdram_ctrl_top; - -architecture rtl of sdram_ctrl_top is - - signal clk0 : std_logic; - signal clk270 : std_logic; - signal read_clk270 : std_logic; - - signal phy_ctrl : phy_ctrl_t; - - signal u_tag : user_tag_t; - signal sd_cmd_in : sdr_cmd_t; - signal sd_cmd : sdr_cmd_t; - signal sd_cmd_we : std_logic; - signal cmd_ctrl : sdr_cmd_lines_t; - signal cke : std_logic; - signal ba : unsigned(DDR_BANK_WIDTH-1 downto 0); - signal addr : unsigned(DDR_ADDR_WIDTH-1 downto 0); - - -- Clock generator - - signal cg_rst : std_logic; - signal cg_read_clk0 : std_logic; - signal cg_read_clk270 : std_logic; - signal cg_sys_clk0 : std_logic; - signal cg_sys_clk270 : std_logic; - signal cg_locked : std_logic; - signal cg_error : std_logic; - signal ctrl_rst : std_logic; - signal part_ctrl : part_ctrl_t; - - -- SD command FIFO - - constant CMD_FIFO_ADDR_WIDTH : positive := 2; - constant CMD_FIFO_DATA_WIDTH : positive := user_tag_t'length + 4 + mode_word_t'length + col_addr_t'length; - signal cmd_fifo_din : unsigned(CMD_FIFO_DATA_WIDTH-1 downto 0); - signal cmd_fifo_dout : unsigned(CMD_FIFO_DATA_WIDTH-1 downto 0); - signal cmd_fifo_re : std_logic; - signal cmd_fifo_we : std_logic; - signal cmd_fifo_full : std_logic; - signal cmd_fifo_empty : std_logic; - - alias tag_fifo_in is cmd_fifo_din(CMD_FIFO_DATA_WIDTH-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length); - alias cmd_fifo_in is cmd_fifo_din(CMD_FIFO_DATA_WIDTH-user_tag_t'length-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length-4); - alias mode_fifo_in is cmd_fifo_din(CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-mode_word_t'length); - alias col_fifo_in is cmd_fifo_din(CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-mode_word_t'length-1 downto 0); - - alias tag_fifo_out is cmd_fifo_dout(CMD_FIFO_DATA_WIDTH-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length); - alias cmd_fifo_out is cmd_fifo_dout(CMD_FIFO_DATA_WIDTH-user_tag_t'length-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length-4); - alias mode_fifo_out is cmd_fifo_dout(CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-mode_word_t'length); - alias col_fifo_out is cmd_fifo_dout(CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-mode_word_t'length-1 downto 0); - -begin - - --------------------------------- - clk0 <= cg_sys_clk0; - clk270 <= cg_sys_clk270; - read_clk270 <= cg_read_clk270; - cg_rst <= not cg_locked; - - --------------------------------- - sys_clk_out <= cg_sys_clk0; - sys_rst_out <= ctrl_rst; - - --------------------------------- - part_ctrl.cmd <= cmd_ctrl; - part_ctrl.ba <= ba; - part_ctrl.addr <= addr; - part_ctrl.cke <= cke; - - --------------------------------- - sd_cmd_we <= not cmd_fifo_empty; - cmd_fifo_in <= to_unsigned(sd_cmd_in, 4); - sd_cmd <= sdr_cmd_t(to_integer(cmd_fifo_out)); - - --------------------------------- - inst_reset: entity work.reset - port map - ( - clk => clk0, - rst_in => cg_rst, - rst_out => ctrl_rst - ); - - inst_clockgen : entity work.clockgen - generic map - ( - read_phaseshift => read_phaseshift, - frequency_hz => f_sysclk - ) - port map - ( - rst => sys_rst_in, - clk_in => sys_clk_in, - clk_fb_in => sys_clk_fb, - read_clk0_out => cg_read_clk0, - read_clk270_out => cg_read_clk270, - sys_clk0_out => cg_sys_clk0, - sys_clk270_out => cg_sys_clk270, - locked_out => cg_locked, - error_out => cg_error - ); - - -- Main controller - inst_sdram_ctrl : entity work.sdram_ctrl - Generic map - ( - f_sysclk => 100E6, - BL => BL - ) - Port map - ( - rst => ctrl_rst, - clk => clk0, - u_busy => u_busy, - u_tag_in => u_tag_in, - u_tag_out => tag_fifo_in, - u_cmd => u_cmd, - u_cmd_we => u_cmd_we, - u_addr => u_addr, - sdr_cmd_busy => cmd_fifo_full, - sdr_cmd => sd_cmd_in, - sdr_cmd_we => cmd_fifo_we, - col_addr => col_fifo_in, - sdr_mode => mode_fifo_in, - sdr_cke => cke - ); - - -- Instantiate synchronous FIFO - inst_sd_cmd_fifo: entity work.fifo_sync - GENERIC MAP - ( - addr_width => CMD_FIFO_ADDR_WIDTH, - data_width => CMD_FIFO_DATA_WIDTH, - almost_full_thresh => 2**(CMD_FIFO_ADDR_WIDTH-1), - almost_empty_thresh => 2**(CMD_FIFO_ADDR_WIDTH-1) - ) - PORT MAP - ( - rst => ctrl_rst, - clk => clk0, - we => cmd_fifo_we, - re => cmd_fifo_re, - fifo_full => cmd_fifo_full, - fifo_empty => cmd_fifo_empty, - fifo_afull => open, - fifo_aempty => open, - data_w => cmd_fifo_din, - data_r => cmd_fifo_dout - ); - - -- DDR SDRAM command fsm - inst_sdram_cmd : entity work.sdram_cmd - Generic map - ( - BL => BL - ) - Port map - ( - rst => ctrl_rst, - clk => clk0, - u_tag_in => tag_fifo_out, - u_tag_out => u_tag, - phy_ctrl => phy_ctrl, - enable => cke, - cmd => sd_cmd, - cmd_we => sd_cmd_we, - cmd_ack => cmd_fifo_re, - sdr_cmd_ctrl => cmd_ctrl, - col_addr => col_fifo_out, - mode_word => mode_fifo_out, - sdr_ba => ba, - sdr_addr => addr - ); - - -- DDR phy - inst_ddr_phy : entity work.ddr_phy - Port map - ( - sys_rst => ctrl_rst, - sys_clk0 => clk0, - sys_clk270 => clk270, - u_tag_in => u_tag, - u_tag_rd => u_tag_rd, - u_tag_wr => u_tag_wr, - read_clk => read_clk270, - phy_ctrl => phy_ctrl, - part_ctrl => part_ctrl, - sdr_data_req_w => u_data_req_w, - sdr_data_req_r => u_data_req_r, - sdr_data_w => u_data_wr, - sdr_dm_wr_in => u_dm_wr_in, - sdr_dm_rd_in => u_dm_rd_in, - sdr_dm_rd_out => u_dm_rd_out, - sdr_data_r => u_data_rd, - sdr_data_vld => u_data_vld, - part_clk_p => sd_clk_p, - part_clk_n => sd_clk_n, - part_addr => sd_addr, - part_ba => sd_ba, - part_dm => sd_dm, - part_dqs => sd_dqs, - part_data => sd_data, - part_cs_n => sd_cs_n, - part_we_n => sd_we_n, - part_cas_n => sd_cas_n, - part_ras_n => sd_ras_n, - part_cke => sd_cke - ); - -end architecture rtl; - diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/sdram_types.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/sdram_types.vhd deleted file mode 100644 index d235d75..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/src/sdram_types.vhd +++ /dev/null @@ -1,133 +0,0 @@ -------------------------------------------------------------------------- --- Project: SDRAM controller --- This file: Type definitions --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -use work.sdram_config.all; - -package sdram_types is - - ----------------------------------------------------------------------------------------- - -- Table of Timing Parameters as a function of operation - - -- Derived constants from sdram_config - - constant DDR_DQS_WIDTH : positive := DDR_DATA_WIDTH / 8; -- Number of data strobe lines - constant DDR_DM_WIDTH : positive := DDR_DATA_WIDTH / 8; -- Number of Data Mask Lines - constant SDR_DATA_WIDTH : positive := 2*DDR_DATA_WIDTH; -- - constant SDR_DM_WIDTH : positive := 2*DDR_DM_WIDTH; -- - - subtype user_cmd_t is unsigned(1 downto 0); - constant UCMD_NOP : user_cmd_t := "00"; - constant UCMD_READ : user_cmd_t := "01"; - constant UCMD_WRITE : user_cmd_t := "10"; - constant UCMD_LMR : user_cmd_t := "11"; - - subtype sdr_cmd_t is natural range 0 to 9; - constant SD_DESELECT : sdr_cmd_t := 0; - constant SD_NOP : sdr_cmd_t := 1; - constant SD_LMR : sdr_cmd_t := 2; - constant SD_ACT : sdr_cmd_t := 3; - constant SD_READ : sdr_cmd_t := 4; - constant SD_WRITE : sdr_cmd_t := 5; - constant SD_PRE : sdr_cmd_t := 6; - constant SD_BST : sdr_cmd_t := 7; - constant SD_AR : sdr_cmd_t := 8; - constant SD_SR : sdr_cmd_t := 9; - - type sdr_state_t is (PWR_DOWN, PRECHARGE, MODE, IDLE, ROW_ACT, WRITE, WRITE_A, READ, READ_A, BURST_STOP, SELF_REF, AUTO_REF, PRE_PWR_DOWN, ACT_PWR_DOWN); - subtype user_addr_t is unsigned(DDR_BANK_WIDTH+DDR_ROW_ADDR_WIDTH+DDR_COL_ADDR_WIDTH-1 downto 0); - subtype sdr_addr_t is unsigned(DDR_ADDR_WIDTH-1 downto 0); - subtype sdr_ba_t is unsigned(DDR_BANK_WIDTH-1 downto 0); - subtype mode_word_t is unsigned(DDR_ADDR_WIDTH+DDR_BANK_WIDTH-1 downto 0); - - subtype bank_addr_t is unsigned(DDR_BANK_WIDTH-1 downto 0); - subtype row_addr_t is unsigned(DDR_ADDR_WIDTH-1 downto 0); - subtype col_addr_t is unsigned(8 downto 0); - - subtype cycle_cnt_t is natural range 0 to 10; - - type phy_ctrl_t is - record - drive_en : std_logic; - re : std_logic; - we : std_logic; - utag_we : std_logic; - end record phy_ctrl_t; - - type sdr_cmd_lines_t is - record - cs_n : std_logic; - ras_n : std_logic; - cas_n : std_logic; - we_n : std_logic; - end record sdr_cmd_lines_t; - - type part_ctrl_t is - record - cmd : sdr_cmd_lines_t; - ba : unsigned(DDR_BANK_WIDTH-1 downto 0); - addr : unsigned(DDR_ADDR_WIDTH-1 downto 0); - cke : std_logic; - end record part_ctrl_t; - - type part_cmd_array_t is array (sdr_cmd_t) of sdr_cmd_lines_t; - constant COMMAND : part_cmd_array_t := - -- command cs_n ras_qn cas_qn we_qn - ( SD_DESELECT => ( '1', '1', '1', '1'), - SD_NOP => ( '0', '1', '1', '1'), - SD_LMR => ( '0', '0', '0', '0'), - SD_ACT => ( '0', '0', '1', '1'), - SD_READ => ( '0', '1', '0', '1'), - SD_WRITE => ( '0', '1', '0', '0'), - SD_PRE => ( '0', '0', '1', '0'), - SD_BST => ( '0', '1', '1', '0'), - SD_AR => ( '0', '0', '0', '1'), - SD_SR => ( '0', '0', '0', '1') - ); - - type part_timing_array_t is array (sdr_cmd_t) of cycle_cnt_t; - constant TIMING : part_timing_array_t := - -- command cycle_cnt - ( SD_DESELECT => ( 0 ), - SD_NOP => ( 0 ), - SD_LMR => ( TMRD-1 ), - SD_ACT => ( TRCD-1 ), - SD_READ => ( TCAS-1 ), - SD_WRITE => ( TWR-1 ), - SD_PRE => ( TRP-1 ), - SD_BST => ( 0 ), - SD_AR => ( TRFC-1 ), - SD_SR => ( TRFC-1 ) - ); - - type init_seq_t is - record - cmd : sdr_cmd_t; - mode_word : mode_word_t; - wait_cycle : natural; - end record init_seq_t; - -end sdram_types; diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl.vhd deleted file mode 100644 index 034215c..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl.vhd +++ /dev/null @@ -1,336 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: cpu_embedded using cpu_core and rom --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.sdram_config.all; -use work.sdram_types.all; -use work.utils_pkg.all; - -entity tb_sdr_ctrl is -end; - -architecture struct of tb_sdr_ctrl is - - -- Number of user data words for simulation - constant CLK_PERIOD : time := 10 ns; - constant BURST_LEN : natural := 8; - - signal rst : std_logic := '1'; - signal clk : std_logic := '0'; - signal rst_out : std_logic; - signal clk_out : std_logic; - signal clk_fb : std_logic; - signal part_clk_p : std_logic; - signal part_clk_n : std_logic; - signal part_cke : std_logic; - signal part_cs_n : std_logic; - signal part_we_n : std_logic; - signal part_ras_n : std_logic; - signal part_cas_n : std_logic; - signal part_ba : unsigned(DDR_BANK_WIDTH-1 downto 0) := (others => '0'); - signal part_dm : unsigned(DDR_DM_WIDTH-1 downto 0) := (others => '0'); - signal part_dqs : unsigned(DDR_DQS_WIDTH-1 downto 0) := (others => '0'); - signal part_addr : unsigned(DDR_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal part_data : unsigned(DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - - signal u_addr : user_addr_t := (others => '0'); - signal u_tag_in : user_tag_t := "0000"; - signal u_tag_rd : user_tag_t; - signal u_tag_wr : user_tag_t; - signal u_cmd : user_cmd_t := UCMD_NOP; - signal u_cmd_we : std_logic := '0'; - signal u_busy : std_logic; - signal u_data_w : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - signal u_dm : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000"; - signal u_dm_rd_in : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000"; - signal u_dm_rd_out : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000"; - signal u_data_r : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - signal u_data_vld : std_logic; - signal u_req_wr : std_logic; - signal u_req_rd : std_logic; - signal u_read_en : std_logic := '0'; - signal u_write_en : std_logic := '0'; - signal u_addr_cnt_en : std_logic := '0'; - signal u_addr_load : std_logic := '0'; - signal u_addr_preset : user_addr_t := (others => '0'); - signal u_addr_end : user_addr_t := (others => '0'); - signal ref_data : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - - type test_phase_t is (IDLE, PART_INIT, WRITE_SINGLE, WRITE_MULTI, READ_SINGLE, READ_MULTI, FINISHED); - signal test_phase : test_phase_t := IDLE; - - type u_addr_mode_t is (MONOTONIC, RANDOM); - signal u_addr_mode : u_addr_mode_t := MONOTONIC; - signal cycle_cnt : natural := 1; - signal data_cnt : natural := 0; - signal efficiency : real := 0.0; - -begin - - clk_fb <= part_clk_p after 1 ns; - - -- DDR SDRAM Controller Core - inst_sdram_ctrl : entity work.sdram_ctrl_top - Generic map - ( - BL => BURST_LEN, - read_phaseshift => 0, - f_sysclk => 100E6 - ) - Port map - ( - - sys_rst_in => rst, - sys_clk_in => clk, - - sys_rst_out => rst_out, - sys_clk_out => clk_out, - sys_clk_fb => clk_fb, - - -- User interface - u_data_vld => u_data_vld, - u_data_req_w => u_req_wr, - u_data_req_r => u_req_rd, - u_tag_in => u_tag_in, - u_tag_rd => u_tag_rd, - u_tag_wr => u_tag_wr, - u_busy => u_busy, - u_addr => u_addr, - u_cmd => u_cmd, - u_cmd_we => u_cmd_we, - u_data_wr => u_data_w, - u_data_rd => u_data_r, - u_dm_wr_in => u_dm, - u_dm_rd_in => u_dm_rd_in, - u_dm_rd_out => u_dm_rd_out, - - -- SDRAM signals - sd_clk_p => part_clk_p, - sd_clk_n => part_clk_n, - sd_cke => part_cke, - sd_cs_n => part_cs_n, - sd_cas_n => part_cas_n, - sd_ras_n => part_ras_n, - sd_we_n => part_we_n, - sd_addr => part_addr, - sd_ba => part_ba, - sd_dm => part_dm, - sd_dqs => part_dqs, - sd_data => part_data - - ); - - -- MICRON DDR SDRAM Simulation Model - i_mt46v16m16_0 : entity work.mt46v16m16 - port map ( - dq => std_logic_vector(part_data), - dqs => std_logic_vector(part_dqs), - addr => std_logic_vector(part_addr), - ba => std_logic_vector(part_ba), - clk => part_clk_p, - clk_n => part_clk_n, - cke => part_cke, - cs_n => part_cs_n, - ras_n => part_ras_n, - cas_n => part_cas_n, - we_n => part_we_n, - dm => std_logic_vector(part_dm) - ); - -CLK_GEN: process - begin - wait for CLK_PERIOD/2; - clk <= not clk; - end process; - ------------------------------------------------------------------------------------------- - -R_DATA_COMPARE: - process(clk_out) - variable last_data : unsigned(7 downto 0) := (others => '0'); - begin - if rising_edge(clk_out) then - if u_data_vld='1' then - if u_read_en = '1' then - assert (ref_data = u_data_r) report "Error on read!" severity failure; - end if; - for i in 0 to DDR_DATA_WIDTH/4-1 loop - ref_data((i+1)*DDR_DATA_WIDTH/2-1 downto i*DDR_DATA_WIDTH/2) <= last_data + i + 1; - end loop; - last_data := last_data + DDR_DATA_WIDTH/4; - elsif u_read_en = '0' then - last_data := (others => '0'); - ref_data <= (others => '0'); - end if; - end if; - end process; - -W_DATA_GEN: - process(clk_out) - variable last_data : unsigned(7 downto 0) := (others => '0'); - begin - if rising_edge(clk_out) then - if u_req_wr = '1' then - for i in 0 to DDR_DATA_WIDTH/4-1 loop - u_data_w((i+1)*DDR_DATA_WIDTH/2-1 downto i*DDR_DATA_WIDTH/2) <= last_data + i + 1; - end loop; - last_data := last_data + DDR_DATA_WIDTH/4; - elsif u_write_en = '0' then - last_data := (others => '0'); - u_data_w <= (others => '0'); - end if; - end if; - end process; - -ADDR_GEN: - process(clk_out) - variable last_data : unsigned(7 downto 0) := (others => '0'); - begin - if rising_edge(clk_out) then - if u_addr_load = '1' then - u_addr <= u_addr_preset; - elsif u_addr_cnt_en = '1' then - if u_addr_mode = MONOTONIC then - u_addr <= u_addr + BURST_LEN; - else - if u_addr(u_addr'left) = '1' then - if BURST_LEN = 2 then - u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)) <= (u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)) & u_addr(u_addr'left)) xor "10000000000010001010100"; - elsif BURST_LEN = 4 then - u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)) <= (u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)) & u_addr(u_addr'left)) xor "1000000000010011010110"; - elsif BURST_LEN = 8 then - u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)) <= (u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)) & u_addr(u_addr'left)) xor "100000000001011110100"; - end if; - else - u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)-1) <= u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)-1) & u_addr(u_addr'left); - end if; - end if; - end if; - end if; - end process; - -performance_count: - process(clk_out) - begin - if rising_edge(clk_out) then - if u_write_en = '1' or u_read_en = '1' then - cycle_cnt <= cycle_cnt + 1; - if u_req_wr = '1' or u_req_rd = '1' then - data_cnt <= data_cnt + 1; - end if; - else - cycle_cnt <= 1; - data_cnt <= 0; - end if; - end if; - end process; - - u_tag_in <= ("00" & u_write_en & u_read_en) when ((u_addr = X"333C98" or u_addr = X"000100") and u_cmd_we = '1') else "0000"; - - efficiency <= real(data_cnt)/real(cycle_cnt); - u_cmd_we <= (u_write_en or u_read_en) and (not u_busy); - u_addr_cnt_en <= '1' when (u_cmd_we = '1' and (u_addr /= u_addr_end)) else '0'; - - process - begin - - -- Write MAX_WORDS to DDR SDRAM Controller - wait for 4*CLK_PERIOD; - rst <= '0'; - - wait until rising_edge(clk_out) and u_busy='0'; - wait for 137*CLK_PERIOD; - - - wait until rising_edge(clk_out) and u_busy='0'; - -- Bank 0 - u_addr_preset <= X"000000"; - u_addr_end <= X"008000"-BURST_LEN; - u_addr_load <= '1'; - wait until rising_edge(clk_out); - u_addr_load <= '0'; - wait until rising_edge(clk_out); - u_cmd <= UCMD_WRITE; - u_write_en <= '1'; - while u_addr /= u_addr_end loop - wait until rising_edge(clk_out); - end loop; - u_write_en <= '0'; - wait until rising_edge(clk_out) and u_req_wr='0'; - - wait until rising_edge(clk_out) and u_busy='0'; - -- Bank 1 - u_addr_preset <= X"400000"; - u_addr_end <= X"408000"-BURST_LEN; - u_addr_load <= '1'; - wait until rising_edge(clk_out); - u_addr_load <= '0'; - wait until rising_edge(clk_out); - u_cmd <= UCMD_WRITE; - u_write_en <= '1'; - while u_addr /= u_addr_end loop - wait until rising_edge(clk_out); - end loop; - u_write_en <= '0'; - wait until rising_edge(clk_out) and u_req_wr='0'; - - wait until rising_edge(clk_out) and u_busy='0'; - -- Bank 0 - u_addr_preset <= X"000000"; - u_addr_end <= X"008000"-BURST_LEN; - u_addr_load <= '1'; - wait until rising_edge(clk_out); - u_addr_load <= '0'; - wait until rising_edge(clk_out); - u_cmd <= UCMD_READ; - u_read_en <= '1'; - while u_addr /= u_addr_end loop - wait until rising_edge(clk_out); - end loop; - u_read_en <= '0'; - wait until rising_edge(clk_out) and u_data_vld='0'; - - wait until rising_edge(clk_out) and u_busy='0'; - -- Bank 1 - u_addr_preset <= X"400000"; - u_addr_end <= X"408000"-BURST_LEN; - u_addr_load <= '1'; - wait until rising_edge(clk_out); - u_addr_load <= '0'; - wait until rising_edge(clk_out); - u_cmd <= UCMD_READ; - u_read_en <= '1'; - while u_addr /= u_addr_end loop - wait until rising_edge(clk_out); - end loop; - u_read_en <= '0'; - wait until rising_edge(clk_out) and u_data_vld='0'; - - wait; - - end process; - -end architecture struct; diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_fifo.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_fifo.vhd deleted file mode 100644 index 51910b0..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_fifo.vhd +++ /dev/null @@ -1,420 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: cpu_embedded using cpu_core and rom --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.fifo_ctrl_pkg.all; -use work.sdram_config.all; -use work.sdram_types.all; - -entity tb_sdr_ctrl_fifo is -end; - -architecture struct of tb_sdr_ctrl_fifo is - - -- Number of user data words for simulation - constant CLK_PERIOD : time := 10 ns; - constant BURST_LEN : natural := 2; - - signal rst : std_logic := '1'; - signal clk : std_logic := '0'; - signal rst_out : std_logic; - signal clk_out : std_logic; - signal clk_fb : std_logic; - signal part_clk_p : std_logic; - signal part_clk_n : std_logic; - signal part_cke : std_logic; - signal part_cs_n : std_logic; - signal part_we_n : std_logic; - signal part_ras_n : std_logic; - signal part_cas_n : std_logic; - signal part_ba : unsigned(DDR_BANK_WIDTH-1 downto 0) := (others => '0'); - signal part_dm : unsigned(DDR_DM_WIDTH-1 downto 0) := (others => '0'); - signal part_dqs : unsigned(DDR_DQS_WIDTH-1 downto 0) := (others => '0'); - signal part_addr : unsigned(DDR_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal part_data : unsigned(DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - - signal u_addr : user_addr_t := (others => '0'); - signal u_tag_in : user_tag_t := "0000"; - signal u_tag_rd : user_tag_t; - signal u_tag_wr : user_tag_t; - signal u_cmd : user_cmd_t := UCMD_NOP; - signal u_cmd_we : std_logic := '0'; - signal u_busy : std_logic; - signal u_data_w : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - signal u_dm : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000"; - signal u_dm_rd_in : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000"; - signal u_dm_rd_out : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000"; - signal u_data_r : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - signal u_data_vld : std_logic; - signal u_req_wr : std_logic; - signal u_req_rd : std_logic; - signal u_read_en : std_logic := '0'; - signal u_write_en : std_logic := '0'; - - signal cmd_fifo_din : unsigned(25 downto 0) := (others => '0'); - signal cmd_fifo_dout : unsigned(25 downto 0) := (others => '0'); - signal cmd_fifo_re : std_logic := '0'; - signal cmd_fifo_we : std_logic := '0'; - signal cmd_fifo_full : std_logic := '0'; - signal cmd_fifo_empty : std_logic := '0'; - signal cmd_fifo_almost_full : std_logic := '0'; - signal cmd_fifo_almost_empty : std_logic := '0'; - - signal write_fifo_din : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - signal write_fifo_dout : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - signal write_fifo_re : std_logic := '0'; - signal write_fifo_we : std_logic := '0'; - signal write_fifo_full : std_logic := '0'; - signal write_fifo_empty : std_logic := '0'; - signal write_fifo_almost_full : std_logic := '0'; - signal write_fifo_almost_empty : std_logic := '0'; - - signal read_fifo_din : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - signal read_fifo_dout : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - signal read_fifo_re : std_logic := '0'; - signal read_fifo_we : std_logic := '0'; - signal read_fifo_full : std_logic := '0'; - signal read_fifo_empty : std_logic := '0'; - signal read_fifo_almost_full : std_logic := '0'; - signal read_fifo_almost_empty : std_logic := '0'; - - signal write_start : std_logic := '1'; - signal read_start : std_logic := '1'; - - alias cmd_fifo_in is cmd_fifo_din(25 downto 24); - alias addr_fifo_in is cmd_fifo_din(23 downto 0); - alias cmd_fifo_out is cmd_fifo_dout(25 downto 24); - alias addr_fifo_out is cmd_fifo_dout(23 downto 0); - -begin - - clk_fb <= part_clk_p after 1 ns; - - -- Instantiate synchronous FIFO - inst_command_fifo: entity work.fifo_sync - GENERIC MAP - ( - addr_width => 8, - data_width => 2+24 - ) - PORT MAP - ( - rst => rst_out, - clk => clk_out, - we => cmd_fifo_we, - re => cmd_fifo_re, - fifo_full => cmd_fifo_full, - fifo_empty => cmd_fifo_empty, - fifo_afull => cmd_fifo_almost_full, - fifo_aempty => cmd_fifo_almost_empty, - data_w => cmd_fifo_din, - data_r => cmd_fifo_dout - ); - - -- Instantiate synchronous FIFO - inst_write_fifo: entity work.fifo_sync - GENERIC MAP - ( - addr_width => 8, - data_width => 2*DDR_DATA_WIDTH - ) - PORT MAP - ( - rst => rst_out, - clk => clk_out, - we => write_fifo_we, - re => write_fifo_re, - fifo_full => write_fifo_full, - fifo_empty => write_fifo_empty, - fifo_afull => write_fifo_almost_full, - fifo_aempty => write_fifo_almost_empty, - data_w => write_fifo_din, - data_r => write_fifo_dout - ); - - -- Instantiate synchronous FIFO - inst_read_fifo: entity work.fifo_sync - GENERIC MAP - ( - addr_width => 8, - data_width => 2*DDR_DATA_WIDTH - ) - PORT MAP - ( - rst => rst_out, - clk => clk_out, - we => read_fifo_we, - re => read_fifo_re, - fifo_full => read_fifo_full, - fifo_empty => read_fifo_empty, - fifo_afull => read_fifo_almost_full, - fifo_aempty => read_fifo_almost_empty, - data_w => read_fifo_din, - data_r => read_fifo_dout - ); - - -- DDR SDRAM Controller Core - inst_sdram_ctrl : entity work.sdram_ctrl_top - Generic map - ( - BL => BURST_LEN, - read_phaseshift => 0, - f_sysclk => 100E6 - ) - Port map - ( - - sys_rst_in => rst, - sys_clk_in => clk, - - sys_rst_out => rst_out, - sys_clk_out => clk_out, - sys_clk_fb => clk_fb, - - -- User interface - u_data_vld => u_data_vld, - u_data_req_w => u_req_wr, - u_data_req_r => u_req_rd, - u_tag_in => u_tag_in, - u_tag_rd => u_tag_rd, - u_tag_wr => u_tag_wr, - u_busy => u_busy, - u_addr => u_addr, - u_cmd => u_cmd, - u_cmd_we => u_cmd_we, - u_data_wr => u_data_w, - u_data_rd => u_data_r, - u_dm_wr_in => u_dm, - u_dm_rd_in => u_dm_rd_in, - u_dm_rd_out => u_dm_rd_out, - - -- SDRAM signals - sd_clk_p => part_clk_p, - sd_clk_n => part_clk_n, - sd_cke => part_cke, - sd_cs_n => part_cs_n, - sd_cas_n => part_cas_n, - sd_ras_n => part_ras_n, - sd_we_n => part_we_n, - sd_addr => part_addr, - sd_ba => part_ba, - sd_dm => part_dm, - sd_dqs => part_dqs, - sd_data => part_data - - ); - - -- MICRON DDR SDRAM Simulation Model - i_mt46v16m16_0 : entity work.mt46v16m16 - port map ( - dq => std_logic_vector(part_data), - dqs => std_logic_vector(part_dqs), - addr => std_logic_vector(part_addr), - ba => std_logic_vector(part_ba), - clk => part_clk_p, - clk_n => part_clk_n, - cke => part_cke, - cs_n => part_cs_n, - ras_n => part_ras_n, - cas_n => part_cas_n, - we_n => part_we_n, - dm => std_logic_vector(part_dm) - ); - -CLK_GEN: process - begin - wait for CLK_PERIOD/2; - clk <= not clk; - end process; - ------------------------------------------------------------------------------------------- - u_cmd_we <= (not cmd_fifo_empty) and write_start and (not u_busy); - u_cmd <= cmd_fifo_out; - u_addr <= addr_fifo_out; - - write_fifo_re <= u_req_wr and (not write_fifo_empty); - cmd_fifo_re <= u_cmd_we; - u_data_w <= write_fifo_dout; - read_fifo_re <= (not read_fifo_empty) and read_start; - read_fifo_we <= u_data_vld; - read_fifo_din <= u_data_r; - - process - begin - - -- Write MAX_WORDS to DDR SDRAM Controller - wait for 4*CLK_PERIOD; - rst <= '0'; - - wait for 4*CLK_PERIOD; - wait until rising_edge(clk_out) and rst_out='0'; - - write_fifo_we <= '1'; - cmd_fifo_we <= '1'; - write_fifo_din <= X"01020304"; - cmd_fifo_in <= UCMD_WRITE; - addr_fifo_in <= X"000000"; - - wait until rising_edge(clk_out); - write_fifo_we <= '1'; - write_fifo_din <= X"05060708"; - cmd_fifo_in <= UCMD_WRITE; - addr_fifo_in <= X"000002"; - - wait until rising_edge(clk_out); - write_fifo_we <= '1'; - write_fifo_din <= X"00001111"; - cmd_fifo_in <= UCMD_WRITE; - addr_fifo_in <= X"000004"; - - wait until rising_edge(clk_out); - write_fifo_we <= '1'; - write_fifo_din <= X"22223333"; - cmd_fifo_in <= UCMD_WRITE; - addr_fifo_in <= X"000006"; - - wait until rising_edge(clk_out); - write_fifo_we <= '1'; - write_fifo_din <= X"44445555"; - cmd_fifo_in <= UCMD_WRITE; - addr_fifo_in <= X"000008"; - - wait until rising_edge(clk_out); - write_fifo_we <= '1'; - write_fifo_din <= X"66667777"; - cmd_fifo_in <= UCMD_WRITE; - addr_fifo_in <= X"00000a"; - - wait until rising_edge(clk_out); - write_fifo_we <= '1'; - write_fifo_din <= X"88889999"; - cmd_fifo_in <= UCMD_WRITE; - addr_fifo_in <= X"00000c"; - - wait until rising_edge(clk_out); - write_fifo_we <= '1'; - write_fifo_din <= X"AAAABBBB"; - cmd_fifo_in <= UCMD_WRITE; - addr_fifo_in <= X"00000e"; - - wait until rising_edge(clk_out); - write_fifo_we <= '1'; - write_fifo_din <= X"CCCCDDDD"; - cmd_fifo_in <= UCMD_WRITE; - addr_fifo_in <= X"000010"; - - wait until rising_edge(clk_out); - write_fifo_we <= '1'; - write_fifo_din <= X"EEEEFFFF"; - cmd_fifo_in <= UCMD_WRITE; - addr_fifo_in <= X"000012"; - - wait until rising_edge(clk_out); - write_fifo_we <= '0'; - cmd_fifo_we <= '0'; - --- wait until rising_edge(clk_out) and u_busy='0'; --- write_start <= '1'; --- wait until rising_edge(clk_out) and write_fifo_empty='1'; - - write_fifo_we <= '1'; - cmd_fifo_we <= '1'; - write_fifo_din <= X"01234567"; - cmd_fifo_in <= UCMD_WRITE; - addr_fifo_in <= X"000014"; - - wait until rising_edge(clk_out); - write_fifo_we <= '0'; - cmd_fifo_in <= UCMD_READ; - addr_fifo_in <= X"000014"; - - wait until rising_edge(clk_out); - write_fifo_we <= '1'; - write_fifo_din <= X"89ABCDEF"; - cmd_fifo_in <= UCMD_WRITE; - addr_fifo_in <= X"000016"; - - wait until rising_edge(clk_out); - write_fifo_we <= '1'; - write_fifo_din <= X"11223344"; - cmd_fifo_in <= UCMD_WRITE; - addr_fifo_in <= X"000018"; - - wait until rising_edge(clk_out); - write_fifo_we <= '0'; - cmd_fifo_in <= UCMD_READ; - addr_fifo_in <= X"000010"; - - wait until rising_edge(clk_out); - write_fifo_we <= '1'; - write_fifo_din <= X"55667788"; - cmd_fifo_in <= UCMD_WRITE; - addr_fifo_in <= X"00001a"; - - wait until rising_edge(clk_out); - write_fifo_we <= '1'; - write_fifo_din <= X"99990000"; - cmd_fifo_in <= UCMD_WRITE; - addr_fifo_in <= X"00001c"; - - wait until rising_edge(clk_out); - write_fifo_we <= '1'; - write_fifo_din <= X"AAAA5555"; - cmd_fifo_in <= UCMD_WRITE; - addr_fifo_in <= X"000020"; - - wait until rising_edge(clk_out); - write_fifo_we <= '0'; - cmd_fifo_in <= UCMD_READ; - addr_fifo_in <= X"000000"; - - wait until rising_edge(clk_out); - cmd_fifo_in <= UCMD_READ; - addr_fifo_in <= X"000018"; - - wait until rising_edge(clk_out); - cmd_fifo_in <= UCMD_READ; - addr_fifo_in <= X"00001A"; - - wait until rising_edge(clk_out); - cmd_fifo_in <= UCMD_READ; - addr_fifo_in <= X"00001C"; - - wait until rising_edge(clk_out); - cmd_fifo_in <= UCMD_READ; - addr_fifo_in <= X"000020"; - - wait until rising_edge(clk_out); - write_fifo_we <= '0'; - cmd_fifo_we <= '0'; - - wait for 40*CLK_PERIOD; - read_start <= '1'; - wait; - - end process; - -end architecture struct; diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_lin_r_rand_w.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_lin_r_rand_w.vhd deleted file mode 100644 index 961b58e..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_lin_r_rand_w.vhd +++ /dev/null @@ -1,322 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: cpu_embedded using cpu_core and rom --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.sdram_config.all; -use work.sdram_types.all; -use work.utils_pkg.all; - -entity tb_sdr_ctrl is -end; - -architecture struct of tb_sdr_ctrl is - - -- Number of user data words for simulation - constant CLK_PERIOD : time := 10 ns; - constant BURST_LEN : natural := 8; - - signal rst : std_logic := '1'; - signal clk : std_logic := '0'; - signal rst_out : std_logic; - signal clk_out : std_logic; - signal clk_fb : std_logic; - signal part_clk_p : std_logic; - signal part_clk_n : std_logic; - signal part_cke : std_logic; - signal part_cs_n : std_logic; - signal part_we_n : std_logic; - signal part_ras_n : std_logic; - signal part_cas_n : std_logic; - signal part_ba : unsigned(DDR_BANK_WIDTH-1 downto 0) := (others => '0'); - signal part_dm : unsigned(DDR_DM_WIDTH-1 downto 0) := (others => '0'); - signal part_dqs : unsigned(DDR_DQS_WIDTH-1 downto 0) := (others => '0'); - signal part_addr : unsigned(DDR_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal part_data : unsigned(DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - - signal u_addr : user_addr_t := (others => '0'); - signal lin_addr : user_addr_t := (others => '0'); - signal rand_gen : unsigned(7 downto 0) := (others => '0'); - signal u_tag_in : user_tag_t := "0000"; - signal u_tag_rd : user_tag_t; - signal u_tag_wr : user_tag_t; - signal u_cmd : user_cmd_t := UCMD_NOP; - signal u_cmd_we : std_logic := '0'; - signal u_busy : std_logic; - signal u_data_w : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - signal u_dm : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000"; - signal u_dm_rd_in : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000"; - signal u_dm_rd_out : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000"; - signal u_data_r : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - signal u_data_vld : std_logic; - signal u_req_wr : std_logic; - signal u_req_rd : std_logic; - signal u_read_en : std_logic := '0'; - signal u_write_en : std_logic := '0'; - signal rw_null_en : std_logic := '0'; - signal u_addr_cnt_en : std_logic := '0'; - signal u_addr_load : std_logic := '0'; - signal u_addr_preset : user_addr_t := (others => '0'); - signal u_addr_end : user_addr_t := (others => '0'); - signal ref_data : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - - type test_phase_t is (IDLE, PART_INIT, WRITE_SINGLE, WRITE_MULTI, READ_SINGLE, READ_MULTI, FINISHED); - signal test_phase : test_phase_t := IDLE; - - type u_addr_mode_t is (MONOTONIC, RANDOM); - signal u_addr_mode : u_addr_mode_t := MONOTONIC; - signal cycle_cnt : natural := 1; - signal data_cnt : natural := 0; - signal efficiency : real := 0.0; - -begin - - clk_fb <= part_clk_p after 1 ns; - - -- DDR SDRAM Controller Core - inst_sdram_ctrl : entity work.sdram_ctrl_top - Generic map - ( - BL => BURST_LEN, - read_phaseshift => 0, - f_sysclk => 100E6 - ) - Port map - ( - - sys_rst_in => rst, - sys_clk_in => clk, - - sys_rst_out => rst_out, - sys_clk_out => clk_out, - sys_clk_fb => clk_fb, - - -- User interface - u_data_vld => u_data_vld, - u_data_req_w => u_req_wr, - u_data_req_r => u_req_rd, - u_tag_in => u_tag_in, - u_tag_rd => u_tag_rd, - u_tag_wr => u_tag_wr, - u_busy => u_busy, - u_addr => u_addr, - u_cmd => u_cmd, - u_cmd_we => u_cmd_we, - u_data_wr => u_data_w, - u_data_rd => u_data_r, - u_dm_wr_in => u_dm, - u_dm_rd_in => u_dm_rd_in, - u_dm_rd_out => u_dm_rd_out, - - -- SDRAM signals - sd_clk_p => part_clk_p, - sd_clk_n => part_clk_n, - sd_cke => part_cke, - sd_cs_n => part_cs_n, - sd_cas_n => part_cas_n, - sd_ras_n => part_ras_n, - sd_we_n => part_we_n, - sd_addr => part_addr, - sd_ba => part_ba, - sd_dm => part_dm, - sd_dqs => part_dqs, - sd_data => part_data - - ); - - -- MICRON DDR SDRAM Simulation Model - i_mt46v16m16_0 : entity work.mt46v16m16 - port map ( - dq => std_logic_vector(part_data), - dqs => std_logic_vector(part_dqs), - addr => std_logic_vector(part_addr), - ba => std_logic_vector(part_ba), - clk => part_clk_p, - clk_n => part_clk_n, - cke => part_cke, - cs_n => part_cs_n, - ras_n => part_ras_n, - cas_n => part_cas_n, - we_n => part_we_n, - dm => std_logic_vector(part_dm) - ); - -CLK_GEN: process - begin - wait for CLK_PERIOD/2; - clk <= not clk; - end process; - ------------------------------------------------------------------------------------------- - -R_DATA_COMPARE: - process(clk_out) - variable last_data : unsigned(7 downto 0) := (others => '0'); - begin - if rising_edge(clk_out) then - if u_data_vld='1' then - if u_read_en = '1' and u_tag_rd = "0000" then - assert (ref_data = u_data_r) report "Error on read!" severity failure; - for i in 0 to DDR_DATA_WIDTH/4-1 loop - ref_data((i+1)*DDR_DATA_WIDTH/2-1 downto i*DDR_DATA_WIDTH/2) <= last_data + i + 1; - end loop; - last_data := last_data + DDR_DATA_WIDTH/4; - end if; - elsif u_read_en = '0' and rw_null_en = '0' then - last_data := (others => '0'); - ref_data <= (others => '0'); - end if; - end if; - end process; - -W_DATA_GEN: - process(clk_out) - variable last_data : unsigned(7 downto 0) := (others => '0'); - begin - if rising_edge(clk_out) then - if u_req_wr = '1' and u_tag_wr = "0000" then - for i in 0 to DDR_DATA_WIDTH/4-1 loop - u_data_w((i+1)*DDR_DATA_WIDTH/2-1 downto i*DDR_DATA_WIDTH/2) <= last_data + i + 1; - end loop; - last_data := last_data + DDR_DATA_WIDTH/4; - elsif u_write_en = '0' and rw_null_en = '0' then - last_data := (others => '0'); - u_data_w <= (others => '0'); - end if; - end if; - end process; - -ADDR_GEN: - process(clk_out) - variable last_data : unsigned(7 downto 0) := (others => '0'); - begin - if rising_edge(clk_out) then - if u_addr_load = '1' then - lin_addr <= u_addr_preset; - rand_gen <= X"80"; - elsif u_addr_cnt_en = '1' then - lin_addr <= lin_addr + BURST_LEN; - if rand_gen(rand_gen'left) = '1' then - rand_gen <= (rand_gen(rand_gen'left-1 downto 0) & rand_gen(rand_gen'left)) xor "10010010"; - else - rand_gen <= rand_gen(rand_gen'left-1 downto 0) & rand_gen(rand_gen'left); - end if; - end if; - end if; - end process; - -performance_count: - process(clk_out) - begin - if rising_edge(clk_out) then - if u_write_en = '1' or u_read_en = '1' then - cycle_cnt <= cycle_cnt + 1; - if u_req_wr = '1' or u_req_rd = '1' then - data_cnt <= data_cnt + 1; - end if; - else - cycle_cnt <= 1; - data_cnt <= 0; - end if; - end if; - end process; - - u_tag_in <= "000" & rw_null_en; - - efficiency <= real(data_cnt)/real(cycle_cnt); - u_cmd_we <= (u_write_en or u_read_en or rw_null_en) and (not u_busy); - u_addr_cnt_en <= '1' when (u_cmd_we = '1' and (lin_addr /= u_addr_end)) else '0'; - u_addr <= (rand_gen(7) and (not rw_null_en)) & lin_addr(lin_addr'left-1 downto 0); - process - begin - - -- Write MAX_WORDS to DDR SDRAM Controller - wait for 4*CLK_PERIOD; - rst <= '0'; - - wait until rising_edge(clk_out) and u_busy='0'; - wait for 137*CLK_PERIOD; - - - wait until rising_edge(clk_out) and u_busy='0'; - -- Bank 0 - test_phase <= WRITE_MULTI; - u_addr_preset <= X"000000"; - u_addr_end <= X"010000"-BURST_LEN; - u_addr_load <= '1'; - wait until rising_edge(clk_out); - u_addr_load <= '0'; - wait until rising_edge(clk_out); - u_cmd <= UCMD_READ; - u_write_en <= '1'; - rw_null_en <= '1'; - while lin_addr /= u_addr_end loop - u_cmd <= UCMD_READ; - rw_null_en <= '1'; - if rand_gen(3) = '0' and rand_gen(4) = '0' and rand_gen(5) = '0' and rand_gen(6) = '0' then - if rand_gen(1) = '1' or rand_gen(7) = '1' then - u_cmd <= UCMD_WRITE; - end if; - rw_null_en <= '0'; - end if; - wait until rising_edge(clk_out); - end loop; - u_write_en <= '0'; - rw_null_en <= '0'; - wait until rising_edge(clk_out) and u_req_wr='0'; - wait for 200*CLK_PERIOD; - - wait until rising_edge(clk_out) and u_busy='0'; - -- Bank 0 - test_phase <= READ_MULTI; - u_addr_preset <= X"000000"; - u_addr_end <= X"010000"-BURST_LEN; - u_addr_load <= '1'; - wait until rising_edge(clk_out); - u_addr_load <= '0'; - wait until rising_edge(clk_out); - u_cmd <= UCMD_WRITE; - u_read_en <= '1'; - rw_null_en <= '1'; - while lin_addr /= u_addr_end loop - u_cmd <= UCMD_WRITE; - rw_null_en <= '1'; - if rand_gen(3) = '0' and rand_gen(4) = '0' and rand_gen(5) = '0' and rand_gen(6) = '0' then - if rand_gen(1) = '1' or rand_gen(7) = '1' then - u_cmd <= UCMD_READ; - end if; - rw_null_en <= '0'; - end if; - wait until rising_edge(clk_out); - end loop; - u_read_en <= '0'; - rw_null_en <= '0'; - wait until rising_edge(clk_out) and u_data_vld='0'; - - wait; - - end process; - -end architecture struct; diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_lin_w_rand_r.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_lin_w_rand_r.vhd deleted file mode 100644 index 286fb33..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_lin_w_rand_r.vhd +++ /dev/null @@ -1,320 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: cpu_embedded using cpu_core and rom --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.sdram_config.all; -use work.sdram_types.all; -use work.utils_pkg.all; - -entity tb_sdr_ctrl is -end; - -architecture struct of tb_sdr_ctrl is - - -- Number of user data words for simulation - constant CLK_PERIOD : time := 10 ns; - constant BURST_LEN : natural := 8; - - signal rst : std_logic := '1'; - signal clk : std_logic := '0'; - signal rst_out : std_logic; - signal clk_out : std_logic; - signal clk_fb : std_logic; - signal part_clk_p : std_logic; - signal part_clk_n : std_logic; - signal part_cke : std_logic; - signal part_cs_n : std_logic; - signal part_we_n : std_logic; - signal part_ras_n : std_logic; - signal part_cas_n : std_logic; - signal part_ba : unsigned(DDR_BANK_WIDTH-1 downto 0) := (others => '0'); - signal part_dm : unsigned(DDR_DM_WIDTH-1 downto 0) := (others => '0'); - signal part_dqs : unsigned(DDR_DQS_WIDTH-1 downto 0) := (others => '0'); - signal part_addr : unsigned(DDR_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal part_data : unsigned(DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - - signal u_addr : user_addr_t := (others => '0'); - signal lin_addr : user_addr_t := (others => '0'); - signal rand_gen : unsigned(7 downto 0) := (others => '0'); - signal u_tag_in : user_tag_t := "0000"; - signal u_tag_rd : user_tag_t; - signal u_tag_wr : user_tag_t; - signal u_cmd : user_cmd_t := UCMD_NOP; - signal u_cmd_we : std_logic := '0'; - signal u_busy : std_logic; - signal u_data_w : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - signal u_dm : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000"; - signal u_dm_rd_in : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000"; - signal u_dm_rd_out : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000"; - signal u_data_r : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - signal u_data_vld : std_logic; - signal u_req_wr : std_logic; - signal u_req_rd : std_logic; - signal u_read_en : std_logic := '0'; - signal u_write_en : std_logic := '0'; - signal rw_null_en : std_logic := '0'; - signal u_addr_cnt_en : std_logic := '0'; - signal u_addr_load : std_logic := '0'; - signal u_addr_preset : user_addr_t := (others => '0'); - signal u_addr_end : user_addr_t := (others => '0'); - signal ref_data : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - - type test_phase_t is (IDLE, PART_INIT, WRITE_SINGLE, WRITE_MULTI, READ_SINGLE, READ_MULTI, FINISHED); - signal test_phase : test_phase_t := IDLE; - - type u_addr_mode_t is (MONOTONIC, RANDOM); - signal u_addr_mode : u_addr_mode_t := MONOTONIC; - signal cycle_cnt : natural := 1; - signal data_cnt : natural := 0; - signal efficiency : real := 0.0; - -begin - - clk_fb <= part_clk_p after 1 ns; - - -- DDR SDRAM Controller Core - inst_sdram_ctrl : entity work.sdram_ctrl_top - Generic map - ( - BL => BURST_LEN, - read_phaseshift => 0, - f_sysclk => 100E6 - ) - Port map - ( - - sys_rst_in => rst, - sys_clk_in => clk, - - sys_rst_out => rst_out, - sys_clk_out => clk_out, - sys_clk_fb => clk_fb, - - -- User interface - u_data_vld => u_data_vld, - u_data_req_w => u_req_wr, - u_data_req_r => u_req_rd, - u_tag_in => u_tag_in, - u_tag_rd => u_tag_rd, - u_tag_wr => u_tag_wr, - u_busy => u_busy, - u_addr => u_addr, - u_cmd => u_cmd, - u_cmd_we => u_cmd_we, - u_data_wr => u_data_w, - u_data_rd => u_data_r, - u_dm_wr_in => u_dm, - u_dm_rd_in => u_dm_rd_in, - u_dm_rd_out => u_dm_rd_out, - - -- SDRAM signals - sd_clk_p => part_clk_p, - sd_clk_n => part_clk_n, - sd_cke => part_cke, - sd_cs_n => part_cs_n, - sd_cas_n => part_cas_n, - sd_ras_n => part_ras_n, - sd_we_n => part_we_n, - sd_addr => part_addr, - sd_ba => part_ba, - sd_dm => part_dm, - sd_dqs => part_dqs, - sd_data => part_data - - ); - - -- MICRON DDR SDRAM Simulation Model - i_mt46v16m16_0 : entity work.mt46v16m16 - port map ( - dq => std_logic_vector(part_data), - dqs => std_logic_vector(part_dqs), - addr => std_logic_vector(part_addr), - ba => std_logic_vector(part_ba), - clk => part_clk_p, - clk_n => part_clk_n, - cke => part_cke, - cs_n => part_cs_n, - ras_n => part_ras_n, - cas_n => part_cas_n, - we_n => part_we_n, - dm => std_logic_vector(part_dm) - ); - -CLK_GEN: process - begin - wait for CLK_PERIOD/2; - clk <= not clk; - end process; - ------------------------------------------------------------------------------------------- - -R_DATA_COMPARE: - process(clk_out) - variable last_data : unsigned(7 downto 0) := (others => '0'); - begin - if rising_edge(clk_out) then - if u_data_vld='1' then - if u_read_en = '1' and u_tag_rd = "0000" then - assert (ref_data = u_data_r) report "Error on read!" severity failure; - for i in 0 to DDR_DATA_WIDTH/4-1 loop - ref_data((i+1)*DDR_DATA_WIDTH/2-1 downto i*DDR_DATA_WIDTH/2) <= last_data + i + 1; - end loop; - last_data := last_data + DDR_DATA_WIDTH/4; - end if; - elsif u_read_en = '0' and rw_null_en = '0' then - last_data := (others => '0'); - ref_data <= (others => '0'); - end if; - end if; - end process; - -W_DATA_GEN: - process(clk_out) - variable last_data : unsigned(7 downto 0) := (others => '0'); - begin - if rising_edge(clk_out) then - if u_req_wr = '1' and u_tag_wr = "0000" then - for i in 0 to DDR_DATA_WIDTH/4-1 loop - u_data_w((i+1)*DDR_DATA_WIDTH/2-1 downto i*DDR_DATA_WIDTH/2) <= last_data + i + 1; - end loop; - last_data := last_data + DDR_DATA_WIDTH/4; - elsif u_write_en = '0' and rw_null_en = '0' then - last_data := (others => '0'); - u_data_w <= (others => '0'); - end if; - end if; - end process; - -ADDR_GEN: - process(clk_out) - variable last_data : unsigned(7 downto 0) := (others => '0'); - begin - if rising_edge(clk_out) then - if u_addr_load = '1' then - lin_addr <= u_addr_preset; - rand_gen <= X"80"; - elsif u_addr_cnt_en = '1' then - lin_addr <= lin_addr + BURST_LEN; - if rand_gen(rand_gen'left) = '1' then - rand_gen <= (rand_gen(rand_gen'left-1 downto 0) & rand_gen(rand_gen'left)) xor "10010010"; - else - rand_gen <= rand_gen(rand_gen'left-1 downto 0) & rand_gen(rand_gen'left); - end if; - end if; - end if; - end process; - -performance_count: - process(clk_out) - begin - if rising_edge(clk_out) then - if u_write_en = '1' or u_read_en = '1' then - cycle_cnt <= cycle_cnt + 1; - if u_req_wr = '1' or u_req_rd = '1' then - data_cnt <= data_cnt + 1; - end if; - else - cycle_cnt <= 1; - data_cnt <= 0; - end if; - end if; - end process; - - u_tag_in <= "000" & rw_null_en; - - efficiency <= real(data_cnt)/real(cycle_cnt); - u_cmd_we <= (u_write_en or u_read_en or rw_null_en) and (not u_busy); - u_addr_cnt_en <= '1' when (u_cmd_we = '1' and (lin_addr /= u_addr_end)) else '0'; - u_addr <= (rand_gen(7) and (rw_null_en)) & lin_addr(lin_addr'left-1 downto 0); - process - begin - - -- Write MAX_WORDS to DDR SDRAM Controller - wait for 4*CLK_PERIOD; - rst <= '0'; - - wait until rising_edge(clk_out) and u_busy='0'; - wait for 137*CLK_PERIOD; - - - wait until rising_edge(clk_out) and u_busy='0'; - -- Bank 0 - test_phase <= WRITE_MULTI; - u_addr_preset <= X"000000"; - u_addr_end <= X"010000"-BURST_LEN; - u_addr_load <= '1'; - wait until rising_edge(clk_out); - u_addr_load <= '0'; - wait until rising_edge(clk_out); - u_cmd <= UCMD_WRITE; - u_write_en <= '1'; - while lin_addr /= u_addr_end loop - u_cmd <= UCMD_WRITE; - rw_null_en <= '0'; - if rand_gen(3) = '0' and rand_gen(4) = '0' and rand_gen(5) = '0' and rand_gen(6) = '0' then - if rand_gen(1) = '1' or rand_gen(7) = '1' then - u_cmd <= UCMD_READ; - end if; - rw_null_en <= '1'; - end if; - wait until rising_edge(clk_out); - end loop; - u_write_en <= '0'; - rw_null_en <= '0'; - wait until rising_edge(clk_out) and u_req_wr='0'; - wait for 200*CLK_PERIOD; - - wait until rising_edge(clk_out) and u_busy='0'; - -- Bank 0 - test_phase <= READ_MULTI; - u_addr_preset <= X"000000"; - u_addr_end <= X"010000"-BURST_LEN; - u_addr_load <= '1'; - wait until rising_edge(clk_out); - u_addr_load <= '0'; - wait until rising_edge(clk_out); - u_cmd <= UCMD_READ; - u_read_en <= '1'; - while lin_addr /= u_addr_end loop - u_cmd <= UCMD_READ; - rw_null_en <= '0'; - if rand_gen(3) = '0' and rand_gen(4) = '0' and rand_gen(5) = '0' and rand_gen(6) = '0' then - if rand_gen(1) = '1' or rand_gen(7) = '1' then - u_cmd <= UCMD_WRITE; - end if; - rw_null_en <= '1'; - end if; - wait until rising_edge(clk_out); - end loop; - u_read_en <= '0'; - rw_null_en <= '0'; - wait until rising_edge(clk_out) and u_data_vld='0'; - - wait; - - end process; - -end architecture struct; diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_rand_addr.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_rand_addr.vhd deleted file mode 100644 index 5f96aa3..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_rand_addr.vhd +++ /dev/null @@ -1,319 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: cpu_embedded using cpu_core and rom --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.sdram_config.all; -use work.sdram_types.all; -use work.utils_pkg.all; - -entity tb_sdr_ctrl is -end; - -architecture struct of tb_sdr_ctrl is - - -- Number of user data words for simulation - constant CLK_PERIOD : time := 10 ns; - constant BURST_LEN : natural := 8; - - signal rst : std_logic := '1'; - signal clk : std_logic := '0'; - signal rst_out : std_logic; - signal clk_out : std_logic; - signal clk_fb : std_logic; - signal part_clk_p : std_logic; - signal part_clk_n : std_logic; - signal part_cke : std_logic; - signal part_cs_n : std_logic; - signal part_we_n : std_logic; - signal part_ras_n : std_logic; - signal part_cas_n : std_logic; - signal part_ba : unsigned(DDR_BANK_WIDTH-1 downto 0) := (others => '0'); - signal part_dm : unsigned(DDR_DM_WIDTH-1 downto 0) := (others => '0'); - signal part_dqs : unsigned(DDR_DQS_WIDTH-1 downto 0) := (others => '0'); - signal part_addr : unsigned(DDR_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal part_data : unsigned(DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - - signal u_addr : user_addr_t := (others => '0'); - signal u_tag_in : user_tag_t := "0000"; - signal u_tag_rd : user_tag_t; - signal u_tag_wr : user_tag_t; - signal u_cmd : user_cmd_t := UCMD_NOP; - signal u_cmd_we : std_logic := '0'; - signal u_busy : std_logic; - signal u_data_w : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - signal u_dm : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000"; - signal u_dm_rd_in : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000"; - signal u_dm_rd_out : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000"; - signal u_data_r : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - signal u_data_vld : std_logic; - signal u_req_wr : std_logic; - signal u_req_rd : std_logic; - signal u_read_en : std_logic := '0'; - signal u_write_en : std_logic := '0'; - signal u_addr_cnt_en : std_logic := '0'; - signal u_addr_load : std_logic := '0'; - signal u_addr_preset : user_addr_t := (others => '0'); - signal u_addr_end : user_addr_t := (others => '0'); - signal ref_data : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - - type test_phase_t is (IDLE, PART_INIT, WRITE_SINGLE, WRITE_MULTI, READ_SINGLE, READ_MULTI, FINISHED); - signal test_phase : test_phase_t := IDLE; - - type u_addr_mode_t is (MONOTONIC, RANDOM); - signal u_addr_mode : u_addr_mode_t := MONOTONIC; - signal cycle_cnt : natural := 1; - signal data_cnt : natural := 0; - signal efficiency : real := 0.0; - -begin - - clk_fb <= part_clk_p after 1 ns; - - -- DDR SDRAM Controller Core - inst_sdram_ctrl : entity work.sdram_ctrl_top - Generic map - ( - BL => BURST_LEN, - read_phaseshift => 0, - f_sysclk => 100E6 - ) - Port map - ( - - sys_rst_in => rst, - sys_clk_in => clk, - - sys_rst_out => rst_out, - sys_clk_out => clk_out, - sys_clk_fb => clk_fb, - - -- User interface - u_data_vld => u_data_vld, - u_data_req_w => u_req_wr, - u_data_req_r => u_req_rd, - u_tag_in => u_tag_in, - u_tag_rd => u_tag_rd, - u_tag_wr => u_tag_wr, - u_busy => u_busy, - u_addr => u_addr, - u_cmd => u_cmd, - u_cmd_we => u_cmd_we, - u_data_wr => u_data_w, - u_data_rd => u_data_r, - u_dm_wr_in => u_dm, - u_dm_rd_in => u_dm_rd_in, - u_dm_rd_out => u_dm_rd_out, - - -- SDRAM signals - sd_clk_p => part_clk_p, - sd_clk_n => part_clk_n, - sd_cke => part_cke, - sd_cs_n => part_cs_n, - sd_cas_n => part_cas_n, - sd_ras_n => part_ras_n, - sd_we_n => part_we_n, - sd_addr => part_addr, - sd_ba => part_ba, - sd_dm => part_dm, - sd_dqs => part_dqs, - sd_data => part_data - - ); - - -- MICRON DDR SDRAM Simulation Model - i_mt46v16m16_0 : entity work.mt46v16m16 - port map ( - dq => std_logic_vector(part_data), - dqs => std_logic_vector(part_dqs), - addr => std_logic_vector(part_addr), - ba => std_logic_vector(part_ba), - clk => part_clk_p, - clk_n => part_clk_n, - cke => part_cke, - cs_n => part_cs_n, - ras_n => part_ras_n, - cas_n => part_cas_n, - we_n => part_we_n, - dm => std_logic_vector(part_dm) - ); - -CLK_GEN: process - begin - wait for CLK_PERIOD/2; - clk <= not clk; - end process; - ------------------------------------------------------------------------------------------- - -R_DATA_COMPARE: - process(clk_out) - variable last_data : unsigned(7 downto 0) := (others => '0'); - begin - if rising_edge(clk_out) then - if u_data_vld='1' then - if u_read_en = '1' then - assert (ref_data = u_data_r) report "Error on read!" severity failure; - end if; - for i in 0 to DDR_DATA_WIDTH/4-1 loop - ref_data((i+1)*DDR_DATA_WIDTH/2-1 downto i*DDR_DATA_WIDTH/2) <= last_data + i + 1; - end loop; - last_data := last_data + DDR_DATA_WIDTH/4; - elsif u_read_en = '0' then - last_data := (others => '0'); - ref_data <= (others => '0'); - end if; - end if; - end process; - -W_DATA_GEN: - process(clk_out) - variable last_data : unsigned(7 downto 0) := (others => '0'); - begin - if rising_edge(clk_out) then - if u_req_wr = '1' then - for i in 0 to DDR_DATA_WIDTH/4-1 loop - u_data_w((i+1)*DDR_DATA_WIDTH/2-1 downto i*DDR_DATA_WIDTH/2) <= last_data + i + 1; - end loop; - last_data := last_data + DDR_DATA_WIDTH/4; - elsif u_write_en = '0' then - last_data := (others => '0'); - u_data_w <= (others => '0'); - end if; - end if; - end process; - -ADDR_GEN: - process(clk_out) - variable last_data : unsigned(7 downto 0) := (others => '0'); - begin - if rising_edge(clk_out) then - if u_addr_load = '1' then - u_addr <= u_addr_preset; - elsif u_addr_cnt_en = '1' then - if u_addr_mode = MONOTONIC then - u_addr <= u_addr + BURST_LEN; - else - if u_addr(u_addr'left) = '1' then - if BURST_LEN = 2 then - u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)) <= (u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)) & u_addr(u_addr'left)) xor "10000000000010001010100"; - elsif BURST_LEN = 4 then - u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)) <= (u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)) & u_addr(u_addr'left)) xor "1000000000010011010110"; - elsif BURST_LEN = 8 then - u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)) <= (u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)) & u_addr(u_addr'left)) xor "100000000001011110100"; - end if; - else - u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)-1) <= u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)-1) & u_addr(u_addr'left); - end if; - end if; - end if; - end if; - end process; - -performance_count: - process(clk_out) - begin - if rising_edge(clk_out) then - if u_write_en = '1' or u_read_en = '1' then - cycle_cnt <= cycle_cnt + 1; - if u_req_wr = '1' or u_req_rd = '1' then - data_cnt <= data_cnt + 1; - end if; - else - cycle_cnt <= 1; - data_cnt <= 0; - end if; - end if; - end process; - - u_tag_in <= ("00" & u_write_en & u_read_en) when ((u_addr = X"333C98" or u_addr = X"000100") and u_cmd_we = '1') else "0000"; - - efficiency <= real(data_cnt)/real(cycle_cnt); - u_cmd_we <= (u_write_en or u_read_en) and (not u_busy); - u_addr_cnt_en <= '1' when (u_cmd_we = '1' and (u_addr /= u_addr_end)) else '0'; - - process - begin - - -- Write MAX_WORDS to DDR SDRAM Controller - wait for 4*CLK_PERIOD; - rst <= '0'; - - wait until rising_edge(clk_out) and u_busy='0'; - wait for 137*CLK_PERIOD; - - wait until rising_edge(clk_out) and u_busy='0'; - -- Bank 0 - test_phase <= WRITE_MULTI; - u_addr_preset <= X"800000"; - if BURST_LEN = 2 then - u_addr_end <= X"5E2330"; - elsif BURST_LEN = 4 then - u_addr_end <= X"7DEDD0"; - elsif BURST_LEN = 8 then - u_addr_end <= X"5666B0"; - end if; - u_addr_load <= '1'; - wait until rising_edge(clk_out); - u_addr_load <= '0'; - wait until rising_edge(clk_out); - u_addr_mode <= RANDOM; - u_cmd <= UCMD_WRITE; - u_write_en <= '1'; - while u_addr /= u_addr_end loop - wait until rising_edge(clk_out); - end loop; - u_write_en <= '0'; - wait until rising_edge(clk_out) and u_req_wr='0'; - - wait until rising_edge(clk_out) and u_busy='0'; - -- Bank 0 - test_phase <= READ_MULTI; - u_addr_preset <= X"800000"; - if BURST_LEN = 2 then - u_addr_end <= X"5E2330"; - elsif BURST_LEN = 4 then - u_addr_end <= X"7DEDD0"; - elsif BURST_LEN = 8 then - u_addr_end <= X"5666B0"; - end if; - u_addr_load <= '1'; - wait until rising_edge(clk_out); - u_addr_load <= '0'; - wait until rising_edge(clk_out); - u_addr_mode <= RANDOM; - u_cmd <= UCMD_READ; - u_read_en <= '1'; - while u_addr /= u_addr_end loop - wait until rising_edge(clk_out); - end loop; - u_read_en <= '0'; - wait until rising_edge(clk_out) and u_data_vld='0'; - - wait; - - end process; - -end architecture struct; diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_rand_rw.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_rand_rw.vhd deleted file mode 100644 index c60d600..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_rand_rw.vhd +++ /dev/null @@ -1,333 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: cpu_embedded using cpu_core and rom --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.sdram_config.all; -use work.sdram_types.all; -use work.utils_pkg.all; - -entity tb_sdr_ctrl is -end; - -architecture struct of tb_sdr_ctrl is - - -- Number of user data words for simulation - constant CLK_PERIOD : time := 10 ns; - constant BURST_LEN : natural := 2; - - signal rst : std_logic := '1'; - signal clk : std_logic := '0'; - signal rst_out : std_logic; - signal clk_out : std_logic; - signal clk_fb : std_logic; - signal part_clk_p : std_logic; - signal part_clk_n : std_logic; - signal part_cke : std_logic; - signal part_cs_n : std_logic; - signal part_we_n : std_logic; - signal part_ras_n : std_logic; - signal part_cas_n : std_logic; - signal part_ba : unsigned(DDR_BANK_WIDTH-1 downto 0) := (others => '0'); - signal part_dm : unsigned(DDR_DM_WIDTH-1 downto 0) := (others => '0'); - signal part_dqs : unsigned(DDR_DQS_WIDTH-1 downto 0) := (others => '0'); - signal part_addr : unsigned(DDR_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal part_data : unsigned(DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - - signal u_addr : user_addr_t := (others => '0'); - signal u_tag_in : user_tag_t := "0000"; - signal u_tag_rd : user_tag_t; - signal u_tag_wr : user_tag_t; - signal u_cmd : user_cmd_t := UCMD_NOP; - signal u_cmd_we : std_logic := '0'; - signal u_busy : std_logic; - signal u_data_w : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - signal u_dm : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000"; - signal u_dm_rd_in : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000"; - signal u_dm_rd_out : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000"; - signal u_data_r : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - signal u_data_vld : std_logic; - signal u_req_wr : std_logic; - signal u_req_rd : std_logic; - signal u_read_en : std_logic := '0'; - signal u_write_en : std_logic := '0'; - signal rw_null_en : std_logic := '0'; - signal u_addr_cnt_en : std_logic := '0'; - signal u_addr_load : std_logic := '0'; - signal u_addr_preset : user_addr_t := (others => '0'); - signal u_addr_end : user_addr_t := (others => '0'); - signal ref_data : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - - type test_phase_t is (IDLE, PART_INIT, WRITE_SINGLE, WRITE_MULTI, READ_SINGLE, READ_MULTI, FINISHED); - signal test_phase : test_phase_t := IDLE; - - type u_addr_mode_t is (MONOTONIC, RANDOM); - signal u_addr_mode : u_addr_mode_t := MONOTONIC; - signal cycle_cnt : natural := 1; - signal data_cnt : natural := 0; - signal efficiency : real := 0.0; - -begin - - clk_fb <= part_clk_p after 1 ns; - - -- DDR SDRAM Controller Core - inst_sdram_ctrl : entity work.sdram_ctrl_top - Generic map - ( - BL => BURST_LEN, - read_phaseshift => 0, - f_sysclk => 100E6 - ) - Port map - ( - - sys_rst_in => rst, - sys_clk_in => clk, - - sys_rst_out => rst_out, - sys_clk_out => clk_out, - sys_clk_fb => clk_fb, - - -- User interface - u_data_vld => u_data_vld, - u_data_req_w => u_req_wr, - u_data_req_r => u_req_rd, - u_tag_in => u_tag_in, - u_tag_rd => u_tag_rd, - u_tag_wr => u_tag_wr, - u_busy => u_busy, - u_addr => u_addr, - u_cmd => u_cmd, - u_cmd_we => u_cmd_we, - u_data_wr => u_data_w, - u_data_rd => u_data_r, - u_dm_wr_in => u_dm, - u_dm_rd_in => u_dm_rd_in, - u_dm_rd_out => u_dm_rd_out, - - -- SDRAM signals - sd_clk_p => part_clk_p, - sd_clk_n => part_clk_n, - sd_cke => part_cke, - sd_cs_n => part_cs_n, - sd_cas_n => part_cas_n, - sd_ras_n => part_ras_n, - sd_we_n => part_we_n, - sd_addr => part_addr, - sd_ba => part_ba, - sd_dm => part_dm, - sd_dqs => part_dqs, - sd_data => part_data - - ); - - -- MICRON DDR SDRAM Simulation Model - i_mt46v16m16_0 : entity work.mt46v16m16 - port map ( - dq => std_logic_vector(part_data), - dqs => std_logic_vector(part_dqs), - addr => std_logic_vector(part_addr), - ba => std_logic_vector(part_ba), - clk => part_clk_p, - clk_n => part_clk_n, - cke => part_cke, - cs_n => part_cs_n, - ras_n => part_ras_n, - cas_n => part_cas_n, - we_n => part_we_n, - dm => std_logic_vector(part_dm) - ); - -CLK_GEN: process - begin - wait for CLK_PERIOD/2; - clk <= not clk; - end process; - ------------------------------------------------------------------------------------------- - -R_DATA_COMPARE: - process(clk_out) - variable last_data : unsigned(7 downto 0) := (others => '0'); - begin - if rising_edge(clk_out) then - if u_data_vld='1' then - if u_read_en = '1' then - assert (ref_data = u_data_r) report "Error on read!" severity failure; - end if; - for i in 0 to DDR_DATA_WIDTH/4-1 loop - ref_data((i+1)*DDR_DATA_WIDTH/2-1 downto i*DDR_DATA_WIDTH/2) <= last_data + i + 1; - end loop; - last_data := last_data + DDR_DATA_WIDTH/4; - elsif u_read_en = '0' and rw_null_en = '0' then - last_data := (others => '0'); - ref_data <= (others => '0'); - end if; - end if; - end process; - -W_DATA_GEN: - process(clk_out) - variable last_data : unsigned(7 downto 0) := (others => '0'); - begin - if rising_edge(clk_out) then - if u_req_wr = '1' then - for i in 0 to DDR_DATA_WIDTH/4-1 loop - u_data_w((i+1)*DDR_DATA_WIDTH/2-1 downto i*DDR_DATA_WIDTH/2) <= last_data + i + 1; - end loop; - last_data := last_data + DDR_DATA_WIDTH/4; - elsif u_write_en = '0' and rw_null_en = '0' then - last_data := (others => '0'); - u_data_w <= (others => '0'); - end if; - end if; - end process; - -ADDR_GEN: - process(clk_out) - variable last_data : unsigned(7 downto 0) := (others => '0'); - begin - if rising_edge(clk_out) then - if u_addr_load = '1' then - u_addr <= u_addr_preset; - elsif u_addr_cnt_en = '1' then - if u_addr_mode = MONOTONIC then - u_addr <= u_addr + BURST_LEN; - else - if u_addr(u_addr'left) = '1' then - if BURST_LEN = 2 then - u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)) <= (u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)) & u_addr(u_addr'left)) xor "10000000000010001010100"; - elsif BURST_LEN = 4 then - u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)) <= (u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)) & u_addr(u_addr'left)) xor "1000000000010011010110"; - elsif BURST_LEN = 8 then - u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)) <= (u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)) & u_addr(u_addr'left)) xor "100000000001011110100"; - end if; - else - u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)-1) <= u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)-1) & u_addr(u_addr'left); - end if; - end if; - end if; - end if; - end process; - -performance_count: - process(clk_out) - begin - if rising_edge(clk_out) then - if u_write_en = '1' or u_read_en = '1' then - cycle_cnt <= cycle_cnt + 1; - if u_req_wr = '1' or u_req_rd = '1' then - data_cnt <= data_cnt + 1; - end if; - else - cycle_cnt <= 1; - data_cnt <= 0; - end if; - end if; - end process; - - u_tag_in <= ("00" & u_write_en & u_read_en) when ((u_addr = X"333C98" or u_addr = X"000100") and u_cmd_we = '1') else "0000"; - - efficiency <= real(data_cnt)/real(cycle_cnt); - u_cmd_we <= (u_write_en or u_read_en or rw_null_en) and (not u_busy); - u_addr_cnt_en <= '1' when (u_cmd_we = '1' and (u_addr /= u_addr_end)) else '0'; - - process - begin - - -- Write MAX_WORDS to DDR SDRAM Controller - wait for 4*CLK_PERIOD; - rst <= '0'; - - wait until rising_edge(clk_out) and u_busy='0'; - wait for 137*CLK_PERIOD; - - -- Bank 0 - test_phase <= WRITE_MULTI; - u_addr_preset <= X"800000"; - if BURST_LEN = 2 then - u_addr_end <= X"646808"; - elsif BURST_LEN = 4 then - u_addr_end <= X"7DEDD0"; - elsif BURST_LEN = 8 then - u_addr_end <= X"5666B0"; - end if; - u_addr_load <= '1'; - wait until rising_edge(clk_out); - u_addr_load <= '0'; - wait until rising_edge(clk_out); - u_addr_mode <= RANDOM; - while u_addr /= u_addr_end loop - u_cmd <= UCMD_WRITE; - u_write_en <= '1'; - rw_null_en <= '0'; - if u_addr(20) = '0' then - u_cmd <= UCMD_READ; - u_write_en <= '0'; - rw_null_en <= '1'; - end if; - wait until rising_edge(clk_out); - end loop; - u_write_en <= '0'; - rw_null_en <= '0'; - wait for 200*CLK_PERIOD; - - wait until rising_edge(clk_out) and u_busy='0'; - -- Bank 0 - test_phase <= READ_MULTI; - u_addr_preset <= X"800000"; - if BURST_LEN = 2 then - u_addr_end <= X"646808"; - elsif BURST_LEN = 4 then - u_addr_end <= X"7DEDD0"; - elsif BURST_LEN = 8 then - u_addr_end <= X"5666B0"; - end if; - u_addr_load <= '1'; - wait until rising_edge(clk_out); - u_addr_load <= '0'; - wait until rising_edge(clk_out); - u_addr_mode <= RANDOM; - while u_addr /= u_addr_end loop - u_cmd <= UCMD_READ; - u_read_en <= '1'; - rw_null_en <= '0'; - if u_addr(20) = '0' then - u_cmd <= UCMD_WRITE; - u_read_en <= '0'; - rw_null_en <= '1'; - end if; - wait until rising_edge(clk_out); - end loop; - u_read_en <= '0'; - rw_null_en <= '0'; - wait until rising_edge(clk_out) and u_data_vld='0'; - - wait; - - end process; - -end architecture struct; diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdram_ctrl_frontend.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdram_ctrl_frontend.vhd deleted file mode 100644 index 95ffa58..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdram_ctrl_frontend.vhd +++ /dev/null @@ -1,385 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: cpu_embedded using cpu_core and rom --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.fifo_ctrl_pkg.all; -use work.sdram_config.all; -use work.sdram_types.all; - -entity tb_sdram_ctrl_frontend is -end; - -architecture struct of tb_sdram_ctrl_frontend is - - -- Number of user data words for simulation - constant CLK_PERIOD : time := 10 ns; - constant BURST_LEN : natural := 2; - - signal rst : std_logic := '1'; - signal clk : std_logic := '0'; - signal rst_out : std_logic; - signal clk_out : std_logic; - signal clk_fb : std_logic; - signal part_clk_p : std_logic; - signal part_clk_n : std_logic; - signal part_cke : std_logic; - signal part_cs_n : std_logic; - signal part_we_n : std_logic; - signal part_ras_n : std_logic; - signal part_cas_n : std_logic; - signal part_ba : unsigned(DDR_BANK_WIDTH-1 downto 0) := (others => '0'); - signal part_dm : unsigned(DDR_DM_WIDTH-1 downto 0) := (others => '0'); - signal part_dqs : unsigned(DDR_DQS_WIDTH-1 downto 0) := (others => '0'); - signal part_addr : unsigned(DDR_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal part_data : unsigned(DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - - signal addr : user_addr_t := (others => '0'); - signal r_wn : std_logic := '0'; - signal en : std_logic := '0'; - signal busy : std_logic; - signal din : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - signal be : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "1111"; - signal dout : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - signal dout_vld : std_logic; - signal dout_re : std_logic; - signal dout_reg : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - -begin - - clk_fb <= part_clk_p after 1 ns; - - -- DDR SDRAM Controller Core - inst_sdram_ctrl_frontend : entity work.sdram_ctrl_frontend - Generic map - ( - BL => BURST_LEN, - read_phaseshift => 0, - f_sysclk => 100E6, - fifo_depth => 4 - ) - Port map - ( - - sys_rst_in => rst, - sys_clk_in => clk, - - sys_rst_out => rst_out, - sys_clk_out => clk_out, - sys_clk_fb => clk_fb, - - busy => busy, - en => en, - r_wn => r_wn, - be => be, - addr => addr, - din => din, - dout => dout, - dout_re => dout_re, - dout_vld => dout_vld, - - -- SDRAM signals - sd_clk_p => part_clk_p, - sd_clk_n => part_clk_n, - sd_cke => part_cke, - sd_cs_n => part_cs_n, - sd_cas_n => part_cas_n, - sd_ras_n => part_ras_n, - sd_we_n => part_we_n, - sd_addr => part_addr, - sd_ba => part_ba, - sd_dm => part_dm, - sd_dqs => part_dqs, - sd_data => part_data - - ); - - -- MICRON DDR SDRAM Simulation Model - i_mt46v16m16_0 : entity work.mt46v16m16 - port map ( - dq => std_logic_vector(part_data), - dqs => std_logic_vector(part_dqs), - addr => std_logic_vector(part_addr), - ba => std_logic_vector(part_ba), - clk => part_clk_p, - clk_n => part_clk_n, - cke => part_cke, - cs_n => part_cs_n, - ras_n => part_ras_n, - cas_n => part_cas_n, - we_n => part_we_n, - dm => std_logic_vector(part_dm) - ); - -CLK_GEN: process - begin - wait for CLK_PERIOD/2; - clk <= not clk; - end process; - -read_register: - process(clk_out) - begin - if rising_edge(clk_out) then - if dout_vld = '1' then - dout_reg <= dout; - end if; - end if; - end process; - ------------------------------------------------------------------------------------------- - dout_re <= dout_vld; - - process - begin - - -- Write MAX_WORDS to DDR SDRAM Controller - wait for 4*CLK_PERIOD; - rst <= '0'; - - wait for 4*CLK_PERIOD; - wait until rising_edge(clk_out) and rst_out='0'; - - for i in 0 to 999 loop - en <= '1'; - r_wn <= '0'; - din <= to_unsigned(i, 32); - addr <= to_unsigned(2*i, 24); - wait until rising_edge(clk_out) and busy = '0'; - end loop; - - for i in 0 to 999 loop - en <= '1'; - r_wn <= '1'; - din <= to_unsigned(i, 32); - addr <= to_unsigned(2*i, 24); - wait until rising_edge(clk_out) and busy = '0'; - end loop; - - en <= '1'; - r_wn <= '0'; - din <= X"01020304"; - addr <= X"000000"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '0'; - din <= X"05060708"; - addr <= X"000002"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '0'; - din <= X"00001111"; - addr <= X"000004"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '0'; - din <= X"22223333"; - addr <= X"000006"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '0'; - din <= X"44445555"; - addr <= X"000008"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '0'; - din <= X"66667777"; - addr <= X"00000a"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '0'; - din <= X"88889999"; - addr <= X"00000c"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '0'; - din <= X"AAAABBBB"; - addr <= X"00000e"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '0'; - din <= X"CCCCDDDD"; - addr <= X"000010"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '0'; - din <= X"EEEEFFFF"; - addr <= X"000012"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '0'; - din <= X"FFFFFFFF"; - addr <= X"000014"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '1'; - addr <= X"000014"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '0'; - din <= X"87CCCCCC"; - be <= "1000"; - addr <= X"000014"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '1'; - addr <= X"000014"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '0'; - din <= X"CC65CCCC"; - be <= "0100"; - addr <= X"000014"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '1'; - addr <= X"000014"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '0'; - din <= X"CCCC43CC"; - be <= "0010"; - addr <= X"000014"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '1'; - addr <= X"000014"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '0'; - din <= X"89ABCDEF"; - addr <= X"000016"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '0'; - din <= X"CCCCCC21"; - be <= "0001"; - addr <= X"000014"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '1'; - addr <= X"000014"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '0'; - din <= X"55555555"; - be <= "1010"; - addr <= X"000014"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '1'; - addr <= X"000014"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '0'; - din <= X"AAAAAAAA"; - be <= "0101"; - addr <= X"000014"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '1'; - addr <= X"000014"; - - wait until rising_edge(clk_out) and busy = '0'; - be <= "1111"; - en <= '1'; - r_wn <= '0'; - din <= X"11223344"; - addr <= X"000018"; - - wait until rising_edge(clk_out) and busy = '0'; - r_wn <= '1'; - addr <= X"000010"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '0'; - din <= X"55667788"; - addr <= X"00001a"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '0'; - din <= X"99990000"; - addr <= X"00001c"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '0'; - din <= X"AAAA5555"; - addr <= X"000020"; - - wait until rising_edge(clk_out) and busy = '0'; - r_wn <= '1'; - addr <= X"000000"; - - wait until rising_edge(clk_out) and busy = '0'; - r_wn <= '1'; - addr <= X"000018"; - - wait until rising_edge(clk_out) and busy = '0'; - r_wn <= '1'; - addr <= X"00001A"; - - wait until rising_edge(clk_out) and busy = '0'; - r_wn <= '1'; - addr <= X"00001C"; - - wait until rising_edge(clk_out) and busy = '0'; - r_wn <= '1'; - addr <= X"000020"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '0'; - - wait; - - end process; - -end architecture struct; diff --git a/lib/SDRAM/ddr_sdr_v1_5/doc/SDRAM_CTRL.vsd b/lib/SDRAM/ddr_sdr_v1_5/doc/SDRAM_CTRL.vsd deleted file mode 100644 index 92e3c51a0a029ef3fda503bb45f1094cfd91d35c..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 91648 zcmeFZcT^MG`!~8LjiyehBBBW(iiie@itR9w&};-LR&*$Wg2GTmQJDy+*iNu}EGJP9 z_TwOmU4y+lh@u|bAOd1gCxRd3tqNNB$#=0l@y1J2{T~&)Z|*2^9bTD5M3a;LUe;bA>b4M)(|!jwh(p@_7Dyb-60$ydO$cq z^n`GR=mpUmLINR$aDi}zaD(Ur;SSLkq923@M1KfRhyf5@5Cb6wLC7GyAqGSEK*%A6 zKn#T#2H^`a9AX5-NQhAoqal8S@PjbT+5f=w43zM_0Ej?{Ac$ay5Qwo5;~>UEOn{gO z5elJ#2!oge5e^Xn5eX3mF&SbC#8ilB5Yr)MKtw~#gqQ_^L&QMDLc~GDL(GOqfJlUx z12GpO2_hL{9>jcz6o^y^0wN6}9U=oF6Cw*D8)5-O4#Yx;MG(0Viy@XkEQQE}AR*Kc z;qaFT_)RIi^HlgZ&&vrI2+Dk>6nb9*!lgz1!SP84l0t7Lf*H5JUcnxCNe1{fy4IkQh4vqmNnnM2*BJXBMyrz63&`#VIWyFnSTq+G%E!BY|&&y5EsRZ z;t971L|X)ATM(TZsp6|Fx0v2&}dUx@-}2g+jM20(6T&yhUKW zMNne1MPR!?^1Ik948$G=ok}SZ?8Xar;~xrk69l^ngWW{IZf3?{X_chTmh9aZ{NO_N zx#jm%Au(I+D*Es$`dr{wxcKpYaA*7N=fD=;UNDPS$bpHxzrcG$$AKZpN^ljd;J|9I z94h>ce!kGG{KZRJ2KAMlPE`N!uy%;Jo1+u5Tbj5%lRRgZT@aV zaCKOWk3(<;9GuM;SNiOPN|gT_&pEnu;9Z^tC|c=b-4#r(0+BrXE__VEXF8ViMu=X} z!zQ4!&@?#Dv%8EPy4LowV1my%8scVT!HT zTKpVVI{69z3J(lZZVv7Wc-8<(QIVkt7$F*o{HZEcT~<9(HB3yNwwymFY#gR|hA)wH zPAl%PB6<;Ut@t?K=$ig8<_K0r)FlqGuS<*^5Z;;0>rCc%&RJ?amtoPMEaVw?WUsgQ!4nPTL35LH3kXdH+Ox^{!}494 z09tVonApW%iU7XC9`Mb)rwD*6ljim*t&hJ{=-w5G#*h(YLT<^zNx>eHQ@#ck% zvj@eRqgrrcRfY75rdsoWD56^9z6q0kaw6FkqrYl=GFI zol1Cf`0IgjLN%DJU!X72Z`U8u-_Td;YxUqX6-Q^$D`=ocX-C?V7KG?4qujLgG5QK! zO~0i9kJ(6-P%>tbXdH7owj6*rhZQwhjE3399AeHhcc&qJo--d9j{3?4?q-j(_t__``8)PIOHX$1&h_U;aT7U!bGcjrx0!3vTcWn8I|@e86X{djE$%t@ z;q#BcCZjoIS%UzF0H~rf(+G}$WFR;pHG#`WikF5FnOR&!d`41QmNX2$lbV$PIe}zC zSmfZ5FE}p9q{1Haz;Y>6RIIV1BWvU;_|@t^o{4SOa<^c5gpF5rU9+ z%>`yQmLU7pyJl&N5r9gQU4g5;xJbjX`R%{wm|Gz^Yq=u9%J%lOwV-!z-WpD5?28UZ z$DuXRXez2kH=sNDYXSdzPP;|7-;0oTjTwiu|CrQd3{Qxko0Y)D&x5Q{nv=w3&6Q>) zEXeVV|TH; z02Mt4JoN+x*9o5!_k-*FjEgO;g4G}fQxaU-qKu?DbKwwpDEmtXj~L<0Nq^B0B}ZhW z5gD;rNgR%LBe#5bf{-}pK7ISl5h^@xv4%T5c z*dKaO1^xhk$`r}TGQ}{NLckMuL6&Z7GI~O{hzHk9X5e8V3TKj`_AAnAL|$-E-NV&? z9rV#62=fN|b_bh`Zh-R#FGll_wW24`e}O7|6gaW(34**-g6LqL0_eMJMUW9@-4O5{ z3>XEDoJWw6hIlZc$rv&KEcpYmLRQ3sQEhNqnw-H_uXoLm-w55-hj4vtR(UI?c{$)~ zuEq6JG#R_TYyM&doUNfJ$OHV|;D}dzS0~qhLc3Ts9bFs&zOA zs#6Al?oGx3IT%uG#)02Q2_~WO@b>@L8HhxvuIKT304G$B zUVQ+Y?~g*ip^MPy2<@WGtb~+}g1>=%=ey<(?j0u(;w&FB-6oL{^W}EjOFaIMy<8i^va~tlBsk+FJkveDhmE9oDk!gfbLOTfRF32h1@uo)@Nj^M=vA@7=nWiI?vuDgU6q)-c9>Hivt z8t3ff@)#I9Ki6w4&EH7)FMamz;ToZZUrL**ev>oXYm}Icn3td8dhpZZWTw3HKm;=_!>xD%=Hi6!&20H<> z4Mje#e~DKO_8bpopBJ0p>quZ#ljcf9?x;kD6#1-vjtrG5kzpQ6 z#CL(W5*c3Pa|jtRT=^UssZb)LLX^nplVM8ax2a0RFGh(R!{#d2O4I$3F$D|z8!CGS{-qcRm(g!7`LN?yuj4<&Dkw~{y2BjP!4+HfUrxkg< zn-v3_;B%F{m^39XcA@e)FHWuG#TP00vriVw`3VQ){KQf@KV{BoIe%`2oS$@4{+yp& zDd*37D(BBXSpz?6l=D-K@GsFW=cfTBKiypUoSz|9@-rQk{H&Aa5&Q)nO8!ER2>#!T zhAa7D;;dYSlAp3TM9E(grsOZ3s+`A<9-fsKqvVrw;aAmZO8&BiN`C%HwUS>@q!bhu z%LOUR56A^8O67v03i%9y-D$bNr#NdB?2KS_rChM)sa&uYc1EzSQ7-u12%Br#<$_|M z6s(7x5o{1E1sffef=#e9g3VH;V2g)RQ0^!$-0H0qWJ?RTJ@$wY5mYAvZNGBQ-5KH7yPb(^J#JQ`5$!rujo*WNMmEYMN(i znky8XQqycw(=1cdc&TX--*`=GL$Se7Tx%$fdS)oDG8Er76kmqISwnG|q4PRTl(WSwQQj+d;9_y*wp=nMv3 ztpQ%gpsOWoqD>LX08FYJ~u-%~BV9>2L=<=bEYtUsFbjb!?92BM-bm0cw zID^g~3L_0VAA`=*pmR0os+|lv8-vc$pc4S?0pKsZ1p{t~XH}EYqQQHP932b9pn9xG zG0s5|eZ+e%m|_R=J{ZY&%^{~<+#*Hiz3)i>foxPzY4r|L%w*yD;qH(Q>wkJLiao%N zvs~_?P$>Ft)I(nW4pXc^jy;*$fqgph&)4$z7&0kE#+)p2dslwh_IvpW+e6Leo%gyq zS4zjv0mzYyVVM>DNg0>G(#r_`2Pg!~ti1)b;LA}k-)%4?kVRb{nNNo-@YAVs`s=9+ z6{mgszNEMHSOcbZs|+x7tMu+x=`1ZZ1FJme0MV8TkA*`9{Udz+?Z?EHvagtlpHp}0 zo3RN(F3~&Pb^eKp;qHR#bzj6|!O~kkt16MDw;tYmk7fSzy+_kkL)zJdUDop0Ke69X)jL@Jh*0bRnRecq|a*U=9x zUH}+W@rl}yQhTkgq6RUW-{5G?TN8)KrNF6%y!2%Zuja3_nMgVGc}Mg)GWjrCom}4g zt^TXtiq7gUeOf=5R?<=QoExEemy??1$l{F4+0A^xYI-LPj?xu$6n(7NI7oXIe2(PK=_!6mP)h8@Cjix@;B31lkdyZyiE_UOJT_8*Le&6ef`8ZNd)$6zqcX1yi3khNsq7>KmI5k?jC+H(sT1T&P}0k?zZyEYbMP> zp{NLdq*$d7a9tnLN6OgOiW=?3imu$f?)_Vy+WWS|80-UEUfV}-t19^u^DbM)xFXBG z?)jb5ab+#99l$nOWA~R|D`elfu4uoPI%^L(8i+ny&J#YzjS^fuz%E}SP-nZtG7iLkm3dNc5s!6Vl2L!fMM|t?R=mIUm_<5HRxA^FS;zvvXGr5)1am@(#rCUdfQ?QrEEH$$P~8 zTad|r9Z+3OF-{75I&aM##p*|#R5X~MZw%QhMk1{RTWxgKGpmvGQ1TL8K2)FyY}ytm zEOoOKo#5C33D#voOnEdQB*xf)i=zTLOyMIeYc3{imY~Pl`Z1XXA1m6FX z=+6ZSc+OO>w3_9S^8CM#iTVeQfe!1@({SB0D?Ya^>Kmr^t==*FVBCJ<3~?v99tH%b zPI(lYo3mZR%Q>mZC7)@)`*r5&#VakfM>K=9+ce?Yqj!_mfR0bntDmH6b3aKVdo2*b z;Afvpo$bFx1PoNB%pO#SDpHOQiR|zgli_?rlkR-ul02wm^J%mG6}r+ZH8WL&YT39! zLdAsNN@(kz3Pn+q{jJ|S*5+IdavT^C`P~JvNL&9@Wl(jfy5UmX2Uou(C*wUdxlvbM zuZS2|Cgeb{;^mhD6)LQA-J~jq%FU!OOp-r_t68ASmlI8tdz}%9+mi6VnEvHUO zW5<;-$HCa+L*r`n6QE#qrRh|}@pkLmJ^k{H&yZcfwcFA}0Whp0b`WbcOSOsz#GBY# z8e6Ru*=vcJ8`VCPB30`rd{}VqWh!#&ZOuW|In_PYe(DT$hf=(xSPIeG>fQCedR|8b zSRUD@c0IlqFUN0$`#-LpEcLH$z`czA)qH}#^Q|-%^r^k}#_i3}xa;hM*gmzN-hc;h z2fq1YSV&B#=hJ!gRa&}-t|Ml1PiX^f{)0vtM;Au^;+geu=Y6W_%zOsqF~!Ut<^*${ zdCC}=4hD2%^CsOlE{|;E$=N`53ahvgZYQdqY$q&YPn52(7w}40zO6_S*T&mw+sYpr z2ewHj#J2IS*zWDl@ozafalni78i!_~D^RcvJ%pY|@1r$n-XxuLc_g^$Bb0QP^q1TSZ|GY+xxrlwL&&8K?l}^^ zB3K%G(+4CeZ^(znC95VtVY4zj_~rxoj&Vci!tdgbJp=%0`yoMPF0whYK-m;oPrS=w z**Y1p97tm1Br<*pHh-AOZFB;QNwAL8lE;?Zjk-xbBQ;nj3B(%L-&ceUD_j@nuZh$o zYQRE`2%mueu5H(RCY-g7Brw;GCTDB?v^=tq{74)i8@Fi>Y0vMngN%=uPiCh`V`tCK zc%?NrYI&61VXKw+ANXPXLNxa1UDn85p;dSt4%%>Y;`(w|Vh9mLOeK;DFyf+GJ@LfK z4LgaWLEhoHnKyTM>T5qP|akPK;y8^=8tXRM2@e< zaja&BCPf3fEYob%lxUnUMBh^HfB5dbl-9h~fEJC_{EOwz+Cf@{He5Sf3v53wEbUiE zUf!ZTpgpU-s|ByLl~gS?foh=BC`%@q0)v>-)CTG^y@08qw=?gl&z+RRI@|R({bN(- zdCT-;^bz_5J?Oeyc3jrc!U?-T=Uc#A2L1O=nHY1$hG0S1R4f?-OE6zrhb7UgV$*BB z3jSyYPq25`cWji+sfMu*r|P{_HuJ@j({*E2{F4nEZQ$o4`P*6+`;S65jQOKEkso9R z_O#5md@rd}wW*%cw;3;7?1%q@#^G6bw?+Cj`d#|G3(>p7JnSr&U)6)h`bPaX{VIDq zx-T8WjiW&{eacTMzB6Q;>+iIVE~CL!`U+|xdBy}V$7FMvY8i-RzRF6O)r?*?20JWE zz#8kAHpXFHmuQd3*g4`stbz?^GgqS-Y$3bl{g3ziKDt0FYO@NFUSuoTTJ|$5;v6|o z4vgkPIle4|8!Fpk9I7au-8nN{_)D|!a|@4gS6UC(JZoDV^uA5HIPeG8J!WyB6MvbD zXPcA zs$TU)Wr6p^!BrB&GjFvN=U?qvc7Qv}8SZ|c`n(w_Z**L94UIcCwM$E9bh+rtAQ9-v zOD*?6o7bo5dX_mIpTGkb^zlf~vc}^#PxU$e@vH^~(};P*49!ICZenbO|Iyc)!hZ;P zFPjdc8!06Zyg8dUxa8N;zEA^9S+P_Sd3-g(s+y4;Btb28k7UTA&TADrKi{pg)&Mun zP))EVkX}R2)S{T21x=bM>=VsmR<7-;9m8H>bpzSA>>TYP?V4S-ubxJ6nF$#`*S5=` zQtf5!Bdy0c+s|4N)!|6x+V(WDt+b9qVXJNY?G=jJPuRlIy)``*7GJvZ5i2{h1S*GG zMeU&eru3Be18N1+N}Xo-yo<((ebfy+PyJ|p=(!CMais#$3Q?zVxHF~`2+OChEf)wu zRm2E;oR2%4Io7~iXtP_!&n=HHZJzh1UiRxa~Aa^_SVz^F+Sz-+KS z*f1;vn~s6`SRPi4?ZG>n&tA5(TWppbC0SjR8^`vl_zeFFQv_IlYV#@?r@zp*}jguR-%H? zF>W?YA7&U6@(ScGk7Y8MNyJv>AY*xP2xL7cMs4^{4(bH?jRgI;_3R#PIeT5Zn>A>E zu;2+>s`a6EY9~{JIVBhMqnAzM54b#XxwYJ%Tz={I?(ujwzA}1f*^cQ&*e|+G;g?`+ zHS9lBWZ~`_ycrh|4ul6Wl2EgnS%i!BYPDA>{V4MCe^C*zhd7bo3|=N?oV=5mQ9jNt z(9UKdl77-Eb5aj}#SP$*9(noQm53|z{0(#@Jg=~S*m`5;m7dR9jvUrOGWL^&EMEW( zpR)NP(>$%67Ng$)Q4M$}=-NC^8?8;%sa=ewSKAnbi6 zdDN$kVP%h|U>v$o=q-1%X?dvkc5-m}E^2)ZHm{zMAG}W5W1t?>uZ-@J7khC9TxP?a zkK$mpz6w98uh3WN>-24Ua~fP@z34COiNO)#b3+!p{y~7l#07$m`@`X7;ve?T0rV|v zWSfIk=J8wnmVO@Ti(P@UJlAcWe=jT&3L$b2-AHUE?40A*vKKJ2o{9z89Wp++y0XXMsrerYrWAa?{81A)7);IYvGME5*aFG+ zbS#XCW59lFE53?=>3SbBPeOE8U2c2nJW@45HA|H?A@vk$vN8)xi&WcHM^xbAgs_ro z)mxQBV}3$u`{-T)?{j~C@MA|G&)Pe0`o9_EqrS@q4)(15^5)4~`I{dGm@!#7 zf?w!8SDUL%)<@HdQtedZq*q3LqqhIV-d5DpUX+X)@j_Uz*V;`nUZFU*=UvPJH~v2v z6ev81RUdD065cCt6P}XLDKn2smg>*J^g@wL%Zcl_>8$d z(~lYPVr5?aB*rvL!Aj;2#xzZ7<~6eg6|%gWDDS>h8QJDDf*sG!WC2lYH*9Hx-O%6J zlg4B3s1Lwy=)3$jpRLMP`ODgEDu?x;&F6}8Z!jmnHBQR;Z~>fph@`K~q}zt!rQBss znnufB%UWb3UO=v=sBCw_yf6pxf$QUaSDB5e89f%8fu&$12HoSmSUF}=-xG^;VKWME z#)*Zh?yCMOqE_-YYH345lz6%-Kg=dON5!w7{4W1y97xK%5&yC_nRHlxGj4Ncb`E$D zza#g(s#7J#UGcei5H6mIn`@TfzvC{|+*|G|mp9@?%1;XaJ`A{_L(yP#T9?zy)1WQW z5Wr;1z{L!;-HAmT3}^=mx=EyxW^%Y@m`o?B(O#7R0aYsTpt{H!BpE*vS!R&FU({4;YBirVN6SGstyJry z4S>ZIJwDDY9asm5%SGDl+9TSF+Dh$Z>JbI}sK<01^^FdtdNYTpLP}jnCo+}vYUUMX zq-GE7+I!i}I7p~X&fZvk{v}Vh-S~0*TJ-E%vyrR7@IV$vh%uNu;Y*AqW)RX8f+RfY zy+kz4n^E&h&{@#@UktN`XiivM=^M1WVQdiCUGGIks$<74p18Yyqklm&aOCH=EY9eG zZb&a^4&e7OGp=nJXX*N$sVoG~kR0f-UV*m4K$GA#d4oQ~bl3FP+(svAaLpCaCrQ6p zzfLb4{Wuvdhjb53JEgy+f362#)-JXe&<^xCZX`W{uJ;2&#b1YvcFm)U={@ubx*P@H z(c8=rX0L22b3+!uG|7OD$%V9Aj_s07!5%RUOb1V|>IVaHFb?N3-;woXN3%1|x<|9A z?6+&tU5Y=NB3UI!_~Ft+?0HxNQo}a00#4z;d2l1SFOpeYe;IFp0^FG$5&ndDM|>x) zHKzylTp&#ke9m*84y8S65q5&MR9QO!8p&r9W}I;(!)9+VA<d{+eRpQ`B6v-*gh zukhcUTKj2|>GL-o4@Ges*u8JmGa=d$Zn+ zt!;THTU*nj*!9NN)(n=f$Pcs!pC&!w&9{Bb7saJWdc{8Bfo--6yVvmlbb8BvWv#eg zoLa_Za}itu*GsmF+rfog0iHHwA95J!vN7!xYqFBt!yqvrcZKeUZot!f2_R{~Q@0I@ z#pJr2>+W;iXm{`^;;H*Nay!b9pUBH-SQuC(og7*0(@!%(GhQ=OV<7`7S*G^oil=?Q zV2HM->VpPgs3 zk;7(&bJO*#u?qyWt8}PsI3a=AT zGw=^re>dL8O$4{wX#H}~lNd-~#3Uk~aJsliJ?I2bZ`e%yj0_Sl37ULOg7M^AEkRmQ zGe{YAid;{ER&5UTTDya4B7cymWrUyYo2Nhnl66eOu4@!8PqM?z za^{q51g6_7n~5>ZCx-t4jr53A#?Bdm4`qYdX&=0k*}s;szrXJ?a?BpXi+@}>1Zzca zvCr8LEXP`NZd}YzE|}|(%;N^h_&jd~ST%cUI7}jNSGmW{3xev}z=FWm&sD8XwhIEE z*w(c^P=W`OWysX8HjpnxO=>CPHe=06Tu#Df7|*KTVh>PLric)GpN4u9&_LEYgd#yY$VPOZrf)hjyi2 zZ9!-12h#c4P1=20_fr!k;Q`a|u{X8PwC}Z-qYd)GDkWTDDz`M=Pfajp~P4(NsZ@wEs zi5Mb-C?r6Veg=J(xErT>^-2Gk7|_dQNEfO%c5J6!z#{xpBDCU z8y@tqubc1MIxsr$T8sP8e12%4TAmej{WUQ2->DQSt>Sj6nqQmw-&Cd@2o@{vkL%4r z79}?dU47dPFe<;!rpZN`9m&6zN1VMSaAYND||5-8EE8aP z4x@jCY6oE8H%x`aVwu=-Y%6vUJBNXV1cMzSx*a>Lwm2T4>j6gKV6+W%tX_Cudw%{^|9_rtrB7Mhtjf%nim zZ^TRR5HS3R#zdTf!)WXQS^G`XMcZ5Jt@YQcBekYAv0A%RdsJJYh4r?j1M2?1T&w-8 z9T{@xWN47|PWb?8PU)TU5Q^X92^@sKFZ(|{a^RlOr%NOjy%4XoqU(s^ZzZW_W3L$(CGf>nSGfJ2?Kme%OOpSJ37b<95{li)3N}Gbo4FyhK@aKV~a&mxO>(#T_G??XBE(VcgBDs*oCH+h`AMuI2gJ96j!_Ttj3 z+@7AAfsjFICc(INly;8xfhJMks)6C7*P5gH-?ZJeSulJQqX$m3sUm)}wmj(?Jcx3TvwS2yLc7is4|hevzkOWq}6rX-;ZxYV5jT#Lq-hO=-kN@UHaxiinNhOS@_%+G%ep>cMXhZ`DuK zl0O&7ewrr+xi#i?%bL$vH|qs7aG*VCQ%qqN zokow~Hql@ncYkoIxO&JI*E{q}nxz3!b;1FCe8OJJMAw|K|BXTT-F&A%*y8Fd-|R+I z4adL=D8$Q^zFN1WktX*KnEbz|+-(#(erzKa$#zSG+Bs-3yN=be&(>m(lTERW>+H|a zZ3nwO&=h2tDVxB};=rTSNJZo98R5m;9_|Ep9ln7%sa~K#=w&<^ZNMj^z>+9K*P@kp zIB_0dKs2DA+fn(2t|?PZ$x<<#of4H~<=J3DvP`nk`G?)Di;I7H@<^|9l6w+H@=0O} z9`uue5wh_zJDiXO;d#d3w7)kM5&0#u&~(9h*?sp2wGixD)^TIq0`&2^>~FGRignq% z?iin4IsE~V@3=9wfT#jJv@4(xu(8k9g$3ibuf?Xo<-OZ`c**e2V;H!C9mh+Eub7qU zwpOMZqpDb6I$1SWm8-gY?%}cBVO(!WM@&&x+xpr=A%%OZ&a3XLM6Fy-PoZ zHkuOJb%g4a$y*H*kPf5=8S6B5m`*fu&z|we#>%RcdncX~%{oxpsl4{;*S;DU?|>dO zv?RF;bx#wkV3o@0gx7_oaz{B&xz;6MaEgt zyLoL@t(EZJm(4w~C+%d>g@vL;Gy)bp8N}v28CK(eJ$f>`>=rCRJ6{oSzM|Uue1&sG zg_(ujd{E+HYd1*#h`lqhVb9kc*xBWKnla_x$?0Q1cd2Z=;uv~5JRviI%d(sUHxXsT z24@i&^%e6oyl*-)X~UO!=DW|**wxjpfm z^DgPkFICrh{H0!Bs;YSW1N_FLDC@!kIoq{&m~hrR9|`p4Slx#(5psgP&Q4Ar_p+f! z=xIzjpNO9){lZ#sjy<`790vEJMsTe+qSL^2i?g4uTX^)!`yM7d&{AcgJNv21Vsx*? zvZt+^UK-VhUK%I7G!Fmp`M?m}_yZy2baMU@?D=si@vNZGM7KklEOD(Yp% zMRiSLwF22Z&h6Rq=|`WRoE^~FGrBY_CH)KB_@GrHKyB4skt_ehpRZLN^S56Qdig(6 zIx9UlRIA3U@8u7-L(~NKRf?t?@AmO;e=sT>29XLuM}D#AifwQ!_C{@qcC&sZ{apJ& zyBW8pT-~S%Z8CFg{*w2}C4QogrMod7leRcqZR?;|J|#3>6gB4z35~)U%w!ZUVGpr- z>vjYPX!BW-huu((X3$g=s@qr0;8$iE| z^O=1!JvUq+$E@#{(U{qOGsipgW3DL#;M#4)7Cv~kL7R%J@$0zaFZ|@B(9}ElOWghM ziGZlHA)H2gcn(cn01M{Kpl-=Zo9uTca-%LO5$TpBe{Nht{7&eIGU6%$9utkkH=+wE zKY2}!o%papFpRvrOfYdlq%w7ZE0vS8Vuu2xHC9~opRnieu?QGX9rNEsQj0%q*tz%p z#`_sy7geABVZ+V62llsZynm=a{&k|%m0yOq!tJLcK2HdEWN!s&8qZ zYj2bqH?fyHwB7btO6?A){3mA$t`FIFSa|KXBVb?6MgPfF(+*E&7VYz^o_hssT5u+v zy}a+?$1C?U_A~YA3ifi2Yrv z;Y=x$!(xST(?eHt)K3)_+~}~VTQLkJ_fov=&dkh^DDtu!?N{6O7`kNd$Ps+cVX#vV zUDM=MZuc|NvHJ9fuDYG_CB84*_Kd9SD!5xy%j^BV*<9iz@sean!X!nkqpQk9SHYws zl8ch}dTB?&0C`+mSgiSFh5er|l%hfOSG_4uIZkFO1psQ<2H9V-lQQRp>tLtK!;5NV zV#f7J&CKipLuceH22Mi){~8iIZ?|*Yw8PFs!DHTvMf_mjGwJ2w^W#rMz&V&g)I(ug z{K7dGBmPYO&LER|^B%^T@(1mhr7BFN7^KQAe-S!OHBVK(F8p_uxlUCn=_ok4Z22!! z3ruAx191$Wg#S#~;{X2?%P4!XnlV4 z#)}2{J~OqOWA*uUQ~P&dxo_Uz?^gf-pP`w zd-Ww@@|z{Y3&ic&d75I))ZL<{eS0*ArrunnYrd*36P7NSUCL80o}lo6IUELjh?Vg` z8+fug?C4*1YK37#+Xho*isPYxQe^W=;IjM1{PL^b2cmX=Bw2krU2sc6 z@1}e1Ct(dHSOc!MSG2BeuZX~G6>i_sdp(zI+AuH{l}2HE~ZN9 z3}@{PQ#IzSig3g%Z0uuC@TypX^k1Nh+(v#rM3zl>f3&0n?%HG-LaHd=e`2ba3hs{j z_F-#mXC!UBW3GUTT-OC;1y=t(2!|ek}vD<0~wrqWq?=y(o49`oawT$?(`wjjL?t!y_ zxgGFC`%e3h{thjn&KmWv%yD`OwQ^}xI#a-uO~81!4?ZiasB$tnF#y&qzUq-y?7aIt zXkvaaCTsbt1Tu*Qi`hd{hk?g^X4&j#&#-qI1xrLs!?C3TBkKs32)l9!|8Ix+KC^6E zY-if$`+Syw&9Sp=ByL>yIkxVe*M8f7Y{av=m=*9p9~d@rC7k*c+~EoLDRU(94(dOiM|$vh{b0YQ&i|FYD#N%gXLW? z9uy$?J4)<*I&!#wibUFd$lJ9SydNx@JZ!?tz^-$oF4``M6XI6}9+T(BCJpxo)k1k)yAv%OUT@z8{bYRS`NBx1`i^tu#mb>?xZ|50!yeervb1SpM}-iQnPnS_A60PaD+g{y?&K&vKz zdp!z*+aL%kDnSt3B%-Le!Vp*0FvM96;Hp-Q+ge9(YsE%UaiO6IxOx9`i7!>Y^;_+i zYRdojJ{<0SFK?W4&mHI9dq&W;&<1IvJ)HBeil1th`8m7U9O(&O6wFUBwodd)sTUa6 z(+v%|56W{Es-A8OgcaI9J967B_mCl9*$`FCiOH%YS%spg3Y}9edgOWN`@6j_!04v7 zS0h(-H+6eWFU>)DmhOuBk`5hFztGufUZ@Z1B>FA7(fXf#G@~`KOKg+lSLL{NU^!=H zXs{i^b+d8JelXTW3l7^?Ivd;5Vd@HEl&g~L}Can}^5^F4;Y@?pAJ_T@HmPo3V$ zPcSX;jaV`_K0wo=W=)C2JJa>yMzJL3eyL~B_1?h+Eb(_W`h+Aq2j?E`7`)C+(ldgJs{w9^MfVhg7NKsD-p-NU z4dvb=%x2G>fLh3RI+YK6_0zEanXVOPE-KhxDi$-{ST4g^Xj0C=Fc-UIzu*OX%x0Mv zWZU~rEIT);;mou0XOU5>W_hoYc&|cjEETotS}NEFi^g8{UfCr7AvFkV(eQipZry{- z^5!&g?L2neW$%TjzVi!+J$}hQAnrF8rf(pl-J!+JT*QY)tSm}lt|?|x%~?6#mR*>| zjoe$ToZa<1JjM9lPU)JkvR|f)#5woEyod`cd*;nOva+YQjkrRe{$;kqW$(8R4I~B& z42pf%V1Y3uAj+cdGO)l{I{JjCUwQ3(d*L$MWeS@;V1RMcgCAgYYTF`cP9mB>`LYa zrtV4}zm37zos^g{X`?22#g?CjA4q!9(0NxvLuVEiUgafNai0;_%X?%C50GJ*&fS-J z`7u4ZF?y4*P&xAak#@`Tlw>$qpXxvGKc8J#~Zbfdok(oap z8FO*Z(JAR;bxYGEKORZG7#zaA$+Zc0wANSjLbi>7AopSHSx}j_L65MXz zTPL2OJtDp&&d{P4&Plh@*sF^9WJA)4l#s|qKUnWC4XS;+01VtTY5lchwf(8ZS~>Ns-C{vP zdE1?hPin89;;d)tzg_j3OOk>WitnguA}j`G(z8 zB3$pOI4~+%pQ+!Yf8q9H?maPHB3#nrn&7q`;dT8jJ^Fj??2gs`W{42({4&>tN%k&_ z^1<5A=nVB6^;F!JECG)>c~a26MY1rWsq7a}L3t#dAiE;XO^}rnpn}qV}_X<}^t zZXY4G?k(gE6HXM$>jy3os)W1tM?`ep7g4eGm6!E+IrBo~L#SxcuXfKLYALc4A!m`N zXrL%W)LObwG(wt{jK+oUU6vSoRCHad-*rv!c)2{b!cwXEwkZOu^(W%`d)3;^ygIM0 zZ>Dd~=?rI5enlkB=;^_;=0H^74NuS{LuBiJAnpOtE4wq(z2!H+Qm zW&KFSfuKrQyxxJa>5?xx9X`oz7Y3sY{(HhOrlh z-f_AaI&;EB(o0_Yst3juT8^miObTG$x>cDS2r)v%_)*#8?Rw;uJJ?D|~zTI;qgWsD8t)Mm095^d^o$~zHA(h$#7UytSa@oca>X*>AM7@kv5 z;WT2AdBb3)ieP>d@)J=c))BuGbxAZfOXt08Zb6`$M=BbID$G)wt^iSCOH-%b%eE})AC?dZqQWR?Z(b{SsXXfp>-D@;hUMnyZ7nomI|i*nljmmz%+G2wKP#o~e6TMF zSa3p-KgYWK;7c%r?a{jjxlpCxNSK{>tU9LnakgLn^_=5J=Uv}*eiW=>)*Ru%WxITv zFwTZ3mbNEeInL=fm;+lgL$^`>_7VwptK;}KMn8t!CV`3&aO$A zR-sKgfoe5-kZjj1Tl;{*-mwG(Y9-MMoV#6V+(;+VdFXs~hy)RPoPKMxUGpyD=ekj1 zbVnB_7VGQj`-;zsJBWW57e(sh^egnU!)c%XjQ%%$(IX3IMA=Xcn^NsxfiBwj z-U}1@QD`I;PQ_Bos14MQ)Grh`222zo;;4ve;qoZxiBDSs^&kclp-c<^say-ccp_WC zw(#3Pu!6@NWjyg&8dT_ut}&G|J)G19jO$)yn6((b_I;=R#(8LD7n#(ojC>7Gf$>QV*u;!Aq`i`trhRo#k1-bfuSMT84}pga5kAtW|DjQ-VVoV{F8OuHehFnHI={DZPRIV z=XFZXd#f48oqD6|O_8@vuzrd@UjMy*n;x$cq6X9+p_sZMY)w(Z`P3*%aa`C_lr0=D z`iVMAN&DMa)#QPpAtG#urbK&U4w}@5z)r;GFXhc|hwc&2!Nv|( zki3x|&P4-JFHfm(l5h^x=#9cvqOBrSOQa?{iY}7PM9<0DqG2M%0a7g8Oa@7JiB5`i zZ*A=?-SOVp3lU%3P(05`j3PqSGu8X$=Vsc2ULzP9-jSbFUst2Y>bGh_gEfk}YY;gO z^y|qb*_{H8%ngi4)#PZvB9NV=2(ekN2rkvQ022BhoMjig7^)4+;au|Un& zOjbK-wn;To-CIj5&RDQBd@ePYHIQ}YAD;ZJtiMb;!R&}#c3~-nRrGH)fI&(#?y|f8U9mczJhn@)b0@`Gub@qGlIs z#qQU&fs^|ePhJ&WeDUPhq+D01okljiJ?*K;QA*X_=z)!40LXbnb}gdfI; z&kLK^`qtU4)CQJt3Tt~_*|Kml(?2)GEvaW$=V%_KvDQi_6w1Qv%J3+Lw#nvbQ?whk zd$oA~c{Rmm=+02gX7+u%^>=Nj>#0Mhr!;!LE84E~gnV52!x?%Sb06|;O|zm&*0fD?z5WQLhbdv^zK9}VT}HmayAK8Lnri8YN#ITT~twCy@Q%* zCRS{9^*MA44PV#EH&PY1x`p3PHy6JnZm5%AEF}=*uH0QL4Sy^_!IO)9o`N?p+&0IP z*(B;Dytbi}{}9>F#4OoPB29(_!bijy*+ZGHtcDz0j=oxRz~&S-zWK&rd^1mYR-@DW zzVG~0yiVWbjI-Nu@S67$D+t37Mb57%kBQNu^Z_3XA!_3cK%!Xoyd2yPN(6DEK;X>?B) zr*^6GoT*(d<{pdgcKY(=8Pl=)XrDI6?EN&@ucV!Fto=0qHj1l{S367A_`ICaf+@N4 zaEVAIk|_<=-e`~VlybM`iLzkG@45LU^@{IvBn_k`?eA}W=cJ_F{mizlN_V=U4)=hf z(iGpoGM!7k;)Typ-Df4Pizo|^dd0h+Eq~tlnfv}%9X!NdOtiZf30C0!v|V*c>U0mu z(~H{E>KpwXW)$n#dY-Z#>xV9-XSjmzecj`|{D&1-4N~IK1mWRCqd%{|qc7EiUrZ$M zZo9{(zACIEM^$rryUykO(`LHEfx`9e!e0iwn3&+j3}3}aOzhNHzKYdRgytmaT=v+6 zHQ8-j;wlqacu4lxtZp*h@sMq5t2*i#HM7~f1+}tR?bJQh*cXW}A#ov8-F~wgMoc7b z^q-kP{FqME);Do;UDa=mcRf%b$f;OoEO#!#PT8^t7qUApc;J?YeXAIR7xbMlNQkAE zRlV|af=KDI`OY!CVk9Roi>FSFP zd0k3!ldgc1k-l9A{o;j257kkxMK#1iv5R=c_6J>g!Qv_6o7-ls7XJXcoQHki-V@z3 zXmqJt^7Ut3!a*GHJvKVVgugaV(SDb27&x zQB-tS^t9lZ=-vajhW$#{L^T&N!x?>+F3XST**af7rkOON_8c@a@={VAb z^T$Sx?zQl!Xx5d+vtn5&UxZ3TuyrhbBmGsHo-r?sC0kZYc5_?I(^PJ8I_q%Erd~;} zGdQQYwSP=K6<71%LswW5jnNPe<}W21*AKoGg9X|9mSy6N8&@S4h`&RYeaYgO6#L}) zDc6ElrG!57PDr_Po^!gv;o0`bl3JXow}9w%QprHd6&=(oR)mXFoi<3-T0G5}kn7iN zLay_K+=f$g&1PQ0)0}yiocb->d!zqqkGuN@=M;-yXS_*^fwj=AOJlOn#HKGlaMf>{ zd4ahgZEab@?9d+?XgqdAt%}ZFrB%RM=+LZMb%$oL`y`CLoZIBk&fK>)`>*-HdNjYs zAei24&*kJ?=xo)y=EdBT=l!SXKJdd57`YjL;kggTuDmlwMceO5Is~ z_ng~tG-k88E>68dy?NWiY^;#VEXtM_Y=~O^LY?cd{pj{%Hs|dbn@>?^3%l)eJAV1p zaGmbvb(o$F%?cQr<=1a$mV4;V1rfWg!xor%c?`t94b+;$nv1(?Dcl1%odemPA@d!` ziI+J?+}Y>a|9SbN3DqPsqA$no3v?2{ke3w`$N zp1r+q5ywvMEVobO)-LmuD|YuWvG<>Bn&`!+5h9r~^g%{WsP+0?h7X(g5FBc%Ii|hCH75fipau_W7TbAhA zOUA;wsA}wh(*|h^VR6ewt`@bI-xdvx=;}Q@aB@f>%rd70CQh0D!-bsq2=IBHh@wNv z***8n^^aYhGS^QtIUSk|n(G&LbZ_v@WL=2u?2tgSNE95@B9g)bR-RV-Awteu0muxr8|_Hf1Oq}q$5Yo%%_IxM{? zy(cwDl-K|VeJ9&gBv5QGaZiep&6ll`p(I!Td3!_r<9?A9hx^Cfhsjpf3ic%Tr0dBY zlIul)+~o`>oQ!)bJd!Q843~$=kwTs%zb414c~jMRHIFmbTEVUrYwkb^H)UST?$pSs z;Y`1}R`Va<8m?em3yAC8+-1iU#W2yJlfqr-a7K$=aYtQteJ^^g)QHZDP!rXrqWskD zB@c7(Ds+V+dZ2of+Lt`g-etG97PKiRYtM>TYFm;la-{Z_wvRTKts6nY@?L+d*FXAp z-`G#u8x(tbMeO%H>^`d?>++@Ey-?g8b*cIdY)bBbfW542L<_xP&0FKA8MD9Py%%sg%5QlwMBNUK2M5Y!p4!+v@G|AHeE&DqMrK6 z_QKY(u(F78;d`g97SE#*Mb~K?dF8 z+M*UBY|Xp8IST0!C*3F7EZrbFD`krFM2ci-Ety=}QC8ump-ZjuIoAhzN_*QkxAz*< zJ&ssGY$i_T#h)ewtw^wSYPcwwi@o+NAW?t2!BHW?|3cevW}S#;%tq0yBMGf$F~6NUHvQG`#M<_|reeiP;o}+-N#5kQ+tzovRUVM? z&iBGYbGt+eIfN@<+ls3290uD~nhMWh77y36#w)BR<+JRTm)Gu}dZ}pr-Svvm0_)ea z`2nr&rm`NVahql{o~0J0BGJy%u-f=muG=F`E!;Uj$2hqX&4nlhcFUPvL364Wn=e6` zlglzT4fNWjU}k1Ak|Ou-%Jj<2+#Y#u*WCS)CA(`MNtmD0@aVi9Twc9H^L8{o%b1_j z>u8IU2|Hd4_~n;1;_!+ImKJYGg(UQt%|?A6F$Tmf8G)Qdk~}UaJ!7kGATKTy$LYJq4B;6UmlTB3X;tMNXpnQZq=&TXGEPAkC!q zQ0Z%ly1fVw@M?Ef_KLD3STh}#8eE(7^sP1Ja%`>~HrZgU^f$6A@(KzOFPiQWyu__j z@b*ZrV1&(X&f;BAacxD3cf+~pbzm*hk?ctJB}b6hodWu8o>xeqTu;uE-ypZhJ4lhW zG+bURA1<%0#7kWJ);?6s=Pt$kU@>+azr ze0f8;lUyS2q)}*)zw&es^Ajy}cjf(bx$N=Z z_e|xU1s7w%pUA0sarb_W57i$IyOlF^g?NXachA}FYCc}wKUZ-1GT>=HiL@`)E=;ja{p^RuLY_50L_t7&Q%zVb^r|B2zv92CRH1MMS-b1GQ zdgiM~Nj%EAJ_YX4-Z&@P#A7RBG=++%RyWI_c2Os(>(pZkm3AFyZ{BT~tHFb|FM)!I zLBesui^LJ}bD}_e2h`0;v9O*nSL{RX7e|Bg120avLKxOTv{QIOcun|7X#Ym&BejQd zq}w;iSnuJ@G|?Kbimvf7tA+$Gz#S0D#{TA4F(If}PzTe7r=e-y<)hK2z)J-Q>>XAo*f4ghY+xD!IA*sNCRcXSg2mr1hn3q+MZ+7aN!t>OEKb zFH4v11Vz<{k<)d4s6X{mY9Y&YY@L!qdB73`3YJZg#miV*o+@nDmnQ9zp;NLOGVK53 zcR5QrQ4aIYM7cseOTHeQ*6fgnsteV~UoFtoPzseU$}-YV2_4`xJzv$|i@zw4T7kY|sm3Qq=unI^gcoj?=4EmATK?m4if46Y8yOkYN{*4G!- z(RUR_>idH)ap62+5wS&Bp;V?%H)Hrb(7)1KQg)OxHBU5MD-2IFkn)h1|HP9W=kA9~q->*ze!bwn0%gg}>w0s>cvfkH2Gs&EX6Mhh2_ zhrmkqJMtpgg?vsTSfm!!72VW#77Y*uh$2MxOGL{>n?&~7d-GOa5j_ySc_nJ(Td{68 zmQfeWYF)%kb7^ppI7*D>i&u%aiVuh%tZp3eVp+=w^jM4yW*ta3vYE7lG>t?F^5f)A zc{X`XUPF4HTqj5N%7yZ7O6*NCSlUVyFGb%=@jB?Q(mT>pkULyY_^oOZz;q0Roj}$F z#V?&EGW(8oo|ZUaw#_0rp2EX~w5E#~tf(bmtT5}qvN!Po;c?!Lv0lnm&?slI92DVE zmKuX+&}l_xI_wzK;w5OMw6i`C$a0!jUK=8Stv^@-dMTimVlkWV7f_PGdY#B^o5o!0x%*XFLibDME7ITDiAtyA@!e@2vuEzp9ub^C_Uv?SApfb;Atb4}Ek&n) zE(d?QLWxAMErl|ecQlghVW0*Uig3Aqg4tX2W<6FiLEr4O3#k2_)QbT*9rRP+B=C;s{qQXp$3FUXu|HlxK9NL_`S%OO;sVV9MYg1~)De zuBxueN7PvbD|!>w3@l=>2N#e3eH4{ZtFyxZ*`DK?u!@CPRnawc>iE_&eUn><4p8gH z?m3nfgbJGJpXr;ur3k{{3;;n+PCb5)=t+h*1lP% zz1jvV7`ZnjY+&2<)VaI9w@&TtgkEYbbo7?t2=Nr1LMd(%nd04M@`1oC-4PwKm3U{A z-teD$_3{nBmzPj+u#?*jKm9XyR3Eoi(S5Vgfk29>Sbhc(DI^v!wEdyxb2M%qin@!>pUm7 zU2%G9fOxJfLJSRN-gcQ{_4??f-D0dIT_{F+c{?RjDiq#SC6EmDOcFIyUn6tK$Eu0y ztExn`r4-po?+8nUgQfLEtwmi#gGGW-qDWDkXhm~XxH49`Oj*8R@dMBi>Z&qBcy$7{ z@0K!;Tc{eTL@MN=@>M1Lwm)nArK3mUR4Y_yv+5_+S(Qe8Uj41Ql}@Tg19W}W5xR}) z*=l#)K3!8C`b~F3jcre?HBB__G(9zvA)3jWSsJXzx}tgNa_J$g5OQWX^Tb_gnY8XV zLTtKX{_}af`il&1c_zxHXcJ|dwLTns^P&-K7v>q+Z!*N1!aN}<4q+azHQ9aIfU^y! zvB;B%oa6%g$EF9#B}~v?G{z1Y6o#xS|TlkJqw!aY)N%@x*ZfyJa)j z#+}lEoMhpe>c)3Nqa)J9GvMTm+YcRTx?Sk>ZW|Xbfo!f=2>tOpSOd|5?Qr^mEVkru z&ZX>MG;_LV-hObf;YB~n7j#-u`q)ZXl55kt*F0hA`^LMu*8L=U)qRZ@%Wv>eOTQ59 zInhEbTB9u!?F%>{IW+p14|aTwu;=S8U=D1jUvS0JzqJhgpd)1~b&;|X-8o%H*-x_6 zW-^_ug}#%%-xK1>U|$t>fIx=oXFiC?Uy*-!X~E(s)x%yWBljSgOXicD$eORa*IgpS zrVl*6w4u~V3d+Lzs5M?MqUgP5lqL;cmlHm1+1^;giU`7+Y&GOUdA!VCwN2Jdg;vSN zs!C;AnUg9@RUaHWBJAj)KkO?{lFyN+$Tv<+Tz^+sCgio@buD#mLQ!G~1p5FBT`z&; zi-`^e`qye`L*pm}XxHQeo<8#}xQFi`snj#JJ1XSc^;FC8DA%fOvdtlV8yEhixtu@- zpV~Q7aP)dM*Qb3p$C~2xN7)>Om}Ta;)+O1-xd}?L&2e=Ror06$O*%WSu|_QNPeWd3;E38Jpt^Y=B1O5hVz-NMwW$3`s$+(EIktm?pOgY41T!iZ!oB0uu?hBEtVgt2W^n>W2Xgiq-mMaeBN|~FqwRqai z%>%>%;x`fEZF4GCvprcHNs@TI7&>D2fRr0z^h8XF+sd1e?Z_khnj~D$YXP!P;Q%B2Ds z_%a^Ls0e@iw%fyE3&cd6CR9aZf$&ChtPWTa-iYEs9K#yO3Q+`vEwF~5SW;V56V-x% zNWT}ibADD-x3sAJ`$3Ni6DTBvNUaR7j|4qp!wu8$4g9>Kw*&6HU_g8x2=Q|it&e<* z4q8wUM|KQCrw}DUC91cmUgYzNxJNkbk@T*<90k_FVUG@U6EeW!WR4^FeMFQ!1UdTi zNO2lNq&Ns#NwE=k4VugHrSv#5t2tUtS+wPihQ|p#7>F?(;UBAqBl2jQNA)ENN*Pk# zOJ)%7x3}Itz5Vk&oM#f5#2(@larZfd1Z^U4EMz=l6qIJw0jd4PgJ%&CwoHJ$+p@sf z=K_6^lki@dbE3t@S#4@jQN&o`bck())(NwOM}(Jz*fkJe)KG++L=|rAMA4!JB3v!d zK~b(KUsNKZCwXrMh~GjyC*S@9`;^<;rXmlBpDUwKAPR=SyuOc7&uPwK)0`vFxYsCX zhO-Q!%ue1i%Qd?*zGQGV&S~8F|hHd5c+nU)wVaO1(!h&>$*!oG#eD z-?%VpTrj+ufjl4@->3=p(}Tmn`QfCybgr`5Vdwxj2L2@3^;-OcdNFYGOE=k?`|JH*~yw`hTbyG5DtGAH2x)OgwAlBTp@z-=$A#;xNavH zS9l%V#LROq%-W%Lap)S?#d%u09~jrT9bHk!TJ`m=?NNC9`W;aC2;?S!K+AptH$Urg zKS8fiQ0QY(p#=)7GjQDWT5f2mn&E~P#tY`f3u3p#3u590)8hrv@q!3A35yqm#tTB? z1wnA)8!zyT7r4a>8b68`*u)DM@q*ux+g5bvyx{VA!B6J}*;~#F($5Q$&I{(B7fgba z!1IFs=LO>Pf>w{t3u>PiaL)@MVkJZoWZ;$wF`fRrWj<#hW@!-{anKYlGJ95Jfh_Nr zY`0`sAg2bXZVluPvBW0ae#OnBtO$F;mAF?1Ey@!WZelPR?2YcnfVi(#5G9xmZQ(f! zS(O$IUdLbrnX&UITd3m{Wk(<{!jBk3fW9ZOmQWLiiF^oxbpni;?w3GkKtXR{3&GdS z#DIc1vbajLW^ejN=nRpv_|J>19~aqxmJ$M^C*;t_R$x2M#!O~&_c^DuXp^(hU3i6I z`Fj!TSrHFxIckg$K#%ggh%KzURCrHVXv;@`giEVT0}h-vQ_o-scT9m0xt-DMGkNb+ zDcTddH$BQ8Jj)di<`z*DHM0lt;8{iR+{r}V8sc%$S!DSH3XEXVk(;4u;Un@AG-UlV z2pCEgpEO5f%1Q;qZ*N;Xp_=VnVYT9pq=l+Qg!KuBj*PZeGk2VN^X$dLV&_pqScrmt zt2U0trat`!xj!y~K)ZFe+%H-DxQI80w@k^d3p*5O!mBrE&8x>n5X!STpguvpl))%} zTm&%?>mS^R)|`Qm!}_AR&^f{D0#M;i*#xNP4fmjx-^uHv^^g}oE-Gy_1$CZ*GC_^e zujk{UruRz+|aeSwsWub4cqScYe zw!t3s^M$MR(QQ%?q%U&C5%bvLZ&A0Xs}KTKUnHJ_@|MUMjF%8rTL^(vf7yeMEo3n2 zPJy4lhZu8H&}7|x2IGKIP}}-6Vs3d@d{Zgt@VKbU{gRrDsRCO=IhyK!sOnJ3|1@0EXKlMJTN?pAH$#TKMG7vBEIp(Q9>h)zrqi8@I3x555O?Ox*+I6V9+*< zmk{m=&Y+8_IGo`>#%Q$RQ~|+vE1t$w;7=;vo#Q;b7)kxTdv}w1`*ip3-F=X+;oget z_;SDA1NwS;_;!Ey%=?skz%@)2J}`xUeSD06fBmH4j@gjJ0?YxJ3lIk|4`4n3E`fM} zg#e2H76U8+SPGy7NB~F#NCHR(SO$;+upD3oz)FBs0ILDM2Ur8J7GNEK3Lq6A4ImvL z17JNsCcp-OjR2bfHUn${*b49iz&3#G0BV3NfdA{K{e*|zTj}=n9uke*L>Vi z@iToOt}-MaZSNoJ2k>Z$@vpcAL;#!ucx;K#4gBeMhXBaJ zU$O7rzX!e>KeLo)C<)vH;!?p!DLhvX5UB?*JZ`vT{QtNY8~HL>$RG6v$1c4Q3BPoM zFOEV}&^Q!^#=N@|_f!=GygP^2Rh*B4E_5e!tIgrOA%KCRKT>>qGXOxL;y0UjdCU#m z8^8a~dhdRldFl;vgnV59d>=lbU@KDkUHG~`fHMHhI#CE*u!RDg4tYr6+H|%p2SW(c zk&R(Gn|>C4SG0h8Fi!YA^mQmY<8@5O*Q6;Pkij%XK|#|r#q*}Kqs%dcFyna`{#`V! zg-V2JqM#1rdW`wBmVd*7vcM3+T+7FB!-D3=-{lj2FMZJO!u+htx<|kFV>sgL^gZu? z8|McBGzB2wrnOKWBcUtHgcSau4yQ4Pa?_afv(TFv-&47M()Zx&pGzCYHPcO#(A1Q(NOrEf#}6RgeRo<`FNg~J`T5Te*)p-E`Zl8 zNc%wwe~|CT4g~yWnYjS;GvfJvIba%T+W(9{aIf*8?|Z+DOoczV{S1K0gxillq!=$- zjt^@n*M~*p{WbZ6+m9FEh1*Xcq?kX0xL&Miz;6&Y5WvfbCy?^V?Fa5P9yFb%${*Wz z{Apn1PaWV-9V6Xen?JmF{Bbn$hX?$r1H5qr;2H6(uKbCA$Dc$af0h7$mKf>&+WY}4 zhKlyH*2te2;Lj4^&02sMBc9cjKi8mB!~NSWNDcj49>@oI#&P#+^XDueh5NTcNDckl zS&$F%KsG1@IBUf7bNBAIzU9XdrPgFT^q|oT7!yX=bze)68hRzh?W10lY#10X%Pw zhZMJ;7=EbPTEH)c9}f^}#1qQA+R1O2KX`tM+YdcIUC2y>_G23JQ`~;={1mqzdVb1d zCqes3gSL|mP`&4;>wtDVKWzm-&rcoMVxZnM=BEn*KRiFhb%&mxW-|M+7Xp5nOc#La zJwL_m2hV?S`=RGQ3z>CTmTc3Q|KRq6=Rdgp(DNT2o5ykl{CI3ffWJ5Y`M1b#^MOBD zezO6f<+p`QHk)9ZhWus;cwzYs^M{t-EZJqiA2!>PZ4FSp<+n+&_Kn9MEFaM0Pn3BY zb2i^J#vd#n;PD5`2lV(8!%u=W>@;Q!KO5lhjX(bu`3>_2_iva#bpIA*UWYZCZyNm@ z<`3@QFn{R&Er!oytp)sI_>KU7uYdbD@dwX;Fn{RvgDCSnXg{Vg|H1sh^B>F~dj1o` zKMU+a)AC!CxtJZtHx2nM7VyII8|Du!zs2%h*lPj5 zSbjeM7vnldb)5g;{td5>;`T$Yk4Bj94f>e@z|SdK#J;0@-_OaKFarh%k8jc+Ra znE-fU{>+Eez@PbiSWo0%K#~?qYM6dD)^IYxs3T3@XNJS11zi7d*PTr*MV-#A04Fd2mHwc{+PyE z1Lltwkiz_V1SxJmxt3bsPag2*5rDSZ^QR^>cFdppkQ(??hjr1?G}h`cfB1kG=1((7 z4gBG=9s_>4mdyb8e@j;ZUS&K?S$@OqhXiCXfBYad@W%)EV;Z`Qm_OYCFU+3+NDchy z4*c-}-UI-2ulD>|_>MmbM*b`T{(PCWAY&zl%=`72Uf;p|QM}{N_eTCGfImxsH{Sy& z{uX~gmM|XgfA@3s&2fFk$Di48(C>wB8FeV|{qJ9=^Y72SaGuuHt_}1%!V4}zDuNV0 zU*EDdCl`Qz_G`*-*yf=D;AIE+b%GSPA3MuV9Ll0K$Ih|=Kqn)f@UyWTFpV_+FojaQ zpZ{DQ;CH=$(C@<6>3Vbq@WXiGc247Y2Jm|f<#+~g#CiHTxb35OHivh722_G7^B zjO8(aOe3Dvl|Pth%pa`3VBilM_+uJ-_Lx5<@A_d|BY#SuA7%q@YynEDbw7;T&$sXR z<7MQJ82Dovds>)3BESo`p8-bxh@kz5fj0vHMAf?e;Bm6>9e+yR@u$9J5%8zTNcY$5 z-|#qj3-H3@BzD6Ae~_oxltmHS&hi!jWyJHp^>6eTgU8Iz9b-OqoWywIdPL)S2Jm|f z<#+~g#CaNr|AuGfaq|6d)6ZA+IElx4Y&UBT_@9E*1rVGLAAtm}O=q}pFr0!shUp9% z5BS|U-s66kzK+Yd1)M`sRM_}_O`7CTc|!ovjet}g(0_+4lAG1xZscJI;mFM})Zx;& z!|z7iKZhph;*AIWuBzq}{oaq^h_BQ4y#H;Sr{&_+z~d=!Ar(>|AQ02I7I?arO&Zrb zzGiz*0KEDFQd=PnffN$R_hqgHo9zThah|5}{c^xG(${hQt6b;)P5gNR#C!++9{4zK*L5zUqK2aLB5EQ$$rF0Wfw43 z1EfGc8Lp+U%i#PKTz>_>moe~tG(W2&pZh{#(0r!b;Q$Mg`MG@lCwSKe_#^@Ra623Z zDcuf-S@Z?`LYNXralSh9=M5Ar<_{D0zi9qYJd#QA{-~Fq(hmPA{uINDF@I_Rel&k- znD+(zLYT$8zD%6|6#mfn{1bTgf_hX2FUEae{ z3kJ(dDFE?Z)vApZjJe#Op!bR(Q^gzFjbJHC&`@4wOTZ8tML; zeLx1_h3nWsNa;G3!A$}Drn3)1iu2W(KkK1U;657bWYc~0MqU~xj&B-$G}g(+eKghs zq5J4qeliDaPB^jr?EuxgkH-AD{*FI7NO2#%k(USj$uo{kU$gyS{%GIv=MkjPlu#^R z3;f9g-aG=(8u5gmtKAriUFtpglm0ClecBk>9G-uF-{{{mj~76_Yy*8}ZAc>_#r4vb z7tXciiHvJaU$b6v057~AW)G<=q_|#kc&>n79j-m3INuDe{gv#{{9no+EPLC5pjrwQ zswtl50UZmO4vb=!gK^IBHTm-t@T!UDO~4otq?kWXSv48vYzM|umI$Dx5zp$_Z(yB1 zJpWDw!rxy9+sHJH`F8@~cL(s>3TgQ}{%mEIGZFy5t;{EI)`~NXNz}OENUK_=JG4UK0$N}GE)4?Amh7j;ehT(trnTy{` zAO93h^n2l3#yJ9zW?W~(*Xet38PoeYI8X2Wjf8T*{u3fV=A->51e&EW!@#PJeim*q zz6WkIeha^cz6W2Y-;Z(l6yL1x^Bo>Bz6)Qcb%*ybMdhqk#7<;4JhmH=2t`%lspfJJ-kSHKba>%a2DPmdFv_r{OEGge_= zC774DAjQuIn&rV*Wg7NFn3vdB3Fam3t0a_n7RIVP7^eyWs<*F_7QkHWt7IC;ShTN_ zXs(#unqwMzojCRb_El05mkv_+gM2@T{~%^Naa;iYp07D*zQ%*D=U9gMTzLrBXMFrq z_776%3$ZV=$xuIOUuJ=3Z1yCcY3N0V0bbab8E!wcFS9US8T5s0b{NkZ;P3e|`?v7t zA+#I3zNLqh)-NgKlFUM`X{>Mk26$opl9!Ou`Xw*9eF47^=5LVVJYD~xseN>wK;Hvw zuJSoUFK9pcfFIT`DTS2QFDc}{Via>ep0i%#xz$kz;AI|gPdI9{7@1ybi zZ!|QA@BAD0AeurSfcKVLK}zo}JDL@-9nDN*Z@C`eh3DmMA*J`0>zSnhe$&})A;tOX z&L6xthIP!|=MU(Z8R>?i`RIK7-&!xRZXK?d@6(NGrg)}NFN*;`TraV19bGSrc`1P3 zbaoB%6gJLR=X%M7N;eVu)A#o-&CT%MWw>!qusYUDyl0EsBc^*C3+xQ&8}Xh2Jc0ZJz_);115$H1H;3yr z;CFlfS7Fz4FCVEt4Bax!*L7dLH(uU7DS_IX0Z$tiCX}8Rm3fT)EKvb0dWfe zzZeF@Er2}TcA$QK(01tSxJ^}VN4PH22YnxW!sO<{m_OK;6Xp-?%PAUl1^$?bFDJmO z!j}`IMqf@0@Z|*f#W28^6Xfagg)*;}{E33Tv7-Gziu*liKYVCE#(wc@jk|3Cml)tn zDBy+1r+7$V=!I*cd}u#>Xg>g^vWKLa4e?FYsj_FBLX#vg#c z=L6y2(!U9yZsPTb+K|%gFt*G@wk`A1)?w(ni)EzG-3Ndo|KOnCg|E|k5nR9v%h?W) z((4giW(wdpo$UZA&eP9v0EhSIKJ;~r+xz*d#Yb~I|!@P8Y6uKiA+gkIMqSnT>qp!_NyoQH)=?*C#ZxbOG4frL(>K@L230}fy z(bwQlKVV1>(2e&!Iq&8ZB$H`QGIts2{#yKL3uWQ~c;P*Y;gI6BJ1$%!VXe-C`G(gA zEbM&&hC?1-`xHLW_rNQwTt1-jO?!v$en<`YrU8!o0oT2N^Io0@7dheI zI>ugx_Kxe-4M^#Fb&bI^zs4|)dUYD`!u6^EQo3GUgZ1Cjj5oYX;O*dMg%^Z3Jbdj_ z_(b0Wulz^q6~-6WD~vB)udXrDz*ED1z;!R+yq9+x^7tB!OLeSQ*oN`?yLzRA6uJd; zjgbfab)J##uhn1m0$k1ke=Y!C*dFN~q<9EE2l(YO@_CmT_jq{#w;_KAuH9x_f%6M+ z{Q~@cg@^B}&b-584d&fWkZoz+k<2_^HtP?%zb5ax0e+ZwLm;JjHw5q-#Js}uVO{`F zE*E$`Am0tH^9u|0S12(f2@G6ngIBK5MLE}EEBRAJOuqIvcQB_tFPJ@=A;XVe!-)qX^KpfHOpbv>51Y#s( zn9epl@!^}96>lzLFp%NP7$?I!={MrE2p;<1Fk=}piw8}MD02)UpizrqI@|Cq8W&at zPTv4dRsHR?{2LaO1qRr~7Re^{Tj)B$4i?256}OM{&=34JkUlA+|yMz1Z$hc%Sz102CEz3S*4#PwoD!+QsD0|C6=y`Sd8*QB=& z&|BvppqB^q)&W`_0eB`v?-HPQ$v;4E4A8p-Xk7~sV?y-iLI0Kau0N^D`g|7pt32qd z3IWcVOn+s|VY5eaAxw7_x8GshGT<+pJ&bD&P-Zgx1xse8CA;eR%VVDfDJ74|V;2Ja zHGjWU{|r$DAu`xBys%%T{c{W-v~=LTF?`U{f&Ba91eUi9=YNd9Uyj~1;BQ)$w_hGR z3HS?g4LcjabmR?3wivLgdU+$0*$*`4#OzF_3xMg!8=#rUvSe5N_{(GSSdQ>s9@`P% zugBjnB~LD7ve^W5&sE)iE!ky2FPm-2wgxbr{yEA#4WhnRefy2!gH{K;H--;d9gsJb z{wm764n*m$`uZHh=Rw5mIuI?}5#X=u^Ox$Mqs;Swzg0i}#_-PqfAfI1g#dp&{(hAb4x ztsJ4;bm%oi4zGH8KaBYOSM+|V{&_9m5Q)30>8%_=+jQtPM7FMadOwUvZ7THAk)o@b z-pUc4|BBu()nCz(m#doI$`O-Ihh9S@1aTFC7WCs_Cs9!S!SG8m@o-eq80qs~>wmy)XEs%9DBx!(ysB=W zvvNel59$8TeW5Q$uOU)lRnc1?_S2fOEIuo0psADv9nG(*$^u(aV4a-GQTR-SUOGBn zRnuEJs@=!vHC+GnK9jCnpA(JlW8bFxv@g}p=qPbjUDlPOyO|2Tbkwz~rnhpmw2#qi zxc>Qd>vN)R@ z9Bt}j^nU5~MMr`97(RyUpWfHdazW+jO{P-*bX29Prnho5BvYXmqJuJUl%lGpw{mnL zQ=ylR`cu{PR*u$VI`kT%=u|zuA4b116?*BYG*wM+goM3%7^LDYlyy4_4Ixi zHN$l1HAJYWdU`*MEb&+LeyMc`I^siB(_1-GgQ?Id$%{TSVb>!03-{PCSX_vZPr?|kY0g7&gm z)#dv!@0cH>`|p^on+d=1_vtEznIvFUTXM4C!j(B2!Xx-34&>!PWY1?>&7 zs>*_1v#RXH@MHASvLAGZfBW!9<4`1k4E07~C7^VAJ!rRHa3Oc_=v{Xp;GPWu-w8{0{Ii;Pq z@aq2QY}#osTwPDa)fP@R`o`>~5^>`(zpBh7SA%nZgS8W)9i*ZxTDmo6I@{+l*AHl5 z<)RP;sRg)+0{Hxp6058=uZu*R9F}|bJNJVm-B{@!vc%ja2txshVUXC|hmEkMR+INZJ4&b$2hfZP{$^pH*re zpBT6jZF+JiulQ;1nFq9P$k+Y;Z+Z=miY_E|;mPqz! zgsNa~PVVZArntncN+nJZ`*pb>-;*%}HQ`%EUzje#3kxY_{Nze30qC7iDTm?nY-6R! zzXoOQEXP{Lh%1K%VG}m?2AM8ihhnN21J%Q3w; fLJyH|q7OE({es1O4i#3#*wnAWOl$=WrXzm^$C@OA diff --git a/lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend64_wb.fdo b/lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend64_wb.fdo deleted file mode 100644 index d25b108..0000000 --- a/lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend64_wb.fdo +++ /dev/null @@ -1,30 +0,0 @@ -## NOTE: Do not edit this file. -## - -vlib work -vcom -explicit -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd" -vcom -explicit -93 "../../../rams/dpram_1w1r2c_ro_sim.vhd" -vcom -explicit -93 "../../../FIFO/src/gray_counter.vhd" -vcom -explicit -93 "../../../FIFO/src/fifo_async_ctrl.vhd" -vcom -explicit -93 "../../../FIFO/src/fifo_async.vhd" -vcom -explicit -93 "../../../FIFO/src/fifo_sync_ctrl.vhd" -vcom -explicit -93 "../../../FIFO/src/fifo_sync.vhd" -vcom -explicit -93 "../../../misc/utils_pkg.vhd" -vcom -explicit -93 "../../../misc/clockgen_virtex4.vhd" -vcom -explicit -93 "../src/sdram_config.vhd" -vcom -explicit -93 "../src/sdram_types.vhd" -vcom -explicit -93 "../src/sdram_cmd.vhd" -vcom -explicit -93 "../src/sdram_ctrl.vhd" -vcom -explicit -93 "../src/ddr_phy_virtex4.vhd" -vcom -explicit -93 "../src/sdram_ctrl_top.vhd" -vcom -explicit -93 "../src/sdram_ctrl_frontend64_wb.vhd" -vcom -explicit -93 "../src/mt46v16m16.vhd" -vcom -explicit -93 "../src/tb_sdram_ctrl_frontend64_wb.vhd" - -#restart -force -vsim -t 1ps -lib work tb_sdram_ctrl_frontend64_wb -do {tb_sdram_ctrl_frontend64_wb.wdo} -view wave -view structure -view signals -run 200us diff --git a/lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend64_wb.wdo b/lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend64_wb.wdo deleted file mode 100644 index f576e65..0000000 --- a/lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend64_wb.wdo +++ /dev/null @@ -1,55 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/clk_o -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/rst_o -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/cyc_o -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/stb_o -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/we_o -add wave -noupdate -format Literal /tb_sdram_ctrl_frontend64_wb/sel_o -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/ack_i -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/mrdy_o -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/srdy_i -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/addr_o -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/dat_i -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/dat_o -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/dout_reg -add wave -noupdate -format Literal /tb_sdram_ctrl_frontend64_wb/dout_cnt -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/clk_fb -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/clk_o -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/clk0_o -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/clk270_o -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/clk270var_o -add wave -noupdate -divider Part -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/part_cs_n -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/part_we_n -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/part_ras_n -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/part_cas_n -add wave -noupdate -format Literal /tb_sdram_ctrl_frontend64_wb/part_ba -add wave -noupdate -format Literal /tb_sdram_ctrl_frontend64_wb/part_dm -add wave -noupdate -format Literal /tb_sdram_ctrl_frontend64_wb/part_dqs -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/part_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/part_data -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb/inst_sdram_ctrl/inst_sdram_ctrl/u_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb/inst_sdram_ctrl/inst_sdram_ctrl/u_col_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb/inst_sdram_ctrl/inst_sdram_ctrl/col_addr_reg -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb/inst_sdram_ctrl/inst_sdram_ctrl/u_row_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb/inst_sdram_ctrl/inst_sdram_ctrl/row_addr_reg -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb/inst_sdram_ctrl/inst_sdram_ctrl/u_bank_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb/inst_sdram_ctrl/inst_sdram_ctrl/bank_addr_reg -add wave -noupdate -format Literal /tb_sdram_ctrl_frontend64_wb/sd_cmd -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {38990166 ps} 0} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -update -WaveRestoreZoom {38975716 ps} {39081070 ps} diff --git a/lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend_wb.fdo b/lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend_wb.fdo deleted file mode 100644 index 4b8b1e3..0000000 --- a/lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend_wb.fdo +++ /dev/null @@ -1,30 +0,0 @@ -## NOTE: Do not edit this file. -## - -vlib work -vcom -explicit -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd" -vcom -explicit -93 "../../../rams/dpram_1w1r2c_ro_sim.vhd" -vcom -explicit -93 "../../../FIFO/src/gray_counter.vhd" -vcom -explicit -93 "../../../FIFO/src/fifo_async_ctrl.vhd" -vcom -explicit -93 "../../../FIFO/src/fifo_async.vhd" -vcom -explicit -93 "../../../FIFO/src/fifo_sync_ctrl.vhd" -vcom -explicit -93 "../../../FIFO/src/fifo_sync.vhd" -vcom -explicit -93 "../../../misc/utils_pkg.vhd" -vcom -explicit -93 "../../../misc/clockgen_virtex4.vhd" -vcom -explicit -93 "../src/sdram_config.vhd" -vcom -explicit -93 "../src/sdram_types.vhd" -vcom -explicit -93 "../src/sdram_cmd.vhd" -vcom -explicit -93 "../src/sdram_ctrl.vhd" -vcom -explicit -93 "../src/ddr_phy_virtex4.vhd" -vcom -explicit -93 "../src/sdram_ctrl_top.vhd" -vcom -explicit -93 "../src/sdram_ctrl_frontend_wb.vhd" -vcom -explicit -93 "../src/mt46v16m16.vhd" -vcom -explicit -93 "../src/tb_sdram_ctrl_frontend_wb.vhd" - -#restart -force -vsim -t 1ps -lib work tb_sdram_ctrl_frontend_wb -do {tb_sdram_ctrl_frontend_wb.wdo} -view wave -view structure -view signals -run 200us diff --git a/lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend_wb.wdo b/lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend_wb.wdo deleted file mode 100644 index 20af0f9..0000000 --- a/lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend_wb.wdo +++ /dev/null @@ -1,62 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/clk_o -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/rst_o -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/cyc_o -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/stb_o -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/we_o -add wave -noupdate -format Literal /tb_sdram_ctrl_frontend_wb/sel_o -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/ack_i -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/mrdy_o -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/srdy_i -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/addr_o -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/dat_i -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/dat_o -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/dout_reg -add wave -noupdate -format Literal /tb_sdram_ctrl_frontend_wb/dout_cnt -add wave -noupdate -divider DEBUG -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl/cmd_fifo_din -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl/cmd_fifo_dout -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl/cmd_fifo_re -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl/cmd_fifo_we -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl/cmd_fifo_full -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl/cmd_fifo_empty -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/clk_o -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/clk0_o -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/clk270_o -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/clk270var_o -add wave -noupdate -divider Part -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/clk0_o -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/part_cs_n -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/part_we_n -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/part_ras_n -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/part_cas_n -add wave -noupdate -format Literal /tb_sdram_ctrl_frontend_wb/part_ba -add wave -noupdate -format Literal /tb_sdram_ctrl_frontend_wb/part_dm -add wave -noupdate -format Literal /tb_sdram_ctrl_frontend_wb/part_dqs -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/part_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/part_data -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/u_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/u_col_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/col_addr_reg -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/u_row_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/row_addr_reg -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/u_bank_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/bank_addr_reg -add wave -noupdate -format Literal /tb_sdram_ctrl_frontend_wb/sd_cmd -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {199582900 ps} 0} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -update -WaveRestoreZoom {199427964 ps} {200030108 ps} diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd deleted file mode 100644 index 11021bc..0000000 --- a/lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd +++ /dev/null @@ -1,367 +0,0 @@ -------------------------------------------------------------------------- --- Project: SDRAM controller --- This file: DDR physical layer (Virtex-4 specific) --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.sdram_config.all; -use work.sdram_types.all; - -Library UNISIM; -use UNISIM.vcomponents.all; - -entity ddr_phy is - Port ( - sys_rst : in STD_LOGIC; - sys_clk0 : in STD_LOGIC; - sys_clk270 : in STD_LOGIC; - u_tag_in : in user_tag_t; - u_tag_rd : out user_tag_t; - u_tag_wr : out user_tag_t; - read_clk : in STD_LOGIC; - phy_ctrl : in phy_ctrl_t; - part_ctrl : in part_ctrl_t; - sdr_data_w : in unsigned(SDR_DATA_WIDTH-1 downto 0); - sdr_dm : in unsigned(SDR_DM_WIDTH-1 downto 0); - sdr_data_r : out unsigned(SDR_DATA_WIDTH-1 downto 0); - sdr_data_vld : out STD_LOGIC; - sdr_data_req_w : out STD_LOGIC; - part_clk_p : out STD_LOGIC; - part_clk_n : out STD_LOGIC; - part_dm : out unsigned(DDR_DM_WIDTH-1 downto 0); - part_dqs : inout unsigned(DDR_DQS_WIDTH-1 downto 0); - part_data : inout unsigned(DDR_DATA_WIDTH-1 downto 0); - part_ba : out unsigned(DDR_BANK_WIDTH-1 downto 0); - part_addr : out unsigned(DDR_ADDR_WIDTH-1 downto 0); - part_cs_n : out STD_LOGIC; - part_we_n : out STD_LOGIC; - part_cas_n : out STD_LOGIC; - part_ras_n : out STD_LOGIC; - part_cke : out STD_LOGIC - ); -end ddr_phy; - -architecture tech of ddr_phy is - - signal dqs_drive : std_logic; - signal drive : std_logic; - signal dqs : unsigned(DDR_DQS_WIDTH-1 downto 0); - signal dqs_zen : unsigned(DDR_DQS_WIDTH-1 downto 0); - signal dqs_rst : std_logic; - signal ddr_data_w : unsigned(DDR_DATA_WIDTH-1 downto 0); - signal data_r : unsigned(SDR_DATA_WIDTH-1 downto 0); - signal data_reg_r : unsigned(SDR_DATA_WIDTH-1 downto 0); - signal drive270 : unsigned(DDR_DATA_WIDTH-1 downto 0); - signal part_ctrl_reg : part_ctrl_t; - signal we_reg : std_logic; - signal read_en : std_logic; - - type u_tag_array_t is array (natural range 0 to 4) of user_tag_t; - signal u_tag_pipe : u_tag_array_t; - -begin - ------------------------------------------------------------------------------------------------------------------------------------------------- -utag_pipe: - process(sys_rst, sys_clk0) - begin - if rising_edge(sys_clk0) then - for i in u_tag_pipe'length-1 downto 1 loop - u_tag_pipe(i) <= u_tag_pipe(i-1); - end loop; - if phy_ctrl.utag_we = '1' then - u_tag_pipe(0) <= u_tag_in; - end if; - end if; - end process; - -WE_REGISTER: - process(sys_rst, sys_clk0) - begin - if sys_rst = '1' then - we_reg <= '0'; - elsif rising_edge(sys_clk0) then - we_reg <= phy_ctrl.we; - end if; - end process; - -DATA_DRIVE_GEN: - process(sys_clk0) - begin - if falling_edge(sys_clk0) then - dqs_rst <= not we_reg; - drive <= we_reg; - end if; - end process; - -DQS_DRIVE_GEN: - process(sys_clk0) - variable p : unsigned(1 downto 0); - begin - if rising_edge(sys_clk0) then - if phy_ctrl.drive_en = '1' then - p := (others => '1'); - else - p := p(p'left-1 downto 0) & '0'; - end if; - end if; - dqs_drive <= p(p'left); - end process; - ------------------------------------------------------------------------------------------------------------------------------------------------- --- SDRAM Clock -ODDR_clk_p : ODDR - generic map - ( - DDR_CLK_EDGE => "OPPOSITE_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE" - INIT => '0', -- Initial value for Q port ('1' or '0') - SRTYPE => "SYNC" -- Reset Type ("ASYNC" or "SYNC") - ) - port map ( - Q => part_clk_p, -- 1-bit DDR output - C => sys_clk0, -- 1-bit clock input - CE => '1', -- 1-bit clock enable input - D1 => '1', -- 1-bit data input (positive edge) - D2 => '0', -- 1-bit data input (negative edge) - R => '0', -- 1-bit reset input - S => '0' -- 1-bit set input - ); - -ODDR_clk_n : ODDR - generic map - ( - DDR_CLK_EDGE => "OPPOSITE_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE" - INIT => '0', -- Initial value for Q port ('1' or '0') - SRTYPE => "SYNC" -- Reset Type ("ASYNC" or "SYNC") - ) - port map ( - Q => part_clk_n, -- 1-bit DDR output - C => sys_clk0, -- 1-bit clock input - CE => '1', -- 1-bit clock enable input - D1 => '0', -- 1-bit data input (positive edge) - D2 => '1', -- 1-bit data input (negative edge) - R => '0', -- 1-bit reset input - S => '0' -- 1-bit set input - ); - ------------------------------------------------------------------------------------------------------------------------------------------------- --- Data OUT DDR-FFs -gen_ddr_data_out: - for n in 0 to DDR_DATA_WIDTH-1 generate - begin - ODDR_data : ODDR - generic map - ( - DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE" - INIT => '0', -- Initial value for Q port ('1' or '0') - SRTYPE => "SYNC" -- Reset Type ("ASYNC" or "SYNC") - ) - port map ( - Q => ddr_data_w(n), -- 1-bit DDR output - C => sys_clk270, -- 1-bit clock input - CE => '1', -- 1-bit clock enable input - D1 => sdr_data_w(n + DDR_DATA_WIDTH), -- 1-bit data input (positive edge) - D2 => sdr_data_w(n), -- 1-bit data input (negative edge) - R => '0', -- 1-bit reset input - S => '0' -- 1-bit set input - ); - end generate gen_ddr_data_out; - --- Sample tristate on clock90 - process (sys_clk270) - begin - if rising_edge(sys_clk270) then - for n in 0 to DDR_DATA_WIDTH-1 loop - drive270(n) <= drive; - end loop; - end if; - end process; - --- Output mux -out_mux_data: - for n in 0 to DDR_DATA_WIDTH-1 generate - part_data(n) <= ddr_data_w(n) when drive270(n) = '1' else 'Z'; - end generate; - ------------------------------------------------------------------------------------------------------------------------------------------------- --- Data-mask OUT DDR-FFs -gen_ddr_dm_out: - for n in 0 to DDR_DM_WIDTH-1 generate - begin - ODDR_dm : ODDR - generic map - ( - DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE" - INIT => '0', -- Initial value for Q port ('1' or '0') - SRTYPE => "SYNC" -- Reset Type ("ASYNC" or "SYNC") - ) - port map ( - Q => part_dm(n), -- 1-bit DDR output - C => sys_clk270, -- 1-bit clock input - CE => '1', -- 1-bit clock enable input - D1 => sdr_dm(n + DDR_DM_WIDTH), -- 1-bit data input (positive edge) - D2 => sdr_dm(n), -- 1-bit data input (negative edge) - R => '0', -- 1-bit reset input - S => '0' -- 1-bit set input - ); - end generate gen_ddr_dm_out; - ------------------------------------------------------------------------------------------------------------------------------------------------- --- DQS OUT DDR-FFs -gen_dqs_out: - for n in 0 to DDR_DQS_WIDTH-1 generate - begin - ODDR_dqs : ODDR - generic map - ( - DDR_CLK_EDGE => "OPPOSITE_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE" - INIT => '0', -- Initial value for Q port ('1' or '0') - SRTYPE => "SYNC" -- Reset Type ("ASYNC" or "SYNC") - ) - port map ( - Q => dqs(n), -- 1-bit DDR output - C => sys_clk0, -- 1-bit clock input - CE => '1', -- 1-bit clock enable input - D2 => '0', -- 1-bit data input (positive edge) - D1 => '1', -- 1-bit data input (negative edge) - R => dqs_rst, -- 1-bit reset input - S => '0' -- 1-bit set input - ); - end generate gen_dqs_out; - --- Tristate-Control fuer dqs - process (sys_clk0) is - variable zctrl : boolean; - begin - if rising_edge(sys_clk0) then - if dqs_drive = '1' then - zctrl := false; - else - zctrl := true; - end if; - if zctrl then - dqs_zen <= (others => '1'); - else - dqs_zen <= (others => '0'); - end if; - end if; - end process; - --- Tristate-Buffer fuer dqs -gen_out_mux_dqs: - for n in 0 to DDR_DQS_WIDTH-1 generate - part_dqs(n) <= 'Z' when dqs_zen(n)='1' else dqs(n); - end generate gen_out_mux_dqs; - ------------------------------------------------------------------------------------------------------------------------------------------------- - process (sys_rst, sys_clk0) is - begin - if sys_rst = '1' then - part_ctrl_reg.cmd <= COMMAND(SD_DESELECT); - part_ctrl_reg.ba <= (others=>'0'); - part_ctrl_reg.addr <= (others=>'0'); - part_ctrl_reg.cke <= '0'; - elsif rising_edge(sys_clk0) then - part_ctrl_reg <= part_ctrl; - end if; - end process; - - process (sys_clk0) is - begin - if falling_edge(sys_clk0) then - part_ras_n <= part_ctrl_reg.cmd.ras_n; - part_cas_n <= part_ctrl_reg.cmd.cas_n; - part_we_n <= part_ctrl_reg.cmd.we_n; - part_cs_n <= part_ctrl_reg.cmd.cs_n; - part_ba <= part_ctrl_reg.ba; - part_addr <= part_ctrl_reg.addr; - part_cke <= part_ctrl_reg.cke; - end if; - end process; - ------------------------------------------------------------------ --- READ DATA Processing ------------------------------------------------------------------ -gen_ddr_data_in: - for n in 0 to DDR_DATA_WIDTH-1 generate - begin - IDDR_data : IDDR - generic map - ( - DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE", "SAME_EDGE" or "SAME_EDGE_PIPELINED" - INIT_Q1 => '0', -- Initial value of Q1: '0' or '1' - INIT_Q2 => '0', -- Initial value of Q2: '0' or '1' - SRTYPE => "SYNC" -- Set/Reset type: "SYNC" or "ASYNC" - ) - port map - ( - Q1 => data_r(n), -- 1-bit output for positive edge of clock - Q2 => data_r(n + DDR_DATA_WIDTH), -- 1-bit output for negative edge of clock - C => read_clk, -- 1-bit clock input - CE => read_en, -- 1-bit clock enable input - D => part_data(n), -- 1-bit DDR data input - R => '0', -- 1-bit reset - S => '0' -- 1-bit set - ); - end generate; - - -data_sample_stage: - process (sys_clk0) - begin - if falling_edge(sys_clk0) then - data_reg_r <= data_r; - end if; - end process; - -misc_flags_and_data_out: - process (sys_rst, sys_clk0) - variable p : unsigned(3 downto 0); - begin - if sys_rst = '1' then - p := (others => '0'); - read_en <= '0'; - sdr_data_vld <= '0'; - sdr_data_req_w <= '0'; - elsif rising_edge(sys_clk0) then - sdr_data_r <= data_reg_r; - if p(3) = '1' then - u_tag_rd <= u_tag_pipe(4); - end if; - if phy_ctrl.we = '1' then - u_tag_wr <= u_tag_pipe(0); - end if; - sdr_data_req_w <= phy_ctrl.we; - sdr_data_vld <= p(3); - read_en <= p(1); - if phy_ctrl.re = '1' then - p := p(p'left-1 downto 0) & '1'; - else - p := p(p'left-1 downto 0) & '0'; - end if; - end if; - end process; - ------------------------------------------------------------------------------------------- -end tech; diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/mt46v16m16.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/mt46v16m16.vhd deleted file mode 100644 index 356bb28..0000000 --- a/lib/SDRAM/ddr_sdr_v1_5/src/mt46v16m16.vhd +++ /dev/null @@ -1,1320 +0,0 @@ ------------------------------------------------------------------------------------------ --- --- File Name: MT46V16M16.VHD --- Version: 2.1 --- Date: January 14th, 2002 --- Model: Behavioral --- Simulator: NCDesktop - http://www.cadence.com --- ModelSim PE - http://www.model.com --- --- Dependencies: None --- --- Author: Son P. Huynh --- Email: sphuynh@micron.com --- Phone: (208) 368-3825 --- Company: Micron Technology, Inc. --- Part Number: MT46V16M16 (4 Mb x 16 x 4 Banks) --- --- Description: Micron 256 Mb SDRAM DDR (Double Data Rate) --- --- Limitation: Doesn't model internal refresh counter --- --- Note: --- --- Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY --- WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY --- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR --- A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT. --- --- Copyright (c) 1998 Micron Semiconductor Products, Inc. --- All rights researved --- --- Rev Author Date Changes --- --- ---------------------------- ---------- ------------------------------------- --- 2.1 Son P. Huynh 01/14/2002 - Fix Burst_counter --- Micron Technology, Inc. --- --- 2.0 Son P. Huynh 11/08/2001 - Second release --- Micron Technology, Inc. - Rewrote and remove SHARED VARIABLE --- ------------------------------------------------------------------------------------------ - -LIBRARY IEEE; - USE IEEE.STD_LOGIC_1164.ALL; - USE IEEE.STD_LOGIC_UNSIGNED.ALL; - USE IEEE.STD_LOGIC_ARITH.ALL; - -ENTITY MT46V16M16 IS - GENERIC ( -- Timing for -75Z CL2 - tCK : TIME := 7.500 ns; - tCH : TIME := 3.375 ns; -- 0.45*tCK - tCL : TIME := 3.375 ns; -- 0.45*tCK - tDH : TIME := 0.500 ns; - tDS : TIME := 0.500 ns; - tIH : TIME := 0.900 ns; - tIS : TIME := 0.900 ns; - tMRD : TIME := 15.000 ns; - tRAS : TIME := 40.000 ns; - tRAP : TIME := 20.000 ns; - tRC : TIME := 65.000 ns; - tRFC : TIME := 75.000 ns; - tRCD : TIME := 20.000 ns; - tRP : TIME := 20.000 ns; - tRRD : TIME := 15.000 ns; - tWR : TIME := 15.000 ns; - addr_bits : INTEGER := 13; - data_bits : INTEGER := 16; - cols_bits : INTEGER := 9 - ); - PORT ( - Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z'); - Dqs : INOUT STD_LOGIC_VECTOR (1 DOWNTO 0) := "ZZ"; - Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); - Ba : IN STD_LOGIC_VECTOR (1 DOWNTO 0); - Clk : IN STD_LOGIC; - Clk_n : IN STD_LOGIC; - Cke : IN STD_LOGIC; - Cs_n : IN STD_LOGIC; - Ras_n : IN STD_LOGIC; - Cas_n : IN STD_LOGIC; - We_n : IN STD_LOGIC; - Dm : IN STD_LOGIC_VECTOR (1 DOWNTO 0) - ); -END MT46V16M16; - -ARCHITECTURE behave OF MT46V16M16 IS - -- Array for Read pipeline - TYPE Array_Read_cmnd IS ARRAY (8 DOWNTO 0) OF STD_LOGIC; - TYPE Array_Read_bank IS ARRAY (8 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0); - TYPE Array_Read_cols IS ARRAY (8 DOWNTO 0) OF STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0); - - -- Array for Write pipeline - TYPE Array_Write_cmnd IS ARRAY (2 DOWNTO 0) OF STD_LOGIC; - TYPE Array_Write_bank IS ARRAY (2 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0); - TYPE Array_Write_cols IS ARRAY (2 DOWNTO 0) OF STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0); - - -- Array for Auto Precharge - TYPE Array_Read_precharge IS ARRAY (3 DOWNTO 0) OF STD_LOGIC; - TYPE Array_Write_precharge IS ARRAY (3 DOWNTO 0) OF STD_LOGIC; - TYPE Array_Count_precharge IS ARRAY (3 DOWNTO 0) OF INTEGER; - - -- Array for Manual Precharge - TYPE Array_A10_precharge IS ARRAY (8 DOWNTO 0) OF STD_LOGIC; - TYPE Array_Bank_precharge IS ARRAY (8 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0); - TYPE Array_Cmnd_precharge IS ARRAY (8 DOWNTO 0) OF STD_LOGIC; - - -- Array for Burst Terminate - TYPE Array_Cmnd_bst IS ARRAY (8 DOWNTO 0) OF STD_LOGIC; - - -- Array for Memory Access - TYPE Array_ram_type IS ARRAY (2**cols_bits - 1 DOWNTO 0) OF STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0); - TYPE Array_ram_pntr IS ACCESS Array_ram_type; - TYPE Array_ram_stor IS ARRAY (2**addr_bits - 1 DOWNTO 0) OF Array_ram_pntr; - - -- Data pair - SIGNAL Dq_pair : STD_LOGIC_VECTOR (2 * data_bits - 1 DOWNTO 0); - SIGNAL Dm_pair : STD_LOGIC_VECTOR (3 DOWNTO 0); - - -- Mode Register - SIGNAL Mode_reg : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0'); - - -- Command Decode Variables - SIGNAL Active_enable, Aref_enable, Burst_term, Ext_mode_enable : STD_LOGIC := '0'; - SIGNAL Mode_reg_enable, Prech_enable, Read_enable, Write_enable : STD_LOGIC := '0'; - - -- Burst Length Decode Variables - SIGNAL Burst_length_2, Burst_length_4, Burst_length_8, Burst_length_f : STD_LOGIC := '0'; - - -- Cas Latency Decode Variables - SIGNAL Cas_latency_15, Cas_latency_2, Cas_latency_25, Cas_latency_3, Cas_latency_4 : STD_LOGIC := '0'; - - -- Internal Control Signals - SIGNAL Cs_in, Ras_in, Cas_in, We_in : STD_LOGIC := '0'; - - -- System Clock - SIGNAL Sys_clk : STD_LOGIC := '0'; - - -- Dqs buffer - SIGNAL Dqs_out : STD_LOGIC_VECTOR (1 DOWNTO 0) := "ZZ"; - -BEGIN - -- Strip the strength - Cs_in <= To_X01 (Cs_n); - Ras_in <= To_X01 (Ras_n); - Cas_in <= To_X01 (Cas_n); - We_in <= To_X01 (We_n); - - -- Commands Decode - Active_enable <= NOT(Cs_in) AND NOT(Ras_in) AND Cas_in AND We_in; - Aref_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND We_in; - Burst_term <= NOT(Cs_in) AND Ras_in AND Cas_in AND NOT(We_in); - Ext_mode_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in) AND Ba(0) AND NOT(Ba(1)); - Mode_reg_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in) AND NOT(Ba(0)) AND NOT(Ba(1)); - Prech_enable <= NOT(Cs_in) AND NOT(Ras_in) AND Cas_in AND NOT(We_in); - Read_enable <= NOT(Cs_in) AND Ras_in AND NOT(Cas_in) AND We_in; - Write_enable <= NOT(Cs_in) AND Ras_in AND NOT(Cas_in) AND NOT(We_in); - - -- Burst Length Decode - Burst_length_2 <= NOT(Mode_reg(2)) AND NOT(Mode_reg(1)) AND Mode_reg(0); - Burst_length_4 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND NOT(Mode_reg(0)); - Burst_length_8 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND Mode_reg(0); - Burst_length_f <= (Mode_reg(2)) AND Mode_reg(1) AND Mode_reg(0); - - -- CAS Latency Decode - Cas_latency_15 <= Mode_reg(6) AND NOT(Mode_reg(5)) AND (Mode_reg(4)); - Cas_latency_2 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND NOT(Mode_reg(4)); - Cas_latency_25 <= Mode_reg(6) AND Mode_reg(5) AND NOT(Mode_reg(4)); - Cas_latency_3 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND Mode_reg(4); - Cas_latency_4 <= (Mode_reg(6)) AND NOT(Mode_reg(5)) AND NOT(Mode_reg(4)); - - -- Dqs buffer - Dqs <= Dqs_out; - - -- - -- System Clock - -- - int_clk : PROCESS (Clk, Clk_n) - VARIABLE ClkZ, CkeZ : STD_LOGIC := '0'; - begin - IF Clk = '1' AND Clk_n = '0' THEN - ClkZ := '1'; - CkeZ := Cke; - ELSIF Clk = '0' AND Clk_n = '1' THEN - ClkZ := '0'; - END IF; - Sys_clk <= CkeZ AND ClkZ; - END PROCESS; - - -- - -- Main Process - -- - state_register : PROCESS - -- Precharge Variables - VARIABLE Pc_b0, Pc_b1, Pc_b2, Pc_b3 : STD_LOGIC := '0'; - - -- Activate Variables - VARIABLE Act_b0, Act_b1, Act_b2, Act_b3 : STD_LOGIC := '1'; - - -- Data IO variables - VARIABLE Data_in_enable, Data_out_enable : STD_LOGIC := '0'; - - -- Internal address mux variables - VARIABLE Cols_brst : STD_LOGIC_VECTOR (2 DOWNTO 0); - VARIABLE Prev_bank : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"; - VARIABLE Bank_addr : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"; - VARIABLE Cols_addr : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0); - VARIABLE Rows_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); - VARIABLE B0_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); - VARIABLE B1_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); - VARIABLE B2_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); - VARIABLE B3_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); - - -- DLL Reset variables - VARIABLE DLL_enable : STD_LOGIC := '0'; - VARIABLE DLL_reset : STD_LOGIC := '0'; - VARIABLE DLL_done : STD_LOGIC := '0'; - VARIABLE DLL_count : INTEGER := 0; - - -- Timing Check - VARIABLE MRD_chk : TIME := 0 ns; - VARIABLE RFC_chk : TIME := 0 ns; - VARIABLE RRD_chk : TIME := 0 ns; - VARIABLE RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3 : TIME := 0 ns; - VARIABLE RAP_chk0, RAP_chk1, RAP_chk2, RAP_chk3 : TIME := 0 ns; - VARIABLE RC_chk0, RC_chk1, RC_chk2, RC_chk3 : TIME := 0 ns; - VARIABLE RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3 : TIME := 0 ns; - VARIABLE RP_chk0, RP_chk1, RP_chk2, RP_chk3 : TIME := 0 ns; - VARIABLE WR_chk0, WR_chk1, WR_chk2, WR_chk3 : TIME := 0 ns; - - -- Read pipeline variables - VARIABLE Read_cmnd : Array_Read_cmnd; - VARIABLE Read_bank : Array_Read_bank; - VARIABLE Read_cols : Array_Read_cols; - - -- Write pipeline variables - VARIABLE Write_cmnd : Array_Write_cmnd; - VARIABLE Write_bank : Array_Write_bank; - VARIABLE Write_cols : Array_Write_cols; - - -- Auto Precharge variables - VARIABLE Read_precharge : Array_Read_precharge := ('0' & '0' & '0' & '0'); - VARIABLE Write_precharge : Array_Write_precharge := ('0' & '0' & '0' & '0'); - VARIABLE Count_precharge : Array_Count_precharge := ( 0 & 0 & 0 & 0 ); - - -- Manual Precharge variables - VARIABLE A10_precharge : Array_A10_precharge; - VARIABLE Bank_precharge : Array_Bank_precharge; - VARIABLE Cmnd_precharge : Array_Cmnd_precharge; - - -- Burst Terminate variable - VARIABLE Cmnd_bst : Array_Cmnd_bst; - - -- Memory Banks - VARIABLE Bank0 : Array_ram_stor; - VARIABLE Bank1 : Array_ram_stor; - VARIABLE Bank2 : Array_ram_stor; - VARIABLE Bank3 : Array_ram_stor; - - -- Burst Counter - VARIABLE Burst_counter : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0); - - -- Internal Dqs initialize - VARIABLE Dqs_int : STD_LOGIC := '0'; - - -- Data buffer for DM Mask - VARIABLE Data_buf : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z'); - - -- - -- Initialize empty rows - -- - PROCEDURE Init_mem (Bank : STD_LOGIC_VECTOR; Row_index : INTEGER) IS - VARIABLE i, j : INTEGER := 0; - BEGIN - IF Bank = "00" THEN - IF Bank0 (Row_index) = NULL THEN -- Check to see if row empty - Bank0 (Row_index) := NEW Array_ram_type; -- Open new row for access - FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP -- Filled row with zeros - FOR j IN (data_bits - 1) DOWNTO 0 LOOP - Bank0 (Row_index) (i) (j) := '0'; - END LOOP; - END LOOP; - END IF; - ELSIF Bank = "01" THEN - IF Bank1 (Row_index) = NULL THEN - Bank1 (Row_index) := NEW Array_ram_type; - FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP - FOR j IN (data_bits - 1) DOWNTO 0 LOOP - Bank1 (Row_index) (i) (j) := '0'; - END LOOP; - END LOOP; - END IF; - ELSIF Bank = "10" THEN - IF Bank2 (Row_index) = NULL THEN - Bank2 (Row_index) := NEW Array_ram_type; - FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP - FOR j IN (data_bits - 1) DOWNTO 0 LOOP - Bank2 (Row_index) (i) (j) := '0'; - END LOOP; - END LOOP; - END IF; - ELSIF Bank = "11" THEN - IF Bank3 (Row_index) = NULL THEN - Bank3 (Row_index) := NEW Array_ram_type; - FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP - FOR j IN (data_bits - 1) DOWNTO 0 LOOP - Bank3 (Row_index) (i) (j) := '0'; - END LOOP; - END LOOP; - END IF; - END IF; - END; - - -- - -- Burst Counter - -- - PROCEDURE Burst_decode IS - VARIABLE Cols_temp : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0) := (OTHERS => '0'); - BEGIN - -- Advance burst counter - Burst_counter := Burst_counter + 1; - - -- Burst Type - IF Mode_reg (3) = '0' THEN - Cols_temp := Cols_addr + 1; - ELSIF Mode_reg (3) = '1' THEN - Cols_temp (2) := Burst_counter (2) XOR Cols_brst (2); - Cols_temp (1) := Burst_counter (1) XOR Cols_brst (1); - Cols_temp (0) := Burst_counter (0) XOR Cols_brst (0); - END IF; - - -- Burst Length - IF Burst_length_2 = '1' THEN - Cols_addr (0) := Cols_temp (0); - ELSIF Burst_length_4 = '1' THEN - Cols_addr (1 DOWNTO 0) := Cols_temp (1 DOWNTO 0); - ELSIF Burst_length_8 = '1' THEN - Cols_addr (2 DOWNTO 0) := Cols_temp (2 DOWNTO 0); - ELSE - Cols_addr := Cols_temp; - END IF; - - -- Data counter - IF Burst_length_2 = '1' THEN - IF Burst_counter >= 2 THEN - IF Data_in_enable = '1' THEN - Data_in_enable := '0'; - ELSIF Data_out_enable = '1' THEN - Data_out_enable := '0'; - END IF; - END IF; - ELSIF Burst_length_4 = '1' THEN - IF Burst_counter >= 4 THEN - IF Data_in_enable = '1' THEN - Data_in_enable := '0'; - ELSIF Data_out_enable = '1' THEN - Data_out_enable := '0'; - END IF; - END IF; - ELSIF Burst_length_8 = '1' THEN - IF Burst_counter >= 8 THEN - IF Data_in_enable = '1' THEN - Data_in_enable := '0'; - ELSIF Data_out_enable = '1' THEN - Data_out_enable := '0'; - END IF; - END IF; - END IF; - END; - - BEGIN - WAIT ON Sys_clk; - - -- - -- Manual Precharge Pipeline - -- - IF ((Sys_clk'EVENT AND Sys_clk = '0') OR (Sys_clk'EVENT AND Sys_clk = '1')) THEN - -- A10 Precharge Pipeline - A10_precharge(0) := A10_precharge(1); - A10_precharge(1) := A10_precharge(2); - A10_precharge(2) := A10_precharge(3); - A10_precharge(3) := A10_precharge(4); - A10_precharge(4) := A10_precharge(5); - A10_precharge(5) := A10_precharge(6); - A10_precharge(6) := A10_precharge(7); - A10_precharge(7) := A10_precharge(8); - A10_precharge(8) := '0'; - - -- Bank Precharge Pipeline - Bank_precharge(0) := Bank_precharge(1); - Bank_precharge(1) := Bank_precharge(2); - Bank_precharge(2) := Bank_precharge(3); - Bank_precharge(3) := Bank_precharge(4); - Bank_precharge(4) := Bank_precharge(5); - Bank_precharge(5) := Bank_precharge(6); - Bank_precharge(6) := Bank_precharge(7); - Bank_precharge(7) := Bank_precharge(8); - Bank_precharge(8) := "00"; - - -- Command Precharge Pipeline - Cmnd_precharge(0) := Cmnd_precharge(1); - Cmnd_precharge(1) := Cmnd_precharge(2); - Cmnd_precharge(2) := Cmnd_precharge(3); - Cmnd_precharge(3) := Cmnd_precharge(4); - Cmnd_precharge(4) := Cmnd_precharge(5); - Cmnd_precharge(5) := Cmnd_precharge(6); - Cmnd_precharge(6) := Cmnd_precharge(7); - Cmnd_precharge(7) := Cmnd_precharge(8); - Cmnd_precharge(8) := '0'; - - -- Terminate Read if same bank or all banks - IF ((Cmnd_precharge (0) = '1') AND - (Bank_precharge (0) = Bank_addr OR A10_precharge (0) = '1') AND - (Data_out_enable = '1')) THEN - Data_out_enable := '0'; - END IF; - END IF; - - -- - -- Burst Terminate Pipeline - -- - IF ((Sys_clk'EVENT AND Sys_clk = '0') OR (Sys_clk'EVENT AND Sys_clk = '1')) THEN - -- Burst Terminate pipeline - Cmnd_bst (0) := Cmnd_bst (1); - Cmnd_bst (1) := Cmnd_bst (2); - Cmnd_bst (2) := Cmnd_bst (3); - Cmnd_bst (3) := Cmnd_bst (4); - Cmnd_bst (4) := Cmnd_bst (5); - Cmnd_bst (5) := Cmnd_bst (6); - Cmnd_bst (6) := Cmnd_bst (7); - Cmnd_bst (7) := Cmnd_bst (8); - Cmnd_bst (8) := '0'; - - -- Terminate current Read - IF ((Cmnd_bst (0) = '1') AND (Data_out_enable = '1')) THEN - Data_out_enable := '0'; - END IF; - END IF; - - -- - -- Dq and Dqs Drivers - -- - IF ((Sys_clk'EVENT AND Sys_clk = '0') OR (Sys_clk'EVENT AND Sys_clk = '1')) THEN - -- Read Command Pipeline - Read_cmnd (0) := Read_cmnd (1); - Read_cmnd (1) := Read_cmnd (2); - Read_cmnd (2) := Read_cmnd (3); - Read_cmnd (3) := Read_cmnd (4); - Read_cmnd (4) := Read_cmnd (5); - Read_cmnd (5) := Read_cmnd (6); - Read_cmnd (6) := Read_cmnd (7); - Read_cmnd (7) := Read_cmnd (8); - Read_cmnd (8) := '0'; - - -- Read Bank Pipeline - Read_bank (0) := Read_bank (1); - Read_bank (1) := Read_bank (2); - Read_bank (2) := Read_bank (3); - Read_bank (3) := Read_bank (4); - Read_bank (4) := Read_bank (5); - Read_bank (5) := Read_bank (6); - Read_bank (6) := Read_bank (7); - Read_bank (7) := Read_bank (8); - Read_bank (8) := "00"; - - -- Read Column Pipeline - Read_cols (0) := Read_cols (1); - Read_cols (1) := Read_cols (2); - Read_cols (2) := Read_cols (3); - Read_cols (3) := Read_cols (4); - Read_cols (4) := Read_cols (5); - Read_cols (5) := Read_cols (6); - Read_cols (6) := Read_cols (7); - Read_cols (7) := Read_cols (8); - Read_cols (8) := (OTHERS => '0'); - - -- Initialize Read command - IF Read_cmnd (0) = '1' THEN - Data_out_enable := '1'; - Bank_addr := Read_bank (0); - Cols_addr := Read_cols (0); - Cols_brst := Cols_addr (2 DOWNTO 0); - Burst_counter := (OTHERS => '0'); - - -- Row address mux - CASE Bank_addr IS - WHEN "00" => Rows_addr := B0_row_addr; - WHEN "01" => Rows_addr := B1_row_addr; - WHEN "10" => Rows_addr := B2_row_addr; - WHEN OTHERS => Rows_addr := B3_row_addr; - END CASE; - END IF; - - -- Toggle Dqs during Read command - IF Data_out_enable = '1' THEN - Dqs_int := '0'; - IF Dqs_out = "00" THEN - Dqs_out <= "11"; - ELSIF Dqs_out = "11" THEN - Dqs_out <= "00"; - ELSE - Dqs_out <= "00"; - END IF; - ELSIF Data_out_enable = '0' AND Dqs_int = '0' THEN - Dqs_out <= "ZZ"; - END IF; - - -- Initialize Dqs for Read command - IF Read_cmnd (2) = '1' THEN - IF Data_out_enable = '0' THEN - Dqs_int := '1'; - Dqs_out <= "00"; - END IF; - END IF; - - -- Read Latch - IF Data_out_enable = '1' THEN - -- Initialize Memory - Init_mem (Bank_addr, CONV_INTEGER(Rows_addr)); - - -- Output Data - CASE Bank_addr IS - WHEN "00" => Dq <= Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - WHEN "01" => Dq <= Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - WHEN "10" => Dq <= Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - WHEN OTHERS => Dq <= Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - END CASE; - - -- Increase Burst Counter - Burst_decode; - ELSE - Dq <= (OTHERS => 'Z'); - END IF; - END IF; - - -- - -- Write FIFO and DM Mask Logic - -- - IF Sys_clk'EVENT AND Sys_clk = '1' THEN - -- Write command pipeline - Write_cmnd (0) := Write_cmnd (1); - Write_cmnd (1) := Write_cmnd (2); - Write_cmnd (2) := '0'; - - -- Write command pipeline - Write_bank (0) := Write_bank (1); - Write_bank (1) := Write_bank (2); - Write_bank (2) := "00"; - - -- Write column pipeline - Write_cols (0) := Write_cols (1); - Write_cols (1) := Write_cols (2); - Write_cols (2) := (OTHERS => '0'); - - -- Initialize Write command - IF Write_cmnd (0) = '1' THEN - Data_in_enable := '1'; - Bank_addr := Write_bank (0); - Cols_addr := Write_cols (0); - Cols_brst := Cols_addr (2 DOWNTO 0); - Burst_counter := (OTHERS => '0'); - - -- Row address mux - CASE Bank_addr IS - WHEN "00" => Rows_addr := B0_row_addr; - WHEN "01" => Rows_addr := B1_row_addr; - WHEN "10" => Rows_addr := B2_row_addr; - WHEN OTHERS => Rows_addr := B3_row_addr; - END CASE; - END IF; - - -- Write data - IF Data_in_enable = '1' THEN - -- Initialize memory - Init_mem (Bank_addr, CONV_INTEGER(Rows_addr)); - - -- Write first data - IF Dm_pair (1) = '0' OR Dm_pair (0) = '0' THEN - -- Data Buffer - CASE Bank_addr IS - WHEN "00" => Data_buf := Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - WHEN "01" => Data_buf := Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - WHEN "10" => Data_buf := Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - WHEN OTHERS => Data_buf := Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - END CASE; - - -- Perform DM Mask - IF Dm_pair (0) = '0' THEN - Data_buf ( 7 DOWNTO 0) := Dq_pair ( 7 DOWNTO 0); - END IF; - IF Dm_pair (1) = '0' THEN - Data_buf (15 DOWNTO 8) := Dq_pair (15 DOWNTO 8); - END IF; - - -- Write Data - CASE Bank_addr IS - WHEN "00" => Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; - WHEN "01" => Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; - WHEN "10" => Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; - WHEN OTHERS => Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; - END CASE; - END IF; - - -- Increase Burst Counter - Burst_decode; - - -- Write second data - IF Dm_pair (3) = '0' OR Dm_pair (2) = '0' THEN - -- Data Buffer - CASE Bank_addr IS - WHEN "00" => Data_buf := Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - WHEN "01" => Data_buf := Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - WHEN "10" => Data_buf := Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - WHEN OTHERS => Data_buf := Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - END CASE; - - -- Perform DM Mask - IF Dm_pair (2) = '0' THEN - Data_buf ( 7 DOWNTO 0) := Dq_pair (23 DOWNTO 16); - END IF; - IF Dm_pair (3) = '0' THEN - Data_buf (15 DOWNTO 8) := Dq_pair (31 DOWNTO 24); - END IF; - - -- Write Data - CASE Bank_addr IS - WHEN "00" => Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; - WHEN "01" => Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; - WHEN "10" => Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; - WHEN OTHERS => Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; - END CASE; - END IF; - - -- Increase Burst Counter - Burst_decode; - - -- tWR start and tWTR check - IF Dm_pair (3 DOWNTO 2) = "00" OR Dm_pair (1 DOWNTO 0) = "00" THEN - CASE Bank_addr IS - WHEN "00" => WR_chk0 := NOW; - WHEN "01" => WR_chk1 := NOW; - WHEN "10" => WR_chk2 := NOW; - WHEN OTHERS => WR_chk3 := NOW; - END CASE; - - -- tWTR check - ASSERT (Read_enable = '0') - REPORT "tWTR violation during Read" - SEVERITY WARNING; - END IF; - END IF; - END IF; - - -- - -- Auto Precharge Calculation - -- - IF Sys_clk'EVENT AND Sys_clk = '1' THEN - -- Precharge counter - IF Read_precharge (0) = '1' OR Write_precharge (0) = '1' THEN - Count_precharge (0) := Count_precharge (0) + 1; - END IF; - IF Read_precharge (1) = '1' OR Write_precharge (1) = '1' THEN - Count_precharge (1) := Count_precharge (1) + 1; - END IF; - IF Read_precharge (2) = '1' OR Write_precharge (2) = '1' THEN - Count_precharge (2) := Count_precharge (2) + 1; - END IF; - IF Read_precharge (3) = '1' OR Write_precharge (3) = '1' THEN - Count_precharge (3) := Count_precharge (3) + 1; - END IF; - - -- Read with AutoPrecharge Calculation - -- The device start internal precharge when: - -- 1. Meet tRAS requirement - -- 2. BL/2 cycles after command - IF ((Read_precharge(0) = '1') AND (NOW - RAS_chk0 >= tRAS)) THEN - IF ((Burst_length_2 = '1' AND Count_precharge(0) >= 1) OR - (Burst_length_4 = '1' AND Count_precharge(0) >= 2) OR - (Burst_length_8 = '1' AND Count_precharge(0) >= 4)) THEN - Pc_b0 := '1'; - Act_b0 := '0'; - RP_chk0 := NOW; - Read_precharge(0) := '0'; - END IF; - END IF; - IF ((Read_precharge(1) = '1') AND (NOW - RAS_chk1 >= tRAS)) THEN - IF ((Burst_length_2 = '1' AND Count_precharge(1) >= 1) OR - (Burst_length_4 = '1' AND Count_precharge(1) >= 2) OR - (Burst_length_8 = '1' AND Count_precharge(1) >= 4)) THEN - Pc_b1 := '1'; - Act_b1 := '0'; - RP_chk1 := NOW; - Read_precharge(1) := '0'; - END IF; - END IF; - IF ((Read_precharge(2) = '1') AND (NOW - RAS_chk2 >= tRAS)) THEN - IF ((Burst_length_2 = '1' AND Count_precharge(2) >= 1) OR - (Burst_length_4 = '1' AND Count_precharge(2) >= 2) OR - (Burst_length_8 = '1' AND Count_precharge(2) >= 4)) THEN - Pc_b2 := '1'; - Act_b2 := '0'; - RP_chk2 := NOW; - Read_precharge(2) := '0'; - END IF; - END IF; - IF ((Read_precharge(3) = '1') AND (NOW - RAS_chk3 >= tRAS)) THEN - IF ((Burst_length_2 = '1' AND Count_precharge(3) >= 1) OR - (Burst_length_4 = '1' AND Count_precharge(3) >= 2) OR - (Burst_length_8 = '1' AND Count_precharge(3) >= 4)) THEN - Pc_b3 := '1'; - Act_b3 := '0'; - RP_chk3 := NOW; - Read_precharge(3) := '0'; - END IF; - END IF; - - -- Write with AutoPrecharge Calculation - -- The device start internal precharge when: - -- 1. Meet tRAS requirement - -- 2. Two clock after last burst - -- Since tWR is time base, the model will compensate tRP - IF ((Write_precharge(0) = '1') AND (NOW - RAS_chk0 >= tRAS)) THEN - IF ((Burst_length_2 = '1' AND Count_precharge (0) >= 4) OR - (Burst_length_4 = '1' AND Count_precharge (0) >= 5) OR - (Burst_length_8 = '1' AND Count_precharge (0) >= 7)) THEN - Pc_b0 := '1'; - Act_b0 := '0'; - RP_chk0 := NOW - ((2 * tCK) - tWR); - Write_precharge(0) := '0'; - END IF; - END IF; - IF ((Write_precharge(1) = '1') AND (NOW - RAS_chk1 >= tRAS)) THEN - IF ((Burst_length_2 = '1' AND Count_precharge (1) >= 4) OR - (Burst_length_4 = '1' AND Count_precharge (1) >= 5) OR - (Burst_length_8 = '1' AND Count_precharge (1) >= 7)) THEN - Pc_b1 := '1'; - Act_b1 := '0'; - RP_chk1 := NOW - ((2 * tCK) - tWR); - Write_precharge(1) := '0'; - END IF; - END IF; - IF ((Write_precharge(2) = '1') AND (NOW - RAS_chk2 >= tRAS)) THEN - IF ((Burst_length_2 = '1' AND Count_precharge (2) >= 4) OR - (Burst_length_4 = '1' AND Count_precharge (2) >= 5) OR - (Burst_length_8 = '1' AND Count_precharge (2) >= 7)) THEN - Pc_b2 := '1'; - Act_b2 := '0'; - RP_chk2 := NOW - ((2 * tCK) - tWR); - Write_precharge(2) := '0'; - END IF; - END IF; - IF ((Write_precharge(3) = '1') AND (NOW - RAS_chk3 >= tRAS)) THEN - IF ((Burst_length_2 = '1' AND Count_precharge (3) >= 4) OR - (Burst_length_4 = '1' AND Count_precharge (3) >= 5) OR - (Burst_length_8 = '1' AND Count_precharge (3) >= 7)) THEN - Pc_b3 := '1'; - Act_b3 := '0'; - RP_chk3 := NOW - ((2 * tCK) - tWR); - Write_precharge(3) := '0'; - END IF; - END IF; - END IF; - - -- - -- DLL Counter - -- - IF Sys_clk'EVENT AND Sys_clk = '1' THEN - IF (DLL_Reset = '1' AND DLL_done = '0') THEN - DLL_count := DLL_count + 1; - IF (DLL_count >= 200) THEN - DLL_done := '1'; - END IF; - END IF; - END IF; - - -- - -- Control Logic - -- - IF Sys_clk'EVENT AND Sys_clk = '1' THEN - -- Auto Refresh - IF Aref_enable = '1' THEN - -- Auto Refresh to Auto Refresh - ASSERT (NOW - RFC_chk >= tRFC) - REPORT "tRFC violation during Auto Refresh" - SEVERITY WARNING; - - -- Precharge to Auto Refresh - ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND - (NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP)) - REPORT "tRP violation during Auto Refresh" - SEVERITY WARNING; - - -- Precharge to Auto Refresh - ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1') - REPORT "All banks must be Precharge before Auto Refresh" - SEVERITY WARNING; - - -- Record current tRFC time - RFC_chk := NOW; - END IF; - - -- Extended Load Mode Register - IF Ext_mode_enable = '1' THEN - IF (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1') THEN - IF (Addr (0) = '0') THEN - DLL_enable := '1'; - ELSE - DLL_enable := '0'; - END IF; - END IF; - - -- Precharge to EMR - ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1') - REPORT "All bank must be Precharged before Extended Mode Register" - SEVERITY WARNING; - - -- Precharge to EMR - ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND - (NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP)) - REPORT "tRP violation during Extended Load Register" - SEVERITY WARNING; - - -- LMR/EMR to EMR - ASSERT (NOW - MRD_chk >= tMRD) - REPORT "tMRD violation during Extended Mode Register" - SEVERITY WARNING; - - -- Record current tMRD time - MRD_chk := NOW; - END IF; - - -- Load Mode Register - IF Mode_reg_enable = '1' THEN - -- Register mode - Mode_reg <= Addr; - - -- DLL Reset - IF (DLL_enable = '1' AND Addr (8) = '1') THEN - DLL_reset := '1'; - DLL_done := '0'; - DLL_count := 0; - ELSIF (DLL_enable = '1' AND DLL_reset = '0' AND Addr (8) = '0') THEN - ASSERT (FALSE) - REPORT "DLL is ENABLE: DLL RESET is require" - SEVERITY WARNING; - ELSIF (DLL_enable = '0' AND Addr (8) = '1') THEN - ASSERT (FALSE) - REPORT "DLL is DISABLE: DLL RESET will be ignored" - SEVERITY WARNING; - END IF; - - -- Precharge to LMR - ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1') - REPORT "All bank must be Precharged before Load Mode Register" - SEVERITY WARNING; - - -- Precharge to EMR - ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND - (NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP)) - REPORT "tRP violation during Load Mode Register" - SEVERITY WARNING; - - -- LMR/ELMR to LMR - ASSERT (NOW - MRD_chk >= tMRD) - REPORT "tMRD violation during Load Mode Register" - SEVERITY WARNING; - - -- Check for invalid Burst Length - ASSERT ((Addr (2 DOWNTO 0) = "001") OR -- BL = 2 - (Addr (2 DOWNTO 0) = "010") OR -- BL = 4 - (Addr (2 DOWNTO 0) = "011")) -- BL = 8 - REPORT "Invalid Burst Length during Load Mode Register" - SEVERITY WARNING; - - -- Check for invalid CAS Latency - ASSERT ((Addr (6 DOWNTO 4) = "010") OR -- CL = 2.0 - (Addr (6 DOWNTO 4) = "110")) -- CL = 2.5 - REPORT "Invalid CAS Latency during Load Mode Register" - SEVERITY WARNING; - - -- Record current tMRD time - MRD_chk := NOW; - END IF; - - -- Active Block (latch Bank and Row Address) - IF Active_enable = '1' THEN - -- Activate an OPEN bank can corrupt data - ASSERT ((Ba = "00" AND Act_b0 = '0') OR - (Ba = "01" AND Act_b1 = '0') OR - (Ba = "10" AND Act_b2 = '0') OR - (Ba = "11" AND Act_b3 = '0')) - REPORT "Bank is already activated - data can be corrupted" - SEVERITY WARNING; - - -- Activate Bank 0 - IF Ba = "00" AND Pc_b0 = '1' THEN - -- Activate to Activate (same bank) - ASSERT (NOW - RC_chk0 >= tRC) - REPORT "tRC violation during Activate Bank 0" - SEVERITY WARNING; - - -- Precharge to Active - ASSERT (NOW - RP_chk0 >= tRP) - REPORT "tRP violation during Activate Bank 0" - SEVERITY WARNING; - - -- Record Variables for checking violation - Act_b0 := '1'; - Pc_b0 := '0'; - B0_row_addr := Addr; - RC_chk0 := NOW; - RCD_chk0 := NOW; - RAS_chk0 := NOW; - RAP_chk0 := NOW; - END IF; - - -- Activate Bank 1 - IF Ba = "01" AND Pc_b1 = '1' THEN - -- Activate to Activate (same bank) - ASSERT (NOW - RC_chk1 >= tRC) - REPORT "tRC violation during Activate Bank 1" - SEVERITY WARNING; - - -- Precharge to Active - ASSERT (NOW - RP_chk1 >= tRP) - REPORT "tRP violation during Activate Bank 1" - SEVERITY WARNING; - - -- Record Variables for checking violation - Act_b1 := '1'; - Pc_b1 := '0'; - B1_row_addr := Addr; - RC_chk1 := NOW; - RCD_chk1 := NOW; - RAS_chk1 := NOW; - RAP_chk1 := NOW; - END IF; - - -- Activate Bank 2 - IF Ba = "10" AND Pc_b2 = '1' THEN - -- Activate to Activate (same bank) - ASSERT (NOW - RC_chk2 >= tRC) - REPORT "tRC violation during Activate Bank 2" - SEVERITY WARNING; - - -- Precharge to Active - ASSERT (NOW - RP_chk2 >= tRP) - REPORT "tRP violation during Activate Bank 2" - SEVERITY WARNING; - - -- Record Variables for checking violation - Act_b2 := '1'; - Pc_b2 := '0'; - B2_row_addr := Addr; - RC_chk2 := NOW; - RCD_chk2 := NOW; - RAS_chk2 := NOW; - RAP_chk2 := NOW; - END IF; - - -- Activate Bank 3 - IF Ba = "11" AND Pc_b3 = '1' THEN - -- Activate to Activate (same bank) - ASSERT (NOW - RC_chk3 >= tRC) - REPORT "tRC violation during Activate Bank 3" - SEVERITY WARNING; - - -- Precharge to Active - ASSERT (NOW - RP_chk3 >= tRP) - REPORT "tRP violation during Activate Bank 3" - SEVERITY WARNING; - - -- Record Variables for checking violation - Act_b3 := '1'; - Pc_b3 := '0'; - B3_row_addr := Addr; - RC_chk3 := NOW; - RCD_chk3 := NOW; - RAS_chk3 := NOW; - RAP_chk3 := NOW; - END IF; - - -- Activate Bank A to Activate Bank B - IF (Prev_bank /= Ba) THEN - ASSERT (NOW - RRD_chk >= tRRD) - REPORT "tRRD violation during Activate" - SEVERITY WARNING; - END IF; - - -- AutoRefresh to Activate - ASSERT (NOW - RFC_chk >= tRFC) - REPORT "tRFC violation during Activate" - SEVERITY WARNING; - - -- Record Variables for Checking Violation - RRD_chk := NOW; - Prev_bank := Ba; - END IF; - - -- Precharge Block - Consider NOP if bank already precharged or in process of precharging - IF Prech_enable = '1' THEN - -- EMR or LMR to Precharge - ASSERT (NOW - MRD_chk >= tMRD) - REPORT "tMRD violation during Precharge" - SEVERITY WARNING; - - -- Precharge Bank 0 - IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "00")) AND Act_b0 = '1') THEN - Act_b0 := '0'; - Pc_b0 := '1'; - RP_chk0 := NOW; - - -- Activate to Precharge bank 0 - ASSERT (NOW - RAS_chk0 >= tRAS) - REPORT "tRAS violation during Precharge" - SEVERITY WARNING; - - -- tWR violation check for Write - ASSERT (NOW - WR_chk0 >= tWR) - REPORT "tWR violation during Precharge" - SEVERITY WARNING; - END IF; - - -- Precharge Bank 1 - IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "01")) AND Act_b1 = '1') THEN - Act_b1 := '0'; - Pc_b1 := '1'; - RP_chk1 := NOW; - - -- Activate to Precharge - ASSERT (NOW - RAS_chk1 >= tRAS) - REPORT "tRAS violation during Precharge" - SEVERITY WARNING; - - -- tWR violation check for Write - ASSERT (NOW - WR_chk1 >= tWR) - REPORT "tWR violation during Precharge" - SEVERITY WARNING; - END IF; - - -- Precharge Bank 2 - IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "10")) AND Act_b2 = '1') THEN - Act_b2 := '0'; - Pc_b2 := '1'; - RP_chk2 := NOW; - - -- Activate to Precharge - ASSERT (NOW - RAS_chk2 >= tRAS) - REPORT "tRAS violation during Precharge" - SEVERITY WARNING; - - -- tWR violation check for Write - ASSERT (NOW - WR_chk2 >= tWR) - REPORT "tWR violation during Precharge" - SEVERITY WARNING; - END IF; - - -- Precharge Bank 3 - IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "11")) AND Act_b3 = '1') THEN - Act_b3 := '0'; - Pc_b3 := '1'; - RP_chk3 := NOW; - - -- Activate to Precharge - ASSERT (NOW - RAS_chk3 >= tRAS) - REPORT "tRAS violation during Precharge" - SEVERITY WARNING; - - -- tWR violation check for Write - ASSERT (NOW - WR_chk3 >= tWR) - REPORT "tWR violation during Precharge" - SEVERITY WARNING; - END IF; - - -- Pipeline for READ - IF CAS_latency_15 = '1' THEN - A10_precharge (3) := Addr(10); - Bank_precharge (3) := Ba; - Cmnd_precharge (3) := '1'; - ELSIF CAS_latency_2 = '1' THEN - A10_precharge (4) := Addr(10); - Bank_precharge (4) := Ba; - Cmnd_precharge (4) := '1'; - ELSIF CAS_latency_25 = '1' THEN - A10_precharge (5) := Addr(10); - Bank_precharge (5) := Ba; - Cmnd_precharge (5) := '1'; - ELSIF CAS_latency_3 = '1' THEN - A10_precharge (6) := Addr(10); - Bank_precharge (6) := Ba; - Cmnd_precharge (6) := '1'; - ELSIF CAS_latency_4 = '1' THEN - A10_precharge (8) := Addr(10); - Bank_precharge (8) := Ba; - Cmnd_precharge (8) := '1'; - END IF; - END IF; - - -- Burst Terminate - IF Burst_term = '1' THEN - -- Pipeline for Read - IF CAS_latency_15 = '1' THEN - Cmnd_bst (3) := '1'; - ELSIF CAS_latency_2 = '1' THEN - Cmnd_bst (4) := '1'; - ELSIF CAS_latency_25 = '1' THEN - Cmnd_bst (5) := '1'; - ELSIF CAS_latency_3 = '1' THEN - Cmnd_bst (6) := '1'; - ELSIF CAS_latency_4 = '1' THEN - Cmnd_bst (8) := '1'; - END IF; - - -- Terminate Write - ASSERT (Data_in_enable = '0') - REPORT "It's illegal to Burst Terminate a Write" - SEVERITY WARNING; - - -- Terminate Read with Auto Precharge - ASSERT (Read_precharge (0) = '0' AND Read_precharge (1) = '0' AND - Read_precharge (2) = '0' AND Read_precharge (3) = '0') - REPORT "It's illegal to Burst Terminate a Read with Auto Precharge" - SEVERITY WARNING; - END IF; - - -- Read Command - IF Read_enable = '1' THEN - -- CAS Latency Pipeline - IF Cas_latency_15 = '1' THEN - Read_cmnd (3) := '1'; - Read_bank (3) := Ba; - Read_cols (3) := Addr (8 DOWNTO 0); - ELSIF Cas_latency_2 = '1' THEN - Read_cmnd (4) := '1'; - Read_bank (4) := Ba; - Read_cols (4) := Addr (8 DOWNTO 0); - ELSIF Cas_latency_25 = '1' THEN - Read_cmnd (5) := '1'; - Read_bank (5) := Ba; - Read_cols (5) := Addr (8 DOWNTO 0); - ELSIF Cas_latency_3 = '1' THEN - Read_cmnd (6) := '1'; - Read_bank (6) := Ba; - Read_cols (6) := Addr (8 DOWNTO 0); - ELSIF Cas_latency_4 = '1' THEN - Read_cmnd (8) := '1'; - Read_bank (8) := Ba; - Read_cols (8) := Addr (8 DOWNTO 0); - END IF; - - -- Write to Read: Terminate Write Immediately - IF Data_in_enable = '1' THEN - Data_in_enable := '0'; - END IF; - - -- Interrupting a Read with Auto Precharge (same bank only) - ASSERT (Read_precharge(CONV_INTEGER(Ba)) = '0') - REPORT "It's illegal to interrupt a Read with Auto Precharge" - SEVERITY WARNING; - - -- Activate to Read - ASSERT ((Ba = "00" AND Act_b0 = '1') OR - (Ba = "01" AND Act_b1 = '1') OR - (Ba = "10" AND Act_b2 = '1') OR - (Ba = "11" AND Act_b3 = '1')) - REPORT "Bank is not Activated for Read" - SEVERITY WARNING; - - -- Activate to Read without Auto Precharge - IF Addr (10) = '0' THEN - ASSERT ((Ba = "00" AND NOW - RCD_chk0 >= tRCD) OR - (Ba = "01" AND NOW - RCD_chk1 >= tRCD) OR - (Ba = "10" AND NOW - RCD_chk2 >= tRCD) OR - (Ba = "11" AND NOW - RCD_chk3 >= tRCD)) - REPORT "tRCD violation during Read" - SEVERITY WARNING; - END IF; - - -- Activate to Read with Auto Precharge - IF Addr (10) = '1' THEN - ASSERT ((Ba = "00" AND NOW - RAP_chk0 >= tRAP) OR - (Ba = "01" AND NOW - RAP_chk1 >= tRAP) OR - (Ba = "10" AND NOW - RAP_chk2 >= tRAP) OR - (Ba = "11" AND NOW - RAP_chk3 >= tRAP)) - REPORT "tRAP violation during Read" - SEVERITY WARNING; - END IF; - - -- Auto precharge - IF Addr (10) = '1' THEN - Read_precharge (Conv_INTEGER(Ba)) := '1'; - Count_precharge (Conv_INTEGER(Ba)) := 0; - END IF; - - -- DLL Check - IF (DLL_reset = '1') THEN - ASSERT (DLL_done = '1') - REPORT "DLL RESET not complete" - SEVERITY WARNING; - END IF; - END IF; - - -- Write Command - IF Write_enable = '1' THEN - -- Pipeline for Write - Write_cmnd (2) := '1'; - Write_bank (2) := Ba; - Write_cols (2) := Addr (8 DOWNTO 0); - - -- Interrupting a Write with Auto Precharge (same bank only) - ASSERT (Write_precharge(CONV_INTEGER(Ba)) = '0') - REPORT "It's illegal to interrupt a Write with Auto Precharge" - SEVERITY WARNING; - - -- Activate to Write - ASSERT ((Ba = "00" AND Act_b0 = '1') OR - (Ba = "01" AND Act_b1 = '1') OR - (Ba = "10" AND Act_b2 = '1') OR - (Ba = "11" AND Act_b3 = '1')) - REPORT "Bank is not Activated for Write" - SEVERITY WARNING; - - -- Activate to Write - ASSERT ((Ba = "00" AND NOW - RCD_chk0 >= tRCD) OR - (Ba = "01" AND NOW - RCD_chk1 >= tRCD) OR - (Ba = "10" AND NOW - RCD_chk2 >= tRCD) OR - (Ba = "11" AND NOW - RCD_chk3 >= tRCD)) - REPORT "tRCD violation during Write" - SEVERITY WARNING; - - -- Auto precharge - IF Addr (10) = '1' THEN - Write_precharge (Conv_INTEGER(Ba)) := '1'; - Count_precharge (Conv_INTEGER(Ba)) := 0; - END IF; - END IF; - END IF; - END PROCESS; - - -- - -- Dqs Receiver - -- - dqs_rcvrs : PROCESS - VARIABLE Dm_temp : STD_LOGIC_VECTOR (1 DOWNTO 0); - VARIABLE Dq_temp : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0); - BEGIN - WAIT ON Dqs; - -- Latch data at posedge Dqs - IF Dqs'EVENT AND Dqs (1) = '1' AND Dqs (0) = '1' THEN - Dq_temp := Dq; - Dm_temp := Dm; - END IF; - -- Latch data at negedge Dqs - IF Dqs'EVENT AND Dqs (1) = '0' AND Dqs (0) = '0' THEN - Dq_pair <= (Dq & Dq_temp); - Dm_pair <= (Dm & Dm_temp); - END IF; - END PROCESS; - - -- - -- Setup timing checks - -- - Setup_check : PROCESS - BEGIN - WAIT ON Sys_clk; - IF Sys_clk'EVENT AND Sys_clk = '1' THEN - ASSERT(Cke'LAST_EVENT >= tIS) - REPORT "CKE Setup time violation -- tIS" - SEVERITY WARNING; - ASSERT(Cs_n'LAST_EVENT >= tIS) - REPORT "CS# Setup time violation -- tIS" - SEVERITY WARNING; - ASSERT(Cas_n'LAST_EVENT >= tIS) - REPORT "CAS# Setup time violation -- tIS" - SEVERITY WARNING; - ASSERT(Ras_n'LAST_EVENT >= tIS) - REPORT "RAS# Setup time violation -- tIS" - SEVERITY WARNING; - ASSERT(We_n'LAST_EVENT >= tIS) - REPORT "WE# Setup time violation -- tIS" - SEVERITY WARNING; - ASSERT(Addr'LAST_EVENT >= tIS) - REPORT "ADDR Setup time violation -- tIS" - SEVERITY WARNING; - ASSERT(Ba'LAST_EVENT >= tIS) - REPORT "BA Setup time violation -- tIS" - SEVERITY WARNING; - END IF; - END PROCESS; - - -- - -- Hold timing checks - -- - Hold_check : PROCESS - BEGIN - WAIT ON Sys_clk'DELAYED (tIH); - IF Sys_clk'DELAYED (tIH) = '1' THEN - ASSERT(Cke'LAST_EVENT >= tIH) - REPORT "CKE Hold time violation -- tIH" - SEVERITY WARNING; - ASSERT(Cs_n'LAST_EVENT >= tIH) - REPORT "CS# Hold time violation -- tIH" - SEVERITY WARNING; - ASSERT(Cas_n'LAST_EVENT >= tIH) - REPORT "CAS# Hold time violation -- tIH" - SEVERITY WARNING; - ASSERT(Ras_n'LAST_EVENT >= tIH) - REPORT "RAS# Hold time violation -- tIH" - SEVERITY WARNING; - ASSERT(We_n'LAST_EVENT >= tIH) - REPORT "WE# Hold time violation -- tIH" - SEVERITY WARNING; - ASSERT(Addr'LAST_EVENT >= tIH) - REPORT "ADDR Hold time violation -- tIH" - SEVERITY WARNING; - ASSERT(Ba'LAST_EVENT >= tIH) - REPORT "BA Hold time violation -- tIH" - SEVERITY WARNING; - END IF; - END PROCESS; - -END behave; diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd deleted file mode 100644 index ae38d48..0000000 --- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd +++ /dev/null @@ -1,290 +0,0 @@ -------------------------------------------------------------------------- --- Project: SDRAM controller --- This file: SDRAM command controller --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.sdram_config.all; -use work.sdram_types.all; - -entity sdram_cmd is - Generic - ( - f_sdrclk : real := 100.0; - BL : natural := 2 - ); - Port - ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - enable : in STD_LOGIC; - u_tag_in : in user_tag_t; - u_tag_out : out user_tag_t; - phy_ctrl : out phy_ctrl_t; - cmd : in sdr_cmd_t; - cmd_we : in STD_LOGIC; - cmd_ack : out STD_LOGIC; - col_addr : in col_addr_t; - mode_word : in mode_word_t; - sdr_cmd_ctrl : out sdr_cmd_lines_t; - sdr_addr : out sdr_addr_t; - sdr_ba : out sdr_ba_t - ); -end sdram_cmd; - -architecture behaviour of sdram_cmd is - - signal st_sdr, st_sdr_next : sdr_state_t; - - signal cc_preset : natural range 0 to 15; - signal cc_load_en : std_logic; - signal cycle_finished : std_logic; - - signal burst_preset : natural range 0 to 3; - signal burst_load_en : std_logic; - signal burst_finished : std_logic; - - subtype cycle_cnt_t is natural range 0 to 15; - - type part_timing_array_t is array (sdr_cmd_t) of cycle_cnt_t; - constant TIMING : part_timing_array_t := - -- command cycle_cnt - ( SD_DESELECT => (0 ), - SD_NOP => (0 ), - SD_LMR => (TMRD-1 ), - SD_ACT => (to_cycles(TRCD, f_sdrclk)-1), - SD_READ => (TCAS-1 ), - SD_WRITE => (to_cycles(TWR, f_sdrclk)-1), - SD_PRE => (to_cycles(TRP, f_sdrclk)-1), - SD_BST => (0 ), - SD_AR => (to_cycles(TRFC, f_sdrclk)-1), - SD_SR => (to_cycles(TRFC, f_sdrclk)-1) - ); - -begin - - u_tag_out <= u_tag_in; - ------------------------------------------------------------------------------------------- - -fsm_sdr_state: - process (st_sdr, cmd, cmd_we, cycle_finished, burst_finished, mode_word, enable, col_addr) - begin - st_sdr_next <= st_sdr; - sdr_cmd_ctrl <= COMMAND(SD_NOP); - - cc_load_en <= '0'; - cc_preset <= TIMING(cmd); - burst_load_en <= '0'; - cmd_ack <= '0'; - burst_preset <= BL/2-1; - phy_ctrl.re <= '0'; - phy_ctrl.drive_en <= '0'; - phy_ctrl.we <= '0'; - phy_ctrl.utag_we <= '0'; - sdr_addr <= mode_word(sdr_addr_t'left downto sdr_addr_t'right); - sdr_ba <= mode_word(mode_word_t'left downto mode_word_t'left-1); - - case st_sdr is - when PWR_DOWN => - sdr_cmd_ctrl <= COMMAND(SD_DESELECT); - if enable = '1' then - st_sdr_next <= IDLE; - end if; - - when PRECHARGE => - if cycle_finished = '1' then - st_sdr_next <= IDLE; - end if; - - when MODE => - if cycle_finished = '1' then - st_sdr_next <= IDLE; - end if; - - when IDLE => - if cmd_we = '1' then - cmd_ack <= '1'; - cc_load_en <= '1'; - cc_preset <= TIMING(cmd); - sdr_cmd_ctrl <= COMMAND(cmd); - case cmd is - when SD_PRE => - st_sdr_next <= PRECHARGE; - when SD_LMR => - st_sdr_next <= MODE; - when SD_ACT => - st_sdr_next <= ROW_ACT; - when SD_AR => - st_sdr_next <= AUTO_REF; - when others => null; - end case; - end if; - - when ROW_ACT => - if cycle_finished = '1' then - if cmd_we = '1' then - cmd_ack <= '1'; - burst_load_en <= '1'; - cc_load_en <= '1'; - cc_preset <= TIMING(cmd); - sdr_cmd_ctrl <= COMMAND(cmd); - case cmd is - when SD_PRE => - st_sdr_next <= PRECHARGE; - when SD_READ => - phy_ctrl.utag_we <= '1'; - st_sdr_next <= READ; - sdr_addr(col_addr_t'range) <= col_addr; - when SD_WRITE => - phy_ctrl.utag_we <= '1'; - phy_ctrl.drive_en <= '1'; - st_sdr_next <= WRITE; - sdr_addr(col_addr_t'range) <= col_addr; - when others => null; - end case; - end if; - end if; - - when WRITE => - phy_ctrl.drive_en <= '1'; - phy_ctrl.we <= '1'; - if burst_finished = '1' then - if cmd_we = '1' and cmd = SD_WRITE then - sdr_addr(col_addr_t'range) <= col_addr; - cmd_ack <= '1'; - burst_load_en <= '1'; - sdr_cmd_ctrl <= COMMAND(cmd); - phy_ctrl.utag_we <= '1'; - else - phy_ctrl.drive_en <= '0'; - cc_load_en <= '1'; - cc_preset <= TIMING(SD_WRITE)+1; - st_sdr_next <= ROW_ACT; - end if; - end if; - - when READ => - phy_ctrl.re <= '1'; - if burst_finished = '1' then - if cmd_we = '1' and cmd = SD_READ then - sdr_addr(col_addr_t'range) <= col_addr; - cmd_ack <= '1'; - burst_load_en <= '1'; - sdr_cmd_ctrl <= COMMAND(cmd); - phy_ctrl.utag_we <= '1'; - else - cc_load_en <= '1'; - cc_preset <= TIMING(SD_READ); - st_sdr_next <= ROW_ACT; - end if; - end if; - - when WRITE_A => -- not implemented yet - cmd_ack <= '1'; - st_sdr_next <= IDLE; - - when READ_A => -- not implemented yet - cmd_ack <= '1'; - st_sdr_next <= IDLE; - - when BURST_STOP => -- not implemented yet - cmd_ack <= '1'; - st_sdr_next <= IDLE; - - when SELF_REF => -- not implemented yet - cmd_ack <= '1'; - st_sdr_next <= IDLE; - - when PRE_PWR_DOWN => -- not implemented yet - cmd_ack <= '1'; - st_sdr_next <= IDLE; - - when ACT_PWR_DOWN => -- not implemented yet - cmd_ack <= '1'; - st_sdr_next <= IDLE; - - when AUTO_REF => - if cycle_finished = '1' then - st_sdr_next <= IDLE; - end if; - - when others => - st_sdr_next <= IDLE; - end case; - - end process; - -fsm_sdr_state_next: - process (rst, clk) - begin - if rst = '1' then - st_sdr <= PWR_DOWN; - elsif rising_edge(clk) then - st_sdr <= st_sdr_next; - end if; - end process; - ------------------------------------------------------------------------------------------- -cycle_counter: - process (rst, clk) - variable cycle_cnt : natural range 0 to 15; - begin - if rst = '1' then - cycle_cnt := 0; - cycle_finished <= '0'; - elsif rising_edge(clk) then - cycle_finished <= '0'; - if cc_load_en = '1' then - cycle_cnt := cc_preset; - elsif cycle_cnt /= 0 then - cycle_cnt := cycle_cnt - 1; - else - cycle_finished <= '1'; - end if; - end if; - end process; - ------------------------------------------------------------------------------------------- -burst_counter: - process (rst, clk) - variable burst_cnt : natural range 0 to 3; - begin - if rst = '1' then - burst_cnt := 0; - elsif rising_edge(clk) then - burst_finished <= '0'; - if burst_load_en = '1' then - burst_cnt := burst_preset; - elsif burst_cnt /= 0 then - burst_cnt := burst_cnt - 1; - end if; - if burst_cnt = 0 then - burst_finished <= '1'; - end if; - end if; - end process; - ------------------------------------------------------------------------------------------- -end behaviour; diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_config.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_config.vhd deleted file mode 100644 index 534232b..0000000 --- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_config.vhd +++ /dev/null @@ -1,74 +0,0 @@ -------------------------------------------------------------------------- --- Project: SDRAM controller --- This file: User SDRAM component adjustments --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -package sdram_config is - - constant DDR_DATA_WIDTH : positive := 32; -- External DDR-SDRAM Module data bus width - constant DDR_ADDR_WIDTH : positive := 13; -- number of address lines to DDR-SDRAM Device/Module - constant DDR_BANK_WIDTH : positive := 2; -- Number of BANK address lines of external DDR-SDRAM - constant DDR_ROW_ADDR_WIDTH : positive := 13; -- - constant DDR_COL_ADDR_WIDTH : positive := 9; -- - - constant LMR_REG_BASE : natural := 0; - constant LMR_REG_EXTENDED : natural := 1; - constant LMR_OP_NORMAL : natural := 0; - constant LMR_OP_RES_DLL : natural := 2; - constant LMR_BT_SEQ : natural := 0; - constant LMR_BT_ILVD : natural := 1; - constant LMR_BL2 : natural := 1; - constant LMR_BL4 : natural := 2; - constant LMR_BL8 : natural := 3; - constant LMR_CL2 : natural := 2; - constant LMR_CL3 : natural := 3; - constant LMR_CL2_5 : natural := 6; - - -- DDR SDRAM Hardware defined constants - constant BIT_AUTO_PRE : positive := 10; -- bit-position in column address for auto precharge (see Data Sheet) - constant BIT_PRE_ALL : positive := 10; -- bit-position in column address for precharge all (see Data Sheet) - constant ENABLE_PRE_ALL : std_logic := '1'; - constant ENABLE_AUTO_PRE : std_logic := '0'; - - -- DDR-SDR TIMING constants ------------------------------------------------------------------ - -- After REFRESH_CLOCKS a refresh cycle is necessary, 64ms / 8192 = max every 7.8125 us refesh - constant REFRESH_INTERVAL : real := 7.8125E3; -- [ns] - - -- These values are for your SDRAM part (see datasheet) - constant TCAS : positive := 2; -- CAS latency [clocks] - constant TRP : real := 20.0; -- precharge command period [ns] - constant TRAS : real := 45.0; -- active to precharge delay [ns] - constant TRFC : real := 75.0; -- auto refresh command period [ns] - constant TMRD : positive := 2; -- load mode register command cylce time [clocks] - constant TRCD : real := 20.0; -- active to read or write delay [ns] - constant TWR : real := 15.0; -- write recovery time [ns] - - constant PWR_UP_WAIT : real := 1.0E3; -- [ns] - - subtype user_tag_t is unsigned(3 downto 0); - - ---------------------------------------------------------------------------------------------- - -end sdram_config; diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd deleted file mode 100644 index d812b1c..0000000 --- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd +++ /dev/null @@ -1,491 +0,0 @@ -------------------------------------------------------------------------- --- Project: SDRAM controller --- This file: SDRAM main controller and user I/F --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.sdram_config.all; -use work.sdram_types.all; -use work.utils_pkg.all; - -entity sdram_ctrl is - Generic - ( - f_sysclk : real := 100.0; - BL : natural := 2 - ); - Port ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - u_busy : out STD_LOGIC; - u_tag_in : in user_tag_t; - u_tag_out : out user_tag_t; - u_addr : in user_addr_t; - u_cmd : in user_cmd_t; - u_cmd_we : in STD_LOGIC; - col_addr : out col_addr_t; - sdr_cmd_busy : in STD_LOGIC; - sdr_cmd : out sdr_cmd_t; - sdr_cmd_we : out STD_LOGIC; - sdr_mode : out mode_word_t; - sdr_cke : out STD_LOGIC - ); -end sdram_ctrl; - -architecture behaviour of sdram_ctrl is - - constant LMR_BURST_LEN : natural := NextExpBaseTwo(BL); - - type ctrl_state_t is (RESET, POWER_WAIT, INIT, INIT_WAIT, USER_READY, USER_WRITE_PRE, USER_WRITE_ACT, USER_WRITE, USER_READ_PRE, USER_READ_ACT, USER_READ, REFRESH_PRE, REFRESH); - signal st_ctrl, st_ctrl_next : ctrl_state_t; - - constant PWR_UP_CLOCK_INTERVAL : natural := to_cycles(PWR_UP_WAIT, f_sysclk); - signal pwr_up_cnt : natural range 0 to PWR_UP_CLOCK_INTERVAL-1; - signal pwr_up_cnt_rst : std_logic; - signal pwr_up_finished : std_logic; - - signal cycle_cnt : natural range 0 to 255; - signal cc_preset : natural range 0 to 255; - signal cc_load_en : std_logic; - signal cycle_finished : std_logic; - - signal seq_cnt : natural range 0 to 31; - signal seq_rst_en : std_logic; - signal seq_cnt_en : std_logic; - - constant REFRESH_CLOCK_INTERVAL : natural := to_cycles(REFRESH_INTERVAL, f_sysclk); - signal refresh_cnt : natural range 0 to REFRESH_CLOCK_INTERVAL-1; - signal refresh_request : std_logic; - signal refresh_cnt_rst : std_logic; - - signal addr_reg_load_en : std_logic; - - signal u_tag_reg : user_tag_t; - signal bank_addr_reg : bank_addr_t; - signal row_addr_reg : row_addr_t; - signal col_addr_reg : col_addr_t; - signal bank_addr_last : bank_addr_t; - signal row_addr_last : row_addr_t; - signal col_addr_last : col_addr_t; - - signal u_bank_addr : bank_addr_t; - signal u_row_addr : row_addr_t; - signal u_col_addr : col_addr_t; - - signal bank_active_reg : unsigned(0 to 3); - signal bank_is_active : std_logic; - signal bank_activate : std_logic; - signal bank_clr : std_logic; - - type init_seq_rom_t is array (0 to 14) of init_seq_t; - - constant init_seq_rom : init_seq_rom_t := - ( - ( - cmd => SD_NOP, - mode_word => (others => '0'), - wait_cycle => 0 - ), - ( - cmd => SD_PRE, - mode_word => "000010000000000", - wait_cycle => 0 - ), - ( - cmd => SD_NOP, - mode_word => (others => '0'), - wait_cycle => 0 - ), - ( - cmd => SD_LMR, - mode_word => to_unsigned(LMR_REG_EXTENDED, 2) & "0000000000010", - wait_cycle => 0 - ), - ( - cmd => SD_NOP, - mode_word => (others => '0'), - wait_cycle => 0 - ), - ( - cmd => SD_LMR, - mode_word => to_unsigned(LMR_REG_BASE, 2) & to_unsigned(LMR_OP_RES_DLL, 6) & to_unsigned(LMR_CL2, 3) & '0' & to_unsigned(LMR_BURST_LEN, 3), - wait_cycle => 200 - ), - ( - cmd => SD_NOP, - mode_word => (others => '0'), - wait_cycle => 0 - ), - ( - cmd => SD_PRE, - mode_word => "000010000000000", - wait_cycle => 0 - ), - ( - cmd => SD_NOP, - mode_word => (others => '0'), - wait_cycle => 0 - ), - ( - cmd => SD_AR, - mode_word => (others => '0'), - wait_cycle => 0 - ), - ( - cmd => SD_NOP, - mode_word => (others => '0'), - wait_cycle => 0 - ), - ( - cmd => SD_AR, - mode_word => (others => '0'), - wait_cycle => 0 - ), - ( - cmd => SD_NOP, - mode_word => (others => '0'), - wait_cycle => 0 - ), - ( - cmd => SD_LMR, - mode_word => to_unsigned(LMR_REG_BASE, 2) & to_unsigned(LMR_OP_NORMAL, 6) & to_unsigned(LMR_CL2, 3) & '0' & to_unsigned(LMR_BURST_LEN, 3), - wait_cycle => 200 - ), - ( - cmd => SD_NOP, - mode_word => (others => '0'), - wait_cycle => 0 - ) - - ); - -begin - - u_row_addr <= u_addr(user_addr_t'left downto user_addr_t'left-row_addr_t'length+1); - u_bank_addr <= u_addr(user_addr_t'left-row_addr_t'length downto user_addr_t'left-row_addr_t'length-bank_addr_t'length+1); - u_col_addr <= u_addr(user_addr_t'left-row_addr_t'length-bank_addr_t'length downto 0); - bank_is_active <= bank_active_reg(to_integer(u_bank_addr)); - ------------------------------------------------------------------------------------------- -fsm_ctrl_state: - process (st_ctrl, u_tag_in, u_tag_reg, u_cmd, u_cmd_we, sdr_cmd_busy, pwr_up_finished, seq_cnt, cycle_finished, u_bank_addr, u_row_addr, bank_addr_reg, row_addr_reg, u_col_addr, col_addr_reg, bank_addr_last, row_addr_last, refresh_request, bank_is_active) - begin - - u_busy <= '1'; - pwr_up_cnt_rst <= '0'; - cc_preset <= init_seq_rom(seq_cnt).wait_cycle; - cc_load_en <= '0'; - sdr_cmd <= init_seq_rom(seq_cnt).cmd; - sdr_cmd_we <= '0'; - sdr_mode <= bank_addr_reg & row_addr_reg; - col_addr <= col_addr_reg; - sdr_cke <= '1'; - seq_cnt_en <= '0'; - seq_rst_en <= '0'; - addr_reg_load_en <= '0'; - refresh_cnt_rst <= '0'; - bank_activate <= '0'; - bank_clr <= '0'; - u_tag_out <= u_tag_reg; - - st_ctrl_next <= st_ctrl; - case st_ctrl is - when RESET => - sdr_cke <= '0'; - pwr_up_cnt_rst <= '1'; - st_ctrl_next <= POWER_WAIT; - - when POWER_WAIT => - sdr_cke <= '0'; - if pwr_up_finished = '1' then - seq_rst_en <= '1'; - st_ctrl_next <= INIT; - end if; - - when INIT => - sdr_mode <= init_seq_rom(seq_cnt).mode_word; - sdr_cmd <= init_seq_rom(seq_cnt).cmd; - cc_preset <= init_seq_rom(seq_cnt).wait_cycle; - if seq_cnt = init_seq_rom_t'high then - bank_clr <= '1'; - refresh_cnt_rst <= '1'; - st_ctrl_next <= USER_READY; - elsif sdr_cmd_busy = '0' then - cc_load_en <= '1'; - sdr_cmd_we <= '1'; - st_ctrl_next <= INIT_WAIT; - end if; - - when INIT_WAIT => - if sdr_cmd_busy = '0' and cycle_finished = '1' then - seq_cnt_en <= '1'; - st_ctrl_next <= INIT; - end if; - - when USER_READY => - if refresh_request = '1' then - st_ctrl_next <= REFRESH_PRE; - else - u_busy <= '0'; - col_addr <= u_col_addr; - u_tag_out <= u_tag_in; - sdr_mode <= u_bank_addr & u_row_addr; - sdr_mode(BIT_AUTO_PRE) <= ENABLE_AUTO_PRE; - if u_cmd_we = '1' then - addr_reg_load_en <= '1'; - case u_cmd is - when UCMD_NOP => - sdr_cmd <= SD_NOP; - when UCMD_LMR => - sdr_cmd <= SD_NOP; - when UCMD_WRITE => - sdr_cmd <= SD_WRITE; - if (u_row_addr /= row_addr_reg) then - st_ctrl_next <= USER_WRITE_PRE; - elsif bank_is_active = '0' then - st_ctrl_next <= USER_WRITE_ACT; - elsif sdr_cmd_busy = '1' then - st_ctrl_next <= USER_WRITE; - else - sdr_cmd_we <= '1'; - end if; - when UCMD_READ => - sdr_cmd <= SD_READ; - if (u_row_addr /= row_addr_reg) then - st_ctrl_next <= USER_READ_PRE; - elsif bank_is_active = '0' then - st_ctrl_next <= USER_READ_ACT; - elsif sdr_cmd_busy = '1' then - st_ctrl_next <= USER_READ; - else - sdr_cmd_we <= '1'; - end if; - when others => null; - end case; - end if; - end if; - - when USER_WRITE_PRE => - bank_clr <= '1'; - sdr_cmd <= SD_PRE; - sdr_mode <= bank_addr_last & row_addr_last; - sdr_mode(BIT_PRE_ALL) <= ENABLE_PRE_ALL; - if sdr_cmd_busy = '0' then - sdr_cmd_we <= '1'; - st_ctrl_next <= USER_WRITE_ACT; - end if; - - when USER_WRITE_ACT => - bank_activate <= '1'; - sdr_cmd <= SD_ACT; - if sdr_cmd_busy = '0' then - sdr_cmd_we <= '1'; - st_ctrl_next <= USER_WRITE; - end if; - - when USER_WRITE => - sdr_cmd <= SD_WRITE; - sdr_mode(BIT_AUTO_PRE) <= ENABLE_AUTO_PRE; - if sdr_cmd_busy = '0' then - sdr_cmd_we <= '1'; - st_ctrl_next <= USER_READY; - end if; - - when USER_READ_PRE => - bank_clr <= '1'; - sdr_cmd <= SD_PRE; - sdr_mode <= bank_addr_last & row_addr_last; - sdr_mode(BIT_PRE_ALL) <= ENABLE_PRE_ALL; - if sdr_cmd_busy = '0' then - sdr_cmd_we <= '1'; - st_ctrl_next <= USER_READ_ACT; - end if; - - when USER_READ_ACT => - bank_activate <= '1'; - sdr_cmd <= SD_ACT; - if sdr_cmd_busy = '0' then - sdr_cmd_we <= '1'; - st_ctrl_next <= USER_READ; - end if; - - when USER_READ => - sdr_cmd <= SD_READ; - sdr_mode(BIT_AUTO_PRE) <= ENABLE_AUTO_PRE; - if sdr_cmd_busy = '0' then - sdr_cmd_we <= '1'; - st_ctrl_next <= USER_READY; - end if; - - when REFRESH_PRE => - bank_clr <= '1'; - sdr_cmd <= SD_PRE; --- sdr_mode <= bank_addr_last & row_addr_last; - sdr_mode(BIT_PRE_ALL) <= ENABLE_PRE_ALL; - if sdr_cmd_busy = '0' then - sdr_cmd_we <= '1'; - st_ctrl_next <= REFRESH; - end if; - - when REFRESH => - sdr_cmd <= SD_AR; - if sdr_cmd_busy = '0' then - sdr_cmd_we <= '1'; - st_ctrl_next <= USER_READY; - refresh_cnt_rst <= '1'; - end if; - - when others => - st_ctrl_next <= RESET; - end case; - - end process; - -fsm_ctrl_state_next: - process (rst, clk) - begin - if rst = '1' then - st_ctrl <= RESET; - elsif rising_edge(clk) then - st_ctrl <= st_ctrl_next; - end if; - end process; - ------------------------------------------------------------------------------------------- -bank_active_register: - process (clk) - begin - if rising_edge(clk) then - if bank_clr = '1' then - bank_active_reg <= (others => '0'); -- assumes PRE_ALL !!!!!!!!!!!!! - elsif bank_activate = '1' then - bank_active_reg(to_integer(bank_addr_reg)) <= '1'; - end if; - end if; - end process; - - ------------------------------------------------------------------------------------------- -user_addr_register: - process (rst, clk) - begin - if rst = '1' then - bank_addr_reg <= (others => '0'); - row_addr_reg <= (others => '0'); - col_addr_reg <= (others => '0'); - u_tag_reg <= (others => '0'); - elsif rising_edge(clk) then - if addr_reg_load_en = '1' then - bank_addr_last <= bank_addr_reg; - row_addr_last <= row_addr_reg; - col_addr_last <= col_addr_reg; - bank_addr_reg <= u_bank_addr; - row_addr_reg <= u_row_addr; - col_addr_reg <= u_col_addr; - u_tag_reg <= u_tag_in; - end if; - end if; - end process; - ------------------------------------------------------------------------------------------- -power_up_counter: - process (rst, clk) - begin - if rst = '1' then - pwr_up_cnt <= 0; - pwr_up_finished <= '0'; - elsif rising_edge(clk) then - pwr_up_finished <= '0'; - if pwr_up_cnt_rst = '1' then - pwr_up_cnt <= PWR_UP_CLOCK_INTERVAL-1; - else - if pwr_up_cnt /= 0 then - pwr_up_cnt <= pwr_up_cnt - 1; - else - pwr_up_finished <= '1'; - end if; - end if; - end if; - end process; - - ------------------------------------------------------------------------------------------- -refresh_counter: - process (rst, clk) - begin - if rst = '1' then - refresh_cnt <= 0; - refresh_request <= '0'; - elsif rising_edge(clk) then - refresh_request <= '0'; - if refresh_cnt_rst = '1' then - refresh_cnt <= REFRESH_CLOCK_INTERVAL-1; - else - if refresh_cnt /= 0 then - refresh_cnt <= refresh_cnt - 1; - else - refresh_request <= '1'; - end if; - end if; - end if; - end process; - ------------------------------------------------------------------------------------------- -cycle_counter: - process (rst, clk) - begin - if rst = '1' then - cycle_cnt <= 0; - cycle_finished <= '0'; - elsif rising_edge(clk) then - cycle_finished <= '0'; - if cc_load_en = '1' then - cycle_cnt <= cc_preset; - elsif cycle_cnt /= 0 then - cycle_cnt <= cycle_cnt - 1; - else - cycle_finished <= '1'; - end if; - end if; - end process; - ------------------------------------------------------------------------------------------- -seq_counter: - process (rst, clk) - begin - if rst = '1' then - seq_cnt <= 0; - elsif rising_edge(clk) then - if seq_rst_en = '1' then - seq_cnt <= 0; - elsif seq_cnt_en = '1' then - if seq_cnt /= init_seq_rom_t'high then - seq_cnt <= seq_cnt + 1; - end if; - end if; - end if; - end process; - ------------------------------------------------------------------------------------------- -end behaviour; diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd deleted file mode 100644 index 5d997c3..0000000 --- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd +++ /dev/null @@ -1,278 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: cpu_embedded using cpu_core and rom --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.fifo_ctrl_pkg.all; -use work.sdram_config.all; -use work.sdram_types.all; - -entity sdram_ctrl_frontend64_wb is - Generic - ( - BL : natural := 2; - f_sysclk : real := 100.0; - f_sdrclk : real := 100.0; - fifo_depth : integer := 4 - ); - Port - ( - RST_I : in STD_LOGIC; - CLK_I : in STD_LOGIC; - SDRAM_CLK0_I : in STD_LOGIC; - SDRAM_CLK270_I : in STD_LOGIC; - SDRAM_CLK270VAR_I : in STD_LOGIC; - - CYC_I : in STD_LOGIC; - STB_I : in STD_LOGIC; - SEL_I : in unsigned(SDR_DM_WIDTH-1 downto 0); - WE_I : in STD_LOGIC; - ACK_O : out STD_LOGIC; - MRDY_I : in STD_LOGIC; - SRDY_O : out STD_LOGIC; - ADDR_I : in unsigned(31 downto 0); - DAT_I : in unsigned(SDR_DATA_WIDTH-1 downto 0); - DAT_O : out unsigned(SDR_DATA_WIDTH-1 downto 0); - - -- SDRAM signals - sd_clk_p : out STD_LOGIC; - sd_clk_n : out STD_LOGIC; - sd_cke : out STD_LOGIC; - sd_cs_n : out STD_LOGIC; - sd_cas_n : out STD_LOGIC; - sd_ras_n : out STD_LOGIC; - sd_we_n : out STD_LOGIC; - sd_addr : out sdr_addr_t; - sd_ba : out sdr_ba_t; - sd_dm : out unsigned(DDR_DM_WIDTH-1 downto 0); - sd_dqs : inout unsigned(DDR_DQS_WIDTH-1 downto 0); - sd_data : inout unsigned(DDR_DATA_WIDTH-1 downto 0) - - ); -end sdram_ctrl_frontend64_wb; - -architecture struct of sdram_ctrl_frontend64_wb is - - -- Number of user data words for simulation - signal u_addr : user_addr_t; - signal u_tag_in : user_tag_t; - signal u_tag_rd : user_tag_t; - signal u_tag_wr : user_tag_t; - signal u_cmd : user_cmd_t; - signal u_cmd_we : std_logic; - signal u_busy : std_logic; - signal u_data_w : unsigned(SDR_DATA_WIDTH-1 downto 0); - signal u_dm_wr_in : unsigned(SDR_DM_WIDTH-1 downto 0); - signal u_data_r : unsigned(SDR_DATA_WIDTH-1 downto 0); - signal u_data_vld : std_logic; - signal u_req_wr : std_logic; - signal rdy : std_logic; - - constant CAT_FIFO_WIDTH : integer := user_cmd_t'length + user_tag_t'length + DDR_ROW_ADDR_WIDTH + DDR_BANK_WIDTH + DDR_COL_ADDR_WIDTH; - signal cat_fifo_din : unsigned(CAT_FIFO_WIDTH-1 downto 0); - signal cat_fifo_dout : unsigned(CAT_FIFO_WIDTH-1 downto 0); - signal cat_fifo_re : std_logic; - signal cat_fifo_we : std_logic; - signal cat_fifo_full : std_logic; - signal cat_fifo_empty : std_logic; --- signal cat_fifo_almost_full : std_logic; --- signal cat_fifo_almost_empty : std_logic; - - signal write_fifo_din : unsigned(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto 0); - signal write_fifo_dout : unsigned(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto 0); - signal write_fifo_re : std_logic; - signal write_fifo_we : std_logic; - signal write_fifo_full : std_logic; - signal write_fifo_empty : std_logic; --- signal write_fifo_almost_full : std_logic; --- signal write_fifo_almost_empty : std_logic; - - signal read_fifo_din : unsigned(SDR_DATA_WIDTH-1 downto 0); - signal read_fifo_dout : unsigned(SDR_DATA_WIDTH-1 downto 0); - signal read_fifo_re : std_logic; - signal read_fifo_we : std_logic; - signal read_fifo_full : std_logic; - signal read_fifo_empty : std_logic; --- signal read_fifo_almost_full : std_logic; --- signal read_fifo_almost_empty : std_logic; - - alias cmd_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-1 downto CAT_FIFO_WIDTH-user_cmd_t'length); - alias tag_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-user_cmd_t'length-1 downto CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length); - alias addr_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length-1 downto 0); - alias cmd_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-1 downto CAT_FIFO_WIDTH-user_cmd_t'length); - alias tag_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-user_cmd_t'length-1 downto CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length); - alias addr_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length-1 downto 0); - - alias write_fifo_dm_in is write_fifo_din(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto SDR_DATA_WIDTH); - alias write_fifo_data_in is write_fifo_din(SDR_DATA_WIDTH-1 downto 0); - alias write_fifo_dm_out is write_fifo_dout(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto SDR_DATA_WIDTH); - alias write_fifo_data_out is write_fifo_dout(SDR_DATA_WIDTH-1 downto 0); - - alias read_fifo_data_in is read_fifo_din(SDR_DATA_WIDTH-1 downto 0); - alias read_fifo_data_out is read_fifo_dout(SDR_DATA_WIDTH-1 downto 0); - -begin - - -- Instantiate synchronous FIFO - inst_cat_fifo: entity work.fifo_sync - GENERIC MAP - ( - addr_width => fifo_depth, - data_width => CAT_FIFO_WIDTH - ) - PORT MAP - ( - rst => RST_I, - clk => CLK_I, - we => cat_fifo_we, - re => cat_fifo_re, - fifo_full => cat_fifo_full, - fifo_empty => cat_fifo_empty, - fifo_afull => open, - fifo_aempty => open, - data_w => cat_fifo_din, - data_r => cat_fifo_dout - ); - - -- Instantiate synchronous FIFO - inst_write_fifo: entity work.fifo_async - GENERIC MAP - ( - addr_width => fifo_depth, - data_width => write_fifo_din'length - ) - PORT MAP - ( - rst => RST_I, - clk_w => CLK_I, - clk_r => SDRAM_CLK0_I, - we => write_fifo_we, - re => write_fifo_re, - fifo_full => write_fifo_full, - fifo_empty => write_fifo_empty, - fifo_afull => open, - fifo_aempty => open, - data_w => write_fifo_din, - data_r => write_fifo_dout - ); - - -- Instantiate synchronous FIFO - inst_read_fifo: entity work.fifo_async - GENERIC MAP - ( - addr_width => fifo_depth, - data_width => read_fifo_din'length - ) - PORT MAP - ( - rst => RST_I, - clk_w => SDRAM_CLK0_I, - clk_r => CLK_I, - we => read_fifo_we, - re => read_fifo_re, - fifo_full => read_fifo_full, - fifo_empty => read_fifo_empty, - fifo_afull => open, - fifo_aempty => open, - data_w => read_fifo_din, - data_r => read_fifo_dout - ); - - -- DDR SDRAM Controller Core - inst_sdram_ctrl : entity work.sdram_ctrl_top - Generic map - ( - BL => BL, - f_sysclk => f_sysclk, - f_sdrclk => f_sdrclk, - fifo_depth => fifo_depth - ) - Port map - ( - - sys_rst_in => RST_I, - sys_clk_in => CLK_I, - - sdram_clk0_in => SDRAM_CLK0_I, - sdram_clk270_in => SDRAM_CLK270_I, - sdram_clk270_rd_in => SDRAM_CLK270VAR_I, - - -- User interface - u_data_vld => u_data_vld, - u_data_req_w => u_req_wr, - u_tag_in => u_tag_in, - u_tag_rd => u_tag_rd, - u_tag_wr => u_tag_wr, - u_busy => u_busy, - u_addr => u_addr, - u_cmd => u_cmd, - u_cmd_we => u_cmd_we, - u_data_wr => u_data_w, - u_data_rd => u_data_r, - u_dm => u_dm_wr_in, - - -- SDRAM signals - sd_clk_p => sd_clk_p, - sd_clk_n => sd_clk_n, - sd_cke => sd_cke, - sd_cs_n => sd_cs_n, - sd_cas_n => sd_cas_n, - sd_ras_n => sd_ras_n, - sd_we_n => sd_we_n, - sd_addr => sd_addr, - sd_ba => sd_ba, - sd_dm => sd_dm, - sd_dqs => sd_dqs, - sd_data => sd_data - - ); - ------------------------------------------------------------------------------------------- - SRDY_O <= rdy; - ACK_O <= not (read_fifo_empty); - DAT_O <= read_fifo_data_out; - rdy <= not (cat_fifo_full or write_fifo_full or read_fifo_full) and CYC_I; - write_fifo_we <= STB_I and WE_I and rdy; - write_fifo_data_in <= DAT_I; - write_fifo_dm_in <= not SEL_I; - cat_fifo_we <= STB_I and rdy; - cmd_fifo_in <= UCMD_WRITE when WE_I = '1' else UCMD_READ; - addr_fifo_in <= ADDR_I(25 downto 3) & "0"; - tag_fifo_in <= "000" & ADDR_I(2); - - u_cmd_we <= (not cat_fifo_empty) and (not u_busy); - u_cmd <= cmd_fifo_out; - u_addr <= addr_fifo_out; - u_dm_wr_in <= (write_fifo_dm_out(SDR_DATA_WIDTH+SDR_DM_WIDTH-5 downto SDR_DATA_WIDTH) & write_fifo_dm_out(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto SDR_DATA_WIDTH+4)) when u_tag_wr(0) = '1' else write_fifo_dm_out(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto SDR_DATA_WIDTH); - u_tag_in <= tag_fifo_out; - u_data_w <= (write_fifo_data_out(31 downto 0) & write_fifo_data_out(63 downto 32)) when u_tag_wr(0) = '1' else write_fifo_data_out(63 downto 0); - - write_fifo_re <= u_req_wr and (not write_fifo_empty); - cat_fifo_re <= u_cmd_we; - read_fifo_re <= (not read_fifo_empty) and MRDY_I; - read_fifo_we <= u_data_vld; - read_fifo_data_in <= (u_data_r(31 downto 0) & u_data_r(63 downto 32)) when u_tag_rd(0) = '1' else u_data_r(63 downto 0); - -end architecture struct; diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb.vhd deleted file mode 100644 index 57002b9..0000000 --- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb.vhd +++ /dev/null @@ -1,278 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: cpu_embedded using cpu_core and rom --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.fifo_ctrl_pkg.all; -use work.sdram_config.all; -use work.sdram_types.all; - -entity sdram_ctrl_frontend_wb is - Generic - ( - BL : natural := 2; - f_sysclk : real := 100.0; - f_sdrclk : real := 100.0; - fifo_depth : integer := 4 - ); - Port - ( - RST_I : in STD_LOGIC; - CLK_I : in STD_LOGIC; - SDRAM_CLK0_I : in STD_LOGIC; - SDRAM_CLK270_I : in STD_LOGIC; - SDRAM_CLK270VAR_I : in STD_LOGIC; - - CYC_I : in STD_LOGIC; - STB_I : in STD_LOGIC; - SEL_I : in unsigned(3 downto 0); - WE_I : in STD_LOGIC; - ACK_O : out STD_LOGIC; - MRDY_I : in STD_LOGIC; - SRDY_O : out STD_LOGIC; - ADDR_I : in unsigned(31 downto 0); - DAT_I : in unsigned(31 downto 0); - DAT_O : out unsigned(31 downto 0); - - -- SDRAM signals - sd_clk_p : out STD_LOGIC; - sd_clk_n : out STD_LOGIC; - sd_cke : out STD_LOGIC; - sd_cs_n : out STD_LOGIC; - sd_cas_n : out STD_LOGIC; - sd_ras_n : out STD_LOGIC; - sd_we_n : out STD_LOGIC; - sd_addr : out sdr_addr_t; - sd_ba : out sdr_ba_t; - sd_dm : out unsigned(DDR_DM_WIDTH-1 downto 0); - sd_dqs : inout unsigned(DDR_DQS_WIDTH-1 downto 0); - sd_data : inout unsigned(DDR_DATA_WIDTH-1 downto 0) - - ); -end sdram_ctrl_frontend_wb; - -architecture struct of sdram_ctrl_frontend_wb is - - -- Number of user data words for simulation - signal u_addr : user_addr_t; - signal u_tag_in : user_tag_t; - signal u_tag_rd : user_tag_t; - signal u_tag_wr : user_tag_t; - signal u_cmd : user_cmd_t; - signal u_cmd_we : std_logic; - signal u_busy : std_logic; - signal u_data_w : unsigned(SDR_DATA_WIDTH-1 downto 0); - signal u_dm_wr_in : unsigned(SDR_DM_WIDTH-1 downto 0); - signal u_data_r : unsigned(SDR_DATA_WIDTH-1 downto 0); - signal u_data_vld : std_logic; - signal u_req_wr : std_logic; - signal rdy : std_logic; - - constant CAT_FIFO_WIDTH : integer := user_cmd_t'length + user_tag_t'length + DDR_ROW_ADDR_WIDTH + DDR_BANK_WIDTH + DDR_COL_ADDR_WIDTH; - signal cat_fifo_din : unsigned(CAT_FIFO_WIDTH-1 downto 0); - signal cat_fifo_dout : unsigned(CAT_FIFO_WIDTH-1 downto 0); - signal cat_fifo_re : std_logic; - signal cat_fifo_we : std_logic; - signal cat_fifo_full : std_logic; - signal cat_fifo_empty : std_logic; --- signal cat_fifo_almost_full : std_logic; --- signal cat_fifo_almost_empty : std_logic; - - signal write_fifo_din : unsigned(35 downto 0); - signal write_fifo_dout : unsigned(35 downto 0); - signal write_fifo_re : std_logic; - signal write_fifo_we : std_logic; - signal write_fifo_full : std_logic; - signal write_fifo_empty : std_logic; --- signal write_fifo_almost_full : std_logic; --- signal write_fifo_almost_empty : std_logic; - - signal read_fifo_din : unsigned(31 downto 0); - signal read_fifo_dout : unsigned(31 downto 0); - signal read_fifo_re : std_logic; - signal read_fifo_we : std_logic; - signal read_fifo_full : std_logic; - signal read_fifo_empty : std_logic; --- signal read_fifo_almost_full : std_logic; --- signal read_fifo_almost_empty : std_logic; - - alias cmd_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-1 downto CAT_FIFO_WIDTH-user_cmd_t'length); - alias tag_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-user_cmd_t'length-1 downto CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length); - alias addr_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length-1 downto 0); - alias cmd_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-1 downto CAT_FIFO_WIDTH-user_cmd_t'length); - alias tag_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-user_cmd_t'length-1 downto CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length); - alias addr_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length-1 downto 0); - - alias write_fifo_data_in is write_fifo_din(write_fifo_din'length-1 downto 4); - alias write_fifo_dm_in is write_fifo_din(3 downto 0); - alias write_fifo_data_out is write_fifo_dout(write_fifo_dout'length-1 downto 4); - alias write_fifo_dm_out is write_fifo_dout(3 downto 0); - - alias read_fifo_data_in is read_fifo_din(read_fifo_din'length-1 downto 0); - alias read_fifo_data_out is read_fifo_dout(read_fifo_dout'length-1 downto 0); - -begin - - -- Instantiate synchronous FIFO - inst_cat_fifo: entity work.fifo_sync - GENERIC MAP - ( - addr_width => fifo_depth, - data_width => CAT_FIFO_WIDTH - ) - PORT MAP - ( - rst => RST_I, - clk => CLK_I, - we => cat_fifo_we, - re => cat_fifo_re, - fifo_full => cat_fifo_full, - fifo_empty => cat_fifo_empty, - fifo_afull => open, - fifo_aempty => open, - data_w => cat_fifo_din, - data_r => cat_fifo_dout - ); - - -- Instantiate synchronous FIFO - inst_write_fifo: entity work.fifo_async - GENERIC MAP - ( - addr_width => fifo_depth, - data_width => write_fifo_din'length - ) - PORT MAP - ( - rst => RST_I, - clk_w => CLK_I, - clk_r => SDRAM_CLK0_I, - we => write_fifo_we, - re => write_fifo_re, - fifo_full => write_fifo_full, - fifo_empty => write_fifo_empty, - fifo_afull => open, - fifo_aempty => open, - data_w => write_fifo_din, - data_r => write_fifo_dout - ); - - -- Instantiate synchronous FIFO - inst_read_fifo: entity work.fifo_async - GENERIC MAP - ( - addr_width => fifo_depth, - data_width => read_fifo_din'length - ) - PORT MAP - ( - rst => RST_I, - clk_w => SDRAM_CLK0_I, - clk_r => CLK_I, - we => read_fifo_we, - re => read_fifo_re, - fifo_full => read_fifo_full, - fifo_empty => read_fifo_empty, - fifo_afull => open, - fifo_aempty => open, - data_w => read_fifo_din, - data_r => read_fifo_dout - ); - - -- DDR SDRAM Controller Core - inst_sdram_ctrl : entity work.sdram_ctrl_top - Generic map - ( - BL => BL, - f_sysclk => f_sysclk, - f_sdrclk => f_sdrclk, - fifo_depth => fifo_depth - ) - Port map - ( - - sys_rst_in => RST_I, - sys_clk_in => CLK_I, - - sdram_clk0_in => SDRAM_CLK0_I, - sdram_clk270_in => SDRAM_CLK270_I, - sdram_clk270_rd_in => SDRAM_CLK270VAR_I, - - -- User interface - u_data_vld => u_data_vld, - u_data_req_w => u_req_wr, - u_tag_in => u_tag_in, - u_tag_rd => u_tag_rd, - u_tag_wr => u_tag_wr, - u_busy => u_busy, - u_addr => u_addr, - u_cmd => u_cmd, - u_cmd_we => u_cmd_we, - u_data_wr => u_data_w, - u_data_rd => u_data_r, - u_dm => u_dm_wr_in, - - -- SDRAM signals - sd_clk_p => sd_clk_p, - sd_clk_n => sd_clk_n, - sd_cke => sd_cke, - sd_cs_n => sd_cs_n, - sd_cas_n => sd_cas_n, - sd_ras_n => sd_ras_n, - sd_we_n => sd_we_n, - sd_addr => sd_addr, - sd_ba => sd_ba, - sd_dm => sd_dm, - sd_dqs => sd_dqs, - sd_data => sd_data - - ); - ------------------------------------------------------------------------------------------- - SRDY_O <= rdy; - ACK_O <= not (read_fifo_empty); - DAT_O <= read_fifo_data_out; - rdy <= not (cat_fifo_full or write_fifo_full or read_fifo_full) and CYC_I; - write_fifo_we <= STB_I and WE_I and rdy; - write_fifo_data_in <= DAT_I; - write_fifo_dm_in <= not SEL_I; - cat_fifo_we <= STB_I and rdy; - cmd_fifo_in <= UCMD_WRITE when WE_I = '1' else UCMD_READ; - addr_fifo_in <= ADDR_I(24 downto 2) & "0"; - tag_fifo_in <= "000" & ADDR_I(25); - - u_cmd_we <= (not cat_fifo_empty) and (not u_busy); - u_cmd <= cmd_fifo_out; - u_addr <= addr_fifo_out; - u_dm_wr_in <= ("1111" & write_fifo_dm_out) when u_tag_wr(0) = '0' else (write_fifo_dm_out & "1111"); - u_tag_in <= tag_fifo_out; - u_data_w <= write_fifo_data_out & write_fifo_data_out; - - write_fifo_re <= u_req_wr and (not write_fifo_empty); - cat_fifo_re <= u_cmd_we; - read_fifo_re <= (not read_fifo_empty) and MRDY_I; - read_fifo_we <= u_data_vld; - read_fifo_data_in <= u_data_r(31 downto 0) when u_tag_rd(0) = '0' else u_data_r(63 downto 32); - -end architecture struct; diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd deleted file mode 100644 index 8d4a9a4..0000000 --- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd +++ /dev/null @@ -1,237 +0,0 @@ -------------------------------------------------------------------------- --- Project: SDRAM controller --- This file: Top-level put all together --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.sdram_config.all; -use work.sdram_types.all; - -entity sdram_ctrl_top is - Generic - ( - BL : natural := 2; - f_sysclk : real := 100.0; - f_sdrclk : real := 100.0; - fifo_depth : natural := 3 - ); - Port - ( - sys_rst_in : in STD_LOGIC; - sys_clk_in : in STD_LOGIC; - - sdram_clk0_in : in STD_LOGIC; - sdram_clk270_in : in STD_LOGIC; - sdram_clk270_rd_in : in STD_LOGIC; - - -- User interface - u_data_vld : out STD_LOGIC; - u_data_req_w : out STD_LOGIC; - u_busy : out STD_LOGIC; - u_tag_in : in user_tag_t; - u_tag_rd : out user_tag_t; - u_tag_wr : out user_tag_t; - u_addr : in user_addr_t; - u_cmd : in user_cmd_t; - u_cmd_we : in STD_LOGIC; - u_data_wr : in unsigned(SDR_DATA_WIDTH-1 downto 0); - u_dm : in unsigned(SDR_DM_WIDTH-1 downto 0); - u_data_rd : out unsigned(SDR_DATA_WIDTH-1 downto 0); - - -- SDRAM signals - sd_clk_p : out STD_LOGIC; - sd_clk_n : out STD_LOGIC; - sd_cke : out STD_LOGIC; - sd_cs_n : out STD_LOGIC; - sd_cas_n : out STD_LOGIC; - sd_ras_n : out STD_LOGIC; - sd_we_n : out STD_LOGIC; - sd_addr : out sdr_addr_t; - sd_ba : out sdr_ba_t; - sd_dm : out unsigned(DDR_DM_WIDTH-1 downto 0); - sd_dqs : inout unsigned(DDR_DQS_WIDTH-1 downto 0); - sd_data : inout unsigned(DDR_DATA_WIDTH-1 downto 0) - - ); -end sdram_ctrl_top; - -architecture rtl of sdram_ctrl_top is - - - signal phy_ctrl : phy_ctrl_t; - - signal u_tag : user_tag_t; - signal sd_cmd_in : sdr_cmd_t; - signal sd_cmd : sdr_cmd_t; - signal sd_cmd_we : std_logic; - signal cmd_ctrl : sdr_cmd_lines_t; - signal cke : std_logic; - signal ba : unsigned(DDR_BANK_WIDTH-1 downto 0); - signal addr : unsigned(DDR_ADDR_WIDTH-1 downto 0); - - -- Clock generator - - signal part_ctrl : part_ctrl_t; - - -- SD command FIFO - - constant CMD_FIFO_DATA_WIDTH : positive := user_tag_t'length + 4 + mode_word_t'length + col_addr_t'length; - signal cmd_fifo_din : unsigned(CMD_FIFO_DATA_WIDTH-1 downto 0); - signal cmd_fifo_dout : unsigned(CMD_FIFO_DATA_WIDTH-1 downto 0); - signal cmd_fifo_re : std_logic; - signal cmd_fifo_we : std_logic; - signal cmd_fifo_full : std_logic; - signal cmd_fifo_empty : std_logic; - - alias tag_fifo_in is cmd_fifo_din(CMD_FIFO_DATA_WIDTH-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length); - alias cmd_fifo_in is cmd_fifo_din(CMD_FIFO_DATA_WIDTH-user_tag_t'length-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length-4); - alias mode_fifo_in is cmd_fifo_din(CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-mode_word_t'length); - alias col_fifo_in is cmd_fifo_din(CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-mode_word_t'length-1 downto 0); - - alias sd_tag_fifo_out is cmd_fifo_dout(CMD_FIFO_DATA_WIDTH-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length); - alias sd_cmd_fifo_out is cmd_fifo_dout(CMD_FIFO_DATA_WIDTH-user_tag_t'length-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length-4); - alias sd_mode_fifo_out is cmd_fifo_dout(CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-mode_word_t'length); - alias sd_col_fifo_out is cmd_fifo_dout(CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-mode_word_t'length-1 downto 0); - -begin - - --------------------------------- - part_ctrl.cmd <= cmd_ctrl; - part_ctrl.ba <= ba; - part_ctrl.addr <= addr; - part_ctrl.cke <= cke; - - --------------------------------- - sd_cmd_we <= not cmd_fifo_empty; - cmd_fifo_in <= to_unsigned(sd_cmd_in, 4); - sd_cmd <= sdr_cmd_t(to_integer(sd_cmd_fifo_out)); - - --------------------------------- - - -- Main controller - inst_sdram_ctrl : entity work.sdram_ctrl - Generic map - ( - f_sysclk => f_sysclk, - BL => BL - ) - Port map - ( - rst => sys_rst_in, - clk => sys_clk_in, - u_busy => u_busy, - u_tag_in => u_tag_in, - u_tag_out => tag_fifo_in, - u_cmd => u_cmd, - u_cmd_we => u_cmd_we, - u_addr => u_addr, - sdr_cmd_busy => cmd_fifo_full, - sdr_cmd => sd_cmd_in, - sdr_cmd_we => cmd_fifo_we, - col_addr => col_fifo_in, - sdr_mode => mode_fifo_in, - sdr_cke => cke - ); - - -- Instantiate synchronous FIFO - inst_sd_cmd_fifo: entity work.fifo_async - GENERIC MAP - ( - addr_width => fifo_depth, - data_width => CMD_FIFO_DATA_WIDTH - ) - PORT MAP - ( - rst => sys_rst_in, - clk_w => sys_clk_in, - clk_r => sdram_clk0_in, - we => cmd_fifo_we, - re => cmd_fifo_re, - fifo_full => cmd_fifo_full, - fifo_empty => cmd_fifo_empty, - fifo_afull => open, - fifo_aempty => open, - data_w => cmd_fifo_din, - data_r => cmd_fifo_dout - ); - - -- DDR SDRAM command fsm - inst_sdram_cmd : entity work.sdram_cmd - Generic map - ( - f_sdrclk => f_sdrclk, - BL => BL - ) - Port map - ( - rst => sys_rst_in, - clk => sdram_clk0_in, - u_tag_in => sd_tag_fifo_out, - u_tag_out => u_tag, - phy_ctrl => phy_ctrl, - enable => cke, - cmd => sd_cmd, - cmd_we => sd_cmd_we, - cmd_ack => cmd_fifo_re, - sdr_cmd_ctrl => cmd_ctrl, - col_addr => sd_col_fifo_out, - mode_word => sd_mode_fifo_out, - sdr_ba => ba, - sdr_addr => addr - ); - - -- DDR phy - inst_ddr_phy : entity work.ddr_phy - Port map - ( - sys_rst => sys_rst_in, - sys_clk0 => sdram_clk0_in, - sys_clk270 => sdram_clk270_in, - u_tag_in => u_tag, - u_tag_rd => u_tag_rd, - u_tag_wr => u_tag_wr, - read_clk => sdram_clk270_rd_in, - phy_ctrl => phy_ctrl, - part_ctrl => part_ctrl, - sdr_data_req_w => u_data_req_w, - sdr_data_w => u_data_wr, - sdr_dm => u_dm, - sdr_data_r => u_data_rd, - sdr_data_vld => u_data_vld, - part_clk_p => sd_clk_p, - part_clk_n => sd_clk_n, - part_addr => sd_addr, - part_ba => sd_ba, - part_dm => sd_dm, - part_dqs => sd_dqs, - part_data => sd_data, - part_cs_n => sd_cs_n, - part_we_n => sd_we_n, - part_cas_n => sd_cas_n, - part_ras_n => sd_ras_n, - part_cke => sd_cke - ); - -end architecture rtl; - diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd deleted file mode 100644 index 5520b28..0000000 --- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd +++ /dev/null @@ -1,130 +0,0 @@ -------------------------------------------------------------------------- --- Project: SDRAM controller --- This file: Type definitions --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; -USE IEEE.MATH_REAL.ALL; - -use work.sdram_config.all; - -package sdram_types is - - ----------------------------------------------------------------------------------------- - -- Table of Timing Parameters as a function of operation - - -- Derived constants from sdram_config - - constant DDR_DQS_WIDTH : positive := DDR_DATA_WIDTH / 8; -- Number of data strobe lines - constant DDR_DM_WIDTH : positive := DDR_DATA_WIDTH / 8; -- Number of Data Mask Lines - constant SDR_DATA_WIDTH : positive := 2*DDR_DATA_WIDTH; -- - constant SDR_DM_WIDTH : positive := 2*DDR_DM_WIDTH; -- - - subtype user_cmd_t is unsigned(1 downto 0); - constant UCMD_NOP : user_cmd_t := "00"; - constant UCMD_READ : user_cmd_t := "01"; - constant UCMD_WRITE : user_cmd_t := "10"; - constant UCMD_LMR : user_cmd_t := "11"; - - subtype sdr_cmd_t is natural range 0 to 9; - constant SD_DESELECT : sdr_cmd_t := 0; - constant SD_NOP : sdr_cmd_t := 1; - constant SD_LMR : sdr_cmd_t := 2; - constant SD_ACT : sdr_cmd_t := 3; - constant SD_READ : sdr_cmd_t := 4; - constant SD_WRITE : sdr_cmd_t := 5; - constant SD_PRE : sdr_cmd_t := 6; - constant SD_BST : sdr_cmd_t := 7; - constant SD_AR : sdr_cmd_t := 8; - constant SD_SR : sdr_cmd_t := 9; - - type sdr_state_t is (PWR_DOWN, PRECHARGE, MODE, IDLE, ROW_ACT, WRITE, WRITE_A, READ, READ_A, BURST_STOP, SELF_REF, AUTO_REF, PRE_PWR_DOWN, ACT_PWR_DOWN); - subtype user_addr_t is unsigned(DDR_BANK_WIDTH+DDR_ROW_ADDR_WIDTH+DDR_COL_ADDR_WIDTH-1 downto 0); - subtype sdr_addr_t is unsigned(DDR_ADDR_WIDTH-1 downto 0); - subtype sdr_ba_t is unsigned(DDR_BANK_WIDTH-1 downto 0); - subtype mode_word_t is unsigned(DDR_ADDR_WIDTH+DDR_BANK_WIDTH-1 downto 0); - - subtype bank_addr_t is unsigned(DDR_BANK_WIDTH-1 downto 0); - subtype row_addr_t is unsigned(DDR_ADDR_WIDTH-1 downto 0); - subtype col_addr_t is unsigned(8 downto 0); - - type phy_ctrl_t is - record - drive_en : std_logic; - re : std_logic; - we : std_logic; - utag_we : std_logic; - end record phy_ctrl_t; - - type sdr_cmd_lines_t is - record - cs_n : std_logic; - ras_n : std_logic; - cas_n : std_logic; - we_n : std_logic; - end record sdr_cmd_lines_t; - - type part_ctrl_t is - record - cmd : sdr_cmd_lines_t; - ba : unsigned(DDR_BANK_WIDTH-1 downto 0); - addr : unsigned(DDR_ADDR_WIDTH-1 downto 0); - cke : std_logic; - end record part_ctrl_t; - - type part_cmd_array_t is array (sdr_cmd_t) of sdr_cmd_lines_t; - constant COMMAND : part_cmd_array_t := - -- command cs_n ras_qn cas_qn we_qn - ( SD_DESELECT => ( '1', '1', '1', '1'), - SD_NOP => ( '0', '1', '1', '1'), - SD_LMR => ( '0', '0', '0', '0'), - SD_ACT => ( '0', '0', '1', '1'), - SD_READ => ( '0', '1', '0', '1'), - SD_WRITE => ( '0', '1', '0', '0'), - SD_PRE => ( '0', '0', '1', '0'), - SD_BST => ( '0', '1', '1', '0'), - SD_AR => ( '0', '0', '0', '1'), - SD_SR => ( '0', '0', '0', '1') - ); - - type init_seq_t is - record - cmd : sdr_cmd_t; - mode_word : mode_word_t; - wait_cycle : natural; - end record init_seq_t; - - function to_cycles(T_ns : real; f_Mhz : real) return natural; - -end sdram_types; - -package body sdram_types is - - function to_cycles(T_ns : real; f_Mhz : real) return natural is - begin - - return natural(ceil(1.0E-3*T_ns*f_Mhz)); - - end to_cycles; - -end sdram_types; diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend64_wb.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend64_wb.vhd deleted file mode 100644 index fdfd07d..0000000 --- a/lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend64_wb.vhd +++ /dev/null @@ -1,871 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: cpu_embedded using cpu_core and rom --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.fifo_ctrl_pkg.all; -use work.sdram_config.all; -use work.sdram_types.all; - -entity tb_sdram_ctrl_frontend64_wb is -end; - -architecture struct of tb_sdram_ctrl_frontend64_wb is - - -- Number of user data words for simulation - constant CLK_PERIOD : time := 10 ns; - constant SDCLK_PERIOD : time := 7.5 ns; - constant BURST_LEN : natural := 2; - - signal rst : std_logic := '1'; - signal clk : std_logic := '1'; - signal sdclk : std_logic := '1'; - signal locked : std_logic; - signal error : std_logic; - signal clk_out : std_logic; - signal clk_fb : std_logic; - signal part_clk_p : std_logic; - signal part_clk_n : std_logic; - signal part_cke : std_logic; - signal part_cs_n : std_logic; - signal part_we_n : std_logic; - signal part_ras_n : std_logic; - signal part_cas_n : std_logic; - signal part_ba : unsigned(DDR_BANK_WIDTH-1 downto 0) := (others => '0'); - signal part_dm : unsigned(DDR_DM_WIDTH-1 downto 0) := (others => '0'); - signal part_dqs : unsigned(DDR_DQS_WIDTH-1 downto 0) := (others => '0'); - signal part_addr : unsigned(DDR_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal part_data : unsigned(DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - - signal CLK_O : std_logic; - signal CLK0_O : std_logic; - signal CLK270_O : std_logic; - signal CLK270VAR_O : std_logic; - signal RST_O : std_logic; - signal CYC_O : std_logic := '0'; - signal STB_O : std_logic := '0'; - signal WE_O : std_logic := '0'; - signal SEL_O : unsigned(SDR_DM_WIDTH-1 downto 0); - signal ACK_I : std_logic; - signal MRDY_O : std_logic := '1'; - signal SRDY_I : std_logic; - signal ADDR_O : unsigned(31 downto 0) := (others => '-'); - signal DAT_I : unsigned(SDR_DATA_WIDTH-1 downto 0); - signal DAT_O : unsigned(SDR_DATA_WIDTH-1 downto 0); - - signal dout_rst : std_logic := '0'; - signal dout_reg : unsigned(31 downto 0); - signal dout_cnt : natural range 0 to 255; - - signal sddat : unsigned(31 downto 0) := (others => '-'); - signal sdsel : unsigned(3 downto 0) := (others => '1'); - - type sd_cmd_t is (nop, lmr, ar, pre, act, write, read, bst); - signal sd_cmd : sd_cmd_t; - -begin - - process(part_cs_n, part_ras_n, part_cas_n, part_we_n) - variable cmd : unsigned (2 downto 0); - - begin - cmd := part_ras_n & part_cas_n & part_we_n; - sd_cmd <= nop; - if part_cs_n = '0' then - case cmd is - when "000" => - sd_cmd <= lmr; - when "001" => - sd_cmd <= ar; - when "010" => - sd_cmd <= pre; - when "011" => - sd_cmd <= act; - when "100" => - sd_cmd <= write; - when "101" => - sd_cmd <= read; - when "110" => - sd_cmd <= bst; - when "111" => - sd_cmd <= nop; - - when others => - sd_cmd <= nop; - - end case; - end if; - end process; - -inst_clockgen : entity work.clockgen - GENERIC MAP - ( - clk_in_freq => 100.0, - clk0_out_phaseshift => 0, - clk1_out_phaseshift => 0 - ) - PORT MAP - ( - -- Clocks and Reset - rst => rst, -- external async reset, low active - clk_in => sdclk, -- system clock (e.g. 100MHz), from board - clk_fb_in => clk_fb, -- feedback clock - clk0_0_out => CLK0_O, -- System clock #0, dcm#0 output 0° - clk0_270_out => CLK270_O, -- System clock #0, dcm#0 output 270° - clk1_0_out => open, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0° - clk1_270_out => CLK270VAR_O, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270° - locked_out => locked, -- DCM locked status - error_out => error - ); - - clk_fb <= part_clk_p after 1 ns; - CLK_O <= clk; - RST_O <= not locked; - DAT_O <= X"DEADBEEF" & sddat; - SEL_O <= "0000" & sdsel; - - -- DDR SDRAM Controller Core - sdram_ctrl_frontend64_wb : entity work.sdram_ctrl_frontend64_wb - GENERIC MAP - ( - BL => BURST_LEN, - f_sysclk => 100.000, - f_sdrclk => 133.333, - fifo_depth => 4 - ) - PORT MAP - ( - RST_I => RST_O, - CLK_I => CLK_O, - SDRAM_CLK0_I => CLK0_O, - SDRAM_CLK270_I => CLK270_O, - SDRAM_CLK270VAR_I => CLK270VAR_O, - CYC_I => CYC_O, - STB_I => STB_O, - SEL_I => SEL_O, - WE_I => WE_O, - ACK_O => ACK_I, - SRDY_O => SRDY_I, - MRDY_I => MRDY_O, - ADDR_I => ADDR_O, - DAT_I => DAT_O, - DAT_O => DAT_I, - - -- SDRAM signals - sd_clk_p => part_clk_p, - sd_clk_n => part_clk_n, - sd_cke => part_cke, - sd_cs_n => part_cs_n, - sd_cas_n => part_cas_n, - sd_ras_n => part_ras_n, - sd_we_n => part_we_n, - sd_addr => part_addr, - sd_ba => part_ba, - sd_dm => part_dm, - sd_dqs => part_dqs, - sd_data => part_data - - ); - - -- MICRON DDR SDRAM Simulation Model -i_mt46v16m16_0 : entity work.mt46v16m16 - port map - ( - dq => std_logic_vector(part_data(15 downto 0)), - dqs => std_logic_vector(part_dqs(1 downto 0)), - addr => std_logic_vector(part_addr), - ba => std_logic_vector(part_ba), - clk => part_clk_p, - clk_n => part_clk_n, - cke => part_cke, - cs_n => part_cs_n, - ras_n => part_ras_n, - cas_n => part_cas_n, - we_n => part_we_n, - dm => std_logic_vector(part_dm(1 downto 0)) - ); - - -- MICRON DDR SDRAM Simulation Model -i_mt46v16m16_1 : entity work.mt46v16m16 - port map - ( - dq => std_logic_vector(part_data(31 downto 16)), - dqs => std_logic_vector(part_dqs(3 downto 2)), - addr => std_logic_vector(part_addr), - ba => std_logic_vector(part_ba), - clk => part_clk_p, - clk_n => part_clk_n, - cke => part_cke, - cs_n => part_cs_n, - ras_n => part_ras_n, - cas_n => part_cas_n, - we_n => part_we_n, - dm => std_logic_vector(part_dm(3 downto 2)) - ); - -CLK_GEN: process - begin - wait for CLK_PERIOD/2; - clk <= not clk; - end process; - -SDCLK_GEN: process - begin - wait for SDCLK_PERIOD/2; - sdclk <= not sdclk; - end process; - -read_register: - process(CLK_O) - begin - if rising_edge(CLK_O) then - if dout_rst = '1' then - dout_cnt <= 0; - elsif ACK_I = '1' and WE_O = '0' then - dout_reg <= DAT_I(31 downto 0); - dout_cnt <= dout_cnt + 1; - end if; - end if; - end process; - ------------------------------------------------------------------------------------------- - -STIMULUS: process - - begin - - wait for 3*CLK_PERIOD; - rst <= '0'; - - wait until RST_O = '0'; - -- 8 single cycles - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '1'; - sddat <= X"1234_0000"; - ADDR_O <= X"0000_0000"; - - for i in 0 to 8192 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - sddat <= sddat + 1; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O); - CYC_O <= '0'; - - ------------------------------------------------------------ - wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_0000"; - - for i in 0 to 31 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 31; - CYC_O <= '0'; - - ------------------------------------------------------------ - wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - wait until rising_edge(CLK_O); - -- 1-word burst cycle - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '1'; - sdsel <= "0011"; - ADDR_O <= X"0000_0080"; - sddat <= X"DEADBEEF"; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '0'; - wait until rising_edge(CLK_O); - CYC_O <= '0'; - - ------------------------------------------------------------ - wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - wait until rising_edge(CLK_O); - -- 1-word burst cycle - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_0080"; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '0'; - wait until rising_edge(CLK_O) and ACK_I = '1'; - CYC_O <= '0'; - - ------------------------------------------------------------ - wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_0000"; - - for i in 0 to 31 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 31; - CYC_O <= '0'; - - ------------------------------------------------------------ - wait for 10*CLK_PERIOD; - ------------------------------------------------------------ - - for k in 0 to 3 loop - ------------------------------------------------------------ --- wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_0000"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 7; - CYC_O <= '0'; - - ------------------------------------------------------------ --- wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_0400"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 7; - CYC_O <= '0'; - - ------------------------------------------------------------ --- wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_0800"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 7; - CYC_O <= '0'; - - ------------------------------------------------------------ --- wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_0C00"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 7; - CYC_O <= '0'; - - end loop; - - ------------------------------------------------------------ - wait for 10*CLK_PERIOD; - ------------------------------------------------------------ - - for k in 0 to 3 loop - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_1000"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 7; - CYC_O <= '0'; - - ------------------------------------------------------------ --- wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_1400"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 7; - CYC_O <= '0'; - - ------------------------------------------------------------ --- wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_1800"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 7; - CYC_O <= '0'; - - ------------------------------------------------------------ --- wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_1C00"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 7; - CYC_O <= '0'; - - end loop; - - ------------------------------------------------------------ - wait for 10*CLK_PERIOD; - ------------------------------------------------------------ - - for k in 0 to 3 loop - ------------------------------------------------------------ --- wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '1'; - sdsel <= "1111"; - sddat <= X"1111_0000"; - ADDR_O <= X"0000_0000"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - sddat <= sddat + 1; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O); - CYC_O <= '0'; - - ------------------------------------------------------------ --- wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '1'; - sdsel <= "1111"; - sddat <= X"2222_0000"; - ADDR_O <= X"0000_0400"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - sddat <= sddat + 1; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O); - CYC_O <= '0'; - - ------------------------------------------------------------ --- wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '1'; - sdsel <= "1111"; - sddat <= X"3333_0000"; - ADDR_O <= X"0000_0800"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - sddat <= sddat + 1; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O); - CYC_O <= '0'; - - ------------------------------------------------------------ --- wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '1'; - sdsel <= "1111"; - sddat <= X"4444_0000"; - ADDR_O <= X"0000_0C00"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - sddat <= sddat + 1; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O); - CYC_O <= '0'; - - end loop; - - ------------------------------------------------------------ - wait for 10*CLK_PERIOD; - ------------------------------------------------------------ - - for k in 0 to 3 loop - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '1'; - sdsel <= "1111"; - sddat <= X"1111_0000"; - ADDR_O <= X"0000_1000"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - sddat <= sddat + 1; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O); - CYC_O <= '0'; - - ------------------------------------------------------------ --- wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '1'; - sdsel <= "1111"; - sddat <= X"2222_0000"; - ADDR_O <= X"0000_1400"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - sddat <= sddat + 1; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O); - CYC_O <= '0'; - - ------------------------------------------------------------ --- wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '1'; - sdsel <= "1111"; - sddat <= X"3333_0000"; - ADDR_O <= X"0000_1800"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - sddat <= sddat + 1; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O); - CYC_O <= '0'; - - ------------------------------------------------------------ --- wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '1'; - sdsel <= "1111"; - sddat <= X"4444_0000"; - ADDR_O <= X"0000_1C00"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - sddat <= sddat + 1; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O); - CYC_O <= '0'; - - end loop; - - ------------------------------------------------------------ - wait for 10*CLK_PERIOD; - ------------------------------------------------------------ - - for k in 0 to 3 loop - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_1000"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 7; - CYC_O <= '0'; - - ------------------------------------------------------------ --- wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_1400"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 7; - CYC_O <= '0'; - - ------------------------------------------------------------ --- wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_1800"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 7; - CYC_O <= '0'; - - ------------------------------------------------------------ --- wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_1C00"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 7; - CYC_O <= '0'; - - end loop; - - wait; - - end process; - -end architecture struct; diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend_wb.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend_wb.vhd deleted file mode 100644 index 9673d37..0000000 --- a/lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend_wb.vhd +++ /dev/null @@ -1,867 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: cpu_embedded using cpu_core and rom --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.fifo_ctrl_pkg.all; -use work.sdram_config.all; -use work.sdram_types.all; - -entity tb_sdram_ctrl_frontend_wb is -end; - -architecture struct of tb_sdram_ctrl_frontend_wb is - - -- Number of user data words for simulation - constant CLK_PERIOD : time := 10 ns; - constant SDCLK_PERIOD : time := 8 ns; - constant BURST_LEN : natural := 2; - - signal rst : std_logic := '1'; - signal clk : std_logic := '1'; - signal sdclk : std_logic := '1'; - signal locked : std_logic; - signal error : std_logic; - signal clk_out : std_logic; - signal clk_fb : std_logic; - signal part_clk_p : std_logic; - signal part_clk_n : std_logic; - signal part_cke : std_logic; - signal part_cs_n : std_logic; - signal part_we_n : std_logic; - signal part_ras_n : std_logic; - signal part_cas_n : std_logic; - signal part_ba : unsigned(DDR_BANK_WIDTH-1 downto 0) := (others => '0'); - signal part_dm : unsigned(DDR_DM_WIDTH-1 downto 0) := (others => '0'); - signal part_dqs : unsigned(DDR_DQS_WIDTH-1 downto 0) := (others => '0'); - signal part_addr : unsigned(DDR_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal part_data : unsigned(DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - - signal CLK_O : std_logic; - signal CLK0_O : std_logic; - signal CLK270_O : std_logic; - signal CLK270VAR_O : std_logic; - signal RST_O : std_logic; - signal CYC_O : std_logic := '0'; - signal STB_O : std_logic := '0'; - signal WE_O : std_logic := '0'; - signal SEL_O : unsigned(3 downto 0) := (others => '1'); - signal ACK_I : std_logic; - signal MRDY_O : std_logic := '1'; - signal SRDY_I : std_logic; - signal ADDR_O : unsigned(31 downto 0) := (others => '-'); - signal DAT_I : unsigned(31 downto 0); - signal DAT_O : unsigned(31 downto 0) := (others => '-'); - - signal dout_rst : std_logic := '0'; - signal dout_reg : unsigned(31 downto 0); - signal dout_cnt : natural range 0 to 255; - - type sd_cmd_t is (nop, lmr, ar, pre, act, write, read, bst); - signal sd_cmd : sd_cmd_t; - -begin - - process(part_cs_n, part_ras_n, part_cas_n, part_we_n) - variable cmd : unsigned (2 downto 0); - - begin - cmd := part_ras_n & part_cas_n & part_we_n; - sd_cmd <= nop; - if part_cs_n = '0' then - case cmd is - when "000" => - sd_cmd <= lmr; - when "001" => - sd_cmd <= ar; - when "010" => - sd_cmd <= pre; - when "011" => - sd_cmd <= act; - when "100" => - sd_cmd <= write; - when "101" => - sd_cmd <= read; - when "110" => - sd_cmd <= bst; - when "111" => - sd_cmd <= nop; - - when others => - sd_cmd <= nop; - - end case; - end if; - end process; - -inst_clockgen : entity work.clockgen - GENERIC MAP - ( - clk_in_freq => 100.0, - clk0_out_phaseshift => 0, - clk1_out_phaseshift => 0 - ) - PORT MAP - ( - -- Clocks and Reset - rst => rst, -- external async reset, low active - clk_in => sdclk, -- system clock (e.g. 100MHz), from board - clk_fb_in => clk_fb, -- feedback clock - clk0_0_out => CLK0_O, -- System clock #0, dcm#0 output 0° - clk0_270_out => CLK270_O, -- System clock #0, dcm#0 output 270° - clk1_0_out => open, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0° - clk1_270_out => CLK270VAR_O, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270° - locked_out => locked, -- DCM locked status - error_out => error - ); - - clk_fb <= part_clk_p after 1 ns; - RST_O <= not locked; - CLK_O <= clk; - - -- DDR SDRAM Controller Core - sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend_wb - GENERIC MAP - ( - BL => BURST_LEN, - f_sysclk => 100.0, - f_sdrclk => 100.0, - fifo_depth => 4 - ) - PORT MAP - ( - RST_I => RST_O, - CLK_I => CLK_O, - SDRAM_CLK0_I => CLK0_O, - SDRAM_CLK270_I => CLK270_O, - SDRAM_CLK270VAR_I => CLK270VAR_O, - - CYC_I => CYC_O, - STB_I => STB_O, - SEL_I => SEL_O, - WE_I => WE_O, - ACK_O => ACK_I, - SRDY_O => SRDY_I, - MRDY_I => MRDY_O, - ADDR_I => ADDR_O, - DAT_I => DAT_O, - DAT_O => DAT_I, - - -- SDRAM signals - sd_clk_p => part_clk_p, - sd_clk_n => part_clk_n, - sd_cke => part_cke, - sd_cs_n => part_cs_n, - sd_cas_n => part_cas_n, - sd_ras_n => part_ras_n, - sd_we_n => part_we_n, - sd_addr => part_addr, - sd_ba => part_ba, - sd_dm => part_dm, - sd_dqs => part_dqs, - sd_data => part_data - - ); - - -- MICRON DDR SDRAM Simulation Model -i_mt46v16m16_0 : entity work.mt46v16m16 - port map - ( - dq => std_logic_vector(part_data(15 downto 0)), - dqs => std_logic_vector(part_dqs(1 downto 0)), - addr => std_logic_vector(part_addr), - ba => std_logic_vector(part_ba), - clk => part_clk_p, - clk_n => part_clk_n, - cke => part_cke, - cs_n => part_cs_n, - ras_n => part_ras_n, - cas_n => part_cas_n, - we_n => part_we_n, - dm => std_logic_vector(part_dm(1 downto 0)) - ); - - -- MICRON DDR SDRAM Simulation Model -i_mt46v16m16_1 : entity work.mt46v16m16 - port map - ( - dq => std_logic_vector(part_data(31 downto 16)), - dqs => std_logic_vector(part_dqs(3 downto 2)), - addr => std_logic_vector(part_addr), - ba => std_logic_vector(part_ba), - clk => part_clk_p, - clk_n => part_clk_n, - cke => part_cke, - cs_n => part_cs_n, - ras_n => part_ras_n, - cas_n => part_cas_n, - we_n => part_we_n, - dm => std_logic_vector(part_dm(3 downto 2)) - ); - -CLK_GEN: process - begin - wait for CLK_PERIOD/2; - clk <= not clk; - end process; - -SDCLK_GEN: process - begin - wait for SDCLK_PERIOD/2; - sdclk <= not sdclk; - end process; - -read_register: - process(CLK_O) - begin - if rising_edge(CLK_O) then - if dout_rst = '1' then - dout_cnt <= 0; - elsif ACK_I = '1' and WE_O = '0' then - dout_reg <= DAT_I; - dout_cnt <= dout_cnt + 1; - end if; - end if; - end process; - ------------------------------------------------------------------------------------------- - -STIMULUS: process - - begin - - wait for 3*CLK_PERIOD; - rst <= '0'; - - wait until RST_O = '0'; - -- 8 single cycles - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '1'; - DAT_O <= X"1234_0000"; - ADDR_O <= X"0000_0000"; - - for i in 0 to 8192 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - DAT_O <= DAT_O + 1; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O); - CYC_O <= '0'; - - ------------------------------------------------------------ - wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_0000"; - - for i in 0 to 31 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 31; - CYC_O <= '0'; - - ------------------------------------------------------------ - wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - wait until rising_edge(CLK_O); - -- 1-word burst cycle - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '1'; - SEL_O <= "0011"; - ADDR_O <= X"0000_0080"; - DAT_O <= X"DEADBEEF"; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '0'; - wait until rising_edge(CLK_O); - CYC_O <= '0'; - - ------------------------------------------------------------ - wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - wait until rising_edge(CLK_O); - -- 1-word burst cycle - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_0080"; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '0'; - wait until rising_edge(CLK_O) and ACK_I = '1'; - CYC_O <= '0'; - - ------------------------------------------------------------ - wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_0000"; - - for i in 0 to 31 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 31; - CYC_O <= '0'; - - ------------------------------------------------------------ - wait for 10*CLK_PERIOD; - ------------------------------------------------------------ - - for k in 0 to 3 loop - ------------------------------------------------------------ --- wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_0000"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 7; - CYC_O <= '0'; - - ------------------------------------------------------------ --- wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_0400"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 7; - CYC_O <= '0'; - - ------------------------------------------------------------ --- wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_0800"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 7; - CYC_O <= '0'; - - ------------------------------------------------------------ --- wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_0C00"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 7; - CYC_O <= '0'; - - end loop; - - ------------------------------------------------------------ - wait for 10*CLK_PERIOD; - ------------------------------------------------------------ - - for k in 0 to 3 loop - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_1000"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 7; - CYC_O <= '0'; - - ------------------------------------------------------------ --- wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_1400"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 7; - CYC_O <= '0'; - - ------------------------------------------------------------ --- wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_1800"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 7; - CYC_O <= '0'; - - ------------------------------------------------------------ --- wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_1C00"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 7; - CYC_O <= '0'; - - end loop; - - ------------------------------------------------------------ - wait for 10*CLK_PERIOD; - ------------------------------------------------------------ - - for k in 0 to 3 loop - ------------------------------------------------------------ --- wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '1'; - SEL_O <= "1111"; - DAT_O <= X"1111_0000"; - ADDR_O <= X"0000_0000"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - DAT_O <= DAT_O + 1; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O); - CYC_O <= '0'; - - ------------------------------------------------------------ --- wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '1'; - SEL_O <= "1111"; - DAT_O <= X"2222_0000"; - ADDR_O <= X"0000_0400"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - DAT_O <= DAT_O + 1; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O); - CYC_O <= '0'; - - ------------------------------------------------------------ --- wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '1'; - SEL_O <= "1111"; - DAT_O <= X"3333_0000"; - ADDR_O <= X"0000_0800"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - DAT_O <= DAT_O + 1; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O); - CYC_O <= '0'; - - ------------------------------------------------------------ --- wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '1'; - SEL_O <= "1111"; - DAT_O <= X"4444_0000"; - ADDR_O <= X"0000_0C00"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - DAT_O <= DAT_O + 1; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O); - CYC_O <= '0'; - - end loop; - - ------------------------------------------------------------ - wait for 10*CLK_PERIOD; - ------------------------------------------------------------ - - for k in 0 to 3 loop - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '1'; - SEL_O <= "1111"; - DAT_O <= X"1111_0000"; - ADDR_O <= X"0000_1000"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - DAT_O <= DAT_O + 1; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O); - CYC_O <= '0'; - - ------------------------------------------------------------ --- wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '1'; - SEL_O <= "1111"; - DAT_O <= X"2222_0000"; - ADDR_O <= X"0000_1400"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - DAT_O <= DAT_O + 1; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O); - CYC_O <= '0'; - - ------------------------------------------------------------ --- wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '1'; - SEL_O <= "1111"; - DAT_O <= X"3333_0000"; - ADDR_O <= X"0000_1800"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - DAT_O <= DAT_O + 1; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O); - CYC_O <= '0'; - - ------------------------------------------------------------ --- wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '1'; - SEL_O <= "1111"; - DAT_O <= X"4444_0000"; - ADDR_O <= X"0000_1C00"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - DAT_O <= DAT_O + 1; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O); - CYC_O <= '0'; - - end loop; - - ------------------------------------------------------------ - wait for 10*CLK_PERIOD; - ------------------------------------------------------------ - - for k in 0 to 3 loop - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_1000"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 7; - CYC_O <= '0'; - - ------------------------------------------------------------ --- wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_1400"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 7; - CYC_O <= '0'; - - ------------------------------------------------------------ --- wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_1800"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 7; - CYC_O <= '0'; - - ------------------------------------------------------------ --- wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_1C00"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 7; - CYC_O <= '0'; - - end loop; - - wait; - - end process; - -end architecture struct; diff --git a/lib/SDRAM/ddr_sdr_v1_5/todo.txt b/lib/SDRAM/ddr_sdr_v1_5/todo.txt deleted file mode 100644 index 62fe90a..0000000 --- a/lib/SDRAM/ddr_sdr_v1_5/todo.txt +++ /dev/null @@ -1,7 +0,0 @@ -2009-11-04 -- several async. resets recognized. Sync. resets better? - -2009-11-11 -- utag-stuff from ddr_phy to sdram_ctrl_top -- connect ddr_phy on top level to sdram_ctrl_frontend* -- u_data_req_r not nessecary (removed 2009-11-15) diff --git a/lib/SSRAM/sim/ModelSim SE .lnk b/lib/SSRAM/sim/ModelSim SE .lnk deleted file mode 100644 index 935209c2310801e57ad76e532c79f82bfed1afce..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 1447 zcmdT^T}YEr7=ETR6bck4m`JV2iUm`r+58DyYAHE4Tre+2W^U;x&V^fU!IurZ$Zq;E z2{H<^3#FTGguF=wDXc4rs4lD|qVfl|5`!q}Ip4RfANslJrgM0I&U@aU=e*xJUo`-Y zE{+@+S2*@w;8IUL`Q%hUKQXDfdOa{NB<^eFx081@IJZ{u)TsV3Zqewl(LQ6F($5u1 z$pcRku_Gtv%6ep%6}e(g-;_PbRTj>|SH&r?*V^{gS~_VmARbyQjovn&>2ns=4C?4* zM>~9IB5#0~(?eT2Y9blN%pav>SZ(DM)dxCrjixf>M{WL!j`+Q23e0%laOKl=EbA*G&>qv{uM`k{AMEIw_uXYTNKoGNn^$ zbNhmRu)FqlUsHR7*Xwav1%QC3vAMp$XlisRr*QpZHIyh@# zVW(VB(H&B2_SaF0(Q@pl6!5gG3-Tk5?&X#(o2mw0#OWR#AH3Yr@c2$@_S2Np50G}# z-TnS=`#K(oXYJ2YKAxk>T3>0iR%HEzxB^*3^!v`m;QZH07W-~PIVyOk9H`=|9+k9M zY5DW{d*o1R5_Y3UE{eS3<<-%D-iz((U*eZ}qxD4n={E*#$?AF8Li!%h2<;+xdWCXU z-4pkDfp%SQSQfe%b+ZQT&5>{{Hs_rhr{zV_FRHrg2~16-qJ;j1{ku9l7F^+H@d?U1 z5kDw9?WIviN;7Bahf#>Vs4mYNw4oC#!7!XFZq64xZ59~YyWc*#9Wc9&d5x@YW?XD;1R-m&nB<`6Z)#$h~Uz45*-*-qat93tjm RW=T-I?F7Dwt(3k<=C3#96%+sf diff --git a/lib/SSRAM/sim/tb_ssram_frontend_wb.fdo b/lib/SSRAM/sim/tb_ssram_frontend_wb.fdo deleted file mode 100644 index 9aafbb0..0000000 --- a/lib/SSRAM/sim/tb_ssram_frontend_wb.fdo +++ /dev/null @@ -1,17 +0,0 @@ -## NOTE: Do not edit this file. -## -vlib work - -# Top and TB -vcom -explicit -93 "../src/package_utility.vhd" -vcom -explicit -93 "../src/CY7C1354B.vhd" -vcom -explicit -93 "../src/ssram_frontend_wb.vhd" -vcom -explicit -93 "../src/tb_ssram_frontend_wb.vhd" - -vsim -t 1ps -lib work tb_ssram_frontend_wb -do {tb_ssram_frontend_wb.wdo} -view wave -view structure -view signals -run 6us - \ No newline at end of file diff --git a/lib/SSRAM/sim/tb_ssram_frontend_wb.wdo b/lib/SSRAM/sim/tb_ssram_frontend_wb.wdo deleted file mode 100644 index 71718ed..0000000 --- a/lib/SSRAM/sim/tb_ssram_frontend_wb.wdo +++ /dev/null @@ -1,47 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_ssram_frontend_wb/clk_o -add wave -noupdate -format Logic /tb_ssram_frontend_wb/rst_o -add wave -noupdate -format Logic /tb_ssram_frontend_wb/cyc_o -add wave -noupdate -format Logic /tb_ssram_frontend_wb/stb_o -add wave -noupdate -format Logic /tb_ssram_frontend_wb/we_o -add wave -noupdate -format Literal /tb_ssram_frontend_wb/sel_o -add wave -noupdate -format Logic /tb_ssram_frontend_wb/ack_i -add wave -noupdate -format Logic /tb_ssram_frontend_wb/mrdy_o -add wave -noupdate -format Logic /tb_ssram_frontend_wb/srdy_i -add wave -noupdate -format Literal -radix hexadecimal /tb_ssram_frontend_wb/addr_o -add wave -noupdate -format Literal -radix hexadecimal /tb_ssram_frontend_wb/dat_i -add wave -noupdate -format Literal -radix hexadecimal /tb_ssram_frontend_wb/dat_o -add wave -noupdate -format Literal -radix hexadecimal /tb_ssram_frontend_wb/ssram_d -add wave -noupdate -format Literal /tb_ssram_frontend_wb/ssram_dp -add wave -noupdate -format Literal -radix hexadecimal /tb_ssram_frontend_wb/ssram_a -add wave -noupdate -format Logic /tb_ssram_frontend_wb/ssram_clk -add wave -noupdate -format Logic /tb_ssram_frontend_wb/ssram_cke_n -add wave -noupdate -format Logic /tb_ssram_frontend_wb/ssram_adv -add wave -noupdate -format Logic /tb_ssram_frontend_wb/ssram_mode -add wave -noupdate -format Literal /tb_ssram_frontend_wb/ssram_bw_n -add wave -noupdate -format Logic /tb_ssram_frontend_wb/ssram_we_n -add wave -noupdate -format Logic /tb_ssram_frontend_wb/ssram_oe_n -add wave -noupdate -format Logic /tb_ssram_frontend_wb/ssram_ce_n -add wave -noupdate -format Logic /tb_ssram_frontend_wb/ssram_zz -add wave -noupdate -format Literal -radix hexadecimal /tb_ssram_frontend_wb/dout_reg -add wave -noupdate -format Literal -radix unsigned /tb_ssram_frontend_wb/dout_cnt -add wave -noupdate -format Literal /tb_ssram_frontend_wb/inst_ssram_frontend_wb/vld_pipe -add wave -noupdate -format Logic /tb_ssram_frontend_wb/ssram_clk_fb -add wave -noupdate -format Logic /tb_ssram_frontend_wb/ssram_clk -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {1343191 ps} 0} {{Cursor 2} {178651436 ps} 0} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -update -WaveRestoreZoom {0 ps} {6300 ns} diff --git a/lib/SSRAM/src/CY7C1354B.vhd b/lib/SSRAM/src/CY7C1354B.vhd deleted file mode 100644 index d652656..0000000 --- a/lib/SSRAM/src/CY7C1354B.vhd +++ /dev/null @@ -1,388 +0,0 @@ ------------------------------------------------------------------------------------------ --- --- File Name: CY7C1354B.VHD --- Version: 2.0 --- Date: Nov 22nd, 2004 --- Model: BUS Functional --- --- --- Author: RKF --- Company: Cypress Semiconductor --- Model: CY7C1354B (256k x 36) --- Mode: Pipelined --- --- Description: NoBL SRAM VHDL Model --- --- Limitation: None --- --- Note: - BSDL Model available separately --- - Set simulator resolution to "ps" timescale --- --- Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY --- WHATSOEVER AND CYPRESS SPECIFICALLY DISCLAIMS ANY --- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR --- A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT. --- --- Copyright (c) 2004 Cypress Semiconductor --- All rights reserved --- --- Trademarks: NoBL and No Bus Latency are trademarks of Cypress Semiconductor --- --- Rev Author Date Changes --- --- -------- ------- ---------- --- 2.0 RKF 11/22/2004 - Second Release --- - Fully Tested with New Test Bench and Test Vectors ------------------------------------------------------------------------------------------ - -LIBRARY ieee,work; - USE ieee.std_logic_1164.all; - USE ieee.std_logic_unsigned.all; - Use IEEE.Std_Logic_Arith.all; --- Use work.all; - USE work.package_utility.all; - -ENTITY cy7c1354 IS - - GENERIC ( - - -- Constant parameters - addr_bits : INTEGER := 18; - data_bits : INTEGER := 32; - par_bits : INTEGER := 4; - - -- Timing parameters for -5 (225 Mhz) --- tCYC : TIME := 4.4 ns; --- tCH : TIME := 1.8 ns; --- tCL : TIME := 1.8 ns; --- tCO : TIME := 2.8 ns; --- tAS : TIME := 1.4 ns; --- tCENS : TIME := 1.4 ns; --- tWES : TIME := 1.4 ns; --- tDS : TIME := 1.4 ns; --- tAH : TIME := 0.4 ns; --- tCENH : TIME := 0.4 ns; --- tWEH : TIME := 0.4 ns; --- tDH : TIME := 0.4 ns - - - - -- Timing parameters for -6 (200 Mhz) - --tCYC : TIME := 5.0 ns; - --tCH : TIME := 2.0 ns; - --tCL : TIME := 2.0 ns; - --tCO : TIME := 3.2 ns; - --tAS : TIME := 1.5 ns; - --tCENS : TIME := 1.5 ns; - --tWES : TIME := 1.5 ns; - --tDS : TIME := 1.5 ns; - --tAH : TIME := 0.5 ns; - --tCENH : TIME := 0.5 ns; - --tWEH : TIME := 0.5 ns; - --tDH : TIME := 0.5 ns - - - -- Timing parameters for -7 (166 Mhz) - tCYC : TIME := 6.0 ns; - tCH : TIME := 2.4 ns; - tCL : TIME := 2.4 ns; - tCO : TIME := 3.5 ns; - tAS : TIME := 1.5 ns; - tCENS : TIME := 1.5 ns; - tWES : TIME := 1.5 ns; - tDS : TIME := 1.5 ns; - tAH : TIME := 0.5 ns; - tCENH : TIME := 0.5 ns; - tWEH : TIME := 0.5 ns; - tDH : TIME := 0.5 ns - - - - ); - - -- Port Declarations - PORT ( - Dq : INOUT STD_LOGIC_VECTOR ((data_bits - 1) DOWNTO 0); -- Data I/O - Dpq : INOUT STD_LOGIC_VECTOR ((par_bits - 1) DOWNTO 0); -- Data parity I/O - Addr : IN STD_LOGIC_VECTOR ((addr_bits - 1) DOWNTO 0); -- Address - Mode : IN STD_LOGIC := '1'; -- Burst Mode - Clk : IN STD_LOGIC; -- Clk - CEN_n : IN STD_LOGIC; -- CEN# - AdvLd_n : IN STD_LOGIC; -- Adv/Ld# - Bwa_n : IN STD_LOGIC; -- Bwa# - Bwb_n : IN STD_LOGIC; -- BWb# - Bwc_n : IN STD_LOGIC; -- Bwc# - Bwd_n : IN STD_LOGIC; -- BWd# - Rw_n : IN STD_LOGIC; -- RW# - Oe_n : IN STD_LOGIC; -- OE# - Ce1_n : IN STD_LOGIC; -- CE1# - Ce2 : IN STD_LOGIC; -- CE2 - Ce3_n : IN STD_LOGIC; -- CE3# - Zz : IN STD_LOGIC -- Snooze Mode - ); -END cy7c1354; - -ARCHITECTURE behave OF cy7c1354 IS - SIGNAL ce : STD_LOGIC := '0'; - SIGNAL doe : STD_LOGIC := '0'; - SIGNAL dout : STD_LOGIC_VECTOR ((data_bits - 1) DOWNTO 0) := (OTHERS => 'Z'); - SIGNAL dout_p : STD_LOGIC_VECTOR ((par_bits - 1) DOWNTO 0) := (OTHERS => 'Z'); - SIGNAL Addr_read_sig : STD_LOGIC_VECTOR ((addr_bits - 1) DOWNTO 0) := (OTHERS => 'Z'); - -BEGIN - - - ce <= NOT(Ce1_n) AND NOT(Ce3_n) AND Ce2; - - doe <= NOT(Oe_n) AND NOT(Zz); - - -- Output Buffers - WITH doe SELECT - Dq <= TRANSPORT dout AFTER (tCO) WHEN '1', - (OTHERS => 'Z') AFTER (tCO) WHEN OTHERS; - - WITH doe SELECT - Dpq <= TRANSPORT dout_p AFTER (tCO) WHEN '1', - (OTHERS => 'Z') AFTER (tCO) WHEN OTHERS; - - - -- Check for Clock Timing Violation - clk_check : PROCESS - VARIABLE clk_high, clk_low : TIME := 0 ns; - BEGIN - WAIT ON Clk; - IF Clk = '1' AND NOW >= tCYC THEN - ASSERT (NOW - clk_low >= tCH) - REPORT "Clk width low - tCH violation" - SEVERITY ERROR; - ASSERT (NOW - clk_high >= tCYC) - REPORT "Clk period high - tCYC violation" - SEVERITY ERROR; - clk_high := NOW; - ELSIF Clk = '0' AND NOW /= 0 ns THEN - ASSERT (NOW - clk_high >= tCL) - REPORT "Clk width high - tCL violation" - SEVERITY ERROR; - ASSERT (NOW - clk_low >= tCYC) - REPORT "Clk period low - tCYC violation" - SEVERITY ERROR; - clk_low := NOW; - END IF; - END PROCESS; - - -- Check for Setup Timing Violation - setup_check : PROCESS - BEGIN - WAIT ON Clk; - IF Clk = '1' and (Ce1_n = '0' and Ce2 = '1' and Ce3_n = '0') THEN - ASSERT (Addr'LAST_EVENT >= tAS) - REPORT "Addr - tAS violation" - SEVERITY ERROR; - ASSERT (CEN_n'LAST_EVENT >= tCENS) - REPORT "CKE# - tCENS violation" - SEVERITY ERROR; - ASSERT (Ce1_n'LAST_EVENT >= tWES) - REPORT "CE1# - tWES violation" - SEVERITY ERROR; - ASSERT (Ce2'LAST_EVENT >= tWES) - REPORT "CE2 - tWES violation" - SEVERITY ERROR; - ASSERT (Ce3_n'LAST_EVENT >= tWES) - REPORT "CE3# - tWES violation" - SEVERITY ERROR; - ASSERT (AdvLd_n'LAST_EVENT >= tWES) - REPORT "ADV/LD# - tWES violation" - SEVERITY ERROR; - ASSERT (Rw_n'LAST_EVENT >= tWES) - REPORT "RW# - tWES violation" - SEVERITY ERROR; - ASSERT (Bwa_n'LAST_EVENT >= tWES) - REPORT "BWa# - tWES violation" - SEVERITY ERROR; - ASSERT (Bwb_n'LAST_EVENT >= tWES) - REPORT "BWb# - tWES violation" - SEVERITY ERROR; - ASSERT (Bwc_n'LAST_EVENT >= tWES) - REPORT "BWc# - tWES violation" - SEVERITY ERROR; - ASSERT (Bwd_n'LAST_EVENT >= tWES) - REPORT "BWd# - tWES violation" - SEVERITY ERROR; - ASSERT (Dq'LAST_EVENT >= tDS) - REPORT "Dq - tDS violation" - SEVERITY ERROR; - END IF; - END PROCESS; - - -- Check for Hold Timing Violation - hold_check : PROCESS - BEGIN - WAIT ON Clk'DELAYED(tAH), Clk'DELAYED(tCENH), Clk'DELAYED(tWEH), Clk'DELAYED(tDH); - IF Clk'DELAYED(tAH) = '1' THEN - ASSERT (Addr'LAST_EVENT > tAH) - REPORT "Addr - tAH violation" - SEVERITY ERROR; - END IF; - IF Clk'DELAYED(tCENH) = '1' THEN - ASSERT (CEN_n'LAST_EVENT > tCENH) - REPORT "CKE# - tCENH violation" - SEVERITY ERROR; - END IF; - IF Clk'DELAYED(tDH) = '1' THEN - ASSERT (Dq'LAST_EVENT > tDH) - REPORT "Dq - tDH violation" - SEVERITY ERROR; - END IF; - IF Clk'DELAYED(tWEH) = '1' THEN - ASSERT (Ce1_n'LAST_EVENT > tWEH) - REPORT "CE1# - tWEH violation" - SEVERITY ERROR; - ASSERT (Ce2'LAST_EVENT > tWEH) - REPORT "CE2 - tWEH violation" - SEVERITY ERROR; - ASSERT (Ce3_n'LAST_EVENT > tWEH) - REPORT "CE3 - tWEH violation" - SEVERITY ERROR; - ASSERT (AdvLd_n'LAST_EVENT > tWEH) - REPORT "ADV/LD# - tWEH violation" - SEVERITY ERROR; - ASSERT (Rw_n'LAST_EVENT > tWEH) - REPORT "RW# - tWEH violation" - SEVERITY ERROR; - ASSERT (Bwa_n'LAST_EVENT > tWEH) - REPORT "BWa# - tWEH violation" - SEVERITY ERROR; - ASSERT (Bwb_n'LAST_EVENT > tWEH) - REPORT "BWb# - tWEH violation" - SEVERITY ERROR; - ASSERT (Bwc_n'LAST_EVENT > tWEH) - REPORT "BWc# - tWEH violation" - SEVERITY ERROR; - ASSERT (Bwd_n'LAST_EVENT > tWEH) - REPORT "BWd# - tWEH violation" - SEVERITY ERROR; - END IF; - - END PROCESS; - - -- Main Program - main : PROCESS - - TYPE memory_array IS ARRAY ((2**addr_bits) - 1 DOWNTO 0) OF STD_LOGIC_VECTOR (((data_bits+par_bits) / 4) - 1 DOWNTO 0); - - VARIABLE Addr_in : STD_LOGIC_VECTOR ((addr_bits - 1) DOWNTO 0) := (OTHERS => '0'); - VARIABLE first_Addr : STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '0'); - VARIABLE Addr_read : STD_LOGIC_VECTOR ((addr_bits - 1) DOWNTO 0) := (OTHERS => '0'); - VARIABLE Addr_write : STD_LOGIC_VECTOR ((addr_bits - 1) DOWNTO 0) := (OTHERS => '0'); - VARIABLE bAddr0, bAddr1 : STD_LOGIC := '0'; - VARIABLE bank0 : memory_array; - VARIABLE bank1 : memory_array; - VARIABLE bank2 : memory_array; - VARIABLE bank3 : memory_array; - - VARIABLE ce_in : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"; - VARIABLE rw_in : STD_LOGIC_VECTOR (2 DOWNTO 0) := "111"; - VARIABLE bwa_in : STD_LOGIC_VECTOR (2 DOWNTO 0) := "000"; - VARIABLE bwb_in : STD_LOGIC_VECTOR (2 DOWNTO 0) := "000"; - VARIABLE bwc_in : STD_LOGIC_VECTOR (2 DOWNTO 0) := "000"; - VARIABLE bwd_in : STD_LOGIC_VECTOR (2 DOWNTO 0) := "000"; - VARIABLE bcnt : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"; - - BEGIN - WAIT ON Clk; - IF Clk'EVENT AND Clk = '1' THEN - IF CEN_n = '0' AND Zz = '0' THEN - -- Write Address Register - Addr_write := Addr_read; - - -- Read Address Register - Addr_read := Addr_in ((addr_bits - 1) DOWNTO 2) & bAddr1 & bAddr0; - - -- Address Register - IF AdvLd_n = '0' and ce = '1' THEN - Addr_in := Addr; - first_Addr := Addr(1 DOWNTO 0); - bcnt := Addr(1 DOWNTO 0); - END IF; - - - -- Burst Logic - IF Mode = '0' AND AdvLd_n = '1' THEN - bcnt := bcnt + 1; - ELSIF Mode = '1' AND AdvLd_n = '1' THEN - IF (CONV_INTEGER1 (first_Addr) REM 2 = 0) THEN - bcnt := bcnt + 1; - ELSIF (CONV_INTEGER1 (first_Addr) REM 2 = 1) THEN - bcnt := bcnt - 1; - END IF; - END IF; - - - bAddr1 := bcnt (1); - bAddr0 := bcnt (0); - - -- Read Logic - ce_in (0) := ce_in (1); - - IF AdvLd_n = '0' THEN - ce_in (1) := ce; - END IF; - - rw_in (0) := rw_in (1); - rw_in (1) := rw_in (2); - - IF AdvLd_n = '0' THEN - rw_in (2) := NOT(ce AND NOT(Rw_n)); - END IF; - - -- Write Registry and Data Coherency Control Logic - bwa_in (0) := bwa_in (1); - bwb_in (0) := bwb_in (1); - bwc_in (0) := bwc_in (1); - bwd_in (0) := bwd_in (1); - bwa_in (1) := bwa_in (2); - bwb_in (1) := bwb_in (2); - bwc_in (1) := bwc_in (2); - bwd_in (1) := bwd_in (2); - bwa_in (2) := Bwa_n; - bwb_in (2) := Bwb_n; - bwc_in (2) := Bwc_n; - bwd_in (2) := Bwd_n; - - -- Write Data to Memory - IF rw_in (0) = '0' AND bwa_in (0) = '0' THEN - bank0 (CONV_INTEGER1 (Addr_write)) := Dpq(0) & Dq ( (data_bits / 4) - 1 DOWNTO 0); - END IF; - IF rw_in (0) = '0' AND bwb_in (0) = '0' THEN - bank1 (CONV_INTEGER1 (Addr_write)) := Dpq(1) & Dq ((data_bits / 2 - 1) DOWNTO (data_bits / 4)); - END IF; - IF rw_in (0) = '0' AND bwc_in (0) = '0' THEN - bank2 (CONV_INTEGER1 (Addr_write)) := Dpq(2) & Dq ((3 * (data_bits / 4)) - 1 DOWNTO (data_bits / 2)); - END IF; - IF rw_in (0) = '0' AND bwd_in (0) = '0' THEN - bank3 (CONV_INTEGER1 (Addr_write)) := Dpq(3) & Dq (data_bits - 1 DOWNTO (3 * (data_bits / 4))); - END IF; - END IF; - - Addr_read_sig <= Addr_read; - - -- Read Data from Memory Array - IF ce_in (0) = '1' AND rw_in (1) = '1' THEN - dout ((data_bits / 4) - 1 DOWNTO 0) <= bank0 (CONV_INTEGER1 (Addr_read))( (data_bits / 4) - 1 DOWNTO 0); - dout ((data_bits / 2 - 1) DOWNTO (data_bits / 4)) <= bank1 (CONV_INTEGER1 (Addr_read))( (data_bits / 4) - 1 DOWNTO 0); - dout ((3 * (data_bits / 4)) - 1 DOWNTO (data_bits / 2)) <= bank2 (CONV_INTEGER1 (Addr_read))( (data_bits / 4) - 1 DOWNTO 0); - dout (data_bits - 1 DOWNTO (3 * (data_bits / 4))) <= bank3 (CONV_INTEGER1 (Addr_read))( (data_bits / 4) - 1 DOWNTO 0); - dout_p(0) <= bank0 (CONV_INTEGER1 (Addr_read))(data_bits / 4); - dout_p(1) <= bank1 (CONV_INTEGER1 (Addr_read))(data_bits / 4); - dout_p(2) <= bank2 (CONV_INTEGER1 (Addr_read))(data_bits / 4); - dout_p(3) <= bank3 (CONV_INTEGER1 (Addr_read))(data_bits / 4); - ELSE - dout <= (OTHERS => 'Z'); - dout_p <= (OTHERS => 'Z'); - END IF; - END IF; - END PROCESS; - -END behave; - - - diff --git a/lib/SSRAM/src/package_utility.vhd b/lib/SSRAM/src/package_utility.vhd deleted file mode 100644 index 9fb543f..0000000 --- a/lib/SSRAM/src/package_utility.vhd +++ /dev/null @@ -1,73 +0,0 @@ ---**************************************************************** ---** MODEL : package_utility ** ---** COMPANY : Cypress Semiconductor ** ---** REVISION: 1.0 Created new package utility model ** ---** ** ---**************************************************************** -Library ieee,work; - Use ieee.std_logic_1164.all; - Use IEEE.Std_Logic_Arith.all; - Use IEEE.std_logic_TextIO.all; - --- Use work.package_timing.all; - -Library Std; - Use STD.TextIO.all; - -Package package_utility is - -FUNCTION convert_string( S: in STRING) RETURN STD_LOGIC_VECTOR; -FUNCTION CONV_INTEGER1(S : STD_LOGIC_VECTOR) RETURN INTEGER; - -End; -- package package_utility - -Package body package_utility is - - ------------------------------------------------------------------------------------------------- ---Converts string into std_logic_vector ------------------------------------------------------------------------------------------------- - -FUNCTION convert_string(S: in STRING) RETURN STD_LOGIC_VECTOR IS - VARIABLE result : STD_LOGIC_VECTOR(S'RANGE); - BEGIN - FOR i IN S'RANGE LOOP - IF S(i) = '0' THEN - result(i) := '0'; - ELSIF S(i) = '1' THEN - result(i) := '1'; - ELSIF S(i) = 'X' THEN - result(i) := 'X'; - ELSE - result(i) := 'Z'; - END IF; - END LOOP; - RETURN result; -END convert_string; - ------------------------------------------------------------------------------------------------- ---Converts std_logic_vector into integer ------------------------------------------------------------------------------------------------- - -FUNCTION CONV_INTEGER1(S : STD_LOGIC_VECTOR) RETURN INTEGER IS - VARIABLE result : INTEGER := 0; - BEGIN - FOR i IN S'RANGE LOOP - IF S(i) = '1' THEN - result := result + (2**i); - ELSIF S(i) = '0' THEN - result := result; - ELSE - result := 0; - END IF; - END LOOP; - RETURN result; - END CONV_INTEGER1; - - - - -end package_utility; - - - - diff --git a/lib/SSRAM/src/ssram_frontend_wb.vhd b/lib/SSRAM/src/ssram_frontend_wb.vhd deleted file mode 100644 index 056b328..0000000 --- a/lib/SSRAM/src/ssram_frontend_wb.vhd +++ /dev/null @@ -1,181 +0,0 @@ -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -Library UNISIM; -use UNISIM.vcomponents.all; - -ENTITY ssram_frontend_wb IS - Generic - ( - latency : natural := 2; -- clock cycles - addr_width : natural := 20; - data_width : natural := 32; - parity_width : natural := 4 - ); - Port - ( - -- J-Bus domain - CLK_I : in STD_LOGIC; - RST_I : in STD_LOGIC; - CYC_I : in STD_LOGIC; - STB_I : in STD_LOGIC; - SEL_I : in unsigned(3 downto 0); - WE_I : in STD_LOGIC; - ACK_O : out STD_LOGIC; - SRDY_O : out STD_LOGIC; - MRDY_I : in STD_LOGIC; - ADDR_I : in unsigned(31 downto 0); - DAT_I : in unsigned(31 downto 0); - DAT_O : out unsigned(31 downto 0); - - -- Sync SRAM domain - ssram_clk_o : out std_logic; - ssram_clk_fb : in std_logic; - ssram_cke_n : out std_logic; - ssram_ce_n : out std_logic; - ssram_oe_n : out std_logic; - ssram_we_n : out std_logic; - ssram_adv : out std_logic; - ssram_mode : out std_logic; - ssram_zz : out std_logic; - ssram_a : out unsigned(addr_width-1 downto 0); - ssram_d : inout unsigned(data_width-1 downto 0); - ssram_dp : inout unsigned(parity_width-1 downto 0); - ssram_bw_n : out unsigned(3 downto 0) - ); -END ssram_frontend_wb; - -ARCHITECTURE behavior OF ssram_frontend_wb IS - - constant topad : time := 3 ns; - subtype ssram_d_t is unsigned(data_width+parity_width-1 downto 0); - type data_pipe_t is array (latency downto 0) of ssram_d_t; - - signal ssram_clk : std_logic; - signal dcm_locked : std_logic; - signal dcm_clk0 : std_logic; - signal dcm_clk1 : std_logic; - signal data_en : std_logic; - signal drive : std_logic; - signal vld_pipe : unsigned(latency downto 0); - signal drive_pipe : unsigned(latency downto 0); - signal data_pipe : data_pipe_t; - signal ssram_dout : ssram_d_t; - -begin - - SRDY_O <= CYC_I and dcm_locked; - ACK_O <= vld_pipe(vld_pipe'left); - DAT_O(data_width-1 downto 0) <= ssram_d; - - data_en <= CYC_I and STB_I; - ssram_dout <= "0000" & DAT_I(data_width-1 downto 0); - drive <= drive_pipe(drive_pipe'left); - - ssram_clk_o <= ssram_clk after topad; - ssram_cke_n <= not dcm_locked after topad; - ssram_oe_n <= not vld_pipe(vld_pipe'left-1) after topad; - -inst_clock_out : ODDR - generic map - ( - DDR_CLK_EDGE => "OPPOSITE_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE" - INIT => '0', -- Initial value for Q port ('1' or '0') - SRTYPE => "SYNC" -- Reset Type ("ASYNC" or "SYNC") - ) - port map ( - Q => ssram_clk, -- 1-bit DDR output - C => dcm_clk1, -- 1-bit clock input - CE => '1', -- 1-bit clock enable input - D1 => '1', -- 1-bit data input (positive edge) - D2 => '0', -- 1-bit data input (negative edge) - R => '0', -- 1-bit reset input - S => '0' -- 1-bit set input - ); - -ssram_bufg: bufg - port map - ( - o => dcm_clk1, - i => dcm_clk0 - ); - -inst_DCM_BASE_0 : DCM_BASE - generic map ( - CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 - -- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 - CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32 - CLKFX_MULTIPLY => 4, -- Can be any integer from 2 to 32 - CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature - CLKIN_PERIOD => 10.0 , -- Specify period of input clock in ns from 1.25 to 1000.00 - CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift mode of NONE or FIXED - CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X - DCM_AUTOCALIBRATION => TRUE, -- DCM calibrartion circuitry TRUE/FALSE - DCM_PERFORMANCE_MODE => "MAX_SPEED", -- Can be MAX_SPEED or MAX_RANGE - DESKEW_ADJUST => "SOURCE_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or - -- an integer from 0 to 15 - DFS_FREQUENCY_MODE => "LOW", -- LOW or HIGH frequency mode for frequency synthesis - DLL_FREQUENCY_MODE => "LOW", -- LOW, HIGH, or HIGH_SER frequency mode for DLL - DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE - FACTORY_JF => X"F0F0", -- FACTORY JF Values Suggested to be set to X"F0F0" - PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 1023 - STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE - port map ( - CLK0 => dcm_clk0, -- 0 degree DCM CLK ouptput - CLK180 => open, -- 180 degree DCM CLK output - CLK270 => open, -- 270 degree DCM CLK output - CLK2X => open, -- 2X DCM CLK output - CLK2X180 => open, -- 2X, 180 degree DCM CLK out - CLK90 => open, -- 90 degree DCM CLK output - CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE) - CLKFX => open, -- DCM CLK synthesis out (M/D) - CLKFX180 => open, -- 180 degree CLK synthesis out - LOCKED => dcm_locked, -- DCM LOCK status output - CLKFB => ssram_clk_fb, -- DCM clock feedback - CLKIN => CLK_I, -- Clock input (from IBUFG, BUFG or DCM) - RST => RST_I -- DCM asynchronous reset input - ); - - -data_valid_pipeline: - process(CLK_I) - begin - if rising_edge(CLK_I) then - if RST_I = '1' then - vld_pipe <= (others => '0'); - else - vld_pipe <= vld_pipe(vld_pipe'left-1 downto 0) & (data_en and MRDY_I and not WE_I); - end if; - end if; - end process; - -data_out_pipeline: - process(CLK_I) - begin - if rising_edge(CLK_I) then - if RST_I = '1' then - ssram_ce_n <= '1' after topad; - ssram_we_n <= '1' after topad; - ssram_adv <= '0' after topad; - ssram_mode <= '0' after topad; - ssram_zz <= '1' after topad; - drive_pipe <= (others => '0'); - elsif dcm_locked = '1' then - ssram_ce_n <= not data_en after topad; - ssram_we_n <= not (WE_I and data_en) after topad; - ssram_adv <= '0' after topad; - ssram_mode <= '0' after topad; - ssram_zz <= '0' after topad; - ssram_a <= ADDR_I(addr_width-1 downto 0) after topad; - ssram_bw_n <= not SEL_I after topad; - drive_pipe <= drive_pipe(drive_pipe'left-1 downto 0) & (data_en and WE_I); - data_pipe <= data_pipe(data_pipe'left-1 downto 0) & ssram_dout; - end if; - end if; - end process; - - ssram_d <= data_pipe(data_pipe'left)(data_width-1 downto 0) after topad when drive = '1' else (others => 'Z') after topad; - ssram_dp <= data_pipe(data_pipe'left)(data_width+parity_width-1 downto data_width) after topad when drive = '1' else (others => 'Z') after topad; - -end behavior; diff --git a/lib/SSRAM/src/tb_ssram_frontend_wb.vhd b/lib/SSRAM/src/tb_ssram_frontend_wb.vhd deleted file mode 100644 index 86f1411..0000000 --- a/lib/SSRAM/src/tb_ssram_frontend_wb.vhd +++ /dev/null @@ -1,457 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: testbench for system test using Xilinx ML-402 - --- Copyright (C) 2007 J. Ahrensfeld - --- This library is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. - --- This library is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. - --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the Free Software --- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - --- For questions and ideas, please contact the author at jens@jayfield.org - ------------------------------------------------------------------------ - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; -USE work.package_utility.all; - -Library UNISIM; -use UNISIM.vcomponents.all; - -ENTITY tb_ssram_frontend_wb IS -END tb_ssram_frontend_wb; - -ARCHITECTURE behavior OF tb_ssram_frontend_wb IS - - constant CLK_PERIOD : time := 10 ns; - signal CLK_O : std_logic := '1'; - signal RST_O : std_logic := '1'; - signal CYC_O : std_logic := '0'; - signal STB_O : std_logic := '0'; - signal WE_O : std_logic := '0'; - signal SEL_O : unsigned(3 downto 0) := (others => '1'); - signal ACK_I : std_logic; - signal MRDY_O : std_logic := '1'; - signal SRDY_I : std_logic; - signal ADDR_O : unsigned(31 downto 0) := (others => '-'); - signal DAT_I : unsigned(31 downto 0); - signal DAT_O : unsigned(31 downto 0) := (others => '-'); - - SIGNAL ssram_d : unsigned (32 - 1 DOWNTO 0) := (OTHERS => 'Z'); - SIGNAL ssram_dp : unsigned (4 - 1 DOWNTO 0) := (OTHERS => 'Z'); - SIGNAL ssram_a : unsigned (20 - 1 DOWNTO 0) := (OTHERS => '0'); - SIGNAL ssram_clk : STD_LOGIC := '0'; - SIGNAL ssram_cke_n : STD_LOGIC; - SIGNAL ssram_adv : STD_LOGIC; - SIGNAL ssram_mode : STD_LOGIC; - SIGNAL ssram_bw_n : unsigned(3 downto 0); - SIGNAL ssram_we_n : STD_LOGIC; - SIGNAL ssram_oe_n : STD_LOGIC; - SIGNAL ssram_ce_n : STD_LOGIC; - SIGNAL ssram_zz : STD_LOGIC; - - SIGNAL ssram_clk_fb : STD_LOGIC; - - signal dout_rst : std_logic := '0'; - signal dout_reg : unsigned(31 downto 0); - signal dout_cnt : natural range 0 to 255; - -BEGIN - - ssram_clk_fb <= ssram_clk after 0.5 ns; - -inst_ssram_frontend_wb : entity work.ssram_frontend_wb - GENERIC MAP - ( - addr_width => 20, - data_width => 32, - parity_width => 4 - ) - PORT MAP - ( - -- J-Bus domain - RST_I => RST_O, - CLK_I => CLK_O, - CYC_I => CYC_O, - STB_I => STB_O, - SEL_I => SEL_O, - WE_I => WE_O, - ACK_O => ACK_I, - SRDY_O => SRDY_I, - MRDY_I => MRDY_O, - ADDR_I => ADDR_O, - DAT_I => DAT_O, - DAT_O => DAT_I, - - -- Sync SRAM domain - ssram_clk_o => ssram_clk, - ssram_clk_fb => ssram_clk_fb, - ssram_cke_n => ssram_cke_n, - ssram_ce_n => ssram_ce_n, - ssram_oe_n => ssram_oe_n, - ssram_we_n => ssram_we_n, - ssram_adv => ssram_adv, - ssram_mode => ssram_mode, - ssram_zz => ssram_zz, - ssram_a => ssram_a, - ssram_d => ssram_d, - ssram_dp => ssram_dp, - ssram_bw_n => ssram_bw_n - ); - -inst_ssram : entity work.cy7c1354 - -- PORT MAP Declarations - PORT MAP - ( - Dq => STD_LOGIC_VECTOR(ssram_d), -- Data I/O - Dpq => STD_LOGIC_VECTOR(ssram_dp), -- Data I/O - Addr => STD_LOGIC_VECTOR(ssram_a(19 downto 2)), -- Address - Mode => ssram_mode, -- Burst Mode - Clk => ssram_clk, -- Clk - CEN_n => ssram_cke_n, -- CEN# - AdvLd_n => ssram_adv, -- Adv/Ld# - Bwa_n => ssram_bw_n(0), -- Bwa# - Bwb_n => ssram_bw_n(1), -- BWb# - Bwc_n => ssram_bw_n(2), -- Bwc# - Bwd_n => ssram_bw_n(3), -- BWd# - Rw_n => ssram_we_n, -- RW# - Oe_n => ssram_oe_n, -- OE# - Ce1_n => ssram_ce_n, -- CE1# - Ce2 => '1', -- CE2 - Ce3_n => '0', -- CE3# - Zz => ssram_zz - ); - -read_register: - process(CLK_O) - begin - if rising_edge(CLK_O) then - if dout_rst = '1' then - dout_cnt <= 0; - elsif ACK_I = '1' and WE_O = '0' then - dout_reg <= DAT_I; - dout_cnt <= dout_cnt + 1; - end if; - end if; - end process; - -CLK_GEN: process - begin - wait for CLK_PERIOD/2; - CLK_O <= not CLK_O; - end process; - -STIMULUS: process - - begin - - wait for 5*CLK_PERIOD; - RST_O <= '0'; - - wait until rising_edge(CLK_O); - -- 8 single cycles - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '1'; - DAT_O <= X"1234_0000"; - ADDR_O <= X"0000_0000"; - - for i in 0 to 31 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - DAT_O <= DAT_O + 1; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O); - CYC_O <= '0'; - - ------------------------------------------------------------ - wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_0000"; - - for i in 0 to 31 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 31; - CYC_O <= '0'; - - ------------------------------------------------------------ - wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - wait until rising_edge(CLK_O); - -- 1-word burst cycle - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '1'; - SEL_O <= "0011"; - ADDR_O <= X"0000_0010"; - DAT_O <= X"DEADBEEF"; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '0'; - wait until rising_edge(CLK_O); - CYC_O <= '0'; - - ------------------------------------------------------------ - wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - wait until rising_edge(CLK_O); - -- 1-word burst cycle - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_0010"; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '0'; - wait until rising_edge(CLK_O) and ACK_I = '1'; - CYC_O <= '0'; - - ------------------------------------------------------------ - wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_0000"; - - for i in 0 to 31 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 31; - CYC_O <= '0'; - - ------------------------------------------------------------ - wait for 10*CLK_PERIOD; - ------------------------------------------------------------ - - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_0000"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 7; - CYC_O <= '0'; - - - ------------------------------------------------------------ - wait for 10*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '1'; - SEL_O <= "1111"; - DAT_O <= X"1111_0000"; - ADDR_O <= X"0000_0000"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - DAT_O <= DAT_O + 1; - ADDR_O <= ADDR_O + 4; - end loop; - - WE_O <= '0'; - ADDR_O <= X"0000_0000"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 7; - CYC_O <= '0'; - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '1'; - SEL_O <= "1111"; - DAT_O <= X"2222_0000"; - ADDR_O <= X"0000_0400"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - DAT_O <= DAT_O + 1; - ADDR_O <= ADDR_O + 4; - end loop; - - WE_O <= '0'; - ADDR_O <= X"0000_0400"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 7; - CYC_O <= '0'; - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '1'; - SEL_O <= "1111"; - DAT_O <= X"3333_0000"; - ADDR_O <= X"0000_0800"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - DAT_O <= DAT_O + 1; - ADDR_O <= ADDR_O + 4; - end loop; - - WE_O <= '0'; - ADDR_O <= X"0000_0800"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 7; - CYC_O <= '0'; - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '1'; - SEL_O <= "1111"; - DAT_O <= X"4444_0000"; - ADDR_O <= X"0000_0C00"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - DAT_O <= DAT_O + 1; - ADDR_O <= ADDR_O + 4; - end loop; - - WE_O <= '0'; - ADDR_O <= X"0000_0C00"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 7; - CYC_O <= '0'; - - ------------------------------------------------------------ - wait for 10*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_0000"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - end loop; - - ADDR_O <= X"0000_0400"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - end loop; - - - ADDR_O <= X"0000_0800"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - end loop; - - - ADDR_O <= X"0000_0C00"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 31; - CYC_O <= '0'; - - wait; - - end process; - -END; diff --git a/lib/VGA_ctrl/sim/ModelSim SE .lnk b/lib/VGA_ctrl/sim/ModelSim SE .lnk deleted file mode 100644 index 0a329502962c27f43d6954378270457c758fb048..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 1453 zcmdT^T}V@57=EWGQ7D+WV2RXpz!%PlzBz>Dn0 z%p}Ap%r2B}yfN~|6r!-MB%-=7iipY|v>)jrih90tw$l&&+;r1-c)$1k-rwhY&-Z<` zM5NMWU?!TDX4-ciOC4nOso9wB){N@%)z~8AbdM9?&fHN^?^?-ICHpJ0U8SK-o@ee^ z-GWU}4?oVPohH+z4OCcZ^C?c>guPTGExgv3<+M@x)MN#B9cYMcv!AH)CkT->+xekjE~3*%tsr#-?VPs>>Pfcp?P>>7PTf>R4xFq8 za$@DD8faY5{CWR{Ks7ujx;UOlG5T-oTAbB$ZgxJ2{TSLD4PCvh0b6s#HrA@V5@_>g-tZ zC6_a^q}#%tDG&5}(vIL3e2wS}v!!Km(ZD56uEvv~{sjX!j+mz#%O&|0I16Vr)-gdE zIW!8NsJTx(3(C&Qp#i#(Hqr~&?1f#T6LicN#|fSdb#WL0QIH^yF?Fs XzhJPKLj@IacEi`;PHY1Yr!s#9ePRv0 diff --git a/lib/VGA_ctrl/sim/tb_vga_frontend.fdo b/lib/VGA_ctrl/sim/tb_vga_frontend.fdo deleted file mode 100644 index 3108918..0000000 --- a/lib/VGA_ctrl/sim/tb_vga_frontend.fdo +++ /dev/null @@ -1,26 +0,0 @@ -## NOTE: Do not edit this file. -## Autogenerated by ProjNav (creatfdo.tcl) on Thu Jul 06 20:49:07 Westeuropäische Sommerzeit 2006 -## -vlib work -vcom -explicit -93 "../../misc/utils_pkg.vhd" -vcom -explicit -93 "../../rams/dpram_1w1r2c_ra_sim.vhd" -vcom -explicit -93 "../../rams/dpram_1w1r2c_ro_sim.vhd" -vcom -explicit -93 "../../FIFO/src/fifo_ctrl_pkg.vhd" -vcom -explicit -93 "../../FIFO/src/gray_counter.vhd" -vcom -explicit -93 "../../FIFO/src/fifo_async_ctrl.vhd" -vcom -explicit -93 "../../FIFO/src/fifo_async.vhd" -vcom -explicit -93 "../src/fonts/char_rom_c64.vhd" -vcom -explicit -93 "../src/vga_types.vhd" -vcom -explicit -93 "../src/char_gen.vhd" -vcom -explicit -93 "../src/vga_sync.vhd" -vcom -explicit -93 "../src/vga_timing.vhd" -vcom -explicit -93 "../src/vga_backend.vhd" -vcom -explicit -93 "../src/vga_frontend.vhd" -vcom -explicit -93 "../src/tb_vga_frontend.vhd" -vsim -t 1ps -lib work tb_vga_frontend -view wave -do {tb_vga_frontend.wdo} -view structure -view signals - -run 20ms diff --git a/lib/VGA_ctrl/sim/tb_vga_frontend.wdo b/lib/VGA_ctrl/sim/tb_vga_frontend.wdo deleted file mode 100644 index 227b8b3..0000000 --- a/lib/VGA_ctrl/sim/tb_vga_frontend.wdo +++ /dev/null @@ -1,79 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_vga_frontend/clk_o -add wave -noupdate -format Logic /tb_vga_frontend/rst_o -add wave -noupdate -divider Master -add wave -noupdate -format Logic /tb_vga_frontend/cyc_o -add wave -noupdate -format Logic /tb_vga_frontend/stb_o -add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend/addr_o -add wave -noupdate -format Literal /tb_vga_frontend/sel_o -add wave -noupdate -format Logic /tb_vga_frontend/we_o -add wave -noupdate -format Logic /tb_vga_frontend/ack_i -add wave -noupdate -format Logic /tb_vga_frontend/mrdy_o -add wave -noupdate -format Logic /tb_vga_frontend/srdy_i -add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend/mdat_i -add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend/mdat_o -add wave -noupdate -divider Slave -add wave -noupdate -format Logic /tb_vga_frontend/cyc_i -add wave -noupdate -format Logic /tb_vga_frontend/stb_i -add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend/addr_i -add wave -noupdate -format Literal /tb_vga_frontend/sel_i -add wave -noupdate -format Logic /tb_vga_frontend/we_i -add wave -noupdate -format Logic /tb_vga_frontend/ack_o -add wave -noupdate -format Logic /tb_vga_frontend/mrdy_i -add wave -noupdate -format Logic /tb_vga_frontend/srdy_o -add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend/sdat_i -add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend/sdat_o -add wave -noupdate -divider VGA -add wave -noupdate -format Logic /tb_vga_frontend/vga_clk -add wave -noupdate -format Logic /tb_vga_frontend/vga_blank_n -add wave -noupdate -format Logic /tb_vga_frontend/vga_sync_n -add wave -noupdate -format Logic /tb_vga_frontend/vga_hsync -add wave -noupdate -format Logic /tb_vga_frontend/vga_vsync -add wave -noupdate -format Literal -radix decimal /tb_vga_frontend/vga_red -add wave -noupdate -format Literal -radix decimal /tb_vga_frontend/vga_green -add wave -noupdate -format Literal -radix decimal /tb_vga_frontend/vga_blue -add wave -noupdate -format Literal /tb_vga_frontend/inst_vga_frontend/s -add wave -noupdate -format Literal /tb_vga_frontend/inst_vga_frontend/request_cnt -add wave -noupdate -format Literal /tb_vga_frontend/inst_vga_frontend/read_cnt -add wave -noupdate -format Logic /tb_vga_frontend/inst_vga_frontend/vga_master_en -add wave -noupdate -divider FIFO -add wave -noupdate -format Logic /tb_vga_frontend/inst_vga_frontend/fifo_full -add wave -noupdate -format Logic /tb_vga_frontend/inst_vga_frontend/fifo_empty -add wave -noupdate -format Logic /tb_vga_frontend/inst_vga_frontend/fifo_almost_empty -add wave -noupdate -format Logic /tb_vga_frontend/inst_vga_frontend/fifo_almost_full -add wave -noupdate -format Logic /tb_vga_frontend/inst_vga_frontend/fifo_color_re -add wave -noupdate -format Logic /tb_vga_frontend/inst_vga_frontend/fifo_color_we -add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend/inst_vga_frontend/fifo_color_out -add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend/inst_vga_frontend/fifo_color_in -add wave -noupdate -divider Backend -add wave -noupdate -format Logic /tb_vga_frontend/inst_vga_frontend/inst_vga_backend/ctrl_scan_en -add wave -noupdate -format Logic /tb_vga_frontend/inst_vga_frontend/inst_vga_backend/sys_rst -add wave -noupdate -format Logic /tb_vga_frontend/inst_vga_frontend/inst_vga_backend/stat_vga_rdy -add wave -noupdate -format Logic /tb_vga_frontend/inst_vga_frontend/inst_vga_backend/stat_scan -add wave -noupdate -format Logic /tb_vga_frontend/inst_vga_frontend/inst_vga_backend/scan_enable -add wave -noupdate -format Logic /tb_vga_frontend/inst_vga_frontend/inst_vga_backend/is_scan -add wave -noupdate -format Literal /tb_vga_frontend/inst_vga_frontend/stat_hpos -add wave -noupdate -format Literal /tb_vga_frontend/inst_vga_frontend/stat_vpos -add wave -noupdate -format Logic /tb_vga_frontend/inst_vga_frontend/inst_vga_backend/rst -add wave -noupdate -format Logic /tb_vga_frontend/vga_en -add wave -noupdate -format Logic /tb_vga_frontend/inst_vga_frontend/cg_draw -add wave -noupdate -format Logic /tb_vga_frontend/inst_vga_frontend/cg_en -add wave -noupdate -format Logic /tb_vga_frontend/inst_vga_frontend/inst_vga_backend/hready -add wave -noupdate -format Logic /tb_vga_frontend/inst_vga_frontend/inst_vga_backend/vready -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {9915333000 ps} 0} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -update -WaveRestoreZoom {9915291469 ps} {9915942555 ps} diff --git a/lib/VGA_ctrl/sim/tb_vga_frontend64.fdo b/lib/VGA_ctrl/sim/tb_vga_frontend64.fdo deleted file mode 100644 index 1d8256e..0000000 --- a/lib/VGA_ctrl/sim/tb_vga_frontend64.fdo +++ /dev/null @@ -1,28 +0,0 @@ -## NOTE: Do not edit this file. -## Autogenerated by ProjNav (creatfdo.tcl) on Thu Jul 06 20:49:07 Westeuropäische Sommerzeit 2006 -## -vlib work -vcom -explicit -93 "../../misc/utils_pkg.vhd" -vcom -explicit -93 "../../rams/dpram_1w1r2c_ra_sim.vhd" -vcom -explicit -93 "../../rams/dpram_1w1r2c_ro_sim.vhd" -vcom -explicit -93 "../../FIFO/src/fifo_ctrl_pkg.vhd" -vcom -explicit -93 "../../FIFO/src/gray_counter.vhd" -vcom -explicit -93 "../../FIFO/src/fifo_async_ctrl.vhd" -vcom -explicit -93 "../../FIFO/src/fifo_async.vhd" -vcom -explicit -93 "../../FIFO/src/fifo_sync_ctrl.vhd" -vcom -explicit -93 "../../FIFO/src/fifo_sync.vhd" -vcom -explicit -93 "../src/fonts/char_rom_c64.vhd" -vcom -explicit -93 "../src/vga_types.vhd" -vcom -explicit -93 "../src/char_gen.vhd" -vcom -explicit -93 "../src/vga_sync.vhd" -vcom -explicit -93 "../src/vga_timing.vhd" -vcom -explicit -93 "../src/vga_backend.vhd" -vcom -explicit -93 "../src/vga_frontend64.vhd" -vcom -explicit -93 "../src/tb_vga_frontend64.vhd" -vsim -t 1ps -lib work tb_vga_frontend64 -view wave -do {tb_vga_frontend64.wdo} -view structure -view signals - -run 2ms diff --git a/lib/VGA_ctrl/sim/tb_vga_frontend64.wdo b/lib/VGA_ctrl/sim/tb_vga_frontend64.wdo deleted file mode 100644 index ddbe21f..0000000 --- a/lib/VGA_ctrl/sim/tb_vga_frontend64.wdo +++ /dev/null @@ -1,240 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_vga_frontend64/clk_o -add wave -noupdate -format Logic /tb_vga_frontend64/rst_o -add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/read_reg -add wave -noupdate -divider Master -add wave -noupdate -format Literal /tb_vga_frontend64/state -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/cyc_o -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/srdy_i -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/stb_o -add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/sdat_o -add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/addr_o -add wave -noupdate -format Literal /tb_vga_frontend64/inst_vga_frontend64/sel_o -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/we_o -add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/sdat_i -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/mrdy_o -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/ack_i -add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/mdat_i -add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/mdat_o -add wave -noupdate -format Literal /tb_vga_frontend64/inst_vga_frontend64/s -add wave -noupdate -divider Slave -add wave -noupdate -format Literal /tb_vga_frontend64/state -add wave -noupdate -format Logic /tb_vga_frontend64/clk_o -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/int_o -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/cyc_i -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/stb_i -add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/addr_i -add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/sdat_i -add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/sdat_o -add wave -noupdate -format Literal /tb_vga_frontend64/inst_vga_frontend64/sel_i -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/we_i -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/ack_o -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/mrdy_i -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/srdy_o -add wave -noupdate -format Logic /tb_vga_frontend64/rdy -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/blit_request -add wave -noupdate -divider {Bus Output FIFO} -add wave -noupdate -format Literal /tb_vga_frontend64/state -add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/busout_fifo_din -add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/busout_fifo_dout -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/busout_fifo_re -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/busout_fifo_we -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/busout_fifo_full -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/busout_fifo_empty -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/busout_fifo_rdy -add wave -noupdate -format Literal /tb_vga_frontend64/inst_vga_frontend64/s -add wave -noupdate -divider {Bus Input FIFO} -add wave -noupdate -format Literal /tb_vga_frontend64/state -add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/busin_fifo_din -add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/busin_fifo_dout -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/busin_fifo_re -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/busin_fifo_we -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/busin_fifo_full -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/busin_fifo_empty -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/busin_fifo_rdy -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/busin_fifo_dout_vld -add wave -noupdate -format Literal /tb_vga_frontend64/inst_vga_frontend64/s -add wave -noupdate -divider VGA -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/vga_scan_dma_en -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/vga_scan_dma_en2 -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/cg_rdy -add wave -noupdate -format Logic /tb_vga_frontend64/vga_clk -add wave -noupdate -format Logic /tb_vga_frontend64/vga_blank_n -add wave -noupdate -format Logic /tb_vga_frontend64/vga_sync_n -add wave -noupdate -format Logic /tb_vga_frontend64/vga_hsync -add wave -noupdate -format Logic /tb_vga_frontend64/vga_vsync -add wave -noupdate -format Literal -radix decimal /tb_vga_frontend64/vga_red -add wave -noupdate -format Literal -radix decimal /tb_vga_frontend64/vga_green -add wave -noupdate -format Literal -radix decimal /tb_vga_frontend64/vga_blue -add wave -noupdate -format Literal -radix unsigned /tb_vga_frontend64/inst_vga_frontend64/request_cnt -add wave -noupdate -format Literal -radix unsigned /tb_vga_frontend64/inst_vga_frontend64/read_cnt -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/bus_read_fin -add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/vga_fb_back -add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/vga_fb_front -add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/host_fb_front -add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/host_fb_back -add wave -noupdate -format Literal /tb_vga_frontend64/inst_vga_frontend64/s -add wave -noupdate -divider FIFO -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/fifo_full -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/fifo_empty -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/fifo_almost_empty -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/fifo_almost_full -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/fifo_color_re -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/fifo_color_we -add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/fifo_color_out -add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/fifo_color_in -add wave -noupdate -divider {Blitter REGS} -add wave -noupdate -format Literal /tb_vga_frontend64/state -add wave -noupdate -format Logic /tb_vga_frontend64/clk_o -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/blit_reset -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/blit_src_finish -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/blit_fill_finish -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/blit_dst_finish -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/blit_request -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/blit_request_set -add wave -noupdate -format Literal /tb_vga_frontend64/inst_vga_frontend64/blit_finish_strobe -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/blit_complete_int -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/blit_complete_int_ack -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/blit_complete_int_en -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/blit_cmd_empty_int -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/blit_cmd_empty_int_ack -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/blit_cmd_empty_int_en -add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/blit_cmd_addr_src_0 -add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/blit_cmd_addr_src_1 -add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/blit_cmd_addr_dst -add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/blit_cmd_dimx_src_0 -add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/blit_cmd_dimx_src_1 -add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/blit_cmd_dimx_dst -add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/blit_cmd_cc -add wave -noupdate -format Literal -radix decimal /tb_vga_frontend64/inst_vga_frontend64/blit_cmd_nx -add wave -noupdate -format Literal -radix decimal /tb_vga_frontend64/inst_vga_frontend64/blit_cmd_ny -add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/blit_cmd_func -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/blit_const_color_en -add wave -noupdate -format Literal /tb_vga_frontend64/inst_vga_frontend64/s -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/blit_request_set -add wave -noupdate -format Literal /tb_vga_frontend64/inst_vga_frontend64/blit_finish_strobe -add wave -noupdate -divider {Blitter CMD} -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/blit_cmd_re -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/blit_cmd_we -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/blit_cmd_bsy -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/blit_cmd_avail -add wave -noupdate -divider {Blitter SRC} -add wave -noupdate -format Literal /tb_vga_frontend64/state -add wave -noupdate -format Literal -expand /tb_vga_frontend64/inst_vga_frontend64/src_dbg -add wave -noupdate -format Logic /tb_vga_frontend64/clk_o -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/blit_src_finish -add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/blit_src_cnt_x_next -add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/blit_src_cnt_y_next -add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/blit_src_cnt_x -add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/blit_src_cnt_y -add wave -noupdate -format Literal -radix decimal /tb_vga_frontend64/inst_vga_frontend64/blit_src_offset -add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/mdat_i -add wave -noupdate -format Literal /tb_vga_frontend64/inst_vga_frontend64/blit_chunk_cnt -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/blit_chunk_full -add wave -noupdate -format Logic /tb_vga_frontend64/clk_o -add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/addr_o_blit_src -add wave -noupdate -format Literal -radix decimal /tb_vga_frontend64/inst_vga_frontend64/blit_cmd_nx -add wave -noupdate -format Literal -radix decimal /tb_vga_frontend64/inst_vga_frontend64/blit_cmd_ny -add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/blit_cmd_addr_src_0 -add wave -noupdate -format Literal /tb_vga_frontend64/inst_vga_frontend64/s -add wave -noupdate -divider BLIT-FIFO -add wave -noupdate -format Literal /tb_vga_frontend64/state -add wave -noupdate -format Literal -expand /tb_vga_frontend64/inst_vga_frontend64/fill_dbg -add wave -noupdate -format Logic /tb_vga_frontend64/clk_o -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/blitfifo_write_en -add wave -noupdate -format Literal /tb_vga_frontend64/inst_vga_frontend64/blitfifo_we -add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/blitfifo_din -add wave -noupdate -format Literal /tb_vga_frontend64/inst_vga_frontend64/blitfifo_full -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/blitfifo_read_en -add wave -noupdate -format Literal /tb_vga_frontend64/inst_vga_frontend64/blitfifo_re -add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/blitfifo_dout_0 -add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/blitfifo_dout_1 -add wave -noupdate -format Literal /tb_vga_frontend64/inst_vga_frontend64/blitfifo_empty -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/blitfifo_empty_read -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/blitfifo_dout_vld -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/blit_src_finish -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/blit_fill_finish -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/blit_dst_finish -add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/blit_fill_cnt_x_next -add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/blit_fill_cnt_y_next -add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/blit_fill_cnt_x -add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/blit_fill_cnt_y -add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/blit_fill_offset -add wave -noupdate -format Literal -radix decimal /tb_vga_frontend64/inst_vga_frontend64/blit_cmd_nx -add wave -noupdate -format Literal -radix decimal /tb_vga_frontend64/inst_vga_frontend64/blit_cmd_ny -add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/blit_fill_addr -add wave -noupdate -format Literal /tb_vga_frontend64/inst_vga_frontend64/s -add wave -noupdate -divider {Blitter DST} -add wave -noupdate -format Literal /tb_vga_frontend64/state -add wave -noupdate -format Literal -expand /tb_vga_frontend64/inst_vga_frontend64/dst_dbg -add wave -noupdate -format Logic /tb_vga_frontend64/clk_o -add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/blit_cmd_cc -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/blit_const_color_en -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/request_cnt_rst -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/request_en -add wave -noupdate -format Literal -radix decimal /tb_vga_frontend64/inst_vga_frontend64/request_cnt -add wave -noupdate -format Literal -radix decimal /tb_vga_frontend64/inst_vga_frontend64/read_cnt -add wave -noupdate -format Literal /tb_vga_frontend64/inst_vga_frontend64/blit_chunk_cnt -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/blit_chunk_full -add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/blit_dst_cnt_y -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/blit_dst_finish -add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/addr_o_blit_dst -add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/blit_dst_cnt_x_next -add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/blit_dst_cnt_y_next -add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/blit_dst_cnt_x -add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/blit_dst_cnt_y -add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/blit_dst_offset -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/blit_dst_finish -add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/blit_dst_addr_next -add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/addr_o_blit_dst -add wave -noupdate -format Literal -radix decimal /tb_vga_frontend64/inst_vga_frontend64/blit_cmd_nx -add wave -noupdate -format Literal -radix decimal /tb_vga_frontend64/inst_vga_frontend64/blit_cmd_ny -add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/blit_cmd_addr_dst -add wave -noupdate -format Literal /tb_vga_frontend64/inst_vga_frontend64/blit_dst_be -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/blitfifo_read_en -add wave -noupdate -format Literal /tb_vga_frontend64/inst_vga_frontend64/blitfifo_re -add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/blitfifo_dout_0 -add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/blitfifo_dout_1 -add wave -noupdate -format Literal /tb_vga_frontend64/inst_vga_frontend64/blitfifo_empty -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/blit_dst_suspend -add wave -noupdate -format Literal /tb_vga_frontend64/inst_vga_frontend64/s -add wave -noupdate -divider RAM -add wave -noupdate -format Literal /tb_vga_frontend64/state -add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/ram_src -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_vga_frontend64/ram_dst -add wave -noupdate -divider Backend -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/vga_scan_rdy -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/inst_vga_backend/ctrl_scan_en -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/inst_vga_backend/sys_rst -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/inst_vga_backend/stat_vga_rdy -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/inst_vga_backend/stat_scan -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/inst_vga_backend/scan_enable -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/inst_vga_backend/is_scan -add wave -noupdate -format Literal /tb_vga_frontend64/inst_vga_frontend64/stat_hpos -add wave -noupdate -format Literal /tb_vga_frontend64/inst_vga_frontend64/stat_vpos -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/inst_vga_backend/rst -add wave -noupdate -format Logic /tb_vga_frontend64/vga_en -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/cg_draw -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/cg_en -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/inst_vga_backend/hready -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/inst_vga_backend/vready -add wave -noupdate -format Logic /tb_vga_frontend64/clk_o -add wave -noupdate -format Logic /tb_vga_frontend64/rst_o -add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/read_reg -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {604745488 ps} 0} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 118 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -update -WaveRestoreZoom {0 ps} {2100 us} diff --git a/lib/VGA_ctrl/src/char_gen.vhd b/lib/VGA_ctrl/src/char_gen.vhd deleted file mode 100644 index f0cb6b8..0000000 --- a/lib/VGA_ctrl/src/char_gen.vhd +++ /dev/null @@ -1,547 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 11:25:45 10/15/05 --- Design Name: --- Module Name: char_gen - Behavioral --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -use work.utils_pkg.all; -use work.vga_types.all; - -entity char_gen is - Generic - ( - tsvga : vga_timespec_t := ts_vga_800_600_72; - - -- User supplied parameters - CHARACTER_SCALE : natural := 1; - CHAR_ROM_SIZE_X : natural := 8; -- Pixels - CHAR_ROM_SIZE_Y : natural := 16; -- Pixels - CHAR_ROM_DEPTH : natural := 256; -- Chars - MAX_CHAR_PER_LINE : natural := 32; -- Chars - MAX_LINE_PER_FRAME : natural := 16; -- Chars - CHAR_SPACING_X : natural := 0; -- Pixels - CHAR_SPACING_Y : natural := 0; -- Pixels - SCREEN_OFFSET_X : natural := 16; -- Pixels - SCREEN_OFFSET_Y : natural := 16 -- Pixels - ); - Port - ( - -- System signals - rst : in std_logic; - vga_clk : in std_logic; - sys_clk : in std_logic; - ce : in std_logic; - frame_pulse : in std_logic; - - - -- Host Signals - clr_screen : in std_logic; - clr_line : in std_logic; - din : in unsigned(7 downto 0); - dout : out unsigned(7 downto 0); - ascii_we : in std_logic; - posy_we : in std_logic; - posx_we : in std_logic; - ready : out std_logic; - - -- Control signals - scan_pos_x_in : in natural range 0 to tsvga.ts_h.ncyc_scan-1; - scan_pos_y_in : in natural range 0 to tsvga.ts_v.ncyc_scan-1; - - -- Status signals - csr_pos_x_out : out natural range 0 to MAX_CHAR_PER_LINE-1; - csr_pos_y_out : out natural range 0 to MAX_LINE_PER_FRAME-1; - - -- Output - char_draw_en : out std_logic - - ); -end char_gen; - -architecture Behavioral of char_gen is - - constant A_RAM_ADDR_WIDTH : integer := 12; - constant A_RAM_DATA_WIDTH : integer := 8; - - type offset_rom_t is array (0 to MAX_LINE_PER_FRAME-1) of unsigned(A_RAM_ADDR_WIDTH-1 downto 0); - - - - function gen_offset_rom(num_char_per_line, num_lines : natural) return offset_rom_t is - variable result : offset_rom_t; - - variable offset : unsigned(A_RAM_ADDR_WIDTH-1 downto 0) := (others => '0'); - begin - for i in 0 to num_lines-1 loop - result(i) := offset; - offset := offset + to_unsigned(num_char_per_line, A_RAM_ADDR_WIDTH-1); - end loop; - return result; - end gen_offset_rom; - - constant offset_rom : offset_rom_t := gen_offset_rom(MAX_CHAR_PER_LINE, MAX_LINE_PER_FRAME); - - -- Calculated parameters - type cg_state_t is (cg_init, cg_ready, cg_clr_line, cg_clr_screen); - signal s, sn : cg_state_t; - - constant CELL_SIZE_X : natural := (CHAR_ROM_SIZE_X+CHAR_SPACING_X)*CHARACTER_SCALE; - constant CELL_SIZE_Y : natural := (CHAR_ROM_SIZE_Y+CHAR_SPACING_Y)*CHARACTER_SCALE; - constant CHAR_SIZE_X : natural := CHAR_ROM_SIZE_X*CHARACTER_SCALE; - constant CHAR_SIZE_Y : natural := CHAR_ROM_SIZE_Y*CHARACTER_SCALE; - - signal line_offset : natural range 0 to MAX_LINE_PER_FRAME-1; - signal cell_x_cnt : natural range 0 to MAX_CHAR_PER_LINE-1; - signal cell_y_cnt : natural range 0 to MAX_LINE_PER_FRAME-1; - signal char_x_cnt : natural range 0 to CELL_SIZE_X-1; - signal char_y_cnt : natural range 0 to CELL_SIZE_Y-1; - signal char_rom_row : unsigned(NextExpBaseTwo(CHAR_SIZE_Y)-1 downto 0); - signal char_rom_addr : unsigned(NextExpBaseTwo(CHAR_ROM_DEPTH*CHAR_ROM_SIZE_Y)-1 downto 0); - signal char_rom_data : unsigned(CHAR_ROM_SIZE_X-1 downto 0); - signal char_reg : unsigned((CHARACTER_SCALE*CHAR_ROM_SIZE_X)-1 downto 0); - - signal a_addr_rd : unsigned(A_RAM_ADDR_WIDTH-1 downto 0); - signal a_addr_wr : unsigned(A_RAM_ADDR_WIDTH-1 downto 0); - signal a_data_rd : unsigned(A_RAM_DATA_WIDTH-1 downto 0); - signal a_data_wr : unsigned(A_RAM_DATA_WIDTH-1 downto 0); - signal a_ram_we : std_logic; - signal a_cnt : natural range 0 to 2**A_RAM_ADDR_WIDTH-1; - signal a_cnt_rst : std_logic; - signal a_cnt_en : std_logic; - signal csr_posx_reg : natural range 0 to MAX_CHAR_PER_LINE-1; - signal csr_posy_reg : natural range 0 to MAX_LINE_PER_FRAME-1; - signal a_data_reg : unsigned(A_RAM_DATA_WIDTH-1 downto 0); - signal a_data_we : std_logic; - signal csr_posx_overflow : std_logic; - signal csr_posx_cnt_din : natural range 0 to MAX_CHAR_PER_LINE-1; - signal csr_posx_cnt_set : std_logic; - signal csr_posx_cnt_en : std_logic; - signal csr_posy_overflow : std_logic; - signal csr_posy_cnt_din : natural range 0 to MAX_LINE_PER_FRAME-1; - signal csr_posy_cnt_set : std_logic; - signal csr_posy_cnt_en : std_logic; - - signal line_addr : unsigned(A_RAM_ADDR_WIDTH-1 downto 0); - signal char_addr : unsigned(A_RAM_ADDR_WIDTH-1 downto 0); - - -- Visible Cursor - constant CURSOR_BLINK_INTERVAL : natural := tsvga.nfps/2; - - type cursor_rom_t is array (0 to 2*CHAR_ROM_SIZE_Y-1) of unsigned (CHAR_ROM_SIZE_X-1 downto 0); - constant cursor_rom : cursor_rom_t := - ( - -- Cursor off - "00000000", - "00000000", - "00000000", - "00000000", - "00000000", - "00000000", - "00000000", - "00000000", - "00000000", - "00000000", - "00000000", - "00000000", - "00000000", - "11111111", - "11111111", - "11111111", - - -- Cursor on - "00000000", - "00000000", - "11111111", - "11111111", - "11111111", - "11111111", - "11111111", - "11111111", - "11111111", - "11111111", - "11111111", - "11111111", - "11111111", - "00000000", - "00000000", - "00000000" - - ); - signal cursor_rom_addr : unsigned(NextExpBaseTwo(2*CHAR_ROM_SIZE_Y)-1 downto 0); - signal cursor_rom_data : unsigned(CHAR_ROM_SIZE_X-1 downto 0); - signal cursor_visible : std_logic; - signal cursor_cnt : natural range 0 to CURSOR_BLINK_INTERVAL-1; - signal csr_posx_synced : natural range 0 to MAX_CHAR_PER_LINE-1; - signal csr_posy_synced : natural range 0 to MAX_LINE_PER_FRAME-1; - - -- Scrolling - signal scroll_offset : natural range 0 to MAX_LINE_PER_FRAME-1; - signal scroll_active : std_logic; - - -begin - - a_addr_rd <= to_unsigned(cell_x_cnt, a_addr_rd'length) + offset_rom(line_offset); - line_addr <= offset_rom(csr_posy_reg); - char_addr <= to_unsigned(csr_posx_reg, char_addr'length); - char_rom_addr <= a_data_rd & char_rom_row(NextExpBaseTwo(CHAR_SIZE_Y)-1 downto (CHARACTER_SCALE-1)); - cursor_rom_addr <= cursor_visible & char_rom_row(NextExpBaseTwo(CHAR_SIZE_Y)-1 downto (CHARACTER_SCALE-1)); - csr_pos_x_out <= csr_posx_reg; - csr_pos_y_out <= csr_posy_reg; - - inst_char_rom : entity work.char_rom - PORT MAP - ( - CLK => vga_clk, - ADDR => char_rom_addr, - DATA => char_rom_data - ); - - inst_ascii_ram: entity work.dpram_1w1r2c_ro - GENERIC MAP ( - addr_width => A_RAM_ADDR_WIDTH, - data_width => A_RAM_DATA_WIDTH - ) - PORT MAP( - clk_a => sys_clk, - clk_b => vga_clk, - en_a => '1', - en_b => '1', - we_a => a_ram_we, - addr_a => a_addr_wr, - addr_b => a_addr_rd, - din_a => a_data_wr, - dout_b => a_data_rd - ); - - --------------------------------------------------------------------------------------------- - --- ASCII RAM control - --------------------------------------------------------------------------------------------- - asci_ram_fsm: - process (s, a_cnt, clr_line, clr_screen, a_data_we, a_data_reg, char_addr, line_addr) - begin - sn <= s; - a_cnt_rst <= '0'; - a_cnt_en <= '0'; - a_ram_we <= '0'; - a_data_wr <= a_data_reg; - a_addr_wr <= char_addr + line_addr; - ready <= '0'; - - case s is - - when cg_init => - sn <= cg_clr_screen; - a_cnt_rst <= '1'; - when cg_ready => - ready <= '1'; - a_ram_we <= a_data_we; - if clr_screen = '1' then - a_cnt_rst <= '1'; - sn <= cg_clr_screen; - elsif clr_line = '1' then - a_cnt_rst <= '1'; - sn <= cg_clr_line; - end if; - when cg_clr_line => - a_ram_we <= '1'; - a_cnt_en <= '1'; - a_data_wr <= to_unsigned(0, A_RAM_DATA_WIDTH); - a_addr_wr <= to_unsigned(a_cnt + to_integer(line_addr), A_RAM_ADDR_WIDTH); - if a_cnt = MAX_CHAR_PER_LINE-1 then - sn <= cg_ready; - end if; - when cg_clr_screen => - a_ram_we <= '1'; - a_cnt_en <= '1'; - a_data_wr <= to_unsigned(0, A_RAM_DATA_WIDTH); - a_addr_wr <= to_unsigned(a_cnt, A_RAM_ADDR_WIDTH); - if a_cnt = (2**A_RAM_ADDR_WIDTH-1) then - sn <= cg_ready; - end if; - - when others => - sn <= cg_ready; - - end case; - end process; - - asci_ram_fsm_next: process (sys_clk) - begin - if rising_edge(sys_clk) then - if rst = '1' then - s <= cg_init; - else - s <= sn; - end if; - end if; - end process; - - --------------------------------------------------------------------------------------------- - asci_ram_cnt: process (sys_clk) - begin - if rising_edge(sys_clk) then - if a_cnt_rst = '1' then - a_cnt <= 0; - elsif a_cnt_en = '1' then - if a_cnt < (2**A_RAM_ADDR_WIDTH-1) then - a_cnt <= a_cnt + 1; - end if; - end if; - end if; - end process; - - --------------------------------------------------------------------------------------------- - asci_addr_reg: process (sys_clk) - begin - if rising_edge(sys_clk) then - a_data_we <= '0'; - csr_posx_cnt_en <= '0'; - csr_posx_cnt_set <= '0'; - csr_posy_cnt_en <= '0'; - csr_posy_cnt_set <= '0'; - if rst = '1' then - a_data_reg <= (others => '0'); - elsif posy_we = '1' then - csr_posy_cnt_din <= to_integer(din); - csr_posy_cnt_set <= '1'; - elsif posx_we = '1' then - csr_posx_cnt_din <= to_integer(din); - csr_posx_cnt_set <= '1'; - elsif ascii_we = '1' then - dout <= din; -- written char is simply echoed back to dout - if din < X"20" then - if din = X"0D" then - csr_posx_cnt_din <= 0; - csr_posx_cnt_set <= '1'; - elsif din = X"0A" then - csr_posy_cnt_en <= '1'; - end if; - else - a_data_reg <= din - X"20"; - a_data_we <= '1'; - csr_posx_cnt_en <= '1'; - end if; - end if; - end if; - end process; - - asci_csr_posx_counter: - process (sys_clk) - begin - if rising_edge(sys_clk) then - csr_posx_overflow <= '0'; - if rst = '1' then - csr_posx_reg <= 0; - elsif csr_posx_cnt_set = '1' then - csr_posx_reg <= csr_posx_cnt_din; - elsif csr_posx_cnt_en = '1' then - if csr_posx_reg < MAX_CHAR_PER_LINE-1 then - csr_posx_reg <= csr_posx_reg + 1; - else - csr_posx_reg <= 0; - csr_posx_overflow <= '1'; - end if; - end if; - end if; - end process; - - asci_csr_posy_counter: - process (sys_clk) - begin - if rising_edge(sys_clk) then - csr_posy_overflow <= '0'; - if rst = '1' then - csr_posy_reg <= 0; - elsif csr_posy_cnt_set = '1' then - csr_posy_reg <= csr_posy_cnt_din; - elsif csr_posy_cnt_en = '1' or csr_posx_overflow = '1' then - if csr_posy_reg < MAX_LINE_PER_FRAME-1 then - csr_posy_reg <= csr_posy_reg + 1; - else - csr_posy_reg <= 0; - csr_posy_overflow <= '1'; - end if; - end if; - end if; - end process; - - scroll_gen: process (sys_clk) - begin - if rising_edge(sys_clk) then - if rst = '1' or clr_screen = '1' then - scroll_offset <= 0; - scroll_active <= '0'; - elsif csr_posy_cnt_set = '1' then - scroll_active <= '0'; - elsif csr_posy_overflow = '1' then - scroll_active <= '1'; - scroll_offset <= 1; - end if; - if (csr_posy_cnt_en = '1' or csr_posx_overflow = '1') and scroll_active = '1' then - scroll_offset <= scroll_offset + 1; - end if; - end if; - end process; - - --------------------------------------------------------------------------------------------- - --- Cursor generator - --------------------------------------------------------------------------------------------- - proc_sync_csr_posx: - process(vga_clk) - variable p1, p2 : natural range 0 to MAX_CHAR_PER_LINE-1; - begin - if rising_edge(vga_clk) then - csr_posx_synced <= p2; - p2 := p1; - p1 := csr_posx_reg; - end if; - end process; - - proc_sync_csr_posy: - process(vga_clk) - variable p1, p2 : natural range 0 to MAX_LINE_PER_FRAME-1; - begin - if rising_edge(vga_clk) then - csr_posy_synced <= p2; - p2 := p1; - p1 := csr_posy_reg; - end if; - end process; - - csr_blink_cnt: process (rst, vga_clk) - begin - if rst = '1' then - cursor_cnt <= 0; - cursor_visible <= '0'; - elsif rising_edge(vga_clk) then - if frame_pulse = '1' then - if cursor_cnt < CURSOR_BLINK_INTERVAL-1 then - cursor_cnt <= cursor_cnt + 1; - else - cursor_cnt <= 0; - cursor_visible <= not cursor_visible; - end if; - end if; - end if; - end process; - - cursor_rom_read: process (vga_clk) - begin - if rising_edge(vga_clk) then - cursor_rom_data <= (others => '0'); - if (cell_x_cnt = csr_posx_synced) and (line_offset = csr_posy_synced) then - cursor_rom_data <= cursor_rom(to_integer(cursor_rom_addr)); - end if; - end if; - end process; - - --------------------------------------------------------------------------------------------- - --- Character generator - --------------------------------------------------------------------------------------------- - char_rom_ctrl: process (vga_clk) - begin - if rising_edge(vga_clk) then - char_rom_row <= to_unsigned(char_y_cnt, char_rom_row'length); - end if; - end process; - - --------------------------------------------------------------------------------------------- - char_reg_ctrl: process (vga_clk) - begin - if rising_edge(vga_clk) and ce = '1' then - if char_x_cnt = 2 then -- +2 delay for ASCII-RAM access and CHAR-ROM access - for i in 0 to CHAR_ROM_SIZE_X-1 loop - for j in 0 to CHARACTER_SCALE-1 loop - char_reg(i*CHARACTER_SCALE + j) <= char_rom_data(i) xor cursor_rom_data(i); - end loop; - end loop; - else - char_reg <= char_reg(char_reg'left-1 downto 0) & '0'; - end if; - end if; - end process; - - --------------------------------------------------------------------------------------------- - cg_ctrl: process (rst, vga_clk) - variable enable_x : std_logic; - variable enable_y : std_logic; - variable char_en : std_logic; - variable char_en2 : std_logic; - begin - - if (rst = '1') then - enable_x := '0'; - enable_y := '0'; - line_offset <= 0; - cell_x_cnt <= 0; - cell_y_cnt <= 0; - char_x_cnt <= 0; - char_y_cnt <= 0; - char_en := '0'; - elsif rising_edge(vga_clk) and ce = '1' then - char_draw_en <= char_en2 and char_reg(char_reg'left); - char_en2 := char_en; - char_en := '0'; - if scan_pos_y_in = SCREEN_OFFSET_Y then - enable_y := '1'; - cell_y_cnt <= 0; - char_x_cnt <= 0; - line_offset <= scroll_offset; - end if; - if scan_pos_x_in = SCREEN_OFFSET_X and enable_y = '1' then - enable_x := '1'; - cell_x_cnt <= 0; - char_x_cnt <= 0; - elsif enable_x = '1' and enable_y = '1' then - if char_x_cnt < CELL_SIZE_X-1 then - char_x_cnt <= char_x_cnt + 1; - else - char_x_cnt <= 0; - if cell_x_cnt < MAX_CHAR_PER_LINE-1 then - cell_x_cnt <= cell_x_cnt + 1; - else - enable_x := '0'; - if char_y_cnt < CELL_SIZE_Y-1 then - char_y_cnt <= char_y_cnt + 1; - else - char_y_cnt <= 0; - if cell_y_cnt < MAX_LINE_PER_FRAME-1 then - cell_y_cnt <= cell_y_cnt + 1; - else - enable_y := '0'; - end if; - if line_offset < MAX_LINE_PER_FRAME-1 then - line_offset <= line_offset + 1; - else - line_offset <= 0; - end if; - end if; - end if; - end if; - if (char_x_cnt < CHAR_SIZE_X) and (char_y_cnt < CHAR_SIZE_Y) then - char_en := '1'; - end if; - end if; - end if; - end process; - - --------------------------------------------------------------------------------------------- -end Behavioral; diff --git a/lib/VGA_ctrl/src/clkgen_virtex4.vhd b/lib/VGA_ctrl/src/clkgen_virtex4.vhd deleted file mode 100644 index 0a08d0c..0000000 --- a/lib/VGA_ctrl/src/clkgen_virtex4.vhd +++ /dev/null @@ -1,106 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 11:25:45 10/15/05 --- Design Name: --- Module Name: vga_ctrl_core - Behavioral --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -library work; -use work.utils_pkg.all; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. -Library UNISIM; -use UNISIM.vcomponents.all; - -entity clkgen is - Generic - ( - clk_in_freq : real := 100.0; - clk_out_freq : real := 100.0 - ); - Port - ( - rst : in std_logic; - clk_in : in std_logic; - clk_out : out std_logic; - locked : out std_logic - ); -end clkgen; - -architecture tech of clkgen is - - signal dcm_clk0 : std_logic; - signal dcm_clk_fb : std_logic; - signal clk_out0 : std_logic; - - begin - - -- Compnent instantiation - DCM_VGA_CLK_inst : DCM_BASE - generic map ( - CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 - -- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 - CLKFX_DIVIDE => UTILS_FREQ_D(clk_in_freq, clk_out_freq), -- Can be any interger from 1 to 32 - CLKFX_MULTIPLY => UTILS_FREQ_M(clk_in_freq, clk_out_freq), -- Can be any integer from 2 to 32 - CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature - CLKIN_PERIOD => UTILS_PERIOD_NS(clk_in_freq), -- Specify period of input clock in ns from 1.25 to 1000.00 - CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift mode of NONE or FIXED - CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X - DCM_PERFORMANCE_MODE => "MAX_SPEED", -- Can be MAX_SPEED or MAX_RANGE - DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or - -- an integer from 0 to 15 - DFS_FREQUENCY_MODE => "LOW", -- LOW or HIGH frequency mode for frequency synthesis - DLL_FREQUENCY_MODE => "LOW", -- LOW, HIGH, or HIGH_SER frequency mode for DLL - DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE - FACTORY_JF => X"F0F0", -- FACTORY JF Values Suggested to be set to X"F0F0" - PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 1023 - STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE - port map - ( - CLK0 => dcm_clk0, -- 0 degree DCM CLK ouptput - CLK180 => open, -- 180 degree DCM CLK output - CLK270 => open, -- 270 degree DCM CLK output - CLK2X => open, -- 2X DCM CLK output - CLK2X180 => open, -- 2X, 180 degree DCM CLK out - CLK90 => open, -- 90 degree DCM CLK output - CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE) - CLKFX => clk_out0, -- DCM CLK synthesis out (M/D) - CLKFX180 => open, -- 180 degree CLK synthesis out - LOCKED => locked, -- DCM LOCK status output - CLKFB => dcm_clk_fb, -- DCM clock feedback - CLKIN => clk_in, -- Clock input (from IBUFG, BUFG or DCM) - RST => rst -- DCM asynchronous reset input - ); - - BUFG_dcm_clk_fb : BUFG - port map - ( - O => dcm_clk_fb, -- Clock buffer output - I => dcm_clk0 -- Clock buffer input - ); - - BUFG_clk_out : BUFG - port map - ( - O => clk_out, -- Clock buffer output - I => clk_out0 -- Clock buffer input - ); - -end tech; diff --git a/lib/VGA_ctrl/src/fonts/Fixedsys_8x15.bff b/lib/VGA_ctrl/src/fonts/Fixedsys_8x15.bff deleted file mode 100644 index a1d2353cf29b6d12c0b71d0401cf7a42f8db4341..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 33044 zcmeHJS(f8S4$J=Qzqvvmb#69y>I2jp0whRAD74tQIIB{6DRBcp24%bIfB(My_4fAP zx3{;y?fwt!KY#!5%a(9o#~b+d>$v`>SN;6I{`fWMoNsUR>=715QG3~}B6cUk203v> z4C)x#!ui3=VkMAA#8Mb0cKU?`tLcj;PRfnv2j1@Z6Bt%Xv+bB;pG-W$@pF0D(i9eN0nx6NG_Zfo%>G{qLB8i+=?t4WUMJ&)*=#avW~BlWS!{Vh)EpI&u3A1DJEqu?kb(LS*uWhhV-cSKffp+Ler0Xju38+@@7_ zRKf$8aSo?`vRUu})L=?yml{(It5b3Xf>lzs*StP%&F3n##SWlBluk$?j%+zW%7U{v zkL1)>P@g75b8f|ZHrd%>M5-=3RxMfp<76TWTyCM=c_OKE$4jj+pH06ZY@YzZt-FE(--_>W#>ilS?9_e!e zPrI8>LRUI-F9&Lx)ft7z8WYOmE$e=ypE^QkzLmi1R1GJC?~i6H1BfoC*;D*(0b0e% z%L3EogTu7fSY;D_3@sU$UCRPw!&%^6WU3E@qK_UTzkHHm9=s)Wb?d#Amz4ld)EMGW zCXay@2>9ogHL%qWj^c3wX%2QcKZzWPaz$sCUhui&>67s3gZK2y6&?ICW4o!B{Aez9c0O%GDFcSHY zbae3WyFS~*A24E53%6xHK>rgYK6JpX*f#SCXZSXf@ioYK#uyQIKY@2zcy7%kB*`d{lrEj^f)z`v%z;B|8}k?TeTZZxAhhVWrzfoXZY||(2JOjX@icd| zUCipdj&rOSdHzUb_2T*Kyqv75z-_l)J`u_rhjBbJ><)A{=Z}3z$3=R-*jE%f&QoG| z=Rjv$t6n@mrn5@|Aqz9zetvJ4HAm^`Le!(AJeLn?CMWGs9eXA)v^uACq^vz?l}C&W zl4rN31g@)0Jc%VN9SAU3JD$~o5uML8%OURf+)y>;E&h=6TT@6=Ry}5mvifeVsuJ>; zx;#_rtB)rH_bgmrv(W(SO(sgIFFxs zYSxLnlb%o!c5wIC=)>$pS2){4jfaX-o=7|C2^C=ncYlpO%5K<^7|oHwBQ<<{S0A69 z^saOl>HaQZT{vj_4%Kz9J9}^7kJ$jeIQWLV+S)?ni^_3cKF?S0Bae@ha~YW6_3!1Y z_P~?+x9W$V-@gW5wfFDRXZ}I`E^~d=9QXOh4Sdz!ze}I-^gri!U;BU6`RBfOd~e|1 zz^8A(zxMuLolkG}dpEFEed7aQxOWYRPr~8(PRfVenk`h$nweT5`&`I+WvnZYW3Uot zZ!E%^u=t606*O~Hn5?6)$)TF~UKLa}VWl^FPRDa~OF*??7pW$hg%J-pB|MpMg|b=~w=46rgF%3;e8R<=twYITmn4)1J?9Ch zqGDMr0{-^$tZ>38=DA3U%6Li>#i?9d+-(m+{IMyft}25J0>5?saR9FhBMHXTu}9E# ze5MN+>Byo9T_-^&5=HLs)Lw!;`3 zlqG^7p5qa<%;sFZKH^vzn=)#sohlJrd zuorNmvD|o@J&lSL&0YzPb8K-@4}uvcI0FNZb>89=fi#>5s#>W5Cx9m#3vLT{aVnhI zuD8(L&;xIVf21hz!I&yutSzQSWLK5zG|G-;!aE)?L7U757qz{-sHjVCAuE_{>rQ3l zgBI~D!Uhc{rHw6Oc^lA&Cwi~$=dq4DIw4PpO&~SsRP{*7Y7&!o0{@_LpSAlr(1U%T zG3t!bzFgog?`vP_fyyx46!dT1bxF-%V(wKwemY`L%Fi8k_(-#KR+paXldyxg+BlDR zvO7Gaqf`iSXq9%0XWZy0KkYz0=0{)G)fBU)^eoSQ!pS!LFpqd;&-$odjE6kyZtM61 zFCFWu#e3ohg9HQ$S2oaioy5eM<;W%LLLZl}c`z7h8rLWB zAw7qT;_{Rktwl`e0ek6YlZ)6%Gv-svYyCpQz#CpaFN=?zKl*!vOJ^U?!-1~za{kRZ zE@~w2=-dPWz|-y9>S><;#XgSTt%2BrlyM)I_|fVrw&U2D&3QV_v9>4YPc1)(e;J^C zc1srmXIRutFwCqi{sZ>(t!ldc_b$XZ`vd3C^IYSs`^~$!6mRx;bV~Kzv;F*d={>&Y zU*o7h*5)6FOJ`lpv*Ew<{HgcQ`PuaP8S4BXUgs^|fp0MPSfOLb*v`cB?b#~lP>1-` z;VE#AWBtNQ)`=E*B6J=%@1#H8@Vha7_5$K#_uXE~JW{-ub^5-n0T za0~~&0FAY*k2w4&WtRc(LDob|yT?m_j?@x#dp{&h$hz2_fAI32=`45>F!2lTS+A_> z$hCeudO3_{aawzx_bG%oj8;m!#nWyaMT>Bp@1-@AyX2EoiojL`Pd6O=5rAjlWCNG= zR0FPIDK4u?wZebIlFdo-C7s_;|OOx&(43w->>K1p4y*u zxqf``Aa}tMWI2l906;Jpp^z*q7iU#U&k{EPWKd35{qNtmzuw;d z`}X$scf0=s`_JD${Ax?Muj38;`gL6Y)2llFuRnebKIhvTz4izTq0M{0uT>vbQsU>1T1}sq$AHYTL7R_ zEyH}M-0@L}{uM@KsI`3e5;SC^-uqYB!WX_hgOU1nXj$*gF{aMv^Xt7Jse_9^0kMttDM`pHpMNB zjLcLv%b*q~T*uxcm|5U*Gf@#pMuE1+%C@H$AZxO1kg=w8S&PWH$qL_3l6@vz4(Blm z1n5{l%a}^g`eX`;#Td#B_Y1nZ=2t*Jh4O>=d0iv^%Tluk$?j%;^=lm)Rk zkLBFgP)!q}Ik)3Io9yf`B3-u~t1Vg%a9`E; zGtP2r-W#|#@G%?s;lB&huQz|q`E#zlFvg+-XSi{;y&nI-8Az&fQ1rHG+rzf=8*%El zi9-j#dLyW@{1_w+#M@P3;Np^NB4J~XRw72g@jRkAXT*ljRu-wY^7s6zK4VtrM>F?G zpA#r8H=l&Abmm?HdYaW4jmR1k&f+cmex{#0LTA36!0U7kCxfp?u{{HbFVWi5{AvMO z#m?ITQ{{uhv}&xf3BQId8JJzm0%XHk;3YEE2STTh9wJ?uWS9qU$z5gD+j(0H@I-}S z4rTHfXn}wqS=PXIKRAxZ39LET;rt|WB+7LIdUN8Weeu>)Rsx|q<7+7t^S-$4%qaAteQSDrJTYho!{geHOxB%aey&5{%rJGdUPC(=nEUM(DT$_&IZ4E_`kz?vQ@hwHw6A)$9A|5 z>)sZ1B6FE;;$U0g&vgC>b1g1A(PIrA`MJ!+HUzq=v!4<$zT;X3icv^j#&Eh`_0gcl z@`ZQz$@1loI2}hLtozg+Y{+p(Z0{q4InKA(t6$7KXyti18H5)7_VkQ(->s!wo56ch zY@X+iwu@QCt2klJ$n!@ct0&Lj&&$b*3fyx0qw;bi+x3* z;*>H&odcb1TlM7mFhesf?>JWMcI^9vv+E?OyMo)=``U>T?{ zaf+`zJ?q5XNl&N^KmkOE*6(;K_Y;ve3zE%yjO<32PJ<;)8-4<{y*qziTnS~J# zI46`$xI^14(81};{<0WZ)M}l6d(1X@vlH^EQDWulGs)f-nzt+Svx7l^?fHb8HCsW+ zVwWUz4SM1k=b~dKMtU( zF_vIVo%RU2kI!@mMmn-+LRTc{M55EH0MFl00c^5CG%qZ10WQ6Zes43prPUk*V4TbF z7zC|6?reuKHmH^ef_cItDw)l>YJJ49GB#yYP&-v3xX1-yO0f$T)Eu6`JjWB>r!fx} zSC1i}T+K%&w!vP&nZ|PAZT2)O_GtFH;5f$?7xf@C!vtqwpxEc_d?JvB6G5-`)POTU z$-;tL!d;vTk8IUj=x*qNZ-yUI9B446Ixp51QzL3uFZa_pJC+Hrc)$!TG8!_m$c|vRgsX?b#kCa-?V)h=u zKd4-1t$q&lWFKgZI%Bji7r4{=+E;p_G7L8b^{?){N0>wFv}qD(5js+=+JSn^&q2i5=tn)P z?C0@qOYdQx>vL?Gr!uYkwLi2|>MsQOSZ6K17yM$7fWYC(1{$xE_}TV!TY&|zjb2#t za$&$NzNbeya>+W;NAi6h3`UyA)g&5HIbF+253LJtqXxiSk#+fm|5HWC+x$w>go31yAk8;Pne_APl0nB>vz0mMQo80q4T_XC;j<`-;MFJ7Z6{& z@AgvedF~B7vw`w8&L2|n72sdWxLTq_&IXR*z&D_vH}0;z90&C9DC7HI3gr@l_8w=oKWQIrbdS zT50t@&+;$g8x73)6#MahrR!Xo#kzQDSNIn>(M{d0akLN5xo55MthL^=ycyq?hZREZ zlm&>ufRm>MP-cz+Q_rsz0LhJ1TVXm^5GweOEQ86E+u zK&M^6($irM*zxCkScDdel_6C7u3w0$EN)Q~gXkls?^nIlL2A((qLmOaK z%mPv(x^Tp9nS@rvuQ=^kMKxEyYVU~qR78%UmP?T(A}5=Th!t9DEV%5#vPUhz7*=jO z3%I2SH6sHXnL^~a2)IHc%j3-PAQUMr%KJe~XDz!^5JF00wcDW=iDn5H?5NOkM-@f! z0@#d8L?g6q3?gWXT>TuCW}H&)-2?S7Q|uR7@>{q;d66_f37)4k4zS5(mk|Zj5|LdI zy153`1%~#RRnP(%^8@DqWhb6e6PO6Lm5)-0&_6j<4Ewna%-{QhgN&4`nnD6<;|7rH zW&%pZ5n!gRN4cYTlm1S4Z@G!@XY1G4683Yrlg@IT_rdr{+W6opU-qvPc%8uO1a6+d z_;px2e#OUkeSX;^8Ikbq90h_^s^akP7DikFas%)|PI>>`8(sLyc1|Nsazc;>kfA8l zVO4HQmWWVo7Sl=%Hk%I6QP6hHd1A5O_&8_Jqe13ZPRgQzNCx5!5nuQz6iJ2mVDw!% z=sN4sFxKkJA8|Zp+^U0WYIRPNUjKk2B7v2OO0H!rK|16eIc`Q~$l|t|FoLvLWtbr) z4CJ5R(Uyn#IRn)Y(N@Jj?Axf`pe`5Lm5bf;U+g2Mvq}c2a|-9#I5A5(JIW$!!c?5! zDDJ^eY@@+7!k+0ns8kEiRX*tIAzPA#cfwY{X@$dNDl-_T*!z_Vjil70EYK2OQi^&0 zR4QF^RPlWH=E4#glXJR&mz%gx5#Q$AiQpZqePnc5IosyKk6nYYNQ0EjZ5v)0>9$Cf zF}ou=;o7>%Zs3b2+iQe}Wzsf2cKDe+y3 z*&~L1u#=Po1i+ys*|hK)sS;2sxcG_4UdoIrXou?Tn;h<2Elp6bp1AiJbL~= z{s105xR>sA0*{}-@?*zu^v5l~lCplysO#lKlz9-8VW9`Dj%98g_6=~jTB+}mrKu?} zZDBD-=~xwr+VAKTNjht!cmTL*7z?;bmdZPKY0lW~QhVkUowj4GsYc^AIFat&nw9^# z6(h?w!L$u)#SRPc>G&GXX59daDFPqoc#3O@ggigWf;^}iIsMA9t2|*fwOq5DpYz+=%1es$|+cQ**N9ISpu_snh4F#OX!UaOT zxj8e~H$Y11yOLW?6ctA)i+sfVd_UNnw@S=)GdV)8&i6l8*FxpMQ$4b%P%F4WW^tF6 zbCw9N43Ew#6}3cWaTufc!IF-dB<6Y`c~AJ*`Z#k~Z;%X|L&=iZ$#$_t_*mfB`Z#k~ zX^;$?L&=ih+ggb^k}v6l_GRlYuw6Y+_&8IX6%B5~X63#juM>Ekzz;ovcYim~U|r+4 zF239HH!!}-d13W-b{qW}bBlL`8 zYvg$3Y@37jArJq$Zu3$<&mZQffWuPZCjnRIx6yJ+oslUqx5j6nQehuk=$~Y4wGj<+ z0L|7x{@2woEcoN%PKZn}5?_6O^dBSUm>O1~&0jG;3`=~e`J-Pno)?xM8`$r*?+;u z&^}p=TA4(<`Q?Q=;(P*V{izK+KkPA(UQy1$l@Ag7H~}5Qm^6w;N_xL5^_ieG(B}83 zy2uBrCz>PiaGcdV{QuyDm;3nyW>;wI+$#hX~FimLy9ZI?dKy5-atYptZp{vhDG)l17fQATy7+XdWL9 zK(k39pwwpqRkt?Tb*|aP@U-=g3}B?F`R?5K6@D@_&wt(?&&pU0o@<^vTk~J(6GQv* zP3FIE4i0_asa-kQpUTNE4xZ~%okD90P>-{mOQisO323+MqepNM zk2iPe2&4YvHK3FW!Ml(3QuD2E=d*Z*eK$sM$d(p$BDiufO1n%YUQ6L6lJ8Qw%d0Jw zKLOE@$>*Zk3ht?w3#$zQ21BxBV01oyj_KM_A3KEyK;JfiCbaMYYEl54Sf7-^P5-xSEITTU?W^D(V)|O8zC=; z99P*;B(gFVNfCi-Gon(yjnKUyee#Zq-Xpvc#OMd}2N!1umlUi0JLk7CP+Y@l*kj<5 zQFbws)k4}ju0kI4({}$(D7Ys+lNZFBG zlU$5AO|A}iS3Q#@dy*12o?aHZKEL`mnTY=wX(;Nv$=W%D<#}6R6_pa@I zxK}#x-`U3C_2oD1kpS|TeVd^x936z8ZU~N5@gjJdABh_{mUmTSHSIl64ghi&;4zr% z2?sTe!S@T~ttvUK#M<(iyf?BcqtW_NoBBcNt?c^*b$adiBWAb!7qi-7;5?3jKhQkQ zW6&~j`f0-qa|obx)^D9Z%+$)A;Ia8NBPO|0^v2kEe76n=hMdfO{x zERQ<*06_FwUMKK6f!7KA>=WSE$n zJG0Yz+_Co-)F>BJWd+!w7ieawM+~hkjH^y3y{Vcke9wF8P62 zkDb7Hdby!t$`gES6FAOvQ9KrZB8NVmJ(bXtl->zJx(fEsA9dt!dm2WH8$~xj;v3+y z;aXHL=bE|}!J&&xLl49SV9UVK<^eh*~!x5<%e04@&F35XJ|stzDJbCxRVr94Yj z&%udaqx?W(31wD8IZpsnPth;8%`y5g9iNSJm3QXx$8#8>&C=jmcYMpvIM1Hr+n+yl N-fcymz4uS(@BhLsE@A)x diff --git a/lib/VGA_ctrl/src/fonts/System_16x16.bff b/lib/VGA_ctrl/src/fonts/System_16x16.bff deleted file mode 100644 index 4ca2523ea9769b9bf3e5a1084b2b998d5935b133..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 65812 zcmeHN3v%qZ4ct`O`^J8oRF07QUm|zP0k%Q_BGKKXMaeVc&zP$BEHuz)e5e_DKmYyT zAOHB{5BvM?a&xrQ<@NRH*UROv*8&V({#BfX z{d{@8Tz*|HCGF|y*VA8?{A}pejHl;klia;tyyDa4`StnN<>}S3i|VhZlKkuU@84TD z|9r8_gkIw+4cYaw#s4ZjSPQNHGE`h;3F}%LSR1Gt`1|i_`Q0G93hEq?^7j^GP7*pl zI~ZA7?@6)uSQ9-78)R2O@h}OTGrq(Hg3!Co>m)T>@uaPjbUC|;_zlARbPNP_0L6opYg~7h ze@AQF5uQem?-kV4Dkn6TIFw$oV zBhye1V}4>d*5|66@iAwFeU9x1a>Kqb48Z#KrwMyyEa4&iZkI_7J6#ht#i+xKG~ z?_5}XOj8Eoz8-~(qGIusFfz>E!yFBS{E}R*@gO7b5iWCj)O(;32R(o;vk@BsaUaL% zV1CK>f_pz$F4o8U>li3^q(9`Fje>q$TuKOzoLKEI?D9+T4}$-q-A@s-INPf!qB4-4xA3fn_|-o=`4_zP&Vjs zAc5(OiuqoVQMmv1f^3v#fFAhF6xdF9y*+g5iSrt`_aY6CNG7ilj+Ck5s zYy~GP?crpl75ws(T+$u~oqX;5rC=)^>uAf=W*W{Gt-nMyKLs&n-r%PXTUTzl8?&kViN)y0bbN2PPLP7Co zQwVNmo*HT>dlnSb*-5GiF7&eArfgu1gW(q`yhaiqIla5d$2&AyZHlpyG zzc$uj&-eO|h0Xh17s4h(A0`E;T1X5;(OMhh|ycm!2kzuxdqO(&K zj3`vVblz1VQE-4kXJ}fra4_J1BZ{I&kcUPlebysQ;N2tZhBeJkV zVeh9D+w#*JR^q-W$2vZ3w`2!SZ%JSUfxAK4bl=+E;9E@Oy?8cP^^@gRLLUgrLZ;XYpi?EzRE+(8v)_mRku6k3c|j5or9)%eSbC321wC=IG*~`R31_ zZwHp%%|Zu6O*TVO1hdC+@OJVdXkvbac3(})Yd1CTQSRM*;t=>KW4AfF`NScxi3b+tXF-p z{fao(yjp*RGkcVe-Hqa0W2DatSS=dF_$VJUj>Kntt*3m(a5yD^xyGygRDZ=)Lvi)j zyT(Vja_xR3KI5B4z0fvakJ-a0`>B4rSG(#Vu665u#(z(|YLDuV^pr1{+9yzmRj>Lh zt{RG~zun~vQ=k>7(vhMBi8HyR2w(eA{s^NFZEMJI{fpRazoftF{>Z!byjS}ScTeZ5 z#PDp6^z>-+cb}jAB|O~t`{Sj4@D{ezzlG$!h7=U2 z3$XvV2ESd#?*{t?&P7@MT<*KrQc$4I-<9b3-Gazb0PWBA2@Xc3ngxLnW;&|H_ljz2 zVlM}OAz!>q-XEtM)cGKrL7m@s+W!jkDU;KNL{CQXHaPcIP1SCXfB9-SfGg*N3k>RmgiWwxYuc*IeS`(o`-s!3Sja2`=0sQDHg`6%h0U{+k>0#Em@`JX-is2^T8 zGZ>v7pQRUC8(16oQ5%r&kM0X(#rbhq`&j$H4Xoz@x6%LZxc0O5gBw`S18!q|UOxMI z;L})WZD4I+ZQuuQK)#R#KKx>2UV)D{{@DSQ|7du2!jCqu&a>v<-+=Dx(eVECkN?jr zYySNWJlgZF^XyN*o`2ofcgM5yUh%bowSl#P2iZXU?^ODw{UF2LVvOl(2LE>(Hd zpffvxgvCZ!0&zmXNb_Bm>P>K{;I1x8k)Q^W?0UjL%M*(KOZwrFPDoRwj zv;5#|7E~#rohT5)oa#wNr(G6MMsAlu#4XSa4l^pGS-uz8uh2>zF|O6?1~^hQIaj8q z&^NW#{NME8R@-X>M>a5f9URg4M9!>z{r*xseHq*P=fr$Uo@Q?eEpLXUVgLQ;?f&$a z4aK6?3)%Q5=I_Xp{_NKYE81#wI6^HBRBv{spUN>C2!%s_S{ym0AB4j0p^}gF2U%|J zU@6&m2f2mIX#ShD@iFH^=I4UcfIqMpr|x7K4uwpRq({lFjww1n#zq1fm-8uMVW?+@ zHD8+WeouU0CB2)!IH+L)ntTB3cqPRoQC2A&N9M5JlrYSyPA=x&s|0y_MX#u_U{uT_ zGXhdL&bhT~yw4fPRy(SZ_c}q6dUJgHr~J60TGrees__k0_Ra4D{p{uXYDJ6X9KmNS zqRAP>Guk&~QhV_}gFTU7x9zcOce)hr(IgtfI4_0|M9`?m97 ztwZO3?Y#5+!TdS%*?w=$x7R_QM(OM3INlhw?|QEru=SzuJg!P{M=kRl!N@WD-WWT^ zT1Wf6bw2j+^X9+y`8%8Mr`(PZcmE0JALX-&yWo^B6B+;qn7)$_#!)Vd-UY{ZTK$$C zJufw8tMLn-j~Q;%ckPd}KLq8rKcw8(EAq1!P@dy}t4(c?$F&@cZt$zJFtZs^<6o0eNVOzHZMKoQb`@<|p@^77H@+?!@)Z zGA)he7|rVmzp0K5+a_j&%^pPYhC(gQpT{xRY;T}F;aXpDpB);TzqVTM`tWq^IkB-l z>^-$Q7K3=V|FiKX3>|}hnCUo)Yht}q>sHYMEx2Ly#AzlYtlQyj>UMKwcmi)-kDsou zIe+XtR&wq9dcfO$Y2Q)9UA`VZe^W?CShvNg=9LRfPgw8ArkL5=WZ)ULP#Gv)ZRolsPIe?4lpf|T<~06NzBaD&(Oqxo3NMvhw9k@C;tIPWrJtuRX&M@e)oCEYUBObp_J6P%mg@G;EA}(U8~pSbGOvG4W#w$IJAA1;JC$* ze;#jp-EO9Kou20N$gJ&?sf!z0Xl-C^U~S;1Y(Tz!{rj9|Kl^ogl7C(O>#}`L?N_k8 zUL59c2i^O$dp*)FM?mWF>#KXc8XGgvHg&<$efM8C`;<MNApYjgCM%*|9)UNG&)gEhx2BTU^Zd~5-U}dUofR(BX_Ysw%U>5s3SXlI{w>Z zUaJ(e;@H4R9H}5Mkks%by=(oo*p1_Acew}xQzx{cy0oDfA2G$1F2G$1F z2G$1F2G$1F2G$1F2G$1F2G$1F2G$1F2G$1F2G$1F2G$1F2G$1F2G$1F2G$1F2L2D3 CZx);Y diff --git a/lib/VGA_ctrl/src/fonts/char_rom_c64.vhd b/lib/VGA_ctrl/src/fonts/char_rom_c64.vhd deleted file mode 100644 index 5a544d0..0000000 --- a/lib/VGA_ctrl/src/fonts/char_rom_c64.vhd +++ /dev/null @@ -1,540 +0,0 @@ --- generated with romgen v3.0 by MikeJ -library ieee; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity char_rom is - port ( - CLK : in std_logic; - ADDR : in unsigned(11 downto 0); - DATA : out unsigned(7 downto 0) - ); -end; - -architecture RTL of char_rom is - - - type ROM_ARRAY is array(0 to 4095) of unsigned(7 downto 0); - constant ROM : ROM_ARRAY := ( - x"3C",x"66",x"6E",x"6E",x"60",x"62",x"3C",x"00", -- 0x0000 - x"18",x"3C",x"66",x"7E",x"66",x"66",x"66",x"00", -- 0x0008 - x"7C",x"66",x"66",x"7C",x"66",x"66",x"7C",x"00", -- 0x0010 - x"3C",x"66",x"60",x"60",x"60",x"66",x"3C",x"00", -- 0x0018 - x"78",x"6C",x"66",x"66",x"66",x"6C",x"78",x"00", -- 0x0020 - x"7E",x"60",x"60",x"78",x"60",x"60",x"7E",x"00", -- 0x0028 - x"7E",x"60",x"60",x"78",x"60",x"60",x"60",x"00", -- 0x0030 - x"3C",x"66",x"60",x"6E",x"66",x"66",x"3C",x"00", -- 0x0038 - x"66",x"66",x"66",x"7E",x"66",x"66",x"66",x"00", -- 0x0040 - x"3C",x"18",x"18",x"18",x"18",x"18",x"3C",x"00", -- 0x0048 - x"1E",x"0C",x"0C",x"0C",x"0C",x"6C",x"38",x"00", -- 0x0050 - x"66",x"6C",x"78",x"70",x"78",x"6C",x"66",x"00", -- 0x0058 - x"60",x"60",x"60",x"60",x"60",x"60",x"7E",x"00", -- 0x0060 - x"63",x"77",x"7F",x"6B",x"63",x"63",x"63",x"00", -- 0x0068 - x"66",x"76",x"7E",x"7E",x"6E",x"66",x"66",x"00", -- 0x0070 - x"3C",x"66",x"66",x"66",x"66",x"66",x"3C",x"00", -- 0x0078 - x"7C",x"66",x"66",x"7C",x"60",x"60",x"60",x"00", -- 0x0080 - x"3C",x"66",x"66",x"66",x"66",x"3C",x"0E",x"00", -- 0x0088 - x"7C",x"66",x"66",x"7C",x"78",x"6C",x"66",x"00", -- 0x0090 - x"3C",x"66",x"60",x"3C",x"06",x"66",x"3C",x"00", -- 0x0098 - x"7E",x"18",x"18",x"18",x"18",x"18",x"18",x"00", -- 0x00A0 - x"66",x"66",x"66",x"66",x"66",x"66",x"3C",x"00", -- 0x00A8 - x"66",x"66",x"66",x"66",x"66",x"3C",x"18",x"00", -- 0x00B0 - x"63",x"63",x"63",x"6B",x"7F",x"77",x"63",x"00", -- 0x00B8 - x"66",x"66",x"3C",x"18",x"3C",x"66",x"66",x"00", -- 0x00C0 - x"66",x"66",x"66",x"3C",x"18",x"18",x"18",x"00", -- 0x00C8 - x"7E",x"06",x"0C",x"18",x"30",x"60",x"7E",x"00", -- 0x00D0 - x"3C",x"30",x"30",x"30",x"30",x"30",x"3C",x"00", -- 0x00D8 - x"0C",x"12",x"30",x"7C",x"30",x"62",x"FC",x"00", -- 0x00E0 - x"3C",x"0C",x"0C",x"0C",x"0C",x"0C",x"3C",x"00", -- 0x00E8 - x"00",x"18",x"3C",x"7E",x"18",x"18",x"18",x"18", -- 0x00F0 - x"00",x"10",x"30",x"7F",x"7F",x"30",x"10",x"00", -- 0x00F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0100 - x"18",x"18",x"18",x"18",x"00",x"00",x"18",x"00", -- 0x0108 - x"66",x"66",x"66",x"00",x"00",x"00",x"00",x"00", -- 0x0110 - x"66",x"66",x"FF",x"66",x"FF",x"66",x"66",x"00", -- 0x0118 - x"18",x"3E",x"60",x"3C",x"06",x"7C",x"18",x"00", -- 0x0120 - x"62",x"66",x"0C",x"18",x"30",x"66",x"46",x"00", -- 0x0128 - x"3C",x"66",x"3C",x"38",x"67",x"66",x"3F",x"00", -- 0x0130 - x"06",x"0C",x"18",x"00",x"00",x"00",x"00",x"00", -- 0x0138 - x"0C",x"18",x"30",x"30",x"30",x"18",x"0C",x"00", -- 0x0140 - x"30",x"18",x"0C",x"0C",x"0C",x"18",x"30",x"00", -- 0x0148 - x"00",x"66",x"3C",x"FF",x"3C",x"66",x"00",x"00", -- 0x0150 - x"00",x"18",x"18",x"7E",x"18",x"18",x"00",x"00", -- 0x0158 - x"00",x"00",x"00",x"00",x"00",x"18",x"18",x"30", -- 0x0160 - x"00",x"00",x"00",x"7E",x"00",x"00",x"00",x"00", -- 0x0168 - x"00",x"00",x"00",x"00",x"00",x"18",x"18",x"00", -- 0x0170 - x"00",x"03",x"06",x"0C",x"18",x"30",x"60",x"00", -- 0x0178 - x"3C",x"66",x"6E",x"76",x"66",x"66",x"3C",x"00", -- 0x0180 - x"18",x"18",x"38",x"18",x"18",x"18",x"7E",x"00", -- 0x0188 - x"3C",x"66",x"06",x"0C",x"30",x"60",x"7E",x"00", -- 0x0190 - x"3C",x"66",x"06",x"1C",x"06",x"66",x"3C",x"00", -- 0x0198 - x"06",x"0E",x"1E",x"66",x"7F",x"06",x"06",x"00", -- 0x01A0 - x"7E",x"60",x"7C",x"06",x"06",x"66",x"3C",x"00", -- 0x01A8 - x"3C",x"66",x"60",x"7C",x"66",x"66",x"3C",x"00", -- 0x01B0 - x"7E",x"66",x"0C",x"18",x"18",x"18",x"18",x"00", -- 0x01B8 - x"3C",x"66",x"66",x"3C",x"66",x"66",x"3C",x"00", -- 0x01C0 - x"3C",x"66",x"66",x"3E",x"06",x"66",x"3C",x"00", -- 0x01C8 - x"00",x"00",x"18",x"00",x"00",x"18",x"00",x"00", -- 0x01D0 - x"00",x"00",x"18",x"00",x"00",x"18",x"18",x"30", -- 0x01D8 - x"0E",x"18",x"30",x"60",x"30",x"18",x"0E",x"00", -- 0x01E0 - x"00",x"00",x"7E",x"00",x"7E",x"00",x"00",x"00", -- 0x01E8 - x"70",x"18",x"0C",x"06",x"0C",x"18",x"70",x"00", -- 0x01F0 - x"3C",x"66",x"06",x"0C",x"18",x"00",x"18",x"00", -- 0x01F8 - x"00",x"00",x"00",x"FF",x"FF",x"00",x"00",x"00", -- 0x0200 - x"08",x"1C",x"3E",x"7F",x"7F",x"1C",x"3E",x"00", -- 0x0208 - x"18",x"18",x"18",x"18",x"18",x"18",x"18",x"18", -- 0x0210 - x"00",x"00",x"00",x"FF",x"FF",x"00",x"00",x"00", -- 0x0218 - x"00",x"00",x"FF",x"FF",x"00",x"00",x"00",x"00", -- 0x0220 - x"00",x"FF",x"FF",x"00",x"00",x"00",x"00",x"00", -- 0x0228 - x"00",x"00",x"00",x"00",x"FF",x"FF",x"00",x"00", -- 0x0230 - x"30",x"30",x"30",x"30",x"30",x"30",x"30",x"30", -- 0x0238 - x"0C",x"0C",x"0C",x"0C",x"0C",x"0C",x"0C",x"0C", -- 0x0240 - x"00",x"00",x"00",x"E0",x"F0",x"38",x"18",x"18", -- 0x0248 - x"18",x"18",x"1C",x"0F",x"07",x"00",x"00",x"00", -- 0x0250 - x"18",x"18",x"38",x"F0",x"E0",x"00",x"00",x"00", -- 0x0258 - x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"FF",x"FF", -- 0x0260 - x"C0",x"E0",x"70",x"38",x"1C",x"0E",x"07",x"03", -- 0x0268 - x"03",x"07",x"0E",x"1C",x"38",x"70",x"E0",x"C0", -- 0x0270 - x"FF",x"FF",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0", -- 0x0278 - x"FF",x"FF",x"03",x"03",x"03",x"03",x"03",x"03", -- 0x0280 - x"00",x"3C",x"7E",x"7E",x"7E",x"7E",x"3C",x"00", -- 0x0288 - x"00",x"00",x"00",x"00",x"00",x"FF",x"FF",x"00", -- 0x0290 - x"36",x"7F",x"7F",x"7F",x"3E",x"1C",x"08",x"00", -- 0x0298 - x"60",x"60",x"60",x"60",x"60",x"60",x"60",x"60", -- 0x02A0 - x"00",x"00",x"00",x"07",x"0F",x"1C",x"18",x"18", -- 0x02A8 - x"C3",x"E7",x"7E",x"3C",x"3C",x"7E",x"E7",x"C3", -- 0x02B0 - x"00",x"3C",x"7E",x"66",x"66",x"7E",x"3C",x"00", -- 0x02B8 - x"18",x"18",x"66",x"66",x"18",x"18",x"3C",x"00", -- 0x02C0 - x"06",x"06",x"06",x"06",x"06",x"06",x"06",x"06", -- 0x02C8 - x"08",x"1C",x"3E",x"7F",x"3E",x"1C",x"08",x"00", -- 0x02D0 - x"18",x"18",x"18",x"FF",x"FF",x"18",x"18",x"18", -- 0x02D8 - x"C0",x"C0",x"30",x"30",x"C0",x"C0",x"30",x"30", -- 0x02E0 - x"18",x"18",x"18",x"18",x"18",x"18",x"18",x"18", -- 0x02E8 - x"00",x"00",x"03",x"3E",x"76",x"36",x"36",x"00", -- 0x02F0 - x"FF",x"7F",x"3F",x"1F",x"0F",x"07",x"03",x"01", -- 0x02F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0300 - x"F0",x"F0",x"F0",x"F0",x"F0",x"F0",x"F0",x"F0", -- 0x0308 - x"00",x"00",x"00",x"00",x"FF",x"FF",x"FF",x"FF", -- 0x0310 - x"FF",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0318 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"FF", -- 0x0320 - x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0", -- 0x0328 - x"CC",x"CC",x"33",x"33",x"CC",x"CC",x"33",x"33", -- 0x0330 - x"03",x"03",x"03",x"03",x"03",x"03",x"03",x"03", -- 0x0338 - x"00",x"00",x"00",x"00",x"CC",x"CC",x"33",x"33", -- 0x0340 - x"FF",x"FE",x"FC",x"F8",x"F0",x"E0",x"C0",x"80", -- 0x0348 - x"03",x"03",x"03",x"03",x"03",x"03",x"03",x"03", -- 0x0350 - x"18",x"18",x"18",x"1F",x"1F",x"18",x"18",x"18", -- 0x0358 - x"00",x"00",x"00",x"00",x"0F",x"0F",x"0F",x"0F", -- 0x0360 - x"18",x"18",x"18",x"1F",x"1F",x"00",x"00",x"00", -- 0x0368 - x"00",x"00",x"00",x"F8",x"F8",x"18",x"18",x"18", -- 0x0370 - x"00",x"00",x"00",x"00",x"00",x"00",x"FF",x"FF", -- 0x0378 - x"00",x"00",x"00",x"1F",x"1F",x"18",x"18",x"18", -- 0x0380 - x"18",x"18",x"18",x"FF",x"FF",x"00",x"00",x"00", -- 0x0388 - x"00",x"00",x"00",x"FF",x"FF",x"18",x"18",x"18", -- 0x0390 - x"18",x"18",x"18",x"F8",x"F8",x"18",x"18",x"18", -- 0x0398 - x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0", -- 0x03A0 - x"E0",x"E0",x"E0",x"E0",x"E0",x"E0",x"E0",x"E0", -- 0x03A8 - x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"07", -- 0x03B0 - x"FF",x"FF",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03B8 - x"FF",x"FF",x"FF",x"00",x"00",x"00",x"00",x"00", -- 0x03C0 - x"00",x"00",x"00",x"00",x"00",x"FF",x"FF",x"FF", -- 0x03C8 - x"03",x"03",x"03",x"03",x"03",x"03",x"FF",x"FF", -- 0x03D0 - x"00",x"00",x"00",x"00",x"F0",x"F0",x"F0",x"F0", -- 0x03D8 - x"0F",x"0F",x"0F",x"0F",x"00",x"00",x"00",x"00", -- 0x03E0 - x"18",x"18",x"18",x"F8",x"F8",x"00",x"00",x"00", -- 0x03E8 - x"F0",x"F0",x"F0",x"F0",x"00",x"00",x"00",x"00", -- 0x03F0 - x"F0",x"F0",x"F0",x"F0",x"0F",x"0F",x"0F",x"0F", -- 0x03F8 - x"C3",x"99",x"91",x"91",x"9F",x"99",x"C3",x"FF", -- 0x0400 - x"E7",x"C3",x"99",x"81",x"99",x"99",x"99",x"FF", -- 0x0408 - x"83",x"99",x"99",x"83",x"99",x"99",x"83",x"FF", -- 0x0410 - x"C3",x"99",x"9F",x"9F",x"9F",x"99",x"C3",x"FF", -- 0x0418 - x"87",x"93",x"99",x"99",x"99",x"93",x"87",x"FF", -- 0x0420 - x"81",x"9F",x"9F",x"87",x"9F",x"9F",x"81",x"FF", -- 0x0428 - x"81",x"9F",x"9F",x"87",x"9F",x"9F",x"9F",x"FF", -- 0x0430 - x"C3",x"99",x"9F",x"91",x"99",x"99",x"C3",x"FF", -- 0x0438 - x"99",x"99",x"99",x"81",x"99",x"99",x"99",x"FF", -- 0x0440 - x"C3",x"E7",x"E7",x"E7",x"E7",x"E7",x"C3",x"FF", -- 0x0448 - x"E1",x"F3",x"F3",x"F3",x"F3",x"93",x"C7",x"FF", -- 0x0450 - x"99",x"93",x"87",x"8F",x"87",x"93",x"99",x"FF", -- 0x0458 - x"9F",x"9F",x"9F",x"9F",x"9F",x"9F",x"81",x"FF", -- 0x0460 - x"9C",x"88",x"80",x"94",x"9C",x"9C",x"9C",x"FF", -- 0x0468 - x"99",x"89",x"81",x"81",x"91",x"99",x"99",x"FF", -- 0x0470 - x"C3",x"99",x"99",x"99",x"99",x"99",x"C3",x"FF", -- 0x0478 - x"83",x"99",x"99",x"83",x"9F",x"9F",x"9F",x"FF", -- 0x0480 - x"C3",x"99",x"99",x"99",x"99",x"C3",x"F1",x"FF", -- 0x0488 - x"83",x"99",x"99",x"83",x"87",x"93",x"99",x"FF", -- 0x0490 - x"C3",x"99",x"9F",x"C3",x"F9",x"99",x"C3",x"FF", -- 0x0498 - x"81",x"E7",x"E7",x"E7",x"E7",x"E7",x"E7",x"FF", -- 0x04A0 - x"99",x"99",x"99",x"99",x"99",x"99",x"C3",x"FF", -- 0x04A8 - x"99",x"99",x"99",x"99",x"99",x"C3",x"E7",x"FF", -- 0x04B0 - x"9C",x"9C",x"9C",x"94",x"80",x"88",x"9C",x"FF", -- 0x04B8 - x"99",x"99",x"C3",x"E7",x"C3",x"99",x"99",x"FF", -- 0x04C0 - x"99",x"99",x"99",x"C3",x"E7",x"E7",x"E7",x"FF", -- 0x04C8 - x"81",x"F9",x"F3",x"E7",x"CF",x"9F",x"81",x"FF", -- 0x04D0 - x"C3",x"CF",x"CF",x"CF",x"CF",x"CF",x"C3",x"FF", -- 0x04D8 - x"F3",x"ED",x"CF",x"83",x"CF",x"9D",x"03",x"FF", -- 0x04E0 - x"C3",x"F3",x"F3",x"F3",x"F3",x"F3",x"C3",x"FF", -- 0x04E8 - x"FF",x"E7",x"C3",x"81",x"E7",x"E7",x"E7",x"E7", -- 0x04F0 - x"FF",x"EF",x"CF",x"80",x"80",x"CF",x"EF",x"FF", -- 0x04F8 - x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0500 - x"E7",x"E7",x"E7",x"E7",x"FF",x"FF",x"E7",x"FF", -- 0x0508 - x"99",x"99",x"99",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0510 - x"99",x"99",x"00",x"99",x"00",x"99",x"99",x"FF", -- 0x0518 - x"E7",x"C1",x"9F",x"C3",x"F9",x"83",x"E7",x"FF", -- 0x0520 - x"9D",x"99",x"F3",x"E7",x"CF",x"99",x"B9",x"FF", -- 0x0528 - x"C3",x"99",x"C3",x"C7",x"98",x"99",x"C0",x"FF", -- 0x0530 - x"F9",x"F3",x"E7",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0538 - x"F3",x"E7",x"CF",x"CF",x"CF",x"E7",x"F3",x"FF", -- 0x0540 - x"CF",x"E7",x"F3",x"F3",x"F3",x"E7",x"CF",x"FF", -- 0x0548 - x"FF",x"99",x"C3",x"00",x"C3",x"99",x"FF",x"FF", -- 0x0550 - x"FF",x"E7",x"E7",x"81",x"E7",x"E7",x"FF",x"FF", -- 0x0558 - x"FF",x"FF",x"FF",x"FF",x"FF",x"E7",x"E7",x"CF", -- 0x0560 - x"FF",x"FF",x"FF",x"81",x"FF",x"FF",x"FF",x"FF", -- 0x0568 - x"FF",x"FF",x"FF",x"FF",x"FF",x"E7",x"E7",x"FF", -- 0x0570 - x"FF",x"FC",x"F9",x"F3",x"E7",x"CF",x"9F",x"FF", -- 0x0578 - x"C3",x"99",x"91",x"89",x"99",x"99",x"C3",x"FF", -- 0x0580 - x"E7",x"E7",x"C7",x"E7",x"E7",x"E7",x"81",x"FF", -- 0x0588 - x"C3",x"99",x"F9",x"F3",x"CF",x"9F",x"81",x"FF", -- 0x0590 - x"C3",x"99",x"F9",x"E3",x"F9",x"99",x"C3",x"FF", -- 0x0598 - x"F9",x"F1",x"E1",x"99",x"80",x"F9",x"F9",x"FF", -- 0x05A0 - x"81",x"9F",x"83",x"F9",x"F9",x"99",x"C3",x"FF", -- 0x05A8 - x"C3",x"99",x"9F",x"83",x"99",x"99",x"C3",x"FF", -- 0x05B0 - x"81",x"99",x"F3",x"E7",x"E7",x"E7",x"E7",x"FF", -- 0x05B8 - x"C3",x"99",x"99",x"C3",x"99",x"99",x"C3",x"FF", -- 0x05C0 - x"C3",x"99",x"99",x"C1",x"F9",x"99",x"C3",x"FF", -- 0x05C8 - x"FF",x"FF",x"E7",x"FF",x"FF",x"E7",x"FF",x"FF", -- 0x05D0 - x"FF",x"FF",x"E7",x"FF",x"FF",x"E7",x"E7",x"CF", -- 0x05D8 - x"F1",x"E7",x"CF",x"9F",x"CF",x"E7",x"F1",x"FF", -- 0x05E0 - x"FF",x"FF",x"81",x"FF",x"81",x"FF",x"FF",x"FF", -- 0x05E8 - x"8F",x"E7",x"F3",x"F9",x"F3",x"E7",x"8F",x"FF", -- 0x05F0 - x"C3",x"99",x"F9",x"F3",x"E7",x"FF",x"E7",x"FF", -- 0x05F8 - x"FF",x"FF",x"FF",x"00",x"00",x"FF",x"FF",x"FF", -- 0x0600 - x"F7",x"E3",x"C1",x"80",x"80",x"E3",x"C1",x"FF", -- 0x0608 - x"E7",x"E7",x"E7",x"E7",x"E7",x"E7",x"E7",x"E7", -- 0x0610 - x"FF",x"FF",x"FF",x"00",x"00",x"FF",x"FF",x"FF", -- 0x0618 - x"FF",x"FF",x"00",x"00",x"FF",x"FF",x"FF",x"FF", -- 0x0620 - x"FF",x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0628 - x"FF",x"FF",x"FF",x"FF",x"00",x"00",x"FF",x"FF", -- 0x0630 - x"CF",x"CF",x"CF",x"CF",x"CF",x"CF",x"CF",x"CF", -- 0x0638 - x"F3",x"F3",x"F3",x"F3",x"F3",x"F3",x"F3",x"F3", -- 0x0640 - x"FF",x"FF",x"FF",x"1F",x"0F",x"C7",x"E7",x"E7", -- 0x0648 - x"E7",x"E7",x"E3",x"F0",x"F8",x"FF",x"FF",x"FF", -- 0x0650 - x"E7",x"E7",x"C7",x"0F",x"1F",x"FF",x"FF",x"FF", -- 0x0658 - x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"00",x"00", -- 0x0660 - x"3F",x"1F",x"8F",x"C7",x"E3",x"F1",x"F8",x"FC", -- 0x0668 - x"FC",x"F8",x"F1",x"E3",x"C7",x"8F",x"1F",x"3F", -- 0x0670 - x"00",x"00",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F", -- 0x0678 - x"00",x"00",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC", -- 0x0680 - x"FF",x"C3",x"81",x"81",x"81",x"81",x"C3",x"FF", -- 0x0688 - x"FF",x"FF",x"FF",x"FF",x"FF",x"00",x"00",x"FF", -- 0x0690 - x"C9",x"80",x"80",x"80",x"C1",x"E3",x"F7",x"FF", -- 0x0698 - x"9F",x"9F",x"9F",x"9F",x"9F",x"9F",x"9F",x"9F", -- 0x06A0 - x"FF",x"FF",x"FF",x"F8",x"F0",x"E3",x"E7",x"E7", -- 0x06A8 - x"3C",x"18",x"81",x"C3",x"C3",x"81",x"18",x"3C", -- 0x06B0 - x"FF",x"C3",x"81",x"99",x"99",x"81",x"C3",x"FF", -- 0x06B8 - x"E7",x"E7",x"99",x"99",x"E7",x"E7",x"C3",x"FF", -- 0x06C0 - x"F9",x"F9",x"F9",x"F9",x"F9",x"F9",x"F9",x"F9", -- 0x06C8 - x"F7",x"E3",x"C1",x"80",x"C1",x"E3",x"F7",x"FF", -- 0x06D0 - x"E7",x"E7",x"E7",x"00",x"00",x"E7",x"E7",x"E7", -- 0x06D8 - x"3F",x"3F",x"CF",x"CF",x"3F",x"3F",x"CF",x"CF", -- 0x06E0 - x"E7",x"E7",x"E7",x"E7",x"E7",x"E7",x"E7",x"E7", -- 0x06E8 - x"FF",x"FF",x"FC",x"C1",x"89",x"C9",x"C9",x"FF", -- 0x06F0 - x"00",x"80",x"C0",x"E0",x"F0",x"F8",x"FC",x"FE", -- 0x06F8 - x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0700 - x"0F",x"0F",x"0F",x"0F",x"0F",x"0F",x"0F",x"0F", -- 0x0708 - x"FF",x"FF",x"FF",x"FF",x"00",x"00",x"00",x"00", -- 0x0710 - x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0718 - x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"00", -- 0x0720 - x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F", -- 0x0728 - x"33",x"33",x"CC",x"CC",x"33",x"33",x"CC",x"CC", -- 0x0730 - x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC", -- 0x0738 - x"FF",x"FF",x"FF",x"FF",x"33",x"33",x"CC",x"CC", -- 0x0740 - x"00",x"01",x"03",x"07",x"0F",x"1F",x"3F",x"7F", -- 0x0748 - x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC", -- 0x0750 - x"E7",x"E7",x"E7",x"E0",x"E0",x"E7",x"E7",x"E7", -- 0x0758 - x"FF",x"FF",x"FF",x"FF",x"F0",x"F0",x"F0",x"F0", -- 0x0760 - x"E7",x"E7",x"E7",x"E0",x"E0",x"FF",x"FF",x"FF", -- 0x0768 - x"FF",x"FF",x"FF",x"07",x"07",x"E7",x"E7",x"E7", -- 0x0770 - x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"00",x"00", -- 0x0778 - x"FF",x"FF",x"FF",x"E0",x"E0",x"E7",x"E7",x"E7", -- 0x0780 - x"E7",x"E7",x"E7",x"00",x"00",x"FF",x"FF",x"FF", -- 0x0788 - x"FF",x"FF",x"FF",x"00",x"00",x"E7",x"E7",x"E7", -- 0x0790 - x"E7",x"E7",x"E7",x"07",x"07",x"E7",x"E7",x"E7", -- 0x0798 - x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F", -- 0x07A0 - x"1F",x"1F",x"1F",x"1F",x"1F",x"1F",x"1F",x"1F", -- 0x07A8 - x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8", -- 0x07B0 - x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x07B8 - x"00",x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x07C0 - x"FF",x"FF",x"FF",x"FF",x"FF",x"00",x"00",x"00", -- 0x07C8 - x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"00",x"00", -- 0x07D0 - x"FF",x"FF",x"FF",x"FF",x"0F",x"0F",x"0F",x"0F", -- 0x07D8 - x"F0",x"F0",x"F0",x"F0",x"FF",x"FF",x"FF",x"FF", -- 0x07E0 - x"E7",x"E7",x"E7",x"07",x"07",x"FF",x"FF",x"FF", -- 0x07E8 - x"0F",x"0F",x"0F",x"0F",x"FF",x"FF",x"FF",x"FF", -- 0x07F0 - x"0F",x"0F",x"0F",x"0F",x"F0",x"F0",x"F0",x"F0", -- 0x07F8 - x"3C",x"66",x"6E",x"6E",x"60",x"62",x"3C",x"00", -- 0x0800 - x"00",x"00",x"3C",x"06",x"3E",x"66",x"3E",x"00", -- 0x0808 - x"00",x"60",x"60",x"7C",x"66",x"66",x"7C",x"00", -- 0x0810 - x"00",x"00",x"3C",x"60",x"60",x"60",x"3C",x"00", -- 0x0818 - x"00",x"06",x"06",x"3E",x"66",x"66",x"3E",x"00", -- 0x0820 - x"00",x"00",x"3C",x"66",x"7E",x"60",x"3C",x"00", -- 0x0828 - x"00",x"0E",x"18",x"3E",x"18",x"18",x"18",x"00", -- 0x0830 - x"00",x"00",x"3E",x"66",x"66",x"3E",x"06",x"7C", -- 0x0838 - x"00",x"60",x"60",x"7C",x"66",x"66",x"66",x"00", -- 0x0840 - x"00",x"18",x"00",x"38",x"18",x"18",x"3C",x"00", -- 0x0848 - x"00",x"06",x"00",x"06",x"06",x"06",x"06",x"3C", -- 0x0850 - x"00",x"60",x"60",x"6C",x"78",x"6C",x"66",x"00", -- 0x0858 - x"00",x"38",x"18",x"18",x"18",x"18",x"3C",x"00", -- 0x0860 - x"00",x"00",x"66",x"7F",x"7F",x"6B",x"63",x"00", -- 0x0868 - x"00",x"00",x"7C",x"66",x"66",x"66",x"66",x"00", -- 0x0870 - x"00",x"00",x"3C",x"66",x"66",x"66",x"3C",x"00", -- 0x0878 - x"00",x"00",x"7C",x"66",x"66",x"7C",x"60",x"60", -- 0x0880 - x"00",x"00",x"3E",x"66",x"66",x"3E",x"06",x"06", -- 0x0888 - x"00",x"00",x"7C",x"66",x"60",x"60",x"60",x"00", -- 0x0890 - x"00",x"00",x"3E",x"60",x"3C",x"06",x"7C",x"00", -- 0x0898 - x"00",x"18",x"7E",x"18",x"18",x"18",x"0E",x"00", -- 0x08A0 - x"00",x"00",x"66",x"66",x"66",x"66",x"3E",x"00", -- 0x08A8 - x"00",x"00",x"66",x"66",x"66",x"3C",x"18",x"00", -- 0x08B0 - x"00",x"00",x"63",x"6B",x"7F",x"3E",x"36",x"00", -- 0x08B8 - x"00",x"00",x"66",x"3C",x"18",x"3C",x"66",x"00", -- 0x08C0 - x"00",x"00",x"66",x"66",x"66",x"3E",x"0C",x"78", -- 0x08C8 - x"00",x"00",x"7E",x"0C",x"18",x"30",x"7E",x"00", -- 0x08D0 - x"3C",x"30",x"30",x"30",x"30",x"30",x"3C",x"00", -- 0x08D8 - x"0C",x"12",x"30",x"7C",x"30",x"62",x"FC",x"00", -- 0x08E0 - x"3C",x"0C",x"0C",x"0C",x"0C",x"0C",x"3C",x"00", -- 0x08E8 - x"00",x"18",x"3C",x"7E",x"18",x"18",x"18",x"18", -- 0x08F0 - x"00",x"10",x"30",x"7F",x"7F",x"30",x"10",x"00", -- 0x08F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0900 - x"18",x"18",x"18",x"18",x"00",x"00",x"18",x"00", -- 0x0908 - x"66",x"66",x"66",x"00",x"00",x"00",x"00",x"00", -- 0x0910 - x"66",x"66",x"FF",x"66",x"FF",x"66",x"66",x"00", -- 0x0918 - x"18",x"3E",x"60",x"3C",x"06",x"7C",x"18",x"00", -- 0x0920 - x"62",x"66",x"0C",x"18",x"30",x"66",x"46",x"00", -- 0x0928 - x"3C",x"66",x"3C",x"38",x"67",x"66",x"3F",x"00", -- 0x0930 - x"06",x"0C",x"18",x"00",x"00",x"00",x"00",x"00", -- 0x0938 - x"0C",x"18",x"30",x"30",x"30",x"18",x"0C",x"00", -- 0x0940 - x"30",x"18",x"0C",x"0C",x"0C",x"18",x"30",x"00", -- 0x0948 - x"00",x"66",x"3C",x"FF",x"3C",x"66",x"00",x"00", -- 0x0950 - x"00",x"18",x"18",x"7E",x"18",x"18",x"00",x"00", -- 0x0958 - x"00",x"00",x"00",x"00",x"00",x"18",x"18",x"30", -- 0x0960 - x"00",x"00",x"00",x"7E",x"00",x"00",x"00",x"00", -- 0x0968 - x"00",x"00",x"00",x"00",x"00",x"18",x"18",x"00", -- 0x0970 - x"00",x"03",x"06",x"0C",x"18",x"30",x"60",x"00", -- 0x0978 - x"3C",x"66",x"6E",x"76",x"66",x"66",x"3C",x"00", -- 0x0980 - x"18",x"18",x"38",x"18",x"18",x"18",x"7E",x"00", -- 0x0988 - x"3C",x"66",x"06",x"0C",x"30",x"60",x"7E",x"00", -- 0x0990 - x"3C",x"66",x"06",x"1C",x"06",x"66",x"3C",x"00", -- 0x0998 - x"06",x"0E",x"1E",x"66",x"7F",x"06",x"06",x"00", -- 0x09A0 - x"7E",x"60",x"7C",x"06",x"06",x"66",x"3C",x"00", -- 0x09A8 - x"3C",x"66",x"60",x"7C",x"66",x"66",x"3C",x"00", -- 0x09B0 - x"7E",x"66",x"0C",x"18",x"18",x"18",x"18",x"00", -- 0x09B8 - x"3C",x"66",x"66",x"3C",x"66",x"66",x"3C",x"00", -- 0x09C0 - x"3C",x"66",x"66",x"3E",x"06",x"66",x"3C",x"00", -- 0x09C8 - x"00",x"00",x"18",x"00",x"00",x"18",x"00",x"00", -- 0x09D0 - x"00",x"00",x"18",x"00",x"00",x"18",x"18",x"30", -- 0x09D8 - x"0E",x"18",x"30",x"60",x"30",x"18",x"0E",x"00", -- 0x09E0 - x"00",x"00",x"7E",x"00",x"7E",x"00",x"00",x"00", -- 0x09E8 - x"70",x"18",x"0C",x"06",x"0C",x"18",x"70",x"00", -- 0x09F0 - x"3C",x"66",x"06",x"0C",x"18",x"00",x"18",x"00", -- 0x09F8 - x"00",x"00",x"00",x"FF",x"FF",x"00",x"00",x"00", -- 0x0A00 - x"18",x"3C",x"66",x"7E",x"66",x"66",x"66",x"00", -- 0x0A08 - x"7C",x"66",x"66",x"7C",x"66",x"66",x"7C",x"00", -- 0x0A10 - x"3C",x"66",x"60",x"60",x"60",x"66",x"3C",x"00", -- 0x0A18 - x"78",x"6C",x"66",x"66",x"66",x"6C",x"78",x"00", -- 0x0A20 - x"7E",x"60",x"60",x"78",x"60",x"60",x"7E",x"00", -- 0x0A28 - x"7E",x"60",x"60",x"78",x"60",x"60",x"60",x"00", -- 0x0A30 - x"3C",x"66",x"60",x"6E",x"66",x"66",x"3C",x"00", -- 0x0A38 - x"66",x"66",x"66",x"7E",x"66",x"66",x"66",x"00", -- 0x0A40 - x"3C",x"18",x"18",x"18",x"18",x"18",x"3C",x"00", -- 0x0A48 - x"1E",x"0C",x"0C",x"0C",x"0C",x"6C",x"38",x"00", -- 0x0A50 - x"66",x"6C",x"78",x"70",x"78",x"6C",x"66",x"00", -- 0x0A58 - x"60",x"60",x"60",x"60",x"60",x"60",x"7E",x"00", -- 0x0A60 - x"63",x"77",x"7F",x"6B",x"63",x"63",x"63",x"00", -- 0x0A68 - x"66",x"76",x"7E",x"7E",x"6E",x"66",x"66",x"00", -- 0x0A70 - x"3C",x"66",x"66",x"66",x"66",x"66",x"3C",x"00", -- 0x0A78 - x"7C",x"66",x"66",x"7C",x"60",x"60",x"60",x"00", -- 0x0A80 - x"3C",x"66",x"66",x"66",x"66",x"3C",x"0E",x"00", -- 0x0A88 - x"7C",x"66",x"66",x"7C",x"78",x"6C",x"66",x"00", -- 0x0A90 - x"3C",x"66",x"60",x"3C",x"06",x"66",x"3C",x"00", -- 0x0A98 - x"7E",x"18",x"18",x"18",x"18",x"18",x"18",x"00", -- 0x0AA0 - x"66",x"66",x"66",x"66",x"66",x"66",x"3C",x"00", -- 0x0AA8 - x"66",x"66",x"66",x"66",x"66",x"3C",x"18",x"00", -- 0x0AB0 - x"63",x"63",x"63",x"6B",x"7F",x"77",x"63",x"00", -- 0x0AB8 - x"66",x"66",x"3C",x"18",x"3C",x"66",x"66",x"00", -- 0x0AC0 - x"66",x"66",x"66",x"3C",x"18",x"18",x"18",x"00", -- 0x0AC8 - x"7E",x"06",x"0C",x"18",x"30",x"60",x"7E",x"00", -- 0x0AD0 - x"18",x"18",x"18",x"FF",x"FF",x"18",x"18",x"18", -- 0x0AD8 - x"C0",x"C0",x"30",x"30",x"C0",x"C0",x"30",x"30", -- 0x0AE0 - x"18",x"18",x"18",x"18",x"18",x"18",x"18",x"18", -- 0x0AE8 - x"33",x"33",x"CC",x"CC",x"33",x"33",x"CC",x"CC", -- 0x0AF0 - x"33",x"99",x"CC",x"66",x"33",x"99",x"CC",x"66", -- 0x0AF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B00 - x"F0",x"F0",x"F0",x"F0",x"F0",x"F0",x"F0",x"F0", -- 0x0B08 - x"00",x"00",x"00",x"00",x"FF",x"FF",x"FF",x"FF", -- 0x0B10 - x"FF",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"FF", -- 0x0B20 - x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0", -- 0x0B28 - x"CC",x"CC",x"33",x"33",x"CC",x"CC",x"33",x"33", -- 0x0B30 - x"03",x"03",x"03",x"03",x"03",x"03",x"03",x"03", -- 0x0B38 - x"00",x"00",x"00",x"00",x"CC",x"CC",x"33",x"33", -- 0x0B40 - x"CC",x"99",x"33",x"66",x"CC",x"99",x"33",x"66", -- 0x0B48 - x"03",x"03",x"03",x"03",x"03",x"03",x"03",x"03", -- 0x0B50 - x"18",x"18",x"18",x"1F",x"1F",x"18",x"18",x"18", -- 0x0B58 - x"00",x"00",x"00",x"00",x"0F",x"0F",x"0F",x"0F", -- 0x0B60 - x"18",x"18",x"18",x"1F",x"1F",x"00",x"00",x"00", -- 0x0B68 - x"00",x"00",x"00",x"F8",x"F8",x"18",x"18",x"18", -- 0x0B70 - x"00",x"00",x"00",x"00",x"00",x"00",x"FF",x"FF", -- 0x0B78 - x"00",x"00",x"00",x"1F",x"1F",x"18",x"18",x"18", -- 0x0B80 - x"18",x"18",x"18",x"FF",x"FF",x"00",x"00",x"00", -- 0x0B88 - x"00",x"00",x"00",x"FF",x"FF",x"18",x"18",x"18", -- 0x0B90 - x"18",x"18",x"18",x"F8",x"F8",x"18",x"18",x"18", -- 0x0B98 - x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0", -- 0x0BA0 - x"E0",x"E0",x"E0",x"E0",x"E0",x"E0",x"E0",x"E0", -- 0x0BA8 - x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"07", -- 0x0BB0 - x"FF",x"FF",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BB8 - x"FF",x"FF",x"FF",x"00",x"00",x"00",x"00",x"00", -- 0x0BC0 - x"00",x"00",x"00",x"00",x"00",x"FF",x"FF",x"FF", -- 0x0BC8 - x"01",x"03",x"06",x"6C",x"78",x"70",x"60",x"00", -- 0x0BD0 - x"00",x"00",x"00",x"00",x"F0",x"F0",x"F0",x"F0", -- 0x0BD8 - x"0F",x"0F",x"0F",x"0F",x"00",x"00",x"00",x"00", -- 0x0BE0 - x"18",x"18",x"18",x"F8",x"F8",x"00",x"00",x"00", -- 0x0BE8 - x"F0",x"F0",x"F0",x"F0",x"00",x"00",x"00",x"00", -- 0x0BF0 - x"F0",x"F0",x"F0",x"F0",x"0F",x"0F",x"0F",x"0F", -- 0x0BF8 - x"C3",x"99",x"91",x"91",x"9F",x"99",x"C3",x"FF", -- 0x0C00 - x"FF",x"FF",x"C3",x"F9",x"C1",x"99",x"C1",x"FF", -- 0x0C08 - x"FF",x"9F",x"9F",x"83",x"99",x"99",x"83",x"FF", -- 0x0C10 - x"FF",x"FF",x"C3",x"9F",x"9F",x"9F",x"C3",x"FF", -- 0x0C18 - x"FF",x"F9",x"F9",x"C1",x"99",x"99",x"C1",x"FF", -- 0x0C20 - x"FF",x"FF",x"C3",x"99",x"81",x"9F",x"C3",x"FF", -- 0x0C28 - x"FF",x"F1",x"E7",x"C1",x"E7",x"E7",x"E7",x"FF", -- 0x0C30 - x"FF",x"FF",x"C1",x"99",x"99",x"C1",x"F9",x"83", -- 0x0C38 - x"FF",x"9F",x"9F",x"83",x"99",x"99",x"99",x"FF", -- 0x0C40 - x"FF",x"E7",x"FF",x"C7",x"E7",x"E7",x"C3",x"FF", -- 0x0C48 - x"FF",x"F9",x"FF",x"F9",x"F9",x"F9",x"F9",x"C3", -- 0x0C50 - x"FF",x"9F",x"9F",x"93",x"87",x"93",x"99",x"FF", -- 0x0C58 - x"FF",x"C7",x"E7",x"E7",x"E7",x"E7",x"C3",x"FF", -- 0x0C60 - x"FF",x"FF",x"99",x"80",x"80",x"94",x"9C",x"FF", -- 0x0C68 - x"FF",x"FF",x"83",x"99",x"99",x"99",x"99",x"FF", -- 0x0C70 - x"FF",x"FF",x"C3",x"99",x"99",x"99",x"C3",x"FF", -- 0x0C78 - x"FF",x"FF",x"83",x"99",x"99",x"83",x"9F",x"9F", -- 0x0C80 - x"FF",x"FF",x"C1",x"99",x"99",x"C1",x"F9",x"F9", -- 0x0C88 - x"FF",x"FF",x"83",x"99",x"9F",x"9F",x"9F",x"FF", -- 0x0C90 - x"FF",x"FF",x"C1",x"9F",x"C3",x"F9",x"83",x"FF", -- 0x0C98 - x"FF",x"E7",x"81",x"E7",x"E7",x"E7",x"F1",x"FF", -- 0x0CA0 - x"FF",x"FF",x"99",x"99",x"99",x"99",x"C1",x"FF", -- 0x0CA8 - x"FF",x"FF",x"99",x"99",x"99",x"C3",x"E7",x"FF", -- 0x0CB0 - x"FF",x"FF",x"9C",x"94",x"80",x"C1",x"C9",x"FF", -- 0x0CB8 - x"FF",x"FF",x"99",x"C3",x"E7",x"C3",x"99",x"FF", -- 0x0CC0 - x"FF",x"FF",x"99",x"99",x"99",x"C1",x"F3",x"87", -- 0x0CC8 - x"FF",x"FF",x"81",x"F3",x"E7",x"CF",x"81",x"FF", -- 0x0CD0 - x"C3",x"CF",x"CF",x"CF",x"CF",x"CF",x"C3",x"FF", -- 0x0CD8 - x"F3",x"ED",x"CF",x"83",x"CF",x"9D",x"03",x"FF", -- 0x0CE0 - x"C3",x"F3",x"F3",x"F3",x"F3",x"F3",x"C3",x"FF", -- 0x0CE8 - x"FF",x"E7",x"C3",x"81",x"E7",x"E7",x"E7",x"E7", -- 0x0CF0 - x"FF",x"EF",x"CF",x"80",x"80",x"CF",x"EF",x"FF", -- 0x0CF8 - x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0D00 - x"E7",x"E7",x"E7",x"E7",x"FF",x"FF",x"E7",x"FF", -- 0x0D08 - x"99",x"99",x"99",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0D10 - x"99",x"99",x"00",x"99",x"00",x"99",x"99",x"FF", -- 0x0D18 - x"E7",x"C1",x"9F",x"C3",x"F9",x"83",x"E7",x"FF", -- 0x0D20 - x"9D",x"99",x"F3",x"E7",x"CF",x"99",x"B9",x"FF", -- 0x0D28 - x"C3",x"99",x"C3",x"C7",x"98",x"99",x"C0",x"FF", -- 0x0D30 - x"F9",x"F3",x"E7",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0D38 - x"F3",x"E7",x"CF",x"CF",x"CF",x"E7",x"F3",x"FF", -- 0x0D40 - x"CF",x"E7",x"F3",x"F3",x"F3",x"E7",x"CF",x"FF", -- 0x0D48 - x"FF",x"99",x"C3",x"00",x"C3",x"99",x"FF",x"FF", -- 0x0D50 - x"FF",x"E7",x"E7",x"81",x"E7",x"E7",x"FF",x"FF", -- 0x0D58 - x"FF",x"FF",x"FF",x"FF",x"FF",x"E7",x"E7",x"CF", -- 0x0D60 - x"FF",x"FF",x"FF",x"81",x"FF",x"FF",x"FF",x"FF", -- 0x0D68 - x"FF",x"FF",x"FF",x"FF",x"FF",x"E7",x"E7",x"FF", -- 0x0D70 - x"FF",x"FC",x"F9",x"F3",x"E7",x"CF",x"9F",x"FF", -- 0x0D78 - x"C3",x"99",x"91",x"89",x"99",x"99",x"C3",x"FF", -- 0x0D80 - x"E7",x"E7",x"C7",x"E7",x"E7",x"E7",x"81",x"FF", -- 0x0D88 - x"C3",x"99",x"F9",x"F3",x"CF",x"9F",x"81",x"FF", -- 0x0D90 - x"C3",x"99",x"F9",x"E3",x"F9",x"99",x"C3",x"FF", -- 0x0D98 - x"F9",x"F1",x"E1",x"99",x"80",x"F9",x"F9",x"FF", -- 0x0DA0 - x"81",x"9F",x"83",x"F9",x"F9",x"99",x"C3",x"FF", -- 0x0DA8 - x"C3",x"99",x"9F",x"83",x"99",x"99",x"C3",x"FF", -- 0x0DB0 - x"81",x"99",x"F3",x"E7",x"E7",x"E7",x"E7",x"FF", -- 0x0DB8 - x"C3",x"99",x"99",x"C3",x"99",x"99",x"C3",x"FF", -- 0x0DC0 - x"C3",x"99",x"99",x"C1",x"F9",x"99",x"C3",x"FF", -- 0x0DC8 - x"FF",x"FF",x"E7",x"FF",x"FF",x"E7",x"FF",x"FF", -- 0x0DD0 - x"FF",x"FF",x"E7",x"FF",x"FF",x"E7",x"E7",x"CF", -- 0x0DD8 - x"F1",x"E7",x"CF",x"9F",x"CF",x"E7",x"F1",x"FF", -- 0x0DE0 - x"FF",x"FF",x"81",x"FF",x"81",x"FF",x"FF",x"FF", -- 0x0DE8 - x"8F",x"E7",x"F3",x"F9",x"F3",x"E7",x"8F",x"FF", -- 0x0DF0 - x"C3",x"99",x"F9",x"F3",x"E7",x"FF",x"E7",x"FF", -- 0x0DF8 - x"FF",x"FF",x"FF",x"00",x"00",x"FF",x"FF",x"FF", -- 0x0E00 - x"E7",x"C3",x"99",x"81",x"99",x"99",x"99",x"FF", -- 0x0E08 - x"83",x"99",x"99",x"83",x"99",x"99",x"83",x"FF", -- 0x0E10 - x"C3",x"99",x"9F",x"9F",x"9F",x"99",x"C3",x"FF", -- 0x0E18 - x"87",x"93",x"99",x"99",x"99",x"93",x"87",x"FF", -- 0x0E20 - x"81",x"9F",x"9F",x"87",x"9F",x"9F",x"81",x"FF", -- 0x0E28 - x"81",x"9F",x"9F",x"87",x"9F",x"9F",x"9F",x"FF", -- 0x0E30 - x"C3",x"99",x"9F",x"91",x"99",x"99",x"C3",x"FF", -- 0x0E38 - x"99",x"99",x"99",x"81",x"99",x"99",x"99",x"FF", -- 0x0E40 - x"C3",x"E7",x"E7",x"E7",x"E7",x"E7",x"C3",x"FF", -- 0x0E48 - x"E1",x"F3",x"F3",x"F3",x"F3",x"93",x"C7",x"FF", -- 0x0E50 - x"99",x"93",x"87",x"8F",x"87",x"93",x"99",x"FF", -- 0x0E58 - x"9F",x"9F",x"9F",x"9F",x"9F",x"9F",x"81",x"FF", -- 0x0E60 - x"9C",x"88",x"80",x"94",x"9C",x"9C",x"9C",x"FF", -- 0x0E68 - x"99",x"89",x"81",x"81",x"91",x"99",x"99",x"FF", -- 0x0E70 - x"C3",x"99",x"99",x"99",x"99",x"99",x"C3",x"FF", -- 0x0E78 - x"83",x"99",x"99",x"83",x"9F",x"9F",x"9F",x"FF", -- 0x0E80 - x"C3",x"99",x"99",x"99",x"99",x"C3",x"F1",x"FF", -- 0x0E88 - x"83",x"99",x"99",x"83",x"87",x"93",x"99",x"FF", -- 0x0E90 - x"C3",x"99",x"9F",x"C3",x"F9",x"99",x"C3",x"FF", -- 0x0E98 - x"81",x"E7",x"E7",x"E7",x"E7",x"E7",x"E7",x"FF", -- 0x0EA0 - x"99",x"99",x"99",x"99",x"99",x"99",x"C3",x"FF", -- 0x0EA8 - x"99",x"99",x"99",x"99",x"99",x"C3",x"E7",x"FF", -- 0x0EB0 - x"9C",x"9C",x"9C",x"94",x"80",x"88",x"9C",x"FF", -- 0x0EB8 - x"99",x"99",x"C3",x"E7",x"C3",x"99",x"99",x"FF", -- 0x0EC0 - x"99",x"99",x"99",x"C3",x"E7",x"E7",x"E7",x"FF", -- 0x0EC8 - x"81",x"F9",x"F3",x"E7",x"CF",x"9F",x"81",x"FF", -- 0x0ED0 - x"E7",x"E7",x"E7",x"00",x"00",x"E7",x"E7",x"E7", -- 0x0ED8 - x"3F",x"3F",x"CF",x"CF",x"3F",x"3F",x"CF",x"CF", -- 0x0EE0 - x"E7",x"E7",x"E7",x"E7",x"E7",x"E7",x"E7",x"E7", -- 0x0EE8 - x"CC",x"CC",x"33",x"33",x"CC",x"CC",x"33",x"33", -- 0x0EF0 - x"CC",x"66",x"33",x"99",x"CC",x"66",x"33",x"99", -- 0x0EF8 - x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0F00 - x"0F",x"0F",x"0F",x"0F",x"0F",x"0F",x"0F",x"0F", -- 0x0F08 - x"FF",x"FF",x"FF",x"FF",x"00",x"00",x"00",x"00", -- 0x0F10 - x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0F18 - x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"00", -- 0x0F20 - x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F", -- 0x0F28 - x"33",x"33",x"CC",x"CC",x"33",x"33",x"CC",x"CC", -- 0x0F30 - x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC", -- 0x0F38 - x"FF",x"FF",x"FF",x"FF",x"33",x"33",x"CC",x"CC", -- 0x0F40 - x"33",x"66",x"CC",x"99",x"33",x"66",x"CC",x"99", -- 0x0F48 - x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC", -- 0x0F50 - x"E7",x"E7",x"E7",x"E0",x"E0",x"E7",x"E7",x"E7", -- 0x0F58 - x"FF",x"FF",x"FF",x"FF",x"F0",x"F0",x"F0",x"F0", -- 0x0F60 - x"E7",x"E7",x"E7",x"E0",x"E0",x"FF",x"FF",x"FF", -- 0x0F68 - x"FF",x"FF",x"FF",x"07",x"07",x"E7",x"E7",x"E7", -- 0x0F70 - x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"00",x"00", -- 0x0F78 - x"FF",x"FF",x"FF",x"E0",x"E0",x"E7",x"E7",x"E7", -- 0x0F80 - x"E7",x"E7",x"E7",x"00",x"00",x"FF",x"FF",x"FF", -- 0x0F88 - x"FF",x"FF",x"FF",x"00",x"00",x"E7",x"E7",x"E7", -- 0x0F90 - x"E7",x"E7",x"E7",x"07",x"07",x"E7",x"E7",x"E7", -- 0x0F98 - x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F", -- 0x0FA0 - x"1F",x"1F",x"1F",x"1F",x"1F",x"1F",x"1F",x"1F", -- 0x0FA8 - x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8", -- 0x0FB0 - x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0FB8 - x"00",x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0FC0 - x"FF",x"FF",x"FF",x"FF",x"FF",x"00",x"00",x"00", -- 0x0FC8 - x"FE",x"FC",x"F9",x"93",x"87",x"8F",x"9F",x"FF", -- 0x0FD0 - x"FF",x"FF",x"FF",x"FF",x"0F",x"0F",x"0F",x"0F", -- 0x0FD8 - x"F0",x"F0",x"F0",x"F0",x"FF",x"FF",x"FF",x"FF", -- 0x0FE0 - x"E7",x"E7",x"E7",x"07",x"07",x"FF",x"FF",x"FF", -- 0x0FE8 - x"0F",x"0F",x"0F",x"0F",x"FF",x"FF",x"FF",x"FF", -- 0x0FF0 - x"0F",x"0F",x"0F",x"0F",x"F0",x"F0",x"F0",x"F0" -- 0x0FF8 - ); - -begin - - p_rom : process - begin - wait until rising_edge(CLK); - DATA <= ROM(to_integer(unsigned(ADDR))); - end process; -end RTL; diff --git a/lib/VGA_ctrl/src/fonts/char_rom_data.vhd b/lib/VGA_ctrl/src/fonts/char_rom_data.vhd deleted file mode 100644 index c52e7f7..0000000 --- a/lib/VGA_ctrl/src/fonts/char_rom_data.vhd +++ /dev/null @@ -1,539 +0,0 @@ -library ieee; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity char_rom is - port ( - CLK : in std_logic; - ADDR : in unsigned(11 downto 0); - DATA : out unsigned(7 downto 0) - ); -end; - -architecture RTL of char_rom is - - - type ROM_ARRAY is array(0 to 4095) of unsigned(7 downto 0); - constant ROM : ROM_ARRAY := ( - x"7C",x"40",x"7C",x"44",x"7C",x"0C",x"0C",x"7C", -- 0x0000 - x"3C",x"24",x"7E",x"62",x"62",x"62",x"62",x"00", -- 0x0008 - x"7C",x"24",x"3E",x"32",x"32",x"32",x"7E",x"00", -- 0x0010 - x"7E",x"42",x"40",x"60",x"60",x"62",x"7E",x"00", -- 0x0018 - x"7E",x"22",x"22",x"32",x"32",x"32",x"7E",x"00", -- 0x0020 - x"7E",x"40",x"40",x"78",x"60",x"60",x"7E",x"00", -- 0x0028 - x"7E",x"40",x"40",x"78",x"60",x"60",x"60",x"00", -- 0x0030 - x"7E",x"42",x"40",x"6E",x"62",x"62",x"7E",x"00", -- 0x0038 - x"42",x"42",x"42",x"7E",x"62",x"62",x"62",x"00", -- 0x0040 - x"10",x"10",x"10",x"18",x"18",x"18",x"18",x"00", -- 0x0048 - x"02",x"02",x"02",x"06",x"06",x"46",x"3C",x"00", -- 0x0050 - x"42",x"44",x"48",x"7E",x"62",x"62",x"62",x"00", -- 0x0058 - x"40",x"40",x"40",x"60",x"60",x"60",x"7E",x"00", -- 0x0060 - x"66",x"5A",x"42",x"62",x"62",x"62",x"62",x"00", -- 0x0068 - x"72",x"4A",x"4A",x"6A",x"6A",x"6A",x"66",x"00", -- 0x0070 - x"7E",x"42",x"42",x"62",x"62",x"62",x"7E",x"00", -- 0x0078 - x"7E",x"42",x"42",x"7E",x"60",x"60",x"60",x"00", -- 0x0080 - x"7E",x"42",x"42",x"62",x"6A",x"64",x"7A",x"00", -- 0x0088 - x"7E",x"42",x"42",x"7E",x"64",x"62",x"62",x"00", -- 0x0090 - x"7E",x"42",x"40",x"7E",x"06",x"46",x"7E",x"00", -- 0x0098 - x"7C",x"10",x"10",x"18",x"18",x"18",x"18",x"00", -- 0x00A0 - x"42",x"42",x"42",x"62",x"62",x"62",x"7E",x"00", -- 0x00A8 - x"42",x"42",x"42",x"24",x"24",x"18",x"18",x"00", -- 0x00B0 - x"62",x"62",x"62",x"62",x"42",x"5A",x"66",x"00", -- 0x00B8 - x"42",x"24",x"18",x"7C",x"62",x"62",x"62",x"00", -- 0x00C0 - x"42",x"42",x"42",x"3C",x"18",x"18",x"18",x"00", -- 0x00C8 - x"7E",x"02",x"1C",x"60",x"60",x"60",x"7E",x"00", -- 0x00D0 - x"3C",x"20",x"20",x"30",x"30",x"30",x"3C",x"00", -- 0x00D8 - x"18",x"20",x"20",x"78",x"60",x"60",x"7C",x"00", -- 0x00E0 - x"3C",x"04",x"04",x"0C",x"0C",x"0C",x"3C",x"00", -- 0x00E8 - x"08",x"1C",x"2A",x"08",x"08",x"08",x"08",x"00", -- 0x00F0 - x"00",x"20",x"40",x"FE",x"40",x"20",x"00",x"00", -- 0x00F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0100 - x"18",x"18",x"1C",x"1C",x"1C",x"00",x"1C",x"00", -- 0x0108 - x"36",x"36",x"12",x"12",x"00",x"00",x"00",x"00", -- 0x0110 - x"24",x"24",x"7E",x"34",x"7E",x"34",x"34",x"00", -- 0x0118 - x"08",x"3E",x"28",x"3E",x"1A",x"3E",x"18",x"00", -- 0x0120 - x"70",x"52",x"74",x"08",x"1E",x"2A",x"4E",x"00", -- 0x0128 - x"78",x"48",x"30",x"70",x"6A",x"64",x"7A",x"00", -- 0x0130 - x"38",x"38",x"08",x"08",x"00",x"00",x"00",x"00", -- 0x0138 - x"0C",x"10",x"20",x"30",x"30",x"10",x"0C",x"00", -- 0x0140 - x"30",x"08",x"04",x"0C",x"0C",x"08",x"30",x"00", -- 0x0148 - x"08",x"2A",x"1C",x"3E",x"1C",x"2A",x"08",x"00", -- 0x0150 - x"00",x"08",x"08",x"3E",x"3E",x"0C",x"0C",x"00", -- 0x0158 - x"00",x"00",x"00",x"00",x"1C",x"1C",x"04",x"04", -- 0x0160 - x"00",x"00",x"00",x"7E",x"7E",x"00",x"00",x"00", -- 0x0168 - x"00",x"00",x"00",x"00",x"00",x"18",x"18",x"00", -- 0x0170 - x"00",x"02",x"04",x"08",x"10",x"20",x"40",x"00", -- 0x0178 - x"7E",x"42",x"46",x"6A",x"72",x"62",x"7E",x"00", -- 0x0180 - x"38",x"08",x"08",x"18",x"18",x"18",x"3C",x"00", -- 0x0188 - x"7E",x"42",x"02",x"7E",x"60",x"60",x"7E",x"00", -- 0x0190 - x"3E",x"02",x"02",x"1E",x"06",x"06",x"7E",x"00", -- 0x0198 - x"40",x"40",x"44",x"44",x"7E",x"0C",x"0C",x"00", -- 0x01A0 - x"3E",x"20",x"20",x"3E",x"06",x"46",x"7E",x"00", -- 0x01A8 - x"7E",x"40",x"40",x"7E",x"62",x"62",x"7E",x"00", -- 0x01B0 - x"7E",x"42",x"04",x"08",x"18",x"18",x"18",x"00", -- 0x01B8 - x"3C",x"24",x"24",x"7E",x"62",x"62",x"7E",x"00", -- 0x01C0 - x"7E",x"42",x"42",x"7E",x"06",x"06",x"7E",x"00", -- 0x01C8 - x"00",x"00",x"18",x"00",x"18",x"18",x"00",x"00", -- 0x01D0 - x"00",x"00",x"1C",x"00",x"1C",x"1C",x"04",x"04", -- 0x01D8 - x"0E",x"18",x"30",x"60",x"30",x"18",x"0E",x"00", -- 0x01E0 - x"00",x"00",x"7E",x"00",x"7E",x"7E",x"00",x"00", -- 0x01E8 - x"70",x"18",x"0C",x"06",x"0C",x"18",x"70",x"00", -- 0x01F0 - x"7E",x"42",x"02",x"3E",x"30",x"00",x"30",x"00", -- 0x01F8 - x"00",x"00",x"00",x"00",x"FF",x"00",x"00",x"00", -- 0x0200 - x"18",x"3C",x"7E",x"7E",x"18",x"18",x"7E",x"00", -- 0x0208 - x"10",x"10",x"10",x"10",x"10",x"10",x"10",x"10", -- 0x0210 - x"00",x"00",x"00",x"FF",x"00",x"00",x"00",x"00", -- 0x0218 - x"00",x"00",x"FF",x"00",x"00",x"00",x"00",x"00", -- 0x0220 - x"00",x"FF",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0228 - x"00",x"00",x"00",x"00",x"00",x"FF",x"00",x"00", -- 0x0230 - x"20",x"20",x"20",x"20",x"20",x"20",x"20",x"20", -- 0x0238 - x"04",x"04",x"04",x"04",x"04",x"04",x"04",x"04", -- 0x0240 - x"00",x"00",x"00",x"C0",x"30",x"10",x"08",x"08", -- 0x0248 - x"10",x"10",x"08",x"0C",x"03",x"00",x"00",x"00", -- 0x0250 - x"08",x"08",x"10",x"30",x"C0",x"00",x"00",x"00", -- 0x0258 - x"80",x"80",x"80",x"80",x"80",x"80",x"80",x"FF", -- 0x0260 - x"80",x"40",x"20",x"10",x"08",x"04",x"02",x"01", -- 0x0268 - x"01",x"02",x"04",x"08",x"10",x"20",x"40",x"80", -- 0x0270 - x"FF",x"80",x"80",x"80",x"80",x"80",x"80",x"80", -- 0x0278 - x"FF",x"01",x"01",x"01",x"01",x"01",x"01",x"01", -- 0x0280 - x"3C",x"7E",x"7E",x"7E",x"7E",x"7E",x"3C",x"00", -- 0x0288 - x"00",x"00",x"00",x"00",x"00",x"00",x"FF",x"00", -- 0x0290 - x"24",x"7E",x"7E",x"7E",x"3C",x"18",x"18",x"00", -- 0x0298 - x"40",x"40",x"40",x"40",x"40",x"40",x"40",x"40", -- 0x02A0 - x"00",x"00",x"00",x"03",x"0C",x"08",x"10",x"10", -- 0x02A8 - x"81",x"42",x"24",x"18",x"18",x"24",x"42",x"81", -- 0x02B0 - x"3C",x"7E",x"66",x"42",x"66",x"7E",x"3C",x"00", -- 0x02B8 - x"18",x"18",x"7E",x"7E",x"18",x"18",x"7E",x"00", -- 0x02C0 - x"02",x"02",x"02",x"02",x"02",x"02",x"02",x"02", -- 0x02C8 - x"00",x"18",x"3C",x"7E",x"7E",x"3C",x"18",x"00", -- 0x02D0 - x"08",x"08",x"08",x"FF",x"08",x"08",x"08",x"08", -- 0x02D8 - x"C0",x"30",x"C0",x"30",x"C0",x"30",x"C0",x"30", -- 0x02E0 - x"08",x"08",x"08",x"08",x"08",x"08",x"08",x"08", -- 0x02E8 - x"00",x"00",x"7C",x"24",x"64",x"64",x"66",x"00", -- 0x02F0 - x"FF",x"7F",x"3F",x"1F",x"0F",x"07",x"03",x"01", -- 0x02F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0300 - x"F0",x"F0",x"F0",x"F0",x"F0",x"F0",x"F0",x"F0", -- 0x0308 - x"00",x"00",x"00",x"00",x"FF",x"FF",x"FF",x"FF", -- 0x0310 - x"FF",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0318 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"FF", -- 0x0320 - x"80",x"80",x"80",x"80",x"80",x"80",x"80",x"80", -- 0x0328 - x"CC",x"33",x"CC",x"33",x"CC",x"33",x"CC",x"33", -- 0x0330 - x"01",x"01",x"01",x"01",x"01",x"01",x"01",x"01", -- 0x0338 - x"00",x"00",x"00",x"00",x"CC",x"33",x"CC",x"33", -- 0x0340 - x"FF",x"FE",x"FC",x"F8",x"F0",x"E0",x"C0",x"80", -- 0x0348 - x"03",x"03",x"03",x"03",x"03",x"03",x"03",x"03", -- 0x0350 - x"08",x"08",x"08",x"0F",x"08",x"08",x"08",x"08", -- 0x0358 - x"00",x"00",x"00",x"00",x"0F",x"0F",x"0F",x"0F", -- 0x0360 - x"08",x"08",x"08",x"0F",x"00",x"00",x"00",x"00", -- 0x0368 - x"00",x"00",x"00",x"F8",x"08",x"08",x"08",x"08", -- 0x0370 - x"00",x"00",x"00",x"00",x"00",x"00",x"FF",x"FF", -- 0x0378 - x"00",x"00",x"00",x"0F",x"08",x"08",x"08",x"08", -- 0x0380 - x"08",x"08",x"08",x"FF",x"00",x"00",x"00",x"00", -- 0x0388 - x"00",x"00",x"00",x"FF",x"08",x"08",x"08",x"08", -- 0x0390 - x"08",x"08",x"08",x"F8",x"08",x"08",x"08",x"08", -- 0x0398 - x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0", -- 0x03A0 - x"E0",x"E0",x"E0",x"E0",x"E0",x"E0",x"E0",x"E0", -- 0x03A8 - x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"07", -- 0x03B0 - x"FF",x"FF",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03B8 - x"FF",x"FF",x"FF",x"00",x"00",x"00",x"00",x"00", -- 0x03C0 - x"00",x"00",x"00",x"00",x"00",x"FF",x"FF",x"FF", -- 0x03C8 - x"01",x"01",x"01",x"01",x"01",x"01",x"01",x"FF", -- 0x03D0 - x"00",x"00",x"00",x"00",x"F0",x"F0",x"F0",x"F0", -- 0x03D8 - x"0F",x"0F",x"0F",x"0F",x"00",x"00",x"00",x"00", -- 0x03E0 - x"08",x"08",x"08",x"F8",x"00",x"00",x"00",x"00", -- 0x03E8 - x"F0",x"F0",x"F0",x"F0",x"00",x"00",x"00",x"00", -- 0x03F0 - x"F0",x"F0",x"F0",x"F0",x"0F",x"0F",x"0F",x"0F", -- 0x03F8 - x"83",x"BF",x"83",x"BB",x"83",x"F3",x"F3",x"83", -- 0x0400 - x"C3",x"DB",x"81",x"9D",x"9D",x"9D",x"9D",x"FF", -- 0x0408 - x"83",x"DB",x"C1",x"CD",x"CD",x"CD",x"81",x"FF", -- 0x0410 - x"81",x"BD",x"BF",x"9F",x"9F",x"9D",x"81",x"FF", -- 0x0418 - x"81",x"DD",x"DD",x"CD",x"CD",x"CD",x"81",x"FF", -- 0x0420 - x"81",x"BF",x"BF",x"87",x"9F",x"9F",x"81",x"FF", -- 0x0428 - x"81",x"BF",x"BF",x"87",x"9F",x"9F",x"9F",x"FF", -- 0x0430 - x"81",x"BD",x"BF",x"91",x"9D",x"9D",x"81",x"FF", -- 0x0438 - x"BD",x"BD",x"BD",x"81",x"9D",x"9D",x"9D",x"FF", -- 0x0440 - x"EF",x"EF",x"EF",x"E7",x"E7",x"E7",x"E7",x"FF", -- 0x0448 - x"FD",x"FD",x"FD",x"F9",x"F9",x"B9",x"C3",x"FF", -- 0x0450 - x"BD",x"BB",x"B7",x"81",x"9D",x"9D",x"9D",x"FF", -- 0x0458 - x"BF",x"BF",x"BF",x"9F",x"9F",x"9F",x"81",x"FF", -- 0x0460 - x"99",x"A5",x"BD",x"9D",x"9D",x"9D",x"9D",x"FF", -- 0x0468 - x"8D",x"B5",x"B5",x"95",x"95",x"95",x"99",x"FF", -- 0x0470 - x"81",x"BD",x"BD",x"9D",x"9D",x"9D",x"81",x"FF", -- 0x0478 - x"81",x"BD",x"BD",x"81",x"9F",x"9F",x"9F",x"FF", -- 0x0480 - x"81",x"BD",x"BD",x"9D",x"95",x"9B",x"85",x"FF", -- 0x0488 - x"81",x"BD",x"BD",x"81",x"9B",x"9D",x"9D",x"FF", -- 0x0490 - x"81",x"BD",x"BF",x"81",x"F9",x"B9",x"81",x"FF", -- 0x0498 - x"83",x"EF",x"EF",x"E7",x"E7",x"E7",x"E7",x"FF", -- 0x04A0 - x"BD",x"BD",x"BD",x"9D",x"9D",x"9D",x"81",x"FF", -- 0x04A8 - x"BD",x"BD",x"BD",x"DB",x"DB",x"E7",x"E7",x"FF", -- 0x04B0 - x"9D",x"9D",x"9D",x"9D",x"BD",x"A5",x"99",x"FF", -- 0x04B8 - x"BD",x"DB",x"E7",x"83",x"9D",x"9D",x"9D",x"FF", -- 0x04C0 - x"BD",x"BD",x"BD",x"C3",x"E7",x"E7",x"E7",x"FF", -- 0x04C8 - x"81",x"FD",x"E3",x"9F",x"9F",x"9F",x"81",x"FF", -- 0x04D0 - x"C3",x"DF",x"DF",x"CF",x"CF",x"CF",x"C3",x"FF", -- 0x04D8 - x"E7",x"DF",x"DF",x"87",x"9F",x"9F",x"83",x"FF", -- 0x04E0 - x"C3",x"FB",x"FB",x"F3",x"F3",x"F3",x"C3",x"FF", -- 0x04E8 - x"F7",x"E3",x"D5",x"F7",x"F7",x"F7",x"F7",x"FF", -- 0x04F0 - x"FF",x"DF",x"BF",x"01",x"BF",x"DF",x"FF",x"FF", -- 0x04F8 - x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0500 - x"E7",x"E7",x"E3",x"E3",x"E3",x"FF",x"E3",x"FF", -- 0x0508 - x"C9",x"C9",x"ED",x"ED",x"FF",x"FF",x"FF",x"FF", -- 0x0510 - x"DB",x"DB",x"81",x"CB",x"81",x"CB",x"CB",x"FF", -- 0x0518 - x"F7",x"C1",x"D7",x"C1",x"E5",x"C1",x"E7",x"FF", -- 0x0520 - x"8F",x"AD",x"8B",x"F7",x"E1",x"D5",x"B1",x"FF", -- 0x0528 - x"87",x"B7",x"CF",x"8F",x"95",x"9B",x"85",x"FF", -- 0x0530 - x"C7",x"C7",x"F7",x"F7",x"FF",x"FF",x"FF",x"FF", -- 0x0538 - x"F3",x"EF",x"DF",x"CF",x"CF",x"EF",x"F3",x"FF", -- 0x0540 - x"CF",x"F7",x"FB",x"F3",x"F3",x"F7",x"CF",x"FF", -- 0x0548 - x"F7",x"D5",x"E3",x"C1",x"E3",x"D5",x"F7",x"FF", -- 0x0550 - x"FF",x"F7",x"F7",x"C1",x"C1",x"F3",x"F3",x"FF", -- 0x0558 - x"FF",x"FF",x"FF",x"FF",x"E3",x"E3",x"FB",x"FB", -- 0x0560 - x"FF",x"FF",x"FF",x"81",x"81",x"FF",x"FF",x"FF", -- 0x0568 - x"FF",x"FF",x"FF",x"FF",x"FF",x"E7",x"E7",x"FF", -- 0x0570 - x"FF",x"FD",x"FB",x"F7",x"EF",x"DF",x"BF",x"FF", -- 0x0578 - x"81",x"BD",x"B9",x"95",x"8D",x"9D",x"81",x"FF", -- 0x0580 - x"C7",x"F7",x"F7",x"E7",x"E7",x"E7",x"C3",x"FF", -- 0x0588 - x"81",x"BD",x"FD",x"81",x"9F",x"9F",x"81",x"FF", -- 0x0590 - x"C1",x"FD",x"FD",x"E1",x"F9",x"F9",x"81",x"FF", -- 0x0598 - x"BF",x"BF",x"BB",x"BB",x"81",x"F3",x"F3",x"FF", -- 0x05A0 - x"C1",x"DF",x"DF",x"C1",x"F9",x"B9",x"81",x"FF", -- 0x05A8 - x"81",x"BF",x"BF",x"81",x"9D",x"9D",x"81",x"FF", -- 0x05B0 - x"81",x"BD",x"FB",x"F7",x"E7",x"E7",x"E7",x"FF", -- 0x05B8 - x"C3",x"DB",x"DB",x"81",x"9D",x"9D",x"81",x"FF", -- 0x05C0 - x"81",x"BD",x"BD",x"81",x"F9",x"F9",x"81",x"FF", -- 0x05C8 - x"FF",x"FF",x"E7",x"FF",x"E7",x"E7",x"FF",x"FF", -- 0x05D0 - x"FF",x"FF",x"E3",x"FF",x"E3",x"E3",x"FB",x"FB", -- 0x05D8 - x"F1",x"E7",x"CF",x"9F",x"CF",x"E7",x"F1",x"FF", -- 0x05E0 - x"FF",x"FF",x"81",x"FF",x"81",x"81",x"FF",x"FF", -- 0x05E8 - x"8F",x"E7",x"F3",x"F9",x"F3",x"E7",x"8F",x"FF", -- 0x05F0 - x"81",x"BD",x"FD",x"C1",x"CF",x"FF",x"CF",x"FF", -- 0x05F8 - x"FF",x"FF",x"FF",x"FF",x"00",x"FF",x"FF",x"FF", -- 0x0600 - x"E7",x"C3",x"81",x"81",x"E7",x"E7",x"81",x"FF", -- 0x0608 - x"EF",x"EF",x"EF",x"EF",x"EF",x"EF",x"EF",x"EF", -- 0x0610 - x"FF",x"FF",x"FF",x"00",x"FF",x"FF",x"FF",x"FF", -- 0x0618 - x"FF",x"FF",x"00",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0620 - x"FF",x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0628 - x"FF",x"FF",x"FF",x"FF",x"FF",x"00",x"FF",x"FF", -- 0x0630 - x"DF",x"DF",x"DF",x"DF",x"DF",x"DF",x"DF",x"DF", -- 0x0638 - x"FB",x"FB",x"FB",x"FB",x"FB",x"FB",x"FB",x"FB", -- 0x0640 - x"FF",x"FF",x"FF",x"3F",x"CF",x"EF",x"F7",x"F7", -- 0x0648 - x"EF",x"EF",x"F7",x"F3",x"FC",x"FF",x"FF",x"FF", -- 0x0650 - x"F7",x"F7",x"EF",x"CF",x"3F",x"FF",x"FF",x"FF", -- 0x0658 - x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"00", -- 0x0660 - x"7F",x"BF",x"DF",x"EF",x"F7",x"FB",x"FD",x"FE", -- 0x0668 - x"FE",x"FD",x"FB",x"F7",x"EF",x"DF",x"BF",x"7F", -- 0x0670 - x"00",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F", -- 0x0678 - x"00",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE", -- 0x0680 - x"C3",x"81",x"81",x"81",x"81",x"81",x"C3",x"FF", -- 0x0688 - x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"00",x"FF", -- 0x0690 - x"DB",x"81",x"81",x"81",x"C3",x"E7",x"E7",x"FF", -- 0x0698 - x"BF",x"BF",x"BF",x"BF",x"BF",x"BF",x"BF",x"BF", -- 0x06A0 - x"FF",x"FF",x"FF",x"FC",x"F3",x"F7",x"EF",x"EF", -- 0x06A8 - x"7E",x"BD",x"DB",x"E7",x"E7",x"DB",x"BD",x"7E", -- 0x06B0 - x"C3",x"81",x"99",x"BD",x"99",x"81",x"C3",x"FF", -- 0x06B8 - x"E7",x"E7",x"81",x"81",x"E7",x"E7",x"81",x"FF", -- 0x06C0 - x"FD",x"FD",x"FD",x"FD",x"FD",x"FD",x"FD",x"FD", -- 0x06C8 - x"FF",x"E7",x"C3",x"81",x"81",x"C3",x"E7",x"FF", -- 0x06D0 - x"F7",x"F7",x"F7",x"00",x"F7",x"F7",x"F7",x"F7", -- 0x06D8 - x"3F",x"CF",x"3F",x"CF",x"3F",x"CF",x"3F",x"CF", -- 0x06E0 - x"F7",x"F7",x"F7",x"F7",x"F7",x"F7",x"F7",x"F7", -- 0x06E8 - x"FF",x"FF",x"83",x"DB",x"9B",x"9B",x"99",x"FF", -- 0x06F0 - x"00",x"80",x"C0",x"E0",x"F0",x"F8",x"FC",x"FE", -- 0x06F8 - x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0700 - x"0F",x"0F",x"0F",x"0F",x"0F",x"0F",x"0F",x"0F", -- 0x0708 - x"FF",x"FF",x"FF",x"FF",x"00",x"00",x"00",x"00", -- 0x0710 - x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0718 - x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"00", -- 0x0720 - x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F", -- 0x0728 - x"33",x"CC",x"33",x"CC",x"33",x"CC",x"33",x"CC", -- 0x0730 - x"FE",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE", -- 0x0738 - x"FF",x"FF",x"FF",x"FF",x"33",x"CC",x"33",x"CC", -- 0x0740 - x"00",x"01",x"03",x"07",x"0F",x"1F",x"3F",x"7F", -- 0x0748 - x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC", -- 0x0750 - x"F7",x"F7",x"F7",x"F0",x"F7",x"F7",x"F7",x"F7", -- 0x0758 - x"FF",x"FF",x"FF",x"FF",x"F0",x"F0",x"F0",x"F0", -- 0x0760 - x"F7",x"F7",x"F7",x"F0",x"FF",x"FF",x"FF",x"FF", -- 0x0768 - x"FF",x"FF",x"FF",x"07",x"F7",x"F7",x"F7",x"F7", -- 0x0770 - x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"00",x"00", -- 0x0778 - x"FF",x"FF",x"FF",x"F0",x"F7",x"F7",x"F7",x"F7", -- 0x0780 - x"F7",x"F7",x"F7",x"00",x"FF",x"FF",x"FF",x"FF", -- 0x0788 - x"FF",x"FF",x"FF",x"00",x"F7",x"F7",x"F7",x"F7", -- 0x0790 - x"F7",x"F7",x"F7",x"07",x"F7",x"F7",x"F7",x"F7", -- 0x0798 - x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F", -- 0x07A0 - x"1F",x"1F",x"1F",x"1F",x"1F",x"1F",x"1F",x"1F", -- 0x07A8 - x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8", -- 0x07B0 - x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x07B8 - x"00",x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x07C0 - x"FF",x"FF",x"FF",x"FF",x"FF",x"00",x"00",x"00", -- 0x07C8 - x"FE",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE",x"00", -- 0x07D0 - x"FF",x"FF",x"FF",x"FF",x"0F",x"0F",x"0F",x"0F", -- 0x07D8 - x"F0",x"F0",x"F0",x"F0",x"FF",x"FF",x"FF",x"FF", -- 0x07E0 - x"F7",x"F7",x"F7",x"07",x"FF",x"FF",x"FF",x"FF", -- 0x07E8 - x"0F",x"0F",x"0F",x"0F",x"FF",x"FF",x"FF",x"FF", -- 0x07F0 - x"0F",x"0F",x"0F",x"0F",x"F0",x"F0",x"F0",x"00", -- 0x07F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0800 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0808 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0810 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0818 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0820 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0828 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0830 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0838 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0840 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0848 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0850 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0858 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0860 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0868 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0870 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0878 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0880 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0888 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0890 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0898 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0900 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0908 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0910 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0918 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0920 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0928 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0930 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0938 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0940 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0948 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0950 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0958 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0960 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0968 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0970 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0978 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0980 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0988 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0990 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0998 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AD8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BD8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CD8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DD8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0ED0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0ED8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FD8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00" -- 0x0FF8 - ); - -begin - - p_rom : process - begin - wait until rising_edge(CLK); - DATA <= ROM(to_integer(unsigned(ADDR))); - end process; -end RTL; diff --git a/lib/VGA_ctrl/src/fonts/char_rom_datasoft.vhd b/lib/VGA_ctrl/src/fonts/char_rom_datasoft.vhd deleted file mode 100644 index 95a9bd1..0000000 --- a/lib/VGA_ctrl/src/fonts/char_rom_datasoft.vhd +++ /dev/null @@ -1,539 +0,0 @@ -library ieee; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity char_rom is - port ( - CLK : in std_logic; - ADDR : in unsigned(11 downto 0); - DATA : out unsigned(7 downto 0) - ); -end; - -architecture RTL of char_rom is - - - type ROM_ARRAY is array(0 to 4095) of unsigned(7 downto 0); - constant ROM : ROM_ARRAY := ( - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0000 - x"08",x"14",x"14",x"22",x"3E",x"41",x"41",x"80", -- 0x0008 - x"FC",x"42",x"42",x"7C",x"42",x"42",x"42",x"FC", -- 0x0010 - x"3C",x"46",x"40",x"40",x"40",x"40",x"46",x"3C", -- 0x0018 - x"FC",x"42",x"42",x"42",x"42",x"42",x"42",x"FC", -- 0x0020 - x"FC",x"46",x"50",x"70",x"50",x"40",x"46",x"FC", -- 0x0028 - x"FC",x"46",x"50",x"70",x"50",x"40",x"40",x"E0", -- 0x0030 - x"3C",x"46",x"40",x"4E",x"44",x"44",x"44",x"3C", -- 0x0038 - x"EE",x"44",x"44",x"7C",x"44",x"44",x"44",x"EE", -- 0x0040 - x"1C",x"08",x"08",x"08",x"08",x"08",x"08",x"1C", -- 0x0048 - x"1C",x"08",x"08",x"08",x"08",x"08",x"C8",x"70", -- 0x0050 - x"E6",x"48",x"50",x"60",x"50",x"48",x"44",x"EE", -- 0x0058 - x"E0",x"40",x"40",x"40",x"40",x"40",x"46",x"FC", -- 0x0060 - x"C6",x"6C",x"6C",x"54",x"54",x"44",x"44",x"EE", -- 0x0068 - x"CE",x"64",x"64",x"54",x"54",x"4C",x"4C",x"E6", -- 0x0070 - x"3C",x"42",x"42",x"42",x"42",x"42",x"42",x"3C", -- 0x0078 - x"FC",x"42",x"42",x"7C",x"40",x"40",x"40",x"E0", -- 0x0080 - x"3C",x"42",x"42",x"42",x"42",x"4A",x"46",x"3D", -- 0x0088 - x"FC",x"42",x"42",x"7C",x"50",x"48",x"44",x"EE", -- 0x0090 - x"3C",x"42",x"40",x"20",x"1C",x"02",x"C2",x"7C", -- 0x0098 - x"FE",x"92",x"10",x"10",x"10",x"10",x"10",x"38", -- 0x00A0 - x"E7",x"42",x"42",x"42",x"42",x"42",x"42",x"3C", -- 0x00A8 - x"E7",x"42",x"42",x"42",x"42",x"42",x"24",x"18", -- 0x00B0 - x"C3",x"41",x"5D",x"49",x"49",x"55",x"63",x"41", -- 0x00B8 - x"EE",x"44",x"28",x"10",x"10",x"28",x"44",x"EE", -- 0x00C0 - x"EE",x"44",x"44",x"28",x"10",x"10",x"10",x"38", -- 0x00C8 - x"FE",x"84",x"08",x"7C",x"24",x"40",x"82",x"FE", -- 0x00D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0100 - x"10",x"10",x"10",x"10",x"10",x"00",x"10",x"10", -- 0x0108 - x"CC",x"44",x"44",x"22",x"00",x"00",x"00",x"00", -- 0x0110 - x"77",x"22",x"FF",x"22",x"22",x"FF",x"22",x"77", -- 0x0118 - x"10",x"3E",x"50",x"3C",x"12",x"12",x"7C",x"10", -- 0x0120 - x"87",x"42",x"04",x"08",x"10",x"20",x"44",x"E2", -- 0x0128 - x"3C",x"66",x"3C",x"38",x"67",x"66",x"3F",x"00", -- 0x0130 - x"1E",x"08",x"3C",x"00",x"00",x"00",x"00",x"00", -- 0x0138 - x"0E",x"12",x"60",x"40",x"40",x"60",x"12",x"0E", -- 0x0140 - x"70",x"48",x"06",x"02",x"02",x"06",x"48",x"70", -- 0x0148 - x"42",x"24",x"99",x"7E",x"99",x"24",x"42",x"00", -- 0x0150 - x"08",x"08",x"08",x"7F",x"08",x"08",x"08",x"00", -- 0x0158 - x"00",x"00",x"00",x"00",x"00",x"18",x"18",x"30", -- 0x0160 - x"00",x"00",x"00",x"7E",x"00",x"00",x"00",x"00", -- 0x0168 - x"00",x"00",x"00",x"00",x"00",x"18",x"18",x"00", -- 0x0170 - x"00",x"03",x"06",x"0C",x"18",x"30",x"60",x"00", -- 0x0178 - x"7C",x"82",x"82",x"82",x"82",x"82",x"82",x"7C", -- 0x0180 - x"10",x"30",x"50",x"10",x"10",x"10",x"10",x"7C", -- 0x0188 - x"7C",x"C2",x"02",x"1C",x"60",x"80",x"86",x"FC", -- 0x0190 - x"7C",x"C2",x"02",x"1C",x"02",x"02",x"C2",x"7C", -- 0x0198 - x"08",x"18",x"28",x"48",x"FE",x"08",x"08",x"3E", -- 0x01A0 - x"FE",x"80",x"80",x"FC",x"02",x"02",x"C2",x"7C", -- 0x01A8 - x"7C",x"86",x"80",x"FC",x"82",x"82",x"82",x"7C", -- 0x01B0 - x"7E",x"C2",x"04",x"08",x"10",x"10",x"10",x"7C", -- 0x01B8 - x"7C",x"82",x"82",x"7C",x"82",x"82",x"82",x"7C", -- 0x01C0 - x"7C",x"82",x"82",x"7E",x"02",x"02",x"C2",x"7C", -- 0x01C8 - x"00",x"00",x"18",x"00",x"00",x"18",x"00",x"00", -- 0x01D0 - x"00",x"00",x"18",x"00",x"00",x"18",x"18",x"30", -- 0x01D8 - x"0E",x"18",x"30",x"60",x"30",x"18",x"0E",x"00", -- 0x01E0 - x"00",x"00",x"7E",x"00",x"7E",x"00",x"00",x"00", -- 0x01E8 - x"70",x"18",x"0C",x"06",x"0C",x"18",x"70",x"00", -- 0x01F0 - x"3C",x"62",x"02",x"04",x"08",x"08",x"00",x"08", -- 0x01F8 - x"3C",x"66",x"6E",x"6E",x"60",x"62",x"3C",x"00", -- 0x0200 - x"FE",x"FE",x"C6",x"FE",x"C6",x"C6",x"C6",x"C6", -- 0x0208 - x"FE",x"FE",x"C6",x"FC",x"C6",x"C6",x"FE",x"FE", -- 0x0210 - x"FE",x"FE",x"C0",x"C0",x"C0",x"C0",x"FE",x"FE", -- 0x0218 - x"FE",x"FE",x"C6",x"C6",x"C6",x"C6",x"FE",x"FE", -- 0x0220 - x"FE",x"FE",x"C0",x"FE",x"C0",x"C0",x"FE",x"FE", -- 0x0228 - x"FE",x"FE",x"C0",x"FE",x"C0",x"C0",x"C0",x"C0", -- 0x0230 - x"FE",x"FE",x"C0",x"DE",x"C6",x"C6",x"FE",x"FE", -- 0x0238 - x"C6",x"C6",x"C6",x"FE",x"C6",x"C6",x"C6",x"C6", -- 0x0240 - x"18",x"18",x"18",x"18",x"18",x"18",x"18",x"18", -- 0x0248 - x"18",x"18",x"18",x"18",x"18",x"18",x"78",x"78", -- 0x0250 - x"C6",x"C6",x"DC",x"F0",x"D8",x"CC",x"C6",x"C6", -- 0x0258 - x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"FE",x"FE", -- 0x0260 - x"FE",x"FE",x"D6",x"D6",x"D6",x"D6",x"D6",x"D6", -- 0x0268 - x"E6",x"E6",x"F6",x"D6",x"D6",x"DE",x"CE",x"CE", -- 0x0270 - x"FE",x"FE",x"C6",x"C6",x"C6",x"C6",x"FE",x"FE", -- 0x0278 - x"FE",x"FE",x"C6",x"FE",x"C0",x"C0",x"C0",x"C0", -- 0x0280 - x"FE",x"FE",x"C6",x"C6",x"C6",x"CE",x"FE",x"FF", -- 0x0288 - x"FE",x"FE",x"C6",x"FE",x"D8",x"D8",x"C6",x"C6", -- 0x0290 - x"FE",x"FE",x"C0",x"FE",x"06",x"06",x"FE",x"FE", -- 0x0298 - x"FE",x"FE",x"18",x"18",x"18",x"18",x"18",x"18", -- 0x02A0 - x"C6",x"C6",x"C6",x"C6",x"C6",x"C6",x"FE",x"FE", -- 0x02A8 - x"C6",x"C6",x"C6",x"C6",x"C6",x"C6",x"FE",x"7C", -- 0x02B0 - x"D6",x"D6",x"D6",x"D6",x"D6",x"D6",x"FE",x"FE", -- 0x02B8 - x"C6",x"C6",x"6C",x"38",x"38",x"6C",x"C6",x"C6", -- 0x02C0 - x"C6",x"C6",x"C6",x"FE",x"06",x"06",x"FE",x"FE", -- 0x02C8 - x"FE",x"FE",x"0E",x"18",x"30",x"E0",x"FE",x"FE", -- 0x02D0 - x"3C",x"30",x"30",x"30",x"30",x"30",x"3C",x"00", -- 0x02D8 - x"0C",x"12",x"30",x"7C",x"30",x"62",x"FC",x"00", -- 0x02E0 - x"3C",x"0C",x"0C",x"0C",x"0C",x"0C",x"3C",x"00", -- 0x02E8 - x"00",x"18",x"3C",x"7E",x"18",x"18",x"18",x"18", -- 0x02F0 - x"00",x"10",x"30",x"7F",x"7F",x"30",x"10",x"00", -- 0x02F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0300 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0308 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0310 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0318 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0320 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0328 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0330 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0338 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0340 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0348 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0350 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0358 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0360 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0368 - x"00",x"00",x"00",x"07",x"1F",x"3F",x"3F",x"7F", -- 0x0370 - x"00",x"00",x"00",x"E0",x"E0",x"E0",x"E0",x"E0", -- 0x0378 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0380 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0388 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0390 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0398 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0400 - x"03",x"1F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F", -- 0x0408 - x"FC",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"0F", -- 0x0410 - x"00",x"80",x"E0",x"F8",x"F8",x"FE",x"FE",x"FE", -- 0x0418 - x"00",x"00",x"00",x"00",x"00",x"00",x"07",x"07", -- 0x0420 - x"00",x"00",x"00",x"00",x"00",x"00",x"F8",x"FE", -- 0x0428 - x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F", -- 0x0430 - x"00",x"00",x"00",x"00",x"00",x"00",x"F0",x"F0", -- 0x0438 - x"00",x"00",x"00",x"00",x"00",x"00",x"7F",x"7F", -- 0x0440 - x"00",x"00",x"00",x"00",x"00",x"00",x"80",x"E0", -- 0x0448 - x"00",x"00",x"00",x"00",x"00",x"00",x"0F",x"3F", -- 0x0450 - x"00",x"00",x"00",x"00",x"00",x"00",x"C0",x"C0", -- 0x0458 - x"00",x"00",x"00",x"00",x"00",x"00",x"1F",x"7F", -- 0x0460 - x"00",x"00",x"00",x"00",x"00",x"00",x"E0",x"F8", -- 0x0468 - x"7E",x"7E",x"7E",x"7E",x"7E",x"7E",x"7F",x"7F", -- 0x0470 - x"0F",x"0F",x"0F",x"0F",x"0F",x"0F",x"FF",x"FF", -- 0x0478 - x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"FC",x"FC", -- 0x0480 - x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"07", -- 0x0488 - x"F0",x"F0",x"F0",x"F0",x"F0",x"F0",x"F0",x"F1", -- 0x0490 - x"00",x"00",x"00",x"00",x"00",x"00",x"7F",x"FF", -- 0x0498 - x"00",x"00",x"00",x"00",x"00",x"00",x"80",x"E0", -- 0x04A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"0F",x"3F", -- 0x04A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"F0",x"F0", -- 0x04B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0500 - x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F", -- 0x0508 - x"03",x"01",x"01",x"01",x"01",x"01",x"01",x"01", -- 0x0510 - x"FE",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE", -- 0x0518 - x"07",x"07",x"07",x"00",x"00",x"07",x"0F",x"3F", -- 0x0520 - x"FE",x"FF",x"FF",x"7F",x"3F",x"FF",x"FF",x"FF", -- 0x0528 - x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F", -- 0x0530 - x"F0",x"F0",x"F0",x"00",x"00",x"00",x"00",x"03", -- 0x0538 - x"7F",x"7F",x"7F",x"07",x"03",x"7F",x"FF",x"FF", -- 0x0540 - x"E0",x"F0",x"F1",x"F1",x"F3",x"F3",x"F3",x"F1", -- 0x0548 - x"7F",x"FF",x"FF",x"FC",x"F0",x"F0",x"F0",x"F8", -- 0x0550 - x"C0",x"C1",x"C1",x"03",x"03",x"03",x"03",x"03", -- 0x0558 - x"FF",x"FF",x"FF",x"FF",x"F8",x"F0",x"F0",x"F0", -- 0x0560 - x"FC",x"FE",x"FE",x"FF",x"7F",x"3F",x"3F",x"3F", -- 0x0568 - x"7F",x"7F",x"7F",x"7E",x"7E",x"7E",x"7E",x"7E", -- 0x0570 - x"FF",x"FF",x"FF",x"0F",x"0F",x"0F",x"0F",x"0F", -- 0x0578 - x"FC",x"FC",x"FC",x"C0",x"C0",x"C0",x"C0",x"C0", -- 0x0580 - x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"07", -- 0x0588 - x"F3",x"F3",x"F3",x"F3",x"F3",x"F3",x"F3",x"F3", -- 0x0590 - x"FF",x"FF",x"FF",x"F3",x"F1",x"F1",x"F1",x"F1", -- 0x0598 - x"F0",x"F0",x"F8",x"F9",x"F9",x"F9",x"F9",x"F9", -- 0x05A0 - x"7F",x"FF",x"FF",x"FC",x"F8",x"F8",x"F8",x"F8", -- 0x05A8 - x"F0",x"F0",x"F0",x"00",x"00",x"00",x"00",x"00", -- 0x05B0 - x"3C",x"42",x"B9",x"A5",x"B9",x"A9",x"A5",x"42", -- 0x05B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0600 - x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F", -- 0x0608 - x"01",x"01",x"03",x"0F",x"7F",x"7F",x"7F",x"7F", -- 0x0610 - x"FE",x"FE",x"FE",x"FE",x"FE",x"FE",x"FC",x"FC", -- 0x0618 - x"3F",x"7F",x"7E",x"7C",x"7E",x"7F",x"3F",x"3F", -- 0x0620 - x"FF",x"FF",x"3F",x"3F",x"3F",x"BF",x"BF",x"BF", -- 0x0628 - x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"1F", -- 0x0630 - x"03",x"07",x"07",x"07",x"07",x"F7",x"F3",x"F3", -- 0x0638 - x"FF",x"FF",x"E3",x"C3",x"E3",x"FB",x"FB",x"FB", -- 0x0640 - x"F1",x"F0",x"F0",x"F0",x"F0",x"F0",x"F0",x"F0", -- 0x0648 - x"FC",x"FE",x"7F",x"3F",x"1F",x"0F",x"07",x"03", -- 0x0650 - x"03",x"03",x"83",x"C3",x"E3",x"F1",x"F1",x"F0", -- 0x0658 - x"F0",x"F0",x"F0",x"F0",x"F8",x"FF",x"FF",x"FF", -- 0x0660 - x"3F",x"3F",x"3F",x"3F",x"7F",x"FE",x"FE",x"FC", -- 0x0668 - x"7E",x"7E",x"7E",x"7E",x"7E",x"7E",x"7E",x"7E", -- 0x0670 - x"0F",x"0F",x"0F",x"0F",x"0F",x"0F",x"0F",x"07", -- 0x0678 - x"C0",x"C0",x"C0",x"C0",x"C0",x"FC",x"FC",x"FC", -- 0x0680 - x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"07", -- 0x0688 - x"F3",x"F3",x"F3",x"F3",x"F3",x"F3",x"F3",x"F3", -- 0x0690 - x"F1",x"F1",x"F1",x"F1",x"F1",x"F1",x"F1",x"F1", -- 0x0698 - x"F9",x"F9",x"F9",x"F9",x"F9",x"F8",x"F8",x"F8", -- 0x06A0 - x"F8",x"F8",x"F8",x"F8",x"FC",x"FF",x"FF",x"7F", -- 0x06A8 - x"00",x"00",x"00",x"00",x"00",x"FC",x"FC",x"FC", -- 0x06B0 - x"3C",x"00",x"00",x"00",x"78",x"FC",x"FC",x"FC", -- 0x06B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0700 - x"7F",x"7F",x"7F",x"00",x"00",x"00",x"00",x"00", -- 0x0708 - x"7F",x"7F",x"7F",x"00",x"00",x"00",x"00",x"00", -- 0x0710 - x"F0",x"E0",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0718 - x"0F",x"07",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0720 - x"BF",x"BF",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0728 - x"1F",x"07",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0730 - x"F0",x"F0",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0738 - x"FB",x"7B",x"03",x"01",x"00",x"00",x"00",x"00", -- 0x0740 - x"F0",x"F8",x"FE",x"FF",x"FF",x"FF",x"3F",x"07", -- 0x0748 - x"03",x"07",x"1F",x"FF",x"FF",x"FF",x"FE",x"F0", -- 0x0750 - x"F0",x"F0",x"E0",x"E0",x"C0",x"80",x"00",x"00", -- 0x0758 - x"7F",x"1F",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0760 - x"F8",x"E0",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0768 - x"7E",x"7E",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0770 - x"07",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0778 - x"FC",x"FC",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0780 - x"07",x"07",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0788 - x"F3",x"F3",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0790 - x"F1",x"F1",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0798 - x"F8",x"F8",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07A0 - x"3F",x"0F",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07A8 - x"FC",x"FC",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07B0 - x"FC",x"78",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0800 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0808 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0810 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0818 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0820 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0828 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0830 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0838 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0840 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0848 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0850 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0858 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0860 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0868 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0870 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0878 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0880 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0888 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0890 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0898 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0900 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0908 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0910 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0918 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0920 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0928 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0930 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0938 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0940 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0948 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0950 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0958 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0960 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0968 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0970 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0978 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0980 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0988 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0990 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0998 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AD8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BD8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CD8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DD8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0ED0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0ED8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FD8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00" -- 0x0FF8 - ); - -begin - - p_rom : process - begin - wait until rising_edge(CLK); - DATA <= ROM(to_integer(unsigned(ADDR))); - end process; -end RTL; diff --git a/lib/VGA_ctrl/src/fonts/char_rom_demo_maker_m.vhd b/lib/VGA_ctrl/src/fonts/char_rom_demo_maker_m.vhd deleted file mode 100644 index ce977b6..0000000 --- a/lib/VGA_ctrl/src/fonts/char_rom_demo_maker_m.vhd +++ /dev/null @@ -1,539 +0,0 @@ -library ieee; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity char_rom is - port ( - CLK : in std_logic; - ADDR : in unsigned(11 downto 0); - DATA : out unsigned(7 downto 0) - ); -end; - -architecture RTL of char_rom is - - - type ROM_ARRAY is array(0 to 4095) of unsigned(7 downto 0); - constant ROM : ROM_ARRAY := ( - x"3C",x"66",x"6E",x"6A",x"6E",x"60",x"3C",x"00", -- 0x0000 - x"00",x"00",x"3C",x"06",x"3E",x"66",x"3E",x"00", -- 0x0008 - x"60",x"60",x"7C",x"66",x"66",x"66",x"7C",x"00", -- 0x0010 - x"00",x"00",x"3C",x"66",x"60",x"66",x"3C",x"00", -- 0x0018 - x"06",x"06",x"3E",x"66",x"66",x"66",x"3E",x"00", -- 0x0020 - x"00",x"00",x"3C",x"66",x"7E",x"60",x"3C",x"00", -- 0x0028 - x"1C",x"30",x"30",x"7C",x"30",x"30",x"30",x"00", -- 0x0030 - x"00",x"00",x"3E",x"66",x"66",x"3E",x"06",x"3C", -- 0x0038 - x"60",x"60",x"7C",x"66",x"66",x"66",x"66",x"00", -- 0x0040 - x"18",x"00",x"38",x"18",x"18",x"18",x"3C",x"00", -- 0x0048 - x"18",x"00",x"38",x"18",x"18",x"18",x"18",x"70", -- 0x0050 - x"60",x"60",x"66",x"6C",x"78",x"6C",x"66",x"00", -- 0x0058 - x"38",x"18",x"18",x"18",x"18",x"18",x"3C",x"00", -- 0x0060 - x"00",x"00",x"36",x"7F",x"6B",x"6B",x"63",x"00", -- 0x0068 - x"00",x"00",x"7C",x"66",x"66",x"66",x"66",x"00", -- 0x0070 - x"00",x"00",x"3C",x"66",x"66",x"66",x"3C",x"00", -- 0x0078 - x"00",x"00",x"7C",x"66",x"66",x"7C",x"60",x"60", -- 0x0080 - x"00",x"00",x"3E",x"66",x"66",x"3E",x"06",x"07", -- 0x0088 - x"00",x"00",x"6C",x"76",x"60",x"60",x"60",x"00", -- 0x0090 - x"00",x"00",x"3E",x"60",x"3C",x"06",x"7C",x"00", -- 0x0098 - x"30",x"30",x"7C",x"30",x"30",x"30",x"1C",x"00", -- 0x00A0 - x"00",x"00",x"66",x"66",x"66",x"66",x"3E",x"00", -- 0x00A8 - x"00",x"00",x"66",x"66",x"66",x"3C",x"18",x"00", -- 0x00B0 - x"00",x"00",x"63",x"6B",x"6B",x"7F",x"36",x"00", -- 0x00B8 - x"00",x"00",x"66",x"3C",x"18",x"3C",x"66",x"00", -- 0x00C0 - x"00",x"00",x"66",x"66",x"66",x"3E",x"06",x"3C", -- 0x00C8 - x"00",x"00",x"7E",x"0C",x"18",x"30",x"7E",x"00", -- 0x00D0 - x"7C",x"60",x"60",x"60",x"60",x"60",x"7C",x"00", -- 0x00D8 - x"1C",x"36",x"30",x"7C",x"30",x"30",x"7E",x"00", -- 0x00E0 - x"3E",x"06",x"06",x"06",x"06",x"06",x"3E",x"00", -- 0x00E8 - x"00",x"18",x"3C",x"7E",x"18",x"18",x"18",x"18", -- 0x00F0 - x"00",x"10",x"30",x"7F",x"7F",x"30",x"10",x"00", -- 0x00F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0100 - x"18",x"18",x"18",x"18",x"18",x"00",x"18",x"00", -- 0x0108 - x"6C",x"6C",x"6C",x"00",x"00",x"00",x"00",x"00", -- 0x0110 - x"36",x"36",x"7F",x"36",x"7F",x"36",x"36",x"00", -- 0x0118 - x"0C",x"3F",x"68",x"3E",x"0B",x"7E",x"18",x"00", -- 0x0120 - x"60",x"66",x"0C",x"18",x"30",x"66",x"06",x"00", -- 0x0128 - x"38",x"6C",x"6C",x"38",x"6D",x"66",x"3B",x"00", -- 0x0130 - x"0C",x"18",x"30",x"00",x"00",x"00",x"00",x"00", -- 0x0138 - x"0C",x"18",x"30",x"30",x"30",x"18",x"0C",x"00", -- 0x0140 - x"30",x"18",x"0C",x"0C",x"0C",x"18",x"30",x"00", -- 0x0148 - x"00",x"18",x"7E",x"3C",x"7E",x"18",x"00",x"00", -- 0x0150 - x"00",x"18",x"18",x"7E",x"18",x"18",x"00",x"00", -- 0x0158 - x"00",x"00",x"00",x"00",x"00",x"18",x"18",x"30", -- 0x0160 - x"00",x"00",x"00",x"7E",x"00",x"00",x"00",x"00", -- 0x0168 - x"00",x"00",x"00",x"00",x"00",x"18",x"18",x"00", -- 0x0170 - x"00",x"06",x"0C",x"18",x"30",x"60",x"00",x"00", -- 0x0178 - x"3C",x"66",x"6E",x"7E",x"76",x"66",x"3C",x"00", -- 0x0180 - x"18",x"38",x"18",x"18",x"18",x"18",x"7E",x"00", -- 0x0188 - x"3C",x"66",x"06",x"0C",x"18",x"30",x"7E",x"00", -- 0x0190 - x"3C",x"66",x"06",x"1C",x"06",x"66",x"3C",x"00", -- 0x0198 - x"0C",x"1C",x"3C",x"6C",x"7E",x"0C",x"0C",x"00", -- 0x01A0 - x"7E",x"60",x"7C",x"06",x"06",x"66",x"3C",x"00", -- 0x01A8 - x"1C",x"30",x"60",x"7C",x"66",x"66",x"3C",x"00", -- 0x01B0 - x"7E",x"06",x"0C",x"18",x"30",x"30",x"30",x"00", -- 0x01B8 - x"3C",x"66",x"66",x"3C",x"66",x"66",x"3C",x"00", -- 0x01C0 - x"3C",x"66",x"66",x"3E",x"06",x"0C",x"38",x"00", -- 0x01C8 - x"00",x"00",x"18",x"18",x"00",x"18",x"18",x"00", -- 0x01D0 - x"00",x"00",x"18",x"18",x"00",x"18",x"18",x"30", -- 0x01D8 - x"0C",x"18",x"30",x"60",x"30",x"18",x"0C",x"00", -- 0x01E0 - x"00",x"00",x"7E",x"00",x"7E",x"00",x"00",x"00", -- 0x01E8 - x"30",x"18",x"0C",x"06",x"0C",x"18",x"30",x"00", -- 0x01F0 - x"3C",x"66",x"0C",x"18",x"18",x"00",x"18",x"00", -- 0x01F8 - x"00",x"00",x"00",x"FF",x"FF",x"00",x"00",x"00", -- 0x0200 - x"3C",x"66",x"66",x"7E",x"66",x"66",x"66",x"00", -- 0x0208 - x"7C",x"66",x"66",x"7C",x"66",x"66",x"7C",x"00", -- 0x0210 - x"3C",x"66",x"60",x"60",x"60",x"66",x"3C",x"00", -- 0x0218 - x"78",x"6C",x"66",x"66",x"66",x"6C",x"78",x"00", -- 0x0220 - x"7E",x"60",x"60",x"7C",x"60",x"60",x"7E",x"00", -- 0x0228 - x"7E",x"60",x"60",x"7C",x"60",x"60",x"60",x"00", -- 0x0230 - x"3C",x"66",x"60",x"6E",x"66",x"66",x"3C",x"00", -- 0x0238 - x"66",x"66",x"66",x"7E",x"66",x"66",x"66",x"00", -- 0x0240 - x"7E",x"18",x"18",x"18",x"18",x"18",x"7E",x"00", -- 0x0248 - x"3E",x"0C",x"0C",x"0C",x"0C",x"6C",x"38",x"00", -- 0x0250 - x"66",x"6C",x"78",x"70",x"78",x"6C",x"66",x"00", -- 0x0258 - x"60",x"60",x"60",x"60",x"60",x"60",x"7E",x"00", -- 0x0260 - x"63",x"77",x"7F",x"6B",x"6B",x"63",x"63",x"00", -- 0x0268 - x"66",x"66",x"76",x"7E",x"6E",x"66",x"66",x"00", -- 0x0270 - x"3C",x"66",x"66",x"66",x"66",x"66",x"3C",x"00", -- 0x0278 - x"7C",x"66",x"66",x"7C",x"60",x"60",x"60",x"00", -- 0x0280 - x"3C",x"66",x"66",x"66",x"6A",x"6C",x"36",x"00", -- 0x0288 - x"7C",x"66",x"66",x"7C",x"6C",x"66",x"66",x"00", -- 0x0290 - x"3C",x"66",x"60",x"3C",x"06",x"66",x"3C",x"00", -- 0x0298 - x"7E",x"18",x"18",x"18",x"18",x"18",x"18",x"00", -- 0x02A0 - x"66",x"66",x"66",x"66",x"66",x"66",x"3C",x"00", -- 0x02A8 - x"66",x"66",x"66",x"66",x"66",x"3C",x"18",x"00", -- 0x02B0 - x"63",x"63",x"6B",x"00",x"00",x"00",x"00",x"00", -- 0x02B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0300 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0308 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0310 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0318 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0320 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0328 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0330 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0338 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0340 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0348 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0350 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0358 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0360 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0368 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0370 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0378 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0380 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0388 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0390 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0398 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0400 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0408 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0410 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0418 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0420 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0428 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0430 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0438 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0440 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0448 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0450 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0458 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0460 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0468 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0470 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0478 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0480 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0488 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0490 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0498 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0500 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0508 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0510 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0518 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0520 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0528 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0530 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0538 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0540 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0548 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0550 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0558 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0560 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0568 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0570 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0578 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0580 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0588 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0590 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0598 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0600 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0608 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0610 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0618 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0620 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0628 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0630 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0638 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0640 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0648 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0650 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0658 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0660 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0668 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0670 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0678 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0680 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0688 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0690 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0698 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0700 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0708 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0710 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0718 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0720 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0728 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0730 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0738 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0740 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0748 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0750 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0758 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0760 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0768 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0770 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0778 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0780 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0788 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0790 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0798 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0800 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0808 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0810 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0818 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0820 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0828 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0830 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0838 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0840 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0848 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0850 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0858 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0860 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0868 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0870 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0878 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0880 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0888 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0890 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0898 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0900 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0908 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0910 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0918 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0920 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0928 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0930 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0938 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0940 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0948 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0950 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0958 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0960 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0968 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0970 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0978 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0980 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0988 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0990 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0998 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AD8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BD8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CD8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DD8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0ED0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0ED8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FD8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00" -- 0x0FF8 - ); - -begin - - p_rom : process - begin - wait until rising_edge(CLK); - DATA <= ROM(to_integer(unsigned(ADDR))); - end process; -end RTL; diff --git a/lib/VGA_ctrl/src/fonts/char_rom_fixedsys_8x15.vhd b/lib/VGA_ctrl/src/fonts/char_rom_fixedsys_8x15.vhd deleted file mode 100644 index 3b60051..0000000 --- a/lib/VGA_ctrl/src/fonts/char_rom_fixedsys_8x15.vhd +++ /dev/null @@ -1,4383 +0,0 @@ -library ieee; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity char_rom is - port - ( - CLK : in std_logic; - ADDR : in unsigned(11 downto 0); - DATA : out unsigned(7 downto 0) - ); -end; - -architecture RTL of char_rom is - - - type ROM_ARRAY is array(0 to 4095) of unsigned(7 downto 0); - constant ROM : ROM_ARRAY := - ( - -- ASCII 032 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 033 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00011000", -- | ## | 03 - "00111100", -- | #### | 04 - "00111100", -- | #### | 05 - "00111100", -- | #### | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00000000", -- | | 09 - "00011000", -- | ## | 10 - "00011000", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 034 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100110", -- | ## ## | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 035 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00110110", -- | ## ## | 03 - "00110110", -- | ## ## | 04 - "01111111", -- | #######| 05 - "00110110", -- | ## ## | 06 - "00110110", -- | ## ## | 07 - "00110110", -- | ## ## | 08 - "01111111", -- | #######| 09 - "00110110", -- | ## ## | 10 - "00110110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 036 --------------- - "00000000", -- | | 00 - "00011000", -- | ## | 01 - "00011000", -- | ## | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100000", -- | ## | 05 - "00110000", -- | ## | 06 - "00011000", -- | ## | 07 - "00001100", -- | ## | 08 - "00000110", -- | ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00011000", -- | ## | 12 - "00011000", -- | ## | 13 - "00000000", -- | | 14 - -- ASCII 037 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "01110000", -- | ### | 02 - "11011000", -- |## ## | 03 - "11011010", -- |## ## # | 04 - "01110110", -- | ### ## | 05 - "00001100", -- | ## | 06 - "00011000", -- | ## | 07 - "00110000", -- | ## | 08 - "01101110", -- | ## ### | 09 - "01011011", -- | # ## ##| 10 - "00011011", -- | ## ##| 11 - "00001110", -- | ### | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 038 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "11111111", -- |########| 13 - "00000000", -- | | 14 - -- ASCII 039 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00011000", -- | ## | 03 - "00011000", -- | ## | 04 - "00011000", -- | ## | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 040 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00001100", -- | ## | 03 - "00011000", -- | ## | 04 - "00011000", -- | ## | 05 - "00110000", -- | ## | 06 - "00110000", -- | ## | 07 - "00110000", -- | ## | 08 - "00110000", -- | ## | 09 - "00110000", -- | ## | 10 - "00011000", -- | ## | 11 - "00011000", -- | ## | 12 - "00001100", -- | ## | 13 - "00000000", -- | | 14 - -- ASCII 041 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00110000", -- | ## | 03 - "00011000", -- | ## | 04 - "00011000", -- | ## | 05 - "00001100", -- | ## | 06 - "00001100", -- | ## | 07 - "00001100", -- | ## | 08 - "00001100", -- | ## | 09 - "00001100", -- | ## | 10 - "00011000", -- | ## | 11 - "00011000", -- | ## | 12 - "00110000", -- | ## | 13 - "00000000", -- | | 14 - -- ASCII 042 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00110110", -- | ## ## | 05 - "00011100", -- | ### | 06 - "01111111", -- | #######| 07 - "00011100", -- | ### | 08 - "00110110", -- | ## ## | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 043 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00011000", -- | ## | 05 - "00011000", -- | ## | 06 - "01111110", -- | ###### | 07 - "00011000", -- | ## | 08 - "00011000", -- | ## | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 044 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00011100", -- | ### | 10 - "00011100", -- | ### | 11 - "00001100", -- | ## | 12 - "00011000", -- | ## | 13 - "00000000", -- | | 14 - -- ASCII 045 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "01111110", -- | ###### | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 046 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00011100", -- | ### | 10 - "00011100", -- | ### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 047 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000110", -- | ## | 03 - "00000110", -- | ## | 04 - "00001100", -- | ## | 05 - "00001100", -- | ## | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00110000", -- | ## | 09 - "00110000", -- | ## | 10 - "01100000", -- | ## | 11 - "01100000", -- | ## | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 048 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00011110", -- | #### | 03 - "00110011", -- | ## ##| 04 - "00110111", -- | ## ###| 05 - "00110111", -- | ## ###| 06 - "00110011", -- | ## ##| 07 - "00111011", -- | ### ##| 08 - "00111011", -- | ### ##| 09 - "00110011", -- | ## ##| 10 - "00011110", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 049 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00001100", -- | ## | 03 - "00011100", -- | ### | 04 - "01111100", -- | ##### | 05 - "00001100", -- | ## | 06 - "00001100", -- | ## | 07 - "00001100", -- | ## | 08 - "00001100", -- | ## | 09 - "00001100", -- | ## | 10 - "00001100", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 050 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "00000110", -- | ## | 06 - "00001100", -- | ## | 07 - "00011000", -- | ## | 08 - "00110000", -- | ## | 09 - "01100000", -- | ## | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 051 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "00000110", -- | ## | 06 - "00011100", -- | ### | 07 - "00000110", -- | ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 052 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00110000", -- | ## | 03 - "00110000", -- | ## | 04 - "00110110", -- | ## ## | 05 - "00110110", -- | ## ## | 06 - "00110110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01111111", -- | #######| 09 - "00000110", -- | ## | 10 - "00000110", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 053 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01100000", -- | ## | 04 - "01100000", -- | ## | 05 - "01100000", -- | ## | 06 - "01111100", -- | ##### | 07 - "00000110", -- | ## | 08 - "00000110", -- | ## | 09 - "00001100", -- | ## | 10 - "01111000", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 054 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00011100", -- | ### | 03 - "00011000", -- | ## | 04 - "00110000", -- | ## | 05 - "01111100", -- | ##### | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 055 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "00000110", -- | ## | 04 - "00001100", -- | ## | 05 - "00001100", -- | ## | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00110000", -- | ## | 09 - "00110000", -- | ## | 10 - "00110000", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 056 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01110110", -- | ### ## | 06 - "00111100", -- | #### | 07 - "01101110", -- | ## ### | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 057 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "00111110", -- | ##### | 08 - "00001100", -- | ## | 09 - "00011000", -- | ## | 10 - "00111000", -- | ### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 058 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00011100", -- | ### | 05 - "00011100", -- | ### | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00011100", -- | ### | 10 - "00011100", -- | ### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 059 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00011100", -- | ### | 05 - "00011100", -- | ### | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00011100", -- | ### | 10 - "00011100", -- | ### | 11 - "00001100", -- | ## | 12 - "00011000", -- | ## | 13 - "00000000", -- | | 14 - -- ASCII 060 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000110", -- | ## | 03 - "00001100", -- | ## | 04 - "00011000", -- | ## | 05 - "00110000", -- | ## | 06 - "01100000", -- | ## | 07 - "00110000", -- | ## | 08 - "00011000", -- | ## | 09 - "00001100", -- | ## | 10 - "00000110", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 061 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "01111110", -- | ###### | 06 - "00000000", -- | | 07 - "01111110", -- | ###### | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 062 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100000", -- | ## | 03 - "00110000", -- | ## | 04 - "00011000", -- | ## | 05 - "00001100", -- | ## | 06 - "00000110", -- | ## | 07 - "00001100", -- | ## | 08 - "00011000", -- | ## | 09 - "00110000", -- | ## | 10 - "01100000", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 063 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "00001100", -- | ## | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00000000", -- | | 09 - "00011000", -- | ## | 10 - "00011000", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 064 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "11000011", -- |## ##| 04 - "11000011", -- |## ##| 05 - "11001111", -- |## ####| 06 - "11011011", -- |## ## ##| 07 - "11011011", -- |## ## ##| 08 - "11001111", -- |## ####| 09 - "11000000", -- |## | 10 - "01111111", -- | #######| 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 065 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00011000", -- | ## | 03 - "00111100", -- | #### | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01111110", -- | ###### | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01100110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 066 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111100", -- | ##### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01111100", -- | ##### | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01111100", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 067 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100000", -- | ## | 06 - "01100000", -- | ## | 07 - "01100000", -- | ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 068 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111000", -- | #### | 03 - "01101100", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01101100", -- | ## ## | 10 - "01111000", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 069 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01100000", -- | ## | 04 - "01100000", -- | ## | 05 - "01100000", -- | ## | 06 - "01111100", -- | ##### | 07 - "01100000", -- | ## | 08 - "01100000", -- | ## | 09 - "01100000", -- | ## | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 070 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01100000", -- | ## | 04 - "01100000", -- | ## | 05 - "01100000", -- | ## | 06 - "01111100", -- | ##### | 07 - "01100000", -- | ## | 08 - "01100000", -- | ## | 09 - "01100000", -- | ## | 10 - "01100000", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 071 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100000", -- | ## | 06 - "01100000", -- | ## | 07 - "01101110", -- | ## ### | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111110", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 072 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100110", -- | ## ## | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01111110", -- | ###### | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01100110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 073 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "00011000", -- | ## | 04 - "00011000", -- | ## | 05 - "00011000", -- | ## | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00011000", -- | ## | 09 - "00011000", -- | ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 074 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000110", -- | ## | 03 - "00000110", -- | ## | 04 - "00000110", -- | ## | 05 - "00000110", -- | ## | 06 - "00000110", -- | ## | 07 - "00000110", -- | ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 075 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100110", -- | ## ## | 03 - "01100110", -- | ## ## | 04 - "01101100", -- | ## ## | 05 - "01101100", -- | ## ## | 06 - "01111000", -- | #### | 07 - "01101100", -- | ## ## | 08 - "01101100", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01100110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 076 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100000", -- | ## | 03 - "01100000", -- | ## | 04 - "01100000", -- | ## | 05 - "01100000", -- | ## | 06 - "01100000", -- | ## | 07 - "01100000", -- | ## | 08 - "01100000", -- | ## | 09 - "01100000", -- | ## | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 077 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100011", -- | ## ##| 03 - "01100011", -- | ## ##| 04 - "01110111", -- | ### ###| 05 - "01101011", -- | ## # ##| 06 - "01101011", -- | ## # ##| 07 - "01101011", -- | ## # ##| 08 - "01100011", -- | ## ##| 09 - "01100011", -- | ## ##| 10 - "01100011", -- | ## ##| 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 078 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100011", -- | ## ##| 03 - "01100011", -- | ## ##| 04 - "01110011", -- | ### ##| 05 - "01111011", -- | #### ##| 06 - "01101111", -- | ## ####| 07 - "01100111", -- | ## ###| 08 - "01100011", -- | ## ##| 09 - "01100011", -- | ## ##| 10 - "01100011", -- | ## ##| 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 079 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 080 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111100", -- | ##### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01111100", -- | ##### | 07 - "01100000", -- | ## | 08 - "01100000", -- | ## | 09 - "01100000", -- | ## | 10 - "01100000", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 081 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00001100", -- | ## | 12 - "00000110", -- | ## | 13 - "00000000", -- | | 14 - -- ASCII 082 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111100", -- | ##### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01111100", -- | ##### | 07 - "01101100", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01100110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 083 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100000", -- | ## | 05 - "00110000", -- | ## | 06 - "00011000", -- | ## | 07 - "00001100", -- | ## | 08 - "00000110", -- | ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 084 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "00011000", -- | ## | 04 - "00011000", -- | ## | 05 - "00011000", -- | ## | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00011000", -- | ## | 09 - "00011000", -- | ## | 10 - "00011000", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 085 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100110", -- | ## ## | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 086 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100110", -- | ## ## | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "00111100", -- | #### | 10 - "00011000", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 087 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100011", -- | ## ##| 03 - "01100011", -- | ## ##| 04 - "01100011", -- | ## ##| 05 - "01101011", -- | ## # ##| 06 - "01101011", -- | ## # ##| 07 - "01101011", -- | ## # ##| 08 - "00110110", -- | ## ## | 09 - "00110110", -- | ## ## | 10 - "00110110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 088 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100110", -- | ## ## | 03 - "01100110", -- | ## ## | 04 - "00110100", -- | ## # | 05 - "00011000", -- | ## | 06 - "00011000", -- | ## | 07 - "00101100", -- | # ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01100110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 089 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100110", -- | ## ## | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "00111100", -- | #### | 07 - "00011000", -- | ## | 08 - "00011000", -- | ## | 09 - "00011000", -- | ## | 10 - "00011000", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 090 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "00000110", -- | ## | 04 - "00000110", -- | ## | 05 - "00001100", -- | ## | 06 - "00011000", -- | ## | 07 - "00110000", -- | ## | 08 - "01100000", -- | ## | 09 - "01100000", -- | ## | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 091 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "00110000", -- | ## | 04 - "00110000", -- | ## | 05 - "00110000", -- | ## | 06 - "00110000", -- | ## | 07 - "00110000", -- | ## | 08 - "00110000", -- | ## | 09 - "00110000", -- | ## | 10 - "00110000", -- | ## | 11 - "00110000", -- | ## | 12 - "00110000", -- | ## | 13 - "00111100", -- | #### | 14 - -- ASCII 092 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100000", -- | ## | 03 - "01100000", -- | ## | 04 - "00110000", -- | ## | 05 - "00110000", -- | ## | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00001100", -- | ## | 09 - "00001100", -- | ## | 10 - "00000110", -- | ## | 11 - "00000110", -- | ## | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 093 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "00001100", -- | ## | 04 - "00001100", -- | ## | 05 - "00001100", -- | ## | 06 - "00001100", -- | ## | 07 - "00001100", -- | ## | 08 - "00001100", -- | ## | 09 - "00001100", -- | ## | 10 - "00001100", -- | ## | 11 - "00001100", -- | ## | 12 - "00001100", -- | ## | 13 - "00111100", -- | #### | 14 - -- ASCII 094 --------------- - "00000000", -- | | 00 - "00011000", -- | ## | 01 - "00111100", -- | #### | 02 - "01100110", -- | ## ## | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 095 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "11111111", -- |########| 14 - -- ASCII 096 --------------- - "00000000", -- | | 00 - "00111000", -- | ### | 01 - "00011000", -- | ## | 02 - "00001100", -- | ## | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 097 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "00000110", -- | ## | 06 - "00000110", -- | ## | 07 - "00111110", -- | ##### | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111110", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 098 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100000", -- | ## | 03 - "01100000", -- | ## | 04 - "01111100", -- | ##### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01111100", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 099 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "01100110", -- | ## ## | 06 - "01100000", -- | ## | 07 - "01100000", -- | ## | 08 - "01100000", -- | ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 100 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000110", -- | ## | 03 - "00000110", -- | ## | 04 - "00111110", -- | ##### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111110", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 101 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01111110", -- | ###### | 08 - "01100000", -- | ## | 09 - "01100000", -- | ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 102 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00011110", -- | #### | 03 - "00110000", -- | ## | 04 - "00110000", -- | ## | 05 - "00110000", -- | ## | 06 - "01111110", -- | ###### | 07 - "00110000", -- | ## | 08 - "00110000", -- | ## | 09 - "00110000", -- | ## | 10 - "00110000", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 103 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00111110", -- | ##### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111110", -- | ##### | 11 - "00000110", -- | ## | 12 - "00000110", -- | ## | 13 - "01111100", -- | ##### | 14 - -- ASCII 104 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100000", -- | ## | 03 - "01100000", -- | ## | 04 - "01111100", -- | ##### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01100110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 105 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00011000", -- | ## | 02 - "00011000", -- | ## | 03 - "00000000", -- | | 04 - "01111000", -- | #### | 05 - "00011000", -- | ## | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00011000", -- | ## | 09 - "00011000", -- | ## | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 106 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00001100", -- | ## | 02 - "00001100", -- | ## | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "00001100", -- | ## | 06 - "00001100", -- | ## | 07 - "00001100", -- | ## | 08 - "00001100", -- | ## | 09 - "00001100", -- | ## | 10 - "00001100", -- | ## | 11 - "00001100", -- | ## | 12 - "00001100", -- | ## | 13 - "01111000", -- | #### | 14 - -- ASCII 107 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100000", -- | ## | 03 - "01100000", -- | ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01101100", -- | ## ## | 07 - "01111000", -- | #### | 08 - "01101100", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01100110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 108 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111000", -- | #### | 03 - "00011000", -- | ## | 04 - "00011000", -- | ## | 05 - "00011000", -- | ## | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00011000", -- | ## | 09 - "00011000", -- | ## | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 109 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "01111110", -- | ###### | 05 - "01101011", -- | ## # ##| 06 - "01101011", -- | ## # ##| 07 - "01101011", -- | ## # ##| 08 - "01101011", -- | ## # ##| 09 - "01101011", -- | ## # ##| 10 - "01100011", -- | ## ##| 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 110 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "01111100", -- | ##### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01100110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 111 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 112 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "01111100", -- | ##### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01111100", -- | ##### | 11 - "01100000", -- | ## | 12 - "01100000", -- | ## | 13 - "01100000", -- | ## | 14 - -- ASCII 113 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00111110", -- | ##### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111110", -- | ##### | 11 - "00000110", -- | ## | 12 - "00000110", -- | ## | 13 - "00000110", -- | ## | 14 - -- ASCII 114 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "01100110", -- | ## ## | 05 - "01101110", -- | ## ### | 06 - "01110000", -- | ### | 07 - "01100000", -- | ## | 08 - "01100000", -- | ## | 09 - "01100000", -- | ## | 10 - "01100000", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 115 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00111110", -- | ##### | 05 - "01100000", -- | ## | 06 - "01100000", -- | ## | 07 - "00111100", -- | #### | 08 - "00000110", -- | ## | 09 - "00000110", -- | ## | 10 - "01111100", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 116 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00110000", -- | ## | 03 - "00110000", -- | ## | 04 - "01111110", -- | ###### | 05 - "00110000", -- | ## | 06 - "00110000", -- | ## | 07 - "00110000", -- | ## | 08 - "00110000", -- | ## | 09 - "00110000", -- | ## | 10 - "00011110", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 117 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111110", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 118 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "00111100", -- | #### | 10 - "00011000", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 119 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "01100011", -- | ## ##| 05 - "01101011", -- | ## # ##| 06 - "01101011", -- | ## # ##| 07 - "01101011", -- | ## # ##| 08 - "01101011", -- | ## # ##| 09 - "00110110", -- | ## ## | 10 - "00110110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 120 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "00111100", -- | #### | 07 - "00011000", -- | ## | 08 - "00111100", -- | #### | 09 - "01100110", -- | ## ## | 10 - "01100110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 121 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00001100", -- | ## | 12 - "00011000", -- | ## | 13 - "11110000", -- |#### | 14 - -- ASCII 122 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "01111110", -- | ###### | 05 - "00000110", -- | ## | 06 - "00001100", -- | ## | 07 - "00011000", -- | ## | 08 - "00110000", -- | ## | 09 - "01100000", -- | ## | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 123 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00001100", -- | ## | 03 - "00011000", -- | ## | 04 - "00011000", -- | ## | 05 - "00011000", -- | ## | 06 - "00110000", -- | ## | 07 - "01100000", -- | ## | 08 - "00110000", -- | ## | 09 - "00011000", -- | ## | 10 - "00011000", -- | ## | 11 - "00011000", -- | ## | 12 - "00001100", -- | ## | 13 - "00000000", -- | | 14 - -- ASCII 124 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00011000", -- | ## | 03 - "00011000", -- | ## | 04 - "00011000", -- | ## | 05 - "00011000", -- | ## | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00011000", -- | ## | 09 - "00011000", -- | ## | 10 - "00011000", -- | ## | 11 - "00011000", -- | ## | 12 - "00011000", -- | ## | 13 - "00011000", -- | ## | 14 - -- ASCII 125 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00110000", -- | ## | 03 - "00011000", -- | ## | 04 - "00011000", -- | ## | 05 - "00011000", -- | ## | 06 - "00001100", -- | ## | 07 - "00000110", -- | ## | 08 - "00001100", -- | ## | 09 - "00011000", -- | ## | 10 - "00011000", -- | ## | 11 - "00011000", -- | ## | 12 - "00110000", -- | ## | 13 - "00000000", -- | | 14 - -- ASCII 126 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01110001", -- | ### #| 03 - "11011011", -- |## ## ##| 04 - "10001110", -- |# ### | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 127 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 128 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 129 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 130 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 131 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 132 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 133 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 134 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 135 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 136 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 137 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 138 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 139 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 140 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 141 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 142 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 143 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 144 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 145 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00001100", -- | ## | 03 - "00011000", -- | ## | 04 - "00011100", -- | ### | 05 - "00011100", -- | ### | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 146 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00011100", -- | ### | 03 - "00011100", -- | ### | 04 - "00001100", -- | ## | 05 - "00011000", -- | ## | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 147 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 148 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 149 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 150 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 151 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 152 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 153 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 154 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 155 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 156 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 157 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 158 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 159 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 160 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 161 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00011000", -- | ## | 06 - "00011000", -- | ## | 07 - "00000000", -- | | 08 - "00011000", -- | ## | 09 - "00011000", -- | ## | 10 - "00111100", -- | #### | 11 - "00111100", -- | #### | 12 - "00111100", -- | #### | 13 - "00011000", -- | ## | 14 - -- ASCII 162 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00011000", -- | ## | 03 - "00011000", -- | ## | 04 - "00111100", -- | #### | 05 - "01100110", -- | ## ## | 06 - "01100000", -- | ## | 07 - "01100000", -- | ## | 08 - "01100110", -- | ## ## | 09 - "00111100", -- | #### | 10 - "00011000", -- | ## | 11 - "00011000", -- | ## | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 163 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100000", -- | ## | 05 - "01100000", -- | ## | 06 - "11111100", -- |###### | 07 - "01100000", -- | ## | 08 - "01100000", -- | ## | 09 - "11000000", -- |## | 10 - "11111110", -- |####### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 164 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "01100110", -- | ## ## | 04 - "00111100", -- | #### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "00111100", -- | #### | 08 - "01100110", -- | ## ## | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 165 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100110", -- | ## ## | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "00111100", -- | #### | 06 - "01111110", -- | ###### | 07 - "00011000", -- | ## | 08 - "01111110", -- | ###### | 09 - "00011000", -- | ## | 10 - "00011000", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 166 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00011000", -- | ## | 03 - "00011000", -- | ## | 04 - "00011000", -- | ## | 05 - "00011000", -- | ## | 06 - "00011000", -- | ## | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00011000", -- | ## | 10 - "00011000", -- | ## | 11 - "00011000", -- | ## | 12 - "00011000", -- | ## | 13 - "00011000", -- | ## | 14 - -- ASCII 167 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100000", -- | ## | 05 - "00111000", -- | ### | 06 - "00111100", -- | #### | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "00111100", -- | #### | 10 - "00011100", -- | ### | 11 - "00000110", -- | ## | 12 - "01100110", -- | ## ## | 13 - "00111100", -- | #### | 14 - -- ASCII 168 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "01100110", -- | ## ## | 02 - "01100110", -- | ## ## | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 169 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "11000011", -- |## ##| 04 - "10011001", -- |# ## #| 05 - "10100101", -- |# # # #| 06 - "10100001", -- |# # #| 07 - "10100101", -- |# # # #| 08 - "10011001", -- |# ## #| 09 - "11000011", -- |## ##| 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 170 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "00000110", -- | ## | 04 - "00111110", -- | ##### | 05 - "01100110", -- | ## ## | 06 - "00111110", -- | ##### | 07 - "00000000", -- | | 08 - "01111110", -- | ###### | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 171 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00110011", -- | ## ##| 07 - "01100110", -- | ## ## | 08 - "11001100", -- |## ## | 09 - "01100110", -- | ## ## | 10 - "00110011", -- | ## ##| 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 172 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "01111110", -- | ###### | 07 - "00000110", -- | ## | 08 - "00000110", -- | ## | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 173 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "01111110", -- | ###### | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 174 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "11000011", -- |## ##| 04 - "10111001", -- |# ### #| 05 - "10100101", -- |# # # #| 06 - "10100101", -- |# # # #| 07 - "10111001", -- |# ### #| 08 - "10100101", -- |# # # #| 09 - "11000011", -- |## ##| 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 175 --------------- - "11111111", -- |########| 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 176 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00111100", -- | #### | 02 - "01100110", -- | ## ## | 03 - "01100110", -- | ## ## | 04 - "00111100", -- | #### | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 177 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00011000", -- | ## | 05 - "00011000", -- | ## | 06 - "01111110", -- | ###### | 07 - "00011000", -- | ## | 08 - "00011000", -- | ## | 09 - "00000000", -- | | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 178 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111000", -- | ### | 03 - "00001100", -- | ## | 04 - "00011000", -- | ## | 05 - "00110000", -- | ## | 06 - "00111100", -- | #### | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 179 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111000", -- | ### | 03 - "00001100", -- | ## | 04 - "00011000", -- | ## | 05 - "00001100", -- | ## | 06 - "00111000", -- | ### | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 180 --------------- - "00000000", -- | | 00 - "00011100", -- | ### | 01 - "00011000", -- | ## | 02 - "00110000", -- | ## | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 181 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01111011", -- | #### ##| 11 - "01100000", -- | ## | 12 - "01100000", -- | ## | 13 - "11000000", -- |## | 14 - -- ASCII 182 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00011111", -- | #####| 03 - "00111110", -- | ##### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "00111110", -- | ##### | 08 - "00011110", -- | #### | 09 - "00000110", -- | ## | 10 - "00000110", -- | ## | 11 - "00000110", -- | ## | 12 - "00000110", -- | ## | 13 - "00000110", -- | ## | 14 - -- ASCII 183 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00011100", -- | ### | 06 - "00011100", -- | ### | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 184 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00011000", -- | ## | 12 - "00001100", -- | ## | 13 - "00111000", -- | ### | 14 - -- ASCII 185 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00011000", -- | ## | 03 - "00111000", -- | ### | 04 - "00011000", -- | ## | 05 - "00011000", -- | ## | 06 - "00011000", -- | ## | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 186 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "00111100", -- | #### | 07 - "00000000", -- | | 08 - "01111110", -- | ###### | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 187 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "11001100", -- |## ## | 07 - "01100110", -- | ## ## | 08 - "00110011", -- | ## ##| 09 - "01100110", -- | ## ## | 10 - "11001100", -- |## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 188 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "01100000", -- | ## | 02 - "11100000", -- |### | 03 - "01100011", -- | ## ##| 04 - "01100110", -- | ## ## | 05 - "01101100", -- | ## ## | 06 - "00011000", -- | ## | 07 - "00110111", -- | ## ###| 08 - "01101111", -- | ## ####| 09 - "11011011", -- |## ## ##| 10 - "00011111", -- | #####| 11 - "00000011", -- | ##| 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 189 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "01100000", -- | ## | 02 - "11100000", -- |### | 03 - "01100011", -- | ## ##| 04 - "01100110", -- | ## ## | 05 - "01101100", -- | ## ## | 06 - "00011000", -- | ## | 07 - "00111110", -- | ##### | 08 - "01100011", -- | ## ##| 09 - "11000110", -- |## ## | 10 - "00001100", -- | ## | 11 - "00001111", -- | ####| 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 190 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "11100000", -- |### | 02 - "00110000", -- | ## | 03 - "01100011", -- | ## ##| 04 - "00110110", -- | ## ## | 05 - "11101100", -- |### ## | 06 - "00011000", -- | ## | 07 - "00110111", -- | ## ###| 08 - "01101111", -- | ## ####| 09 - "11011011", -- |## ## ##| 10 - "00011111", -- | #####| 11 - "00000011", -- | ##| 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 191 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00011000", -- | ## | 06 - "00011000", -- | ## | 07 - "00000000", -- | | 08 - "00011000", -- | ## | 09 - "00011000", -- | ## | 10 - "00110000", -- | ## | 11 - "01100110", -- | ## ## | 12 - "01100110", -- | ## ## | 13 - "00111100", -- | #### | 14 - -- ASCII 192 --------------- - "00110000", -- | ## | 00 - "00011000", -- | ## | 01 - "00000000", -- | | 02 - "00011000", -- | ## | 03 - "00111100", -- | #### | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01111110", -- | ###### | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01100110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 193 --------------- - "00001100", -- | ## | 00 - "00011000", -- | ## | 01 - "00000000", -- | | 02 - "00011000", -- | ## | 03 - "00111100", -- | #### | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01111110", -- | ###### | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01100110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 194 --------------- - "00111100", -- | #### | 00 - "01100110", -- | ## ## | 01 - "00000000", -- | | 02 - "00011000", -- | ## | 03 - "00111100", -- | #### | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01111110", -- | ###### | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01100110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 195 --------------- - "00111011", -- | ### ##| 00 - "01101110", -- | ## ### | 01 - "00000000", -- | | 02 - "00011000", -- | ## | 03 - "00111100", -- | #### | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01111110", -- | ###### | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01100110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 196 --------------- - "01100110", -- | ## ## | 00 - "01100110", -- | ## ## | 01 - "00000000", -- | | 02 - "00011000", -- | ## | 03 - "00111100", -- | #### | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01111110", -- | ###### | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01100110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 197 --------------- - "00111100", -- | #### | 00 - "01100110", -- | ## ## | 01 - "00111100", -- | #### | 02 - "00011000", -- | ## | 03 - "00111100", -- | #### | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01111110", -- | ###### | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01100110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 198 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00001111", -- | ####| 03 - "00011100", -- | ### | 04 - "00111100", -- | #### | 05 - "01101100", -- | ## ## | 06 - "01101111", -- | ## ####| 07 - "01111100", -- | ##### | 08 - "01101100", -- | ## ## | 09 - "01101100", -- | ## ## | 10 - "01101111", -- | ## ####| 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 199 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100000", -- | ## | 06 - "01100000", -- | ## | 07 - "01100000", -- | ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00011000", -- | ## | 12 - "00001100", -- | ## | 13 - "00111000", -- | ### | 14 - -- ASCII 200 --------------- - "00110000", -- | ## | 00 - "00011000", -- | ## | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01100000", -- | ## | 04 - "01100000", -- | ## | 05 - "01100000", -- | ## | 06 - "01111100", -- | ##### | 07 - "01100000", -- | ## | 08 - "01100000", -- | ## | 09 - "01100000", -- | ## | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 201 --------------- - "00001100", -- | ## | 00 - "00011000", -- | ## | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01100000", -- | ## | 04 - "01100000", -- | ## | 05 - "01100000", -- | ## | 06 - "01111100", -- | ##### | 07 - "01100000", -- | ## | 08 - "01100000", -- | ## | 09 - "01100000", -- | ## | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 202 --------------- - "00111100", -- | #### | 00 - "01100110", -- | ## ## | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01100000", -- | ## | 04 - "01100000", -- | ## | 05 - "01100000", -- | ## | 06 - "01111100", -- | ##### | 07 - "01100000", -- | ## | 08 - "01100000", -- | ## | 09 - "01100000", -- | ## | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 203 --------------- - "01100110", -- | ## ## | 00 - "01100110", -- | ## ## | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01100000", -- | ## | 04 - "01100000", -- | ## | 05 - "01100000", -- | ## | 06 - "01111100", -- | ##### | 07 - "01100000", -- | ## | 08 - "01100000", -- | ## | 09 - "01100000", -- | ## | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 204 --------------- - "00110000", -- | ## | 00 - "00011000", -- | ## | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "00011000", -- | ## | 04 - "00011000", -- | ## | 05 - "00011000", -- | ## | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00011000", -- | ## | 09 - "00011000", -- | ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 205 --------------- - "00001100", -- | ## | 00 - "00011000", -- | ## | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "00011000", -- | ## | 04 - "00011000", -- | ## | 05 - "00011000", -- | ## | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00011000", -- | ## | 09 - "00011000", -- | ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 206 --------------- - "00111100", -- | #### | 00 - "01100110", -- | ## ## | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "00011000", -- | ## | 04 - "00011000", -- | ## | 05 - "00011000", -- | ## | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00011000", -- | ## | 09 - "00011000", -- | ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 207 --------------- - "01100110", -- | ## ## | 00 - "01100110", -- | ## ## | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "00011000", -- | ## | 04 - "00011000", -- | ## | 05 - "00011000", -- | ## | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00011000", -- | ## | 09 - "00011000", -- | ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 208 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111000", -- | #### | 03 - "01101100", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "11110110", -- |#### ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01101100", -- | ## ## | 10 - "01111000", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 209 --------------- - "00111011", -- | ### ##| 00 - "01101110", -- | ## ### | 01 - "00000000", -- | | 02 - "01100011", -- | ## ##| 03 - "01100011", -- | ## ##| 04 - "01110011", -- | ### ##| 05 - "01111011", -- | #### ##| 06 - "01101111", -- | ## ####| 07 - "01100111", -- | ## ###| 08 - "01100011", -- | ## ##| 09 - "01100011", -- | ## ##| 10 - "01100011", -- | ## ##| 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 210 --------------- - "00110000", -- | ## | 00 - "00011000", -- | ## | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 211 --------------- - "00001100", -- | ## | 00 - "00011000", -- | ## | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 212 --------------- - "00111100", -- | #### | 00 - "01100110", -- | ## ## | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 213 --------------- - "00111011", -- | ### ##| 00 - "01101110", -- | ## ### | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 214 --------------- - "01100110", -- | ## ## | 00 - "01100110", -- | ## ## | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 215 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "01000010", -- | # # | 04 - "01100110", -- | ## ## | 05 - "00111100", -- | #### | 06 - "00011000", -- | ## | 07 - "00111100", -- | #### | 08 - "01100110", -- | ## ## | 09 - "01000010", -- | # # | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 216 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111110", -- | ##### | 03 - "01100110", -- | ## ## | 04 - "01101110", -- | ## ### | 05 - "01101110", -- | ## ### | 06 - "01111110", -- | ###### | 07 - "01110110", -- | ### ## | 08 - "01110110", -- | ### ## | 09 - "01100110", -- | ## ## | 10 - "01111100", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 217 --------------- - "00110000", -- | ## | 00 - "00011000", -- | ## | 01 - "00000000", -- | | 02 - "01100110", -- | ## ## | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 218 --------------- - "00001100", -- | ## | 00 - "00011000", -- | ## | 01 - "00000000", -- | | 02 - "01100110", -- | ## ## | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 219 --------------- - "00111100", -- | #### | 00 - "01100110", -- | ## ## | 01 - "00000000", -- | | 02 - "01100110", -- | ## ## | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 220 --------------- - "01100110", -- | ## ## | 00 - "01100110", -- | ## ## | 01 - "00000000", -- | | 02 - "01100110", -- | ## ## | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 221 --------------- - "00001100", -- | ## | 00 - "00011000", -- | ## | 01 - "00000000", -- | | 02 - "01100110", -- | ## ## | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "00111100", -- | #### | 07 - "00011000", -- | ## | 08 - "00011000", -- | ## | 09 - "00011000", -- | ## | 10 - "00011000", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 222 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100000", -- | ## | 03 - "01100000", -- | ## | 04 - "01111100", -- | ##### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01111100", -- | ##### | 09 - "01100000", -- | ## | 10 - "01100000", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 223 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111000", -- | ### | 03 - "01101100", -- | ## ## | 04 - "01101100", -- | ## ## | 05 - "01101100", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01101100", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 224 --------------- - "00000000", -- | | 00 - "01110000", -- | ### | 01 - "00110000", -- | ## | 02 - "00011000", -- | ## | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "00000110", -- | ## | 06 - "00000110", -- | ## | 07 - "00111110", -- | ##### | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111110", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 225 --------------- - "00000000", -- | | 00 - "00001110", -- | ### | 01 - "00001100", -- | ## | 02 - "00011000", -- | ## | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "00000110", -- | ## | 06 - "00000110", -- | ## | 07 - "00111110", -- | ##### | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111110", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 226 --------------- - "00000000", -- | | 00 - "00011000", -- | ## | 01 - "00111100", -- | #### | 02 - "01100110", -- | ## ## | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "00000110", -- | ## | 06 - "00000110", -- | ## | 07 - "00111110", -- | ##### | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111110", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 227 --------------- - "00000000", -- | | 00 - "01110001", -- | ### #| 01 - "11011011", -- |## ## ##| 02 - "10001110", -- |# ### | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "00000110", -- | ## | 06 - "00000110", -- | ## | 07 - "00111110", -- | ##### | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111110", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 228 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "01100110", -- | ## ## | 02 - "01100110", -- | ## ## | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "00000110", -- | ## | 06 - "00000110", -- | ## | 07 - "00111110", -- | ##### | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111110", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 229 --------------- - "00000000", -- | | 00 - "00111100", -- | #### | 01 - "01100110", -- | ## ## | 02 - "00111100", -- | #### | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "00000110", -- | ## | 06 - "00000110", -- | ## | 07 - "00111110", -- | ##### | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111110", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 230 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "01101110", -- | ## ### | 05 - "00011011", -- | ## ##| 06 - "00011011", -- | ## ##| 07 - "01111111", -- | #######| 08 - "11011000", -- |## ## | 09 - "11011000", -- |## ## | 10 - "01110111", -- | ### ###| 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 231 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "01100110", -- | ## ## | 06 - "01100000", -- | ## | 07 - "01100000", -- | ## | 08 - "01100000", -- | ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00011000", -- | ## | 12 - "00001100", -- | ## | 13 - "00111000", -- | ### | 14 - -- ASCII 232 --------------- - "00000000", -- | | 00 - "01110000", -- | ### | 01 - "00110000", -- | ## | 02 - "00011000", -- | ## | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01111110", -- | ###### | 08 - "01100000", -- | ## | 09 - "01100000", -- | ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 233 --------------- - "00000000", -- | | 00 - "00001110", -- | ### | 01 - "00001100", -- | ## | 02 - "00011000", -- | ## | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01111110", -- | ###### | 08 - "01100000", -- | ## | 09 - "01100000", -- | ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 234 --------------- - "00000000", -- | | 00 - "00011000", -- | ## | 01 - "00111100", -- | #### | 02 - "01100110", -- | ## ## | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01111110", -- | ###### | 08 - "01100000", -- | ## | 09 - "01100000", -- | ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 235 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "01100110", -- | ## ## | 02 - "01100110", -- | ## ## | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01111110", -- | ###### | 08 - "01100000", -- | ## | 09 - "01100000", -- | ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 236 --------------- - "00000000", -- | | 00 - "01110000", -- | ### | 01 - "00110000", -- | ## | 02 - "00011000", -- | ## | 03 - "00000000", -- | | 04 - "01111000", -- | #### | 05 - "00011000", -- | ## | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00011000", -- | ## | 09 - "00011000", -- | ## | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 237 --------------- - "00000000", -- | | 00 - "00001110", -- | ### | 01 - "00001100", -- | ## | 02 - "00011000", -- | ## | 03 - "00000000", -- | | 04 - "01111000", -- | #### | 05 - "00011000", -- | ## | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00011000", -- | ## | 09 - "00011000", -- | ## | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 238 --------------- - "00000000", -- | | 00 - "00011000", -- | ## | 01 - "00111100", -- | #### | 02 - "01100110", -- | ## ## | 03 - "00000000", -- | | 04 - "01111000", -- | #### | 05 - "00011000", -- | ## | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00011000", -- | ## | 09 - "00011000", -- | ## | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 239 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "01100110", -- | ## ## | 02 - "01100110", -- | ## ## | 03 - "00000000", -- | | 04 - "01111000", -- | #### | 05 - "00011000", -- | ## | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00011000", -- | ## | 09 - "00011000", -- | ## | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 240 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00110110", -- | ## ## | 03 - "00011000", -- | ## | 04 - "01101100", -- | ## ## | 05 - "00011110", -- | #### | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 241 --------------- - "00000000", -- | | 00 - "01110001", -- | ### #| 01 - "11011011", -- |## ## ##| 02 - "10001110", -- |# ### | 03 - "00000000", -- | | 04 - "01111100", -- | ##### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01100110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 242 --------------- - "00000000", -- | | 00 - "01110000", -- | ### | 01 - "00110000", -- | ## | 02 - "00011000", -- | ## | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 243 --------------- - "00000000", -- | | 00 - "00001110", -- | ### | 01 - "00001100", -- | ## | 02 - "00011000", -- | ## | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 244 --------------- - "00000000", -- | | 00 - "00011000", -- | ## | 01 - "00111100", -- | #### | 02 - "01100110", -- | ## ## | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 245 --------------- - "00000000", -- | | 00 - "01110001", -- | ### #| 01 - "11011011", -- |## ## ##| 02 - "10001110", -- |# ### | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 246 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "01100110", -- | ## ## | 02 - "01100110", -- | ## ## | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 247 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00011000", -- | ## | 04 - "00011000", -- | ## | 05 - "00000000", -- | | 06 - "01111110", -- | ###### | 07 - "00000000", -- | | 08 - "00011000", -- | ## | 09 - "00011000", -- | ## | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 248 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00111110", -- | ##### | 05 - "01100110", -- | ## ## | 06 - "01101110", -- | ## ### | 07 - "01111110", -- | ###### | 08 - "01110110", -- | ### ## | 09 - "01100110", -- | ## ## | 10 - "01111100", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 249 --------------- - "00000000", -- | | 00 - "01110000", -- | ### | 01 - "00110000", -- | ## | 02 - "00011000", -- | ## | 03 - "00000000", -- | | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111110", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 250 --------------- - "00000000", -- | | 00 - "00001110", -- | ### | 01 - "00001100", -- | ## | 02 - "00011000", -- | ## | 03 - "00000000", -- | | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111110", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 251 --------------- - "00000000", -- | | 00 - "00011000", -- | ## | 01 - "00111100", -- | #### | 02 - "01100110", -- | ## ## | 03 - "00000000", -- | | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111110", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 252 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "01100110", -- | ## ## | 02 - "01100110", -- | ## ## | 03 - "00000000", -- | | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111110", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 253 --------------- - "00000000", -- | | 00 - "00001110", -- | ### | 01 - "00001100", -- | ## | 02 - "00011000", -- | ## | 03 - "00000000", -- | | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00001100", -- | ## | 12 - "00011000", -- | ## | 13 - "11110000", -- |#### | 14 - -- ASCII 254 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100000", -- | ## | 03 - "01100000", -- | ## | 04 - "01100000", -- | ## | 05 - "01111100", -- | ##### | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01111100", -- | ##### | 11 - "01100000", -- | ## | 12 - "01100000", -- | ## | 13 - "01100000", -- | ## | 14 - -- ASCII 255 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "01100110", -- | ## ## | 02 - "01100110", -- | ## ## | 03 - "00000000", -- | | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00001100", -- | ## | 12 - "00011000", -- | ## | 13 - "11110000", -- |#### | 14 - -- ASCII 256 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 257 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 258 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 259 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 260 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 261 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 262 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 263 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 264 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 265 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 266 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 267 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 268 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 269 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 270 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 271 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 272 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 273 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 274 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 275 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 276 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 277 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 278 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 279 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 280 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 281 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 282 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 283 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 284 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 285 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 286 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 287 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- Padding --------------- - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000" -- Padded - ); -begin - - p_rom : process - begin - wait until rising_edge(CLK); - DATA <= ROM(to_integer(unsigned(ADDR))); - end process; - -end RTL; - diff --git a/lib/VGA_ctrl/src/fonts/char_rom_fixedsys_8x16.vhd b/lib/VGA_ctrl/src/fonts/char_rom_fixedsys_8x16.vhd deleted file mode 100644 index e46151c..0000000 --- a/lib/VGA_ctrl/src/fonts/char_rom_fixedsys_8x16.vhd +++ /dev/null @@ -1,4382 +0,0 @@ -library ieee; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity char_rom is - port - ( - CLK : in std_logic; - ADDR : in unsigned(11 downto 0); - DATA : out unsigned(7 downto 0) - ); -end; - -architecture RTL of char_rom is - - - type ROM_ARRAY is array(0 to 4095) of unsigned(7 downto 0); - constant ROM : ROM_ARRAY := - ( - -- ASCII 032 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 033 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00011000", -- | ## | 03 - "00111100", -- | #### | 04 - "00111100", -- | #### | 05 - "00111100", -- | #### | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00000000", -- | | 09 - "00011000", -- | ## | 10 - "00011000", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 034 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100110", -- | ## ## | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 035 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00110110", -- | ## ## | 03 - "00110110", -- | ## ## | 04 - "01111111", -- | #######| 05 - "00110110", -- | ## ## | 06 - "00110110", -- | ## ## | 07 - "00110110", -- | ## ## | 08 - "01111111", -- | #######| 09 - "00110110", -- | ## ## | 10 - "00110110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 036 --------------- - "00000000", -- | | 00 - "00011000", -- | ## | 01 - "00011000", -- | ## | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100000", -- | ## | 05 - "00110000", -- | ## | 06 - "00011000", -- | ## | 07 - "00001100", -- | ## | 08 - "00000110", -- | ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00011000", -- | ## | 12 - "00011000", -- | ## | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 037 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "01110000", -- | ### | 02 - "11011000", -- |## ## | 03 - "11011010", -- |## ## # | 04 - "01110110", -- | ### ## | 05 - "00001100", -- | ## | 06 - "00011000", -- | ## | 07 - "00110000", -- | ## | 08 - "01101110", -- | ## ### | 09 - "01011011", -- | # ## ##| 10 - "00011011", -- | ## ##| 11 - "00001110", -- | ### | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 038 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "11111111", -- |########| 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 039 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00011000", -- | ## | 03 - "00011000", -- | ## | 04 - "00011000", -- | ## | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 040 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00001100", -- | ## | 03 - "00011000", -- | ## | 04 - "00011000", -- | ## | 05 - "00110000", -- | ## | 06 - "00110000", -- | ## | 07 - "00110000", -- | ## | 08 - "00110000", -- | ## | 09 - "00110000", -- | ## | 10 - "00011000", -- | ## | 11 - "00011000", -- | ## | 12 - "00001100", -- | ## | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 041 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00110000", -- | ## | 03 - "00011000", -- | ## | 04 - "00011000", -- | ## | 05 - "00001100", -- | ## | 06 - "00001100", -- | ## | 07 - "00001100", -- | ## | 08 - "00001100", -- | ## | 09 - "00001100", -- | ## | 10 - "00011000", -- | ## | 11 - "00011000", -- | ## | 12 - "00110000", -- | ## | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 042 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00110110", -- | ## ## | 05 - "00011100", -- | ### | 06 - "01111111", -- | #######| 07 - "00011100", -- | ### | 08 - "00110110", -- | ## ## | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 043 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00011000", -- | ## | 05 - "00011000", -- | ## | 06 - "01111110", -- | ###### | 07 - "00011000", -- | ## | 08 - "00011000", -- | ## | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 044 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00011100", -- | ### | 10 - "00011100", -- | ### | 11 - "00001100", -- | ## | 12 - "00011000", -- | ## | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 045 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "01111110", -- | ###### | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 046 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00011100", -- | ### | 10 - "00011100", -- | ### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 047 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000110", -- | ## | 03 - "00000110", -- | ## | 04 - "00001100", -- | ## | 05 - "00001100", -- | ## | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00110000", -- | ## | 09 - "00110000", -- | ## | 10 - "01100000", -- | ## | 11 - "01100000", -- | ## | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 048 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00011110", -- | #### | 03 - "00110011", -- | ## ##| 04 - "00110111", -- | ## ###| 05 - "00110111", -- | ## ###| 06 - "00110011", -- | ## ##| 07 - "00111011", -- | ### ##| 08 - "00111011", -- | ### ##| 09 - "00110011", -- | ## ##| 10 - "00011110", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 049 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00001100", -- | ## | 03 - "00011100", -- | ### | 04 - "01111100", -- | ##### | 05 - "00001100", -- | ## | 06 - "00001100", -- | ## | 07 - "00001100", -- | ## | 08 - "00001100", -- | ## | 09 - "00001100", -- | ## | 10 - "00001100", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 050 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "00000110", -- | ## | 06 - "00001100", -- | ## | 07 - "00011000", -- | ## | 08 - "00110000", -- | ## | 09 - "01100000", -- | ## | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 051 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "00000110", -- | ## | 06 - "00011100", -- | ### | 07 - "00000110", -- | ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 052 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00110000", -- | ## | 03 - "00110000", -- | ## | 04 - "00110110", -- | ## ## | 05 - "00110110", -- | ## ## | 06 - "00110110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01111111", -- | #######| 09 - "00000110", -- | ## | 10 - "00000110", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 053 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01100000", -- | ## | 04 - "01100000", -- | ## | 05 - "01100000", -- | ## | 06 - "01111100", -- | ##### | 07 - "00000110", -- | ## | 08 - "00000110", -- | ## | 09 - "00001100", -- | ## | 10 - "01111000", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 054 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00011100", -- | ### | 03 - "00011000", -- | ## | 04 - "00110000", -- | ## | 05 - "01111100", -- | ##### | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 055 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "00000110", -- | ## | 04 - "00001100", -- | ## | 05 - "00001100", -- | ## | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00110000", -- | ## | 09 - "00110000", -- | ## | 10 - "00110000", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 056 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01110110", -- | ### ## | 06 - "00111100", -- | #### | 07 - "01101110", -- | ## ### | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 057 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "00111110", -- | ##### | 08 - "00001100", -- | ## | 09 - "00011000", -- | ## | 10 - "00111000", -- | ### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 058 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00011100", -- | ### | 05 - "00011100", -- | ### | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00011100", -- | ### | 10 - "00011100", -- | ### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 059 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00011100", -- | ### | 05 - "00011100", -- | ### | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00011100", -- | ### | 10 - "00011100", -- | ### | 11 - "00001100", -- | ## | 12 - "00011000", -- | ## | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 060 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000110", -- | ## | 03 - "00001100", -- | ## | 04 - "00011000", -- | ## | 05 - "00110000", -- | ## | 06 - "01100000", -- | ## | 07 - "00110000", -- | ## | 08 - "00011000", -- | ## | 09 - "00001100", -- | ## | 10 - "00000110", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 061 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "01111110", -- | ###### | 06 - "00000000", -- | | 07 - "01111110", -- | ###### | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 062 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100000", -- | ## | 03 - "00110000", -- | ## | 04 - "00011000", -- | ## | 05 - "00001100", -- | ## | 06 - "00000110", -- | ## | 07 - "00001100", -- | ## | 08 - "00011000", -- | ## | 09 - "00110000", -- | ## | 10 - "01100000", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 063 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "00001100", -- | ## | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00000000", -- | | 09 - "00011000", -- | ## | 10 - "00011000", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 064 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "11000011", -- |## ##| 04 - "11000011", -- |## ##| 05 - "11001111", -- |## ####| 06 - "11011011", -- |## ## ##| 07 - "11011011", -- |## ## ##| 08 - "11001111", -- |## ####| 09 - "11000000", -- |## | 10 - "01111111", -- | #######| 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 065 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00011000", -- | ## | 03 - "00111100", -- | #### | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01111110", -- | ###### | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01100110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 066 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111100", -- | ##### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01111100", -- | ##### | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01111100", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 067 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100000", -- | ## | 06 - "01100000", -- | ## | 07 - "01100000", -- | ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 068 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111000", -- | #### | 03 - "01101100", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01101100", -- | ## ## | 10 - "01111000", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 069 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01100000", -- | ## | 04 - "01100000", -- | ## | 05 - "01100000", -- | ## | 06 - "01111100", -- | ##### | 07 - "01100000", -- | ## | 08 - "01100000", -- | ## | 09 - "01100000", -- | ## | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 070 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01100000", -- | ## | 04 - "01100000", -- | ## | 05 - "01100000", -- | ## | 06 - "01111100", -- | ##### | 07 - "01100000", -- | ## | 08 - "01100000", -- | ## | 09 - "01100000", -- | ## | 10 - "01100000", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 071 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100000", -- | ## | 06 - "01100000", -- | ## | 07 - "01101110", -- | ## ### | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111110", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 072 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100110", -- | ## ## | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01111110", -- | ###### | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01100110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 073 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "00011000", -- | ## | 04 - "00011000", -- | ## | 05 - "00011000", -- | ## | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00011000", -- | ## | 09 - "00011000", -- | ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 074 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000110", -- | ## | 03 - "00000110", -- | ## | 04 - "00000110", -- | ## | 05 - "00000110", -- | ## | 06 - "00000110", -- | ## | 07 - "00000110", -- | ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 075 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100110", -- | ## ## | 03 - "01100110", -- | ## ## | 04 - "01101100", -- | ## ## | 05 - "01101100", -- | ## ## | 06 - "01111000", -- | #### | 07 - "01101100", -- | ## ## | 08 - "01101100", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01100110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 076 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100000", -- | ## | 03 - "01100000", -- | ## | 04 - "01100000", -- | ## | 05 - "01100000", -- | ## | 06 - "01100000", -- | ## | 07 - "01100000", -- | ## | 08 - "01100000", -- | ## | 09 - "01100000", -- | ## | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 077 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100011", -- | ## ##| 03 - "01100011", -- | ## ##| 04 - "01110111", -- | ### ###| 05 - "01101011", -- | ## # ##| 06 - "01101011", -- | ## # ##| 07 - "01101011", -- | ## # ##| 08 - "01100011", -- | ## ##| 09 - "01100011", -- | ## ##| 10 - "01100011", -- | ## ##| 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 078 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100011", -- | ## ##| 03 - "01100011", -- | ## ##| 04 - "01110011", -- | ### ##| 05 - "01111011", -- | #### ##| 06 - "01101111", -- | ## ####| 07 - "01100111", -- | ## ###| 08 - "01100011", -- | ## ##| 09 - "01100011", -- | ## ##| 10 - "01100011", -- | ## ##| 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 079 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 080 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111100", -- | ##### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01111100", -- | ##### | 07 - "01100000", -- | ## | 08 - "01100000", -- | ## | 09 - "01100000", -- | ## | 10 - "01100000", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 081 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00001100", -- | ## | 12 - "00000110", -- | ## | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 082 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111100", -- | ##### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01111100", -- | ##### | 07 - "01101100", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01100110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 083 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100000", -- | ## | 05 - "00110000", -- | ## | 06 - "00011000", -- | ## | 07 - "00001100", -- | ## | 08 - "00000110", -- | ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 084 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "00011000", -- | ## | 04 - "00011000", -- | ## | 05 - "00011000", -- | ## | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00011000", -- | ## | 09 - "00011000", -- | ## | 10 - "00011000", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 085 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100110", -- | ## ## | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 086 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100110", -- | ## ## | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "00111100", -- | #### | 10 - "00011000", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 087 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100011", -- | ## ##| 03 - "01100011", -- | ## ##| 04 - "01100011", -- | ## ##| 05 - "01101011", -- | ## # ##| 06 - "01101011", -- | ## # ##| 07 - "01101011", -- | ## # ##| 08 - "00110110", -- | ## ## | 09 - "00110110", -- | ## ## | 10 - "00110110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 088 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100110", -- | ## ## | 03 - "01100110", -- | ## ## | 04 - "00110100", -- | ## # | 05 - "00011000", -- | ## | 06 - "00011000", -- | ## | 07 - "00101100", -- | # ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01100110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 089 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100110", -- | ## ## | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "00111100", -- | #### | 07 - "00011000", -- | ## | 08 - "00011000", -- | ## | 09 - "00011000", -- | ## | 10 - "00011000", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 090 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "00000110", -- | ## | 04 - "00000110", -- | ## | 05 - "00001100", -- | ## | 06 - "00011000", -- | ## | 07 - "00110000", -- | ## | 08 - "01100000", -- | ## | 09 - "01100000", -- | ## | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 091 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "00110000", -- | ## | 04 - "00110000", -- | ## | 05 - "00110000", -- | ## | 06 - "00110000", -- | ## | 07 - "00110000", -- | ## | 08 - "00110000", -- | ## | 09 - "00110000", -- | ## | 10 - "00110000", -- | ## | 11 - "00110000", -- | ## | 12 - "00110000", -- | ## | 13 - "00111100", -- | #### | 14 - "00000000", -- | | 15 - -- ASCII 092 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100000", -- | ## | 03 - "01100000", -- | ## | 04 - "00110000", -- | ## | 05 - "00110000", -- | ## | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00001100", -- | ## | 09 - "00001100", -- | ## | 10 - "00000110", -- | ## | 11 - "00000110", -- | ## | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 093 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "00001100", -- | ## | 04 - "00001100", -- | ## | 05 - "00001100", -- | ## | 06 - "00001100", -- | ## | 07 - "00001100", -- | ## | 08 - "00001100", -- | ## | 09 - "00001100", -- | ## | 10 - "00001100", -- | ## | 11 - "00001100", -- | ## | 12 - "00001100", -- | ## | 13 - "00111100", -- | #### | 14 - "00000000", -- | | 15 - -- ASCII 094 --------------- - "00000000", -- | | 00 - "00011000", -- | ## | 01 - "00111100", -- | #### | 02 - "01100110", -- | ## ## | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 095 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "11111111", -- |########| 14 - "00000000", -- | | 15 - -- ASCII 096 --------------- - "00000000", -- | | 00 - "00111000", -- | ### | 01 - "00011000", -- | ## | 02 - "00001100", -- | ## | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 097 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "00000110", -- | ## | 06 - "00000110", -- | ## | 07 - "00111110", -- | ##### | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111110", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 098 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100000", -- | ## | 03 - "01100000", -- | ## | 04 - "01111100", -- | ##### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01111100", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 099 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "01100110", -- | ## ## | 06 - "01100000", -- | ## | 07 - "01100000", -- | ## | 08 - "01100000", -- | ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 100 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000110", -- | ## | 03 - "00000110", -- | ## | 04 - "00111110", -- | ##### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111110", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 101 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01111110", -- | ###### | 08 - "01100000", -- | ## | 09 - "01100000", -- | ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 102 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00011110", -- | #### | 03 - "00110000", -- | ## | 04 - "00110000", -- | ## | 05 - "00110000", -- | ## | 06 - "01111110", -- | ###### | 07 - "00110000", -- | ## | 08 - "00110000", -- | ## | 09 - "00110000", -- | ## | 10 - "00110000", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 103 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00111110", -- | ##### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111110", -- | ##### | 11 - "00000110", -- | ## | 12 - "00000110", -- | ## | 13 - "01111100", -- | ##### | 14 - "00000000", -- | | 15 - -- ASCII 104 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100000", -- | ## | 03 - "01100000", -- | ## | 04 - "01111100", -- | ##### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01100110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 105 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00011000", -- | ## | 02 - "00011000", -- | ## | 03 - "00000000", -- | | 04 - "01111000", -- | #### | 05 - "00011000", -- | ## | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00011000", -- | ## | 09 - "00011000", -- | ## | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 106 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00001100", -- | ## | 02 - "00001100", -- | ## | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "00001100", -- | ## | 06 - "00001100", -- | ## | 07 - "00001100", -- | ## | 08 - "00001100", -- | ## | 09 - "00001100", -- | ## | 10 - "00001100", -- | ## | 11 - "00001100", -- | ## | 12 - "00001100", -- | ## | 13 - "01111000", -- | #### | 14 - "00000000", -- | | 15 - -- ASCII 107 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100000", -- | ## | 03 - "01100000", -- | ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01101100", -- | ## ## | 07 - "01111000", -- | #### | 08 - "01101100", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01100110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 108 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111000", -- | #### | 03 - "00011000", -- | ## | 04 - "00011000", -- | ## | 05 - "00011000", -- | ## | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00011000", -- | ## | 09 - "00011000", -- | ## | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 109 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "01111110", -- | ###### | 05 - "01101011", -- | ## # ##| 06 - "01101011", -- | ## # ##| 07 - "01101011", -- | ## # ##| 08 - "01101011", -- | ## # ##| 09 - "01101011", -- | ## # ##| 10 - "01100011", -- | ## ##| 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 110 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "01111100", -- | ##### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01100110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 111 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 112 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "01111100", -- | ##### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01111100", -- | ##### | 11 - "01100000", -- | ## | 12 - "01100000", -- | ## | 13 - "01100000", -- | ## | 14 - "00000000", -- | | 15 - -- ASCII 113 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00111110", -- | ##### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111110", -- | ##### | 11 - "00000110", -- | ## | 12 - "00000110", -- | ## | 13 - "00000110", -- | ## | 14 - "00000000", -- | | 15 - -- ASCII 114 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "01100110", -- | ## ## | 05 - "01101110", -- | ## ### | 06 - "01110000", -- | ### | 07 - "01100000", -- | ## | 08 - "01100000", -- | ## | 09 - "01100000", -- | ## | 10 - "01100000", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 115 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00111110", -- | ##### | 05 - "01100000", -- | ## | 06 - "01100000", -- | ## | 07 - "00111100", -- | #### | 08 - "00000110", -- | ## | 09 - "00000110", -- | ## | 10 - "01111100", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 116 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00110000", -- | ## | 03 - "00110000", -- | ## | 04 - "01111110", -- | ###### | 05 - "00110000", -- | ## | 06 - "00110000", -- | ## | 07 - "00110000", -- | ## | 08 - "00110000", -- | ## | 09 - "00110000", -- | ## | 10 - "00011110", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 117 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111110", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 118 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "00111100", -- | #### | 10 - "00011000", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 119 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "01100011", -- | ## ##| 05 - "01101011", -- | ## # ##| 06 - "01101011", -- | ## # ##| 07 - "01101011", -- | ## # ##| 08 - "01101011", -- | ## # ##| 09 - "00110110", -- | ## ## | 10 - "00110110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 120 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "00111100", -- | #### | 07 - "00011000", -- | ## | 08 - "00111100", -- | #### | 09 - "01100110", -- | ## ## | 10 - "01100110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 121 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00001100", -- | ## | 12 - "00011000", -- | ## | 13 - "11110000", -- |#### | 14 - "00000000", -- | | 15 - -- ASCII 122 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "01111110", -- | ###### | 05 - "00000110", -- | ## | 06 - "00001100", -- | ## | 07 - "00011000", -- | ## | 08 - "00110000", -- | ## | 09 - "01100000", -- | ## | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 123 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00001100", -- | ## | 03 - "00011000", -- | ## | 04 - "00011000", -- | ## | 05 - "00011000", -- | ## | 06 - "00110000", -- | ## | 07 - "01100000", -- | ## | 08 - "00110000", -- | ## | 09 - "00011000", -- | ## | 10 - "00011000", -- | ## | 11 - "00011000", -- | ## | 12 - "00001100", -- | ## | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 124 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00011000", -- | ## | 03 - "00011000", -- | ## | 04 - "00011000", -- | ## | 05 - "00011000", -- | ## | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00011000", -- | ## | 09 - "00011000", -- | ## | 10 - "00011000", -- | ## | 11 - "00011000", -- | ## | 12 - "00011000", -- | ## | 13 - "00011000", -- | ## | 14 - "00000000", -- | | 15 - -- ASCII 125 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00110000", -- | ## | 03 - "00011000", -- | ## | 04 - "00011000", -- | ## | 05 - "00011000", -- | ## | 06 - "00001100", -- | ## | 07 - "00000110", -- | ## | 08 - "00001100", -- | ## | 09 - "00011000", -- | ## | 10 - "00011000", -- | ## | 11 - "00011000", -- | ## | 12 - "00110000", -- | ## | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 126 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01110001", -- | ### #| 03 - "11011011", -- |## ## ##| 04 - "10001110", -- |# ### | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 127 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 128 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 129 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 130 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 131 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 132 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 133 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 134 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 135 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 136 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 137 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 138 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 139 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 140 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 141 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 142 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 143 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 144 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 145 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00001100", -- | ## | 03 - "00011000", -- | ## | 04 - "00011100", -- | ### | 05 - "00011100", -- | ### | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 146 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00011100", -- | ### | 03 - "00011100", -- | ### | 04 - "00001100", -- | ## | 05 - "00011000", -- | ## | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 147 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 148 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 149 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 150 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 151 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 152 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 153 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 154 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 155 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 156 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 157 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 158 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 159 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 160 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 161 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00011000", -- | ## | 06 - "00011000", -- | ## | 07 - "00000000", -- | | 08 - "00011000", -- | ## | 09 - "00011000", -- | ## | 10 - "00111100", -- | #### | 11 - "00111100", -- | #### | 12 - "00111100", -- | #### | 13 - "00011000", -- | ## | 14 - "00000000", -- | | 15 - -- ASCII 162 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00011000", -- | ## | 03 - "00011000", -- | ## | 04 - "00111100", -- | #### | 05 - "01100110", -- | ## ## | 06 - "01100000", -- | ## | 07 - "01100000", -- | ## | 08 - "01100110", -- | ## ## | 09 - "00111100", -- | #### | 10 - "00011000", -- | ## | 11 - "00011000", -- | ## | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 163 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100000", -- | ## | 05 - "01100000", -- | ## | 06 - "11111100", -- |###### | 07 - "01100000", -- | ## | 08 - "01100000", -- | ## | 09 - "11000000", -- |## | 10 - "11111110", -- |####### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 164 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "01100110", -- | ## ## | 04 - "00111100", -- | #### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "00111100", -- | #### | 08 - "01100110", -- | ## ## | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 165 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100110", -- | ## ## | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "00111100", -- | #### | 06 - "01111110", -- | ###### | 07 - "00011000", -- | ## | 08 - "01111110", -- | ###### | 09 - "00011000", -- | ## | 10 - "00011000", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 166 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00011000", -- | ## | 03 - "00011000", -- | ## | 04 - "00011000", -- | ## | 05 - "00011000", -- | ## | 06 - "00011000", -- | ## | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00011000", -- | ## | 10 - "00011000", -- | ## | 11 - "00011000", -- | ## | 12 - "00011000", -- | ## | 13 - "00011000", -- | ## | 14 - "00000000", -- | | 15 - -- ASCII 167 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100000", -- | ## | 05 - "00111000", -- | ### | 06 - "00111100", -- | #### | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "00111100", -- | #### | 10 - "00011100", -- | ### | 11 - "00000110", -- | ## | 12 - "01100110", -- | ## ## | 13 - "00111100", -- | #### | 14 - "00000000", -- | | 15 - -- ASCII 168 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "01100110", -- | ## ## | 02 - "01100110", -- | ## ## | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 169 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "11000011", -- |## ##| 04 - "10011001", -- |# ## #| 05 - "10100101", -- |# # # #| 06 - "10100001", -- |# # #| 07 - "10100101", -- |# # # #| 08 - "10011001", -- |# ## #| 09 - "11000011", -- |## ##| 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 170 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "00000110", -- | ## | 04 - "00111110", -- | ##### | 05 - "01100110", -- | ## ## | 06 - "00111110", -- | ##### | 07 - "00000000", -- | | 08 - "01111110", -- | ###### | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 171 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00110011", -- | ## ##| 07 - "01100110", -- | ## ## | 08 - "11001100", -- |## ## | 09 - "01100110", -- | ## ## | 10 - "00110011", -- | ## ##| 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 172 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "01111110", -- | ###### | 07 - "00000110", -- | ## | 08 - "00000110", -- | ## | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 173 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "01111110", -- | ###### | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 174 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "11000011", -- |## ##| 04 - "10111001", -- |# ### #| 05 - "10100101", -- |# # # #| 06 - "10100101", -- |# # # #| 07 - "10111001", -- |# ### #| 08 - "10100101", -- |# # # #| 09 - "11000011", -- |## ##| 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 175 --------------- - "11111111", -- |########| 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 176 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00111100", -- | #### | 02 - "01100110", -- | ## ## | 03 - "01100110", -- | ## ## | 04 - "00111100", -- | #### | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 177 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00011000", -- | ## | 05 - "00011000", -- | ## | 06 - "01111110", -- | ###### | 07 - "00011000", -- | ## | 08 - "00011000", -- | ## | 09 - "00000000", -- | | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 178 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111000", -- | ### | 03 - "00001100", -- | ## | 04 - "00011000", -- | ## | 05 - "00110000", -- | ## | 06 - "00111100", -- | #### | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 179 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111000", -- | ### | 03 - "00001100", -- | ## | 04 - "00011000", -- | ## | 05 - "00001100", -- | ## | 06 - "00111000", -- | ### | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 180 --------------- - "00000000", -- | | 00 - "00011100", -- | ### | 01 - "00011000", -- | ## | 02 - "00110000", -- | ## | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 181 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01111011", -- | #### ##| 11 - "01100000", -- | ## | 12 - "01100000", -- | ## | 13 - "11000000", -- |## | 14 - "00000000", -- | | 15 - -- ASCII 182 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00011111", -- | #####| 03 - "00111110", -- | ##### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "00111110", -- | ##### | 08 - "00011110", -- | #### | 09 - "00000110", -- | ## | 10 - "00000110", -- | ## | 11 - "00000110", -- | ## | 12 - "00000110", -- | ## | 13 - "00000110", -- | ## | 14 - "00000000", -- | | 15 - -- ASCII 183 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00011100", -- | ### | 06 - "00011100", -- | ### | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 184 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00011000", -- | ## | 12 - "00001100", -- | ## | 13 - "00111000", -- | ### | 14 - "00000000", -- | | 15 - -- ASCII 185 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00011000", -- | ## | 03 - "00111000", -- | ### | 04 - "00011000", -- | ## | 05 - "00011000", -- | ## | 06 - "00011000", -- | ## | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 186 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "00111100", -- | #### | 07 - "00000000", -- | | 08 - "01111110", -- | ###### | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 187 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "11001100", -- |## ## | 07 - "01100110", -- | ## ## | 08 - "00110011", -- | ## ##| 09 - "01100110", -- | ## ## | 10 - "11001100", -- |## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 188 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "01100000", -- | ## | 02 - "11100000", -- |### | 03 - "01100011", -- | ## ##| 04 - "01100110", -- | ## ## | 05 - "01101100", -- | ## ## | 06 - "00011000", -- | ## | 07 - "00110111", -- | ## ###| 08 - "01101111", -- | ## ####| 09 - "11011011", -- |## ## ##| 10 - "00011111", -- | #####| 11 - "00000011", -- | ##| 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 189 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "01100000", -- | ## | 02 - "11100000", -- |### | 03 - "01100011", -- | ## ##| 04 - "01100110", -- | ## ## | 05 - "01101100", -- | ## ## | 06 - "00011000", -- | ## | 07 - "00111110", -- | ##### | 08 - "01100011", -- | ## ##| 09 - "11000110", -- |## ## | 10 - "00001100", -- | ## | 11 - "00001111", -- | ####| 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 190 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "11100000", -- |### | 02 - "00110000", -- | ## | 03 - "01100011", -- | ## ##| 04 - "00110110", -- | ## ## | 05 - "11101100", -- |### ## | 06 - "00011000", -- | ## | 07 - "00110111", -- | ## ###| 08 - "01101111", -- | ## ####| 09 - "11011011", -- |## ## ##| 10 - "00011111", -- | #####| 11 - "00000011", -- | ##| 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 191 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00011000", -- | ## | 06 - "00011000", -- | ## | 07 - "00000000", -- | | 08 - "00011000", -- | ## | 09 - "00011000", -- | ## | 10 - "00110000", -- | ## | 11 - "01100110", -- | ## ## | 12 - "01100110", -- | ## ## | 13 - "00111100", -- | #### | 14 - "00000000", -- | | 15 - -- ASCII 192 --------------- - "00110000", -- | ## | 00 - "00011000", -- | ## | 01 - "00000000", -- | | 02 - "00011000", -- | ## | 03 - "00111100", -- | #### | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01111110", -- | ###### | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01100110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 193 --------------- - "00001100", -- | ## | 00 - "00011000", -- | ## | 01 - "00000000", -- | | 02 - "00011000", -- | ## | 03 - "00111100", -- | #### | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01111110", -- | ###### | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01100110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 194 --------------- - "00111100", -- | #### | 00 - "01100110", -- | ## ## | 01 - "00000000", -- | | 02 - "00011000", -- | ## | 03 - "00111100", -- | #### | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01111110", -- | ###### | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01100110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 195 --------------- - "00111011", -- | ### ##| 00 - "01101110", -- | ## ### | 01 - "00000000", -- | | 02 - "00011000", -- | ## | 03 - "00111100", -- | #### | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01111110", -- | ###### | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01100110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 196 --------------- - "01100110", -- | ## ## | 00 - "01100110", -- | ## ## | 01 - "00000000", -- | | 02 - "00011000", -- | ## | 03 - "00111100", -- | #### | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01111110", -- | ###### | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01100110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 197 --------------- - "00111100", -- | #### | 00 - "01100110", -- | ## ## | 01 - "00111100", -- | #### | 02 - "00011000", -- | ## | 03 - "00111100", -- | #### | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01111110", -- | ###### | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01100110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 198 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00001111", -- | ####| 03 - "00011100", -- | ### | 04 - "00111100", -- | #### | 05 - "01101100", -- | ## ## | 06 - "01101111", -- | ## ####| 07 - "01111100", -- | ##### | 08 - "01101100", -- | ## ## | 09 - "01101100", -- | ## ## | 10 - "01101111", -- | ## ####| 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 199 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100000", -- | ## | 06 - "01100000", -- | ## | 07 - "01100000", -- | ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00011000", -- | ## | 12 - "00001100", -- | ## | 13 - "00111000", -- | ### | 14 - "00000000", -- | | 15 - -- ASCII 200 --------------- - "00110000", -- | ## | 00 - "00011000", -- | ## | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01100000", -- | ## | 04 - "01100000", -- | ## | 05 - "01100000", -- | ## | 06 - "01111100", -- | ##### | 07 - "01100000", -- | ## | 08 - "01100000", -- | ## | 09 - "01100000", -- | ## | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 201 --------------- - "00001100", -- | ## | 00 - "00011000", -- | ## | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01100000", -- | ## | 04 - "01100000", -- | ## | 05 - "01100000", -- | ## | 06 - "01111100", -- | ##### | 07 - "01100000", -- | ## | 08 - "01100000", -- | ## | 09 - "01100000", -- | ## | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 202 --------------- - "00111100", -- | #### | 00 - "01100110", -- | ## ## | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01100000", -- | ## | 04 - "01100000", -- | ## | 05 - "01100000", -- | ## | 06 - "01111100", -- | ##### | 07 - "01100000", -- | ## | 08 - "01100000", -- | ## | 09 - "01100000", -- | ## | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 203 --------------- - "01100110", -- | ## ## | 00 - "01100110", -- | ## ## | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01100000", -- | ## | 04 - "01100000", -- | ## | 05 - "01100000", -- | ## | 06 - "01111100", -- | ##### | 07 - "01100000", -- | ## | 08 - "01100000", -- | ## | 09 - "01100000", -- | ## | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 204 --------------- - "00110000", -- | ## | 00 - "00011000", -- | ## | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "00011000", -- | ## | 04 - "00011000", -- | ## | 05 - "00011000", -- | ## | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00011000", -- | ## | 09 - "00011000", -- | ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 205 --------------- - "00001100", -- | ## | 00 - "00011000", -- | ## | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "00011000", -- | ## | 04 - "00011000", -- | ## | 05 - "00011000", -- | ## | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00011000", -- | ## | 09 - "00011000", -- | ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 206 --------------- - "00111100", -- | #### | 00 - "01100110", -- | ## ## | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "00011000", -- | ## | 04 - "00011000", -- | ## | 05 - "00011000", -- | ## | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00011000", -- | ## | 09 - "00011000", -- | ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 207 --------------- - "01100110", -- | ## ## | 00 - "01100110", -- | ## ## | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "00011000", -- | ## | 04 - "00011000", -- | ## | 05 - "00011000", -- | ## | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00011000", -- | ## | 09 - "00011000", -- | ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 208 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111000", -- | #### | 03 - "01101100", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "11110110", -- |#### ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01101100", -- | ## ## | 10 - "01111000", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 209 --------------- - "00111011", -- | ### ##| 00 - "01101110", -- | ## ### | 01 - "00000000", -- | | 02 - "01100011", -- | ## ##| 03 - "01100011", -- | ## ##| 04 - "01110011", -- | ### ##| 05 - "01111011", -- | #### ##| 06 - "01101111", -- | ## ####| 07 - "01100111", -- | ## ###| 08 - "01100011", -- | ## ##| 09 - "01100011", -- | ## ##| 10 - "01100011", -- | ## ##| 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 210 --------------- - "00110000", -- | ## | 00 - "00011000", -- | ## | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 211 --------------- - "00001100", -- | ## | 00 - "00011000", -- | ## | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 212 --------------- - "00111100", -- | #### | 00 - "01100110", -- | ## ## | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 213 --------------- - "00111011", -- | ### ##| 00 - "01101110", -- | ## ### | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 214 --------------- - "01100110", -- | ## ## | 00 - "01100110", -- | ## ## | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 215 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "01000010", -- | # # | 04 - "01100110", -- | ## ## | 05 - "00111100", -- | #### | 06 - "00011000", -- | ## | 07 - "00111100", -- | #### | 08 - "01100110", -- | ## ## | 09 - "01000010", -- | # # | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 216 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111110", -- | ##### | 03 - "01100110", -- | ## ## | 04 - "01101110", -- | ## ### | 05 - "01101110", -- | ## ### | 06 - "01111110", -- | ###### | 07 - "01110110", -- | ### ## | 08 - "01110110", -- | ### ## | 09 - "01100110", -- | ## ## | 10 - "01111100", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 217 --------------- - "00110000", -- | ## | 00 - "00011000", -- | ## | 01 - "00000000", -- | | 02 - "01100110", -- | ## ## | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 218 --------------- - "00001100", -- | ## | 00 - "00011000", -- | ## | 01 - "00000000", -- | | 02 - "01100110", -- | ## ## | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 219 --------------- - "00111100", -- | #### | 00 - "01100110", -- | ## ## | 01 - "00000000", -- | | 02 - "01100110", -- | ## ## | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 220 --------------- - "01100110", -- | ## ## | 00 - "01100110", -- | ## ## | 01 - "00000000", -- | | 02 - "01100110", -- | ## ## | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 221 --------------- - "00001100", -- | ## | 00 - "00011000", -- | ## | 01 - "00000000", -- | | 02 - "01100110", -- | ## ## | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "00111100", -- | #### | 07 - "00011000", -- | ## | 08 - "00011000", -- | ## | 09 - "00011000", -- | ## | 10 - "00011000", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 222 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100000", -- | ## | 03 - "01100000", -- | ## | 04 - "01111100", -- | ##### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01111100", -- | ##### | 09 - "01100000", -- | ## | 10 - "01100000", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 223 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111000", -- | ### | 03 - "01101100", -- | ## ## | 04 - "01101100", -- | ## ## | 05 - "01101100", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01101100", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 224 --------------- - "00000000", -- | | 00 - "01110000", -- | ### | 01 - "00110000", -- | ## | 02 - "00011000", -- | ## | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "00000110", -- | ## | 06 - "00000110", -- | ## | 07 - "00111110", -- | ##### | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111110", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 225 --------------- - "00000000", -- | | 00 - "00001110", -- | ### | 01 - "00001100", -- | ## | 02 - "00011000", -- | ## | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "00000110", -- | ## | 06 - "00000110", -- | ## | 07 - "00111110", -- | ##### | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111110", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 226 --------------- - "00000000", -- | | 00 - "00011000", -- | ## | 01 - "00111100", -- | #### | 02 - "01100110", -- | ## ## | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "00000110", -- | ## | 06 - "00000110", -- | ## | 07 - "00111110", -- | ##### | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111110", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 227 --------------- - "00000000", -- | | 00 - "01110001", -- | ### #| 01 - "11011011", -- |## ## ##| 02 - "10001110", -- |# ### | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "00000110", -- | ## | 06 - "00000110", -- | ## | 07 - "00111110", -- | ##### | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111110", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 228 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "01100110", -- | ## ## | 02 - "01100110", -- | ## ## | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "00000110", -- | ## | 06 - "00000110", -- | ## | 07 - "00111110", -- | ##### | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111110", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 229 --------------- - "00000000", -- | | 00 - "00111100", -- | #### | 01 - "01100110", -- | ## ## | 02 - "00111100", -- | #### | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "00000110", -- | ## | 06 - "00000110", -- | ## | 07 - "00111110", -- | ##### | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111110", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 230 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "01101110", -- | ## ### | 05 - "00011011", -- | ## ##| 06 - "00011011", -- | ## ##| 07 - "01111111", -- | #######| 08 - "11011000", -- |## ## | 09 - "11011000", -- |## ## | 10 - "01110111", -- | ### ###| 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 231 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "01100110", -- | ## ## | 06 - "01100000", -- | ## | 07 - "01100000", -- | ## | 08 - "01100000", -- | ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00011000", -- | ## | 12 - "00001100", -- | ## | 13 - "00111000", -- | ### | 14 - "00000000", -- | | 15 - -- ASCII 232 --------------- - "00000000", -- | | 00 - "01110000", -- | ### | 01 - "00110000", -- | ## | 02 - "00011000", -- | ## | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01111110", -- | ###### | 08 - "01100000", -- | ## | 09 - "01100000", -- | ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 233 --------------- - "00000000", -- | | 00 - "00001110", -- | ### | 01 - "00001100", -- | ## | 02 - "00011000", -- | ## | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01111110", -- | ###### | 08 - "01100000", -- | ## | 09 - "01100000", -- | ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 234 --------------- - "00000000", -- | | 00 - "00011000", -- | ## | 01 - "00111100", -- | #### | 02 - "01100110", -- | ## ## | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01111110", -- | ###### | 08 - "01100000", -- | ## | 09 - "01100000", -- | ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 235 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "01100110", -- | ## ## | 02 - "01100110", -- | ## ## | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01111110", -- | ###### | 08 - "01100000", -- | ## | 09 - "01100000", -- | ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 236 --------------- - "00000000", -- | | 00 - "01110000", -- | ### | 01 - "00110000", -- | ## | 02 - "00011000", -- | ## | 03 - "00000000", -- | | 04 - "01111000", -- | #### | 05 - "00011000", -- | ## | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00011000", -- | ## | 09 - "00011000", -- | ## | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 237 --------------- - "00000000", -- | | 00 - "00001110", -- | ### | 01 - "00001100", -- | ## | 02 - "00011000", -- | ## | 03 - "00000000", -- | | 04 - "01111000", -- | #### | 05 - "00011000", -- | ## | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00011000", -- | ## | 09 - "00011000", -- | ## | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 238 --------------- - "00000000", -- | | 00 - "00011000", -- | ## | 01 - "00111100", -- | #### | 02 - "01100110", -- | ## ## | 03 - "00000000", -- | | 04 - "01111000", -- | #### | 05 - "00011000", -- | ## | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00011000", -- | ## | 09 - "00011000", -- | ## | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 239 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "01100110", -- | ## ## | 02 - "01100110", -- | ## ## | 03 - "00000000", -- | | 04 - "01111000", -- | #### | 05 - "00011000", -- | ## | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00011000", -- | ## | 09 - "00011000", -- | ## | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 240 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00110110", -- | ## ## | 03 - "00011000", -- | ## | 04 - "01101100", -- | ## ## | 05 - "00011110", -- | #### | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 241 --------------- - "00000000", -- | | 00 - "01110001", -- | ### #| 01 - "11011011", -- |## ## ##| 02 - "10001110", -- |# ### | 03 - "00000000", -- | | 04 - "01111100", -- | ##### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01100110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 242 --------------- - "00000000", -- | | 00 - "01110000", -- | ### | 01 - "00110000", -- | ## | 02 - "00011000", -- | ## | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 243 --------------- - "00000000", -- | | 00 - "00001110", -- | ### | 01 - "00001100", -- | ## | 02 - "00011000", -- | ## | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 244 --------------- - "00000000", -- | | 00 - "00011000", -- | ## | 01 - "00111100", -- | #### | 02 - "01100110", -- | ## ## | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 245 --------------- - "00000000", -- | | 00 - "01110001", -- | ### #| 01 - "11011011", -- |## ## ##| 02 - "10001110", -- |# ### | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 246 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "01100110", -- | ## ## | 02 - "01100110", -- | ## ## | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 247 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00011000", -- | ## | 04 - "00011000", -- | ## | 05 - "00000000", -- | | 06 - "01111110", -- | ###### | 07 - "00000000", -- | | 08 - "00011000", -- | ## | 09 - "00011000", -- | ## | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 248 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00111110", -- | ##### | 05 - "01100110", -- | ## ## | 06 - "01101110", -- | ## ### | 07 - "01111110", -- | ###### | 08 - "01110110", -- | ### ## | 09 - "01100110", -- | ## ## | 10 - "01111100", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 249 --------------- - "00000000", -- | | 00 - "01110000", -- | ### | 01 - "00110000", -- | ## | 02 - "00011000", -- | ## | 03 - "00000000", -- | | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111110", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 250 --------------- - "00000000", -- | | 00 - "00001110", -- | ### | 01 - "00001100", -- | ## | 02 - "00011000", -- | ## | 03 - "00000000", -- | | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111110", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 251 --------------- - "00000000", -- | | 00 - "00011000", -- | ## | 01 - "00111100", -- | #### | 02 - "01100110", -- | ## ## | 03 - "00000000", -- | | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111110", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 252 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "01100110", -- | ## ## | 02 - "01100110", -- | ## ## | 03 - "00000000", -- | | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111110", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 253 --------------- - "00000000", -- | | 00 - "00001110", -- | ### | 01 - "00001100", -- | ## | 02 - "00011000", -- | ## | 03 - "00000000", -- | | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00001100", -- | ## | 12 - "00011000", -- | ## | 13 - "11110000", -- |#### | 14 - "00000000", -- | | 15 - -- ASCII 254 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100000", -- | ## | 03 - "01100000", -- | ## | 04 - "01100000", -- | ## | 05 - "01111100", -- | ##### | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01111100", -- | ##### | 11 - "01100000", -- | ## | 12 - "01100000", -- | ## | 13 - "01100000", -- | ## | 14 - "00000000", -- | | 15 - -- ASCII 255 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "01100110", -- | ## ## | 02 - "01100110", -- | ## ## | 03 - "00000000", -- | | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00001100", -- | ## | 12 - "00011000", -- | ## | 13 - "11110000", -- |#### | 14 - "00000000", -- | | 15 - -- ASCII 256 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 257 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 258 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 259 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 260 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 261 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 262 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 263 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 264 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 265 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 266 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 267 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 268 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 269 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 270 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 271 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 272 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 273 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 274 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 275 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 276 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 277 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 278 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 279 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 280 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 281 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 282 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 283 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 284 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 285 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 286 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 287 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "11111111", -- |########| 12 - "11111111", -- |########| 13 - "11111111", -- |########| 14 - "00000000" -- | | 15 - ); -begin - - p_rom : process - begin - wait until rising_edge(CLK); - DATA <= ROM(to_integer(unsigned(ADDR))); - end process; - -end RTL; - diff --git a/lib/VGA_ctrl/src/fonts/char_rom_fixedsys_9x16.vhd b/lib/VGA_ctrl/src/fonts/char_rom_fixedsys_9x16.vhd deleted file mode 100644 index 9b32d16..0000000 --- a/lib/VGA_ctrl/src/fonts/char_rom_fixedsys_9x16.vhd +++ /dev/null @@ -1,4351 +0,0 @@ -library ieee; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity char_rom is - port - ( - CLK : in std_logic; - ADDR : in unsigned(11 downto 0); - DATA : out unsigned(8 downto 0) - ); -end; - -architecture RTL of char_rom is - - - type ROM_ARRAY is array(0 to 4095) of unsigned(8 downto 0); - constant ROM : ROM_ARRAY := - ( - -- ASCII 032 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "000000000", -- | | 05 - "000000000", -- | | 06 - "000000000", -- | | 07 - "000000000", -- | | 08 - "000000000", -- | | 09 - "000000000", -- | | 10 - "000000000", -- | | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 033 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000110000", -- | ## | 03 - "001111000", -- | #### | 04 - "001111000", -- | #### | 05 - "001111000", -- | #### | 06 - "000110000", -- | ## | 07 - "000110000", -- | ## | 08 - "000000000", -- | | 09 - "000110000", -- | ## | 10 - "000110000", -- | ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 034 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011001100", -- | ## ## | 03 - "011001100", -- | ## ## | 04 - "011001100", -- | ## ## | 05 - "000000000", -- | | 06 - "000000000", -- | | 07 - "000000000", -- | | 08 - "000000000", -- | | 09 - "000000000", -- | | 10 - "000000000", -- | | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 035 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "001101100", -- | ## ## | 03 - "001101100", -- | ## ## | 04 - "011111110", -- | ####### | 05 - "001101100", -- | ## ## | 06 - "001101100", -- | ## ## | 07 - "001101100", -- | ## ## | 08 - "011111110", -- | ####### | 09 - "001101100", -- | ## ## | 10 - "001101100", -- | ## ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 036 --------------- - "000000000", -- | | 00 - "000110000", -- | ## | 01 - "000110000", -- | ## | 02 - "001111000", -- | #### | 03 - "011001100", -- | ## ## | 04 - "011000000", -- | ## | 05 - "001100000", -- | ## | 06 - "000110000", -- | ## | 07 - "000011000", -- | ## | 08 - "000001100", -- | ## | 09 - "011001100", -- | ## ## | 10 - "001111000", -- | #### | 11 - "000110000", -- | ## | 12 - "000110000", -- | ## | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 037 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "011100000", -- | ### | 02 - "110110000", -- |## ## | 03 - "110110100", -- |## ## # | 04 - "011101100", -- | ### ## | 05 - "000011000", -- | ## | 06 - "000110000", -- | ## | 07 - "001100000", -- | ## | 08 - "011011100", -- | ## ### | 09 - "010110110", -- | # ## ## | 10 - "000110110", -- | ## ## | 11 - "000011100", -- | ### | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 038 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "000000000", -- | | 05 - "000000000", -- | | 06 - "000000000", -- | | 07 - "000000000", -- | | 08 - "000000000", -- | | 09 - "000000000", -- | | 10 - "000000000", -- | | 11 - "000000000", -- | | 12 - "111111110", -- |######## | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 039 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000110000", -- | ## | 03 - "000110000", -- | ## | 04 - "000110000", -- | ## | 05 - "000000000", -- | | 06 - "000000000", -- | | 07 - "000000000", -- | | 08 - "000000000", -- | | 09 - "000000000", -- | | 10 - "000000000", -- | | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 040 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000011000", -- | ## | 03 - "000110000", -- | ## | 04 - "000110000", -- | ## | 05 - "001100000", -- | ## | 06 - "001100000", -- | ## | 07 - "001100000", -- | ## | 08 - "001100000", -- | ## | 09 - "001100000", -- | ## | 10 - "000110000", -- | ## | 11 - "000110000", -- | ## | 12 - "000011000", -- | ## | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 041 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "001100000", -- | ## | 03 - "000110000", -- | ## | 04 - "000110000", -- | ## | 05 - "000011000", -- | ## | 06 - "000011000", -- | ## | 07 - "000011000", -- | ## | 08 - "000011000", -- | ## | 09 - "000011000", -- | ## | 10 - "000110000", -- | ## | 11 - "000110000", -- | ## | 12 - "001100000", -- | ## | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 042 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "001101100", -- | ## ## | 05 - "000111000", -- | ### | 06 - "011111110", -- | ####### | 07 - "000111000", -- | ### | 08 - "001101100", -- | ## ## | 09 - "000000000", -- | | 10 - "000000000", -- | | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 043 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "000110000", -- | ## | 05 - "000110000", -- | ## | 06 - "011111100", -- | ###### | 07 - "000110000", -- | ## | 08 - "000110000", -- | ## | 09 - "000000000", -- | | 10 - "000000000", -- | | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 044 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "000000000", -- | | 05 - "000000000", -- | | 06 - "000000000", -- | | 07 - "000000000", -- | | 08 - "000000000", -- | | 09 - "000111000", -- | ### | 10 - "000111000", -- | ### | 11 - "000011000", -- | ## | 12 - "000110000", -- | ## | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 045 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "000000000", -- | | 05 - "000000000", -- | | 06 - "011111100", -- | ###### | 07 - "000000000", -- | | 08 - "000000000", -- | | 09 - "000000000", -- | | 10 - "000000000", -- | | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 046 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "000000000", -- | | 05 - "000000000", -- | | 06 - "000000000", -- | | 07 - "000000000", -- | | 08 - "000000000", -- | | 09 - "000111000", -- | ### | 10 - "000111000", -- | ### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 047 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000001100", -- | ## | 03 - "000001100", -- | ## | 04 - "000011000", -- | ## | 05 - "000011000", -- | ## | 06 - "000110000", -- | ## | 07 - "000110000", -- | ## | 08 - "001100000", -- | ## | 09 - "001100000", -- | ## | 10 - "011000000", -- | ## | 11 - "011000000", -- | ## | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 048 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000111100", -- | #### | 03 - "001100110", -- | ## ## | 04 - "001101110", -- | ## ### | 05 - "001101110", -- | ## ### | 06 - "001100110", -- | ## ## | 07 - "001110110", -- | ### ## | 08 - "001110110", -- | ### ## | 09 - "001100110", -- | ## ## | 10 - "000111100", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 049 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000011000", -- | ## | 03 - "000111000", -- | ### | 04 - "011111000", -- | ##### | 05 - "000011000", -- | ## | 06 - "000011000", -- | ## | 07 - "000011000", -- | ## | 08 - "000011000", -- | ## | 09 - "000011000", -- | ## | 10 - "000011000", -- | ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 050 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "001111000", -- | #### | 03 - "011001100", -- | ## ## | 04 - "011001100", -- | ## ## | 05 - "000001100", -- | ## | 06 - "000011000", -- | ## | 07 - "000110000", -- | ## | 08 - "001100000", -- | ## | 09 - "011000000", -- | ## | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 051 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "001111000", -- | #### | 03 - "011001100", -- | ## ## | 04 - "011001100", -- | ## ## | 05 - "000001100", -- | ## | 06 - "000111000", -- | ### | 07 - "000001100", -- | ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 052 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "001100000", -- | ## | 03 - "001100000", -- | ## | 04 - "001101100", -- | ## ## | 05 - "001101100", -- | ## ## | 06 - "001101100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011111110", -- | ####### | 09 - "000001100", -- | ## | 10 - "000001100", -- | ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 053 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "011000000", -- | ## | 04 - "011000000", -- | ## | 05 - "011000000", -- | ## | 06 - "011111000", -- | ##### | 07 - "000001100", -- | ## | 08 - "000001100", -- | ## | 09 - "000011000", -- | ## | 10 - "011110000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 054 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000111000", -- | ### | 03 - "000110000", -- | ## | 04 - "001100000", -- | ## | 05 - "011111000", -- | ##### | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 055 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "000001100", -- | ## | 04 - "000011000", -- | ## | 05 - "000011000", -- | ## | 06 - "000110000", -- | ## | 07 - "000110000", -- | ## | 08 - "001100000", -- | ## | 09 - "001100000", -- | ## | 10 - "001100000", -- | ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 056 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "001111000", -- | #### | 03 - "011001100", -- | ## ## | 04 - "011001100", -- | ## ## | 05 - "011101100", -- | ### ## | 06 - "001111000", -- | #### | 07 - "011011100", -- | ## ### | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 057 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "001111000", -- | #### | 03 - "011001100", -- | ## ## | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "001111100", -- | ##### | 08 - "000011000", -- | ## | 09 - "000110000", -- | ## | 10 - "001110000", -- | ### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 058 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "000111000", -- | ### | 05 - "000111000", -- | ### | 06 - "000000000", -- | | 07 - "000000000", -- | | 08 - "000000000", -- | | 09 - "000111000", -- | ### | 10 - "000111000", -- | ### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 059 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "000111000", -- | ### | 05 - "000111000", -- | ### | 06 - "000000000", -- | | 07 - "000000000", -- | | 08 - "000000000", -- | | 09 - "000111000", -- | ### | 10 - "000111000", -- | ### | 11 - "000011000", -- | ## | 12 - "000110000", -- | ## | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 060 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000001100", -- | ## | 03 - "000011000", -- | ## | 04 - "000110000", -- | ## | 05 - "001100000", -- | ## | 06 - "011000000", -- | ## | 07 - "001100000", -- | ## | 08 - "000110000", -- | ## | 09 - "000011000", -- | ## | 10 - "000001100", -- | ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 061 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "000000000", -- | | 05 - "011111100", -- | ###### | 06 - "000000000", -- | | 07 - "011111100", -- | ###### | 08 - "000000000", -- | | 09 - "000000000", -- | | 10 - "000000000", -- | | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 062 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011000000", -- | ## | 03 - "001100000", -- | ## | 04 - "000110000", -- | ## | 05 - "000011000", -- | ## | 06 - "000001100", -- | ## | 07 - "000011000", -- | ## | 08 - "000110000", -- | ## | 09 - "001100000", -- | ## | 10 - "011000000", -- | ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 063 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "001111000", -- | #### | 03 - "011001100", -- | ## ## | 04 - "011001100", -- | ## ## | 05 - "000011000", -- | ## | 06 - "000110000", -- | ## | 07 - "000110000", -- | ## | 08 - "000000000", -- | | 09 - "000110000", -- | ## | 10 - "000110000", -- | ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 064 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "110000110", -- |## ## | 04 - "110000110", -- |## ## | 05 - "110011110", -- |## #### | 06 - "110110110", -- |## ## ## | 07 - "110110110", -- |## ## ## | 08 - "110011110", -- |## #### | 09 - "110000000", -- |## | 10 - "011111110", -- | ####### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 065 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000110000", -- | ## | 03 - "001111000", -- | #### | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011111100", -- | ###### | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "011001100", -- | ## ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 066 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111000", -- | ##### | 03 - "011001100", -- | ## ## | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "011111000", -- | ##### | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "011111000", -- | ##### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 067 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "001111000", -- | #### | 03 - "011001100", -- | ## ## | 04 - "011001100", -- | ## ## | 05 - "011000000", -- | ## | 06 - "011000000", -- | ## | 07 - "011000000", -- | ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 068 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011110000", -- | #### | 03 - "011011000", -- | ## ## | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011011000", -- | ## ## | 10 - "011110000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 069 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "011000000", -- | ## | 04 - "011000000", -- | ## | 05 - "011000000", -- | ## | 06 - "011111000", -- | ##### | 07 - "011000000", -- | ## | 08 - "011000000", -- | ## | 09 - "011000000", -- | ## | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 070 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "011000000", -- | ## | 04 - "011000000", -- | ## | 05 - "011000000", -- | ## | 06 - "011111000", -- | ##### | 07 - "011000000", -- | ## | 08 - "011000000", -- | ## | 09 - "011000000", -- | ## | 10 - "011000000", -- | ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 071 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "001111000", -- | #### | 03 - "011001100", -- | ## ## | 04 - "011001100", -- | ## ## | 05 - "011000000", -- | ## | 06 - "011000000", -- | ## | 07 - "011011100", -- | ## ### | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111100", -- | ##### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 072 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011001100", -- | ## ## | 03 - "011001100", -- | ## ## | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "011111100", -- | ###### | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "011001100", -- | ## ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 073 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "001111000", -- | #### | 03 - "000110000", -- | ## | 04 - "000110000", -- | ## | 05 - "000110000", -- | ## | 06 - "000110000", -- | ## | 07 - "000110000", -- | ## | 08 - "000110000", -- | ## | 09 - "000110000", -- | ## | 10 - "001111000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 074 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000001100", -- | ## | 03 - "000001100", -- | ## | 04 - "000001100", -- | ## | 05 - "000001100", -- | ## | 06 - "000001100", -- | ## | 07 - "000001100", -- | ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 075 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011001100", -- | ## ## | 03 - "011001100", -- | ## ## | 04 - "011011000", -- | ## ## | 05 - "011011000", -- | ## ## | 06 - "011110000", -- | #### | 07 - "011011000", -- | ## ## | 08 - "011011000", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "011001100", -- | ## ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 076 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011000000", -- | ## | 03 - "011000000", -- | ## | 04 - "011000000", -- | ## | 05 - "011000000", -- | ## | 06 - "011000000", -- | ## | 07 - "011000000", -- | ## | 08 - "011000000", -- | ## | 09 - "011000000", -- | ## | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 077 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011000110", -- | ## ## | 03 - "011000110", -- | ## ## | 04 - "011101110", -- | ### ### | 05 - "011010110", -- | ## # ## | 06 - "011010110", -- | ## # ## | 07 - "011010110", -- | ## # ## | 08 - "011000110", -- | ## ## | 09 - "011000110", -- | ## ## | 10 - "011000110", -- | ## ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 078 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011000110", -- | ## ## | 03 - "011000110", -- | ## ## | 04 - "011100110", -- | ### ## | 05 - "011110110", -- | #### ## | 06 - "011011110", -- | ## #### | 07 - "011001110", -- | ## ### | 08 - "011000110", -- | ## ## | 09 - "011000110", -- | ## ## | 10 - "011000110", -- | ## ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 079 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "001111000", -- | #### | 03 - "011001100", -- | ## ## | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 080 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111000", -- | ##### | 03 - "011001100", -- | ## ## | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "011111000", -- | ##### | 07 - "011000000", -- | ## | 08 - "011000000", -- | ## | 09 - "011000000", -- | ## | 10 - "011000000", -- | ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 081 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "001111000", -- | #### | 03 - "011001100", -- | ## ## | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111000", -- | #### | 11 - "000011000", -- | ## | 12 - "000001100", -- | ## | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 082 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111000", -- | ##### | 03 - "011001100", -- | ## ## | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "011111000", -- | ##### | 07 - "011011000", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "011001100", -- | ## ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 083 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "001111000", -- | #### | 03 - "011001100", -- | ## ## | 04 - "011000000", -- | ## | 05 - "001100000", -- | ## | 06 - "000110000", -- | ## | 07 - "000011000", -- | ## | 08 - "000001100", -- | ## | 09 - "011001100", -- | ## ## | 10 - "001111000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 084 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "000110000", -- | ## | 04 - "000110000", -- | ## | 05 - "000110000", -- | ## | 06 - "000110000", -- | ## | 07 - "000110000", -- | ## | 08 - "000110000", -- | ## | 09 - "000110000", -- | ## | 10 - "000110000", -- | ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 085 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011001100", -- | ## ## | 03 - "011001100", -- | ## ## | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 086 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011001100", -- | ## ## | 03 - "011001100", -- | ## ## | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "001111000", -- | #### | 10 - "000110000", -- | ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 087 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011000110", -- | ## ## | 03 - "011000110", -- | ## ## | 04 - "011000110", -- | ## ## | 05 - "011010110", -- | ## # ## | 06 - "011010110", -- | ## # ## | 07 - "011010110", -- | ## # ## | 08 - "001101100", -- | ## ## | 09 - "001101100", -- | ## ## | 10 - "001101100", -- | ## ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 088 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011001100", -- | ## ## | 03 - "011001100", -- | ## ## | 04 - "001101000", -- | ## # | 05 - "000110000", -- | ## | 06 - "000110000", -- | ## | 07 - "001011000", -- | # ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "011001100", -- | ## ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 089 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011001100", -- | ## ## | 03 - "011001100", -- | ## ## | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "001111000", -- | #### | 07 - "000110000", -- | ## | 08 - "000110000", -- | ## | 09 - "000110000", -- | ## | 10 - "000110000", -- | ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 090 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "000001100", -- | ## | 04 - "000001100", -- | ## | 05 - "000011000", -- | ## | 06 - "000110000", -- | ## | 07 - "001100000", -- | ## | 08 - "011000000", -- | ## | 09 - "011000000", -- | ## | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 091 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "001111000", -- | #### | 03 - "001100000", -- | ## | 04 - "001100000", -- | ## | 05 - "001100000", -- | ## | 06 - "001100000", -- | ## | 07 - "001100000", -- | ## | 08 - "001100000", -- | ## | 09 - "001100000", -- | ## | 10 - "001100000", -- | ## | 11 - "001100000", -- | ## | 12 - "001100000", -- | ## | 13 - "001111000", -- | #### | 14 - "000000000", -- | | 15 - -- ASCII 092 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011000000", -- | ## | 03 - "011000000", -- | ## | 04 - "001100000", -- | ## | 05 - "001100000", -- | ## | 06 - "000110000", -- | ## | 07 - "000110000", -- | ## | 08 - "000011000", -- | ## | 09 - "000011000", -- | ## | 10 - "000001100", -- | ## | 11 - "000001100", -- | ## | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 093 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "001111000", -- | #### | 03 - "000011000", -- | ## | 04 - "000011000", -- | ## | 05 - "000011000", -- | ## | 06 - "000011000", -- | ## | 07 - "000011000", -- | ## | 08 - "000011000", -- | ## | 09 - "000011000", -- | ## | 10 - "000011000", -- | ## | 11 - "000011000", -- | ## | 12 - "000011000", -- | ## | 13 - "001111000", -- | #### | 14 - "000000000", -- | | 15 - -- ASCII 094 --------------- - "000000000", -- | | 00 - "000110000", -- | ## | 01 - "001111000", -- | #### | 02 - "011001100", -- | ## ## | 03 - "000000000", -- | | 04 - "000000000", -- | | 05 - "000000000", -- | | 06 - "000000000", -- | | 07 - "000000000", -- | | 08 - "000000000", -- | | 09 - "000000000", -- | | 10 - "000000000", -- | | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 095 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "000000000", -- | | 05 - "000000000", -- | | 06 - "000000000", -- | | 07 - "000000000", -- | | 08 - "000000000", -- | | 09 - "000000000", -- | | 10 - "000000000", -- | | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "111111110", -- |######## | 14 - "000000000", -- | | 15 - -- ASCII 096 --------------- - "000000000", -- | | 00 - "001110000", -- | ### | 01 - "000110000", -- | ## | 02 - "000011000", -- | ## | 03 - "000000000", -- | | 04 - "000000000", -- | | 05 - "000000000", -- | | 06 - "000000000", -- | | 07 - "000000000", -- | | 08 - "000000000", -- | | 09 - "000000000", -- | | 10 - "000000000", -- | | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 097 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "001111000", -- | #### | 05 - "000001100", -- | ## | 06 - "000001100", -- | ## | 07 - "001111100", -- | ##### | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111100", -- | ##### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 098 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011000000", -- | ## | 03 - "011000000", -- | ## | 04 - "011111000", -- | ##### | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "011111000", -- | ##### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 099 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "001111000", -- | #### | 05 - "011001100", -- | ## ## | 06 - "011000000", -- | ## | 07 - "011000000", -- | ## | 08 - "011000000", -- | ## | 09 - "011001100", -- | ## ## | 10 - "001111000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 100 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000001100", -- | ## | 03 - "000001100", -- | ## | 04 - "001111100", -- | ##### | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111100", -- | ##### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 101 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "001111000", -- | #### | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011111100", -- | ###### | 08 - "011000000", -- | ## | 09 - "011000000", -- | ## | 10 - "001111000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 102 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000111100", -- | #### | 03 - "001100000", -- | ## | 04 - "001100000", -- | ## | 05 - "001100000", -- | ## | 06 - "011111100", -- | ###### | 07 - "001100000", -- | ## | 08 - "001100000", -- | ## | 09 - "001100000", -- | ## | 10 - "001100000", -- | ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 103 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "001111100", -- | ##### | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111100", -- | ##### | 11 - "000001100", -- | ## | 12 - "000001100", -- | ## | 13 - "011111000", -- | ##### | 14 - "000000000", -- | | 15 - -- ASCII 104 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011000000", -- | ## | 03 - "011000000", -- | ## | 04 - "011111000", -- | ##### | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "011001100", -- | ## ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 105 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000110000", -- | ## | 02 - "000110000", -- | ## | 03 - "000000000", -- | | 04 - "011110000", -- | #### | 05 - "000110000", -- | ## | 06 - "000110000", -- | ## | 07 - "000110000", -- | ## | 08 - "000110000", -- | ## | 09 - "000110000", -- | ## | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 106 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000011000", -- | ## | 02 - "000011000", -- | ## | 03 - "000000000", -- | | 04 - "001111000", -- | #### | 05 - "000011000", -- | ## | 06 - "000011000", -- | ## | 07 - "000011000", -- | ## | 08 - "000011000", -- | ## | 09 - "000011000", -- | ## | 10 - "000011000", -- | ## | 11 - "000011000", -- | ## | 12 - "000011000", -- | ## | 13 - "011110000", -- | #### | 14 - "000000000", -- | | 15 - -- ASCII 107 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011000000", -- | ## | 03 - "011000000", -- | ## | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "011011000", -- | ## ## | 07 - "011110000", -- | #### | 08 - "011011000", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "011001100", -- | ## ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 108 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011110000", -- | #### | 03 - "000110000", -- | ## | 04 - "000110000", -- | ## | 05 - "000110000", -- | ## | 06 - "000110000", -- | ## | 07 - "000110000", -- | ## | 08 - "000110000", -- | ## | 09 - "000110000", -- | ## | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 109 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "011111100", -- | ###### | 05 - "011010110", -- | ## # ## | 06 - "011010110", -- | ## # ## | 07 - "011010110", -- | ## # ## | 08 - "011010110", -- | ## # ## | 09 - "011010110", -- | ## # ## | 10 - "011000110", -- | ## ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 110 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "011111000", -- | ##### | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "011001100", -- | ## ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 111 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "001111000", -- | #### | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 112 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "011111000", -- | ##### | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "011111000", -- | ##### | 11 - "011000000", -- | ## | 12 - "011000000", -- | ## | 13 - "011000000", -- | ## | 14 - "000000000", -- | | 15 - -- ASCII 113 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "001111100", -- | ##### | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111100", -- | ##### | 11 - "000001100", -- | ## | 12 - "000001100", -- | ## | 13 - "000001100", -- | ## | 14 - "000000000", -- | | 15 - -- ASCII 114 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "011001100", -- | ## ## | 05 - "011011100", -- | ## ### | 06 - "011100000", -- | ### | 07 - "011000000", -- | ## | 08 - "011000000", -- | ## | 09 - "011000000", -- | ## | 10 - "011000000", -- | ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 115 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "001111100", -- | ##### | 05 - "011000000", -- | ## | 06 - "011000000", -- | ## | 07 - "001111000", -- | #### | 08 - "000001100", -- | ## | 09 - "000001100", -- | ## | 10 - "011111000", -- | ##### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 116 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "001100000", -- | ## | 03 - "001100000", -- | ## | 04 - "011111100", -- | ###### | 05 - "001100000", -- | ## | 06 - "001100000", -- | ## | 07 - "001100000", -- | ## | 08 - "001100000", -- | ## | 09 - "001100000", -- | ## | 10 - "000111100", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 117 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111100", -- | ##### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 118 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "001111000", -- | #### | 10 - "000110000", -- | ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 119 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "011000110", -- | ## ## | 05 - "011010110", -- | ## # ## | 06 - "011010110", -- | ## # ## | 07 - "011010110", -- | ## # ## | 08 - "011010110", -- | ## # ## | 09 - "001101100", -- | ## ## | 10 - "001101100", -- | ## ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 120 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "001111000", -- | #### | 07 - "000110000", -- | ## | 08 - "001111000", -- | #### | 09 - "011001100", -- | ## ## | 10 - "011001100", -- | ## ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 121 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111000", -- | #### | 11 - "000011000", -- | ## | 12 - "000110000", -- | ## | 13 - "111100000", -- |#### | 14 - "000000000", -- | | 15 - -- ASCII 122 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "011111100", -- | ###### | 05 - "000001100", -- | ## | 06 - "000011000", -- | ## | 07 - "000110000", -- | ## | 08 - "001100000", -- | ## | 09 - "011000000", -- | ## | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 123 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000011000", -- | ## | 03 - "000110000", -- | ## | 04 - "000110000", -- | ## | 05 - "000110000", -- | ## | 06 - "001100000", -- | ## | 07 - "011000000", -- | ## | 08 - "001100000", -- | ## | 09 - "000110000", -- | ## | 10 - "000110000", -- | ## | 11 - "000110000", -- | ## | 12 - "000011000", -- | ## | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 124 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000110000", -- | ## | 03 - "000110000", -- | ## | 04 - "000110000", -- | ## | 05 - "000110000", -- | ## | 06 - "000110000", -- | ## | 07 - "000110000", -- | ## | 08 - "000110000", -- | ## | 09 - "000110000", -- | ## | 10 - "000110000", -- | ## | 11 - "000110000", -- | ## | 12 - "000110000", -- | ## | 13 - "000110000", -- | ## | 14 - "000000000", -- | | 15 - -- ASCII 125 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "001100000", -- | ## | 03 - "000110000", -- | ## | 04 - "000110000", -- | ## | 05 - "000110000", -- | ## | 06 - "000011000", -- | ## | 07 - "000001100", -- | ## | 08 - "000011000", -- | ## | 09 - "000110000", -- | ## | 10 - "000110000", -- | ## | 11 - "000110000", -- | ## | 12 - "001100000", -- | ## | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 126 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011100010", -- | ### # | 03 - "110110110", -- |## ## ## | 04 - "100011100", -- |# ### | 05 - "000000000", -- | | 06 - "000000000", -- | | 07 - "000000000", -- | | 08 - "000000000", -- | | 09 - "000000000", -- | | 10 - "000000000", -- | | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 127 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "011111100", -- | ###### | 04 - "011111100", -- | ###### | 05 - "011111100", -- | ###### | 06 - "011111100", -- | ###### | 07 - "011111100", -- | ###### | 08 - "011111100", -- | ###### | 09 - "011111100", -- | ###### | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 128 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "011111100", -- | ###### | 04 - "011111100", -- | ###### | 05 - "011111100", -- | ###### | 06 - "011111100", -- | ###### | 07 - "011111100", -- | ###### | 08 - "011111100", -- | ###### | 09 - "011111100", -- | ###### | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 129 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "011111100", -- | ###### | 04 - "011111100", -- | ###### | 05 - "011111100", -- | ###### | 06 - "011111100", -- | ###### | 07 - "011111100", -- | ###### | 08 - "011111100", -- | ###### | 09 - "011111100", -- | ###### | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 130 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "011111100", -- | ###### | 04 - "011111100", -- | ###### | 05 - "011111100", -- | ###### | 06 - "011111100", -- | ###### | 07 - "011111100", -- | ###### | 08 - "011111100", -- | ###### | 09 - "011111100", -- | ###### | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 131 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "011111100", -- | ###### | 04 - "011111100", -- | ###### | 05 - "011111100", -- | ###### | 06 - "011111100", -- | ###### | 07 - "011111100", -- | ###### | 08 - "011111100", -- | ###### | 09 - "011111100", -- | ###### | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 132 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "011111100", -- | ###### | 04 - "011111100", -- | ###### | 05 - "011111100", -- | ###### | 06 - "011111100", -- | ###### | 07 - "011111100", -- | ###### | 08 - "011111100", -- | ###### | 09 - "011111100", -- | ###### | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 133 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "011111100", -- | ###### | 04 - "011111100", -- | ###### | 05 - "011111100", -- | ###### | 06 - "011111100", -- | ###### | 07 - "011111100", -- | ###### | 08 - "011111100", -- | ###### | 09 - "011111100", -- | ###### | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 134 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "011111100", -- | ###### | 04 - "011111100", -- | ###### | 05 - "011111100", -- | ###### | 06 - "011111100", -- | ###### | 07 - "011111100", -- | ###### | 08 - "011111100", -- | ###### | 09 - "011111100", -- | ###### | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 135 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "011111100", -- | ###### | 04 - "011111100", -- | ###### | 05 - "011111100", -- | ###### | 06 - "011111100", -- | ###### | 07 - "011111100", -- | ###### | 08 - "011111100", -- | ###### | 09 - "011111100", -- | ###### | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 136 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "011111100", -- | ###### | 04 - "011111100", -- | ###### | 05 - "011111100", -- | ###### | 06 - "011111100", -- | ###### | 07 - "011111100", -- | ###### | 08 - "011111100", -- | ###### | 09 - "011111100", -- | ###### | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 137 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "011111100", -- | ###### | 04 - "011111100", -- | ###### | 05 - "011111100", -- | ###### | 06 - "011111100", -- | ###### | 07 - "011111100", -- | ###### | 08 - "011111100", -- | ###### | 09 - "011111100", -- | ###### | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 138 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "011111100", -- | ###### | 04 - "011111100", -- | ###### | 05 - "011111100", -- | ###### | 06 - "011111100", -- | ###### | 07 - "011111100", -- | ###### | 08 - "011111100", -- | ###### | 09 - "011111100", -- | ###### | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 139 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "011111100", -- | ###### | 04 - "011111100", -- | ###### | 05 - "011111100", -- | ###### | 06 - "011111100", -- | ###### | 07 - "011111100", -- | ###### | 08 - "011111100", -- | ###### | 09 - "011111100", -- | ###### | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 140 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "011111100", -- | ###### | 04 - "011111100", -- | ###### | 05 - "011111100", -- | ###### | 06 - "011111100", -- | ###### | 07 - "011111100", -- | ###### | 08 - "011111100", -- | ###### | 09 - "011111100", -- | ###### | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 141 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "011111100", -- | ###### | 04 - "011111100", -- | ###### | 05 - "011111100", -- | ###### | 06 - "011111100", -- | ###### | 07 - "011111100", -- | ###### | 08 - "011111100", -- | ###### | 09 - "011111100", -- | ###### | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 142 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "011111100", -- | ###### | 04 - "011111100", -- | ###### | 05 - "011111100", -- | ###### | 06 - "011111100", -- | ###### | 07 - "011111100", -- | ###### | 08 - "011111100", -- | ###### | 09 - "011111100", -- | ###### | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 143 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "011111100", -- | ###### | 04 - "011111100", -- | ###### | 05 - "011111100", -- | ###### | 06 - "011111100", -- | ###### | 07 - "011111100", -- | ###### | 08 - "011111100", -- | ###### | 09 - "011111100", -- | ###### | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 144 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "011111100", -- | ###### | 04 - "011111100", -- | ###### | 05 - "011111100", -- | ###### | 06 - "011111100", -- | ###### | 07 - "011111100", -- | ###### | 08 - "011111100", -- | ###### | 09 - "011111100", -- | ###### | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 145 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000011000", -- | ## | 03 - "000110000", -- | ## | 04 - "000111000", -- | ### | 05 - "000111000", -- | ### | 06 - "000000000", -- | | 07 - "000000000", -- | | 08 - "000000000", -- | | 09 - "000000000", -- | | 10 - "000000000", -- | | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 146 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000111000", -- | ### | 03 - "000111000", -- | ### | 04 - "000011000", -- | ## | 05 - "000110000", -- | ## | 06 - "000000000", -- | | 07 - "000000000", -- | | 08 - "000000000", -- | | 09 - "000000000", -- | | 10 - "000000000", -- | | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 147 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "011111100", -- | ###### | 04 - "011111100", -- | ###### | 05 - "011111100", -- | ###### | 06 - "011111100", -- | ###### | 07 - "011111100", -- | ###### | 08 - "011111100", -- | ###### | 09 - "011111100", -- | ###### | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 148 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "011111100", -- | ###### | 04 - "011111100", -- | ###### | 05 - "011111100", -- | ###### | 06 - "011111100", -- | ###### | 07 - "011111100", -- | ###### | 08 - "011111100", -- | ###### | 09 - "011111100", -- | ###### | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 149 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "011111100", -- | ###### | 04 - "011111100", -- | ###### | 05 - "011111100", -- | ###### | 06 - "011111100", -- | ###### | 07 - "011111100", -- | ###### | 08 - "011111100", -- | ###### | 09 - "011111100", -- | ###### | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 150 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "011111100", -- | ###### | 04 - "011111100", -- | ###### | 05 - "011111100", -- | ###### | 06 - "011111100", -- | ###### | 07 - "011111100", -- | ###### | 08 - "011111100", -- | ###### | 09 - "011111100", -- | ###### | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 151 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "011111100", -- | ###### | 04 - "011111100", -- | ###### | 05 - "011111100", -- | ###### | 06 - "011111100", -- | ###### | 07 - "011111100", -- | ###### | 08 - "011111100", -- | ###### | 09 - "011111100", -- | ###### | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 152 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "011111100", -- | ###### | 04 - "011111100", -- | ###### | 05 - "011111100", -- | ###### | 06 - "011111100", -- | ###### | 07 - "011111100", -- | ###### | 08 - "011111100", -- | ###### | 09 - "011111100", -- | ###### | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 153 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "011111100", -- | ###### | 04 - "011111100", -- | ###### | 05 - "011111100", -- | ###### | 06 - "011111100", -- | ###### | 07 - "011111100", -- | ###### | 08 - "011111100", -- | ###### | 09 - "011111100", -- | ###### | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 154 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "011111100", -- | ###### | 04 - "011111100", -- | ###### | 05 - "011111100", -- | ###### | 06 - "011111100", -- | ###### | 07 - "011111100", -- | ###### | 08 - "011111100", -- | ###### | 09 - "011111100", -- | ###### | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 155 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "011111100", -- | ###### | 04 - "011111100", -- | ###### | 05 - "011111100", -- | ###### | 06 - "011111100", -- | ###### | 07 - "011111100", -- | ###### | 08 - "011111100", -- | ###### | 09 - "011111100", -- | ###### | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 156 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "011111100", -- | ###### | 04 - "011111100", -- | ###### | 05 - "011111100", -- | ###### | 06 - "011111100", -- | ###### | 07 - "011111100", -- | ###### | 08 - "011111100", -- | ###### | 09 - "011111100", -- | ###### | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 157 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "011111100", -- | ###### | 04 - "011111100", -- | ###### | 05 - "011111100", -- | ###### | 06 - "011111100", -- | ###### | 07 - "011111100", -- | ###### | 08 - "011111100", -- | ###### | 09 - "011111100", -- | ###### | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 158 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "011111100", -- | ###### | 04 - "011111100", -- | ###### | 05 - "011111100", -- | ###### | 06 - "011111100", -- | ###### | 07 - "011111100", -- | ###### | 08 - "011111100", -- | ###### | 09 - "011111100", -- | ###### | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 159 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "011111100", -- | ###### | 04 - "011111100", -- | ###### | 05 - "011111100", -- | ###### | 06 - "011111100", -- | ###### | 07 - "011111100", -- | ###### | 08 - "011111100", -- | ###### | 09 - "011111100", -- | ###### | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 160 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "000000000", -- | | 05 - "000000000", -- | | 06 - "000000000", -- | | 07 - "000000000", -- | | 08 - "000000000", -- | | 09 - "000000000", -- | | 10 - "000000000", -- | | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 161 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "000000000", -- | | 05 - "000110000", -- | ## | 06 - "000110000", -- | ## | 07 - "000000000", -- | | 08 - "000110000", -- | ## | 09 - "000110000", -- | ## | 10 - "001111000", -- | #### | 11 - "001111000", -- | #### | 12 - "001111000", -- | #### | 13 - "000110000", -- | ## | 14 - "000000000", -- | | 15 - -- ASCII 162 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000110000", -- | ## | 03 - "000110000", -- | ## | 04 - "001111000", -- | #### | 05 - "011001100", -- | ## ## | 06 - "011000000", -- | ## | 07 - "011000000", -- | ## | 08 - "011001100", -- | ## ## | 09 - "001111000", -- | #### | 10 - "000110000", -- | ## | 11 - "000110000", -- | ## | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 163 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "001111000", -- | #### | 03 - "011001100", -- | ## ## | 04 - "011000000", -- | ## | 05 - "011000000", -- | ## | 06 - "111111000", -- |###### | 07 - "011000000", -- | ## | 08 - "011000000", -- | ## | 09 - "110000000", -- |## | 10 - "111111100", -- |####### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 164 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "011001100", -- | ## ## | 04 - "001111000", -- | #### | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "001111000", -- | #### | 08 - "011001100", -- | ## ## | 09 - "000000000", -- | | 10 - "000000000", -- | | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 165 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011001100", -- | ## ## | 03 - "011001100", -- | ## ## | 04 - "011001100", -- | ## ## | 05 - "001111000", -- | #### | 06 - "011111100", -- | ###### | 07 - "000110000", -- | ## | 08 - "011111100", -- | ###### | 09 - "000110000", -- | ## | 10 - "000110000", -- | ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 166 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000110000", -- | ## | 03 - "000110000", -- | ## | 04 - "000110000", -- | ## | 05 - "000110000", -- | ## | 06 - "000110000", -- | ## | 07 - "000000000", -- | | 08 - "000000000", -- | | 09 - "000110000", -- | ## | 10 - "000110000", -- | ## | 11 - "000110000", -- | ## | 12 - "000110000", -- | ## | 13 - "000110000", -- | ## | 14 - "000000000", -- | | 15 - -- ASCII 167 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "001111000", -- | #### | 03 - "011001100", -- | ## ## | 04 - "011000000", -- | ## | 05 - "001110000", -- | ### | 06 - "001111000", -- | #### | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "001111000", -- | #### | 10 - "000111000", -- | ### | 11 - "000001100", -- | ## | 12 - "011001100", -- | ## ## | 13 - "001111000", -- | #### | 14 - "000000000", -- | | 15 - -- ASCII 168 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "011001100", -- | ## ## | 02 - "011001100", -- | ## ## | 03 - "000000000", -- | | 04 - "000000000", -- | | 05 - "000000000", -- | | 06 - "000000000", -- | | 07 - "000000000", -- | | 08 - "000000000", -- | | 09 - "000000000", -- | | 10 - "000000000", -- | | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 169 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "110000110", -- |## ## | 04 - "100110010", -- |# ## # | 05 - "101001010", -- |# # # # | 06 - "101000010", -- |# # # | 07 - "101001010", -- |# # # # | 08 - "100110010", -- |# ## # | 09 - "110000110", -- |## ## | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 170 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "001111000", -- | #### | 03 - "000001100", -- | ## | 04 - "001111100", -- | ##### | 05 - "011001100", -- | ## ## | 06 - "001111100", -- | ##### | 07 - "000000000", -- | | 08 - "011111100", -- | ###### | 09 - "000000000", -- | | 10 - "000000000", -- | | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 171 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "000000000", -- | | 05 - "000000000", -- | | 06 - "001100110", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "110011000", -- |## ## | 09 - "011001100", -- | ## ## | 10 - "001100110", -- | ## ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 172 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "000000000", -- | | 05 - "000000000", -- | | 06 - "011111100", -- | ###### | 07 - "000001100", -- | ## | 08 - "000001100", -- | ## | 09 - "000000000", -- | | 10 - "000000000", -- | | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 173 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "000000000", -- | | 05 - "000000000", -- | | 06 - "011111100", -- | ###### | 07 - "000000000", -- | | 08 - "000000000", -- | | 09 - "000000000", -- | | 10 - "000000000", -- | | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 174 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "110000110", -- |## ## | 04 - "101110010", -- |# ### # | 05 - "101001010", -- |# # # # | 06 - "101001010", -- |# # # # | 07 - "101110010", -- |# ### # | 08 - "101001010", -- |# # # # | 09 - "110000110", -- |## ## | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 175 --------------- - "111111110", -- |######## | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "000000000", -- | | 05 - "000000000", -- | | 06 - "000000000", -- | | 07 - "000000000", -- | | 08 - "000000000", -- | | 09 - "000000000", -- | | 10 - "000000000", -- | | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 176 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "001111000", -- | #### | 02 - "011001100", -- | ## ## | 03 - "011001100", -- | ## ## | 04 - "001111000", -- | #### | 05 - "000000000", -- | | 06 - "000000000", -- | | 07 - "000000000", -- | | 08 - "000000000", -- | | 09 - "000000000", -- | | 10 - "000000000", -- | | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 177 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "000110000", -- | ## | 05 - "000110000", -- | ## | 06 - "011111100", -- | ###### | 07 - "000110000", -- | ## | 08 - "000110000", -- | ## | 09 - "000000000", -- | | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 178 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "001110000", -- | ### | 03 - "000011000", -- | ## | 04 - "000110000", -- | ## | 05 - "001100000", -- | ## | 06 - "001111000", -- | #### | 07 - "000000000", -- | | 08 - "000000000", -- | | 09 - "000000000", -- | | 10 - "000000000", -- | | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 179 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "001110000", -- | ### | 03 - "000011000", -- | ## | 04 - "000110000", -- | ## | 05 - "000011000", -- | ## | 06 - "001110000", -- | ### | 07 - "000000000", -- | | 08 - "000000000", -- | | 09 - "000000000", -- | | 10 - "000000000", -- | | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 180 --------------- - "000000000", -- | | 00 - "000111000", -- | ### | 01 - "000110000", -- | ## | 02 - "001100000", -- | ## | 03 - "000000000", -- | | 04 - "000000000", -- | | 05 - "000000000", -- | | 06 - "000000000", -- | | 07 - "000000000", -- | | 08 - "000000000", -- | | 09 - "000000000", -- | | 10 - "000000000", -- | | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 181 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "011110110", -- | #### ## | 11 - "011000000", -- | ## | 12 - "011000000", -- | ## | 13 - "110000000", -- |## | 14 - "000000000", -- | | 15 - -- ASCII 182 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000111110", -- | ##### | 03 - "001111100", -- | ##### | 04 - "011111100", -- | ###### | 05 - "011111100", -- | ###### | 06 - "011111100", -- | ###### | 07 - "001111100", -- | ##### | 08 - "000111100", -- | #### | 09 - "000001100", -- | ## | 10 - "000001100", -- | ## | 11 - "000001100", -- | ## | 12 - "000001100", -- | ## | 13 - "000001100", -- | ## | 14 - "000000000", -- | | 15 - -- ASCII 183 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "000000000", -- | | 05 - "000111000", -- | ### | 06 - "000111000", -- | ### | 07 - "000000000", -- | | 08 - "000000000", -- | | 09 - "000000000", -- | | 10 - "000000000", -- | | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 184 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "000000000", -- | | 05 - "000000000", -- | | 06 - "000000000", -- | | 07 - "000000000", -- | | 08 - "000000000", -- | | 09 - "000000000", -- | | 10 - "000000000", -- | | 11 - "000110000", -- | ## | 12 - "000011000", -- | ## | 13 - "001110000", -- | ### | 14 - "000000000", -- | | 15 - -- ASCII 185 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000110000", -- | ## | 03 - "001110000", -- | ### | 04 - "000110000", -- | ## | 05 - "000110000", -- | ## | 06 - "000110000", -- | ## | 07 - "000000000", -- | | 08 - "000000000", -- | | 09 - "000000000", -- | | 10 - "000000000", -- | | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 186 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "001111000", -- | #### | 03 - "011001100", -- | ## ## | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "001111000", -- | #### | 07 - "000000000", -- | | 08 - "011111100", -- | ###### | 09 - "000000000", -- | | 10 - "000000000", -- | | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 187 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "000000000", -- | | 05 - "000000000", -- | | 06 - "110011000", -- |## ## | 07 - "011001100", -- | ## ## | 08 - "001100110", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "110011000", -- |## ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 188 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "011000000", -- | ## | 02 - "111000000", -- |### | 03 - "011000110", -- | ## ## | 04 - "011001100", -- | ## ## | 05 - "011011000", -- | ## ## | 06 - "000110000", -- | ## | 07 - "001101110", -- | ## ### | 08 - "011011110", -- | ## #### | 09 - "110110110", -- |## ## ## | 10 - "000111110", -- | ##### | 11 - "000000110", -- | ## | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 189 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "011000000", -- | ## | 02 - "111000000", -- |### | 03 - "011000110", -- | ## ## | 04 - "011001100", -- | ## ## | 05 - "011011000", -- | ## ## | 06 - "000110000", -- | ## | 07 - "001111100", -- | ##### | 08 - "011000110", -- | ## ## | 09 - "110001100", -- |## ## | 10 - "000011000", -- | ## | 11 - "000011110", -- | #### | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 190 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "111000000", -- |### | 02 - "001100000", -- | ## | 03 - "011000110", -- | ## ## | 04 - "001101100", -- | ## ## | 05 - "111011000", -- |### ## | 06 - "000110000", -- | ## | 07 - "001101110", -- | ## ### | 08 - "011011110", -- | ## #### | 09 - "110110110", -- |## ## ## | 10 - "000111110", -- | ##### | 11 - "000000110", -- | ## | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 191 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "000000000", -- | | 05 - "000110000", -- | ## | 06 - "000110000", -- | ## | 07 - "000000000", -- | | 08 - "000110000", -- | ## | 09 - "000110000", -- | ## | 10 - "001100000", -- | ## | 11 - "011001100", -- | ## ## | 12 - "011001100", -- | ## ## | 13 - "001111000", -- | #### | 14 - "000000000", -- | | 15 - -- ASCII 192 --------------- - "001100000", -- | ## | 00 - "000110000", -- | ## | 01 - "000000000", -- | | 02 - "000110000", -- | ## | 03 - "001111000", -- | #### | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011111100", -- | ###### | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "011001100", -- | ## ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 193 --------------- - "000011000", -- | ## | 00 - "000110000", -- | ## | 01 - "000000000", -- | | 02 - "000110000", -- | ## | 03 - "001111000", -- | #### | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011111100", -- | ###### | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "011001100", -- | ## ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 194 --------------- - "001111000", -- | #### | 00 - "011001100", -- | ## ## | 01 - "000000000", -- | | 02 - "000110000", -- | ## | 03 - "001111000", -- | #### | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011111100", -- | ###### | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "011001100", -- | ## ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 195 --------------- - "001110110", -- | ### ## | 00 - "011011100", -- | ## ### | 01 - "000000000", -- | | 02 - "000110000", -- | ## | 03 - "001111000", -- | #### | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011111100", -- | ###### | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "011001100", -- | ## ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 196 --------------- - "011001100", -- | ## ## | 00 - "011001100", -- | ## ## | 01 - "000000000", -- | | 02 - "000110000", -- | ## | 03 - "001111000", -- | #### | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011111100", -- | ###### | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "011001100", -- | ## ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 197 --------------- - "001111000", -- | #### | 00 - "011001100", -- | ## ## | 01 - "001111000", -- | #### | 02 - "000110000", -- | ## | 03 - "001111000", -- | #### | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011111100", -- | ###### | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "011001100", -- | ## ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 198 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000011110", -- | #### | 03 - "000111000", -- | ### | 04 - "001111000", -- | #### | 05 - "011011000", -- | ## ## | 06 - "011011110", -- | ## #### | 07 - "011111000", -- | ##### | 08 - "011011000", -- | ## ## | 09 - "011011000", -- | ## ## | 10 - "011011110", -- | ## #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 199 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "001111000", -- | #### | 03 - "011001100", -- | ## ## | 04 - "011001100", -- | ## ## | 05 - "011000000", -- | ## | 06 - "011000000", -- | ## | 07 - "011000000", -- | ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111000", -- | #### | 11 - "000110000", -- | ## | 12 - "000011000", -- | ## | 13 - "001110000", -- | ### | 14 - "000000000", -- | | 15 - -- ASCII 200 --------------- - "001100000", -- | ## | 00 - "000110000", -- | ## | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "011000000", -- | ## | 04 - "011000000", -- | ## | 05 - "011000000", -- | ## | 06 - "011111000", -- | ##### | 07 - "011000000", -- | ## | 08 - "011000000", -- | ## | 09 - "011000000", -- | ## | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 201 --------------- - "000011000", -- | ## | 00 - "000110000", -- | ## | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "011000000", -- | ## | 04 - "011000000", -- | ## | 05 - "011000000", -- | ## | 06 - "011111000", -- | ##### | 07 - "011000000", -- | ## | 08 - "011000000", -- | ## | 09 - "011000000", -- | ## | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 202 --------------- - "001111000", -- | #### | 00 - "011001100", -- | ## ## | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "011000000", -- | ## | 04 - "011000000", -- | ## | 05 - "011000000", -- | ## | 06 - "011111000", -- | ##### | 07 - "011000000", -- | ## | 08 - "011000000", -- | ## | 09 - "011000000", -- | ## | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 203 --------------- - "011001100", -- | ## ## | 00 - "011001100", -- | ## ## | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "011000000", -- | ## | 04 - "011000000", -- | ## | 05 - "011000000", -- | ## | 06 - "011111000", -- | ##### | 07 - "011000000", -- | ## | 08 - "011000000", -- | ## | 09 - "011000000", -- | ## | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 204 --------------- - "001100000", -- | ## | 00 - "000110000", -- | ## | 01 - "000000000", -- | | 02 - "001111000", -- | #### | 03 - "000110000", -- | ## | 04 - "000110000", -- | ## | 05 - "000110000", -- | ## | 06 - "000110000", -- | ## | 07 - "000110000", -- | ## | 08 - "000110000", -- | ## | 09 - "000110000", -- | ## | 10 - "001111000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 205 --------------- - "000011000", -- | ## | 00 - "000110000", -- | ## | 01 - "000000000", -- | | 02 - "001111000", -- | #### | 03 - "000110000", -- | ## | 04 - "000110000", -- | ## | 05 - "000110000", -- | ## | 06 - "000110000", -- | ## | 07 - "000110000", -- | ## | 08 - "000110000", -- | ## | 09 - "000110000", -- | ## | 10 - "001111000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 206 --------------- - "001111000", -- | #### | 00 - "011001100", -- | ## ## | 01 - "000000000", -- | | 02 - "001111000", -- | #### | 03 - "000110000", -- | ## | 04 - "000110000", -- | ## | 05 - "000110000", -- | ## | 06 - "000110000", -- | ## | 07 - "000110000", -- | ## | 08 - "000110000", -- | ## | 09 - "000110000", -- | ## | 10 - "001111000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 207 --------------- - "011001100", -- | ## ## | 00 - "011001100", -- | ## ## | 01 - "000000000", -- | | 02 - "001111000", -- | #### | 03 - "000110000", -- | ## | 04 - "000110000", -- | ## | 05 - "000110000", -- | ## | 06 - "000110000", -- | ## | 07 - "000110000", -- | ## | 08 - "000110000", -- | ## | 09 - "000110000", -- | ## | 10 - "001111000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 208 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011110000", -- | #### | 03 - "011011000", -- | ## ## | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "111101100", -- |#### ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011011000", -- | ## ## | 10 - "011110000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 209 --------------- - "001110110", -- | ### ## | 00 - "011011100", -- | ## ### | 01 - "000000000", -- | | 02 - "011000110", -- | ## ## | 03 - "011000110", -- | ## ## | 04 - "011100110", -- | ### ## | 05 - "011110110", -- | #### ## | 06 - "011011110", -- | ## #### | 07 - "011001110", -- | ## ### | 08 - "011000110", -- | ## ## | 09 - "011000110", -- | ## ## | 10 - "011000110", -- | ## ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 210 --------------- - "001100000", -- | ## | 00 - "000110000", -- | ## | 01 - "000000000", -- | | 02 - "001111000", -- | #### | 03 - "011001100", -- | ## ## | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 211 --------------- - "000011000", -- | ## | 00 - "000110000", -- | ## | 01 - "000000000", -- | | 02 - "001111000", -- | #### | 03 - "011001100", -- | ## ## | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 212 --------------- - "001111000", -- | #### | 00 - "011001100", -- | ## ## | 01 - "000000000", -- | | 02 - "001111000", -- | #### | 03 - "011001100", -- | ## ## | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 213 --------------- - "001110110", -- | ### ## | 00 - "011011100", -- | ## ### | 01 - "000000000", -- | | 02 - "001111000", -- | #### | 03 - "011001100", -- | ## ## | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 214 --------------- - "011001100", -- | ## ## | 00 - "011001100", -- | ## ## | 01 - "000000000", -- | | 02 - "001111000", -- | #### | 03 - "011001100", -- | ## ## | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 215 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "010000100", -- | # # | 04 - "011001100", -- | ## ## | 05 - "001111000", -- | #### | 06 - "000110000", -- | ## | 07 - "001111000", -- | #### | 08 - "011001100", -- | ## ## | 09 - "010000100", -- | # # | 10 - "000000000", -- | | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 216 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "001111100", -- | ##### | 03 - "011001100", -- | ## ## | 04 - "011011100", -- | ## ### | 05 - "011011100", -- | ## ### | 06 - "011111100", -- | ###### | 07 - "011101100", -- | ### ## | 08 - "011101100", -- | ### ## | 09 - "011001100", -- | ## ## | 10 - "011111000", -- | ##### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 217 --------------- - "001100000", -- | ## | 00 - "000110000", -- | ## | 01 - "000000000", -- | | 02 - "011001100", -- | ## ## | 03 - "011001100", -- | ## ## | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 218 --------------- - "000011000", -- | ## | 00 - "000110000", -- | ## | 01 - "000000000", -- | | 02 - "011001100", -- | ## ## | 03 - "011001100", -- | ## ## | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 219 --------------- - "001111000", -- | #### | 00 - "011001100", -- | ## ## | 01 - "000000000", -- | | 02 - "011001100", -- | ## ## | 03 - "011001100", -- | ## ## | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 220 --------------- - "011001100", -- | ## ## | 00 - "011001100", -- | ## ## | 01 - "000000000", -- | | 02 - "011001100", -- | ## ## | 03 - "011001100", -- | ## ## | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 221 --------------- - "000011000", -- | ## | 00 - "000110000", -- | ## | 01 - "000000000", -- | | 02 - "011001100", -- | ## ## | 03 - "011001100", -- | ## ## | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "001111000", -- | #### | 07 - "000110000", -- | ## | 08 - "000110000", -- | ## | 09 - "000110000", -- | ## | 10 - "000110000", -- | ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 222 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011000000", -- | ## | 03 - "011000000", -- | ## | 04 - "011111000", -- | ##### | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011111000", -- | ##### | 09 - "011000000", -- | ## | 10 - "011000000", -- | ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 223 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "001110000", -- | ### | 03 - "011011000", -- | ## ## | 04 - "011011000", -- | ## ## | 05 - "011011000", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "011011000", -- | ## ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 224 --------------- - "000000000", -- | | 00 - "011100000", -- | ### | 01 - "001100000", -- | ## | 02 - "000110000", -- | ## | 03 - "000000000", -- | | 04 - "001111000", -- | #### | 05 - "000001100", -- | ## | 06 - "000001100", -- | ## | 07 - "001111100", -- | ##### | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111100", -- | ##### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 225 --------------- - "000000000", -- | | 00 - "000011100", -- | ### | 01 - "000011000", -- | ## | 02 - "000110000", -- | ## | 03 - "000000000", -- | | 04 - "001111000", -- | #### | 05 - "000001100", -- | ## | 06 - "000001100", -- | ## | 07 - "001111100", -- | ##### | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111100", -- | ##### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 226 --------------- - "000000000", -- | | 00 - "000110000", -- | ## | 01 - "001111000", -- | #### | 02 - "011001100", -- | ## ## | 03 - "000000000", -- | | 04 - "001111000", -- | #### | 05 - "000001100", -- | ## | 06 - "000001100", -- | ## | 07 - "001111100", -- | ##### | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111100", -- | ##### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 227 --------------- - "000000000", -- | | 00 - "011100010", -- | ### # | 01 - "110110110", -- |## ## ## | 02 - "100011100", -- |# ### | 03 - "000000000", -- | | 04 - "001111000", -- | #### | 05 - "000001100", -- | ## | 06 - "000001100", -- | ## | 07 - "001111100", -- | ##### | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111100", -- | ##### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 228 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "011001100", -- | ## ## | 02 - "011001100", -- | ## ## | 03 - "000000000", -- | | 04 - "001111000", -- | #### | 05 - "000001100", -- | ## | 06 - "000001100", -- | ## | 07 - "001111100", -- | ##### | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111100", -- | ##### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 229 --------------- - "000000000", -- | | 00 - "001111000", -- | #### | 01 - "011001100", -- | ## ## | 02 - "001111000", -- | #### | 03 - "000000000", -- | | 04 - "001111000", -- | #### | 05 - "000001100", -- | ## | 06 - "000001100", -- | ## | 07 - "001111100", -- | ##### | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111100", -- | ##### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 230 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "011011100", -- | ## ### | 05 - "000110110", -- | ## ## | 06 - "000110110", -- | ## ## | 07 - "011111110", -- | ####### | 08 - "110110000", -- |## ## | 09 - "110110000", -- |## ## | 10 - "011101110", -- | ### ### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 231 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "001111000", -- | #### | 05 - "011001100", -- | ## ## | 06 - "011000000", -- | ## | 07 - "011000000", -- | ## | 08 - "011000000", -- | ## | 09 - "011001100", -- | ## ## | 10 - "001111000", -- | #### | 11 - "000110000", -- | ## | 12 - "000011000", -- | ## | 13 - "001110000", -- | ### | 14 - "000000000", -- | | 15 - -- ASCII 232 --------------- - "000000000", -- | | 00 - "011100000", -- | ### | 01 - "001100000", -- | ## | 02 - "000110000", -- | ## | 03 - "000000000", -- | | 04 - "001111000", -- | #### | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011111100", -- | ###### | 08 - "011000000", -- | ## | 09 - "011000000", -- | ## | 10 - "001111000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 233 --------------- - "000000000", -- | | 00 - "000011100", -- | ### | 01 - "000011000", -- | ## | 02 - "000110000", -- | ## | 03 - "000000000", -- | | 04 - "001111000", -- | #### | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011111100", -- | ###### | 08 - "011000000", -- | ## | 09 - "011000000", -- | ## | 10 - "001111000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 234 --------------- - "000000000", -- | | 00 - "000110000", -- | ## | 01 - "001111000", -- | #### | 02 - "011001100", -- | ## ## | 03 - "000000000", -- | | 04 - "001111000", -- | #### | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011111100", -- | ###### | 08 - "011000000", -- | ## | 09 - "011000000", -- | ## | 10 - "001111000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 235 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "011001100", -- | ## ## | 02 - "011001100", -- | ## ## | 03 - "000000000", -- | | 04 - "001111000", -- | #### | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011111100", -- | ###### | 08 - "011000000", -- | ## | 09 - "011000000", -- | ## | 10 - "001111000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 236 --------------- - "000000000", -- | | 00 - "011100000", -- | ### | 01 - "001100000", -- | ## | 02 - "000110000", -- | ## | 03 - "000000000", -- | | 04 - "011110000", -- | #### | 05 - "000110000", -- | ## | 06 - "000110000", -- | ## | 07 - "000110000", -- | ## | 08 - "000110000", -- | ## | 09 - "000110000", -- | ## | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 237 --------------- - "000000000", -- | | 00 - "000011100", -- | ### | 01 - "000011000", -- | ## | 02 - "000110000", -- | ## | 03 - "000000000", -- | | 04 - "011110000", -- | #### | 05 - "000110000", -- | ## | 06 - "000110000", -- | ## | 07 - "000110000", -- | ## | 08 - "000110000", -- | ## | 09 - "000110000", -- | ## | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 238 --------------- - "000000000", -- | | 00 - "000110000", -- | ## | 01 - "001111000", -- | #### | 02 - "011001100", -- | ## ## | 03 - "000000000", -- | | 04 - "011110000", -- | #### | 05 - "000110000", -- | ## | 06 - "000110000", -- | ## | 07 - "000110000", -- | ## | 08 - "000110000", -- | ## | 09 - "000110000", -- | ## | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 239 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "011001100", -- | ## ## | 02 - "011001100", -- | ## ## | 03 - "000000000", -- | | 04 - "011110000", -- | #### | 05 - "000110000", -- | ## | 06 - "000110000", -- | ## | 07 - "000110000", -- | ## | 08 - "000110000", -- | ## | 09 - "000110000", -- | ## | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 240 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "001101100", -- | ## ## | 03 - "000110000", -- | ## | 04 - "011011000", -- | ## ## | 05 - "000111100", -- | #### | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 241 --------------- - "000000000", -- | | 00 - "011100010", -- | ### # | 01 - "110110110", -- |## ## ## | 02 - "100011100", -- |# ### | 03 - "000000000", -- | | 04 - "011111000", -- | ##### | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "011001100", -- | ## ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 242 --------------- - "000000000", -- | | 00 - "011100000", -- | ### | 01 - "001100000", -- | ## | 02 - "000110000", -- | ## | 03 - "000000000", -- | | 04 - "001111000", -- | #### | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 243 --------------- - "000000000", -- | | 00 - "000011100", -- | ### | 01 - "000011000", -- | ## | 02 - "000110000", -- | ## | 03 - "000000000", -- | | 04 - "001111000", -- | #### | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 244 --------------- - "000000000", -- | | 00 - "000110000", -- | ## | 01 - "001111000", -- | #### | 02 - "011001100", -- | ## ## | 03 - "000000000", -- | | 04 - "001111000", -- | #### | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 245 --------------- - "000000000", -- | | 00 - "011100010", -- | ### # | 01 - "110110110", -- |## ## ## | 02 - "100011100", -- |# ### | 03 - "000000000", -- | | 04 - "001111000", -- | #### | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 246 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "011001100", -- | ## ## | 02 - "011001100", -- | ## ## | 03 - "000000000", -- | | 04 - "001111000", -- | #### | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 247 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000110000", -- | ## | 04 - "000110000", -- | ## | 05 - "000000000", -- | | 06 - "011111100", -- | ###### | 07 - "000000000", -- | | 08 - "000110000", -- | ## | 09 - "000110000", -- | ## | 10 - "000000000", -- | | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 248 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "001111100", -- | ##### | 05 - "011001100", -- | ## ## | 06 - "011011100", -- | ## ### | 07 - "011111100", -- | ###### | 08 - "011101100", -- | ### ## | 09 - "011001100", -- | ## ## | 10 - "011111000", -- | ##### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 249 --------------- - "000000000", -- | | 00 - "011100000", -- | ### | 01 - "001100000", -- | ## | 02 - "000110000", -- | ## | 03 - "000000000", -- | | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111100", -- | ##### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 250 --------------- - "000000000", -- | | 00 - "000011100", -- | ### | 01 - "000011000", -- | ## | 02 - "000110000", -- | ## | 03 - "000000000", -- | | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111100", -- | ##### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 251 --------------- - "000000000", -- | | 00 - "000110000", -- | ## | 01 - "001111000", -- | #### | 02 - "011001100", -- | ## ## | 03 - "000000000", -- | | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111100", -- | ##### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 252 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "011001100", -- | ## ## | 02 - "011001100", -- | ## ## | 03 - "000000000", -- | | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111100", -- | ##### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 253 --------------- - "000000000", -- | | 00 - "000011100", -- | ### | 01 - "000011000", -- | ## | 02 - "000110000", -- | ## | 03 - "000000000", -- | | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111000", -- | #### | 11 - "000011000", -- | ## | 12 - "000110000", -- | ## | 13 - "111100000", -- |#### | 14 - "000000000", -- | | 15 - -- ASCII 254 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011000000", -- | ## | 03 - "011000000", -- | ## | 04 - "011000000", -- | ## | 05 - "011111000", -- | ##### | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "011111000", -- | ##### | 11 - "011000000", -- | ## | 12 - "011000000", -- | ## | 13 - "011000000", -- | ## | 14 - "000000000", -- | | 15 - -- ASCII 255 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "011001100", -- | ## ## | 02 - "011001100", -- | ## ## | 03 - "000000000", -- | | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111000", -- | #### | 11 - "000011000", -- | ## | 12 - "000110000", -- | ## | 13 - "111100000", -- |#### | 14 - "000000000", -- | | 15 - -- Padding --------------- - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000" -- Padded - ); -begin - - p_rom : process - begin - wait until rising_edge(CLK); - DATA <= ROM(to_integer(unsigned(ADDR))); - end process; - -end RTL; - diff --git a/lib/VGA_ctrl/src/fonts/char_rom_system_16x16.vhd b/lib/VGA_ctrl/src/fonts/char_rom_system_16x16.vhd deleted file mode 100644 index d50d36f..0000000 --- a/lib/VGA_ctrl/src/fonts/char_rom_system_16x16.vhd +++ /dev/null @@ -1,4382 +0,0 @@ -library ieee; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity char_rom is - port - ( - CLK : in std_logic; - ADDR : in unsigned(11 downto 0); - DATA : out unsigned(15 downto 0) - ); -end; - -architecture RTL of char_rom is - - - type ROM_ARRAY is array(0 to 4095) of unsigned(15 downto 0); - constant ROM : ROM_ARRAY := - ( - -- ASCII 032 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 033 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0110000000000000", -- | ## | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0000000000000000", -- | | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 034 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "1100110000000000", -- |## ## | 03 - "1100110000000000", -- |## ## | 04 - "1100110000000000", -- |## ## | 05 - "1100110000000000", -- |## ## | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 035 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0011011000000000", -- | ## ## | 03 - "0011011000000000", -- | ## ## | 04 - "0111111100000000", -- | ####### | 05 - "0011011000000000", -- | ## ## | 06 - "0011011000000000", -- | ## ## | 07 - "0110110000000000", -- | ## ## | 08 - "0110110000000000", -- | ## ## | 09 - "1111111000000000", -- |####### | 10 - "0110110000000000", -- | ## ## | 11 - "0110110000000000", -- | ## ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 036 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0001100000000000", -- | ## | 03 - "0011110000000000", -- | #### | 04 - "0110011000000000", -- | ## ## | 05 - "0110011000000000", -- | ## ## | 06 - "0110000000000000", -- | ## | 07 - "0011110000000000", -- | #### | 08 - "0000011000000000", -- | ## | 09 - "0000011000000000", -- | ## | 10 - "0110011000000000", -- | ## ## | 11 - "0011110000000000", -- | #### | 12 - "0001100000000000", -- | ## | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 037 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0111000001100000", -- | ### ## | 03 - "1101100011000000", -- |## ## ## | 04 - "1101100110000000", -- |## ## ## | 05 - "1101101100000000", -- |## ## ## | 06 - "0111011000000000", -- | ### ## | 07 - "0000110111000000", -- | ## ### | 08 - "0001101101100000", -- | ## ## ## | 09 - "0011001101100000", -- | ## ## ## | 10 - "0110001101100000", -- | ## ## ## | 11 - "1100000111000000", -- |## ### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 038 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "1111000000000000", -- |#### | 14 - "0000000000000000", -- | | 15 - -- ASCII 039 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0110000000000000", -- | ## | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 040 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0011000000000000", -- | ## | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0110000000000000", -- | ## | 13 - "0110000000000000", -- | ## | 14 - "0011000000000000", -- | ## | 15 - -- ASCII 041 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "1100000000000000", -- |## | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0110000000000000", -- | ## | 13 - "0110000000000000", -- | ## | 14 - "1100000000000000", -- |## | 15 - -- ASCII 042 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0011000000000000", -- | ## | 03 - "1111110000000000", -- |###### | 04 - "0011000000000000", -- | ## | 05 - "0111100000000000", -- | #### | 06 - "0100100000000000", -- | # # | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 043 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0001100000000000", -- | ## | 05 - "0001100000000000", -- | ## | 06 - "0001100000000000", -- | ## | 07 - "0111111000000000", -- | ###### | 08 - "0001100000000000", -- | ## | 09 - "0001100000000000", -- | ## | 10 - "0001100000000000", -- | ## | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 044 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "1100000000000000", -- |## | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 045 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "1111000000000000", -- |#### | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 046 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 047 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0011000000000000", -- | ## | 03 - "0011000000000000", -- | ## | 04 - "0011000000000000", -- | ## | 05 - "0011000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "1100000000000000", -- |## | 11 - "1100000000000000", -- |## | 12 - "1100000000000000", -- |## | 13 - "1100000000000000", -- |## | 14 - "0000000000000000", -- | | 15 - -- ASCII 048 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0011110000000000", -- | #### | 03 - "0110011000000000", -- | ## ## | 04 - "0110011000000000", -- | ## ## | 05 - "0110011000000000", -- | ## ## | 06 - "0110011000000000", -- | ## ## | 07 - "0110011000000000", -- | ## ## | 08 - "0110011000000000", -- | ## ## | 09 - "0110011000000000", -- | ## ## | 10 - "0110011000000000", -- | ## ## | 11 - "0011110000000000", -- | #### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 049 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0001100000000000", -- | ## | 03 - "0111100000000000", -- | #### | 04 - "0001100000000000", -- | ## | 05 - "0001100000000000", -- | ## | 06 - "0001100000000000", -- | ## | 07 - "0001100000000000", -- | ## | 08 - "0001100000000000", -- | ## | 09 - "0001100000000000", -- | ## | 10 - "0001100000000000", -- | ## | 11 - "0001100000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 050 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0011110000000000", -- | #### | 03 - "0110011000000000", -- | ## ## | 04 - "0110011000000000", -- | ## ## | 05 - "0000011000000000", -- | ## | 06 - "0000110000000000", -- | ## | 07 - "0001100000000000", -- | ## | 08 - "0011000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0111111000000000", -- | ###### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 051 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0011110000000000", -- | #### | 03 - "0110011000000000", -- | ## ## | 04 - "0000011000000000", -- | ## | 05 - "0000011000000000", -- | ## | 06 - "0001110000000000", -- | ### | 07 - "0000011000000000", -- | ## | 08 - "0000011000000000", -- | ## | 09 - "0000011000000000", -- | ## | 10 - "0110011000000000", -- | ## ## | 11 - "0011110000000000", -- | #### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 052 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000011000000000", -- | ## | 03 - "0000111000000000", -- | ### | 04 - "0001111000000000", -- | #### | 05 - "0001111000000000", -- | #### | 06 - "0011011000000000", -- | ## ## | 07 - "0011011000000000", -- | ## ## | 08 - "0110011000000000", -- | ## ## | 09 - "0111111000000000", -- | ###### | 10 - "0000011000000000", -- | ## | 11 - "0000011000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 053 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0111111000000000", -- | ###### | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0111110000000000", -- | ##### | 07 - "0110011000000000", -- | ## ## | 08 - "0000011000000000", -- | ## | 09 - "0000011000000000", -- | ## | 10 - "0110011000000000", -- | ## ## | 11 - "0011110000000000", -- | #### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 054 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0011110000000000", -- | #### | 03 - "0110011000000000", -- | ## ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0111110000000000", -- | ##### | 07 - "0110011000000000", -- | ## ## | 08 - "0110011000000000", -- | ## ## | 09 - "0110011000000000", -- | ## ## | 10 - "0110011000000000", -- | ## ## | 11 - "0011110000000000", -- | #### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 055 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0111111000000000", -- | ###### | 03 - "0000011000000000", -- | ## | 04 - "0000110000000000", -- | ## | 05 - "0000110000000000", -- | ## | 06 - "0001100000000000", -- | ## | 07 - "0001100000000000", -- | ## | 08 - "0001100000000000", -- | ## | 09 - "0011000000000000", -- | ## | 10 - "0011000000000000", -- | ## | 11 - "0011000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 056 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0011110000000000", -- | #### | 03 - "0110011000000000", -- | ## ## | 04 - "0110011000000000", -- | ## ## | 05 - "0110011000000000", -- | ## ## | 06 - "0011110000000000", -- | #### | 07 - "0110011000000000", -- | ## ## | 08 - "0110011000000000", -- | ## ## | 09 - "0110011000000000", -- | ## ## | 10 - "0110011000000000", -- | ## ## | 11 - "0011110000000000", -- | #### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 057 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0011110000000000", -- | #### | 03 - "0110011000000000", -- | ## ## | 04 - "0110011000000000", -- | ## ## | 05 - "0110011000000000", -- | ## ## | 06 - "0110011000000000", -- | ## ## | 07 - "0011111000000000", -- | ##### | 08 - "0000011000000000", -- | ## | 09 - "0000011000000000", -- | ## | 10 - "0110011000000000", -- | ## ## | 11 - "0011110000000000", -- | #### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 058 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 059 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "1100000000000000", -- |## | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 060 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000011000000000", -- | ## | 04 - "0000110000000000", -- | ## | 05 - "0001100000000000", -- | ## | 06 - "0011000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0011000000000000", -- | ## | 09 - "0001100000000000", -- | ## | 10 - "0000110000000000", -- | ## | 11 - "0000011000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 061 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0111111000000000", -- | ###### | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0111111000000000", -- | ###### | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 062 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0110000000000000", -- | ## | 04 - "0011000000000000", -- | ## | 05 - "0001100000000000", -- | ## | 06 - "0000110000000000", -- | ## | 07 - "0000011000000000", -- | ## | 08 - "0000110000000000", -- | ## | 09 - "0001100000000000", -- | ## | 10 - "0011000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 063 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0011110000000000", -- | #### | 03 - "0110011000000000", -- | ## ## | 04 - "0110011000000000", -- | ## ## | 05 - "0000011000000000", -- | ## | 06 - "0000110000000000", -- | ## | 07 - "0001100000000000", -- | ## | 08 - "0001100000000000", -- | ## | 09 - "0000000000000000", -- | | 10 - "0001100000000000", -- | ## | 11 - "0001100000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 064 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000011110000000", -- | #### | 02 - "0001110011100000", -- | ### ### | 03 - "0011000000110000", -- | ## ## | 04 - "0011001110110000", -- | ## ### ## | 05 - "0110011011011000", -- | ## ## ## ## | 06 - "0110011011011000", -- | ## ## ## ## | 07 - "0110110011011000", -- | ## ## ## ## | 08 - "0110110110011000", -- | ## ## ## ## | 09 - "0110110110011000", -- | ## ## ## ## | 10 - "0011011011110000", -- | ## ## #### | 11 - "0011000000000000", -- | ## | 12 - "0001110001110000", -- | ### ### | 13 - "0000011111000000", -- | ##### | 14 - "0000000000000000", -- | | 15 - -- ASCII 065 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0001100000000000", -- | ## | 03 - "0001100000000000", -- | ## | 04 - "0011110000000000", -- | #### | 05 - "0011110000000000", -- | #### | 06 - "0010010000000000", -- | # # | 07 - "0110011000000000", -- | ## ## | 08 - "0110011000000000", -- | ## ## | 09 - "0111111000000000", -- | ###### | 10 - "1100001100000000", -- |## ## | 11 - "1100001100000000", -- |## ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 066 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0111111100000000", -- | ####### | 03 - "0110000110000000", -- | ## ## | 04 - "0110000110000000", -- | ## ## | 05 - "0110000110000000", -- | ## ## | 06 - "0111111100000000", -- | ####### | 07 - "0110000110000000", -- | ## ## | 08 - "0110000110000000", -- | ## ## | 09 - "0110000110000000", -- | ## ## | 10 - "0110000110000000", -- | ## ## | 11 - "0111111100000000", -- | ####### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 067 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0001111000000000", -- | #### | 03 - "0011001100000000", -- | ## ## | 04 - "0110000100000000", -- | ## # | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000100000000", -- | ## # | 10 - "0011001100000000", -- | ## ## | 11 - "0001111000000000", -- | #### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 068 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0111111000000000", -- | ###### | 03 - "0110001100000000", -- | ## ## | 04 - "0110000110000000", -- | ## ## | 05 - "0110000110000000", -- | ## ## | 06 - "0110000110000000", -- | ## ## | 07 - "0110000110000000", -- | ## ## | 08 - "0110000110000000", -- | ## ## | 09 - "0110000110000000", -- | ## ## | 10 - "0110001100000000", -- | ## ## | 11 - "0111111000000000", -- | ###### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 069 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0111111100000000", -- | ####### | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0111111000000000", -- | ###### | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0111111100000000", -- | ####### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 070 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0111111100000000", -- | ####### | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0111111000000000", -- | ###### | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 071 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0001111100000000", -- | ##### | 03 - "0011000110000000", -- | ## ## | 04 - "0110000010000000", -- | ## # | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110011110000000", -- | ## #### | 08 - "0110000110000000", -- | ## ## | 09 - "0110000110000000", -- | ## ## | 10 - "0011000110000000", -- | ## ## | 11 - "0001111010000000", -- | #### # | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 072 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0110000110000000", -- | ## ## | 03 - "0110000110000000", -- | ## ## | 04 - "0110000110000000", -- | ## ## | 05 - "0110000110000000", -- | ## ## | 06 - "0111111110000000", -- | ######## | 07 - "0110000110000000", -- | ## ## | 08 - "0110000110000000", -- | ## ## | 09 - "0110000110000000", -- | ## ## | 10 - "0110000110000000", -- | ## ## | 11 - "0110000110000000", -- | ## ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 073 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0110000000000000", -- | ## | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 074 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000110000000000", -- | ## | 03 - "0000110000000000", -- | ## | 04 - "0000110000000000", -- | ## | 05 - "0000110000000000", -- | ## | 06 - "0000110000000000", -- | ## | 07 - "0000110000000000", -- | ## | 08 - "0000110000000000", -- | ## | 09 - "1100110000000000", -- |## ## | 10 - "1100110000000000", -- |## ## | 11 - "0111100000000000", -- | #### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 075 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0110001100000000", -- | ## ## | 03 - "0110011000000000", -- | ## ## | 04 - "0110110000000000", -- | ## ## | 05 - "0111100000000000", -- | #### | 06 - "0111000000000000", -- | ### | 07 - "0111100000000000", -- | #### | 08 - "0110110000000000", -- | ## ## | 09 - "0110011000000000", -- | ## ## | 10 - "0110001100000000", -- | ## ## | 11 - "0110000110000000", -- | ## ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 076 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0110000000000000", -- | ## | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0111111100000000", -- | ####### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 077 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0110000001100000", -- | ## ## | 03 - "0110000001100000", -- | ## ## | 04 - "0111000011100000", -- | ### ### | 05 - "0111000011100000", -- | ### ### | 06 - "0111100111100000", -- | #### #### | 07 - "0111100111100000", -- | #### #### | 08 - "0110111101100000", -- | ## #### ## | 09 - "0110111101100000", -- | ## #### ## | 10 - "0110011001100000", -- | ## ## ## | 11 - "0110011001100000", -- | ## ## ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 078 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0110000110000000", -- | ## ## | 03 - "0111000110000000", -- | ### ## | 04 - "0111100110000000", -- | #### ## | 05 - "0111100110000000", -- | #### ## | 06 - "0110110110000000", -- | ## ## ## | 07 - "0110110110000000", -- | ## ## ## | 08 - "0110011110000000", -- | ## #### | 09 - "0110011110000000", -- | ## #### | 10 - "0110001110000000", -- | ## ### | 11 - "0110000110000000", -- | ## ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 079 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0001111000000000", -- | #### | 03 - "0011001100000000", -- | ## ## | 04 - "0110000110000000", -- | ## ## | 05 - "0110000110000000", -- | ## ## | 06 - "0110000110000000", -- | ## ## | 07 - "0110000110000000", -- | ## ## | 08 - "0110000110000000", -- | ## ## | 09 - "0110000110000000", -- | ## ## | 10 - "0011001100000000", -- | ## ## | 11 - "0001111000000000", -- | #### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 080 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0111111100000000", -- | ####### | 03 - "0110000110000000", -- | ## ## | 04 - "0110000110000000", -- | ## ## | 05 - "0110000110000000", -- | ## ## | 06 - "0110000110000000", -- | ## ## | 07 - "0111111100000000", -- | ####### | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 081 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0001111000000000", -- | #### | 03 - "0011001100000000", -- | ## ## | 04 - "0110000110000000", -- | ## ## | 05 - "0110000110000000", -- | ## ## | 06 - "0110000110000000", -- | ## ## | 07 - "0110000110000000", -- | ## ## | 08 - "0110000110000000", -- | ## ## | 09 - "0110011110000000", -- | ## #### | 10 - "0011001100000000", -- | ## ## | 11 - "0001111110000000", -- | ###### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 082 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0111111100000000", -- | ####### | 03 - "0110000110000000", -- | ## ## | 04 - "0110000110000000", -- | ## ## | 05 - "0110000110000000", -- | ## ## | 06 - "0110000110000000", -- | ## ## | 07 - "0111111100000000", -- | ####### | 08 - "0110000110000000", -- | ## ## | 09 - "0110000110000000", -- | ## ## | 10 - "0110000110000000", -- | ## ## | 11 - "0110000011000000", -- | ## ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 083 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0011111000000000", -- | ##### | 03 - "0110001100000000", -- | ## ## | 04 - "0110001100000000", -- | ## ## | 05 - "0110000000000000", -- | ## | 06 - "0011100000000000", -- | ### | 07 - "0000111000000000", -- | ### | 08 - "0000001100000000", -- | ## | 09 - "0110001100000000", -- | ## ## | 10 - "0110001100000000", -- | ## ## | 11 - "0011111000000000", -- | ##### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 084 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "1111111100000000", -- |######## | 03 - "0001100000000000", -- | ## | 04 - "0001100000000000", -- | ## | 05 - "0001100000000000", -- | ## | 06 - "0001100000000000", -- | ## | 07 - "0001100000000000", -- | ## | 08 - "0001100000000000", -- | ## | 09 - "0001100000000000", -- | ## | 10 - "0001100000000000", -- | ## | 11 - "0001100000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 085 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0110000110000000", -- | ## ## | 03 - "0110000110000000", -- | ## ## | 04 - "0110000110000000", -- | ## ## | 05 - "0110000110000000", -- | ## ## | 06 - "0110000110000000", -- | ## ## | 07 - "0110000110000000", -- | ## ## | 08 - "0110000110000000", -- | ## ## | 09 - "0110000110000000", -- | ## ## | 10 - "0011001100000000", -- | ## ## | 11 - "0001111000000000", -- | #### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 086 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "1100001100000000", -- |## ## | 03 - "1100001100000000", -- |## ## | 04 - "0110011000000000", -- | ## ## | 05 - "0110011000000000", -- | ## ## | 06 - "0110011000000000", -- | ## ## | 07 - "0010010000000000", -- | # # | 08 - "0011110000000000", -- | #### | 09 - "0011110000000000", -- | #### | 10 - "0001100000000000", -- | ## | 11 - "0001100000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 087 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "1100001100001100", -- |## ## ## | 03 - "1100001100001100", -- |## ## ## | 04 - "1100001100001100", -- |## ## ## | 05 - "0110011110011000", -- | ## #### ## | 06 - "0110011110011000", -- | ## #### ## | 07 - "0011010010110000", -- | ## # # ## | 08 - "0011110011110000", -- | #### #### | 09 - "0001100001100000", -- | ## ## | 10 - "0001100001100000", -- | ## ## | 11 - "0001100001100000", -- | ## ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 088 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "1100000110000000", -- |## ## | 03 - "1100000110000000", -- |## ## | 04 - "0110001100000000", -- | ## ## | 05 - "0011011000000000", -- | ## ## | 06 - "0001110000000000", -- | ### | 07 - "0001110000000000", -- | ### | 08 - "0011011000000000", -- | ## ## | 09 - "0110001100000000", -- | ## ## | 10 - "1100000110000000", -- |## ## | 11 - "1100000110000000", -- |## ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 089 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "1100000011000000", -- |## ## | 03 - "1100000011000000", -- |## ## | 04 - "0110000110000000", -- | ## ## | 05 - "0011001100000000", -- | ## ## | 06 - "0001111000000000", -- | #### | 07 - "0000110000000000", -- | ## | 08 - "0000110000000000", -- | ## | 09 - "0000110000000000", -- | ## | 10 - "0000110000000000", -- | ## | 11 - "0000110000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 090 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "1111111110000000", -- |######### | 03 - "0000000110000000", -- | ## | 04 - "0000001100000000", -- | ## | 05 - "0000011000000000", -- | ## | 06 - "0000110000000000", -- | ## | 07 - "0001100000000000", -- | ## | 08 - "0011000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "1100000000000000", -- |## | 11 - "1111111110000000", -- |######### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 091 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0111000000000000", -- | ### | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0110000000000000", -- | ## | 13 - "0110000000000000", -- | ## | 14 - "0111000000000000", -- | ### | 15 - -- ASCII 092 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "1100000000000000", -- |## | 03 - "1100000000000000", -- |## | 04 - "1100000000000000", -- |## | 05 - "1100000000000000", -- |## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0011000000000000", -- | ## | 11 - "0011000000000000", -- | ## | 12 - "0011000000000000", -- | ## | 13 - "0011000000000000", -- | ## | 14 - "0000000000000000", -- | | 15 - -- ASCII 093 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "1110000000000000", -- |### | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0110000000000000", -- | ## | 13 - "0110000000000000", -- | ## | 14 - "1110000000000000", -- |### | 15 - -- ASCII 094 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0010000000000000", -- | # | 03 - "0111000000000000", -- | ### | 04 - "1101100000000000", -- |## ## | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 095 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "1111111100000000", -- |######## | 15 - -- ASCII 096 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0111000000000000", -- | ### | 02 - "0011000000000000", -- | ## | 03 - "0001100000000000", -- | ## | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 097 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0011110000000000", -- | #### | 06 - "0110011000000000", -- | ## ## | 07 - "0001111000000000", -- | #### | 08 - "0011011000000000", -- | ## ## | 09 - "0110011000000000", -- | ## ## | 10 - "0110011000000000", -- | ## ## | 11 - "0011111000000000", -- | ##### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 098 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0110000000000000", -- | ## | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0111110000000000", -- | ##### | 06 - "0110011000000000", -- | ## ## | 07 - "0110011000000000", -- | ## ## | 08 - "0110011000000000", -- | ## ## | 09 - "0110011000000000", -- | ## ## | 10 - "0110011000000000", -- | ## ## | 11 - "0111110000000000", -- | ##### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 099 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0011110000000000", -- | #### | 06 - "0110011000000000", -- | ## ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110011000000000", -- | ## ## | 11 - "0011110000000000", -- | #### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 100 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000011000000000", -- | ## | 03 - "0000011000000000", -- | ## | 04 - "0000011000000000", -- | ## | 05 - "0011111000000000", -- | ##### | 06 - "0110011000000000", -- | ## ## | 07 - "0110011000000000", -- | ## ## | 08 - "0110011000000000", -- | ## ## | 09 - "0110011000000000", -- | ## ## | 10 - "0110011000000000", -- | ## ## | 11 - "0011111000000000", -- | ##### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 101 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0011110000000000", -- | #### | 06 - "0110011000000000", -- | ## ## | 07 - "0111111000000000", -- | ###### | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110011000000000", -- | ## ## | 11 - "0011110000000000", -- | #### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 102 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0011000000000000", -- | ## | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "1111000000000000", -- |#### | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 103 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0011111000000000", -- | ##### | 06 - "0110011000000000", -- | ## ## | 07 - "0110011000000000", -- | ## ## | 08 - "0110011000000000", -- | ## ## | 09 - "0110011000000000", -- | ## ## | 10 - "0110011000000000", -- | ## ## | 11 - "0011111000000000", -- | ##### | 12 - "0000011000000000", -- | ## | 13 - "0110011000000000", -- | ## ## | 14 - "0011110000000000", -- | #### | 15 - -- ASCII 104 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0110000000000000", -- | ## | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0111110000000000", -- | ##### | 06 - "0110011000000000", -- | ## ## | 07 - "0110011000000000", -- | ## ## | 08 - "0110011000000000", -- | ## ## | 09 - "0110011000000000", -- | ## ## | 10 - "0110011000000000", -- | ## ## | 11 - "0110011000000000", -- | ## ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 105 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0110000000000000", -- | ## | 03 - "0110000000000000", -- | ## | 04 - "0000000000000000", -- | | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 106 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0110000000000000", -- | ## | 03 - "0110000000000000", -- | ## | 04 - "0000000000000000", -- | | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0110000000000000", -- | ## | 13 - "0110000000000000", -- | ## | 14 - "1100000000000000", -- |## | 15 - -- ASCII 107 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0110000000000000", -- | ## | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110011000000000", -- | ## ## | 06 - "0110110000000000", -- | ## ## | 07 - "0111100000000000", -- | #### | 08 - "0111000000000000", -- | ### | 09 - "0111100000000000", -- | #### | 10 - "0110110000000000", -- | ## ## | 11 - "0110011000000000", -- | ## ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 108 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0110000000000000", -- | ## | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 109 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0111111111000000", -- | ######### | 06 - "0110011001100000", -- | ## ## ## | 07 - "0110011001100000", -- | ## ## ## | 08 - "0110011001100000", -- | ## ## ## | 09 - "0110011001100000", -- | ## ## ## | 10 - "0110011001100000", -- | ## ## ## | 11 - "0110011001100000", -- | ## ## ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 110 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0111110000000000", -- | ##### | 06 - "0110011000000000", -- | ## ## | 07 - "0110011000000000", -- | ## ## | 08 - "0110011000000000", -- | ## ## | 09 - "0110011000000000", -- | ## ## | 10 - "0110011000000000", -- | ## ## | 11 - "0110011000000000", -- | ## ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 111 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0011110000000000", -- | #### | 06 - "0110011000000000", -- | ## ## | 07 - "0110011000000000", -- | ## ## | 08 - "0110011000000000", -- | ## ## | 09 - "0110011000000000", -- | ## ## | 10 - "0110011000000000", -- | ## ## | 11 - "0011110000000000", -- | #### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 112 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0111110000000000", -- | ##### | 06 - "0110011000000000", -- | ## ## | 07 - "0110011000000000", -- | ## ## | 08 - "0110011000000000", -- | ## ## | 09 - "0110011000000000", -- | ## ## | 10 - "0110011000000000", -- | ## ## | 11 - "0111110000000000", -- | ##### | 12 - "0110000000000000", -- | ## | 13 - "0110000000000000", -- | ## | 14 - "0110000000000000", -- | ## | 15 - -- ASCII 113 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0011111000000000", -- | ##### | 06 - "0110011000000000", -- | ## ## | 07 - "0110011000000000", -- | ## ## | 08 - "0110011000000000", -- | ## ## | 09 - "0110011000000000", -- | ## ## | 10 - "0110011000000000", -- | ## ## | 11 - "0011111000000000", -- | ##### | 12 - "0000011000000000", -- | ## | 13 - "0000011000000000", -- | ## | 14 - "0000011000000000", -- | ## | 15 - -- ASCII 114 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0111100000000000", -- | #### | 06 - "0111000000000000", -- | ### | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 115 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0011110000000000", -- | #### | 06 - "0110011000000000", -- | ## ## | 07 - "0110000000000000", -- | ## | 08 - "0011110000000000", -- | #### | 09 - "0000011000000000", -- | ## | 10 - "0110011000000000", -- | ## ## | 11 - "0011110000000000", -- | #### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 116 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "1111000000000000", -- |#### | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0011000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 117 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0110011000000000", -- | ## ## | 06 - "0110011000000000", -- | ## ## | 07 - "0110011000000000", -- | ## ## | 08 - "0110011000000000", -- | ## ## | 09 - "0110011000000000", -- | ## ## | 10 - "0110011000000000", -- | ## ## | 11 - "0011111000000000", -- | ##### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 118 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "1100001100000000", -- |## ## | 06 - "1100001100000000", -- |## ## | 07 - "0110011000000000", -- | ## ## | 08 - "0110011000000000", -- | ## ## | 09 - "0011110000000000", -- | #### | 10 - "0001100000000000", -- | ## | 11 - "0001100000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 119 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "1100000011000000", -- |## ## | 06 - "1100110011000000", -- |## ## ## | 07 - "0110110110000000", -- | ## ## ## | 08 - "0110110110000000", -- | ## ## ## | 09 - "0111111110000000", -- | ######## | 10 - "0011001100000000", -- | ## ## | 11 - "0011001100000000", -- | ## ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 120 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "1100001100000000", -- |## ## | 06 - "0110011000000000", -- | ## ## | 07 - "0011110000000000", -- | #### | 08 - "0001100000000000", -- | ## | 09 - "0011110000000000", -- | #### | 10 - "0110011000000000", -- | ## ## | 11 - "1100001100000000", -- |## ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 121 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "1100001100000000", -- |## ## | 06 - "1100001100000000", -- |## ## | 07 - "0110011000000000", -- | ## ## | 08 - "0110011000000000", -- | ## ## | 09 - "0011110000000000", -- | #### | 10 - "0011110000000000", -- | #### | 11 - "0001100000000000", -- | ## | 12 - "0001100000000000", -- | ## | 13 - "0011000000000000", -- | ## | 14 - "0110000000000000", -- | ## | 15 - -- ASCII 122 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0111111000000000", -- | ###### | 06 - "0000011000000000", -- | ## | 07 - "0000110000000000", -- | ## | 08 - "0001100000000000", -- | ## | 09 - "0011000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0111111000000000", -- | ###### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 123 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0001100000000000", -- | ## | 03 - "0011000000000000", -- | ## | 04 - "0011000000000000", -- | ## | 05 - "0011000000000000", -- | ## | 06 - "0011000000000000", -- | ## | 07 - "0011000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0011000000000000", -- | ## | 10 - "0011000000000000", -- | ## | 11 - "0011000000000000", -- | ## | 12 - "0011000000000000", -- | ## | 13 - "0011000000000000", -- | ## | 14 - "0001100000000000", -- | ## | 15 - -- ASCII 124 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0110000000000000", -- | ## | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0110000000000000", -- | ## | 13 - "0110000000000000", -- | ## | 14 - "0110000000000000", -- | ## | 15 - -- ASCII 125 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "1100000000000000", -- |## | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0011000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0110000000000000", -- | ## | 13 - "0110000000000000", -- | ## | 14 - "1100000000000000", -- |## | 15 - -- ASCII 126 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "1110100000000000", -- |### # | 03 - "1011100000000000", -- |# ### | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 127 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 128 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 129 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 130 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 131 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 132 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 133 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 134 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 135 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 136 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 137 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 138 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 139 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 140 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 141 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 142 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 143 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 144 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 145 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0011000000000000", -- | ## | 02 - "0110000000000000", -- | ## | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 146 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0110000000000000", -- | ## | 02 - "1100000000000000", -- |## | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 147 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 148 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 149 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 150 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 151 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 152 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 153 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 154 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 155 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 156 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 157 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 158 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 159 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 160 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 161 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0110000000000000", -- | ## | 03 - "0110000000000000", -- | ## | 04 - "0000000000000000", -- | | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 162 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000110000000000", -- | ## | 05 - "0011110000000000", -- | #### | 06 - "0110111000000000", -- | ## ### | 07 - "0110100000000000", -- | ## # | 08 - "0110100000000000", -- | ## # | 09 - "0111000000000000", -- | ### | 10 - "0111011000000000", -- | ### ## | 11 - "0011110000000000", -- | #### | 12 - "0011000000000000", -- | ## | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 163 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0011100000000000", -- | ### | 03 - "0110110000000000", -- | ## ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0011000000000000", -- | ## | 07 - "0111100000000000", -- | #### | 08 - "0011000000000000", -- | ## | 09 - "0011000000000000", -- | ## | 10 - "0110011000000000", -- | ## ## | 11 - "0111110000000000", -- | ##### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 164 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0110011000000000", -- | ## ## | 03 - "0011110000000000", -- | #### | 04 - "0010010000000000", -- | # # | 05 - "0010010000000000", -- | # # | 06 - "0011110000000000", -- | #### | 07 - "0110011000000000", -- | ## ## | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 165 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "1100001100000000", -- |## ## | 03 - "1100001100000000", -- |## ## | 04 - "0110011000000000", -- | ## ## | 05 - "0110011000000000", -- | ## ## | 06 - "1111111100000000", -- |######## | 07 - "0001100000000000", -- | ## | 08 - "1111111100000000", -- |######## | 09 - "0001100000000000", -- | ## | 10 - "0001100000000000", -- | ## | 11 - "0001100000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 166 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0110000000000000", -- | ## | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0000000000000000", -- | | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0110000000000000", -- | ## | 13 - "0110000000000000", -- | ## | 14 - "0110000000000000", -- | ## | 15 - -- ASCII 167 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0011110000000000", -- | #### | 03 - "0110011000000000", -- | ## ## | 04 - "0011100000000000", -- | ### | 05 - "0011100000000000", -- | ### | 06 - "0110110000000000", -- | ## ## | 07 - "0011011000000000", -- | ## ## | 08 - "0001110000000000", -- | ### | 09 - "0001110000000000", -- | ### | 10 - "0110011000000000", -- | ## ## | 11 - "0011110000000000", -- | #### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 168 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "1101100000000000", -- |## ## | 03 - "1101100000000000", -- |## ## | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 169 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0011111100000000", -- | ###### | 03 - "0110000110000000", -- | ## ## | 04 - "1100110011000000", -- |## ## ## | 05 - "1101001011000000", -- |## # # ## | 06 - "1101000011000000", -- |## # ## | 07 - "1101000011000000", -- |## # ## | 08 - "1101001011000000", -- |## # # ## | 09 - "1100110011000000", -- |## ## ## | 10 - "0110000110000000", -- | ## ## | 11 - "0011111100000000", -- | ###### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 170 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0010000000000000", -- | # | 03 - "0001000000000000", -- | # | 04 - "0011000000000000", -- | ## | 05 - "0101000000000000", -- | # # | 06 - "0011000000000000", -- | ## | 07 - "0000000000000000", -- | | 08 - "0111000000000000", -- | ### | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 171 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0011011000000000", -- | ## ## | 07 - "0110110000000000", -- | ## ## | 08 - "1101100000000000", -- |## ## | 09 - "0110110000000000", -- | ## ## | 10 - "0011011000000000", -- | ## ## | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 172 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0111111000000000", -- | ###### | 07 - "0000011000000000", -- | ## | 08 - "0000011000000000", -- | ## | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 173 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "1111000000000000", -- |#### | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 174 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0011111100000000", -- | ###### | 03 - "0110000110000000", -- | ## ## | 04 - "1101110011000000", -- |## ### ## | 05 - "1101001011000000", -- |## # # ## | 06 - "1101001011000000", -- |## # # ## | 07 - "1101110011000000", -- |## ### ## | 08 - "1101010011000000", -- |## # # ## | 09 - "1101001011000000", -- |## # # ## | 10 - "0110000110000000", -- | ## ## | 11 - "0011111100000000", -- | ###### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 175 --------------- - "0000000000000000", -- | | 00 - "1111111100000000", -- |######## | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 176 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0111000000000000", -- | ### | 03 - "0101000000000000", -- | # # | 04 - "0101000000000000", -- | # # | 05 - "0111000000000000", -- | ### | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 177 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0001100000000000", -- | ## | 06 - "0001100000000000", -- | ## | 07 - "0111111000000000", -- | ###### | 08 - "0001100000000000", -- | ## | 09 - "0001100000000000", -- | ## | 10 - "0000000000000000", -- | | 11 - "0111111000000000", -- | ###### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 178 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0110000000000000", -- | ## | 03 - "1011000000000000", -- |# ## | 04 - "0011000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "1111000000000000", -- |#### | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 179 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0110000000000000", -- | ## | 03 - "1011000000000000", -- |# ## | 04 - "0110000000000000", -- | ## | 05 - "1011000000000000", -- |# ## | 06 - "0110000000000000", -- | ## | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 180 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0011100000000000", -- | ### | 02 - "0011000000000000", -- | ## | 03 - "0110000000000000", -- | ## | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 181 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0110011000000000", -- | ## ## | 05 - "0110011000000000", -- | ## ## | 06 - "0110011000000000", -- | ## ## | 07 - "0110011000000000", -- | ## ## | 08 - "0110011000000000", -- | ## ## | 09 - "0110011000000000", -- | ## ## | 10 - "0110011000000000", -- | ## ## | 11 - "0111111100000000", -- | ####### | 12 - "0110000000000000", -- | ## | 13 - "0110000000000000", -- | ## | 14 - "0110000000000000", -- | ## | 15 - -- ASCII 182 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0011110000000000", -- | #### | 03 - "0111110000000000", -- | ##### | 04 - "0111110000000000", -- | ##### | 05 - "0111110000000000", -- | ##### | 06 - "0111110000000000", -- | ##### | 07 - "0011110000000000", -- | #### | 08 - "0000110000000000", -- | ## | 09 - "0000110000000000", -- | ## | 10 - "0000110000000000", -- | ## | 11 - "0000110000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 183 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 184 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0011000000000000", -- | ## | 13 - "0001100000000000", -- | ## | 14 - "0111000000000000", -- | ### | 15 - -- ASCII 185 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0110000000000000", -- | ## | 03 - "1110000000000000", -- |### | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 186 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0111000000000000", -- | ### | 03 - "0101000000000000", -- | # # | 04 - "0101000000000000", -- | # # | 05 - "0101000000000000", -- | # # | 06 - "0111000000000000", -- | ### | 07 - "0000000000000000", -- | | 08 - "0111000000000000", -- | ### | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 187 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "1101100000000000", -- |## ## | 07 - "0110110000000000", -- | ## ## | 08 - "0011011000000000", -- | ## ## | 09 - "0110110000000000", -- | ## ## | 10 - "1101100000000000", -- |## ## | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 188 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0011000001100000", -- | ## ## | 03 - "0111000011000000", -- | ### ## | 04 - "0011000110000000", -- | ## ## | 05 - "0011001100000000", -- | ## ## | 06 - "0011011000000000", -- | ## ## | 07 - "0000110011000000", -- | ## ## | 08 - "0001100111000000", -- | ## ### | 09 - "0011001101000000", -- | ## ## # | 10 - "0110001111000000", -- | ## #### | 11 - "1100000011000000", -- |## ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 189 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0011000001100000", -- | ## ## | 03 - "0111000011000000", -- | ### ## | 04 - "0011000110000000", -- | ## ## | 05 - "0011001100000000", -- | ## ## | 06 - "0011011000000000", -- | ## ## | 07 - "0000110110000000", -- | ## ## | 08 - "0001101011000000", -- | ## # ## | 09 - "0011000011000000", -- | ## ## | 10 - "0110000110000000", -- | ## ## | 11 - "1100001111000000", -- |## #### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 190 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0011000001100000", -- | ## ## | 03 - "0101100011000000", -- | # ## ## | 04 - "0011000110000000", -- | ## ## | 05 - "0101101100000000", -- | # ## ## | 06 - "0011011000000000", -- | ## ## | 07 - "0000110011000000", -- | ## ## | 08 - "0001100111000000", -- | ## ### | 09 - "0011001101000000", -- | ## ## # | 10 - "0110001111000000", -- | ## #### | 11 - "1100000011000000", -- |## ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 191 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0001100000000000", -- | ## | 03 - "0001100000000000", -- | ## | 04 - "0000000000000000", -- | | 05 - "0001100000000000", -- | ## | 06 - "0001100000000000", -- | ## | 07 - "0011000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110011000000000", -- | ## ## | 10 - "0110011000000000", -- | ## ## | 11 - "0011110000000000", -- | #### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 192 --------------- - "0011100000000000", -- | ### | 00 - "0001100000000000", -- | ## | 01 - "0000110000000000", -- | ## | 02 - "0001100000000000", -- | ## | 03 - "0001100000000000", -- | ## | 04 - "0011110000000000", -- | #### | 05 - "0011110000000000", -- | #### | 06 - "0010010000000000", -- | # # | 07 - "0110011000000000", -- | ## ## | 08 - "0110011000000000", -- | ## ## | 09 - "0111111000000000", -- | ###### | 10 - "1100001100000000", -- |## ## | 11 - "1100001100000000", -- |## ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 193 --------------- - "0001110000000000", -- | ### | 00 - "0001100000000000", -- | ## | 01 - "0011000000000000", -- | ## | 02 - "0001100000000000", -- | ## | 03 - "0001100000000000", -- | ## | 04 - "0011110000000000", -- | #### | 05 - "0011110000000000", -- | #### | 06 - "0010010000000000", -- | # # | 07 - "0110011000000000", -- | ## ## | 08 - "0110011000000000", -- | ## ## | 09 - "0111111000000000", -- | ###### | 10 - "1100001100000000", -- |## ## | 11 - "1100001100000000", -- |## ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 194 --------------- - "0001100000000000", -- | ## | 00 - "0011110000000000", -- | #### | 01 - "0110011000000000", -- | ## ## | 02 - "0001100000000000", -- | ## | 03 - "0001100000000000", -- | ## | 04 - "0011110000000000", -- | #### | 05 - "0011110000000000", -- | #### | 06 - "0010010000000000", -- | # # | 07 - "0110011000000000", -- | ## ## | 08 - "0110011000000000", -- | ## ## | 09 - "0111111000000000", -- | ###### | 10 - "1100001100000000", -- |## ## | 11 - "1100001100000000", -- |## ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 195 --------------- - "0111101000000000", -- | #### # | 00 - "0101111000000000", -- | # #### | 01 - "0000000000000000", -- | | 02 - "0001100000000000", -- | ## | 03 - "0001100000000000", -- | ## | 04 - "0011110000000000", -- | #### | 05 - "0011110000000000", -- | #### | 06 - "0010010000000000", -- | # # | 07 - "0110011000000000", -- | ## ## | 08 - "0110011000000000", -- | ## ## | 09 - "0111111000000000", -- | ###### | 10 - "1100001100000000", -- |## ## | 11 - "1100001100000000", -- |## ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 196 --------------- - "0110011000000000", -- | ## ## | 00 - "0110011000000000", -- | ## ## | 01 - "0000000000000000", -- | | 02 - "0001100000000000", -- | ## | 03 - "0001100000000000", -- | ## | 04 - "0011110000000000", -- | #### | 05 - "0011110000000000", -- | #### | 06 - "0010010000000000", -- | # # | 07 - "0110011000000000", -- | ## ## | 08 - "0110011000000000", -- | ## ## | 09 - "0111111000000000", -- | ###### | 10 - "1100001100000000", -- |## ## | 11 - "1100001100000000", -- |## ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 197 --------------- - "0001100000000000", -- | ## | 00 - "0011110000000000", -- | #### | 01 - "0001100000000000", -- | ## | 02 - "0000000000000000", -- | | 03 - "0001100000000000", -- | ## | 04 - "0001100000000000", -- | ## | 05 - "0011110000000000", -- | #### | 06 - "0010010000000000", -- | # # | 07 - "0110011000000000", -- | ## ## | 08 - "0110011000000000", -- | ## ## | 09 - "0111111000000000", -- | ###### | 10 - "1100001100000000", -- |## ## | 11 - "1100001100000000", -- |## ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 198 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0001111111110000", -- | ######### | 03 - "0001111000000000", -- | #### | 04 - "0011011000000000", -- | ## ## | 05 - "0011011000000000", -- | ## ## | 06 - "0011011111100000", -- | ## ###### | 07 - "0110011000000000", -- | ## ## | 08 - "0110011000000000", -- | ## ## | 09 - "0111111000000000", -- | ###### | 10 - "1100011000000000", -- |## ## | 11 - "1100011111110000", -- |## ####### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 199 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0001111000000000", -- | #### | 03 - "0011001100000000", -- | ## ## | 04 - "0110000100000000", -- | ## # | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000100000000", -- | ## # | 10 - "0011001100000000", -- | ## ## | 11 - "0001111000000000", -- | #### | 12 - "0000110000000000", -- | ## | 13 - "0000011000000000", -- | ## | 14 - "0001110000000000", -- | ### | 15 - -- ASCII 200 --------------- - "0001110000000000", -- | ### | 00 - "0000110000000000", -- | ## | 01 - "0000011000000000", -- | ## | 02 - "0111111100000000", -- | ####### | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0111111000000000", -- | ###### | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0111111100000000", -- | ####### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 201 --------------- - "0000111000000000", -- | ### | 00 - "0000110000000000", -- | ## | 01 - "0001100000000000", -- | ## | 02 - "0111111100000000", -- | ####### | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0111111000000000", -- | ###### | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0111111100000000", -- | ####### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 202 --------------- - "0000110000000000", -- | ## | 00 - "0001111000000000", -- | #### | 01 - "0011001100000000", -- | ## ## | 02 - "0111111100000000", -- | ####### | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0111111000000000", -- | ###### | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0111111100000000", -- | ####### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 203 --------------- - "0011001100000000", -- | ## ## | 00 - "0011001100000000", -- | ## ## | 01 - "0000000000000000", -- | | 02 - "0111111100000000", -- | ####### | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0111111000000000", -- | ###### | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0111111100000000", -- | ####### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 204 --------------- - "1100000000000000", -- |## | 00 - "0110000000000000", -- | ## | 01 - "0000000000000000", -- | | 02 - "0110000000000000", -- | ## | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 205 --------------- - "0011000000000000", -- | ## | 00 - "0110000000000000", -- | ## | 01 - "0000000000000000", -- | | 02 - "0110000000000000", -- | ## | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 206 --------------- - "0110000000000000", -- | ## | 00 - "1001000000000000", -- |# # | 01 - "0000000000000000", -- | | 02 - "0110000000000000", -- | ## | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 207 --------------- - "1001000000000000", -- |# # | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0110000000000000", -- | ## | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 208 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0111111000000000", -- | ###### | 03 - "0110001100000000", -- | ## ## | 04 - "0110000110000000", -- | ## ## | 05 - "0110000110000000", -- | ## ## | 06 - "1111100110000000", -- |##### ## | 07 - "0110000110000000", -- | ## ## | 08 - "0110000110000000", -- | ## ## | 09 - "0110000110000000", -- | ## ## | 10 - "0110001100000000", -- | ## ## | 11 - "0111111000000000", -- | ###### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 209 --------------- - "0011110100000000", -- | #### # | 00 - "0010111100000000", -- | # #### | 01 - "0000000000000000", -- | | 02 - "0110000110000000", -- | ## ## | 03 - "0111000110000000", -- | ### ## | 04 - "0111100110000000", -- | #### ## | 05 - "0111100110000000", -- | #### ## | 06 - "0110110110000000", -- | ## ## ## | 07 - "0110110110000000", -- | ## ## ## | 08 - "0110011110000000", -- | ## #### | 09 - "0110011110000000", -- | ## #### | 10 - "0110001110000000", -- | ## ### | 11 - "0110000110000000", -- | ## ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 210 --------------- - "0001110000000000", -- | ### | 00 - "0000110000000000", -- | ## | 01 - "0000011000000000", -- | ## | 02 - "0001111000000000", -- | #### | 03 - "0011001100000000", -- | ## ## | 04 - "0110000110000000", -- | ## ## | 05 - "0110000110000000", -- | ## ## | 06 - "0110000110000000", -- | ## ## | 07 - "0110000110000000", -- | ## ## | 08 - "0110000110000000", -- | ## ## | 09 - "0110000110000000", -- | ## ## | 10 - "0011001100000000", -- | ## ## | 11 - "0001111000000000", -- | #### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 211 --------------- - "0000111000000000", -- | ### | 00 - "0000110000000000", -- | ## | 01 - "0001100000000000", -- | ## | 02 - "0001111000000000", -- | #### | 03 - "0011001100000000", -- | ## ## | 04 - "0110000110000000", -- | ## ## | 05 - "0110000110000000", -- | ## ## | 06 - "0110000110000000", -- | ## ## | 07 - "0110000110000000", -- | ## ## | 08 - "0110000110000000", -- | ## ## | 09 - "0110000110000000", -- | ## ## | 10 - "0011001100000000", -- | ## ## | 11 - "0001111000000000", -- | #### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 212 --------------- - "0000110000000000", -- | ## | 00 - "0001111000000000", -- | #### | 01 - "0011001100000000", -- | ## ## | 02 - "0001111000000000", -- | #### | 03 - "0011001100000000", -- | ## ## | 04 - "0110000110000000", -- | ## ## | 05 - "0110000110000000", -- | ## ## | 06 - "0110000110000000", -- | ## ## | 07 - "0110000110000000", -- | ## ## | 08 - "0110000110000000", -- | ## ## | 09 - "0110000110000000", -- | ## ## | 10 - "0011001100000000", -- | ## ## | 11 - "0001111000000000", -- | #### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 213 --------------- - "0011110100000000", -- | #### # | 00 - "0010111100000000", -- | # #### | 01 - "0000000000000000", -- | | 02 - "0001111000000000", -- | #### | 03 - "0011001100000000", -- | ## ## | 04 - "0110000110000000", -- | ## ## | 05 - "0110000110000000", -- | ## ## | 06 - "0110000110000000", -- | ## ## | 07 - "0110000110000000", -- | ## ## | 08 - "0110000110000000", -- | ## ## | 09 - "0110000110000000", -- | ## ## | 10 - "0011001100000000", -- | ## ## | 11 - "0001111000000000", -- | #### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 214 --------------- - "0011001100000000", -- | ## ## | 00 - "0011001100000000", -- | ## ## | 01 - "0000000000000000", -- | | 02 - "0001111000000000", -- | #### | 03 - "0011001100000000", -- | ## ## | 04 - "0110000110000000", -- | ## ## | 05 - "0110000110000000", -- | ## ## | 06 - "0110000110000000", -- | ## ## | 07 - "0110000110000000", -- | ## ## | 08 - "0110000110000000", -- | ## ## | 09 - "0110000110000000", -- | ## ## | 10 - "0011001100000000", -- | ## ## | 11 - "0001111000000000", -- | #### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 215 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0110011000000000", -- | ## ## | 07 - "0011110000000000", -- | #### | 08 - "0001100000000000", -- | ## | 09 - "0011110000000000", -- | #### | 10 - "0110011000000000", -- | ## ## | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 216 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0001111110000000", -- | ###### | 03 - "0011001100000000", -- | ## ## | 04 - "0110001110000000", -- | ## ### | 05 - "0110011110000000", -- | ## #### | 06 - "0110110110000000", -- | ## ## ## | 07 - "0110110110000000", -- | ## ## ## | 08 - "0111100110000000", -- | #### ## | 09 - "0111000110000000", -- | ### ## | 10 - "0011001100000000", -- | ## ## | 11 - "0111111000000000", -- | ###### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 217 --------------- - "0001110000000000", -- | ### | 00 - "0000110000000000", -- | ## | 01 - "0000011000000000", -- | ## | 02 - "0110000110000000", -- | ## ## | 03 - "0110000110000000", -- | ## ## | 04 - "0110000110000000", -- | ## ## | 05 - "0110000110000000", -- | ## ## | 06 - "0110000110000000", -- | ## ## | 07 - "0110000110000000", -- | ## ## | 08 - "0110000110000000", -- | ## ## | 09 - "0110000110000000", -- | ## ## | 10 - "0011001100000000", -- | ## ## | 11 - "0001111000000000", -- | #### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 218 --------------- - "0000111000000000", -- | ### | 00 - "0000110000000000", -- | ## | 01 - "0001100000000000", -- | ## | 02 - "0110000110000000", -- | ## ## | 03 - "0110000110000000", -- | ## ## | 04 - "0110000110000000", -- | ## ## | 05 - "0110000110000000", -- | ## ## | 06 - "0110000110000000", -- | ## ## | 07 - "0110000110000000", -- | ## ## | 08 - "0110000110000000", -- | ## ## | 09 - "0110000110000000", -- | ## ## | 10 - "0011001100000000", -- | ## ## | 11 - "0001111000000000", -- | #### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 219 --------------- - "0000110000000000", -- | ## | 00 - "0001111000000000", -- | #### | 01 - "0011001100000000", -- | ## ## | 02 - "0000000000000000", -- | | 03 - "0110000110000000", -- | ## ## | 04 - "0110000110000000", -- | ## ## | 05 - "0110000110000000", -- | ## ## | 06 - "0110000110000000", -- | ## ## | 07 - "0110000110000000", -- | ## ## | 08 - "0110000110000000", -- | ## ## | 09 - "0110000110000000", -- | ## ## | 10 - "0011001100000000", -- | ## ## | 11 - "0001111000000000", -- | #### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 220 --------------- - "0011001100000000", -- | ## ## | 00 - "0011001100000000", -- | ## ## | 01 - "0000000000000000", -- | | 02 - "0110000110000000", -- | ## ## | 03 - "0110000110000000", -- | ## ## | 04 - "0110000110000000", -- | ## ## | 05 - "0110000110000000", -- | ## ## | 06 - "0110000110000000", -- | ## ## | 07 - "0110000110000000", -- | ## ## | 08 - "0110000110000000", -- | ## ## | 09 - "0110000110000000", -- | ## ## | 10 - "0011001100000000", -- | ## ## | 11 - "0001111000000000", -- | #### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 221 --------------- - "0000111000000000", -- | ### | 00 - "0000110000000000", -- | ## | 01 - "0001100000000000", -- | ## | 02 - "1100000011000000", -- |## ## | 03 - "1100000011000000", -- |## ## | 04 - "0110000110000000", -- | ## ## | 05 - "0011001100000000", -- | ## ## | 06 - "0001111000000000", -- | #### | 07 - "0000110000000000", -- | ## | 08 - "0000110000000000", -- | ## | 09 - "0000110000000000", -- | ## | 10 - "0000110000000000", -- | ## | 11 - "0000110000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 222 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0110000000000000", -- | ## | 03 - "0110000000000000", -- | ## | 04 - "0111111000000000", -- | ###### | 05 - "0110001100000000", -- | ## ## | 06 - "0110001100000000", -- | ## ## | 07 - "0110001100000000", -- | ## ## | 08 - "0110001100000000", -- | ## ## | 09 - "0111111000000000", -- | ###### | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 223 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0011110000000000", -- | #### | 03 - "0110011000000000", -- | ## ## | 04 - "0110011000000000", -- | ## ## | 05 - "0110011000000000", -- | ## ## | 06 - "0110110000000000", -- | ## ## | 07 - "0110011000000000", -- | ## ## | 08 - "0110011000000000", -- | ## ## | 09 - "0110011000000000", -- | ## ## | 10 - "0110011000000000", -- | ## ## | 11 - "0110110000000000", -- | ## ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 224 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0011100000000000", -- | ### | 02 - "0001100000000000", -- | ## | 03 - "0000110000000000", -- | ## | 04 - "0000000000000000", -- | | 05 - "0011110000000000", -- | #### | 06 - "0110011000000000", -- | ## ## | 07 - "0001111000000000", -- | #### | 08 - "0011011000000000", -- | ## ## | 09 - "0110011000000000", -- | ## ## | 10 - "0110011000000000", -- | ## ## | 11 - "0011111000000000", -- | ##### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 225 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0001110000000000", -- | ### | 02 - "0001100000000000", -- | ## | 03 - "0011000000000000", -- | ## | 04 - "0000000000000000", -- | | 05 - "0011110000000000", -- | #### | 06 - "0110011000000000", -- | ## ## | 07 - "0001111000000000", -- | #### | 08 - "0011011000000000", -- | ## ## | 09 - "0110011000000000", -- | ## ## | 10 - "0110011000000000", -- | ## ## | 11 - "0011111000000000", -- | ##### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 226 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0001100000000000", -- | ## | 02 - "0011110000000000", -- | #### | 03 - "0110011000000000", -- | ## ## | 04 - "0000000000000000", -- | | 05 - "0011110000000000", -- | #### | 06 - "0110011000000000", -- | ## ## | 07 - "0001111000000000", -- | #### | 08 - "0011011000000000", -- | ## ## | 09 - "0110011000000000", -- | ## ## | 10 - "0110011000000000", -- | ## ## | 11 - "0011111000000000", -- | ##### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 227 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0111101000000000", -- | #### # | 03 - "0101111000000000", -- | # #### | 04 - "0000000000000000", -- | | 05 - "0011110000000000", -- | #### | 06 - "0110011000000000", -- | ## ## | 07 - "0001111000000000", -- | #### | 08 - "0011011000000000", -- | ## ## | 09 - "0110011000000000", -- | ## ## | 10 - "0110011000000000", -- | ## ## | 11 - "0011111000000000", -- | ##### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 228 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0110011000000000", -- | ## ## | 03 - "0110011000000000", -- | ## ## | 04 - "0000000000000000", -- | | 05 - "0011110000000000", -- | #### | 06 - "0110011000000000", -- | ## ## | 07 - "0001111000000000", -- | #### | 08 - "0011011000000000", -- | ## ## | 09 - "0110011000000000", -- | ## ## | 10 - "0110011000000000", -- | ## ## | 11 - "0011111000000000", -- | ##### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 229 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0001100000000000", -- | ## | 02 - "0011110000000000", -- | #### | 03 - "0001100000000000", -- | ## | 04 - "0000000000000000", -- | | 05 - "0011110000000000", -- | #### | 06 - "0110011000000000", -- | ## ## | 07 - "0001111000000000", -- | #### | 08 - "0011011000000000", -- | ## ## | 09 - "0110011000000000", -- | ## ## | 10 - "0110011000000000", -- | ## ## | 11 - "0011111000000000", -- | ##### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 230 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0011111111000000", -- | ######## | 06 - "0110011001100000", -- | ## ## ## | 07 - "0001111111100000", -- | ######## | 08 - "0011011000000000", -- | ## ## | 09 - "0110011000000000", -- | ## ## | 10 - "0110011001100000", -- | ## ## ## | 11 - "0011111111000000", -- | ######## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 231 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0011110000000000", -- | #### | 06 - "0110011000000000", -- | ## ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110011000000000", -- | ## ## | 11 - "0011110000000000", -- | #### | 12 - "0001100000000000", -- | ## | 13 - "0000110000000000", -- | ## | 14 - "0011100000000000", -- | ### | 15 - -- ASCII 232 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0011100000000000", -- | ### | 02 - "0001100000000000", -- | ## | 03 - "0000110000000000", -- | ## | 04 - "0000000000000000", -- | | 05 - "0011110000000000", -- | #### | 06 - "0110011000000000", -- | ## ## | 07 - "0111111000000000", -- | ###### | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110011000000000", -- | ## ## | 11 - "0011110000000000", -- | #### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 233 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0001110000000000", -- | ### | 02 - "0001100000000000", -- | ## | 03 - "0011000000000000", -- | ## | 04 - "0000000000000000", -- | | 05 - "0011110000000000", -- | #### | 06 - "0110011000000000", -- | ## ## | 07 - "0111111000000000", -- | ###### | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110011000000000", -- | ## ## | 11 - "0011110000000000", -- | #### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 234 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0001100000000000", -- | ## | 02 - "0011110000000000", -- | #### | 03 - "0110011000000000", -- | ## ## | 04 - "0000000000000000", -- | | 05 - "0011110000000000", -- | #### | 06 - "0110011000000000", -- | ## ## | 07 - "0111111000000000", -- | ###### | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110011000000000", -- | ## ## | 11 - "0011110000000000", -- | #### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 235 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0110011000000000", -- | ## ## | 03 - "0110011000000000", -- | ## ## | 04 - "0000000000000000", -- | | 05 - "0011110000000000", -- | #### | 06 - "0110011000000000", -- | ## ## | 07 - "0111111000000000", -- | ###### | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110011000000000", -- | ## ## | 11 - "0011110000000000", -- | #### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 236 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "1110000000000000", -- |### | 02 - "0110000000000000", -- | ## | 03 - "0011000000000000", -- | ## | 04 - "0000000000000000", -- | | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 237 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0111000000000000", -- | ### | 02 - "0110000000000000", -- | ## | 03 - "1100000000000000", -- |## | 04 - "0000000000000000", -- | | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 238 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0110000000000000", -- | ## | 02 - "1111000000000000", -- |#### | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 239 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "1001000000000000", -- |# # | 03 - "1001000000000000", -- |# # | 04 - "0000000000000000", -- | | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 240 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0111011000000000", -- | ### ## | 03 - "0001100000000000", -- | ## | 04 - "0110110000000000", -- | ## ## | 05 - "0000110000000000", -- | ## | 06 - "0011111000000000", -- | ##### | 07 - "0110011000000000", -- | ## ## | 08 - "0110011000000000", -- | ## ## | 09 - "0110011000000000", -- | ## ## | 10 - "0110011000000000", -- | ## ## | 11 - "0011110000000000", -- | #### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 241 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0111101000000000", -- | #### # | 03 - "0101111000000000", -- | # #### | 04 - "0000000000000000", -- | | 05 - "0111110000000000", -- | ##### | 06 - "0110011000000000", -- | ## ## | 07 - "0110011000000000", -- | ## ## | 08 - "0110011000000000", -- | ## ## | 09 - "0110011000000000", -- | ## ## | 10 - "0110011000000000", -- | ## ## | 11 - "0110011000000000", -- | ## ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 242 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0011100000000000", -- | ### | 02 - "0001100000000000", -- | ## | 03 - "0000110000000000", -- | ## | 04 - "0000000000000000", -- | | 05 - "0011110000000000", -- | #### | 06 - "0110011000000000", -- | ## ## | 07 - "0110011000000000", -- | ## ## | 08 - "0110011000000000", -- | ## ## | 09 - "0110011000000000", -- | ## ## | 10 - "0110011000000000", -- | ## ## | 11 - "0011110000000000", -- | #### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 243 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0001110000000000", -- | ### | 02 - "0001100000000000", -- | ## | 03 - "0011000000000000", -- | ## | 04 - "0000000000000000", -- | | 05 - "0011110000000000", -- | #### | 06 - "0110011000000000", -- | ## ## | 07 - "0110011000000000", -- | ## ## | 08 - "0110011000000000", -- | ## ## | 09 - "0110011000000000", -- | ## ## | 10 - "0110011000000000", -- | ## ## | 11 - "0011110000000000", -- | #### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 244 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0001100000000000", -- | ## | 02 - "0011110000000000", -- | #### | 03 - "0110011000000000", -- | ## ## | 04 - "0000000000000000", -- | | 05 - "0011110000000000", -- | #### | 06 - "0110011000000000", -- | ## ## | 07 - "0110011000000000", -- | ## ## | 08 - "0110011000000000", -- | ## ## | 09 - "0110011000000000", -- | ## ## | 10 - "0110011000000000", -- | ## ## | 11 - "0011110000000000", -- | #### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 245 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0111101000000000", -- | #### # | 03 - "0101111000000000", -- | # #### | 04 - "0000000000000000", -- | | 05 - "0011110000000000", -- | #### | 06 - "0110011000000000", -- | ## ## | 07 - "0110011000000000", -- | ## ## | 08 - "0110011000000000", -- | ## ## | 09 - "0110011000000000", -- | ## ## | 10 - "0110011000000000", -- | ## ## | 11 - "0011110000000000", -- | #### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 246 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0110011000000000", -- | ## ## | 03 - "0110011000000000", -- | ## ## | 04 - "0000000000000000", -- | | 05 - "0011110000000000", -- | #### | 06 - "0110011000000000", -- | ## ## | 07 - "0110011000000000", -- | ## ## | 08 - "0110011000000000", -- | ## ## | 09 - "0110011000000000", -- | ## ## | 10 - "0110011000000000", -- | ## ## | 11 - "0011110000000000", -- | #### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 247 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0011000000000000", -- | ## | 05 - "0011000000000000", -- | ## | 06 - "0000000000000000", -- | | 07 - "0111100000000000", -- | #### | 08 - "0000000000000000", -- | | 09 - "0011000000000000", -- | ## | 10 - "0011000000000000", -- | ## | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 248 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0011111000000000", -- | ##### | 06 - "0110111000000000", -- | ## ### | 07 - "0110111000000000", -- | ## ### | 08 - "0110011000000000", -- | ## ## | 09 - "0111011000000000", -- | ### ## | 10 - "0111011000000000", -- | ### ## | 11 - "0111110000000000", -- | ##### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 249 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0011100000000000", -- | ### | 02 - "0001100000000000", -- | ## | 03 - "0000110000000000", -- | ## | 04 - "0000000000000000", -- | | 05 - "0110011000000000", -- | ## ## | 06 - "0110011000000000", -- | ## ## | 07 - "0110011000000000", -- | ## ## | 08 - "0110011000000000", -- | ## ## | 09 - "0110011000000000", -- | ## ## | 10 - "0110011000000000", -- | ## ## | 11 - "0011111000000000", -- | ##### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 250 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0001110000000000", -- | ### | 02 - "0001100000000000", -- | ## | 03 - "0011000000000000", -- | ## | 04 - "0000000000000000", -- | | 05 - "0110011000000000", -- | ## ## | 06 - "0110011000000000", -- | ## ## | 07 - "0110011000000000", -- | ## ## | 08 - "0110011000000000", -- | ## ## | 09 - "0110011000000000", -- | ## ## | 10 - "0110011000000000", -- | ## ## | 11 - "0011111000000000", -- | ##### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 251 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0001100000000000", -- | ## | 02 - "0011110000000000", -- | #### | 03 - "0110011000000000", -- | ## ## | 04 - "0000000000000000", -- | | 05 - "0110011000000000", -- | ## ## | 06 - "0110011000000000", -- | ## ## | 07 - "0110011000000000", -- | ## ## | 08 - "0110011000000000", -- | ## ## | 09 - "0110011000000000", -- | ## ## | 10 - "0110011000000000", -- | ## ## | 11 - "0011111000000000", -- | ##### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 252 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0110011000000000", -- | ## ## | 03 - "0110011000000000", -- | ## ## | 04 - "0000000000000000", -- | | 05 - "0110011000000000", -- | ## ## | 06 - "0110011000000000", -- | ## ## | 07 - "0110011000000000", -- | ## ## | 08 - "0110011000000000", -- | ## ## | 09 - "0110011000000000", -- | ## ## | 10 - "0110011000000000", -- | ## ## | 11 - "0011111000000000", -- | ##### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 253 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0001110000000000", -- | ### | 02 - "0001100000000000", -- | ## | 03 - "0011000000000000", -- | ## | 04 - "0000000000000000", -- | | 05 - "1100001100000000", -- |## ## | 06 - "1100001100000000", -- |## ## | 07 - "0110011000000000", -- | ## ## | 08 - "0110011000000000", -- | ## ## | 09 - "0011110000000000", -- | #### | 10 - "0011110000000000", -- | #### | 11 - "0001100000000000", -- | ## | 12 - "0001100000000000", -- | ## | 13 - "0011000000000000", -- | ## | 14 - "0110000000000000", -- | ## | 15 - -- ASCII 254 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0110000000000000", -- | ## | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0111110000000000", -- | ##### | 06 - "0110011000000000", -- | ## ## | 07 - "0110011000000000", -- | ## ## | 08 - "0110011000000000", -- | ## ## | 09 - "0110011000000000", -- | ## ## | 10 - "0110011000000000", -- | ## ## | 11 - "0111110000000000", -- | ##### | 12 - "0110000000000000", -- | ## | 13 - "0110000000000000", -- | ## | 14 - "0110000000000000", -- | ## | 15 - -- ASCII 255 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0110011000000000", -- | ## ## | 03 - "0110011000000000", -- | ## ## | 04 - "0000000000000000", -- | | 05 - "1100001100000000", -- |## ## | 06 - "1100001100000000", -- |## ## | 07 - "0110011000000000", -- | ## ## | 08 - "0110011000000000", -- | ## ## | 09 - "0011110000000000", -- | #### | 10 - "0011110000000000", -- | #### | 11 - "0001100000000000", -- | ## | 12 - "0001100000000000", -- | ## | 13 - "0011000000000000", -- | ## | 14 - "0110000000000000", -- | ## | 15 - -- ASCII 256 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 257 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 258 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 259 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 260 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 261 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 262 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 263 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 264 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 265 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 266 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 267 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 268 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 269 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 270 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 271 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 272 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 273 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 274 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 275 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 276 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 277 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 278 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 279 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 280 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 281 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 282 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 283 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 284 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 285 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 286 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 287 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000" -- | | 15 - ); -begin - - p_rom : process - begin - wait until rising_edge(CLK); - DATA <= ROM(to_integer(unsigned(ADDR))); - end process; - -end RTL; - diff --git a/lib/VGA_ctrl/src/fonts/char_rom_the_goonies.vhd b/lib/VGA_ctrl/src/fonts/char_rom_the_goonies.vhd deleted file mode 100644 index f5bbcc5..0000000 --- a/lib/VGA_ctrl/src/fonts/char_rom_the_goonies.vhd +++ /dev/null @@ -1,539 +0,0 @@ -library ieee; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity char_rom is - port ( - CLK : in std_logic; - ADDR : in unsigned(11 downto 0); - DATA : out unsigned(7 downto 0) - ); -end; - -architecture RTL of char_rom is - - - type ROM_ARRAY is array(0 to 4095) of unsigned(7 downto 0); - constant ROM : ROM_ARRAY := ( - x"00",x"00",x"01",x"03",x"07",x"0F",x"0F",x"0F", -- 0x0000 - x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0008 - x"00",x"00",x"E0",x"F0",x"F8",x"FC",x"FC",x"FC", -- 0x0010 - x"00",x"00",x"01",x"07",x"1F",x"3F",x"7F",x"7F", -- 0x0018 - x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0020 - x"00",x"00",x"E0",x"F0",x"F8",x"F8",x"F8",x"F8", -- 0x0028 - x"00",x"00",x"07",x"1F",x"7F",x"FF",x"FF",x"FF", -- 0x0030 - x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"8F", -- 0x0038 - x"00",x"00",x"C3",x"E3",x"F1",x"F1",x"F1",x"F1", -- 0x0040 - x"00",x"00",x"F8",x"FC",x"FE",x"FE",x"FE",x"FE", -- 0x0048 - x"00",x"00",x"1F",x"1F",x"0F",x"0F",x"0F",x"0F", -- 0x0050 - x"00",x"00",x"81",x"C3",x"E2",x"E2",x"E2",x"E2", -- 0x0058 - x"00",x"00",x"FC",x"06",x"FA",x"72",x"DA",x"FA", -- 0x0060 - x"00",x"00",x"03",x"0F",x"3F",x"7F",x"7F",x"7F", -- 0x0068 - x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"C7", -- 0x0070 - x"00",x"00",x"E0",x"F0",x"F8",x"F8",x"F8",x"F8", -- 0x0078 - x"00",x"00",x"07",x"1F",x"7F",x"FF",x"FF",x"FF", -- 0x0080 - x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0088 - x"00",x"00",x"80",x"C0",x"C0",x"E0",x"E0",x"F0", -- 0x0090 - x"00",x"00",x"3F",x"3F",x"06",x"06",x"06",x"06", -- 0x0098 - x"00",x"00",x"D8",x"D8",x"18",x"1F",x"1F",x"18", -- 0x00A0 - x"00",x"00",x"DF",x"DF",x"D8",x"DE",x"DE",x"D8", -- 0x00A8 - x"00",x"00",x"80",x"80",x"00",x"00",x"00",x"00", -- 0x00B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00F8 - x"1F",x"1F",x"1F",x"1F",x"1F",x"1F",x"1F",x"3F", -- 0x0100 - x"C1",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"80", -- 0x0108 - x"FC",x"F8",x"F0",x"00",x"00",x"00",x"00",x"00", -- 0x0110 - x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F", -- 0x0118 - x"FF",x"C3",x"03",x"03",x"03",x"03",x"03",x"03", -- 0x0120 - x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8", -- 0x0128 - x"FF",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE", -- 0x0130 - x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"07", -- 0x0138 - x"F1",x"F1",x"F1",x"F1",x"F1",x"F1",x"F1",x"F1", -- 0x0140 - x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0148 - x"0F",x"0F",x"0F",x"8F",x"8F",x"8F",x"DF",x"FF", -- 0x0150 - x"E3",x"E3",x"E1",x"E0",x"E1",x"E1",x"E1",x"E3", -- 0x0158 - x"56",x"8E",x"FC",x"00",x"FF",x"FE",x"FE",x"FC", -- 0x0160 - x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F", -- 0x0168 - x"83",x"03",x"03",x"0F",x"3F",x"FF",x"FF",x"FC", -- 0x0170 - x"F8",x"F8",x"F8",x"F8",x"F0",x"C0",x"00",x"00", -- 0x0178 - x"FF",x"FF",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE", -- 0x0180 - x"E7",x"87",x"07",x"07",x"07",x"00",x"00",x"FF", -- 0x0188 - x"F0",x"F0",x"F0",x"E0",x"80",x"00",x"00",x"80", -- 0x0190 - x"06",x"06",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0198 - x"18",x"18",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01A0 - x"DF",x"DF",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01A8 - x"80",x"80",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01F8 - x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"7F",x"7F", -- 0x0200 - x"80",x"80",x"80",x"83",x"87",x"87",x"07",x"06", -- 0x0208 - x"00",x"1C",x"7C",x"FC",x"FC",x"FC",x"F0",x"F0", -- 0x0210 - x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F", -- 0x0218 - x"03",x"03",x"03",x"03",x"03",x"03",x"03",x"03", -- 0x0220 - x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8", -- 0x0228 - x"FE",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE", -- 0x0230 - x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"0F", -- 0x0238 - x"F1",x"F1",x"F1",x"F1",x"F1",x"F1",x"F1",x"F1", -- 0x0240 - x"FF",x"FF",x"FF",x"FF",x"FE",x"FC",x"FC",x"FC", -- 0x0248 - x"FF",x"FF",x"FF",x"FF",x"FF",x"7F",x"7F",x"7F", -- 0x0250 - x"E3",x"E3",x"E3",x"E3",x"E3",x"E3",x"E3",x"E3", -- 0x0258 - x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC", -- 0x0260 - x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F", -- 0x0268 - x"F0",x"C0",x"03",x"07",x"07",x"07",x"03",x"01", -- 0x0270 - x"18",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8", -- 0x0278 - x"FF",x"FF",x"FF",x"FC",x"E0",x"06",x"1E",x"FE", -- 0x0280 - x"FF",x"FF",x"FF",x"0F",x"07",x"07",x"07",x"07", -- 0x0288 - x"C0",x"C0",x"E0",x"E0",x"F0",x"F0",x"F0",x"F0", -- 0x0290 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0298 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02F8 - x"7F",x"7F",x"7F",x"7F",x"7F",x"3F",x"1F",x"0F", -- 0x0300 - x"00",x"00",x"00",x"80",x"FF",x"FF",x"FF",x"FF", -- 0x0308 - x"F0",x"78",x"7C",x"FC",x"FC",x"F8",x"F0",x"E0", -- 0x0310 - x"7F",x"7F",x"7F",x"7F",x"3F",x"1F",x"0F",x"07", -- 0x0318 - x"8F",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0320 - x"F8",x"F8",x"F8",x"F8",x"F8",x"F0",x"E0",x"C0", -- 0x0328 - x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"7F",x"3F", -- 0x0330 - x"1F",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0338 - x"F1",x"F1",x"F1",x"F1",x"E1",x"C1",x"81",x"03", -- 0x0340 - x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FE",x"FF", -- 0x0348 - x"7F",x"3F",x"3F",x"3F",x"3F",x"1F",x"1F",x"1F", -- 0x0350 - x"E3",x"E3",x"E3",x"E3",x"E3",x"E3",x"E3",x"C7", -- 0x0358 - x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"F8",x"F0", -- 0x0360 - x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F", -- 0x0368 - x"01",x"03",x"07",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0370 - x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8", -- 0x0378 - x"FE",x"FE",x"FE",x"FF",x"FF",x"7F",x"1F",x"07", -- 0x0380 - x"07",x"07",x"0F",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0388 - x"F0",x"F0",x"F0",x"F0",x"FF",x"EF",x"C3",x"83", -- 0x0390 - x"00",x"00",x"00",x"00",x"DB",x"DF",x"1F",x"1B", -- 0x0398 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0400 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0408 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0410 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0418 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0420 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0428 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0430 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0438 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0440 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0448 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0450 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0458 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0460 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0468 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0470 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0478 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0480 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0488 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0490 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0498 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0500 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0508 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0510 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0518 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0520 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0528 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0530 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0538 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0540 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0548 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0550 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0558 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0560 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0568 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0570 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0578 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0580 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0588 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0590 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0598 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0600 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0608 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0610 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0618 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0620 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0628 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0630 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0638 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0640 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0648 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0650 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0658 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0660 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0668 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0670 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0678 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0680 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0688 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0690 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0698 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0700 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0708 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0710 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0718 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0720 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0728 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0730 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0738 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0740 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0748 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0750 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0758 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0760 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0768 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0770 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0778 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0780 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0788 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0790 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0798 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0800 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0808 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0810 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0818 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0820 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0828 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0830 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0838 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0840 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0848 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0850 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0858 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0860 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0868 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0870 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0878 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0880 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0888 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0890 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0898 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0900 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0908 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0910 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0918 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0920 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0928 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0930 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0938 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0940 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0948 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0950 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0958 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0960 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0968 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0970 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0978 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0980 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0988 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0990 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0998 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AD8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BD8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CD8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DD8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0ED0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0ED8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FD8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00" -- 0x0FF8 - ); - -begin - - p_rom : process - begin - wait until rising_edge(CLK); - DATA <= ROM(to_integer(unsigned(ADDR))); - end process; -end RTL; diff --git a/lib/VGA_ctrl/src/fonts/make_rom.bat b/lib/VGA_ctrl/src/fonts/make_rom.bat deleted file mode 100644 index 9cfa61b..0000000 --- a/lib/VGA_ctrl/src/fonts/make_rom.bat +++ /dev/null @@ -1,6 +0,0 @@ -@echo off - -bff2rom fixedsys_8x15.bff y >char_rom_fixedsys_8x15.vhd -bff2rom fixedsys_8x16.bff y >char_rom_fixedsys_8x16.vhd -bff2rom fixedsys_9x16.bff y >char_rom_fixedsys_9x16.vhd -bff2rom System_16x16.bff y >char_rom_system_16x16.vhd diff --git a/lib/VGA_ctrl/src/tb_vga_frontend.vhd b/lib/VGA_ctrl/src/tb_vga_frontend.vhd deleted file mode 100644 index a89f7a4..0000000 --- a/lib/VGA_ctrl/src/tb_vga_frontend.vhd +++ /dev/null @@ -1,322 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: testbench for system test using Xilinx ML-402 - --- Copyright (C) 2007 J. Ahrensfeld - --- This library is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. - --- This library is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. - --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the Free Software --- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - --- For questions and ideas, please contact the author at jens@jayfield.org - ------------------------------------------------------------------------ - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -use work.vga_types.all; - -ENTITY tb_vga_frontend IS -END tb_vga_frontend; - -ARCHITECTURE behavior OF tb_vga_frontend IS - - constant tsvga : vga_timespec_t := ts_vga_testbench; - constant CLK_PERIOD : time := 10 ns; - constant VGA_CLK_PERIOD : time := (integer(1E9) / tsvga.f_pxl_clk) * 1 ns; - signal CLK_O : std_logic := '1'; - signal RST_O : std_logic := '1'; - - -- Master - signal CYC_O : std_logic; - signal STB_O : std_logic; - signal WE_O : std_logic; - signal SEL_O : unsigned(3 downto 0) := (others => '1'); - signal ACK_I : std_logic := '0'; - signal MRDY_O : std_logic := '1'; - signal SRDY_I : std_logic := '0'; - signal ADDR_O : unsigned(31 downto 0) := (others => '-'); - signal MDAT_I : unsigned(31 downto 0) := (others => '-'); - signal MDAT_O : unsigned(31 downto 0) := (others => '-'); - - -- Slave - signal CYC_I : std_logic := '0'; - signal STB_I : std_logic := '0'; - signal WE_I : std_logic := '0'; - signal SEL_I : unsigned(3 downto 0); - signal ACK_O : std_logic; - signal MRDY_I : std_logic; - signal SRDY_O : std_logic; - signal ADDR_I : unsigned(31 downto 0) := (others => '-'); - signal SDAT_I : unsigned(31 downto 0) := (others => '-'); - signal SDAT_O : unsigned(31 downto 0) := (others => '-'); - - -- VGA signals - signal vga_clk : std_logic := '1'; - signal vga_red : unsigned(7 downto 0); - signal vga_green : unsigned(7 downto 0); - signal vga_blue : unsigned(7 downto 0); - signal vga_blank_n : std_logic; - signal vga_sync_n : std_logic; - signal vga_hsync : std_logic; - signal vga_vsync : std_logic; - signal vga_en : std_logic; - - -BEGIN - -inst_vga_frontend : entity work.vga_frontend - GENERIC MAP - ( - fifo_depth => 256, - fifo_almost_full_thresh => 240, - fifo_almost_empty_thresh => 16, - tsvga => tsvga - ) - PORT MAP - ( - -- System signals - RST_I => RST_O, - CLK_I => CLK_O, - - -- JBUS Master signals - CYC_O => CYC_I, - STB_O => STB_I, - WE_O => WE_I, - SEL_O => SEL_I, - ACK_I => ACK_O, - SRDY_I => SRDY_O, - MRDY_O => MRDY_I, - ADDR_O => ADDR_I, - MDAT_I => MDAT_O, - MDAT_O => MDAT_I, - - -- JBUS Slave signals - CYC_I => CYC_O, - STB_I => STB_O, - WE_I => WE_O, - SEL_I => SEL_O, - ACK_O => ACK_I, - SRDY_O => SRDY_I, - MRDY_I => MRDY_O, - ADDR_I => ADDR_O, - SDAT_I => SDAT_O, - SDAT_O => SDAT_I, - - -- VGA signals - vga_clk_in => vga_clk, - vga_clk_ce => vga_en, - vga_red => vga_red, - vga_green => vga_green, - vga_blue => vga_blue, - vga_blank_n => vga_blank_n, - vga_sync_n => vga_sync_n, - vga_hsync => vga_hsync, - vga_vsync => vga_vsync - ); - - vga_en <= not RST_O; - -CLK_GEN: process - begin - wait for CLK_PERIOD/2; - CLK_O <= not CLK_O; - end process; - -VGA_CLK_GEN: process - begin - wait for VGA_CLK_PERIOD/2; - vga_clk <= not vga_clk after 3 ns; - end process; - --- Slave - SRDY_O <= CYC_I; - - process(CLK_O) - begin - if rising_edge(CLK_O) then - if RST_O = '1' then - MDAT_O <= X"00000000"; - elsif (CYC_I and STB_I) = '1' then - MDAT_O <= MDAT_O + 1; - ACK_O <= '1'; - else - ACK_O <= '0'; - end if; - end if; - end process; - --- Master -STIMULUS: process - - begin - - wait for 6*CLK_PERIOD; - RST_O <= '0'; - wait for 60*CLK_PERIOD; - - -- Enable master - CYC_O <= '1'; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '1'; - WE_O <= '1'; - SDAT_O <= X"0000_0002"; - ADDR_O <= X"0000_0000"; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '0'; - - -- Read status - CYC_O <= '1'; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_0000"; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '0'; - - -- Read resolution X - CYC_O <= '1'; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_0018"; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '0'; - - -- Read resolution Y - CYC_O <= '1'; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_001C"; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '0'; - - -- Read Cursor X - CYC_O <= '1'; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_0008"; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '0'; - - -- Read Cursor Y - CYC_O <= '1'; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_000C"; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '0'; - - -- Write char 1 - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '1'; - WE_O <= '1'; - SDAT_O <= X"0000_0035"; - ADDR_O <= X"0000_0004"; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '0'; - - -- Read char 1 - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_0004"; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '0'; - - -- Write char 2 - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '1'; - WE_O <= '1'; - SDAT_O <= X"0000_0045"; - ADDR_O <= X"0000_0004"; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '0'; - - -- Read char 2 - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_0004"; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '0'; - - -- Read Cursor X - CYC_O <= '1'; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_0008"; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '0'; - - -- Read Cursor Y - CYC_O <= '1'; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_000C"; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '0'; - - -- Set Cursor X - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '1'; - WE_O <= '1'; - SDAT_O <= X"0000_0012"; - ADDR_O <= X"0000_0008"; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '0'; - - -- Set Cursor Y - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '1'; - WE_O <= '1'; - SDAT_O <= X"0000_0014"; - ADDR_O <= X"0000_000C"; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '0'; - - -- Read Cursor X - CYC_O <= '1'; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_0008"; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '0'; - - -- Read Cursor Y - CYC_O <= '1'; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_000C"; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '0'; - - wait until rising_edge(CLK_O); - CYC_O <= '0'; - - - - wait; - - end process; - -END; diff --git a/lib/VGA_ctrl/src/tb_vga_frontend64.vhd b/lib/VGA_ctrl/src/tb_vga_frontend64.vhd deleted file mode 100644 index cdcb8bb..0000000 --- a/lib/VGA_ctrl/src/tb_vga_frontend64.vhd +++ /dev/null @@ -1,969 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: testbench for system test using Xilinx ML-402 - --- Copyright (C) 2007 J. Ahrensfeld - --- This library is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. - --- This library is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. - --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the Free Software --- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - --- For questions and ideas, please contact the author at jens@jayfield.org - ------------------------------------------------------------------------ - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -use work.vga_types.all; - -ENTITY tb_vga_frontend64 IS -END tb_vga_frontend64; - -ARCHITECTURE behavior OF tb_vga_frontend64 IS - - constant tsvga : vga_timespec_t := ts_vga_testbench; - constant CLK_PERIOD : time := 10 ns; - constant VGA_CLK_PERIOD : time := (integer(1E9) / tsvga.f_pxl_clk) * 1 ns; - signal CLK_O : std_logic := '1'; - signal RST_O : std_logic := '1'; - - -- Master - signal INT_O : std_logic; - signal CYC_O : std_logic; - signal STB_O : std_logic; - signal WE_O : std_logic; - signal SEL_O : unsigned(3 downto 0) := (others => '1'); - signal ACK_I : std_logic := '0'; - signal MRDY_O : std_logic := '1'; - signal SRDY_I : std_logic := '0'; - signal ADDR_O : unsigned(31 downto 0) := (others => '-'); - signal MDAT_I : unsigned(63 downto 0) := (others => '-'); - signal MDAT_O : unsigned(63 downto 0) := (others => '-'); - - -- Slave - signal CYC_I : std_logic := '0'; - signal STB_I : std_logic := '0'; - signal WE_I : std_logic := '0'; - signal SEL_I : unsigned(7 downto 0); - signal ACK_O : std_logic; - signal MRDY_I : std_logic; - signal SRDY_O : std_logic; - signal ADDR_I : unsigned(31 downto 0) := (others => '0'); - signal SDAT_I : unsigned(31 downto 0) := (others => '-'); - signal SDAT_O : unsigned(31 downto 0) := (others => '-'); - signal rdy : std_logic := '0'; - - signal read_reg : unsigned(31 downto 0) := (others => '-'); - signal const_color : unsigned(31 downto 0) := X"0000_0000"; - - -- VGA signals - signal vga_clk : std_logic := '1'; - signal vga_red : unsigned(7 downto 0); - signal vga_green : unsigned(7 downto 0); - signal vga_blue : unsigned(7 downto 0); - signal vga_blank_n : std_logic; - signal vga_sync_n : std_logic; - signal vga_hsync : std_logic; - signal vga_vsync : std_logic; - signal vga_en : std_logic; - - type blit_size_array_t is array (0 to 9) of natural; - - constant blit_size_x : blit_size_array_t := (8, 1, 2, 7, 8, 7, 1, 8, 8, 0); - constant blit_size_y : blit_size_array_t := (8, 1, 2, 8, 7, 7, 8, 1, 0, 8); - signal blit_count_rst : std_logic := '0'; - type state_t is (IDLE, LA_SA, LA_SU, LU_SA, LU_SU, CC_SA, CC_SU); - signal state : state_t := IDLE; - - type ram_t is array (0 to 127) of unsigned(63 downto 0); - - signal ram_src : ram_t := - ( - X"B000_0000_A000_0000", - X"B000_0001_A000_0001", - X"B000_0002_A000_0002", - X"B000_0003_A000_0003", - X"B000_0004_A000_0004", - X"B000_0005_A000_0005", - X"B000_0006_A000_0006", - X"B000_0007_A000_0007", - X"B000_0008_A000_0008", - X"B000_0009_A000_0009", - X"B000_000A_A000_000A", - X"B000_000B_A000_000B", - X"B000_000C_A000_000C", - X"B000_000D_A000_000D", - X"B000_000E_A000_000E", - X"B000_000F_A000_000F", - - X"B000_0010_A000_0010", - X"B000_0011_A000_0011", - X"B000_0012_A000_0012", - X"B000_0013_A000_0013", - X"B000_0014_A000_0014", - X"B000_0015_A000_0015", - X"B000_0016_A000_0016", - X"B000_0017_A000_0017", - X"B000_0018_A000_0018", - X"B000_0019_A000_0019", - X"B000_001A_A000_001A", - X"B000_001B_A000_001B", - X"B000_001C_A000_001C", - X"B000_001D_A000_001D", - X"B000_001E_A000_001E", - X"B000_001F_A000_001F", - - X"B000_0020_A000_0020", - X"B000_0021_A000_0021", - X"B000_0022_A000_0022", - X"B000_0023_A000_0023", - X"B000_0024_A000_0024", - X"B000_0025_A000_0025", - X"B000_0026_A000_0026", - X"B000_0027_A000_0027", - X"B000_0028_A000_0028", - X"B000_0029_A000_0029", - X"B000_002A_A000_002A", - X"B000_002B_A000_002B", - X"B000_002C_A000_002C", - X"B000_002D_A000_002D", - X"B000_002E_A000_002E", - X"B000_002F_A000_002F", - - X"B000_0030_A000_0030", - X"B000_0031_A000_0031", - X"B000_0032_A000_0032", - X"B000_0033_A000_0033", - X"B000_0034_A000_0034", - X"B000_0035_A000_0035", - X"B000_0036_A000_0036", - X"B000_0037_A000_0037", - X"B000_0038_A000_0038", - X"B000_0039_A000_0039", - X"B000_003A_A000_003A", - X"B000_003B_A000_003B", - X"B000_003C_A000_003C", - X"B000_003D_A000_003D", - X"B000_003E_A000_003E", - X"B000_003F_A000_003F", - - X"B000_0040_A000_0040", - X"B000_0041_A000_0041", - X"B000_0042_A000_0042", - X"B000_0043_A000_0043", - X"B000_0044_A000_0044", - X"B000_0045_A000_0045", - X"B000_0046_A000_0046", - X"B000_0047_A000_0047", - X"B000_0048_A000_0048", - X"B000_0049_A000_0049", - X"B000_004A_A000_004A", - X"B000_004B_A000_004B", - X"B000_004C_A000_004C", - X"B000_004D_A000_004D", - X"B000_004E_A000_004E", - X"B000_004F_A000_004F", - - X"B000_0050_A000_0050", - X"B000_0051_A000_0051", - X"B000_0052_A000_0052", - X"B000_0053_A000_0053", - X"B000_0054_A000_0054", - X"B000_0055_A000_0055", - X"B000_0056_A000_0056", - X"B000_0057_A000_0057", - X"B000_0058_A000_0058", - X"B000_0059_A000_0059", - X"B000_005A_A000_005A", - X"B000_005B_A000_005B", - X"B000_005C_A000_005C", - X"B000_005D_A000_005D", - X"B000_005E_A000_005E", - X"B000_005F_A000_005F", - - X"B000_0060_A000_0060", - X"B000_0061_A000_0061", - X"B000_0062_A000_0062", - X"B000_0063_A000_0063", - X"B000_0064_A000_0064", - X"B000_0065_A000_0065", - X"B000_0066_A000_0066", - X"B000_0067_A000_0067", - X"B000_0068_A000_0068", - X"B000_0069_A000_0069", - X"B000_006A_A000_006A", - X"B000_006B_A000_006B", - X"B000_006C_A000_006C", - X"B000_006D_A000_006D", - X"B000_006E_A000_006E", - X"B000_006F_A000_006F", - - X"B000_0070_A000_0070", - X"B000_0071_A000_0071", - X"B000_0072_A000_0072", - X"B000_0073_A000_0073", - X"B000_0074_A000_0074", - X"B000_0075_A000_0075", - X"B000_0076_A000_0076", - X"B000_0077_A000_0077", - X"B000_0078_A000_0078", - X"B000_0079_A000_0079", - X"B000_007A_A000_007A", - X"B000_007B_A000_007B", - X"B000_007C_A000_007C", - X"B000_007D_A000_007D", - X"B000_007E_A000_007E", - X"B000_007F_A000_007F" - ); - - signal ram_dst : ram_t := - ( - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - - - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000", - X"0000_0000_0000_0000" - - ); - -BEGIN - -inst_vga_frontend64 : entity work.vga_frontend64 - GENERIC MAP - ( - fifo_depth => 64, - fifo_almost_full_thresh => 48, - fifo_almost_empty_thresh => 16, - BLIT_CHUNK_SIZE => 16, - tsvga => tsvga - ) - PORT MAP - ( - -- System signals - RST_I => RST_O, - CLK_I => CLK_O, - - -- JBUS Master signals - CYC_O => CYC_I, - STB_O => STB_I, - WE_O => WE_I, - SEL_O => SEL_I, - ACK_I => ACK_O, - SRDY_I => SRDY_O, - MRDY_O => MRDY_I, - ADDR_O => ADDR_I, - MDAT_I => MDAT_O, - MDAT_O => MDAT_I, - - -- JBUS Slave signals - INT_O => INT_O, - CYC_I => CYC_O, - STB_I => STB_O, - WE_I => WE_O, - SEL_I => SEL_O, - ACK_O => ACK_I, - SRDY_O => SRDY_I, - MRDY_I => MRDY_O, - ADDR_I => ADDR_O, - SDAT_I => SDAT_O, - SDAT_O => SDAT_I, - - -- VGA signals - vga_clk_in => vga_clk, - vga_clk_ce => vga_en, - vga_red => vga_red, - vga_green => vga_green, - vga_blue => vga_blue, - vga_blank_n => vga_blank_n, - vga_sync_n => vga_sync_n, - vga_hsync => vga_hsync, - vga_vsync => vga_vsync - ); - - vga_en <= not RST_O; - -rdy_GEN: process - begin - wait for 3*CLK_PERIOD/2; - wait until rising_edge(CLK_O); - rdy <= not rdy; - end process; - -CLK_GEN: process - begin - wait for CLK_PERIOD/2; - CLK_O <= not CLK_O; - end process; - -VGA_CLK_GEN: process - begin - wait for VGA_CLK_PERIOD/2; - vga_clk <= not vga_clk after 3 ns; - end process; - --- Slave - SRDY_O <= CYC_I and rdy; - - process(CLK_O) - variable ack_v : unsigned(11 downto 0); - type arr64_t is array (11 downto 0) of unsigned(63 downto 0); - variable dat_v : arr64_t; - variable res: unsigned(63 downto 0); - variable scan_count: unsigned(31 downto 0); - variable ram_data : unsigned(63 downto 0); - begin - if rising_edge(CLK_O) then - if RST_O = '1' then - scan_count := X"00000000"; - for i in 0 to 11 loop - dat_v(i) := X"FFFFFFFF_FFFFFFFF"; - ack_v(i) := '0'; - end loop; - else - if (CYC_I and STB_I) = '1' and rdy = '1' then - if WE_I = '0' then - if ADDR_I(30) = '1' then - if ADDR_I(2) = '0' then - res := ADDR_I & scan_count; - else - res := scan_count & ADDR_I; - end if; - scan_count := scan_count + 8; - else - ram_data := ram_src(to_integer(ADDR_I(31 downto 3))); - if ADDR_I(2) = '0' then - res := ram_data; - else - res := ram_data(31 downto 0) & ram_data(63 downto 32); - end if; - end if; - dat_v := dat_v(10 downto 0) & res; - ack_v := ack_v(10 downto 0) & '1'; - else -- WE=1 - ram_data := ram_dst(to_integer(ADDR_I(31 downto 3))); - ram_data := (others => '-'); - if ADDR_I(2) = '0' then - if SEL_I = "11111111" then - ram_dst(to_integer(ADDR_I(31 downto 3))) <= MDAT_I; - elsif SEL_I = "00001111" then - ram_dst(to_integer(ADDR_I(31 downto 3))) <= ram_data(63 downto 32) & MDAT_I(31 downto 0); - elsif SEL_I = "11110000" then - ram_dst(to_integer(ADDR_I(31 downto 3))) <= MDAT_I(63 downto 32) & ram_data(31 downto 0); - end if; - else - if SEL_I = "11111111" then - ram_dst(to_integer(ADDR_I(31 downto 3))) <= MDAT_I(31 downto 0) & MDAT_I(63 downto 32); - elsif SEL_I = "00001111" then - ram_dst(to_integer(ADDR_I(31 downto 3))) <= MDAT_I(31 downto 0) & ram_data(31 downto 0); - elsif SEL_I = "11110000" then - ram_dst(to_integer(ADDR_I(31 downto 3))) <= ram_data(63 downto 32) & MDAT_I(63 downto 32); - end if; - end if; - end if; - else - dat_v := dat_v(10 downto 0) & X"FFFFFFFF_FFFFFFFF"; - ack_v := ack_v(10 downto 0) & '0'; - end if; - - MDAT_O <= dat_v(dat_v'left); - ACK_O <= ack_v(ack_v'left); - end if; - end if; - end process; - - process(CLK_O) - begin - if rising_edge(CLK_O) then - if RST_O = '1' then - read_reg <= X"00000000"; - elsif ACK_I = '1' then - read_reg <= SDAT_I; - end if; - end if; - end process; - --- Master -STIMULUS: process - - variable result : unsigned(31 downto 0); - - procedure reg_write(reg, val : unsigned) is - begin - - CYC_O <= '1'; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - WE_O <= '1'; - ADDR_O <= reg; - SDAT_O <= val; - STB_O <= '1'; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '0'; - CYC_O <= '0'; - - end procedure reg_write; - - procedure reg_read(reg : unsigned) is - begin - - CYC_O <= '1'; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - WE_O <= '0'; - ADDR_O <= reg; - STB_O <= '1'; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '0'; - wait until rising_edge(CLK_O) and ACK_I = '1'; - result := SDAT_I; - CYC_O <= '0'; - - end procedure reg_read; - - begin - - wait for 6*CLK_PERIOD; - RST_O <= '0'; - wait for 60*CLK_PERIOD; - - reg_write(X"0000_0018", X"4000_0000"); -- set frontbuffer address - reg_write(X"0000_001C", X"4000_0000"); -- set backbuffer address - reg_write(X"0000_0020", X"0000_0000"); -- set BLIT source address 0 - reg_write(X"0000_0024", X"0000_0000"); -- set BLIT source dimension 0 - reg_write(X"0000_0030", X"0000_0000"); -- set BLIT source address 1 - reg_write(X"0000_0034", X"0000_0000"); -- set BLIT source dimension 1 - reg_write(X"0000_0040", X"0000_0000"); -- set BLIT destination address - reg_write(X"0000_0044", X"0000_0000"); -- set BLIT destination dimension - - -- Enable master - reg_write(X"0000_0000", X"0000_0002"); - - -- Read status - CYC_O <= '1'; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_0000"; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '0'; - - -- Read resolution - CYC_O <= '1'; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_0014"; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '0'; - - -- Read Cursor X - CYC_O <= '1'; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_0008"; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '0'; - - -- Read Cursor Y - CYC_O <= '1'; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_000C"; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '0'; - - -- Write char 1 - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '1'; - WE_O <= '1'; - SDAT_O <= X"0000_0035"; - ADDR_O <= X"0000_0004"; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '0'; - - -- Read char 1 - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_0004"; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '0'; - - -- Write char 2 - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '1'; - WE_O <= '1'; - SDAT_O <= X"0000_0045"; - ADDR_O <= X"0000_0004"; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '0'; - - -- Read char 2 - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_0004"; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '0'; - - -- Read Cursor X - CYC_O <= '1'; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_0008"; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '0'; - - -- Read Cursor Y - CYC_O <= '1'; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_000C"; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '0'; - - -- Set Cursor X - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '1'; - WE_O <= '1'; - SDAT_O <= X"0000_0012"; - ADDR_O <= X"0000_0008"; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '0'; - - -- Set Cursor Y - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '1'; - WE_O <= '1'; - SDAT_O <= X"0000_0014"; - ADDR_O <= X"0000_000C"; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '0'; - - -- Read Cursor X - CYC_O <= '1'; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_0008"; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '0'; - - -- Read Cursor Y - CYC_O <= '1'; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_000C"; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '0'; - - wait until rising_edge(CLK_O); - CYC_O <= '0'; - - wait for 60000*CLK_PERIOD; - - for i in 0 to blit_size_array_t'length-1 loop - --- wait for 600*CLK_PERIOD; - - ------------------------------------------------- - -- BLIT aligned => aligned test - ------------------------------------------------- - while(true) loop - reg_read(X"0000_0000"); - if result(8) = '0' then - exit; - end if; - end loop; - state <= LA_SA; - - blit_count_rst <= '1'; - wait until rising_edge(CLK_O); - blit_count_rst <= '0'; - - -- set source start address - reg_write(X"0000_0020", X"0000_0000"); - - -- set src dim-x - reg_write(X"0000_0024", to_unsigned(32, 32)); - - -- set destination start address - reg_write(X"0000_0040", X"0000_0000"); - - -- set constant color - reg_write(X"0000_0058", const_color); - - -- set dst dim-x - reg_write(X"0000_0044", to_unsigned(32, 32)); - - -- set nx - reg_write(X"0000_0050", to_unsigned(blit_size_x(i), 32)); - - -- set ny - reg_write(X"0000_0054", to_unsigned(blit_size_y(i), 32)); - - -- set blit request - reg_read(X"0000_0000"); - reg_write(X"0000_0000", (result and not X"0001_0000") or X"0000_0100"); - --- wait for 600*CLK_PERIOD; - ------------------------------------------------- - -- BLIT unaligned => aligned test - ------------------------------------------------- - while(true) loop - reg_read(X"0000_0000"); - if result(8) = '0' then - exit; - end if; - end loop; - blit_count_rst <= '1'; - wait until rising_edge(CLK_O); - blit_count_rst <= '0'; - state <= LU_SA; - - -- set source start address - reg_write(X"0000_0020", X"0000_0004"); - - -- set src dim-x - reg_write(X"0000_0024", to_unsigned(32, 32)); - - -- set destination start address - reg_write(X"0000_0040", X"0000_0000"); - - -- set constant color - reg_write(X"0000_0058", const_color); - - -- set dst dim-x - reg_write(X"0000_0044", to_unsigned(32, 32)); - - -- set nx - reg_write(X"0000_0050", to_unsigned(blit_size_x(i), 32)); - - -- set ny - reg_write(X"0000_0054", to_unsigned(blit_size_y(i), 32)); - - -- set blit request - reg_read(X"0000_0000"); - reg_write(X"0000_0000", (result and not X"0001_0000") or X"0000_0100"); - --- wait for 600*CLK_PERIOD; - - ------------------------------------------------- - -- BLIT aligned => unaligned test - ------------------------------------------------- - while(true) loop - reg_read(X"0000_0000"); - if result(8) = '0' then - exit; - end if; - end loop; - blit_count_rst <= '1'; - wait until rising_edge(CLK_O); - blit_count_rst <= '0'; - state <= LA_SU; - - -- set source start address - reg_write(X"0000_0020", X"0000_0000"); - - -- set src dim-x - reg_write(X"0000_0024", to_unsigned(32, 32)); - - -- set destination start address - reg_write(X"0000_0040", X"0000_0004"); - - -- set constant color - reg_write(X"0000_0058", const_color); - - -- set dst dim-x - reg_write(X"0000_0044", to_unsigned(32, 32)); - - -- set nx - reg_write(X"0000_0050", to_unsigned(blit_size_x(i), 32)); - - -- set ny - reg_write(X"0000_0054", to_unsigned(blit_size_y(i), 32)); - - -- set blit request - reg_read(X"0000_0000"); - reg_write(X"0000_0000", (result and not X"0001_0000") or X"0000_0100"); - --- wait for 600*CLK_PERIOD; - ------------------------------------------------- - -- BLIT unaligned => unaligned test - ------------------------------------------------- - while(true) loop - reg_read(X"0000_0000"); - if result(8) = '0' then - exit; - end if; - end loop; - blit_count_rst <= '1'; - wait until rising_edge(CLK_O); - blit_count_rst <= '0'; - state <= LU_SU; - - -- set source start address - reg_write(X"0000_0020", X"0000_0004"); - - -- set src dim-x - reg_write(X"0000_0024", to_unsigned(32, 32)); - - -- set destination start address - reg_write(X"0000_0040", X"0000_0004"); - - -- set constant color - reg_write(X"0000_0058", const_color); - - -- set dst dim-x - reg_write(X"0000_0044", to_unsigned(32, 32)); - - -- set nx - reg_write(X"0000_0050", to_unsigned(blit_size_x(i), 32)); - - -- set ny - reg_write(X"0000_0054", to_unsigned(blit_size_y(i), 32)); - - -- set blit request - reg_read(X"0000_0000"); - reg_write(X"0000_0000", (result and not X"0001_0000") or X"0000_0100"); - --- wait for 600*CLK_PERIOD; - ------------------------------------------------- - -- BLIT const => aligned test - ------------------------------------------------- - while(true) loop - reg_read(X"0000_0000"); - if result(8) = '0' then - exit; - end if; - end loop; - blit_count_rst <= '1'; - wait until rising_edge(CLK_O); - blit_count_rst <= '0'; - state <= CC_SA; - - const_color <= const_color + X"1111_1111"; - - -- set source start address - reg_write(X"0000_0020", X"0000_0000"); - - -- set src dim-x - reg_write(X"0000_0024", to_unsigned(32, 32)); - - -- set destination start address - reg_write(X"0000_0040", X"0000_0000"); - - -- set constant color - reg_write(X"0000_0058", const_color); - - -- set dst dim-x - reg_write(X"0000_0044", to_unsigned(32, 32)); - - -- set nx - reg_write(X"0000_0050", to_unsigned(blit_size_x(i), 32)); - - -- set ny - reg_write(X"0000_0054", to_unsigned(blit_size_y(i), 32)); - - -- set blit request - reg_read(X"0000_0000"); - reg_write(X"0000_0000", result or X"0001_0100"); - --- wait for 600*CLK_PERIOD; - ------------------------------------------------- - -- BLIT const => unaligned test - ------------------------------------------------- - while(true) loop - reg_read(X"0000_0000"); - if result(8) = '0' then - exit; - end if; - end loop; - blit_count_rst <= '1'; - wait until rising_edge(CLK_O); - blit_count_rst <= '0'; - state <= CC_SU; - - const_color <= const_color + X"1111_1111"; - - -- set source start address - reg_write(X"0000_0020", X"0000_0000"); - - -- set src dim-x - reg_write(X"0000_0024", to_unsigned(32, 32)); - - -- set destination start address - reg_write(X"0000_0040", X"0000_0004"); - - -- set constant color - reg_write(X"0000_0058", const_color); - - -- set dst dim-x - reg_write(X"0000_0044", to_unsigned(32, 32)); - - -- set nx - reg_write(X"0000_0050", to_unsigned(blit_size_x(i), 32)); - - -- set ny - reg_write(X"0000_0054", to_unsigned(blit_size_y(i), 32)); - - -- set blit request - reg_read(X"0000_0000"); - reg_write(X"0000_0000", result or X"0001_0100"); - --- wait for 600*CLK_PERIOD; - - end loop; - state <= IDLE; - - wait; - - end process; - -END; diff --git a/lib/VGA_ctrl/src/vga_backend.vhd b/lib/VGA_ctrl/src/vga_backend.vhd deleted file mode 100644 index ed741ec..0000000 --- a/lib/VGA_ctrl/src/vga_backend.vhd +++ /dev/null @@ -1,177 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 11:25:45 10/15/05 --- Design Name: --- Module Name: vga_backend - Behavioral --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -use work.vga_types.all; - -entity vga_backend is - Generic - ( - tsvga : vga_timespec_t := ts_vga_800_600_72 - ); - Port - ( - -- System signals - sys_rst : in std_logic; - sys_clk : in std_logic; - - -- Color channels - color_in : in color_array_t; - color_op : in color_op_t; - color_en : unsigned (VGA_NUM_CH-1 downto 0); - - -- Control signals - ctrl_scan_en : in std_logic; - - -- Status signals - stat_vga_rdy : out std_logic; - stat_scan : out std_logic; - stat_hsync : out std_logic; - stat_vsync : out std_logic; - stat_hready : out std_logic; - stat_vready : out std_logic; - stat_hscan : out std_logic; - stat_vscan : out std_logic; - stat_hpos : out natural range 0 to tsvga.ts_h.ncyc_scan-1; - stat_vpos : out natural range 0 to tsvga.ts_v.ncyc_scan-1; - - -- VGA domain signals - vga_clk_in : in std_logic; - vga_clk_ce : in std_logic; - vga_red : out unsigned(7 downto 0); - vga_green : out unsigned(7 downto 0); - vga_blue : out unsigned(7 downto 0); - vga_blank_n : out std_logic; - vga_sync_n : out std_logic; - vga_hsync : out std_logic; - vga_vsync : out std_logic - ); -end vga_backend; - -architecture Behavioral of vga_backend is - - signal scan_enable : std_logic; - signal is_scan : std_logic; - signal is_hscan : std_logic; - signal is_vscan : std_logic; - signal hsync : std_logic; - signal vsync : std_logic; - signal hready : std_logic; - signal vready : std_logic; - signal rst : std_logic; - -begin - -inst_vga_timing: entity work.vga_timing - GENERIC MAP - ( - tsvga => tsvga - ) - PORT MAP - ( - sys_rst => sys_rst, - vga_clk => vga_clk_in, - vga_ce => vga_clk_ce, - sync_h => hsync, - sync_v => vsync, - scan_pos_h => stat_hpos, - scan_pos_v => stat_vpos, - is_scan_h => is_hscan, - is_scan_v => is_vscan, - scan_rdy_h => hready, - scan_rdy_v => vready - ); - - --------------------------------------------------------------------------------------------- - rst <= not vga_clk_ce; - stat_vga_rdy <= vga_clk_ce; - stat_hsync <= hsync; - stat_vsync <= vsync; - stat_hscan <= is_hscan; - stat_vscan <= is_vscan; - stat_hready <= hready; - stat_vready <= vready; - stat_scan <= is_scan; - - vga_blank_n <= '1'; - vga_sync_n <= '0'; - is_scan <= is_hscan and is_vscan and scan_enable; - - --------------------------------------------------------------------------------------------- - proc_vga_start: - process (rst, vga_clk_in) - begin - if rst = '1' then - scan_enable <= '0'; - elsif rising_edge(vga_clk_in) then - if vsync = '1' then - if ctrl_scan_en = '1' then - scan_enable <= '1'; - else - scan_enable <= '0'; - end if; - end if; - end if; - end process; - - proc_vga_color_out: - process (vga_clk_in) - variable do_scan : std_logic; - variable color : color_t; - begin - if rising_edge(vga_clk_in) then - vga_red <= X"00"; - vga_green <= X"00"; - vga_blue <= X"00"; - if is_scan = '1' then - for i in 0 to VGA_NUM_CH-1 loop - color := color_in(i); - if color_en(i) = '1' then - vga_red <= color(r); -- ToDo: color_op over channels - vga_green <= color(g); -- ToDo: color_op over channels - vga_blue <= color(b); -- ToDo: color_op over channels - end if; - end loop; - end if; - end if; - end process; - - --------------------------------------------------------------------------------------------- - proc_vga_sync_out: - process (rst, vga_clk_in) - variable hsync_r : std_logic; - variable vsync_r : std_logic; - begin - if rst = '1' then - vga_hsync <= tsvga.ts_h.sync_polarity; - vga_vsync <= tsvga.ts_v.sync_polarity; - hsync_r := tsvga.ts_h.sync_polarity; - vsync_r := tsvga.ts_v.sync_polarity; - elsif rising_edge(vga_clk_in) then - vga_hsync <= hsync_r; - vga_vsync <= vsync_r; - hsync_r := hsync xor (not tsvga.ts_h.sync_polarity); - vsync_r := vsync xor (not tsvga.ts_v.sync_polarity); - end if; - end process; - -end Behavioral; diff --git a/lib/VGA_ctrl/src/vga_frontend.vhd b/lib/VGA_ctrl/src/vga_frontend.vhd deleted file mode 100644 index 8e1f6a6..0000000 --- a/lib/VGA_ctrl/src/vga_frontend.vhd +++ /dev/null @@ -1,495 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 11:25:45 10/15/05 --- Design Name: --- Module Name: vga_backend - Behavioral --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -use work.utils_pkg.all; -use work.vga_types.all; - -entity vga_frontend is - Generic - ( - fifo_depth : integer := 2048; - fifo_almost_full_thresh : natural := 2000; - fifo_almost_empty_thresh : natural := 48; - tsvga : vga_timespec_t := ts_vga_800_600_72 - ); - Port - ( - -- System signals - RST_I : in STD_LOGIC; - CLK_I : in STD_LOGIC; - - -- JBUS Master signals - CYC_O : out STD_LOGIC; - STB_O : out STD_LOGIC; - WE_O : out STD_LOGIC; - SEL_O : out unsigned(3 downto 0); - ACK_I : in STD_LOGIC; - SRDY_I : in STD_LOGIC; - MRDY_O : out STD_LOGIC; - ADDR_O : out unsigned(31 downto 0); - MDAT_I : in unsigned(31 downto 0); - MDAT_O : out unsigned(31 downto 0); - - -- JBUS Slave signals - CYC_I : in STD_LOGIC; - STB_I : in STD_LOGIC; - WE_I : in STD_LOGIC; - SEL_I : in unsigned(3 downto 0); - ACK_O : out STD_LOGIC; - SRDY_O : out STD_LOGIC; - MRDY_I : in STD_LOGIC; - ADDR_I : in unsigned(31 downto 0); - SDAT_I : in unsigned(31 downto 0); - SDAT_O : out unsigned(31 downto 0); - - -- VGA signals - vga_clk_in : in std_logic; - vga_clk_ce : in std_logic; - vga_red : out unsigned(7 downto 0); - vga_green : out unsigned(7 downto 0); - vga_blue : out unsigned(7 downto 0); - vga_blank_n : out std_logic; - vga_sync_n : out std_logic; - vga_hsync : out std_logic; - vga_vsync : out std_logic - ); -end vga_frontend; - -architecture Behavioral of vga_frontend is - - signal vga_clk : std_logic; - - -- Color FIFO signals - signal fifo_full : std_logic; - signal fifo_empty : std_logic; - signal fifo_almost_empty : std_logic; - signal fifo_almost_full : std_logic; - signal fifo_color_re : std_logic; - signal fifo_color_we : std_logic; - signal fifo_color_out : unsigned(31 downto 0); - signal fifo_color_in : unsigned(31 downto 0); - - -- Backend signals - signal scan_rdy : std_logic; - signal ctrl_scan_en : std_logic; - signal color_in : color_array_t; - signal color_op : color_op_t; - signal color_en : unsigned (VGA_NUM_CH-1 downto 0); - - signal stat_vga_rdy : std_logic; - signal stat_hready : std_logic; - signal stat_vready : std_logic; - signal stat_scan : std_logic; - signal stat_hscan : std_logic; - signal stat_vscan : std_logic; - signal stat_hsync : std_logic; - signal stat_vsync : std_logic; - signal stat_hpos : natural range 0 to tsvga.ts_h.ncyc_scan-1; - signal stat_vpos : natural range 0 to tsvga.ts_v.ncyc_scan-1; - - -- CG signals - signal cg_en : std_logic; - signal cg_rdy : std_logic; - signal cg_draw : std_logic; - signal cg_clr_screen : std_logic; - signal cg_clr_line : std_logic; - signal cg_din : unsigned(7 downto 0); - signal cg_dout : unsigned(7 downto 0); - signal cg_ascii_we : std_logic; - signal cg_posy_we : std_logic; - signal cg_posx_we : std_logic; - signal cg_color : color_t; - signal cg_csr_pos_x : natural range 0 to 80-1; - signal cg_csr_pos_y : natural range 0 to 32-1; - - -- Bus master signals - constant MAX_REQUEST_CNT : natural := tsvga.ts_h.ncyc_scan*tsvga.ts_v.ncyc_scan; - - signal vga_mem_offset : unsigned(31 downto 0); - signal vga_scan_rdy : std_logic; - signal vga_master_en : std_logic; - signal request_cnt_rst : std_logic; - signal request_cnt_en : std_logic; - signal pixel_cnt_rst : std_logic; - signal read_bus_en : std_logic; - signal request_cnt : natural range 0 to MAX_REQUEST_CNT-1; - signal read_cnt : natural range 0 to MAX_REQUEST_CNT-1; - - type vm_state_t is (init, idle, rdy, bus_request, bus_access, bus_data); - signal s, sn : vm_state_t; - -begin - -inst_vga_backend : entity work.vga_backend - GENERIC MAP - ( - tsvga => tsvga - ) - PORT MAP - ( - -- System signals - sys_rst => RST_I, - sys_clk => CLK_I, - - -- Color channels - color_in => color_in, - color_op => color_op, - color_en => color_en, - - -- Control signals - ctrl_scan_en => ctrl_scan_en, - - -- Status signals - stat_vga_rdy => stat_vga_rdy, - stat_scan => stat_scan, - stat_hsync => stat_hsync, - stat_vsync => stat_vsync, - stat_hready => stat_hready, - stat_vready => stat_vready, - stat_hscan => stat_hscan, - stat_vscan => stat_vscan, - stat_hpos => stat_hpos, - stat_vpos => stat_vpos, - - -- VGA domain signals - vga_clk_in => vga_clk_in, - vga_clk_ce => vga_clk_ce, - vga_red => vga_red, - vga_green => vga_green, - vga_blue => vga_blue, - vga_blank_n => vga_blank_n, - vga_sync_n => vga_sync_n, - vga_hsync => vga_hsync, - vga_vsync => vga_vsync - ); - - ctrl_scan_en <= '1'; - color_en(0) <= not fifo_empty; - color_en(1) <= cg_draw; - color_in(0) <= to_color_t(fifo_color_out); - color_in(1) <= cg_color; --(X"FF", X"FF", X"FF", X"FF"); -- white opaque - color_op <= op_over; - vga_scan_rdy <= stat_hready and stat_vready; - -inst_linefifo: entity work.fifo_async - GENERIC MAP - ( - addr_width => NextExpBaseTwo(fifo_depth), - data_width => 32, - almost_full_thresh => fifo_almost_full_thresh, - almost_empty_thresh => fifo_almost_empty_thresh - ) - PORT MAP - ( - rst => RST_I, - clk_w => CLK_I, - clk_r => vga_clk_in, - we => fifo_color_we, - re => fifo_color_re, - data_w => fifo_color_in, - data_r => fifo_color_out, - fifo_full => fifo_full, - fifo_empty => fifo_empty, - fifo_afull => fifo_almost_full, - fifo_aempty => fifo_almost_empty - - ); - - fifo_color_in <= MDAT_I; - fifo_color_re <= stat_scan; - fifo_color_we <= ACK_I and read_bus_en; -- TODO: - MRDY_O <= not fifo_full; - SEL_O <= (others => '0'); - WE_O <= '0'; - -vga_master_next: - process(CLK_I) - begin - if rising_edge(CLK_I) then - if RST_I = '1' then - s <= init; - else - s <= sn; - end if; - end if; - end process; - -vga_master: - process(s, stat_vga_rdy, vga_master_en, vga_scan_rdy, fifo_almost_empty, fifo_almost_full, SRDY_I, ACK_I, read_cnt, request_cnt) - begin - - CYC_O <= '0'; - STB_O <= '0'; - pixel_cnt_rst <= '0'; - request_cnt_rst <= '0'; - request_cnt_en <= '0'; - read_bus_en <= '0'; - sn <= s; - - case s is - when init => - if stat_vga_rdy = '1' then - sn <= idle; - end if; - - when idle => - pixel_cnt_rst <= '1'; - if vga_master_en = '1' and vga_scan_rdy = '1' then - sn <= rdy; - end if; - - when rdy => --- pixel_cnt_rst <= '1'; - if fifo_almost_empty = '1' then - sn <= bus_request; - end if; - - when bus_request => - CYC_O <= '1'; - request_cnt_rst <= '1'; - if SRDY_I = '1' then - sn <= bus_access; - end if; - - when bus_access => - CYC_O <= '1'; - STB_O <= '1'; - request_cnt_en <= '1'; - read_bus_en <= '1'; - if fifo_almost_full = '1' then - sn <= bus_data; - end if; - when bus_data => - CYC_O <= '1'; - read_bus_en <= '1'; - if read_cnt = request_cnt then - sn <= rdy; - if vga_master_en = '0' then - sn <= idle; - end if; - end if; - when others => - sn <= idle; - - end case; - end process; - -request_counter: - process(CLK_I) - begin - if rising_edge(CLK_I) then - if request_cnt_rst = '1' then - request_cnt <= 0; - elsif request_cnt_en = '1' and SRDY_I = '1' then - if request_cnt /= MAX_REQUEST_CNT-1 then - request_cnt <= request_cnt + 1; - end if; - end if; - end if; - end process; - -read_counter: - process(CLK_I) - begin - if rising_edge(CLK_I) then - if request_cnt_rst = '1' then - read_cnt <= 0; - elsif read_bus_en = '1' and ACK_I = '1' then - if read_cnt /= MAX_REQUEST_CNT-1 then - read_cnt <= read_cnt + 1; - end if; - end if; - end if; - end process; - -pixel_counter: - process(CLK_I) - variable pixel_cnt : natural range 0 to MAX_REQUEST_CNT-1; - begin - if rising_edge(CLK_I) then - if pixel_cnt_rst = '1' then - pixel_cnt := 0; - elsif request_cnt_en = '1' and SRDY_I = '1' then - if pixel_cnt /= MAX_REQUEST_CNT-1 then - pixel_cnt := pixel_cnt + 1; - else - pixel_cnt := 0; - end if; - end if; - ADDR_O <= vga_mem_offset + (to_unsigned(pixel_cnt, 30) & "00"); - end if; - end process; - -inst_char_gen : entity work.char_gen - GENERIC MAP - ( - tsvga => tsvga, - CHARACTER_SCALE => 1, - CHAR_ROM_SIZE_X => 8, -- Pixels - CHAR_ROM_SIZE_Y => 16, -- Pixels - CHAR_ROM_DEPTH => 256, -- Chars - MAX_CHAR_PER_LINE => 80, -- Chars - MAX_LINE_PER_FRAME => 32, -- Chars - CHAR_SPACING_X => 0, -- Pixels - CHAR_SPACING_Y => 0, -- Pixels - SCREEN_OFFSET_X => 16, -- Pixels - SCREEN_OFFSET_Y => 16 -- Pixels - ) - PORT MAP - ( - rst => RST_I, - sys_clk => CLK_I, - vga_clk => vga_clk_in, - ce => cg_en, - frame_pulse => scan_rdy, - clr_screen => cg_clr_screen, - clr_line => cg_clr_line, - din => cg_din, - dout => cg_dout, - ascii_we => cg_ascii_we, - posy_we => cg_posy_we, - posx_we => cg_posx_we, - ready => cg_rdy, - scan_pos_x_in => stat_hpos, - scan_pos_y_in => stat_vpos, - csr_pos_x_out => cg_csr_pos_x, - csr_pos_y_out => cg_csr_pos_y, - char_draw_en => cg_draw - ); - SRDY_O <= CYC_I; -- and cg_rdy; --- SDAT_O <= X"0000000" & "000" & cg_rdy; - MDAT_O <= (others => '-'); - scan_rdy <= stat_hready and stat_vready; - cg_en <= stat_scan; - - -registers_read: - process(CLK_I) - begin - if rising_edge(CLK_I) then - ACK_O <= '0'; - if (STB_I and CYC_I) = '1' then - ACK_O <= not WE_I; - SDAT_O <= (others => '0'); - case ADDR_I(5 downto 2) is - - -- sys_vga_ctrl 0 - when "0000" => - SDAT_O(0) <= cg_rdy; - SDAT_O(1) <= vga_master_en; - - -- sys_vga_ascii 4 - when "0001" => - SDAT_O(7 downto 0) <= cg_dout; - - -- sys_vga_posx 8 - when "0010" => - SDAT_O(7 downto 0) <= to_unsigned(cg_csr_pos_x, 8); - - -- sys_vga_posy 12 - when "0011" => - SDAT_O(7 downto 0) <= to_unsigned(cg_csr_pos_y, 8); - - -- sys_vga_cgcol 16 - when "0100" => - SDAT_O <= to_unsigned(cg_color); - - -- sys_vga_moffs 20 - when "0101" => - SDAT_O <= vga_mem_offset; - - -- sys_vga_resx 24 - when "0110" => - SDAT_O(15 downto 0) <= to_unsigned(tsvga.ts_h.ncyc_scan, 16); - - -- sys_vga_resy 28 - when "0111" => - SDAT_O(15 downto 0) <= to_unsigned(tsvga.ts_v.ncyc_scan, 16); - - -- sys_vga_fps 32 - when "1000" => - SDAT_O(15 downto 0) <= to_unsigned(tsvga.nfps, 16); - - when others => null; - end case; - end if; - end if; - end process; - - -registers_write: - process(CLK_I) - begin - if rising_edge(CLK_I) then - cg_ascii_we <= '0'; - cg_posy_we <= '0'; - cg_posx_we <= '0'; - cg_clr_screen <= '0'; - cg_clr_line <= '0'; - if RST_I = '1' then - cg_din <= (others => '0'); - vga_master_en <= '0'; - vga_mem_offset <= X"40000000"; - cg_color <= (X"FF", X"FF", X"FF", X"FF"); - elsif (STB_I and CYC_I and WE_I) = '1' then - case ADDR_I(5 downto 2) is - - -- sys_vga_ctrl 0 - when "0000" => - vga_master_en <= SDAT_I(1); - cg_clr_screen <= SDAT_I(4); - cg_clr_line <= SDAT_I(5); - - -- sys_vga_ascii 4 - when "0001" => - cg_ascii_we <= '1'; - cg_din <= SDAT_I(7 downto 0); - - -- sys_vga_posx 8 - when "0010" => - cg_posx_we <= '1'; - cg_din <= SDAT_I(7 downto 0); - - -- sys_vga_posy 12 - when "0011" => - cg_posy_we <= '1'; - cg_din <= SDAT_I(7 downto 0); - - -- sys_vga_cgcol 16 - when "0100" => - cg_color <= to_color_t(SDAT_I(31 downto 0)); - - -- sys_vga_moffs 20 - when "0101" => - vga_mem_offset <= SDAT_I(31 downto 2) & "00"; - - when others => null; - end case; - - end if; - end if; - end process; - - --------------------------------------------------------------------------------------------- - -end Behavioral; diff --git a/lib/VGA_ctrl/src/vga_frontend64.vhd b/lib/VGA_ctrl/src/vga_frontend64.vhd deleted file mode 100644 index 60c1a6c..0000000 --- a/lib/VGA_ctrl/src/vga_frontend64.vhd +++ /dev/null @@ -1,1329 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 11:25:45 10/15/05 --- Design Name: --- Module Name: vga_backend - Behavioral --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -use work.utils_pkg.all; -use work.vga_types.all; - -entity vga_frontend64 is - Generic - ( - fifo_depth : integer := 4096; - fifo_almost_full_thresh : natural := 4000; - fifo_almost_empty_thresh : natural := 800; - BLIT_CHUNK_SIZE : natural := 512; - BLIT_CMD_FIFO_DEPTH : natural := 256; - tsvga : vga_timespec_t := ts_vga_800_600_72 - ); - Port - ( - -- System signals - RST_I : in STD_LOGIC; - CLK_I : in STD_LOGIC; - - -- JBUS Master signals - CYC_O : out STD_LOGIC; - STB_O : out STD_LOGIC; - WE_O : out STD_LOGIC; - SEL_O : out unsigned(7 downto 0); - ACK_I : in STD_LOGIC; - SRDY_I : in STD_LOGIC; - MRDY_O : out STD_LOGIC; - ADDR_O : out unsigned(31 downto 0); - MDAT_I : in unsigned(63 downto 0); - MDAT_O : out unsigned(63 downto 0); - - -- JBUS Slave signals - INT_O : out STD_LOGIC; - CYC_I : in STD_LOGIC; - STB_I : in STD_LOGIC; - WE_I : in STD_LOGIC; - SEL_I : in unsigned(3 downto 0); - ACK_O : out STD_LOGIC; - SRDY_O : out STD_LOGIC; - MRDY_I : in STD_LOGIC; - ADDR_I : in unsigned(31 downto 0); - SDAT_I : in unsigned(31 downto 0); - SDAT_O : out unsigned(31 downto 0); - - -- VGA signals - vga_clk_in : in std_logic; - vga_clk_ce : in std_logic; - vga_red : out unsigned(7 downto 0); - vga_green : out unsigned(7 downto 0); - vga_blue : out unsigned(7 downto 0); - vga_blank_n : out std_logic; - vga_sync_n : out std_logic; - vga_hsync : out std_logic; - vga_vsync : out std_logic - ); -end vga_frontend64; - -architecture Behavioral of vga_frontend64 is - - -- Color FIFO signals - signal fifo_full : std_logic; - signal fifo_empty : std_logic; - signal fifo_almost_empty : std_logic; - signal fifo_almost_full : std_logic; - signal fifo_color_re : std_logic; - signal fifo_color_we : std_logic; - signal fifo_color_out : unsigned(63 downto 0); - signal fifo_color_in : unsigned(63 downto 0); - - -- Backend signals - signal scan_rdy : std_logic; - signal ctrl_scan_en : std_logic; - signal color_in : color_array_t; - signal color_op : color_op_t; - signal color_en : unsigned (VGA_NUM_CH-1 downto 0); - - signal stat_vga_rdy : std_logic; - signal stat_hready : std_logic; - signal stat_vready : std_logic; - signal stat_scan : std_logic; - signal stat_hscan : std_logic; - signal stat_vscan : std_logic; - signal stat_hsync : std_logic; - signal stat_vsync : std_logic; - signal stat_hpos : natural range 0 to tsvga.ts_h.ncyc_scan-1; - signal stat_vpos : natural range 0 to tsvga.ts_v.ncyc_scan-1; - - -- CG signals - signal cg_en : std_logic; - signal cg_rdy : std_logic; - signal cg_draw : std_logic; - signal cg_clr_screen : std_logic; - signal cg_clr_line : std_logic; - signal cg_din : unsigned(7 downto 0); - signal cg_dout : unsigned(7 downto 0); - signal cg_ascii_we : std_logic; - signal cg_posy_we : std_logic; - signal cg_posx_we : std_logic; - signal cg_color : color_t; - signal cg_csr_pos_x : natural range 0 to 80-1; - signal cg_csr_pos_y : natural range 0 to 32-1; - - -- Bus master signals - constant MAX_REQUEST_CNT : natural := tsvga.ts_h.ncyc_scan*tsvga.ts_v.ncyc_scan; - - signal reg_read_vld : std_logic; - signal bufchg : std_logic; - signal bufchg_irq_en : std_logic; - signal bufchg_flag : std_logic; - signal bufchg_flag_ack : std_logic; - signal vga_fb_back : unsigned(31 downto 0); - signal vga_fb_front : unsigned(31 downto 0); - signal host_fb_front : unsigned(31 downto 0); - signal host_fb_back : unsigned(31 downto 0); - signal blit_reg_addr_src_0 : unsigned(31 downto 0); - signal blit_reg_addr_src_1 : unsigned(31 downto 0); - signal blit_reg_addr_dst : unsigned(31 downto 0); - signal blit_reg_dimx_src_0 : unsigned(31 downto 0); - signal blit_reg_dimx_src_1 : unsigned(31 downto 0); - signal blit_reg_dimx_dst : unsigned(31 downto 0); - signal blit_reg_nx : unsigned(31 downto 0); - signal blit_reg_ny : unsigned(31 downto 0); - signal blit_reg_const_color : unsigned(31 downto 0); - signal blit_reg_func : unsigned(7 downto 0); - signal vga_scan_rdy : std_logic; - signal vga_scan_dma_en : std_logic; - signal vga_scan_dma_en2 : std_logic; - signal request_cnt_rst : std_logic; - signal request_en : std_logic; - signal bus_read_en : std_logic; - signal request_cnt : unsigned(28 downto 0); - signal read_cnt : unsigned(28 downto 0); - signal bus_read_fin : std_logic; - signal bus_cycle_en : std_logic; - - signal CYC_O_scan : std_logic; - signal STB_O_scan : std_logic; - signal ADDR_O_scan : unsigned(31 downto 0); - signal pixel_cnt : natural range 0 to MAX_REQUEST_CNT/2-1; - signal front : unsigned(31 downto 0); - signal back : unsigned(31 downto 0); - - - -- Blitter vars - signal blit_reset : std_logic; - signal blit_request : std_logic; - signal blit_const_color_en : std_logic; - signal blit_request_set : std_logic; - signal blit_finish_strobe : unsigned(2 downto 0); - signal blit_complete_int : std_logic; - signal blit_complete_int_ack : std_logic; - signal blit_complete_int_en : std_logic; - signal blit_cmd_empty_int : std_logic; - signal blit_cmd_empty_int_ack : std_logic; - signal blit_cmd_empty_int_en : std_logic; - - -- BLIT command FIFO - constant BLIT_CMD_FIFO_WIDTH : natural := 320; - signal blit_cmd_din : unsigned(BLIT_CMD_FIFO_WIDTH-1 downto 0); - signal blit_cmd_dout : unsigned(BLIT_CMD_FIFO_WIDTH-1 downto 0); - signal blit_cmd_re : std_logic; - signal blit_cmd_we : std_logic; - signal blit_cmd_empty : std_logic; - signal blit_cmd_full : std_logic; - signal blit_cmd_bsy : std_logic; - signal blit_cmd_avail : std_logic; - - signal blit_cmd_addr_src_0 : unsigned(31 downto 0); - signal blit_cmd_addr_src_1 : unsigned(31 downto 0); - signal blit_cmd_addr_dst : unsigned(31 downto 0); - signal blit_cmd_dimx_src_0 : unsigned(31 downto 0); - signal blit_cmd_dimx_src_1 : unsigned(31 downto 0); - signal blit_cmd_dimx_dst : unsigned(31 downto 0); - signal blit_cmd_nx : unsigned(31 downto 0); - signal blit_cmd_ny : unsigned(31 downto 0); - signal blit_cmd_CC : unsigned(31 downto 0); - signal blit_cmd_func : unsigned(31 downto 0); - - signal blit_chunk_cnt : natural range 0 to BLIT_CHUNK_SIZE-1; - signal blit_chunk_full : std_logic; - - -- Blitter FIFO signals - signal blitfifo_dout_vld : std_logic; - signal blitfifo_write_en : std_logic; - signal blitfifo_read_en : std_logic; - signal blitfifo_full : unsigned(1 downto 0); - signal blitfifo_empty : unsigned(1 downto 0); - signal blitfifo_we : unsigned(1 downto 0); - signal blitfifo_re : unsigned(1 downto 0); - signal blitfifo_din : unsigned(63 downto 0); - signal blitfifo_dout_0 : unsigned(31 downto 0); - signal blitfifo_dout_1 : unsigned(31 downto 0); - - - -- BLIT Source register - signal blit_src_cnt_x_next : unsigned(32 downto 0); - signal blit_src_cnt_y_next : unsigned(32 downto 0); - signal blit_src_cnt_x : unsigned(31 downto 0); - signal blit_src_cnt_y : unsigned(31 downto 0); - signal blit_src_offset : unsigned(31 downto 0); - signal blit_src_addr_next : unsigned(31 downto 0); - signal blit_src_finish : std_logic; - signal blit_src_START_U : std_logic; - signal blit_src_START_A : std_logic; - signal blit_src_STOP_U : std_logic; - signal blit_src_STOP_A : std_logic; - - signal CYC_O_blit_src : std_logic; - signal STB_O_blit_src : std_logic; - signal ADDR_O_blit_src : unsigned(31 downto 0); - - -- BLIT Destination register - signal blit_dst_cnt_x_next : unsigned(32 downto 0); - signal blit_dst_cnt_y_next : unsigned(32 downto 0); - signal blit_dst_cnt_x : unsigned(31 downto 0); - signal blit_dst_cnt_y : unsigned(31 downto 0); - signal blit_dst_offset : unsigned(31 downto 0); - signal blit_dst_addr_next : unsigned(31 downto 0); - signal blit_dst_finish : std_logic; - signal blitfifo_empty_read : std_logic; - signal blit_dst_suspend : std_logic; - signal blit_dst_be : unsigned(7 downto 0); - - -- BLIT Source Tracker - signal blit_fill_cnt_x_next : unsigned(32 downto 0); - signal blit_fill_cnt_y_next : unsigned(32 downto 0); - signal blit_fill_cnt_x : unsigned(31 downto 0); - signal blit_fill_cnt_y : unsigned(31 downto 0); - signal blit_fill_offset : unsigned(2 downto 0); - signal blit_fill_finish : std_logic; - signal blit_fill_addr : unsigned(2 downto 0); - - signal CYC_O_blit_dst : std_logic; - signal STB_O_blit_dst : std_logic; - signal ADDR_O_blit_dst : unsigned(31 downto 0); - - signal odd_pixel : unsigned(NextExpBaseTwo(tsvga.ts_h.ncyc_scan)-1 downto 0); - - - -- Bus output FIFO - signal busout_fifo_din : unsigned(104 downto 0); - signal busout_fifo_dout : unsigned(104 downto 0); - signal busout_fifo_re : std_logic; - signal busout_fifo_we : std_logic; - signal busout_fifo_full : std_logic; - signal busout_fifo_empty : std_logic; - signal busout_fifo_rdy : std_logic; - - alias busout_fifo_addr_in is busout_fifo_din(31 downto 0); - alias busout_fifo_data_in is busout_fifo_din(95 downto 32); - alias busout_fifo_sel_in is busout_fifo_din(103 downto 96); - alias busout_fifo_we_in is busout_fifo_din(104); - - alias busout_fifo_addr_out is busout_fifo_dout(31 downto 0); - alias busout_fifo_data_out is busout_fifo_dout(95 downto 32); - alias busout_fifo_sel_out is busout_fifo_dout(103 downto 96); - alias busout_fifo_we_out is busout_fifo_dout(104); - - -- Bus input FIFO - signal busin_fifo_din : unsigned(63 downto 0); - signal busin_fifo_dout : unsigned(63 downto 0); - signal busin_fifo_re : std_logic; - signal busin_fifo_we : std_logic; - signal busin_fifo_full : std_logic; - signal busin_fifo_empty : std_logic; - signal busin_fifo_rdy : std_logic; - signal busin_fifo_dout_vld : std_logic; - - type vm_state_t is (init, rdy, scan_bus_request, scan_bus_read, blit_src_bus_request, blit_src_bus_read, blit_dst_bus_request, const_dst_bus_request, bus_fin); - signal s, sn : vm_state_t; - - type debug_t is - record - FIRST : std_logic; - LAST : std_logic; - UNALIGNED : std_logic; - PARTIAL : std_logic; - end record debug_t; - - signal src_dbg : debug_t; - signal fill_dbg : debug_t; - signal dst_dbg : debug_t; - --------------------------------------------------------------------------- -begin - - blit_cmd_din(BLIT_CMD_FIFO_WIDTH-1 downto BLIT_CMD_FIFO_WIDTH-32) <= blit_reg_addr_src_0; - blit_cmd_din(BLIT_CMD_FIFO_WIDTH-32-1 downto BLIT_CMD_FIFO_WIDTH-64) <= blit_reg_dimx_src_0; - blit_cmd_din(BLIT_CMD_FIFO_WIDTH-64-1 downto BLIT_CMD_FIFO_WIDTH-96) <= blit_reg_addr_src_1; - blit_cmd_din(BLIT_CMD_FIFO_WIDTH-96-1 downto BLIT_CMD_FIFO_WIDTH-128) <= blit_reg_dimx_src_1; - blit_cmd_din(BLIT_CMD_FIFO_WIDTH-128-1 downto BLIT_CMD_FIFO_WIDTH-160) <= blit_reg_addr_dst; - blit_cmd_din(BLIT_CMD_FIFO_WIDTH-160-1 downto BLIT_CMD_FIFO_WIDTH-192) <= blit_reg_dimx_dst; - blit_cmd_din(BLIT_CMD_FIFO_WIDTH-192-1 downto BLIT_CMD_FIFO_WIDTH-224) <= blit_reg_nx; - blit_cmd_din(BLIT_CMD_FIFO_WIDTH-224-1 downto BLIT_CMD_FIFO_WIDTH-256) <= blit_reg_ny; - blit_cmd_din(BLIT_CMD_FIFO_WIDTH-256-1 downto BLIT_CMD_FIFO_WIDTH-288) <= blit_reg_const_color; - blit_cmd_din(BLIT_CMD_FIFO_WIDTH-288-1 downto BLIT_CMD_FIFO_WIDTH-320) <= (31 downto 8 => '0') & blit_reg_func; - - blit_cmd_addr_src_0 <= blit_cmd_dout(BLIT_CMD_FIFO_WIDTH-1 downto BLIT_CMD_FIFO_WIDTH-32); - blit_cmd_dimx_src_0 <= blit_cmd_dout(BLIT_CMD_FIFO_WIDTH-32-1 downto BLIT_CMD_FIFO_WIDTH-64); - blit_cmd_addr_src_1 <= blit_cmd_dout(BLIT_CMD_FIFO_WIDTH-64-1 downto BLIT_CMD_FIFO_WIDTH-96); - blit_cmd_dimx_src_1 <= blit_cmd_dout(BLIT_CMD_FIFO_WIDTH-96-1 downto BLIT_CMD_FIFO_WIDTH-128); - blit_cmd_addr_dst <= blit_cmd_dout(BLIT_CMD_FIFO_WIDTH-128-1 downto BLIT_CMD_FIFO_WIDTH-160); - blit_cmd_dimx_dst <= blit_cmd_dout(BLIT_CMD_FIFO_WIDTH-160-1 downto BLIT_CMD_FIFO_WIDTH-192); - blit_cmd_nx <= blit_cmd_dout(BLIT_CMD_FIFO_WIDTH-192-1 downto BLIT_CMD_FIFO_WIDTH-224); - blit_cmd_ny <= blit_cmd_dout(BLIT_CMD_FIFO_WIDTH-224-1 downto BLIT_CMD_FIFO_WIDTH-256); - blit_cmd_CC <= blit_cmd_dout(BLIT_CMD_FIFO_WIDTH-256-1 downto BLIT_CMD_FIFO_WIDTH-288); - blit_cmd_func <= blit_cmd_dout(BLIT_CMD_FIFO_WIDTH-288-1 downto BLIT_CMD_FIFO_WIDTH-320); - - blit_cmd_avail <= not blit_cmd_empty; - blit_cmd_bsy <= blit_cmd_full; - blit_cmd_re <= blit_finish_strobe(0); - blit_cmd_we <= blit_request_set; - --- Command FIFO -inst_blit_cmd_fifo: entity work.fifo_sync - GENERIC MAP - ( - addr_width => NextExpBaseTwo(BLIT_CMD_FIFO_DEPTH), - data_width => BLIT_CMD_FIFO_WIDTH, - do_last_read_update => false - ) - PORT MAP - ( - rst => RST_I, - clk => CLK_I, - we => blit_cmd_we, - re => blit_cmd_re, - fifo_full => blit_cmd_full, - fifo_empty => blit_cmd_empty, - fifo_afull => open, - fifo_aempty => open, - data_w => blit_cmd_din, - data_r => blit_cmd_dout - ); - -proc_synced_vga_scan_en: - process(CLK_I) - begin - if rising_edge(CLK_I) then - if RST_I = '1' then - vga_scan_dma_en2 <= '0'; - elsif vga_scan_rdy = '1' then - vga_scan_dma_en2 <= vga_scan_dma_en; - end if; - end if; - end process; - - ADDR_O_scan <= front + (to_unsigned(pixel_cnt, 29) & "000"); - -proc_scan_addr: - process(CLK_I) - begin - if rising_edge(CLK_I) then - bufchg <= '0'; - if vga_scan_dma_en2 = '0' then - pixel_cnt <= 0; - front <= host_fb_front; - elsif STB_O_scan = '1' and busout_fifo_rdy = '1' then - if pixel_cnt /= MAX_REQUEST_CNT/2-1 then - pixel_cnt <= pixel_cnt + 1; - else - pixel_cnt <= 0; - front <= host_fb_back; - bufchg <= '1'; - end if; - end if; - vga_fb_front <= front; - vga_fb_back <= back; - end if; - end process; - ---------------------------------------------------------------------------------- -inst_vga_backend : entity work.vga_backend - GENERIC MAP - ( - tsvga => tsvga - ) - PORT MAP - ( - -- System signals - sys_rst => RST_I, - sys_clk => CLK_I, - - -- Color channels - color_in => color_in, - color_op => color_op, - color_en => color_en, - - -- Control signals - ctrl_scan_en => ctrl_scan_en, - - -- Status signals - stat_vga_rdy => stat_vga_rdy, - stat_scan => stat_scan, - stat_hsync => stat_hsync, - stat_vsync => stat_vsync, - stat_hready => stat_hready, - stat_vready => stat_vready, - stat_hscan => stat_hscan, - stat_vscan => stat_vscan, - stat_hpos => stat_hpos, - stat_vpos => stat_vpos, - - -- VGA domain signals - vga_clk_in => vga_clk_in, - vga_clk_ce => vga_clk_ce, - vga_red => vga_red, - vga_green => vga_green, - vga_blue => vga_blue, - vga_blank_n => vga_blank_n, - vga_sync_n => vga_sync_n, - vga_hsync => vga_hsync, - vga_vsync => vga_vsync - ); - - SRDY_O <= CYC_I; -- and cg_rdy; - MRDY_O <= busin_fifo_rdy; --not fifo_full; - STB_O <= not busout_fifo_empty; - ADDR_O <= busout_fifo_addr_out; - MDAT_O <= busout_fifo_data_out; - SEL_O <= busout_fifo_sel_out; - WE_O <= busout_fifo_we_out; - - odd_pixel <= to_unsigned(stat_hpos, odd_pixel'length); - ctrl_scan_en <= '1'; - color_en(0) <= not fifo_empty; - color_en(1) <= cg_draw; - color_in(0) <= to_color_t(fifo_color_out(31 downto 0)) when odd_pixel(0) = '0' else to_color_t(fifo_color_out(63 downto 32)); - color_in(1) <= cg_color; --(X"FF", X"FF", X"FF", X"FF"); -- white opaque - color_op <= op_over; - vga_scan_rdy <= stat_hready and stat_vready; - --- SCAN line FIFO -inst_linefifo: entity work.fifo_async - GENERIC MAP - ( - addr_width => NextExpBaseTwo(fifo_depth), - data_width => 64, - almost_full_thresh => fifo_almost_full_thresh, - almost_empty_thresh => fifo_almost_empty_thresh - ) - PORT MAP - ( - rst => RST_I, - clk_w => CLK_I, - clk_r => vga_clk_in, - we => fifo_color_we, - re => fifo_color_re, - data_w => fifo_color_in, - data_r => fifo_color_out, - fifo_full => fifo_full, - fifo_empty => fifo_empty, - fifo_afull => fifo_almost_full, - fifo_aempty => fifo_almost_empty - - ); - - fifo_color_in <= busin_fifo_dout; - fifo_color_re <= stat_scan and odd_pixel(0); - fifo_color_we <= busin_fifo_dout_vld and CYC_O_scan; -- TODO: - - --- Bus input FIFO -inst_busin_fifo: entity work.fifo_sync - GENERIC MAP - ( - addr_width => 2, - data_width => busin_fifo_din'length, - do_last_read_update => true - ) - PORT MAP - ( - rst => RST_I, - clk => CLK_I, - we => busin_fifo_we, - re => busin_fifo_re, - fifo_full => busin_fifo_full, - fifo_empty => busin_fifo_empty, - fifo_afull => open, - fifo_aempty => open, - data_w => busin_fifo_din, - data_r => busin_fifo_dout - ); - busin_fifo_rdy <= not busin_fifo_full; - busin_fifo_din <= MDAT_I; - busin_fifo_we <= ACK_I and bus_cycle_en and bus_read_en; - busin_fifo_dout_vld <= not busin_fifo_empty; - busin_fifo_re <= not fifo_full when CYC_O_scan = '1' else CYC_O_blit_src; - --- Bus output FIFO -inst_busout_fifo: entity work.fifo_sync - GENERIC MAP - ( - addr_width => 2, - data_width => busout_fifo_din'length, - do_last_read_update => false - ) - PORT MAP - ( - rst => RST_I, - clk => CLK_I, - we => busout_fifo_we, - re => busout_fifo_re, - fifo_full => busout_fifo_full, - fifo_empty => busout_fifo_empty, - fifo_afull => open, - fifo_aempty => open, - data_w => busout_fifo_din, - data_r => busout_fifo_dout - ); - - blit_const_color_en <= blit_cmd_func(0); - - busout_fifo_rdy <= not busout_fifo_full; - busout_fifo_re <= not busout_fifo_empty and SRDY_I; - busout_fifo_we <= bus_cycle_en and (STB_O_scan or STB_O_blit_src or STB_O_blit_dst); - busout_fifo_data_in <= (blitfifo_dout_1 & blitfifo_dout_0) when blit_const_color_en = '0' else (blit_cmd_CC & blit_cmd_CC); - busout_fifo_addr_in <= ADDR_O_blit_src when CYC_O_blit_src = '1' else - ADDR_O_blit_dst when CYC_O_blit_dst = '1' else - ADDR_O_scan; - busout_fifo_sel_in <= blit_dst_be; - busout_fifo_we_in <= CYC_O_blit_dst; - request_en <= bus_cycle_en and busout_fifo_we and busout_fifo_rdy; - CYC_O <= bus_cycle_en; - ------------------------------------------------------------------------------------- --- Bus request counter ------------------------------------------------------------------------------------- -proc_bus_request_counter: - process(CLK_I) - begin - if rising_edge(CLK_I) then - if request_cnt_rst = '1' then - request_cnt <= (others => '0'); - elsif request_en = '1' then - request_cnt <= request_cnt + 1; - end if; - end if; - end process; - -proc_bus_read_counter: - process(CLK_I) - begin - if rising_edge(CLK_I) then - if request_cnt_rst = '1' then - read_cnt <= (others => '0'); - elsif busin_fifo_dout_vld = '1' then - read_cnt <= read_cnt + 1; - end if; - end if; - end process; - -proc_bus_read_finish: - process(CLK_I) - begin - if rising_edge(CLK_I) then - bus_read_fin <= '0'; - if read_cnt = request_cnt then - bus_read_fin <= '1'; - end if; - end if; - end process; - ------------------------------------------------------------------------------------- --- VGA master FSM ------------------------------------------------------------------------------------- -vga_master_next: - process(CLK_I) - begin - if rising_edge(CLK_I) then - if RST_I = '1' then - s <= init; - else - s <= sn; - end if; - end if; - end process; - -vga_master: - process(s, stat_vga_rdy, vga_scan_dma_en2, fifo_almost_empty, fifo_almost_full, bus_read_fin, busout_fifo_empty, blit_request, blit_dst_suspend, blit_chunk_full, blitfifo_dout_vld, blit_src_finish, blitfifo_empty_read, blit_dst_finish, blit_const_color_en) - begin - - CYC_O_scan <= '0'; - STB_O_scan <= '0'; - CYC_O_blit_src <= '0'; - STB_O_blit_src <= '0'; - CYC_O_blit_dst <= '0'; - STB_O_blit_dst <= '0'; - request_cnt_rst <= '0'; - bus_read_en <= '0'; - bus_cycle_en <= '0'; - - sn <= s; - case s is - when init => - if stat_vga_rdy = '1' then - sn <= rdy; - end if; - - when rdy => - request_cnt_rst <= '1'; - if fifo_almost_empty = '1' and vga_scan_dma_en2 = '1' then - sn <= scan_bus_request; - elsif blit_request = '1' then -- ToDo: richtig prüfen anhand eines states wer dran ist. Nicht auf FIFO state prüfen - sn <= blit_dst_bus_request; - if blitfifo_dout_vld = '0' or blit_dst_suspend = '1' then - sn <= blit_src_bus_request; - if blit_const_color_en = '1' then - sn <= const_dst_bus_request; - end if; - end if; - end if; - - when scan_bus_request => - bus_cycle_en <= '1'; - CYC_O_scan <= '1'; - STB_O_scan <= '1'; - bus_read_en <= '1'; - if fifo_almost_full = '1' then - sn <= scan_bus_read; - end if; - - when scan_bus_read => - bus_cycle_en <= '1'; - CYC_O_scan <= '1'; - bus_read_en <= '1'; - if bus_read_fin = '1' then - sn <= rdy; - end if; - - when blit_src_bus_request => - bus_cycle_en <= '1'; - bus_read_en <= '1'; - CYC_O_blit_src <= '1'; - STB_O_blit_src <= '1'; - if blit_chunk_full = '1' or blit_src_finish = '1' then - STB_O_blit_src <= '0'; - sn <= blit_src_bus_read; - end if; - - when blit_src_bus_read => - bus_cycle_en <= '1'; - bus_read_en <= '1'; - CYC_O_blit_src <= '1'; - if bus_read_fin = '1' then - sn <= rdy; - end if; - - when blit_dst_bus_request => - bus_cycle_en <= '1'; - CYC_O_blit_dst <= '1'; - STB_O_blit_dst <= '1'; - if blitfifo_empty_read = '1' or blitfifo_dout_vld = '0' or blit_dst_finish = '1' then - STB_O_blit_dst <= '0'; - sn <= bus_fin; - end if; - - when const_dst_bus_request => - bus_cycle_en <= '1'; - CYC_O_blit_dst <= '1'; - STB_O_blit_dst <= '1'; - if blit_chunk_full = '1' or blit_dst_finish = '1' then - STB_O_blit_dst <= '0'; - sn <= bus_fin; - end if; - - when bus_fin => - bus_cycle_en <= '1'; - if busout_fifo_empty = '1' then - sn <= rdy; - end if; - - when others => - sn <= rdy; - - end case; - end process; - ---------------------------------------------------------------------------------- --- BLITTER ---------------------------------------------------------------------------------- -proc_blit_complete_int_flag: - process(CLK_I) - begin - if rising_edge(CLK_I) then - if RST_I = '1' or (blit_complete_int = '1' and blit_complete_int_ack = '1') then - blit_complete_int <= '0'; - elsif blit_finish_strobe(2) = '1' or (blit_complete_int = '0' and blit_complete_int_ack = '1') then - blit_complete_int <= '1'; - end if; - end if; - end process; - -proc_blit_cmd_empty_int_flag: - process(CLK_I) - begin - if rising_edge(CLK_I) then - if RST_I = '1' or (blit_cmd_empty_int = '1' and blit_cmd_empty_int_ack = '1') then - blit_cmd_empty_int <= '0'; - elsif (blit_finish_strobe(2) = '1' and blit_cmd_avail = '0') or (blit_cmd_empty_int = '0' and blit_cmd_empty_int_ack = '1') then - blit_cmd_empty_int <= '1'; - end if; - end if; - end process; - -proc_irq: - process(CLK_I) - begin - if rising_edge(CLK_I) then - if vga_scan_dma_en2 = '0' or bufchg_flag_ack = '1' then - bufchg_flag <= '0'; - elsif bufchg = '1' then - bufchg_flag <= '1'; - end if; - INT_O <= (bufchg_flag and bufchg_irq_en) - or (blit_complete_int and blit_complete_int_en) - or (blit_cmd_empty_int and blit_cmd_empty_int_en); - end if; - end process; - -proc_blit_reset: - process(CLK_I) - begin - if rising_edge(CLK_I) then - if RST_I = '1' then - blit_reset <= '1'; - blit_request <= '0'; - else - blit_reset <= (blit_cmd_avail and not blit_request) or (blit_request and blit_finish_strobe(0)); - blit_request <= blit_cmd_avail; - end if; - end if; - end process; - -proc_blit_chunk_counter: - process(CLK_I) - begin - if rising_edge(CLK_I) then - if request_cnt_rst = '1' then - blit_chunk_full <= '0'; - blit_chunk_cnt <= BLIT_CHUNK_SIZE-2; - elsif request_en = '1' then - if blit_chunk_cnt = 0 then - blit_chunk_full <= '1'; - else - blit_chunk_cnt <= blit_chunk_cnt - 1; - end if; - end if; - end if; - end process; - --- BLIT buffer low -inst_blitfifo_src0: entity work.fifo_sync - GENERIC MAP - ( - addr_width => NextExpBaseTwo(BLIT_CHUNK_SIZE), - data_width => 32, - - do_last_read_update => false - - ) - PORT MAP - ( - rst => blit_reset, - clk => CLK_I, - we => blitfifo_we(0), - re => blitfifo_re(0), - data_w => blitfifo_din(31 downto 0), - data_r => blitfifo_dout_0, - fifo_full => blitfifo_full(0), - fifo_empty => blitfifo_empty(0), - fifo_afull => open, - fifo_aempty => open - - ); - --- BLIT buffer high -inst_blitfifo_src1: entity work.fifo_sync - GENERIC MAP - ( - addr_width => NextExpBaseTwo(BLIT_CHUNK_SIZE), - data_width => 32, - - do_last_read_update => false - - ) - PORT MAP - ( - rst => blit_reset, - clk => CLK_I, - we => blitfifo_we(1), - re => blitfifo_re(1), - data_w => blitfifo_din(63 downto 32), - data_r => blitfifo_dout_1, - fifo_full => blitfifo_full(1), - fifo_empty => blitfifo_empty(1), - fifo_afull => open, - fifo_aempty => open - - ); - - blitfifo_din <= busin_fifo_dout; - blitfifo_write_en <= busin_fifo_dout_vld and CYC_O_blit_src; - blitfifo_read_en <= busout_fifo_rdy and CYC_O_blit_dst; - blitfifo_dout_vld <= not (blitfifo_empty(0) and blitfifo_empty(1)); - ---------------------------------------------------------------------------------- -blit_dst_be_gen: - process(dst_dbg) - begin - blit_dst_be <= "11111111"; - if dst_dbg.UNALIGNED = '1' then - if dst_dbg.FIRST = '1' then - blit_dst_be <= "00001111"; - elsif dst_dbg.LAST = '1' then - if dst_dbg.PARTIAL = '1' then - blit_dst_be <= "11110000"; - end if; - end if; - elsif dst_dbg.LAST = '1' then - if dst_dbg.PARTIAL = '1' then - blit_dst_be <= "00001111"; - end if; - end if; - end process; - -blitfifo_we_gen: - process(fill_dbg, blitfifo_write_en) - begin - blitfifo_we <= (blitfifo_write_en & blitfifo_write_en); - if fill_dbg.UNALIGNED = '1' then - if fill_dbg.FIRST = '1' then - blitfifo_we <= ('0' & blitfifo_write_en); - elsif fill_dbg.LAST = '1' then - if fill_dbg.PARTIAL = '1' then - blitfifo_we <= (blitfifo_write_en & '0'); - end if; - end if; - elsif fill_dbg.LAST = '1' then - if fill_dbg.PARTIAL = '1' then - blitfifo_we <= ('0' & blitfifo_write_en); - end if; - end if; - end process; - -blitfifo_re_gen: - process(dst_dbg, blitfifo_empty, blitfifo_read_en) - variable fifo_re : unsigned(1 downto 0); - variable empty_read : std_logic; - begin - fifo_re := (blitfifo_read_en & blitfifo_read_en); - if dst_dbg.UNALIGNED = '1' then - if dst_dbg.FIRST = '1' then - fifo_re := ('0' & blitfifo_read_en); - elsif dst_dbg.LAST = '1' then - if dst_dbg.PARTIAL = '1' then - fifo_re := (blitfifo_read_en & '0'); - end if; - end if; - elsif dst_dbg.LAST = '1' then - if dst_dbg.PARTIAL = '1' then - fifo_re := ('0' & blitfifo_read_en); - end if; - end if; - empty_read := (blitfifo_empty(0) and fifo_re(0)) or (blitfifo_empty(1) and fifo_re(1)); - blitfifo_re <= fifo_re and not (empty_read & empty_read); - blitfifo_empty_read <= empty_read; - end process; - -blit_dst_suspend_gen: - process(CLK_I) - begin - if rising_edge(CLK_I) then - if RST_I = '1' or blit_dst_finish = '1' or CYC_O_blit_src = '1' then - blit_dst_suspend <= '0'; - elsif blitfifo_read_en = '1' and blitfifo_empty_read = '1' then - blit_dst_suspend <= not (blitfifo_empty(0) and blitfifo_empty(1)); - end if; - end if; - end process; - - fill_dbg.LAST <= '1' when blit_fill_cnt_x_next = '0' & X"0000_0000" or blit_fill_cnt_x_next(32) = '1' else '0'; - fill_dbg.PARTIAL <= blit_fill_cnt_x_next(32); - - blit_fill_cnt_x_next <= ('0' & blit_fill_cnt_x - 1) when fill_dbg.FIRST = '1' and fill_dbg.UNALIGNED = '1' else ('0' & blit_fill_cnt_x - 2); - blit_fill_cnt_y_next <= ('0' & blit_fill_cnt_y) - 1; - --- BLIT Buffer fill address generator -blitfifo_fill_src_0: - process(CLK_I) - variable addr_next : unsigned(31 downto 0); - begin - if rising_edge(CLK_I) then - if RST_I = '1' or blit_reset = '1' then - blit_fill_addr <= blit_cmd_addr_src_0(2) & "00"; - blit_fill_cnt_x <= blit_cmd_nx; - blit_fill_cnt_y <= blit_cmd_ny; - blit_fill_offset <= blit_cmd_dimx_src_0(2 downto 0); - blit_fill_finish <= '0'; - fill_dbg.FIRST <= '1'; - fill_dbg.UNALIGNED <= blit_cmd_addr_src_0(2); - elsif blit_request = '1' and blit_fill_finish = '0' and blit_const_color_en = '0' and blitfifo_write_en = '1' then - fill_dbg.FIRST <= '0'; - if fill_dbg.LAST = '1' then - if blit_fill_cnt_y_next = ('0' & X"0000_0000") or blit_fill_cnt_y_next(32) = '1' then - blit_fill_finish <= '1'; - else - addr_next := (blit_cmd_addr_src_0(31 downto 2) & "00") + blit_fill_offset; - blit_fill_addr <= addr_next(2 downto 0); - blit_fill_offset <= blit_fill_offset + blit_cmd_dimx_src_0(2 downto 0); - blit_fill_cnt_x <= blit_cmd_nx; - blit_fill_cnt_y <= blit_fill_cnt_y_next(31 downto 0); - fill_dbg.FIRST <= '1'; - fill_dbg.UNALIGNED <= addr_next(2); - end if; - else - blit_fill_cnt_x <= blit_fill_cnt_x_next(31 downto 0); - blit_fill_addr <= (others => '0'); - end if; - end if; - end if; - end process; - - src_dbg.LAST <= '1' when blit_src_cnt_x_next = '0' & X"0000_0000" or blit_src_cnt_x_next(32) = '1' else '0'; - src_dbg.PARTIAL <= blit_src_cnt_x_next(32); - - blit_src_addr_next <= ADDR_O_blit_src + 8; - blit_src_cnt_x_next <= ('0' & blit_src_cnt_x - 1) when src_dbg.FIRST = '1' and src_dbg.UNALIGNED = '1' else ('0' & blit_src_cnt_x - 2); - blit_src_cnt_y_next <= ('0' & blit_src_cnt_y) - 1; - --- BLIT Source address generator -blit_request_addr_src: - process(CLK_I) - variable addr_next : unsigned(31 downto 0); - begin - if rising_edge(CLK_I) then - if RST_I = '1' or blit_reset = '1' then - ADDR_O_blit_src <= blit_cmd_addr_src_0(31 downto 2) & "00"; - blit_src_cnt_x <= blit_cmd_nx; - blit_src_cnt_y <= blit_cmd_ny; - blit_src_offset <= blit_cmd_dimx_src_0; - blit_src_finish <= '0'; - src_dbg.FIRST <= '1'; - src_dbg.UNALIGNED <= blit_cmd_addr_src_0(2); - elsif blit_request = '1' and blit_src_finish = '0' and blit_const_color_en = '0' and (STB_O_blit_src = '1' and busout_fifo_rdy = '1') then - src_dbg.FIRST <= '0'; - if src_dbg.LAST = '1' then - if blit_src_cnt_y_next = ('0' & X"0000_0000") or blit_src_cnt_y_next(32) = '1' then - blit_src_finish <= '1'; - else - addr_next := (blit_cmd_addr_src_0(31 downto 2) & "00") + blit_src_offset; - ADDR_O_blit_src <= addr_next; - blit_src_offset <= blit_src_offset + blit_cmd_dimx_src_0; - blit_src_cnt_x <= blit_cmd_nx; - blit_src_cnt_y <= blit_src_cnt_y_next(31 downto 0); - src_dbg.FIRST <= '1'; - src_dbg.UNALIGNED <= addr_next(2); - end if; - else - ADDR_O_blit_src <= blit_src_addr_next; - blit_src_cnt_x <= blit_src_cnt_x_next(31 downto 0); - end if; - end if; - end if; - end process; - - - dst_dbg.LAST <= '1' when blit_dst_cnt_x_next = '0' & X"0000_0000" or blit_dst_cnt_x_next(32) = '1' else '0'; - dst_dbg.PARTIAL <= blit_dst_cnt_x_next(32); - - blit_dst_addr_next <= ADDR_O_blit_dst + 8; - blit_dst_cnt_x_next <= ('0' & blit_dst_cnt_x - 1) when dst_dbg.FIRST = '1' and dst_dbg.UNALIGNED = '1' else ('0' & blit_dst_cnt_x - 2); - blit_dst_cnt_y_next <= ('0' & blit_dst_cnt_y) - 1; - --- BLIT Destination address generator -blit_request_addr_dst: - process(CLK_I) - variable addr_next : unsigned(31 downto 0); - begin - if rising_edge(CLK_I) then - blit_finish_strobe <= blit_finish_strobe(blit_finish_strobe'left-1 downto 0) & '0'; - if RST_I = '1' then - blit_finish_strobe <= (others =>'0'); - elsif blit_reset = '1' then - ADDR_O_blit_dst <= blit_cmd_addr_dst(31 downto 2) & "00"; - blit_dst_cnt_x <= blit_cmd_nx; - blit_dst_cnt_y <= blit_cmd_ny; - blit_dst_offset <= blit_cmd_dimx_dst; - blit_dst_finish <= '0'; - dst_dbg.FIRST <= '1'; - dst_dbg.UNALIGNED <= blit_cmd_addr_dst(2); - elsif blit_request = '1' and blit_dst_finish = '0' and (STB_O_blit_dst = '1' and busout_fifo_rdy = '1') then - dst_dbg.FIRST <= '0'; - if dst_dbg.LAST = '1' then - if blit_dst_cnt_y_next = ('0' & X"0000_0000") or blit_dst_cnt_y_next(32) = '1' then - blit_dst_finish <= '1'; - blit_finish_strobe(0) <= '1'; - else - addr_next := (blit_cmd_addr_dst(31 downto 2) & "00") + blit_dst_offset; - ADDR_O_blit_dst <= addr_next; - blit_dst_offset <= blit_dst_offset + blit_cmd_dimx_dst; - blit_dst_cnt_x <= blit_cmd_nx; - blit_dst_cnt_y <= blit_dst_cnt_y_next(31 downto 0); - dst_dbg.FIRST <= '1'; - dst_dbg.UNALIGNED <= addr_next(2); - end if; - else - ADDR_O_blit_dst <= blit_dst_addr_next; - blit_dst_cnt_x <= blit_dst_cnt_x_next(31 downto 0); - end if; - end if; - end if; - end process; - ---------------------------------------------------------------------------------- --- Character generator ---------------------------------------------------------------------------------- -inst_char_gen : entity work.char_gen - GENERIC MAP - ( - tsvga => tsvga, - CHARACTER_SCALE => 1, - CHAR_ROM_SIZE_X => 8, -- Pixels - CHAR_ROM_SIZE_Y => 16, -- Pixels - CHAR_ROM_DEPTH => 256, -- Chars - MAX_CHAR_PER_LINE => 80, -- Chars - MAX_LINE_PER_FRAME => 32, -- Chars - CHAR_SPACING_X => 0, -- Pixels - CHAR_SPACING_Y => 0, -- Pixels - SCREEN_OFFSET_X => 16, -- Pixels - SCREEN_OFFSET_Y => 16 -- Pixels - ) - PORT MAP - ( - rst => RST_I, - sys_clk => CLK_I, - vga_clk => vga_clk_in, - ce => cg_en, - frame_pulse => scan_rdy, - clr_screen => cg_clr_screen, - clr_line => cg_clr_line, - din => cg_din, - dout => cg_dout, - ascii_we => cg_ascii_we, - posy_we => cg_posy_we, - posx_we => cg_posx_we, - ready => cg_rdy, - scan_pos_x_in => stat_hpos, - scan_pos_y_in => stat_vpos, - csr_pos_x_out => cg_csr_pos_x, - csr_pos_y_out => cg_csr_pos_y, - char_draw_en => cg_draw - ); - scan_rdy <= stat_hready and stat_vready; - cg_en <= stat_scan; - ---------------------------------------------------------------------------------- --- JBUS registers ---------------------------------------------------------------------------------- -registers_read: - process(CLK_I) - begin - if rising_edge(CLK_I) then - ACK_O <= '0'; - reg_read_vld <= '0'; - if CYC_I = '1' and WE_I = '0' then - ACK_O <= reg_read_vld; - reg_read_vld <= STB_I; - - SDAT_O <= (others => '0'); - case ADDR_I(6 downto 2) is - - -- sys_vga_ctrl - -- 0x00 - when "00000" => - SDAT_O(0) <= cg_rdy; - SDAT_O(1) <= vga_scan_dma_en; - SDAT_O(2) <= bufchg_irq_en; - SDAT_O(3) <= bufchg_flag; - SDAT_O(8) <= blit_cmd_bsy; - SDAT_O(9) <= blit_complete_int; - SDAT_O(10) <= blit_complete_int_en; - SDAT_O(11) <= blit_cmd_empty_int; - SDAT_O(12) <= blit_cmd_empty_int_en; - SDAT_O(23 downto 16) <= blit_reg_func(7 downto 0); - SDAT_O(31) <= blit_request; -- RO: Blitter is active. Blit jobs avaliable in CMD-FIFO - - -- sys_vga_ascii - -- 0x04 - when "00001" => - SDAT_O(7 downto 0) <= cg_dout; - - -- sys_vga_posx - -- 0x08 - when "00010" => - SDAT_O(7 downto 0) <= to_unsigned(cg_csr_pos_x, 8); - - -- sys_vga_posy - -- 0x0C - when "00011" => - SDAT_O(7 downto 0) <= to_unsigned(cg_csr_pos_y, 8); - - -- sys_vga_cgcol - -- 0x10 - when "00100" => - SDAT_O <= to_unsigned(cg_color); - - -- sys_vga_res - -- 0x14 - when "00101" => - SDAT_O <= to_unsigned(tsvga.nfps, 8) & to_unsigned(tsvga.ts_v.ncyc_scan, 12) & to_unsigned(tsvga.ts_h.ncyc_scan, 12); - - -- sys_vga_fb_front - -- 0x18 - when "00110" => - SDAT_O <= vga_fb_front; - - -- sys_vga_fb_back - -- 0x1C - when "00111" => - SDAT_O <= vga_fb_back; - - -- sys_blit_descr_src_0 - -- 0x20 - when "01000" => - SDAT_O <= blit_reg_addr_src_0; - - -- 0x24 - when "01001" => - SDAT_O <= blit_reg_dimx_src_0; - - -- sys_blit_descr_src_1 - -- 0x30 - when "01100" => - SDAT_O <= blit_reg_addr_src_1; - - -- 0x34 - when "01101" => - SDAT_O <= blit_reg_dimx_src_1; - - -- sys_blit_descr_dst - -- 0x40 - when "10000" => - SDAT_O <= blit_reg_addr_dst; - - -- 0x44 - when "10001" => - SDAT_O <= blit_reg_dimx_dst; - - -- sys_blit_reg_nx - -- 0x50 - when "10100" => - SDAT_O <= blit_reg_nx; - - -- sys_blit_reg_ny - -- 0x54 - when "10101" => - SDAT_O <= blit_reg_ny; - - -- sys_blit_color - -- 0x58 - when "10110" => - SDAT_O <= blit_reg_const_color; - - when others => null; - end case; - end if; - end if; - end process; - - -registers_write: - process(CLK_I) - begin - if rising_edge(CLK_I) then - cg_ascii_we <= '0'; - cg_posy_we <= '0'; - cg_posx_we <= '0'; - cg_clr_screen <= '0'; - cg_clr_line <= '0'; - bufchg_flag_ack <= '0'; - blit_request_set <= '0'; - blit_complete_int_ack <= '0'; - blit_cmd_empty_int_ack <= '0'; - if RST_I = '1' then - cg_din <= (others => '0'); - vga_scan_dma_en <= '0'; - bufchg_irq_en <= '0'; - blit_complete_int_en <= '0'; - blit_cmd_empty_int_en <= '0'; - blit_reg_func <= (others => '0'); - blit_reg_addr_src_0 <= (others => '0'); - blit_reg_addr_src_1 <= (others => '0'); - blit_reg_dimx_src_0 <= (others => '0'); - blit_reg_dimx_src_1 <= (others => '0'); - blit_reg_addr_dst <= (others => '0'); - blit_reg_dimx_dst <= (others => '0'); - blit_reg_nx <= (others => '0'); - blit_reg_ny <= (others => '0'); - host_fb_front <= (others => '0'); - host_fb_back <= (others => '0'); - cg_color <= (X"FF", X"FF", X"FF", X"FF"); - elsif (STB_I and CYC_I and WE_I) = '1' then - case ADDR_I(6 downto 2) is - - -- sys_vga_ctrl - -- 0x00 - when "00000" => - vga_scan_dma_en <= SDAT_I(1); - bufchg_irq_en <= SDAT_I(2); - bufchg_flag_ack <= SDAT_I(3); - cg_clr_screen <= SDAT_I(4); - cg_clr_line <= SDAT_I(5); - blit_request_set <= SDAT_I(8); - blit_complete_int_ack <= SDAT_I(9); - blit_complete_int_en <= SDAT_I(10); - blit_cmd_empty_int_ack <= SDAT_I(11); - blit_cmd_empty_int_en <= SDAT_I(12); - blit_reg_func <= SDAT_I(23 downto 16); - - -- sys_vga_ascii - -- 0x04 - when "00001" => - cg_ascii_we <= '1'; - cg_din <= SDAT_I(7 downto 0); - - -- sys_vga_posx - -- 0x08 - when "00010" => - cg_posx_we <= '1'; - cg_din <= SDAT_I(7 downto 0); - - -- sys_vga_posy - -- 0x0C - when "00011" => - cg_posy_we <= '1'; - cg_din <= SDAT_I(7 downto 0); - - -- sys_vga_cgcol - -- 0x10 - when "00100" => - cg_color <= to_color_t(SDAT_I(31 downto 0)); - - -- sys_vga_fb_front - -- 0x18 - when "00110" => - host_fb_front <= SDAT_I(31 downto 3) & "000"; - - -- sys_vga_fb_back - -- 0x1C - when "00111" => - bufchg_flag_ack <= '1'; - host_fb_back <= SDAT_I(31 downto 3) & "000"; - - -- sys_blit_descr_src_0 - -- 0x20 - when "01000" => - blit_reg_addr_src_0 <= SDAT_I(31 downto 0); - - -- 0x24 - when "01001" => - blit_reg_dimx_src_0 <= SDAT_I(29 downto 0) & "00"; - - -- sys_blit_descr_src_1 - -- 0x30 - when "01100" => - blit_reg_addr_src_1 <= SDAT_I(31 downto 0); - - -- 0x34 - when "01101" => - blit_reg_dimx_src_1 <= SDAT_I(29 downto 0) & "00"; - - -- sys_blit_descr_dst - -- 0x40 - when "10000" => - blit_reg_addr_dst <= SDAT_I(31 downto 0); - - -- 0x44 - when "10001" => - blit_reg_dimx_dst <= SDAT_I(29 downto 0) & "00"; - - -- sys_blit_reg_nx - -- 0x50 - when "10100" => - blit_reg_nx <= SDAT_I; - - -- sys_blit_reg_ny - -- 0x54 - when "10101" => - blit_reg_ny <= SDAT_I; - - -- sys_blit_color - -- 0x58 - when "10110" => - blit_reg_const_color <= SDAT_I; - - when others => null; - end case; - - end if; - end if; - end process; - - --------------------------------------------------------------------------------------------- - -end Behavioral; diff --git a/lib/VGA_ctrl/src/vga_sync.vhd b/lib/VGA_ctrl/src/vga_sync.vhd deleted file mode 100644 index 56e4384..0000000 --- a/lib/VGA_ctrl/src/vga_sync.vhd +++ /dev/null @@ -1,127 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 11:15:39 10/21/05 --- Design Name: --- Module Name: fsm_scan - Behavioral --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -use work.vga_types.all; - -entity vga_sync is - Generic - ( - ts : scan_timespec_t := (4,2,1,3,'0') - ); - Port - ( - rst : in std_logic; - clk : in std_logic; - ce : in std_logic; - pos : out natural range 0 to ts.ncyc_scan-1; - sync : out std_logic; - is_scan : out std_logic; - rdy_scan : out std_logic - ); - end vga_sync; - -architecture Behavioral of vga_sync is - - type timing_state_t is (st_init, st_scan, st_front, st_sync, st_back); - - -- Counter - signal state, next_state : timing_state_t; - signal count_srst : std_logic; - signal count : natural range 0 to ts.ncyc_scan-1; - -begin - - pos <= count; - ---------------------------------------------------------------------------------------------- -counter: - process (clk) - begin - if rising_edge(clk) then - if ce = '1' then - if count_srst = '1' then - count <= 0; - else - count <= count + 1; - end if; - end if; - end if; - end process; - ---------------------------------------------------------------------------------------------- -SYNC_TIMING: -process (state, count) - begin - count_srst <= '0'; - rdy_scan <= '0'; - is_scan <= '0'; - sync <= '0'; - - next_state <= state; --default is to stay in current state - - case (state) is - - when st_init => - count_srst <= '1'; - next_state <= st_front; - when st_front => - if count = ts.ncyc_porch_front - 1 then - count_srst <= '1'; - next_state <= st_sync; - end if; - when st_sync => - sync <= '1'; - if count = ts.ncyc_sync_pulse - 1 then - count_srst <= '1'; - next_state <= st_back; - end if; - when st_back => - if count = ts.ncyc_porch_back - 1 then - count_srst <= '1'; - next_state <= st_scan; - end if; - when st_scan => - is_scan <= '1'; - if count = ts.ncyc_scan - 1 then - count_srst <= '1'; - rdy_scan <= '1'; - next_state <= st_front; - end if; - when others => - next_state <= st_init; - - end case; - end process; - -SYNC_TIMING_NEXT: - process (rst, clk) - begin - if rst = '1' then - state <= st_init; - elsif rising_edge(clk) and ce = '1' then - state <= next_state; - end if; - end process; - ---------------------------------------------------------------------------------------------- -end Behavioral; diff --git a/lib/VGA_ctrl/src/vga_timing.vhd b/lib/VGA_ctrl/src/vga_timing.vhd deleted file mode 100644 index c110652..0000000 --- a/lib/VGA_ctrl/src/vga_timing.vhd +++ /dev/null @@ -1,102 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 11:25:45 10/15/05 --- Design Name: --- Module Name: vga_ctrl_core - Behavioral --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -use work.vga_types.all; - -entity vga_timing is - Generic - ( - tsvga : vga_timespec_t := ts_vga_800_600_72 - ); - Port - ( - sys_rst : in std_logic; - vga_clk : in std_logic; - vga_ce : in std_logic; - sync_h : out std_logic; - sync_v : out std_logic; - scan_pos_h : out natural range 0 to tsvga.ts_h.ncyc_scan-1; - scan_pos_v : out natural range 0 to tsvga.ts_v.ncyc_scan-1; - is_scan_h : out std_logic; - is_scan_v : out std_logic; - scan_rdy_h : out std_logic; - scan_rdy_v : out std_logic - ); -end vga_timing; - -architecture Behavioral of vga_timing is - - --------------------------------------------------------------------------------------------- - signal is_scan_h_i : std_logic; - signal is_scan_v_i : std_logic; - signal scan_rdy_h_i : std_logic; - signal scan_rdy_v_i : std_logic; - signal sync_h_i : std_logic; - signal sync_v_i : std_logic; - - --------------------------------------------------------------------------------------------- -begin - - is_scan_h <= is_scan_h_i; - is_scan_v <= is_scan_v_i; - scan_rdy_h <= scan_rdy_h_i; - scan_rdy_v <= scan_rdy_v_i; - sync_h <= sync_h_i; - sync_v <= sync_v_i; - - --------------------------------------------------------------------------------------------- - inst_vga_sync_h: entity work.vga_sync - GENERIC MAP - ( - ts => tsvga.ts_h - ) - PORT MAP - ( - rst => sys_rst, - clk => vga_clk, - ce => vga_ce, - pos => scan_pos_h, - sync => sync_h_i, - is_scan => is_scan_h_i, - rdy_scan => scan_rdy_h_i - ); - - inst_vga_sync_v: entity work.vga_sync - GENERIC MAP - ( - ts => tsvga.ts_v - ) - PORT MAP - ( - rst => sys_rst, - clk => vga_clk, - ce => scan_rdy_h_i, - pos => scan_pos_v, - sync => sync_v_i, - is_scan => is_scan_v_i, - rdy_scan => scan_rdy_v_i - ); - ---------------------------------------------------------------------------------------------- - -end Behavioral; diff --git a/lib/VGA_ctrl/src/vga_types.vhd b/lib/VGA_ctrl/src/vga_types.vhd deleted file mode 100644 index e8fa93e..0000000 --- a/lib/VGA_ctrl/src/vga_types.vhd +++ /dev/null @@ -1,158 +0,0 @@ --- Package File Template --- --- Purpose: This package defines supplemental types, subtypes, --- constants, and functions - - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; -use IEEE.MATH_REAL.ALL; - -package vga_types is - - -- Constants - constant VGA_NUM_CH : natural := 2; - - -- Types - type color_range_t is (r, g, b, a); - type color_t is array (color_range_t) of unsigned(7 downto 0); - type color_array_t is array (0 to VGA_NUM_CH-1) of color_t; - - type color_op_t is (op_over, op_xor, op_alpha); - - type scan_timespec_t is - record - ncyc_scan : integer; - ncyc_porch_front : integer; - ncyc_sync_pulse : integer; - ncyc_porch_back : integer; - sync_polarity : std_logic; - end record; - - type vga_timespec_t is - record - f_pxl_clk : integer; - nfps : integer; - ts_h : scan_timespec_t; - ts_v : scan_timespec_t; - end record; - - ----------------------------------------------------------------------- - -- Common timimg specifications - ----------------------------------------------------------------------- - -- For test bench (not for H/W use) - constant ts_vga_testbench : vga_timespec_t := - ( - f_pxl_clk => 40E6, - nfps => 6, - ts_h => (80,5,2,3,'0'), - ts_v => (60,4,2,3,'0') - ); - - -- 640 x 480 @ 60 Hz (not recommended) - constant ts_vga_640_480_60 : vga_timespec_t := - ( - f_pxl_clk => 25175000, - nfps => 60, - ts_h => (640,16,96,48,'0'), - ts_v => (480,11,2,31,'0') - ); - - -- 640 x 480 @ 72 Hz (not recommended) - constant ts_vga_640_480_72 : vga_timespec_t := - ( - f_pxl_clk => 31500000, - nfps => 72, - ts_h => (640,24,40,128,'0'), - ts_v => (480,9,3,28,'0') - ); - - -- 800 x 600 @ 60 Hz (OK) - constant ts_vga_800_600_60 : vga_timespec_t := - ( - f_pxl_clk => 40000000, - nfps => 60, - ts_h => (800,40,128,88,'0'), - ts_v => (600,1,4,23,'0') - ); - - -- 800 x 600 @ 72 Hz (OK) - constant ts_vga_800_600_72 : vga_timespec_t := - ( - f_pxl_clk => 50000000, - nfps => 72, - ts_h => (800,56,120,64,'0'), - ts_v => (600,37,6,23,'0') - ); - - -- 1024 x 768 @ 60 Hz (Noisy) - constant ts_vga_1024_768_60 : vga_timespec_t := - ( - f_pxl_clk => 65000000, - nfps => 60, - ts_h => (1024,24,136,160,'0'), - ts_v => (768,3,6,29,'0') - ); - - -- 1024 x 768 @ 70 Hz (OK) - constant ts_vga_1024_768_70 : vga_timespec_t := - ( - f_pxl_clk => 75000000, - nfps => 70, - ts_h => (1024,24,136,144,'0'), - ts_v => (768,3,6,29,'0') - ); - - -- 1280 x 1024 @ 70 Hz (Noisy) - constant ts_vga_1280_1024_70 : vga_timespec_t := - ( - f_pxl_clk => 125000000, - nfps => 70, - ts_h => (1280,16,176,192,'0'), - ts_v => (1024,3,3,42,'0') - ); - - -- 1280 x 1024 @ 72 Hz (OK) - constant ts_vga_1280_1024_72 : vga_timespec_t := - ( - f_pxl_clk => 130000000, - nfps => 72, - ts_h => (1280,32,160,224,'0'), - ts_v => (1024,2,2,33,'0') - ); - - -- Functions - function to_color_t(x : unsigned) return color_t; - function to_unsigned(x : color_t) return unsigned; - -end vga_types; - - -package body vga_types is - - function to_color_t(x : unsigned) return color_t is - variable result : color_t; - begin - result(r) := x(x'right+7 downto x'right+0); - result(g) := x(x'right+15 downto x'right+8); - result(b) := x(x'right+23 downto x'right+16); - result(a) := x(x'right+31 downto x'right+24); - - return result; - end to_color_t; - - function to_unsigned(x : color_t) return unsigned is - variable result : unsigned(31 downto 0); - begin - result(7 downto 0) := x(r); - result(15 downto 8) := x(g); - result(23 downto 16) := x(b); - result(31 downto 24) := x(a); - - return result; - end to_unsigned; - -end vga_types; - - diff --git a/lib/VGA_ctrl/todo.txt b/lib/VGA_ctrl/todo.txt deleted file mode 100644 index e20e96d..0000000 --- a/lib/VGA_ctrl/todo.txt +++ /dev/null @@ -1,21 +0,0 @@ -2009-11-04 -- char_gen.vhdl: add csr_posx_out, csr_posy_out to port. Make it register readable (done 2009-11-04) -- several async. resets recognized. Sync. resets better? -- Make screen width, screen height and FPS register readable (done 2009-11-04) - -2009-11-08 -- Double-buffering to reduce artifacts on buffer write by host and buffer read by VGA master. - currently double-buffer can only be updatetd if msten = 0. Buffer updates should be always possible - for large screen change, which need more time than one frame. (done 2009-11-08) -- VGA-INT every n-th buffer change? - -2009-11-11 -- adding a blitter for blockcopy of whole frame or box region. (done 2009-11-22) -- Adding blitter capability to read from three sources (image 1, image 2 and mask), manipulate and store back of whole frame or box region - -2009-11-25 -- Adding blitter capability to read/write single 32-Bit words (and even bytes) -- Adding blitter capability to blit constant color -- Increase BLIT_CHUNKSIZE to LINEFIFO_DEPTH/2 for more performance (needs modification to FSM) - - diff --git a/lib/ac97_ctrl/sim/tb_ac97_wb.fdo b/lib/ac97_ctrl/sim/tb_ac97_wb.fdo deleted file mode 100644 index bbdc249..0000000 --- a/lib/ac97_ctrl/sim/tb_ac97_wb.fdo +++ /dev/null @@ -1,20 +0,0 @@ -## NOTE: Do not edit this file. -## Autogenerated by ProjNav (creatfdo.tcl) on Tue Jun 05 17:37:16 Westeuropäische Normalzeit 2007 -## -vlib work -vcom -explicit -93 "../../FIFO/src/fifo_ctrl_pkg.vhd" -vcom -explicit -93 "../../FIFO/src/fifo_sync_ctrl.vhd" -vcom -explicit -93 "../../misc/dpram_1w1r_dist.vhd" -vcom -explicit -93 "../../FIFO/src/fifo_sync_dist.vhd" -vcom -explicit -93 "../../misc/singleshot.vhd" -vcom -explicit -93 "../src/core/ac_out.vhd" -vcom -explicit -93 "../src/core/ac_in.vhd" -vcom -explicit -93 "../src/core/ac_io.vhd" -vcom -explicit -93 "../src/core/ac97_wb.vhd" -vcom -explicit -93 "../src/tb_ac97_wb.vhd" -vsim -t 1ps -lib work tb_ac97_wb -do {tb_ac97_wb.wdo} -view wave -view structure -view signals -run 700us diff --git a/lib/ac97_ctrl/sim/tb_ac97_wb.wdo b/lib/ac97_ctrl/sim/tb_ac97_wb.wdo deleted file mode 100644 index f7e1885..0000000 --- a/lib/ac97_ctrl/sim/tb_ac97_wb.wdo +++ /dev/null @@ -1,77 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_ac97_wb/clk_o -add wave -noupdate -format Logic /tb_ac97_wb/rst_o -add wave -noupdate -format Logic /tb_ac97_wb/int_i -add wave -noupdate -format Logic /tb_ac97_wb/cyc_o -add wave -noupdate -format Logic /tb_ac97_wb/stb_o -add wave -noupdate -format Logic /tb_ac97_wb/we_o -add wave -noupdate -format Logic /tb_ac97_wb/ack_i -add wave -noupdate -format Logic /tb_ac97_wb/mrdy_o -add wave -noupdate -format Logic /tb_ac97_wb/srdy_i -add wave -noupdate -format Literal -radix hexadecimal /tb_ac97_wb/addr_o -add wave -noupdate -format Literal -radix hexadecimal /tb_ac97_wb/dat_i -add wave -noupdate -format Literal -radix hexadecimal /tb_ac97_wb/dat_o -add wave -noupdate -format Logic /tb_ac97_wb/dout_rst -add wave -noupdate -format Literal -radix hexadecimal /tb_ac97_wb/dout_reg -add wave -noupdate -format Literal /tb_ac97_wb/dout_cnt -add wave -noupdate -format Logic /tb_ac97_wb/ac97_bit_clk -add wave -noupdate -format Logic /tb_ac97_wb/ac97_reset_n -add wave -noupdate -format Logic /tb_ac97_wb/ac97_sdata_out -add wave -noupdate -format Logic /tb_ac97_wb/ac97_ssync -add wave -noupdate -format Logic /tb_ac97_wb/ac97_sdata_in -add wave -noupdate -divider UUT -add wave -noupdate -format Logic /tb_ac97_wb/uut/cmd_reg_we -add wave -noupdate -format Logic /tb_ac97_wb/uut/cmd_pending -add wave -noupdate -format Literal -radix hexadecimal /tb_ac97_wb/uut/ac_cmd_data -add wave -noupdate -format Literal -radix hexadecimal /tb_ac97_wb/uut/ac_cmd_addr -add wave -noupdate -format Logic /tb_ac97_wb/uut/ac_cmd_we -add wave -noupdate -format Logic /tb_ac97_wb/uut/ac_tx_pcm_we -add wave -noupdate -format Literal -radix hexadecimal /tb_ac97_wb/uut/stat_reg -add wave -noupdate -format Logic /tb_ac97_wb/uut/stat_reg_re -add wave -noupdate -format Logic /tb_ac97_wb/uut/stat_pending -add wave -noupdate -format Literal -radix hexadecimal /tb_ac97_wb/uut/ac_stat_data -add wave -noupdate -format Literal -radix hexadecimal /tb_ac97_wb/uut/ac_stat_addr -add wave -noupdate -format Literal /tb_ac97_wb/uut/ac_tx_pcm_addr -add wave -noupdate -format Literal /tb_ac97_wb/uut/ac_rx_pcm_addr -add wave -noupdate -format Literal /tb_ac97_wb/uut/ac_sync_strobe -add wave -noupdate -format Literal /tb_ac97_wb/uut/ac_slot_valid -add wave -noupdate -format Logic /tb_ac97_wb/uut/ac_ready -add wave -noupdate -format Logic /tb_ac97_wb/uut/tx_data_start -add wave -noupdate -format Logic /tb_ac97_wb/clk_o -add wave -noupdate -format Logic /tb_ac97_wb/uut/sync_status -add wave -noupdate -format Logic /tb_ac97_wb/uut/sync_frame -add wave -noupdate -format Logic /tb_ac97_wb/uut/rx_frame_valid -add wave -noupdate -format Logic /tb_ac97_wb/uut/sync_tx -add wave -noupdate -format Literal /tb_ac97_wb/uut/request -add wave -noupdate -format Literal -radix hexadecimal /tb_ac97_wb/uut/tx_fifo_din -add wave -noupdate -format Literal -radix hexadecimal /tb_ac97_wb/uut/tx_fifo_dout -add wave -noupdate -format Logic /tb_ac97_wb/uut/tx_fifo_re -add wave -noupdate -format Logic /tb_ac97_wb/uut/tx_fifo_we -add wave -noupdate -format Logic /tb_ac97_wb/uut/tx_fifo_full -add wave -noupdate -format Logic /tb_ac97_wb/uut/tx_fifo_empty -add wave -noupdate -format Logic /tb_ac97_wb/uut/rx_data_start -add wave -noupdate -format Logic /tb_ac97_wb/clk_o -add wave -noupdate -format Literal -radix hexadecimal /tb_ac97_wb/uut/rx_fifo_din -add wave -noupdate -format Literal -radix hexadecimal /tb_ac97_wb/uut/rx_fifo_dout -add wave -noupdate -format Logic /tb_ac97_wb/uut/rx_fifo_re -add wave -noupdate -format Logic /tb_ac97_wb/uut/rx_fifo_we -add wave -noupdate -format Logic /tb_ac97_wb/uut/rx_fifo_full -add wave -noupdate -format Logic /tb_ac97_wb/uut/rx_fifo_empty -add wave -noupdate -format Literal -radix hexadecimal /tb_ac97_wb/uut/ac97_stat -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 4} {200000401 ps} 0} {{Cursor 2} {699514236 ps} 0} {{Cursor 4} {4999959266 ps} 0} -configure wave -namecolwidth 173 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -update -WaveRestoreZoom {699260742 ps} {700038909 ps} diff --git a/lib/ac97_ctrl/sim/tb_ac_in.fdo b/lib/ac97_ctrl/sim/tb_ac_in.fdo deleted file mode 100644 index fd7fb1f..0000000 --- a/lib/ac97_ctrl/sim/tb_ac_in.fdo +++ /dev/null @@ -1,14 +0,0 @@ -## NOTE: Do not edit this file. -## Autogenerated by ProjNav (creatfdo.tcl) on Tue Jun 05 17:37:16 Westeuropäische Normalzeit 2007 -## -vlib work -vcom -explicit -93 "../../../lib/src/misc/singleshot.vhd" -vcom -explicit -93 "../src/core/ac_out.vhd" -vcom -explicit -93 "../src/core/ac_in.vhd" -vcom -explicit -93 "../src/tb_ac_in.vhd" -vsim -t 1ps -lib work tb_ac_in -do {tb_ac_in.wdo} -view wave -view structure -view signals -run 700us diff --git a/lib/ac97_ctrl/sim/tb_ac_in.wdo b/lib/ac97_ctrl/sim/tb_ac_in.wdo deleted file mode 100644 index a7d0e35..0000000 --- a/lib/ac97_ctrl/sim/tb_ac_in.wdo +++ /dev/null @@ -1,43 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_ac_in/uut/rst -add wave -noupdate -format Logic /tb_ac_in/uut/clk -add wave -noupdate -format Logic /tb_ac_in/uut/sync_frame -add wave -noupdate -format Logic /tb_ac_in/uut/sync_status -add wave -noupdate -divider {AC97 lines} -add wave -noupdate -format Logic /tb_ac_in/uut/ac_reset -add wave -noupdate -format Logic /tb_ac_in/uut/ac_bit_clk -add wave -noupdate -format Logic /tb_ac_in/uut/ac_sdata_in -add wave -noupdate -format Logic /tb_ac_in/uut/ac_ssync -add wave -noupdate -divider Debug -add wave -noupdate -format Literal -radix hexadecimal /tb_ac_in/uut/stat_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_ac_in/uut/stat_data -add wave -noupdate -format Literal /tb_ac_in/uut/pcm_out_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_ac_in/uut/pcm_out_data -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_ac_in/uut/data_array -add wave -noupdate -format Literal -radix hexadecimal /tb_ac_in/uut/tag -add wave -noupdate -format Literal /tb_ac_in/uut/sac -add wave -noupdate -format Literal /tb_ac_in/uut/bitcnt -add wave -noupdate -format Literal /tb_ac_in/uut/slotcnt -add wave -noupdate -format Literal -radix hexadecimal /tb_ac_in/uut/rx_reg -add wave -noupdate -format Logic /tb_ac_in/uut/stat_read -add wave -noupdate -format Logic /tb_ac_in/uut/host_update -add wave -noupdate -format Logic /tb_ac_in/uut/slot_end -add wave -noupdate -format Logic /tb_ac_in/uut/sync_end -add wave -noupdate -format Logic /tb_ac_in/uut/last_slot -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {53431686 ps} 0} {{Cursor 2} {44308511 ps} 0} {{Cursor 4} {677821715 ps} 0} -configure wave -namecolwidth 173 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -update -WaveRestoreZoom {52190046 ps} {56168939 ps} diff --git a/lib/ac97_ctrl/sim/tb_ac_io.fdo b/lib/ac97_ctrl/sim/tb_ac_io.fdo deleted file mode 100644 index 4b0180f..0000000 --- a/lib/ac97_ctrl/sim/tb_ac_io.fdo +++ /dev/null @@ -1,15 +0,0 @@ -## NOTE: Do not edit this file. -## Autogenerated by ProjNav (creatfdo.tcl) on Tue Jun 05 17:37:16 Westeuropäische Normalzeit 2007 -## -vlib work -vcom -explicit -93 "../../../lib/misc/singleshot.vhd" -vcom -explicit -93 "../src/core/ac_out.vhd" -vcom -explicit -93 "../src/core/ac_in.vhd" -vcom -explicit -93 "../src/core/ac_io.vhd" -vcom -explicit -93 "../src/tb_ac_io.vhd" -vsim -t 1ps -lib work tb_ac_io -do {tb_ac_io.wdo} -view wave -view structure -view signals -run 700us diff --git a/lib/ac97_ctrl/sim/tb_ac_io.wdo b/lib/ac97_ctrl/sim/tb_ac_io.wdo deleted file mode 100644 index b445bdb..0000000 --- a/lib/ac97_ctrl/sim/tb_ac_io.wdo +++ /dev/null @@ -1,51 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_ac_io/uut/rst -add wave -noupdate -format Logic /tb_ac_io/uut/clk -add wave -noupdate -format Logic /tb_ac_io/uut/ready -add wave -noupdate -format Literal /tb_ac_io/uut/slot_valid -add wave -noupdate -format Logic /tb_ac_io/uut/sync_strobe -add wave -noupdate -format Literal -radix hexadecimal /tb_ac_io/uut/stat_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_ac_io/uut/stat_data -add wave -noupdate -format Literal /tb_ac_io/uut/rx_pcm_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_ac_io/uut/rx_pcm_data -add wave -noupdate -format Literal -radix hexadecimal /tb_ac_io/uut/cmd_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_ac_io/uut/cmd_data -add wave -noupdate -format Logic /tb_ac_io/uut/cmd_we -add wave -noupdate -format Literal -radix hexadecimal /tb_ac_io/uut/tx_pcm_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_ac_io/uut/tx_pcm_data -add wave -noupdate -format Logic /tb_ac_io/uut/tx_pcm_we -add wave -noupdate -divider {AC97 lines} -add wave -noupdate -format Logic /tb_ac_io/uut/ac_sdata_in -add wave -noupdate -format Logic /tb_ac_io/uut/ac_bit_clk -add wave -noupdate -format Logic /tb_ac_io/uut/ac_reset_n -add wave -noupdate -format Logic /tb_ac_io/uut/ac_sdata_out -add wave -noupdate -format Logic /tb_ac_io/uut/ac_ssync -add wave -noupdate -divider Debug -add wave -noupdate -format Logic /tb_ac_io/uut/inst_ac_in/stat_read -add wave -noupdate -format Literal -radix hexadecimal /tb_ac_io/uut/inst_ac_in/rx_reg -add wave -noupdate -format Literal -radix hexadecimal /tb_ac_io/uut/inst_ac_out/tx_reg -add wave -noupdate -format Literal /tb_ac_io/uut/inst_ac_in/bitcnt -add wave -noupdate -format Literal /tb_ac_io/uut/inst_ac_in/sac -add wave -noupdate -format Literal -radix hexadecimal /tb_ac_io/uut/inst_ac_in/tag -add wave -noupdate -format Literal /tb_ac_io/uut/inst_ac_in/data_array -add wave -noupdate -format Literal /tb_ac_io/uut/inst_ac_out/bitcnt -add wave -noupdate -format Literal /tb_ac_io/uut/inst_ac_out/slotcnt -add wave -noupdate -format Logic /tb_ac_io/uut/inst_ac_out/ssync -add wave -noupdate -format Literal /tb_ac_io/uut/inst_ac_out/slot_valid -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 4} {0 ps} 0} {{Cursor 2} {292930000 ps} 0} {{Cursor 4} {4999959266 ps} 0} -configure wave -namecolwidth 173 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -update -WaveRestoreZoom {0 ps} {735 us} diff --git a/lib/ac97_ctrl/sim/tb_ac_out.fdo b/lib/ac97_ctrl/sim/tb_ac_out.fdo deleted file mode 100644 index ac9d3c4..0000000 --- a/lib/ac97_ctrl/sim/tb_ac_out.fdo +++ /dev/null @@ -1,13 +0,0 @@ -## NOTE: Do not edit this file. -## Autogenerated by ProjNav (creatfdo.tcl) on Tue Jun 05 17:37:16 Westeuropäische Normalzeit 2007 -## -vlib work -vcom -explicit -93 "../../../lib/src/misc/singleshot.vhd" -vcom -explicit -93 "../src/core/ac_out.vhd" -vcom -explicit -93 "../src/tb_ac_out.vhd" -vsim -t 1ps -lib work tb_ac_out -do {tb_ac_out.wdo} -view wave -view structure -view signals -run 600us diff --git a/lib/ac97_ctrl/sim/tb_ac_out.wdo b/lib/ac97_ctrl/sim/tb_ac_out.wdo deleted file mode 100644 index b9d9a25..0000000 --- a/lib/ac97_ctrl/sim/tb_ac_out.wdo +++ /dev/null @@ -1,41 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_ac_out/rst -add wave -noupdate -format Logic /tb_ac_out/clk -add wave -noupdate -format Logic /tb_ac_out/ce -add wave -noupdate -divider {Host hand shake} -add wave -noupdate -format Logic /tb_ac_out/sync_tx -add wave -noupdate -divider {Command I/F} -add wave -noupdate -format Literal -radix hexadecimal /tb_ac_out/cmd_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_ac_out/cmd_data -add wave -noupdate -format Logic /tb_ac_out/uut/cmd_we -add wave -noupdate -divider {PCM I/F} -add wave -noupdate -format Literal -radix hexadecimal /tb_ac_out/pcm_in_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_ac_out/pcm_in_data -add wave -noupdate -format Logic /tb_ac_out/pcm_in_we -add wave -noupdate -divider {AC97 I/F} -add wave -noupdate -format Logic /tb_ac_out/ac_bit_clk -add wave -noupdate -format Logic /tb_ac_out/ac_reset -add wave -noupdate -format Logic /tb_ac_out/ac_sdata_out -add wave -noupdate -format Logic /tb_ac_out/ac_ssync -add wave -noupdate -divider Debug -add wave -noupdate -format Literal -radix hexadecimal /tb_ac_out/uut/tx_reg -add wave -noupdate -format Literal /tb_ac_out/uut/sac -add wave -noupdate -format Literal /tb_ac_out/uut/bitcnt -add wave -noupdate -format Literal /tb_ac_out/uut/slotcnt -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {544839100 ps} 0} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -update -WaveRestoreZoom {532851785 ps} {556826415 ps} diff --git a/lib/ac97_ctrl/src/core/ac97_wb.vhd b/lib/ac97_ctrl/src/core/ac97_wb.vhd deleted file mode 100644 index 1b4fb57..0000000 --- a/lib/ac97_ctrl/src/core/ac97_wb.vhd +++ /dev/null @@ -1,330 +0,0 @@ -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -ENTITY ac97_wb IS - Generic - ( - fifo_depth : natural := 8 - ); - Port - ( - -- J-Bus domain - CLK_I : in STD_LOGIC; - RST_I : in STD_LOGIC; - CYC_I : in STD_LOGIC; - STB_I : in STD_LOGIC; - WE_I : in STD_LOGIC; - ACK_O : out STD_LOGIC; - SRDY_O : out STD_LOGIC; - MRDY_I : in STD_LOGIC; - ADDR_I : in unsigned(31 downto 0); - DAT_I : in unsigned(31 downto 0); - DAT_O : out unsigned(31 downto 0); - INT_O : out STD_LOGIC; - - -- AC97 domain - ac97_sdata_in : in std_logic; - ac97_bit_clk : in std_logic; - ac97_reset_n : out std_logic; - ac97_sdata_out : out std_logic; - ac97_ssync : out std_logic - ); -END ac97_wb; - -ARCHITECTURE behavior OF ac97_wb IS - - constant ac_data_width : natural := 20; - constant pcm_data_width : natural := 18; - constant stat_data_width : natural := 16; - signal cmd_reg_we : std_logic; - signal cmd_pending : std_logic; - signal ac_cmd_data : unsigned(ac_data_width-1 downto 0); - signal ac_cmd_addr : unsigned(ac_data_width-1 downto 0); - signal ac_cmd_we : std_logic; - signal ac_tx_pcm_we : std_logic; - - signal stat_reg : unsigned(stat_data_width-1 downto 0); - signal stat_reg_re : std_logic; - signal stat_valid : std_logic; - signal stat_pending : std_logic; - signal ac_stat_data : unsigned(ac_data_width-1 downto 0); - signal ac_stat_addr : unsigned(ac_data_width-1 downto 0); - signal ac_stat_read : std_logic; - signal ac_stat_valid : std_logic; - - signal ac_tx_pcm_data : unsigned(ac_data_width-1 downto 0); - signal ac_tx_pcm_addr : unsigned (3 downto 0); - signal ac_rx_pcm_data : unsigned(ac_data_width-1 downto 0); - signal ac_rx_pcm_addr : unsigned (3 downto 0); - signal ac_sync_strobe : unsigned(0 to 2); - signal ac_slot_valid : unsigned(0 to 12); - signal ac_ready : std_logic; - signal rx_frame_valid : std_logic; - signal sync_frame : std_logic; - signal sync_tx : std_logic; - signal sync_status : std_logic; - signal request : unsigned(3 to 12); - - signal tx_data_start : std_logic; - signal tx_fifo_din : unsigned(pcm_data_width-1 downto 0); - signal tx_fifo_dout : unsigned(pcm_data_width-1 downto 0); - signal tx_fifo_re : std_logic; - signal tx_fifo_we : std_logic; - signal tx_fifo_full : std_logic; - signal tx_fifo_empty : std_logic; - signal tx_fifo_almost_full : std_logic; - signal tx_fifo_almost_empty : std_logic; - - signal rx_data_irq : std_logic; - signal rx_data_ack : std_logic; - - signal ac97_stat : unsigned(31 downto 0); - signal addr_reg : unsigned(31 downto 0); - signal data_reg : unsigned(31 downto 0); - signal int_en_frame_sync : std_logic; - signal int_en_rx : std_logic; - signal int_en_tx : std_logic; - signal rx_en : std_logic; - signal tx_en : std_logic; - signal rx_fifo_rst : std_logic; - signal tx_fifo_rst : std_logic; - - function GetRequest(slot1 : unsigned) return unsigned is - variable res : unsigned(3 to 12); - begin - res := (others => '0'); - for i in res'range loop - res(i) := not slot1(14-i); - end loop; - return res; - - end GetRequest; - - type ac_state_t is (reset, idle, pcm_3, pcm_4); - signal rx_state, rx_state_n : ac_state_t; - -begin - - SRDY_O <= CYC_I; - INT_O <= (rx_data_irq and int_en_rx) or (not tx_fifo_full and int_en_tx) or (sync_frame and int_en_frame_sync) ; - - rx_frame_valid <= ac_slot_valid(0); - sync_frame <= ac_sync_strobe(0); - sync_status <= ac_sync_strobe(1); - sync_tx <= ac_sync_strobe(2); - request <= GetRequest(ac_stat_addr); - - ac_stat_read <= not addr_reg(9); - ac_stat_valid <= '1' when (sync_status = '1' and ac_slot_valid(0 to 2) = "111") else '0'; - ac97_stat <= ac_ready & '0' & X"00000" & '0' & int_en_rx & int_en_tx & int_en_frame_sync & '0' & tx_fifo_full & rx_data_irq & tx_fifo_almost_full & stat_valid & cmd_pending; - -command_logic: - process (CLK_I) - begin - - if rising_edge(CLK_I) then - ac_cmd_we <= '0'; - if RST_I = '1' then - cmd_pending <= '0'; - elsif cmd_reg_we = '1' and cmd_pending = '0' then - cmd_pending <= '1'; - elsif (rx_frame_valid and sync_tx) = '1' and cmd_pending = '1' then - ac_cmd_we <= '1'; - cmd_pending <= '0'; - end if; - end if; - end process; - -status_logic: - process (CLK_I) - begin - - if rising_edge(CLK_I) then - if RST_I = '1' then - stat_pending <= '0'; - elsif cmd_reg_we = '1' and cmd_pending = '0' then - stat_pending <= ac_stat_read; - elsif ac_stat_valid = '1' then - stat_pending <= '0'; - end if; - end if; - end process; - -command_register: - process (CLK_I) - begin - if rising_edge(CLK_I) then - if cmd_reg_we = '1' and cmd_pending = '0' then - ac_cmd_addr <= ac_stat_read & addr_reg(8 downto 2) & X"000"; - ac_cmd_data <= data_reg(stat_data_width-1 downto 0) & X"0"; - end if; - end if; - end process; - -status_register: - process (CLK_I) - begin - - if rising_edge(CLK_I) then - if RST_I = '1' then - stat_valid <= '0'; - elsif stat_pending = '1' and ac_stat_valid = '1' then - stat_reg <= ac_stat_data(ac_data_width-1 downto ac_data_width-stat_data_width); - stat_valid <= '1'; - elsif stat_reg_re = '1' then - stat_valid <= '0'; - end if; - end if; - end process; - - -- Instantiate synchronous FIFO -inst_tx_fifo: entity work.fifo_sync - GENERIC MAP - ( - addr_width => fifo_depth, - data_width => pcm_data_width, - almost_full_thresh => 90*(2**fifo_depth)/100, - almost_empty_thresh => 10*(2**fifo_depth)/100 - ) - PORT MAP - ( - rst => tx_fifo_rst, - clk => CLK_I, - we => tx_fifo_we, - re => tx_fifo_re, - fifo_full => tx_fifo_full, - fifo_empty => tx_fifo_empty, - fifo_afull => tx_fifo_almost_full, - fifo_aempty => tx_fifo_almost_empty, - data_w => tx_fifo_din, - data_r => tx_fifo_dout - ); - tx_fifo_rst <= not tx_en or RST_I; - -tx_logic: - process (CLK_I) - begin - if rising_edge(CLK_I) then - if RST_I = '1' or tx_en = '0' then - ac_tx_pcm_addr <= "0011"; - tx_data_start <= '0'; - elsif sync_tx = '1' and (request(3) and request(4)) = '1' then - ac_tx_pcm_addr <= "0011"; - tx_data_start <= '1'; - elsif ac_tx_pcm_addr /= "0100" then - ac_tx_pcm_addr <= ac_tx_pcm_addr + 1; - else - tx_data_start <= '0'; - end if; - end if; - end process; - - ac_tx_pcm_we <= not tx_fifo_empty and tx_data_start; - tx_fifo_re <= ac_tx_pcm_we; - - tx_fifo_din <= data_reg(pcm_data_width-1 downto 0); - - ac_rx_pcm_addr <= addr_reg(5 downto 2); - -rx_logic: - process (CLK_I) - begin - if rising_edge(CLK_I) then - if RST_I = '1' then - rx_data_irq <= '0'; - elsif rx_frame_valid = '1' and sync_frame = '1' then - if ac_slot_valid(3) = '1' and ac_slot_valid(4) = '1' then - rx_data_irq <= rx_en; - end if; - elsif rx_data_ack = '1' then - rx_data_irq <= '0'; - end if; - end if; - end process; - -inst_ac_io : entity work.ac_io - PORT MAP - ( - rst => RST_I, - clk => CLK_I, - ready => ac_ready, - sync_strobe => ac_sync_strobe, - slot_valid => ac_slot_valid, - stat_addr => ac_stat_addr, - stat_data => ac_stat_data, - rx_pcm_addr => ac_rx_pcm_addr, - rx_pcm_data => ac_rx_pcm_data, - cmd_addr => ac_cmd_addr, - cmd_data => ac_cmd_data, - cmd_we => ac_cmd_we, - tx_pcm_addr => ac_tx_pcm_addr, - tx_pcm_data => ac_tx_pcm_data, - tx_pcm_we => ac_tx_pcm_we, - ac_sdata_in => ac97_sdata_in, - ac_bit_clk => ac97_bit_clk, - ac_reset_n => ac97_reset_n, - ac_sdata_out => ac97_sdata_out, - ac_ssync => ac97_ssync - ); - - ac_tx_pcm_data <= tx_fifo_dout & (ac_data_width-pcm_data_width-1 downto 0 => '0'); - -slave_data_out: - process (CLK_I) - begin - - if rising_edge(CLK_I) then - tx_fifo_we <= '0'; - stat_reg_re <= '0'; - cmd_reg_we <= '0'; - rx_data_ack <= '0'; - ACK_O <= '0'; - if RST_I = '1' then - addr_reg <= (others => '0'); - int_en_frame_sync <= '0'; - int_en_rx <= '0'; - int_en_tx <= '0'; - tx_en <= '0'; - rx_en <= '0'; - else --- DAT_O <= (others => '-'); - - if (STB_I and CYC_I) = '1' then - ACK_O <= not WE_I; - - case ADDR_I(11 downto 10) is - - when "00" => - DAT_O <= ac97_stat; - if WE_I = '1' then - int_en_frame_sync <= DAT_I(0); - int_en_tx <= DAT_I(1); - int_en_rx <= DAT_I(2); - tx_en <= DAT_I(4); - rx_en <= DAT_I(5); - end if; - when "01" => - addr_reg <= ADDR_I; - data_reg <= DAT_I; - stat_reg_re <= not WE_I; - cmd_reg_we <= WE_I; - DAT_O <= (31 downto stat_data_width => '0') & stat_reg; - - when "10" => - rx_data_ack <= not WE_I; - addr_reg <= ADDR_I; - data_reg <= DAT_I; - tx_fifo_we <= WE_I; - DAT_O <= (31 downto pcm_data_width => ac_rx_pcm_data(ac_data_width-1)) & ac_rx_pcm_data(ac_data_width-1 downto ac_data_width-pcm_data_width); - - when others => null; - - end case; - end if; - end if; - end if; - - end process; - -end behavior; diff --git a/lib/ac97_ctrl/src/core/ac_in.vhd b/lib/ac97_ctrl/src/core/ac_in.vhd deleted file mode 100644 index a072a9b..0000000 --- a/lib/ac97_ctrl/src/core/ac_in.vhd +++ /dev/null @@ -1,309 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 08:27:43 08/26/2006 --- Design Name: --- Module Name: ac_out - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity ac_in is - Port ( - rst : in std_logic; - clk : in std_logic; - sync_frame : out std_logic; - sync_status : out std_logic; - slot_valid : out unsigned(0 to 12); - stat_addr : out unsigned (19 downto 0); - stat_data : out unsigned (19 downto 0); - pcm_out_addr : in unsigned (3 downto 0); - pcm_out_data : out unsigned (19 downto 0); - ac_reset : in std_logic; - ac_bit_clk : in std_logic; - ac_sdata_in : in std_logic; - ac_ssync : in std_logic - ); -end ac_in; - -architecture Behavioral of ac_in is - ------------------------------------------------------------------- -COMPONENT singleshot -GENERIC (mode : integer); -PORT( - rst : IN std_logic; - clk : IN std_logic; - input : IN std_logic; - output : OUT std_logic - ); -END COMPONENT; - ------------------------------------------------------------------- -type sac_t is (ac_idle, ac_tag, ac_data); -subtype bitcnt_t is integer range 0 to 19; -subtype slotcnt_t is integer range 0 to 12; -subtype slot_valid_t is UNSIGNED(0 to 12); -subtype tag_t is UNSIGNED(15 downto 0); -subtype slot_t is UNSIGNED(19 downto 0); -type slot_array_t is array (natural range <>) of slot_t; - -signal data_array : slot_array_t (1 to 12); -signal tag : tag_t; - -signal sac, snac : sac_t; -signal bitcnt : bitcnt_t; -signal bitcnt_rst, bitcnt_en : STD_LOGIC; -signal slotcnt : slotcnt_t; -signal slotcnt_rst, slotcnt_en : STD_LOGIC; - -signal rx_reg : slot_t; -signal stat_read, host_update : STD_LOGIC; -signal sync_end, slot_end, last_slot, start_of_frame : STD_LOGIC; - ------------------------------------------------------------------- -function GetSlotValid(data : tag_t) return slot_valid_t is -variable res : slot_valid_t := (others => '0'); -begin - res := (others => '0'); - for i in slot_valid_t'range loop - res(i) := data(data'left-i); - end loop; - return res; - -end GetSlotValid; - ------------------------------------------------------------------- -begin - -------------------------------------------------------------- --- proc_status_flags -------------------------------------------------------------- -proc_status_flags: -process (rst, clk, host_update, tag, data_array) -begin - if rising_edge(clk) then - sync_status <= '0'; - if rst = '1' then - slot_valid <= (others => '0'); - stat_addr <= (others => '0'); - stat_data <= (others => '0'); - elsif host_update = '1' then - sync_status <= '1'; - slot_valid <= GetSlotValid(tag); - stat_addr <= data_array(1); - stat_data <= data_array(2); - end if; - end if; -end process; - -------------------------------------------------------------- --- proc_pcm_data -------------------------------------------------------------- -proc_pcm_data: -process (clk, pcm_out_addr, data_array) -variable slot_id : integer range 0 to 12; -begin - pcm_out_data <= (others => '-'); - slot_id := to_integer(pcm_out_addr); - if (slot_id > 2) then - pcm_out_data <= data_array(slot_id); - end if; -end process; - -------------------------------------------------------------- --- proc_read_data -------------------------------------------------------------- -proc_read_data : -process (ac_reset, ac_bit_clk, slot_end, slotcnt) -begin - - if ac_reset = '1' then - stat_read <= '0'; - elsif rising_edge(ac_bit_clk) then - stat_read <= '0'; - if slot_end = '1' and slotcnt /= 0 then - data_array(slotcnt) <= rx_reg; - if slotcnt = 2 then - stat_read <= '1'; - end if; - end if; - end if; -end process; - -------------------------------------------------------------- --- proc_read_stat -------------------------------------------------------------- -proc_read_tag : -process (ac_reset, ac_bit_clk, sync_end) -begin - - if ac_reset = '1' then - tag <= (others => '0'); - elsif rising_edge(ac_bit_clk) then - if sync_end = '1' then - tag <= rx_reg(15 downto 0); - end if; - end if; - -end process; - -------------------------------------------------------------- --- proc_slot_count -------------------------------------------------------------- -proc_slot_count: -process (slotcnt_rst, ac_bit_clk, slotcnt_en, slotcnt) -begin - if rising_edge(ac_bit_clk) then - if slotcnt_rst = '1' then - slotcnt <= slotcnt_t'low; - elsif slotcnt_en = '1' then - if slotcnt /= slotcnt_t'high then - slotcnt <= slotcnt + 1; - else - slotcnt <= slotcnt_t'low; - end if; - end if; - end if; -end process; - -------------------------------------------------------------- --- proc_bit_count -------------------------------------------------------------- -proc_bit_count: -process (bitcnt_rst, ac_bit_clk, bitcnt_en, bitcnt) -begin - if rising_edge(ac_bit_clk) then - if bitcnt_rst = '1' then - bitcnt <= bitcnt_t'low; - elsif bitcnt_en = '1' then - if bitcnt /= bitcnt_t'high then - bitcnt <= bitcnt + 1; - else - bitcnt <= bitcnt_t'low; - end if; - end if; - end if; -end process; - ------------------------------------------------------------------- -proc_ac_fsm: -process (bitcnt, slotcnt, sac, ac_ssync) -begin - snac <= sac; - bitcnt_rst <= '0'; - bitcnt_en <= '1'; - slotcnt_rst <= '0'; - slotcnt_en <= '0'; - slot_end <= '0'; - sync_end <= '0'; - last_slot <= '0'; - start_of_frame <= '0'; - - if bitcnt = 19 then - slot_end <= '1'; - end if; - if slotcnt = 12 and bitcnt = 19 then - last_slot <= '1'; - end if; - - case sac is - - when ac_idle => - bitcnt_rst <= '1'; - slotcnt_rst <= '1'; - if (ac_ssync = '1') then - snac <= ac_tag; - end if; - - when ac_tag => - if (bitcnt = 0) then - start_of_frame <= '1'; - elsif (bitcnt = 15) then - slotcnt_en <= '1'; - bitcnt_rst <= '1'; - sync_end <= '1'; - if (ac_ssync = '0') then - snac <= ac_data; - else - snac <= ac_idle; - end if; - end if; - - when ac_data => - if bitcnt = 19 then - slotcnt_en <= '1'; - if slotcnt = 12 then - slotcnt_rst <= '1'; - snac <= ac_tag; - end if; - end if; - when others => null; - end case; -end process; - -proc_ac_fsm_next: -process (ac_reset, ac_bit_clk, snac) -begin - if ac_reset = '1' then - sac <= ac_idle; - elsif rising_edge(ac_bit_clk) then - sac <= snac; - end if; -end process; - -------------------------------------------------------------- --- Receive Shift Register -------------------------------------------------------------- -process (ac_reset, ac_bit_clk, ac_sdata_in) -begin - if ac_reset = '1' then - rx_reg <= (others => '0'); - elsif falling_edge(ac_bit_clk) then - rx_reg <= rx_reg(rx_reg'left-1 downto 0) & ac_sdata_in; - end if; -end process; - ------------------------------------------------------------------- -singleshot_inst1: singleshot -GENERIC MAP ( - mode => 0) -PORT MAP( - rst => rst, - clk => clk, - input => stat_read, - output => host_update -); - -singleshot_inst2: singleshot -GENERIC MAP ( - mode => 1) -PORT MAP( - rst => rst, - clk => clk, - input => start_of_frame, - output => sync_frame -); - -------------------------------------------------------------- - -end Behavioral; - diff --git a/lib/ac97_ctrl/src/core/ac_io.vhd b/lib/ac97_ctrl/src/core/ac_io.vhd deleted file mode 100644 index 211a5ef..0000000 --- a/lib/ac97_ctrl/src/core/ac_io.vhd +++ /dev/null @@ -1,189 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 18:29:55 08/26/2006 --- Design Name: --- Module Name: ac_io - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity ac_io is - Port - ( - rst : in std_logic; - clk : in std_logic; - ready : out std_logic; - sync_strobe : out unsigned(0 to 2); - slot_valid : out unsigned(0 to 12); - stat_addr : out unsigned (19 downto 0); - stat_data : out unsigned (19 downto 0); - rx_pcm_addr : in unsigned (3 downto 0); - rx_pcm_data : out unsigned (19 downto 0); - cmd_addr : in unsigned(19 downto 0); - cmd_data : in unsigned(19 downto 0); - cmd_we : in std_logic; - tx_pcm_addr : in unsigned(3 downto 0); - tx_pcm_data : in unsigned(19 downto 0); - tx_pcm_we : in std_logic; - ac_sdata_in : in std_logic; - ac_bit_clk : in std_logic; - ac_reset_n : out std_logic; - ac_sdata_out : out std_logic; - ac_ssync : out std_logic - ); -end ac_io; - -architecture Behavioral of ac_io is - - COMPONENT ac_in - Port - ( - rst : in std_logic; - clk : in std_logic; - sync_frame : out std_logic; - sync_status : out std_logic; - slot_valid : out unsigned(0 to 12); - stat_addr : out unsigned (19 downto 0); - stat_data : out unsigned (19 downto 0); - pcm_out_addr : in unsigned (3 downto 0); - pcm_out_data : out unsigned (19 downto 0); - ac_reset : in std_logic; - ac_bit_clk : in std_logic; - ac_sdata_in : in std_logic; - ac_ssync : in std_logic - ); - END COMPONENT; - - COMPONENT ac_out - PORT - ( - rst : in std_logic; - clk : in std_logic; - sync_tx : out std_logic; - cmd_addr : in unsigned(19 downto 0); - cmd_data : in unsigned(19 downto 0); - cmd_we : in std_logic; - pcm_in_addr : in unsigned(3 downto 0); - pcm_in_data : in unsigned(19 downto 0); - pcm_in_we : in std_logic; - ac_bit_clk : in std_logic; - ac_reset : in std_logic; - ac_sdata_out : out std_logic; - ac_ssync : out std_logic - ); - END COMPONENT; - - SIGNAL ac_reset : std_logic; - SIGNAL ssync_rx : std_logic; - SIGNAL ssync_tx : std_logic; - SIGNAL sync_frame : std_logic; - SIGNAL sync_status : std_logic; - SIGNAL sync_tx : std_logic; - -begin - -inst_ac_in: ac_in - PORT MAP - ( - rst => rst, - clk => clk, - sync_frame => sync_frame, - sync_status => sync_status, - slot_valid => slot_valid, - stat_addr => stat_addr, - stat_data => stat_data, - pcm_out_addr => rx_pcm_addr, - pcm_out_data => rx_pcm_data, - ac_reset => ac_reset, - ac_bit_clk => ac_bit_clk, - ac_sdata_in => ac_sdata_in, - ac_ssync => ssync_rx - ); - -inst_ac_out: ac_out - PORT MAP - ( - rst => rst, - clk => clk, - sync_tx => sync_tx, - cmd_addr => cmd_addr, - cmd_data => cmd_data, - cmd_we => cmd_we, - pcm_in_addr => tx_pcm_addr, - pcm_in_data => tx_pcm_data, - pcm_in_we => tx_pcm_we, - ac_reset => ac_reset, - ac_bit_clk => ac_bit_clk, - ac_sdata_out => ac_sdata_out, - ac_ssync => ssync_tx - ); - - ------------------------------------------------------------------ - ready <= not ac_reset; - ac_ssync <= ssync_tx; - ssync_rx <= ssync_tx; - sync_strobe <= sync_frame & sync_status & sync_tx; - - ------------------------------------------------------------------ - proc_reset_gen: - process (rst, clk, ac_bit_clk) - type rstate_t is (s0, s1); - variable rstate, rstaten : rstate_t; - subtype cnt_t is integer range 0 to 999; - variable cnt : cnt_t; - begin - if rising_edge(clk) then - if rst = '1' then - rstate := s0; - cnt := cnt_t'high; - ac_reset <= '1'; - ac_reset_n <= '0'; - else - rstaten := rstate; - case rstate is - when s0 => - if cnt /= 0 then - cnt := cnt - 1; - else - ac_reset_n <= '1'; - if ac_bit_clk = '1' then - rstaten := s1; - cnt := cnt_t'high; - end if; - end if; - - when s1 => - if cnt /= 0 then - cnt := cnt - 1; - else - ac_reset <= '0'; - end if; - end case; - rstate := rstaten; - end if; - end if; - end process; - - ------------------------------------------------------------------ - -end Behavioral; - diff --git a/lib/ac97_ctrl/src/core/ac_out.vhd b/lib/ac97_ctrl/src/core/ac_out.vhd deleted file mode 100644 index a770495..0000000 --- a/lib/ac97_ctrl/src/core/ac_out.vhd +++ /dev/null @@ -1,276 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 15:41:12 06/05/2007 --- Design Name: --- Module Name: ac_out - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity ac_out is - Port ( - rst : in std_logic; - clk : in std_logic; - sync_tx : out std_logic; - cmd_addr : in unsigned (19 downto 0); - cmd_data : in unsigned (19 downto 0); - cmd_we : in std_logic; - pcm_in_addr : in unsigned (3 downto 0); - pcm_in_data : in unsigned (19 downto 0); - pcm_in_we : in std_logic; - ac_reset : in std_logic; - ac_bit_clk : in std_logic; - ac_sdata_out : out std_logic; - ac_ssync : out std_logic - ); -end ac_out; - -architecture Behavioral of ac_out is - ------------------------------------------------------------------- -COMPONENT singleshot -GENERIC (mode : integer); -PORT( - rst : IN std_logic; - clk : IN std_logic; - input : IN std_logic; - output : OUT std_logic - ); -END COMPONENT; - ------------------------------------------------------------------- -subtype tag_t is UNSIGNED(15 downto 0); -subtype slot_valid_t is UNSIGNED(1 to 12); -signal slot_valid : slot_valid_t; -subtype slot_t is UNSIGNED(19 downto 0); -type slot_array_t is array (natural range <>) of slot_t; -signal data_array : slot_array_t (1 to 12); - signal tx_reg : UNSIGNED(19 downto 0); -signal last_slot, ssync : STD_LOGIC; - -type sac_t is (ac_idle, ac_tag, ac_data); -signal sac, snac : sac_t; - -subtype bitcnt_t is integer range 0 to 19; -subtype slotcnt_t is integer range 0 to 12; - -signal bitcnt : bitcnt_t; -signal bitcnt_rst, bitcnt_en : STD_LOGIC; -signal slotcnt : slotcnt_t; -signal slotcnt_rst, slotcnt_en : STD_LOGIC; - -signal slot_start : STD_LOGIC; - ------------------------------------------------------------------- -function CreateTag(slot_valid : slot_valid_t) return tag_t is -variable tag : tag_t := (others => '0'); -begin - tag := (others => '0'); - for i in slot_valid_t'range loop - tag(15-i) := slot_valid(i); - if slot_valid(i) = '1' then - tag(15) := '1'; - end if; - end loop; - tag(0) := '0'; -- ID0 - tag(1) := '0'; -- ID1 - tag(2) := '0'; -- Reserved --- tag(15) := '1'; -- Frame is valid - return tag; - -end CreateTag; - -begin - ------------------------------------------------------------------- -proc_slot_reg: -process (clk, cmd_addr, cmd_data, cmd_we, pcm_in_data, pcm_in_we, pcm_in_addr, last_slot) -variable slot_id : integer range 0 to 12; -begin - slot_id := to_integer(pcm_in_addr); - if rising_edge(clk) then - if rst = '1' then - for i in data_array'range(1) loop - data_array(i) <= (others => '0'); - end loop; - slot_valid <= (others => '0'); - elsif last_slot = '1' then - slot_valid <= (others => '0'); - else - if cmd_we = '1' then - slot_valid(1) <= '1'; - slot_valid(2) <= '1'; - data_array(1) <= cmd_addr; - data_array(2) <= cmd_data; - end if; - if pcm_in_we = '1' then - if (slot_id > 2) then - data_array(slot_id) <= pcm_in_data; - slot_valid(slot_id) <= '1'; - end if; - end if; - end if; - end if; -end process; - -------------------------------------------------------------- --- proc_slot_count -------------------------------------------------------------- -proc_slot_count: -process (slotcnt_rst, ac_bit_clk, slotcnt_en, slotcnt) -begin - if rising_edge(ac_bit_clk) then - if slotcnt_rst = '1' then - slotcnt <= slotcnt_t'low; - elsif slotcnt_en = '1' then - if slotcnt /= slotcnt_t'high then - slotcnt <= slotcnt + 1; - else - slotcnt <= slotcnt_t'low; - end if; - end if; - end if; -end process; - ------------------------------------------------------------------- --- proc_bit_count ------------------------------------------------------------------- -proc_bit_count: -process (bitcnt_rst, ac_bit_clk, bitcnt_en, bitcnt) -begin - if rising_edge(ac_bit_clk) then - if bitcnt_rst = '1' then - bitcnt <= bitcnt_t'low; - elsif bitcnt_en = '1' then - if bitcnt /= bitcnt_t'high then - bitcnt <= bitcnt + 1; - else - bitcnt <= bitcnt_t'low; - end if; - end if; - end if; -end process; - ------------------------------------------------------------------- -proc_ac_fsm: -process (bitcnt, slotcnt, sac) -begin - snac <= sac; - bitcnt_rst <= '0'; - bitcnt_en <= '1'; - slotcnt_rst <= '0'; - slotcnt_en <= '0'; - slot_start <= '0'; - ssync <= '0'; - - if bitcnt = 0 then - slot_start <= '1'; - end if; - - case sac is - - when ac_idle => - bitcnt_rst <= '1'; - slotcnt_rst <= '1'; - snac <= ac_tag; - - when ac_tag => - ssync <= '1'; - if (bitcnt = 15) then - slotcnt_en <= '1'; - bitcnt_rst <= '1'; - snac <= ac_data; - end if; - - when ac_data => - if bitcnt = 19 then - slotcnt_en <= '1'; - if slotcnt = 12 then - slotcnt_rst <= '1'; - snac <= ac_tag; - end if; - end if; - when others => null; - end case; -end process; - -proc_ac_fsm_next: -process (ac_reset, ac_bit_clk, snac) -begin - if ac_reset = '1' then - sac <= ac_idle; - elsif rising_edge(ac_bit_clk) then - sac <= snac; - end if; -end process; - ------------------------------------------------------------------- -proc_tx_shift_reg: -process (ac_reset, ac_bit_clk, tx_reg, ssync, slot_valid, data_array) -begin - - if ac_reset = '1' then - tx_reg <= (others => '0'); - elsif rising_edge(ac_bit_clk) then - last_slot <= '0'; - if slot_start = '1' then - if ssync = '1' then - tx_reg <= CreateTag(slot_valid) & "0000"; - else - if slotcnt /= 0 then - tx_reg <= data_array(slotcnt); - if slotcnt = 12 then - last_slot <= '1'; - end if; - end if; - end if; - else - tx_reg <= tx_reg(tx_reg'left-1 downto 0) & '0'; - end if; - end if; -end process; - ------------------------------------------------------------------- -proc_ac_sync_out: -process (ac_reset, ac_bit_clk, ssync, tx_reg) -begin - if ac_reset = '1' then - ac_ssync <= '0'; - ac_sdata_out <= '0'; - elsif rising_edge(ac_bit_clk) then - ac_ssync <= ssync; - ac_sdata_out <= tx_reg(tx_reg'left); - end if; -end process; - ------------------------------------------------------------------- -singleshot_inst1: singleshot -GENERIC MAP ( - mode => 0) -PORT MAP( - rst => rst, - clk => clk, - input => last_slot, - output => sync_tx -); - -end Behavioral; diff --git a/lib/ac97_ctrl/src/tb_ac97_wb.vhd b/lib/ac97_ctrl/src/tb_ac97_wb.vhd deleted file mode 100644 index 7ab47a4..0000000 --- a/lib/ac97_ctrl/src/tb_ac97_wb.vhd +++ /dev/null @@ -1,152 +0,0 @@ - --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 17:33:47 06/05/2007 --- Design Name: eval_ac --- Module Name: E:/work/VHDL/eval_ac/tb_eval_ac.vhd --- Project Name: ac_out --- Target Device: --- Tool versions: --- Description: --- --- VHDL Test Bench Created by ISE for module: ac_out --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --- Notes: --- This testbench has been automatically generated using types std_logic and --- std_logic_vector for the ports of the unit under test. Xilinx recommends --- that these types always be used for the top-level I/O of a design in order --- to guarantee that the testbench will bind correctly to the post-implementation --- simulation model. --------------------------------------------------------------------------------- -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.numeric_std.ALL; - -ENTITY tb_ac97_wb IS -END tb_ac97_wb; - -ARCHITECTURE behavior OF tb_ac97_wb IS - - constant SYS_CLK_PERIOD : time := 10 ns; - CONSTANT BIT_CLK_PERIOD : time := 100 ns; --- constant BIT_CLK_PERIOD : time := 81.38 ns; - - signal CLK_O : std_logic := '1'; - signal RST_O : std_logic := '1'; - signal CYC_O : std_logic := '0'; - signal STB_O : std_logic := '0'; - signal WE_O : std_logic := '0'; - signal ACK_I : std_logic; - signal MRDY_O : std_logic := '1'; - signal SRDY_I : std_logic; - signal INT_I : std_logic; - signal ADDR_O : unsigned(31 downto 0) := (others => '-'); - signal DAT_I : unsigned(31 downto 0); - signal DAT_O : unsigned(31 downto 0) := (others => '-'); - - signal dout_rst : std_logic := '0'; - signal dout_reg : unsigned(31 downto 0); - signal dout_cnt : natural range 0 to 255; - - SIGNAL ac97_bit_clk : std_logic := '0'; - SIGNAL ac97_reset_n : std_logic; - SIGNAL ac97_sdata_out : std_logic; - SIGNAL ac97_ssync : std_logic; - SIGNAL ac97_sdata_in : std_logic; - -BEGIN - - -- Instantiate the Unit Under Test (UUT) -uut : entity work.ac97_wb - GENERIC MAP - ( - fifo_depth => 4 - ) - PORT MAP - ( - -- J-Bus domain - CLK_I => CLK_O, - RST_I => RST_O, - CYC_I => CYC_O, - STB_I => STB_O, - WE_I => WE_O, - ACK_O => ACK_I, - SRDY_O => SRDY_I, - MRDY_I => MRDY_O, - ADDR_I => ADDR_O, - DAT_I => DAT_O, - DAT_O => DAT_I, - INT_O => INT_I, - - -- AC97 domain - ac97_sdata_in => ac97_sdata_in, - ac97_bit_clk => ac97_bit_clk, - ac97_reset_n => ac97_reset_n, - ac97_sdata_out => ac97_sdata_out, - ac97_ssync => ac97_ssync - ); - - - ac97_sdata_in <= ac97_sdata_out; - -CLK_GEN: process - begin - wait for SYS_CLK_PERIOD/2; - CLK_O <= not CLK_O; - end process; - - bit_clk_gen : PROCESS - begin - if (ac97_reset_n = '0') then - ac97_bit_clk <= '0'; - wait until ac97_reset_n = '1'; - wait for 150 us; - end if; - wait for BIT_CLK_PERIOD/2; - ac97_bit_clk <= not ac97_bit_clk; - END PROCESS; - -STIMULUS: process - - begin - - wait for 3*SYS_CLK_PERIOD; - RST_O <= '0'; - - wait for 200 us; - wait until rising_edge(CLK_O); - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '0'; - DAT_O <= X"0000_0000"; - ADDR_O <= X"0000_0000"; - wait until rising_edge(CLK_O); - STB_O <= '0'; - wait until rising_edge(CLK_O) and ACK_I = '1'; - CYC_O <= '0'; - - wait until rising_edge(CLK_O); - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '1'; - DAT_O <= X"5555_1000"; - ADDR_O <= X"0000_0800"; - wait until rising_edge(CLK_O); - DAT_O <= X"5555_1001"; - wait until rising_edge(CLK_O); - STB_O <= '0'; - CYC_O <= '0'; - - WAIT; - END PROCESS; -END; diff --git a/lib/ac97_ctrl/src/tb_ac_in.vhd b/lib/ac97_ctrl/src/tb_ac_in.vhd deleted file mode 100644 index 359e79b..0000000 --- a/lib/ac97_ctrl/src/tb_ac_in.vhd +++ /dev/null @@ -1,203 +0,0 @@ - --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 17:33:47 06/05/2007 --- Design Name: eval_ac --- Module Name: E:/work/VHDL/eval_ac/tb_eval_ac.vhd --- Project Name: ac_out --- Target Device: --- Tool versions: --- Description: --- --- VHDL Test Bench Created by ISE for module: ac_out --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --- Notes: --- This testbench has been automatically generated using types std_logic and --- std_logic_vector for the ports of the unit under test. Xilinx recommends --- that these types always be used for the top-level I/O of a design in order --- to guarantee that the testbench will bind correctly to the post-implementation --- simulation model. --------------------------------------------------------------------------------- -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.numeric_std.ALL; - -ENTITY tb_ac_in IS -END tb_ac_in; - -ARCHITECTURE behavior OF tb_ac_in IS - - -- Component Declaration for the Unit Under Test (UUT) - COMPONENT ac_in - Port ( - rst : in std_logic; - clk : in std_logic; - sync_frame : out std_logic; - sync_status : out std_logic; - slot_valid : out unsigned(0 to 12); - stat_addr : out unsigned (19 downto 0); - stat_data : out unsigned (19 downto 0); - pcm_out_addr : in unsigned (3 downto 0); - pcm_out_data : out unsigned (19 downto 0); - ac_reset : in std_logic; - ac_bit_clk : in std_logic; - ac_sdata_in : in std_logic; - ac_ssync : in std_logic - ); - END COMPONENT; - - COMPONENT ac_out - PORT( - rst : in std_logic; - clk : in std_logic; - sync_tx : out std_logic; - cmd_addr : in unsigned(19 downto 0); - cmd_data : in unsigned(19 downto 0); - cmd_we : in std_logic; - pcm_in_addr : in unsigned(3 downto 0); - pcm_in_data : in unsigned(19 downto 0); - pcm_in_we : in std_logic; - ac_bit_clk : in std_logic; - ac_reset : in std_logic; - ac_sdata_out : out std_logic; - ac_ssync : out std_logic - ); - END COMPONENT; - - constant SYS_CLK_PERIOD : time := 10 ns; - constant BIT_CLK_PERIOD : time := 81.38 ns; - - --Inputs - SIGNAL rst : std_logic := '1'; - SIGNAL clk : std_logic := '0'; - SIGNAL cmd_we : std_logic := '0'; - SIGNAL pcm_in_we : std_logic := '0'; - SIGNAL ac_bit_clk : std_logic := '0'; - SIGNAL cmd_addr : unsigned(19 downto 0) := (others=>'0'); - SIGNAL cmd_data : unsigned(19 downto 0) := (others=>'0'); - SIGNAL pcm_in_addr : unsigned(3 downto 0) := "0011"; - SIGNAL pcm_in_data : unsigned(19 downto 0) := (others=>'0'); - SIGNAL ac_sdata_in : std_logic; - SIGNAL pcm_out_addr : unsigned(3 downto 0) := "0101"; - SIGNAL ac_reset : std_logic := '1'; - - --Outputs - SIGNAL sync_frame : std_logic; - SIGNAL sync_status : std_logic; - SIGNAL sync_tx : std_logic; - SIGNAL ac_sdata_out : std_logic; - SIGNAL ac_ssync : std_logic; - SIGNAL stat_addr : unsigned(19 downto 0); - SIGNAL stat_data : unsigned(19 downto 0); - SIGNAL stat_valid : std_logic; - SIGNAL pcm_out_data : unsigned(19 downto 0); - SIGNAL pcm_out_valid : std_logic; - SIGNAL pcm_out_avail : std_logic; - -BEGIN - - -- Instantiate the Unit Under Test (UUT) - uut: ac_in PORT MAP( - rst => rst, - clk => clk, - sync_frame => sync_frame, - sync_status => sync_status, - stat_addr => stat_addr, - stat_data => stat_data, - pcm_out_addr => pcm_out_addr, - pcm_out_data => pcm_out_data, - ac_reset => ac_reset, - ac_bit_clk => ac_bit_clk, - ac_sdata_in => ac_sdata_in, - ac_ssync => ac_ssync - ); - - inst_ac_out: ac_out PORT MAP( - rst => rst, - clk => clk, - sync_tx => sync_tx, - cmd_addr => cmd_addr, - cmd_data => cmd_data, - cmd_we => cmd_we, - pcm_in_addr => pcm_in_addr, - pcm_in_data => pcm_in_data, - pcm_in_we => pcm_in_we, - ac_reset => ac_reset, - ac_bit_clk => ac_bit_clk, - ac_sdata_out => ac_sdata_out, - ac_ssync => ac_ssync - ); - - ac_sdata_in <= ac_sdata_out; - - sys_clk_gen : - PROCESS - BEGIN - wait for SYS_CLK_PERIOD; - clk <= not clk; - END PROCESS; - - bit_clk_gen : - PROCESS - BEGIN - wait for BIT_CLK_PERIOD; - ac_bit_clk <= not ac_bit_clk; - END PROCESS; - - tb_out : PROCESS - BEGIN - - -- Wait 100 ns for global reset to finish - wait for 100*SYS_CLK_PERIOD; - rst <= '0'; - - wait for 100*SYS_CLK_PERIOD; - ac_reset <= '0'; - - wait until rising_edge(clk) and sync_tx = '1'; - wait for 100*SYS_CLK_PERIOD; - cmd_data <= X"12340"; - cmd_addr <= X"8B930"; - - wait until rising_edge(clk); - cmd_we <= '1'; - wait until rising_edge(clk); - cmd_we <= '0'; - - for k in 1 to 10 loop - pcm_in_we <= '0'; - wait until rising_edge(clk) and sync_tx = '1'; - wait for 100*SYS_CLK_PERIOD; - for i in 3 to 12 loop - pcm_in_addr <= to_unsigned(i, 4); - pcm_in_data <= to_unsigned(2048*k + integer(i), 20); - pcm_in_we <= '1'; - wait until rising_edge(clk); - end loop; - end loop; - pcm_in_we <= '0'; - - -- Place stimulus here - - wait; -- will wait forever - END PROCESS; - - tb_in : PROCESS(clk, pcm_out_addr, sync_status) - BEGIN - if rising_edge(clk) then - if sync_status = '1' then - pcm_out_addr <= "0011"; - elsif pcm_out_addr /= "1100" then - pcm_out_addr <= pcm_out_addr + 1; - end if; - end if; - END PROCESS; -END; diff --git a/lib/ac97_ctrl/src/tb_ac_io.vhd b/lib/ac97_ctrl/src/tb_ac_io.vhd deleted file mode 100644 index 6f25c1d..0000000 --- a/lib/ac97_ctrl/src/tb_ac_io.vhd +++ /dev/null @@ -1,186 +0,0 @@ - --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 17:33:47 06/05/2007 --- Design Name: eval_ac --- Module Name: E:/work/VHDL/eval_ac/tb_eval_ac.vhd --- Project Name: ac_out --- Target Device: --- Tool versions: --- Description: --- --- VHDL Test Bench Created by ISE for module: ac_out --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --- Notes: --- This testbench has been automatically generated using types std_logic and --- std_logic_vector for the ports of the unit under test. Xilinx recommends --- that these types always be used for the top-level I/O of a design in order --- to guarantee that the testbench will bind correctly to the post-implementation --- simulation model. --------------------------------------------------------------------------------- -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.numeric_std.ALL; - -ENTITY tb_ac_io IS -END tb_ac_io; - -ARCHITECTURE behavior OF tb_ac_io IS - - -- Component Declaration for the Unit Under Test (UUT) - COMPONENT ac_io - Port ( - rst : in std_logic; - clk : in std_logic; - ready : out std_logic; - sync_strobe : out unsigned(0 to 2); - slot_valid : out unsigned(0 to 12); - stat_addr : out unsigned (19 downto 0); - stat_data : out unsigned (19 downto 0); - rx_pcm_addr : in unsigned (3 downto 0); - rx_pcm_data : out unsigned (19 downto 0); - cmd_addr : in unsigned(19 downto 0); - cmd_data : in unsigned(19 downto 0); - cmd_we : in std_logic; - tx_pcm_addr : in unsigned(3 downto 0); - tx_pcm_data : in unsigned(19 downto 0); - tx_pcm_we : in std_logic; - ac_sdata_in : in std_logic; - ac_bit_clk : in std_logic; - ac_reset_n : out std_logic; - ac_sdata_out : out std_logic; - ac_ssync : out std_logic - ); - END COMPONENT; - - constant SYS_CLK_PERIOD : time := 10 ns; - CONSTANT BIT_CLK_PERIOD : time := 100 ns; --- constant BIT_CLK_PERIOD : time := 81.38 ns; - - --Inputs - SIGNAL rst : std_logic := '1'; - SIGNAL clk : std_logic := '0'; - SIGNAL acio_ready : std_logic; - SIGNAL cmd_we : std_logic := '0'; - SIGNAL tx_pcm_we : std_logic := '0'; - SIGNAL ac_bit_clk : std_logic := '0'; - SIGNAL cmd_addr : unsigned(19 downto 0) := (others=>'0'); - SIGNAL cmd_data : unsigned(19 downto 0) := (others=>'0'); - SIGNAL tx_pcm_addr : unsigned(3 downto 0) := "0011"; - SIGNAL tx_pcm_data : unsigned(19 downto 0) := (others=>'0'); - SIGNAL ac_sdata_in : std_logic; - SIGNAL rx_pcm_addr : unsigned(3 downto 0) := "0101"; - - --Outputs - SIGNAL slot_valid : unsigned(0 to 12); - SIGNAL sync_strobe : unsigned(0 to 2); - SIGNAL ac_reset_n : std_logic; - SIGNAL ac_sdata_out : std_logic; - SIGNAL ac_ssync : std_logic; - SIGNAL stat_addr : unsigned(19 downto 0); - SIGNAL stat_data : unsigned(19 downto 0); - SIGNAL rx_pcm_data : unsigned(19 downto 0); - -BEGIN - - -- Instantiate the Unit Under Test (UUT) - uut: ac_io PORT MAP( - rst => rst, - clk => clk, - ready => acio_ready, - sync_strobe => sync_strobe, - slot_valid => slot_valid, - stat_addr => stat_addr, - stat_data => stat_data, - rx_pcm_addr => rx_pcm_addr, - rx_pcm_data => rx_pcm_data, - cmd_addr => cmd_addr, - cmd_data => cmd_data, - cmd_we => cmd_we, - tx_pcm_addr => tx_pcm_addr, - tx_pcm_data => tx_pcm_data, - tx_pcm_we => tx_pcm_we, - ac_sdata_in => ac_sdata_in, - ac_bit_clk => ac_bit_clk, - ac_reset_n => ac_reset_n, - ac_sdata_out => ac_sdata_out, - ac_ssync => ac_ssync - ); - - ac_sdata_in <= ac_sdata_out; - - sys_clk_gen : - PROCESS - BEGIN - wait for SYS_CLK_PERIOD; - clk <= not clk; - END PROCESS; - - bit_clk_gen : PROCESS - begin - if (ac_reset_n = '0') then - ac_bit_clk <= '0'; - wait until ac_reset_n = '1'; - wait for 150 us; - end if; - wait for BIT_CLK_PERIOD/2; - ac_bit_clk <= not ac_bit_clk; - END PROCESS; - - tb_out : PROCESS - BEGIN - - -- Wait 100 ns for global reset to finish - wait for 100*SYS_CLK_PERIOD; - rst <= '0'; - - wait until (ac_reset_n = '1'); - - wait until rising_edge(clk) and sync_strobe(2) = '1'; - wait for 100*SYS_CLK_PERIOD; - cmd_data <= X"12340"; - cmd_addr <= X"8B930"; - - wait until rising_edge(clk); - cmd_we <= '1'; - wait until rising_edge(clk); - cmd_we <= '0'; - - for k in 1 to 10 loop - tx_pcm_we <= '0'; - wait until rising_edge(clk) and sync_strobe(2) = '1'; - wait for 10*BIT_CLK_PERIOD; - for i in 3 to 12 loop - tx_pcm_addr <= to_unsigned(i, 4); - tx_pcm_data <= to_unsigned(2048*k + integer(i), 20); - tx_pcm_we <= '1'; - wait until rising_edge(clk); - end loop; - end loop; - tx_pcm_we <= '0'; - - -- Place stimulus here - - wait; -- will wait forever - END PROCESS; - - tb_in : PROCESS(clk, rx_pcm_addr, sync_strobe) - BEGIN - if rising_edge(clk) then - if sync_strobe(1) = '1' then - rx_pcm_addr <= "0011"; - elsif rx_pcm_addr /= "1100" then - rx_pcm_addr <= rx_pcm_addr + 1; - end if; - end if; - END PROCESS; - -END; diff --git a/lib/ac97_ctrl/src/tb_ac_out.vhd b/lib/ac97_ctrl/src/tb_ac_out.vhd deleted file mode 100644 index 6f6cb42..0000000 --- a/lib/ac97_ctrl/src/tb_ac_out.vhd +++ /dev/null @@ -1,149 +0,0 @@ - --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 17:33:47 06/05/2007 --- Design Name: eval_ac --- Module Name: E:/work/VHDL/eval_ac/tb_eval_ac.vhd --- Project Name: ac_out --- Target Device: --- Tool versions: --- Description: --- --- VHDL Test Bench Created by ISE for module: ac_out --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --- Notes: --- This testbench has been automatically generated using types std_logic and --- std_logic_vector for the ports of the unit under test. Xilinx recommends --- that these types always be used for the top-level I/O of a design in order --- to guarantee that the testbench will bind correctly to the post-implementation --- simulation model. --------------------------------------------------------------------------------- -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.numeric_std.ALL; - -ENTITY tb_ac_out IS -END tb_ac_out; - -ARCHITECTURE behavior OF tb_ac_out IS - - -- Component Declaration for the Unit Under Test (UUT) - COMPONENT ac_out - PORT( - rst : IN std_logic; - clk : IN std_logic; - sync_tx : OUT std_logic; - cmd_addr : IN unsigned(19 downto 0); - cmd_data : IN unsigned(19 downto 0); - cmd_we : IN std_logic; - pcm_in_addr : IN unsigned(3 downto 0); - pcm_in_data : IN unsigned(19 downto 0); - pcm_in_we : IN std_logic; - ac_bit_clk : IN std_logic; - ac_reset : in std_logic; - ac_sdata_out : OUT std_logic; - ac_ssync : OUT std_logic - ); - END COMPONENT; - - constant SYS_CLK_PERIOD : time := 10 ns; - constant BIT_CLK_PERIOD : time := 81.38 ns; - - --Inputs - SIGNAL rst : std_logic := '1'; - SIGNAL clk : std_logic := '0'; - SIGNAL ce : std_logic := '0'; - SIGNAL cmd_we : std_logic := '0'; - SIGNAL pcm_in_we : std_logic := '0'; - SIGNAL ac_bit_clk : std_logic := '0'; - SIGNAL cmd_addr : unsigned(19 downto 0) := (others=>'0'); - SIGNAL cmd_data : unsigned(19 downto 0) := (others=>'0'); - SIGNAL pcm_in_addr : unsigned(3 downto 0) := (others=>'0'); - SIGNAL pcm_in_data : unsigned(19 downto 0) := (others=>'0'); - - --Outputs - SIGNAL sync_tx : std_logic; - SIGNAL ac_reset : std_logic; - SIGNAL ac_sdata_out : std_logic; - SIGNAL ac_ssync : std_logic; - -BEGIN - - -- Instantiate the Unit Under Test (UUT) - uut: ac_out PORT MAP( - rst => rst, - clk => clk, - sync_tx => sync_tx, - cmd_addr => cmd_addr, - cmd_data => cmd_data, - cmd_we => cmd_we, - pcm_in_addr => pcm_in_addr, - pcm_in_data => pcm_in_data, - pcm_in_we => pcm_in_we, - ac_reset => ac_reset, - ac_bit_clk => ac_bit_clk, - ac_sdata_out => ac_sdata_out, - ac_ssync => ac_ssync - ); - - sys_clk_gen : - PROCESS - BEGIN - wait for SYS_CLK_PERIOD; - clk <= not clk; - END PROCESS; - - bit_clk_gen : - PROCESS - BEGIN - wait for BIT_CLK_PERIOD; - ac_bit_clk <= not ac_bit_clk; - END PROCESS; - - tb : PROCESS - BEGIN - - -- Wait 100 ns for global reset to finish - wait for 100*SYS_CLK_PERIOD; - rst <= '0'; - - wait for 100*SYS_CLK_PERIOD; - ac_reset <= '0'; - - wait until rising_edge(clk) and sync_tx = '1'; - wait for 100*SYS_CLK_PERIOD; - cmd_data <= X"aaaa0"; - cmd_addr <= X"1DFC0"; - - wait until rising_edge(clk); - cmd_we <= '1'; - wait until rising_edge(clk); - cmd_we <= '0'; - - for k in 1 to 10 loop - pcm_in_we <= '0'; - wait until rising_edge(clk) and sync_tx = '1'; - wait for 100*SYS_CLK_PERIOD; - for i in 3 to 12 loop - pcm_in_addr <= to_unsigned(i, 4); - pcm_in_data <= to_unsigned(2048*k + integer(i), 20); - pcm_in_we <= '1'; - wait until rising_edge(clk); - end loop; - end loop; - pcm_in_we <= '0'; - - -- Place stimulus here - - wait; -- will wait forever - END PROCESS; - -END; diff --git a/lib/ac97_ctrl/todo.txt b/lib/ac97_ctrl/todo.txt deleted file mode 100644 index 7abc706..0000000 --- a/lib/ac97_ctrl/todo.txt +++ /dev/null @@ -1,2 +0,0 @@ -2010-07-08 -- RX FIFO diff --git a/lib/filter/sim/eval_lowpass.m b/lib/filter/sim/eval_lowpass.m deleted file mode 100644 index ccac021..0000000 --- a/lib/filter/sim/eval_lowpass.m +++ /dev/null @@ -1,37 +0,0 @@ -function eval_filter(N) -omega_lp = 0.15 -omega_hp = 0.05 - -omega_bp_m = 0.02; -bw2_bp = 0.02; - -lp = lowpass(N, omega_lp, 1.0); -coef_lp = hann(N)'.*lp./sum(lp.^2); - -hp = lowpass(N, 0.5-omega_hp, 1.0).*cos(pi*(0:N-1)); -coef_hp = hp./sum(hp.^2).*hann(N)'; - -bp = lowpass(N, bw2_bp/2, 1.0).*cos(2*pi*omega_bp_m*(0:N-1)); -coef_bp = bp./sum(bp.^2).*hann(N)'; - -abs_lp = 20*log10(abs(fft(coef_lp))); -abs_hp = 20*log10(abs(fft(coef_hp))); -abs_bp = 20*log10(abs(fft(coef_bp))); - -close all; -plot((0:N/2)/N, abs_lp(1:N/2+1));grid; -figure -plot((0:N/2)/N, abs_hp(1:N/2+1));grid; -figure -plot((0:N/2)/N, abs_bp(1:N/2+1));grid; - -figure -plot((0:N-1), coef_lp);grid; -figure -plot((0:N-1), coef_hp);grid; -figure -plot((0:N-1), coef_bp);grid; - -mean_lp = mean(coef_lp-mean(coef_lp)) -mean_hp = mean(coef_hp) -mean_bp = mean(coef_bp) diff --git a/lib/filter/sim/lowpass.m b/lib/filter/sim/lowpass.m deleted file mode 100644 index 292964d..0000000 --- a/lib/filter/sim/lowpass.m +++ /dev/null @@ -1,20 +0,0 @@ -function coef = lowpass(N, omega, scale) - -phi = 0; -dphi = 2*omega; -if (mod(N, 2) == 0) - M = N/2; - for i=0:M-1, - phi = phi + dphi; - coef(M+i+1) = scale*sinc(phi); - coef(M-i-1+1) = coef(M+i+1); - end; -else - M = (N-1)/2; - for i=1:M, - phi = phi + dphi; - coef(M+i+1) = scale*sinc(phi); - coef(M-i+1) = coef(M+i+1); - end; - coef(M+1) = scale*Sinc(0.0); -end; diff --git a/lib/filter/sim/tb_fir_iterative.fdo b/lib/filter/sim/tb_fir_iterative.fdo deleted file mode 100644 index 5260669..0000000 --- a/lib/filter/sim/tb_fir_iterative.fdo +++ /dev/null @@ -1,18 +0,0 @@ -vmap ieee_proposed ../../../Common/sim/ieee_proposed - -vlib work -vcom -explicit -93 "../../../lib/misc/utils_pkg.vhd" -vcom -explicit -93 "../../../lib/fixed/fixed_util_pkg.vhd" -vcom -explicit -93 "../../../lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd" -vcom -explicit -93 "../../../lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd" -vcom -explicit -93 "../src/filter_pkg.vhd" -vcom -explicit -93 "../src/fir_pkg.vhd" -vcom -explicit -93 "../src/fir_stage.vhd" -vcom -explicit -93 "../src/fir_iterative.vhd" -vcom -explicit -93 "../src/tb_fir_iterative.vhd" -vsim -t 1ps -lib work tb_fir_iterative -do {tb_fir_iterative.wdo} -view wave -view structure -view signals -run 20us diff --git a/lib/filter/sim/tb_fir_iterative.wdo b/lib/filter/sim/tb_fir_iterative.wdo deleted file mode 100644 index cb193af..0000000 --- a/lib/filter/sim/tb_fir_iterative.wdo +++ /dev/null @@ -1,144 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/srst -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/clk -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/h_addr -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/ready -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/x_din -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/s -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/xo -add wave -noupdate -format Literal /tb_fir_iterative/coeffs -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xtap_cnt_w -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xtap_cnt_r -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/htap_cnt -add wave -noupdate -format Literal /tb_fir_iterative/xi -add wave -noupdate -format Literal /tb_fir_iterative/yo -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/stage_en -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/fir_stage_clr -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/fir_stage_en -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/cnt_reset -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/x_valid -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/valid -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/y_valid -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/y_dout -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/new_round -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/x_stage -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/h_din -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/ymem -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xmem -add wave -noupdate -divider {Xmem Dual} -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/srst -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/clk -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/h_addr -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/ready -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/x_din -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/s -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/xo -add wave -noupdate -format Literal /tb_fir_iterative/coeffs -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xtap_cnt_w -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xtap_cnt_r -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/htap_cnt -add wave -noupdate -format Analog-Step -scale 10.0 /tb_fir_iterative/xi -add wave -noupdate -format Analog-Step -scale 10.0 /tb_fir_iterative/yo -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/stage_en -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/valid -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/y_valid -add wave -noupdate -format Logic /tb_fir_iterative/y_valid -add wave -noupdate -format Analog-Step -radix decimal -scale 0.00061037000000000005 /tb_fir_iterative/uut_fir_iterative/y_dout -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/x_valid -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/new_round -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/x_stage -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/h_din -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/y_stage -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/ymem -add wave -noupdate -divider {FIR Stage} -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/clk -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/x_in -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/h_in -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/y_in -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/xin -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/hin -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/yin -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/prod -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/x_out -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/y_out -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/s -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/srst -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/clk -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/h_addr -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/ready -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/x_din -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/s -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/xo -add wave -noupdate -format Literal /tb_fir_iterative/coeffs -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xtap_cnt_w -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xtap_cnt_r -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/htap_cnt -add wave -noupdate -format Literal /tb_fir_iterative/xi -add wave -noupdate -format Literal /tb_fir_iterative/yo -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/stage_en -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/fir_stage_clr -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/fir_stage_en -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/cnt_reset -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/x_valid -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/valid -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/y_valid -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/y_dout -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/new_round -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/x_stage -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/h_din -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/ymem -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xmem -add wave -noupdate -divider {Xmem Dual} -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/srst -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/clk -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/h_addr -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/ready -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/x_din -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/s -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/xo -add wave -noupdate -format Literal /tb_fir_iterative/coeffs -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xtap_cnt_w -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xtap_cnt_r -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/htap_cnt -add wave -noupdate -format Analog-Step -scale 10.0 /tb_fir_iterative/xi -add wave -noupdate -format Analog-Step -scale 10.0 /tb_fir_iterative/yo -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/stage_en -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/valid -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/y_valid -add wave -noupdate -format Logic /tb_fir_iterative/y_valid -add wave -noupdate -format Analog-Step -radix decimal -scale 0.00061037000000000005 /tb_fir_iterative/uut_fir_iterative/y_dout -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/x_valid -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/new_round -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/x_stage -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/h_din -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/y_stage -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/ymem -add wave -noupdate -divider {FIR Stage} -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/clk -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/x_in -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/h_in -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/y_in -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/xin -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/hin -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/yin -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/prod -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/x_out -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/y_out -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/s -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {5100000 ps} 0} -configure wave -namecolwidth 140 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -update -WaveRestoreZoom {0 ps} {42 us} diff --git a/lib/filter/sim/tb_fir_parallel b/lib/filter/sim/tb_fir_parallel deleted file mode 100644 index f784c1a898ebf425293acc60146ab6ba80a1f4cd..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 1354927 zcmeEv4PabFwf`nfOVB`rR4rJvV1f2Qu}H<%6b#ra1zTL8fhu5I`auinhiw7{8wjS0 z*=|>&CRikDN`pqNkMJk>@=B^piA}($L8=BU5H;!z2@*9tq6YH+{mz-Wdv~*G(k}!h z?cO^x_s-0jGv{-@?(NRpkEf-j1?*pXU{rvys;^{ZPRD)PJ;%wT>4AxXqXUxzrv=_0 z7=si(n_i4}@SBJX{EbFh27aUPn~(VXJ2Eo)J05ZV_zcPN!z~a%Uj8QEkCO3Y{y?@q zm$VNZn>iW3_M-xU<_`y?UOrF9YqRkFEIi|{9dZ5$7wh0}1u9yBy7`-kIDht8@DBw` z7gZk}STyO_O#aTqGyd%J%kUi0L4N>4-YI@(#VnJ`(Oe;|M5bsxxIIyHag>cS0Y ztzUE22Q?j_OWQBHG*7a#9fbL4{62=?r|{$76?zMtjC;_8KZ^V1_+4h=AICk%gx`(( z`|vvkzYm$TOU#|OOMT%J5oV8`YSPZZeGYyX;+JXC0B&G5eplkR0KZS*$G=bNEpWEE z6Xx^qI}N`X_|3=f6#UM|?``1UWJyDADH+%lG4W}#Tm^qX(!=6(S&&$?+Y_H$rlI7$sfqT`+E;Uq%G2p z|L=4YAzzR#-izNmP1*;{ojmpt6DFNZGvQ-#pJ~G9;yw<)x8p~?y8yo_`0;Nle(%C> z0)BJx`!D?Xcd_15UT-t0>{H_D%cfEHoA_!IXFu}!I3W8Q-_8;qe+RI3GUBuD&&nh% zFh0e+UuoX|JnsA>{W1Spct5QwEAwY~kMDn(5AjF1`TUQJ;I9ck#_z$8JdYdb_%8#q zkbm;MS(y(Z&ioNmpDlkKU&P-n_%T0m#lJHA7=OvUf3k^RVB%A8=kqxzzixY0W~s!p z0yiU#e?|E5`IUIyUXhhK2L#9Z=a~G9&GV3nFOmF#z(TzLAn?ULyZC4M^)~Z9bq(wL6ylS8 z^!p+69ONj^>rI?`P2e~251RNM#2bNM<%eSfJIwR{#hvf3$B%zj{=E$NF88&M`qTbR zMBq{rxeIsZKMF#)4D#;*DK9HQk4?mL>O1~f`Xt=^TZSL=2Vgra%~zvgY5uZx>(;Cb zEX`kk%c{V_OKw_t`LgR*t}j@&?qm6j*RNl;KCp1%^{dvbUbwzs@w$SA3-RKbwaZqs zh*d1%+(7=C>jUdQyRIOxWZBC6!1DYxC~a}U;?*CN>x#g#4Qm67*RNb1SiEG-`W12w z6s#*;y@X}l$}-LlTz{(+x^VWVF1=vh#UBeST)BE>0aBObuUWq=uy8q|h~2zyWx+Ds z*A^B?<|P(@)z{y!YHeWsE$f%8S-m{4zF_H^!h%5I>g$)`z4a@vU$$y(!7b~T6$Dl- zTeWJsQ{oEU+Ar^?Y&3+FJt4m#tYIShYAm ze~py0IKKc`SaM@v`SSciG-cJQ#c0}fYuI*{#G290b;~pd3n5r5uV0MEYgPxA7k?6+f(jQFu3xqk z-2`+lG2OIkG2lSi`RJ*emYc?+df;-|Qgja9zHa?`eHlrsmj-THyK>>GB}*4d6^sC) zh0-V+xoL5J;WBxTk5IUT0p!B?ll4m$qeA3fXNYJaIt6%Ul7WIjLb7npbvGlUN?8NSI^){4ceLBn2#)r-*&d`Ht4UUv&`5H;_;6&XQ&As@-k1hNl$kB$x7^1gAe5nn}DLkX_hNiGI`YU>+4X8D!&BrDjw{qn%v<}~m zqOuXsmiXwv$t)UweE-L|^I81;F-h-_N_d~Tlkf9S%g;!9KizwO!nwz0j=3@*Ho|Ba zp|lM~!s z9gfZp-l05dd52P|;~h>`J@4lR0u8*wNRROjhpdtJS@2hRKR*y?;T_IfEAP3`&%9p{ z2(#w1?P z_;|)^CEmdJM8>Nm9%Fnm<7E@Ng?_hi_;{l1gjBjAPr=RWbX1tj3c8T{eUdni@ z#CsVpV>~ADKE}5)UMul_#;X{wk~leYMGfO+5+{eQsAarZ;^fp7^^C8TI5~DjjPXT? zpZ(%z!oMx)=n2lhe8nQztt)y?IVSV6D_3Ow@a>uILUdqnSs8fy3U+Yd>N_60;=ZE; zmq$uiQYcoCKG3@0>c<}|i~p${C_e8@`alI)T@y-T8QUkL%7I^O<1LaM`bA;ap3!`s zhMfBTwi$4_QQpa<(*OeFn=&Rb&26~xpRYv4iHQD)&sZ7qJpLFicXXE`W!sK#ACpMP_}c_#Mu-MW*`;`Y8Y39vm_l?gtH}#E5hR>jBDoR z;CO^fc}4gH3FC_Ji4w*Y;rB=wSA-`>7*~W(k}$3)b0WfFUJ;%oVO$ZOEMZ&`o+e>l zOJZk+oze*Y=VnB5vmR|vm&X0!R&CsFJVC?Eds~oMGL%J}EzH1%m1)kIy9})j|a$x={DWn|pvBhJ?FxY7Zq zvg>&Pb%ub-Ye{T+*r|%(e*&lH7P*N3%bv3FrZcw)LN5) zpzdgL>J-$v9A^hXt&5;UfLbS@)(WU~2Gm>umDiHktgurb!T$tM?^2wEfz^5gD&A`l zP!Whl5H_I3Qh<78&^^b3+CWg7O$LJ6*yOY*s4Y28BSCG6phSS$BA_-4s4WK6*#auA zAcnaT=Cvd?C+xIF@IL|UHm#Ikw;HhV-d+J4fwl<32JE&JU@r)|8*erk-b=9CO$LI! zugU39usd>`eFVEBf)W9Chk)HKV0Rd>=L@L3mc)W#$Bp2B0;p5tpt=TByw@$DBG3~- z*nrxT0@P0h-6wA{pmr0~K9hl<_BJ{F3Tl6j(@RkMBPbD|_6w+e0&0KP^WdO?!cFeo zSDKPG1>OJo=fFToV@66ra*HD8-&2rODmqC!2PsH$3k@2Nv>^G5Rzy$_Qjk;>7*LP2 zAo+M4)PocxFRVA9zMg{QF2&Cw2$FLw*hgBBbZA8c^&kaF={keqLlz|SE;l7XkgR@X zXhAZ~!2EA%kzAqZJOn}V%36cQBP~d3J}VU+f*_e|K|RufOHHF8NKXA*T#%G>k8g75Leu?;ixBI_tt6IZYxv6lNex}&<3O$WGD--#-?`Di)z@_=;o9hf>s$Yj zTwSuO193%T;p+eiyq3grQ+YXm zRRGvPktzD#UTGjQv<>0q*d|;Qbnm{wu-75VlsN(_t^hkIVO~pOb5nUdIdQOEdOZ4G zw}6cdJwtdr7VL|I?(-`R*oP=z>fF2DXG*G*L4^Cn>B%9moLt zSiGi8_p5&!&0&?K)SVas@}*X_o_}m6L{HY9(F~=zzkY2r25WS9#}t&Vz$B#}n+TJ6 zw`-07F7HA2J!#_%lUV-}V?roa(oLq_;P4 z?1|4ZPnKs0Wo6qC19%^4<1l5Qq4AJG8k*p}HxWrp+mkyLhk?a4h&W2ftF@)${+ zk|s^*cdz=Z;7?+G?&mS4CU}!^tdedKKE?sg@*LnXdz_a7U6+#J#G6LTJjvXbo?kT}+!5~aiuhM3Y z)3Xk!>VZP(LQA^E%{EE_Rrjtt1&Mg60Fd*36RLPVz3XCJ16?1(HLdGB53G#zQs*@v zWTno)X6Ln!I0FUa^loy$U2+SU_iT2aH(){#dY}Q!Yzs12sAm)*b4!ZcKp{rovf1=Z za$9ypM*E-zI$uR^0qZwpyQlnIsEIm~I-)mxVFs@lOvvk_J8>a|THl`B%z%{lPDGkG zcz-(s&|@fvs79g^g*yl0r@y4AKdtB(RuFJsSf+f&;`*g@gI_!jy4!!I)kBa8jBHdG z!zt(lNY-|atYA0;k~s@;ywqOOopIUaLHFI)X{pk3jLc{TywDxZNEZRP&t%NjjBO_4 zbBiUTLE~E_Mglz|B*x(vE4KT&)LL}W=Jdd5KfAk!PNLEz`w>iyhO=+8;E zCX;}#$Q%@dy^5h;$e#5RBJ;q~y^KaJswpMy~BYz!rT~#elZxy?(fc>X7@dP0^x` z$9=ds#1#8T|>q;n6& z+Qi7b9wVK{p?nq0J(SJQ(du%#y)h2F-o5@t3~Au4JsH^n4pDTXf>+vnRd{dHCWWjV zQ56uNd~a-0*+y{)Xi zp%%NRw9+pDmOvUdIh==yKp8CSg5@NnG-W8t6SC=E*JcQ{>*sb2!dpi2>tG~*?a?G& zIUqlbRIooIIp8i?Amxi!H`ooEU}}dNI3PEyY`&Iyz;4)8n$hseTNL&>P}qzg9Z3pH zbJNTcg4Ax<&L3*+2TEaQ+4)2caU6)F|MF#0p-`Bt!;%3vkJ60Wg+j3yC}~Uy^&FWo zB@_%vtriEuP&^zadc%z=DVRE@q+pI@OsO3*h!$X``?H2&C=JNRm{PiqDZ$3-+Y_J} zwI??%(Dg2fil0v{3v~-Eej%J!^(5gSW7sI))UZEl%1AM6)c#3<3_5Z@)Fc^`hK;_h z8I$Ez3M#tEK+4$wV_SL@_G$Z!)+Zpq5S7dn99C+ZVd}LWlC1=kCtb>P?OUy!=FbR* z3|}+do9(`|^N4k?nB^W~q^s{Rwe6>?nTz9u#O2_j!tQy)_c=@8fT1ZNsq??9C78}% zu*Z2M-hU;1X=6hV0XN#CvM`Qa8^%&Lr)6_4NB-Z&b!`~hXzarDV~ad&j5v+5EG@n2ApK}1v3iW9@PEdR10J;p@wVJ?;|nW=uu zqZns*BY7R1R2>z?;Ey)Ih50@92Qit~?Lfb8E?$HdmpYFK@EJ3meFa#5+OB|Mv}<4I zhcR9~FmGSy2XNc$JW}dBu-SP)I`c{lf#pV=38S2GXk3)2g;z$g9Ok%pkB)nH2MS?o z_tRBL~v{@{y*wwJldWyr7^sW z#NZ`>OoTR?{fiAJ6r2(%Y>r%u2J578N6=kZB)tp2C*!>XPDj_TnjBe*EdJE^f)C;z z$;$?|;Kxo(%LxQp`v>J9i1NfzKsEh?N&#Kb?#pwvZ=8{X zR-6plX!ikI%E&=uDfh*bEBA9o@~K_-JS&xJi~SSKGNC zqwP3NQ!PU))#M+mjlfSx#kDkyW!6xQ5IAL#yi)TVQfzm@yR7tD@i6KLx_|kEpfMWC zm&$6ep4nDrG#D$Zk;-bcGF5S?2B}$*&<4p^PK}59wni$L;OW1FD!G(C=-y_lyhd{F zh+ti{ncMQUZ--R5BdL8zMU^WgV*i+~ltHujQ`AFcjBu zRO#?f9fyB>uoz6BE$7r1&pakG9GZ_BnnDY3ZA2V13M&e5zhP8Vo&??B=?rq`&6u-` zhP0s#W-&v(tYJ_caFy>lg%b5gJ%<@uAjd=tL9xUvDeR*PwQoRBb?E$^k@(cEGo5xT z@#8(sy$eD2s7s8hYNuAr+lxi^80HsBZYwEjJ9=GmhF@K5GGG|2)e;C~t*mhtAj$C} zJ^Bm?Jpw}SP#|owB|=p}a=KXDZ$ZGAP4{3Bt}q$$T1DEVwTczh8krY^dfr?{F^EpX zkd-bAnd#IQKp)k2eh2g1wxdBNRpHQFbd~9d5Vu-IC56*mGDmycgVI*gx{g`)(}rLS zcROJ;+A#<*hNT!!v;8^IH|81h_Jbi{EMW=>C0u@4&~2P81&A!Yqnq1JqS&0_95@F! zW!N`iIDBg)ugs&?1a{ja{XSMnF&ZjBvt>U+tz|bKht~?b)h2N`Qo-lNVQj@v_O6QL z6{qHHs_CG6-$l~GXlSWa29~O`mHGGyD{nIJB#F0?3f^8T8LJ`6l6jk57?E!C@pe3s zdpk_-`X+}fO9G&Z9FPQf8@yMeyxp)L-fkD(Cbu?)7U4SSBg)%*4R7;F&>f>>&^cXr zR~st43-JfKY^3=?`)-`?IoX+<8zXOn_4ewLBXGD-Kszlf`xtEDibd!euA;>_)9Dz@ zRjq>avp#Of65?QABo9Ku>pg~TrT&q#tyb_;OZQ+~j1{-3<~MVNRm#C)EVf1F zHN(2Lj9DX$34Fk0jFB;8o!!EiULV(}BsJtB@>C_L$C!WkzBF$CjG2Fd!GNDJzvs^h z-0qJt&(H!4W2*L5y;cS3k%EG&go3M*C>W_=7jSf`;ms|w7tBz80&hMoUAJBZLe%Ia zQoXIr$D0YNUeZ~OsCvWHWrjV=BNgQG)ExSZR2i^UQhCXKC{N-0I5a`wOFFAmg|8I9 z6=asoq13zk)xMPxBN(ugsutjYLu;{4?*iT0H@ zI!3I0e=lecUua0w)4p4*>PyzXnqh&>pxReW9?Ql8!pPZJOB`cM^t5le1tD4cYKC7L zwo2B%P`%=Ti0#l4nFrz8vbl_QE&5P+p6f+tI(6jvy3Vf&&wEr;84k@sFGYphtzu@1 z$Mb*r&IovZ!+9xq{(t;AhvE4TYXJ$$7@DpIWNvwIWDMbKp_#4bc6lUkOKN5Of{?-I za|Pcb>$NXCKPC*V4Hbq4!-G0Gf+H&V{l4eqaq8R#GJLBH`m~7A-590C({5CC08b>Wa#5Kx9*M1gH+pVxwTrj z73cxCHjrBzI-eD8%@FwKb)z$E_dx)(E)uiJ2+5^=N-i^u+!&bXW^W z(9p^Xex>On=me$d5ws}Hk@?4*Wyk){S%zU1BYx@NW7q_B=`pOT%MF4oSnI?4#~c6- zx}ULCUL!gEGQ!us1R3GAPi4fv(mxL5B>Km>h|@prH4ID78N21RJKq@oF^_-=x_|nJ zAyH3559uFkh9B4rhrvJA5|`Q%Jq_(y^2r)nGn`{GBx`8nA9ED#@c74{xo-qa{)Z2x zVDd@+oWn4AwHA<|l3`6BI0uZ(KR#Ca{iPX(!;h?gJXR|Eyshj_=^rl=-lkYm|G3KV zb`W=3-+U5u|ERtA2Jnx$jUwnC`(ZVq@i(OI{rksrKWG5-`^OP~&S4ny?OH&B_Eo(`t1yMRe8~PWkDLs;S12jHKK?OJ zqYS$3(*;+?Jvj(>z<9V@|0Vu$OgNPGnfk{WvsC-m8V*(ec(!)u8^b?7L(snR97Cd> z_8rnc)(kUjhQr_=Yl(lfT;ge8&uCB9zMA1-lOb9A(my7LA1VL%$*+xo=NFung6F^L z&p8awzgr7PP{#0!{1&j!98Iu*J#$nn;F0;q9~3gU?rg(-YeB+^n%`$`C)mE8xqZO? zF^?4vx-U&LRlX_x~ZT6@Q>gBRcY(~HS~A?%OJ$Bp*!#PajEirTjiV5KQ0!Ar59}Gj}5~X7=~5<_&)8-w zNkMzl8HPkX4LziPtQqdM84iPgtR>F2C3+g#v*eRCv}QQoWJuP~#y>7TZ2s~2U-7Xj zCpS~gAOH9?gF!!&XZUjt!{nQ^fCQC%1pVVHrQd%(#c=qM^^ds{BIsUcD|=J=$L+$~ zasPPId1n6D@V5HLd$bqd0RHhJ!TFz0H)QE4V~?v2)j!q>qPBum$~dKetc-a${NwxY z8UbUT`Ti7)d80q)FpSxCiWHEbeUGevyk5HQ93`dK$3NzYJV7^hsxL2HVBNOJ2 z4Tnz0JwAUtN$KH@;U5VZ6<782n=`agXH^Py2dCd$RV`3>79r zvi7BaOb$O%{_%qm!PWjP?iueh2=y!DoBcV5;rUnID+MGd<0I%FZxS-NPz8;hL-db~ z`^@db8dNN~Nv)=hn^dF$nQ<>*HVWQqTNFE$s!vzV;yS7RZI#tZIKeAnFT?$G>m#x_+_&f=o+u|xBP&jT=0dgrmO0=A zXs)nn0#^!VZavBLr>9G5hgyrI87{UNy16uR9+psc*hLKWvWNljV-Z6O7csPS z&LWBo{_1g(vNX0-mRgzxztND7c7}4;#+{IY>aOtT9ER$i8ZQMTP+iqQ(ZUW{xg%6p z7s(R>l+A4kRCk}?_PrCN(kLfEvDl+A1=TeQ)iowj9a2Gc;EH+>$^lay*4ZE{_SD4B z9d9Ppfwmfy>RL#30E+8hNp+w;oD{ArbM6zW!$Z5uu9Z~RVOQCK_S&LY$1NubaMg}H z9y!&0OE8mRrHD$sZmdDJROd$Kf!5>JjZ;d(@L6Z?fi_;lwzj=OFX41TcTV{ zVrXh+$p~mF_O28(HSl>~&S7Zkb}c|?%6Ebr#vD`-y|vr+d4ro79!g|iof=3PN<$;q zj@b^9chMc%JwqO^1>_&vZrj(26A6G_Ddg`vq%GBM+jZj%HL-ERJj{T-2mV9a zQth^#sTtp*BAy30vU31|Ur3CDr=k;YKhjiGf7`)P(V6c!NGkfXz#`& zO-1WW4YC&s%4npr=#OI$l8U~s84VR>Y<92>^|j)n*G3hb!t2eMxTY6mcb$m)m;%O* zD#+~0+T#oa^bY?9rR#y*b*VG>sJl+J4JkXCM=#JLCZ25lc* z9ttZ2%QeN;8hUe8I=&Z&{ol$tb{SFJ8<5&+SX+%(8~0E8Ytz~BV%c3aXeT2b(}+yp z`mFqTqI~)WSyOJLFxwchk-`E-i!OQh!z9>5ViMCei3HBTfynWV56x!p5tmNSbQ%Zm zJsP9!R{@|KC1jfw$Bs)w3juxcE?!3!%r}9X->!l5f_HW0Yj8|~Njs|GtgZzX*jDjM z1RmIA7{8*yNGFB1q_i#mF8vY%yK5I|ci4SUd^fG@Oj~XbJr-?epY>P7666V3Rhyk` z9A!m3*}V(%>N@vvHMH3Phh2nR1Z+x^75sME(-?p=Zc*M8&Kb(7_)(T&6Td6_+6G@v z5RG|8O+IKB;cZ%gu*)6YN1oENrKg*fNi8n_gD9O}0S~&($C_?yFUTC#Z4>gb*Mtvmh zu0Krx_=>WsNLh$re^v5*je4)D`lPDr#TSPr+7WSfB>UoA->=)7eYzo@C_@Fv+R)_0 z(9i(Hdk(gDz!!(4uhl&_G5X@rj~EkbrebL1-T2}>m?Y`|J5~^b4QSTGnHKG{S0QBNryap)y8AvNQqbn%DSYeL(1`Bfnp5Ar3yl5pkUQCqa zJiV4Lj*{lUd2fXCKCiKJDlx{f2cWYyEQ4oKP_f-wZzT9l>qkJ>uZ~GU*R%XNhoS2R zEx-_?4n|f>ANVPxk;K^OQ3ywC{KTlEHMNF@(S`N0iPDsiFfMeCbjg^v3E0xJ=yrcq z&8(`~tExGvs%9ZZ&^@GHLozYOM;?8|7*CYZE@W+Ka=4oq#MqjHVLA|FE9g>*v6aLK zdLxmM7@_amEHU!i;&DaP`Ym@C-n?D zKc^YKV>9^Y=O&%Y{f7rNKlkFw5l~&ht0}1NA%D(csO}ss;Ps-qC4$@A0!D6Ojy3j% znHB!mQr-1}nWa{WKy(d5b(-NEo8d4~-ObmJfa+fRM+&Mt&!2M`s@tUn2-V?pQhM4S zzqjH)0Bf~i_5hDr8krNjPGI<%GKu(0^0IvDC+4Clq(Bu#&+-=KdaR^QaF`Ef7S z);N?OJ0i|^rPBW_f-I4yUub2|n~xyhbKM9C^1hc-5ae$c`*IFLkc+hdD_dpA@WtYy7iGxs z#k7KByTy|EB!?XT)^9I*5>%X`asHgc z5OcW}@On{QmEiVy<)F8y&PR3Cf|(!p8sRj&d8!%8ZHB`{b#2#-fa(_Zq!6Ls@aG(c z>fWmbSP`1qJpGcLshW{*U;2~-HbSq%qeAd7*pB@1z zm%o^Tl%M*PFXu3%e1#V9dJ$xU^vXAsfBv%wGA2#m{*vjiHy=T6yvj#bLuvF;T`36i zLVwO-2y*ueQh=4M2Wg%*3$lBSkU(0udVfLkg-JxXhPx7^=Hn3$P+IwR!3aM#k9&dZVZ0sn^RI z=oT2tl*|6JtbrbBdWFh|k*xuGV~w7!{-lo}hq4A<{#^=Ep6<^%3@O)X0k0Q9{#|-y zK>6oCiy&W>re|2$^X4;8pPf4bf?V33f*`m1a}Gn0@7DsXY&}Txbo3}Ln7vGiJJ~$N zgckT5&lMLvmwEH?(2dVUGD5xB>psxF z$9X=jYl;AkEoOzcqwDOv}fg ze@HFQC@#uWG-d*gvrJ(FX^N!_b2v6EGnxQoJh0Oy4l33D{hL6LI zcJ~6i_8X~pbhm+C>K9#rvqbJyIr>@4#9Ft^DsQ1GeX~ zaz5O~kgYt;RL(S8d6UU83u*E)9LTOye|bw383FF=Q)0%2duYTlr5-j=4yamrdndQoVZ{Q%&VhJfkgdm&(hVoUJ`lc{x@S zYUQ6dMJ+(4oqV{BAzS%o%`a)T@}S8vpOy1vQ+bP2&Qw$RJX3k#LK57TCZ{YLA@QJE zwer!Xs71)MlMlBsWGg?$RL(S8`BTp+uC76vylg7xaRR%yG1XMw`n0xuqEx=A$tj&C zm170zUah>;6tx1GcJkpihHT|!nqSgv9OEwb+9^KA@S5RNe*FwKJS)U(?De5A?C1_Z8O-o1^fw*76|{zU=; z&roZU@5!tcDD+IVeG0|xrpyhLU`1WGt-pS|N7_v~L87P=$p=dHWHX==4Hc;@3r@OZ? z)j-ksYsE#CK(SPy;I@TYfr4?USA}A|DYF#0ck=l*hAb4H(}E<;LSZD^_DzI>FB>R2 z1PZ1aD9$%f!~}|K1PY%0+A2^m4t1(fyr?|Cy$rc`^7%G~EEF&QN}3~S7K%qqjxBi4 zKAW#qWdlX8K*3Z4#c2kLT!CViK#_}UP@rHOMx8?OOO*)QYms{=pKoKx zLh1yc3An!?Aw()s8=vck=e_Px)3;u!0rG9%+7^ZLTgPqwEuKiZz2)*Rmb z=L~UAiP;#TOnQo!0tfd-yTQXWvU}j*bhVzCfD1GMcZTFyv-K z#YqZ;Vz+1@TK2txf!n~yboZj!^wcj|s&yH?K7d`hlazDEu6N?S6w(ehjU^Wegz9y%C8bavX6)yW73+wuV z?!Z$j%+Z~e)7u2CPM|>>em|-FqMt0TWW6b=plebFjux*79Xzqi;!3Wgzjy0m48_xJ1zSs7q1mv)9G|ofFe0jYgB+ z4%DHDXRmGUI{Mkst_JbOKBxKVqF*hKIKQgPS`IVk=~a7wb8YL>tA2&0h{4}vOo}d@ zlz{?SP;rM-+?zYLg6=N7;XuKe^|dGm=xcI%S`i}Bt8piqx`XcKUkK8Pruwd_zkyTS zor&W5o}Dnsy$$=hfvSD;VAObtQ?4@jtAEz1H~3p1-P9&n+=mk_WTW3W04lh9`f&?b zf3AnXv_c@ZH8o=U1z;j}yrTg37=VG;r=RoyuI>Ca5bNt7M~c@`0ARQkZ6b#26EM6M zWdilY@CFUyjeSn+>7t(j!#@)Yw>-V7azt3=@!Irqyqey2(H&|*% zt03#y(X~iRVuY$I2Q$J9Kfg&wVo(Ad*#TZj>?laCFB=}NO zTQ2Sf?~nX+2wc45vSDz+CZaAC71S?N>tkL`uBmBjyr#>Bs;N0eO)IJzUyIPio!Q)L0uT8A~#2IKBt-M$D>rp?Ix#fvQ)m;^IQx?Z*O7ce7KDv zTX~MDoN2c5G*fvq(&S}h8>;8RR8#qDj|=4WGofoeaN(v54SO7 zE5E>0&NN&3Q6@(l(&S}Rx%w$gHI-+W$~Q>m++JTQl{a|qNrRHv_6}s)$%oq*vXwVB zYo9aCR=(NfXh)j7Y${jxgsGd$ zoefK_FURR$#~0GNrt$??#C@By(wSX?8R;_~g(;$Jtp$x9aQeD_jCJ3p(n-F8u|3?> zEBns7bDW-a&}0wtGK6~o-Uv>->!*z)ZuV;Zv=N#T$wS+E!xzHO=%ovo z2RFk5?m>t039jE(o*C+*h!RuBW7^$Gnr~UT@#wgdB!+;EF=< zq75As5M#fo!nN=c*fP1)S4Dj$Yr1=;&Duv6&vP*z;=T_9GKl&_#wa(#zK6v;ZdVOT zGVMe&x(Po#X5OR$J$@L_nw~U24Bd$^WVkhrrdv@d&I0R64Z~=+*uDoCdI&?ez;NXi zcXVf?$ttO!#^!`W(;yC`p^3Qa_XZ*r99NA_FvsS!DIMUtVF^bV=_BnFF` z^#fleyEr}^xFt(J?Z>uu9ivCYy2np~}h-M-n3yO!i=f@;tsi za0xwu%o{ca-RG6WqoHic%<=F@gfSnK|*q zaA=NX)nW<|);S|q9g*3i9Qkf(!T3nU26>b3%UL?|wCkD8&bZRhCne)XTs5Phz$wHD;BRHj;IA1=0&HVj^&mt$S2_IV zWz!{Eqj6Cv1DY+yN=7D_IPb`vl7Np`d*1M+VAvtW~g3x-z?E38zOa z;ci?_k**ZkJyelvZIRF}F`iH+{joU<-O=Fhj>{mKz;YNMDSa%GS8rZR?5Q8>3*kMH zygGkguPeWH`ZK1`72{ zm?G7-o^)}Z^Me%VLf)d>lC#yCAg*uJoZ zQNrcG%PK7(x~%W&&-`2HBP?_>l>9|uj=8%8Lx$i~zr2A}QXG69UKVtt4F>$Tw9@OQ zmC6P4$3J3N>u_i#Eiz`g^>AnxZO(xK_dzA*{lVhRUcRLk+n4 z3y=h8I=OoWI^R+QUEVj3sYH!q)QA^KcJV3(dW-@5(J^8o40I+%DkQsv#Xzq_VmMUA zM{-Rz(2HN?6JC7=dOR^4s+O!;Of$kwp%z?ObwolrA*RwmXL>~5R|B2#u4kg5V%)=_ zRzCH{6OCm6lwy$oT|FeMOr9hzuMs(X-9ru|iX17$JoX`{4KI}J;#H8dmjQzuCIUH3 zid0B;2@7(zATb=O;Ul>wBWIH!hgTnR;)&tV4#}#;>_fOI)Q+nnhoPJhQ;8hLBJ#c> zhjAijE$-n^2cKHx2p*V1Jn-(}ff2!jzKVfidCo&iLmQbPREw+efa@5nV6s=To|S4W zj%@%l=su&=-xR9Hi%2Q1Z~FwsXF@9wZ3^Y%x({)8CB8}&4!MZJ6dNea#D^FW4n{+Z zcym|0z#h!jXgJi3#E4#X{5n*Ll$pE7hN7s#JPAZ9s*%d_9FkEc`Zl0S9W2a6vM*Mh3NzGwCkBjNQ$r6fplpLK}1^~eL%&^{RCXmi!ujn zkJCbmh(ih^S1f81lZEy-t+VfC%6oE!Gt-ZNILM(lN0a z;uCl)+G`0ij&(fyJOEj1kQ3pFa zQZbQ@ldK#?mt++Q@&KG7_qe>AjQ2}+@hT!=5(D_7yksIo0+VdH42wvZFOYET#met9 zC9DumV-^`~;?R}E0=AVh_!QzbtfNm7rf>MDd6oKORE3O8X&F39d+b+ZM>k{TeB73< z1(;aB{-DxNC=QV_jQV@gjP!6Q7rB031QBiIz0h3h25qoK(Ng%g|!b`Qsh zt^u^3bYVnM$`BhU_c%(IBKaW3x28+=vsk8(CE!Nb68LNhD~NOC9j35$iFxRqE6;c} z!;G?s)1X&gRrChqW$X{VzccI^@EfU@xnn2;*AqX79g{w`2qU)ZOu*Q2Q1CE!6I&y&D+jxLOY-H%|H%j*p`TN9|#}#3U0bau#12ZU9ccXkpk9 zn>>nQfm@DlavFr~kHRjETpqKE%ua)_dcRarYTAqwu1%$75oZfaD}!WK_)_`LK+!i>Q;YcXQKMNx}jpxI)e1sG^%DNeIsV4sv*Y1q=KGCb*2M?+d= zO~k2Yu{Cj2?1(t<-fD3*sHichKvMM(sQ7=<$7^;NRM=|yNr76yLo)y|b%t6H7WQId zFd8BUj(=Mv1e|#>oM#= zIAW*vQ4Knok8!J&dQR^ViK-ULdR8+U!c~<|NFo;|>!BB)@ zA^@NHNyk@Rtm1dJs!y?%oW2#XSR$$_DXJ0yQfUQ96$D776j3Pxgz_KaT0IWTs#J(V zu#QZEyRlp7>_(*xI0}-pI+9myz^V4YG2f~Z!2^lnfwQBeXorAPW5L-0aPVak6j3AK zmJczJHZC;18DSfoDc77wm(notqQM+`= zKHDMf=n#BYq78E|(jj85QEHY#T3H%&ZLQs$PeGYn`(_kv52jOum1R-|E$TKc0(ZOn zZP9VsB8tSkUhH-N$5yak+$riQ)g8JV$#^(P24pTwA`-%g4TIFYp_hC76UEQtK}HY1Dt15STD#y5cioS0`m z&W}%nEY||wxV-)|p|RVmrJa_L|8003z2k98>W_gOgfV)Axt=>cFxRHUZut*f4^9=i zg}chFH#o0rJ5JSh94N1!^^Ig+*W!Mq{B(f4K3%^uw0~ZIOP8GgyAT6Po9TpW0vgVRfbIHNsC~|kO>np zWFpSB5vvS~ke|kY4tYTH!$F>fgh&OGJsTv!6nI96aZ!~K591_1&F@HsTy+oy;4|id z&xnFAF9CeH$HAvbQL>9y0iPUY!Dk}CXOgW$7>>(tCL&RXBy_4h*>q?W^ORSg=@3t} zt6#Jj4v{p8Th6N0LC*;>l_QAauFEW#(NinU5VxL7)T2fRh7Re^*c{u&0ut+vVFb08dz_GWpS%>+gr4Szd zeyzCd@c8||L)Ag|^UAkT9iVrr`29Rf*9@|WVklN=Q>xgMDqmA-N{VWvDIAy%bfGCV zXbO~QRm7>5rf}Su=D6@176%zY0GHZS3d6OQ#nRt3_7&{YdimH)J^e!TW1X?D8u)JN zfedZXgO!F4zJiHcBSXp&j4X^hK%#AXV zF`Xz#_xJXcRu1_(jq;HN^BFj?d11_YR;LVWY&fZFl4r3gfY}P5_}17hVX>Ax<`H16 zG9blSg%-dQHSTg=M2{fNvY9unR-S+H0J6uwrJ^RevN*4DMlZnEVq!5+~FoR*4 z9E(Z{m%NIk`m=tS$dgp!3`-1MZY}0QQ;D^Tkrg!M&xzjJpT#^~3m8I+&H$ho=M`{8 zrx-QFbZSwiS(W1GiHB!Ok)LOJl$m_&=3}=leu%c-q6-${(JrjV> zmzaVc%UC);Z~U+2LqhVc+x0 zF4AhaB8F?pE?xr#6Lc2+91#fEVxAR=@};yWA4haLT}m(6MWZQDII;7i(085)($0u} zRp97k*I|GkSCur83UZ6rBPPazr~*VXXrIVy=o7ie`^2w6u_$^2GTJ`jBlHQAY%L5+ zpNwNbY&OhAFwAivfr>*mqC7XnMO>+P>2PyPjcV9rL>!W!V^fZC{{>(K-Mf{$Fcb@9 z@sr}lLY%=mjRG&H0x!2@=#;D0E2o$(_X+pPlA=n{dRwJ|(0Y~7dKk4ThfHe=O z_eDc((oFFxt?=G{mqTCPO&Fqj$_S*i(sM2J%)4`~c*5A#MBJ}?ujw)%}9{Gyt z|Bm>m5+R6)&4~V=#8D;F|8`*M;rXWj?~=^Eu_Y~Zxfa@mrMrHyNg~p9GN!*|p$eu& zq{T*G{_vkt=Kl4iqZNBPQS{{|e@@_MfBG^*3;4Ivm;VrAeZlgi2*m$TeR*nBi0EIa zFSRqSEfY9W=u7HGqc2r~sKstnqg5ksV$B)ANKVkbM)}ODu5xc@2Ims6NyC~5ZvuU( z4T^kGdX%ngYJCYWaY%jn#m$o0Dye#z=ocdbUSgagj3TM`KE(%@G4+URg6>oRUr^FF zUgD5z1CG4zOcMgQTEVfptIabJ4%-yW>!mNXJ&`S@{|`oAez8_2oOYVoxWEzMSvRIgGyC`vs{*^kqr+f+ziP4jDx+nu^>PXx(|I2o>61=ze{sE&i=P* z&Sq^6R+5#+q>HdAw-?4uRK~aU^iLgFZK4wu@W@&g7SmxQ8OW+FcwzQ2=s*{8F|a~R z(R@+Dye5xZ(X&(+$mh++6Lo;q6oX+~M}}iD1dFNjf_FsnHmM^ogW%4lu0PrX7)#-N zTA0nr6NDMF$K;Drg;pMrYLN<17YL{Y0uZmspwiBZi2LgUHJ)f(XDvpKj8&AC-wWGHJnj8t+K3$sDdAG8j}K%3J!S6&;-$jp^2R(Mj(P?xB4X8`&Iv| z+~|5h7hXt#Y!C{(f=MWlwM&6)912{i1)9!=p2hzFx2e}~6$D&gr-uGJR*YaY8LN@1 z?P{bGyUy~4E423K?o@gEc`tp6K($BHBMx@4R@#bcIY2BG=@>Ewmt_nY70JM{Q#W{R zkrsEeEv}9`Sg*zUksaFqvi%ezd5_LS6LnJ$(I;C?sqQ((%(Io*x@N9fqm*klt&2(P z8V6VUU($wjTWO3A*%dSyHpZID4+XYWwOJrpwCh|N4Lk!!Jxutf>O zw&B$oUK`kB(gu!BQRbVqH|-GqIz$#V6C?EaxJ{LEyTc;dg`}t4?x5UuMQ(Qp{ktN! zJ49|H9UOr4tf=mNhmH_J746Uymc*#pT0Tvx!Ac5L(`$JRdZLfj^s<^hsis$|>62=D zr5dE88l;PQkV1n|8RZMQqozuWMGQr*wP!KB>2=?kXG*hXrH#G&E$RA3m#){`mRh>b z6dCZ^9V*`rK)SwN3$(m=aMD$4FE+KurE9K0wL;SmUAk&o9B3K_z#h;_v7>D(1{|3taKf`uCpwPC{!4)x1SG%N*g9=E=vs9uKp zWw|9Mxa)H{zRn`*WT;&!~$h^6(9_D}iU%sYMsdaT>Us6E;Pa znsYHO=QMUEms~{e#+&t{&p(#?-%vL8zu`IqGp5+?hLHF1hM9j9@{c=}GCvI~f@7+7 z(lU07;Sn>?Do&;OCXwcZ;`I%};!KUi(++Oe0y_B(GuQpYX!v@tg0y$G>Pb25ezE#l zX&N?U0ZJ(7MZCFJjZWu|6TAMd1d)#maRKgTs59nFtKwdv1!jY_@vNF{zfTKW-e?G zRiZ!aES1z_rYwSjah!O@1uab-Nf;M5Itk;KZb*Ugs6S^S#(8W%rt;%US&q>HI@bVL zZ?&qLV+oD!kyWbQaLno8=XIb3Z1kwHp?lG0cNVIoe{M)n8>n-F+CUnH^tWZY6a7Uy z5PRE^SFp{fIP!f-{WY1ET0(zaeX}%K`m5J{<@XZvxfxdo+F!m^)4!hx5=>T1Qz}Ta zB+L|VYW@l>El%aB7PCHcQwp4);Ln+ebF+*+j`Mr80PDzR0APTXJ7mfpb#ys#DQSjv@fG>9se5bgis8|3e z{|ex5!`v*OX55~T#IT4@cBxtOrZOUF-z>*CbsoznMB|C(v?{Z@XcN9?!W!Xr=Qx|_ z8J9*x&ZsCYr4v7m6=FXWbcSspJZf|Fm$OCnfNZVW;?o1=B}L_;2g;;H&;#Yr17)Il z%0|?XOlb(OzJ|mT&8i5~kgZLQY-hmCa*nf=4Z#YkrO2xdsqFgWp3semj`FB5Sv5?? z(hp$08l)xA*U4%-td!NE( zySG*sm1$=utSYOc-iC)y_nru~dLV{=_4L4E;f$rq^qnj4npwZ5i!&u-ScYpX+f2Ya zb^^OWk^H~UB_X*X1(I{ur9krS{+x-DsUaE31D}-wIwwQ_S}VfPIL0AhPBf0aD<93V zm=OgVID;d!)Rc1A{9ZF!0nLlCnAX9=3(Eu_^9v2ESYgm?%cE+=(k_+<4bw5Qq#a$#UG2<4F@#cG~yZLKvAF1zIW_3Ow07h1DTt9FZyW3**da7bZagxcW!Yh7r9C8!S%Gz8%d&{t3dR41E0i0zK5g2Yoz|D#+wc zxtVK=LNA-Svb29fF|N0E9w{z*Bv5#q*KPjfv75v@$Pn*fJ}}!P*7jua4j9Kcqe`du zJd;Flsif0=t5Oi$Z=d$%1R8zb!650hSPSTUoGRc6WW;Ex2yqgXsDatI2i>&)5j7y% z!3^E$5Ma=q_Oj6sV&8CZm41vk2qYbK5a5Ml;awlnvvn{w=x%w~kMuLy5jy4@ zbRYSfLHcy0icF^~BS@z?KKD2U*s`8$9F%KVo{5$lnEHubAf|`Llm6?Vv zVMg30@a9hVjwl{8YHk-O&+|h{!b;@@?OmCojmP_QCbn^q7xWb^K)j&+>W&w_^_K1! zej~6)!*3|vp(9Jw6{u_{U!lTzCBUa)I0Ej!P8a!=XFw6fri|$O#o=2cSD{&~Ht}#aJrc z@t0*OkUq_yGZE>7bVscgpt|D(WE?_w++X8IdV=l<{pG-Q$4sr(=#F1LDXlmhx+5$| z|Jn*E&?sz=?}pbMFSkm@IMP$;j*UxGApH@4&P1dS(j7Tkfa;EFWIRH;V{J;^ahxC0 zp>)UAB`MnY>!16uli0>Vy5lM>z^vAp?CwHd89p?|EzF4EKw);&af9wX-?YTVD9uEt zC+L3SZ>ssY_ui~CzS0lCP@q41T?)`A_;U^edZiZNfu3$bH-3|X4j=*gbKkI_o5l#} zWq%z6`n~#b~q(%7e@0)4SR=P;oEcCobG1N|c89SZ9o-)2GgW1VNAaJ<)t_4c3o zx_v0DU#~SM8dTr%=Nty~(~>~ng1iEH3am$}Ea-l$U-`-)&`1SdBR6Cq_$Lc()piBL2X6;oQc#n z$WD6oS}CCOcl5EBBjXTu($~LjnS_&Y33gHo4vLXUow;J>HIBr`zEi6;cG4*d@ZqqN z9u$@RC*`37_pvX0JPGNk?4-x9NrCiCf6hdt53-X=wSdl5^s)caOr)puu_u4akMsmP z>8cKc^yz~1c3pM5e;@let=8B{-$%XDZQ@mPxh~ga=>p3G^s(y%>FX9MDIKtn{nMr- zq^Giz=3kux>0j~ZOho!1JLz~WppzdGb2lR60oq9!K(zI-GZB{AO(q77uk9ZDed&`M zMx}PXzj=>p6kW1rt&r9|NsUjX%CGu#ipJmV&zacxK?c;jw1DB2%BruvrBwcno$u=! zlc+6~Qt7-Z1+`7~=S-xwK}w}Y3s9wU95N22RKDhyZwX4J==Vmx9e`3fTdOrn<)@EH zD-MTJ*)8(z%gRFsu2f#!orLsMN~Pe+6i9!_pED8ZgOtiST7W8*N@N^Lsodj7dV*5P z{GCDi0VtJ*Jb~LNl?4j$;c&ixEJ#1;Q&RkaJKq}~O+tDqr7|!-1=7#==S)QUAf@s{ zEkKpZ>BxB4mC7e}N}mj+RGvwxR6Z9=YJ4iClAfyZ7x;4~Hhz#&dGrdY#q$qON8X|Q z!%=0H>iquU34^`z*pEg4`bAoEqJMa&Kj$!@k4XYOA9;uJ59i!vLHGNIpBe0xkM;vF zlz+J8@)RWZlOOsTJq+ld&;mTHKZv|TVZHWC7IZ(>`v$wVm-qn~3iKy0O96VeKj$!@ zmuUeW=>NBCXso~N5sV+}=M4t^E))VgcK>4`?@9%Fop#L%`wO9iRhPyZ2jU`;| zoUXMq;fQlbqS@81vo#gtVJJrAJuc~D%+7vGMAt;gOR&M^?oETs@m(dmxW+|RMsX^K z^VK}Bgo#)j#iWR-gJGE)-v=P{g9ZdOV7^&U!DJ8ige6^_B5}W`tPwRQf=rU4<*H{c z0er?h@EK9?*`U1$?ST3qBJ8 zK9g)6qB#kEgJ3_t;2?R1zYk~RVtoRxz8U^_qWxfk7BdSqG|8MWtJZ@da%8m^&s@u8 z{qm^;nf90W_~DHz0b#a4Cs(fn8S^l}h+;rq0tVzB$G}{?U=D@h2P@|wYB9h^zyOoX z@ktUE`r9GZ2lz-%cuK}VzhHn@9|q!yVL5-oo|+s)G4XF@>S=vBvILJ9m@k!N;Hns4 zoEXq^ix=>zUBpN^VFm$lmWk{a9xD)vf2}5;AnXS#d`_(J?qP)y z#foG%k9}AvzzYYl{B(<8B^#Ob{JLbUWC&Jx^w`@c_M`qJW zD~##JPNfybc|u|0I+>E6k+YgZA`+h&3-Lm;9<%*tl)U)Vrhmr0;TRJ6@K@4 z0jDfMoa-5M@@W;TWvA0W3Jbxg2WnZR840VgJ5Q_Sba1SvW%Fgh z3AQMgI`jafPK?XmFml@fo=6*T8o6zxAyScL z@kV(Cy#4$lCDr>CfJ(MNq?r9aPY@|q?9P`kQ?M*b`Qi5uN&dL4)|`SLZZMVDwPDDL zZ_@g6Ch|jbGCxew0y-CPO#92o$Yopdt%0z9jz~|#G~bqyZV1f=n2H%r$YI+8;<(M> z&8<>f)O?2q8)>q(`0S!jzR%&}|N5;3-Q@SI?G+5aQ5x~+OqEkz=LAq7}%&rV0!3R{)gY&YyUd8e4I z3Z027P^ll60VbIrw;8;-yMBp>+_%H1?&q}#B~1aLXUUECw0f;VKN3OmYvS4yEBkCdqSblU`kjW}d70G-I2d(lE84jC0MtIq;zdj4G9 zurjFUt7pdn?R9e%P^_6oPZylx1Nc?xnsW`n-yCrEb{>biQguN#(rp)vlQ2`f`RqGu zrN%gOrE>a@QLqv{=ehoz+1@jjG|1_1`IyvV93dCbd#V$TPY*%2_7&o^+3|f7f|=k5 z@x9m05$cxe`*8IZ1bf19N@Mtb_Bfm_T)kvK>m^!KT#K0mN^cS`MR|BK;yL2-(70gC zZ;CTcldBb_>5g^t#dg(!@TJaVdG_1!jHr3V5S4`7<3{InB$w>sRh*G&4B(HhAQNGV zGs)J$u+J47+7u`G<16in7>FlYQ+%JaVg^dZx3_Rr3^0@2QQcdqv@5*M%1E$kAMm$S?`EpK}Cze zk;z9X?Qb$V{Ayf%#1K!k_O})@7sWJ*7ow;LBAz3AsfY^3R57ak%{Wm}DSD^|zEEW|^1S-UbF>VsWf{F%#BOB4wM)xE^1+P9- z#1pO2t;H-tF-@|!MNzR7@f>lIhziF1MmOX3!-7;^vJ;|s7q>?Q3dcr-JCf7KZu%yQ zHk( BLdbX{V|xNe_QOXC*(){rL*y=`(y>!n{kU&NUw^TgPg<j zjLycRph8bUUfp9S`b3tgR{^-7``ssuE@9N1nre?hm5Eyl7^uGM%;BghZ0t{JO*ALu z+-cYSu7L0Ez}=pXj%~6WG7D{$TBqAu8P)w5J|p@VSR6sO{sJkb6Q3bQFKy)2m^b8j zfOMlt1xOiqik5k%bi;X)S3uf;XKtQ?WTZYV-GRLy^eW1X$xMErAP?6SKMZJi&1{ANIsM&Tt)E&62`8h`cxKr|3{=P zq~F3icPn6lVQP+?jR@7w!R#fxAvj6NCi?M0hPNtHc10}7H_I1{&cHYL#8r?@BmCwl zPb`AN0~5VvFqOSi$~w!6qZa!yJWJBnMBn`_Vr#E;sQq2L7A>`1TY#_~gj5MXPP%`E zyrUW@A7S9q`_L`(1EU*wbFXa0Lz?J}>h^al6xau9qGJ+rFbRHlW*nn?-H!ual;g8_ zwWYIFZghRy?YW;Vf;YmRN;J_IAjRs-YY-NZYCg(phX_iqGF`uj*?A_Nx7);YJxp}& zHW_51r}+Tg=YAbv08s7e1QY$;(luXE&gz1R-XJEr?QXhZaS7LB_oc|^ozUa1^mzB+ z9zQ{fon;u-+h{+?DQm4JetJ{&_#DAcj13RX#WfWUbLAcF@!1GVk24Wn&HT6pd2@gJ ztm$z^6Mda{kN2hO@%j(Pd%V}34|o%M{6uN#<;wJ3-%iz%8K~3J?kov2#q({xyIsnR zi=|Y)&Djb@qAp+S&xzhOA}ghD({rxW;>}N8iM&Hit$lF4kR7qB<)KC z{U6(WjUEQ{TeScW>+Q%p6xN?Fu%P>~{@K4M<@%Nx-{J>gD9{6`K>w&e=P;oEXnG>S zoN7T&f%Qoq=zgsKpl1;1KdkcMZYakg!=ChM;ljfzOD7&k&t(xyQlJNAf{@KSJ%VX)F_%g}FYRL9yUG zR40IczJUK83w{p;qB*@|Ewg&qXUqei5d~jf0{C)|gTDbUlZP^$&h76COV_3@ev>U;r} zS07g6iRJ_vo%>Jre*o$Z9T`zjckrmv#96zCii;jfF>5Eu3A1+ffB+x(#Z_nR7>5s{ zKG1phCJEp=QdZKyLE~BSQlbDJ<-DX#EAV3cP?X(hr293}&tD&E|kx;NZTcs2S496l~G z?V_`#9y4p_ZOJDy0anb~aZA2@XiH!ve*)Iae6Ysc7w?fWqGn{FH3DY~!mbBp*jc+a z?2)%8m9)rtrn68|+-LtuanVl_XYDQ$@M@+hcsgs>&JxwHK=~3gvx43P3{Ec52^I2u zQu*;Qfoo8Zeikj6E&e}y-veJ~QLLTP0tJGNTCoaxt5iiOTu{_P5F&E4LMsPopg`po zEK;>dfffp11Hm+s^dwRxl?c^F2@)h~l%Nq)2@sk9QKJTp5Hv!-H>OIIc!}Ohzvp>o z-+$+vv`tgE3Ag>F@1H&I?#|54?99&Y>@L(Vyhg+#Of2V=Opm}AY)cGTuQ`;T7^F`C zyOnH#Kw#Exh(3WWwrP{-#?AtCd(&*8le)tIP(ik2!)^Pt4n_OJ>?%Do1vZ$;!;#g> z9~$4B14);M#v`l}-@ujy`@$`eoN;-;Kq5YieWex9zksHQQxm3b*l6V%=)1-)tpIrO zE}Vq-{RL{GQu7yNBD*Sr>}r)0?X(uCoaOqa1y?9TJu?OT&CIwJ+pUZ@?=M%O*)VW) zGw#+;vq#OGakrs%FskYLN`yQkS$gLmo`tZtMsvmqn=xbaW-GwW*eu1QXwYq9hDM#Q z-_hfpT!#Q3T-`z7>ud0gewQgQmH6f>0lk>5p^rcV-2*+W&Z}e-`zqNQwS2%o+8RuR zt-+*}tAo!{&PhI$ie1gpTdc2`9KaqkmAG3)(i=2J$37Iw&)zb%URR+-@c9;i&ldw< z9|3&bL+~5%LCGdw1%3k`9QaHG_)PNa;IqIl;6v#W{$!TkQhmkbK&QsQFBJI4_~6e{ z{w8J8HK0D<0`U1_;OirRuX_l73qEkie{qVW8LvM0{0ZPQDYahN%>6>s=x8Lum(HJb zP4BI0w(=KVBfV9a2pd&dt(aCkx9R*pR&6H%=9e;+^8)SqlHW_G>pM=7Oh<|xU6`^J ze?bFw;Fo{`d@%~}iQT{MAqBdST(XH*HDD(n@Q?h*L{NZ9ejR*P1J2}wBp(Jap3^B% zD+=%$p+J}jPdrQ2EK<47Y-&^IU=--VZ~00k1^5QT8&{(M-${WfxcduBBNn6SA0XO` z-vc`EMRYKG2=%>v>I19@o`PZrB1l;8o@=0mAsZ$7Avb2(}(9aEh;ixJiO;? zSs`)ZTS}dy;lg*~GK4jLZuzO-(`ez{7W~fHF5UxN_+q&Dwx!wX#3hFrT+hA+&*`|- z3m0A^xP*zOMEqg~S*vCP43{Ci=gWQ|E__Q#=@>42CoX-$WthME#;0&$3UT2*z=bbq z?V|69%b*IXU_sJn>9{lq7hWT{D6x{)^2&9}YQ=12ts3AOE;&#?`BI|9g>NZ&{tXwt z6PGT5FonOy+Jz~^h4%m#zNEE_z7w;lpeg~xYdS8C!iCoeE@7fsmEc(wGnKV!nWN#t zadW=rYKaTqQnEq~7rqZXvAJ|3stpyJZEIEfdi+?tiPxN!(*qnce~e8nb^waD(oS4$ zYLV|Y*J&6Lub<4(W@wgi;91SY+D9W`Uy$wcah%aZ8 za?r304=^a(-zFqDXt;L1$hpO-Ykm{Mms{?-~>LK{+1-^a(_^XgA@K@jg;O`d!pRju0 ztW<&6`bluwa7R}NfzsTXgV6ioyf^NYgV}^(y{=Mz!4RPI2>epKiB}FZt_)@{FBB#x z%`!~hkKcWzSHQBg7J~Y0Iw6XzcyPxm+u8Zf#%!vf zNx$$K5z{cy9l-813WxVQT9G{u-#|JB3J*1=#aXDuvM1U zf))I2UHPfMPwQf2hQ)|qD@&{NO&zWlvrGY$qs~{IOIee)`XU{dFe~m#g{f@`d|(RC zgHQ^OgmB-Wi&iF{KVbkZ#Fy3u9Gnuo!H6huaHcs4Hon#HiVcc>zc!LN-UYCR^l{Po zR!09_Sl#P$=yHB%e!VmfU8P@mjjk|=Z!Ao4CXZlBaVB`ey9@xi4R&L;AHRdP6}e3^ z%J8hXXC^{sD|qwXaVJtaRk#|jSo>`0+F%V+|0o&B2*c!$rNy{9R~?rDl(E^gDgcdy z?bvWxr-M2wbWq1S9n?{wgF287Hxts)9#&CtN++XhmX~S}u7i9gLFCr~bTJt9D;Vsc zw}|HIu~vgP-uKFtV0vRx|F6+u1hRRFWb^i!`eNYL%F-nS9j-gcwiXR+0IwmjvUCA| zDqV^zR~HbO8rMklpVbnp8e&x|tZIZ+t+1*QR!9d{NC#F{O%>NHyZ+2!HPbC)PRFX? z5Cd^W0QzSHx@Y1vaIfoAuwyO$;=Ktb+_{%+LyAXh)ujsS%m{US@n-VHIc3f%#ctI% zhuOiv`6=YpIhD@EvzUU3N$j4*o0oToV~P{-iWziE*ZDTw2ELTZ*h`Qet@vJA5@{U4jT(~PmrN1|zJ?Yi+?<6MIc#%yC4%BY=`f+xB}{t!X6WTa zG_dI*O1(mS#bfAQEpk&o_(zWF{!l49?(0b!^l#Y6HI!7!Q=)W=kAGkMe zcaov7q7AV6hHW0$3o^ef9Dl=}Z2RDM0^lrXbJXE|%#@)0v4?#-32TIA6eNEN#4xEZeJLJZI z1lJ9CkB@dtb@ZqfgQ^$L=oTtVnTTqb8@DaIc@<5LWBF>Ut9_~yS1=M5C1a*PQ++kf z2pOr*TL1v#^WRsh4bF7ZdM6BT)iCG?hq-+mK%_(%YW%6R8&|G?rXUPEjfSG8@Dh@R99kJhTTv#*6Gv{zdC>5k*Kp#M;%eGBh1eG z+E7x|pgA5blHwds1Lkg;I}YQqM{w4oHA4F?V&;U2JX(WU8`~01fIkNdhw>AR zbhS32r`D(=(S&`02{BH|BE-#vxH*8h*&uEv#B{{_5Vw{TwF=@EmP?3R0dY&J5S>=b z_8_L~-B$QUAPy6CCK@1aZ%cHrWb~K$iFQKVkWMLO~CXq23C=g*6^jUFsxy}mcKP~E&JT6f^?Tb7%ht}!| zL_M(qcn7F+wsDRq!fTLRu4&0sB@@f%cc~4#+Y&uSksdC*2Ss|Y1|My>*S16tDbkfH zMgv19Zj##MzuEg%4W9-QlF2JJ!xl5;I;}mlip<)xN#O=(ODTu zpDj)!XroTPo}Bt60k=pUvEuR=z2Wx}vpt3qk+CcPC&2OwX| z(G{pSkmjih#(zkQoy76W*9(3LwC7!FFnPzQib0=DHSRzQl8MfAb+;TVXe&M$%1N*6 z59$n%$B4I(zuPG;N$)+MaIneT$E?P|fq7G+j&wikWBNaeTw-s!RKaxAY z;&sMjvG#rJx(H{)+c(3Vf0`8#p~@Oj`jwIEx0o_9oo29bc*2noVO6FzevSU1(CE=hf$p7Pas(UZo$$xbmbPa5AD z2rIX1L9WgO*@%p$BrH%x;UzX@J{zCgsL^`2eOE_#m;>w8EI(6cq^4yNfJgsdBy&sv zte7;l@lh+IAKtMXuK{^+1_1lGd&$RIaz6|Aq*r;GlT*HO%YQ8rVQ(Q>XHQ2AnGCaz z+@Mk@)fgZA@ihWUQd8^|8HnD8R9%@*V}9!&pOcGcpM~;VVO)vNbo3q5dGjisKrNgu zWK&z;q96P{y5GCd!F&jQ$6EP_px-1x-`_fb{{O`97!bSe&mqJ}M1|)jt@Lg8I%K9t zkSX&Tu62#z8v8i)0Mj-Qub5LJ-wotp_H@Gd5%Pm7 zALH)!^!~OHzobfejdV6)BF5-GbUkf}UJ^F|(r+ARs}GhG4GM}renlt-0YzVmXTErC zi7m>T*pi>{xOl1;2CUg=z1tF7u*}D;@c@h+<(f%z^=g(&zK0$FnZ!&JZ{A6{5+N{A z>JGLiSSe@4QB5rxF?J!LP1A3Ec!vNkt;d~_=lmtl@haA z*BMJHX1W4`6I&wVvCXia02j*%$77c%anE?{e{DRb{qr>*)7(>JJXW_N((W`aJG1E4 z|D2kIV?GzniQZv*XG+FGAj>nc@OdcqUU_6$8vZ#;o*z=gu)Od^*7TmwY#-{q#GX>)@8n_&f@g59D z_+o<*KEVR8Jb?wIS+`x-!RcsLW?q%7OTITy_h~zkhcZtGm$rlfZld58COHH>9{Aox4^L{dx)>mIZCvZ240wAUn>>o!r*njga9f4n zyuA#!pyxPFBQTBDQpH87_-O4O)&J~dl`&A_u(df>^sm*7D&XnY)h;4+9S19ks?7Mr zMisQd3R16Z=bjSWaI}_Mn@E)<7;25tT0OF0It9e!(9Q{LVnf=1WrLLM1{<(!;DBXA zD5yB)v#3@>g&GbDI8>-Dpi3Tym|~ukqqSj`zlNi=y0ASHb$-nl)@ib!9-~u#u0YeA znDT6Jqcw~VHCjUw<`lAy*6ua@_cHPDYjqn+BpNkZS}lG_X+3SED+&`aS>Z$1 z(U#~WaRVUJMr*w#MZNJcV=th9N4*Pyz;Tayk(s!I!>*(a z7n9x%IC~kL5BN282U&-kykTINGoMq59Jbj?)meClKrS6}14I6j^qzQW3Nw2JpQfFH zfniiPP$^kVz=!N4CihYBypSN#%NBE zDq`km3=H>m1q1`bS7-cRt2oNFn;*2YgnZ*RB$0J7ZsY$R7WfAn+xejn%LTr!d*c80 z#Q$+FG|8T3Py8QT$Ga*1?~`eLaMt+0|IX3}Pmbn{_raO*e^!8t|GS7fW!K~X{OwOT z6U0>sT6Q3FnwBk=u8bJ}_Ya{#TN7)bz6vm?;yxj8T6Q`9ugIx34uoL7M6BbVsZaap zKUM2!!X5@TLD(BxhV6GHjA7t$+y_|92wD%?Z6s!Y)ONR=Tb4mg$)(frF~+f(Us=S}<__ z-?I?*)@aT+VKW?5Z?*#5lC0|JN}IWE+nCU5mm0xZN`k5Am(=<)JY$BFDKM4z7Ifp~Bub3Q+2x8#(2>fGw@DEXbd6E3d8O0c>I|Y=y2T1V6Mw6Py z;oP>qA=gyz1-p|eJ&F&^-KpYya%}O#c1W;hQb?HeC2lT()Z2Y7>8rwF^^-3-19gd`W8;eMelT zGQ)P_3zrKQUL&}KiGF;c71PXG)yWtxEqKq@Ad|T8EgE0QcjB@|xNu|}u%z0BDa3{M z02jWbwTr$ZE$I(yv_&o#SsDFxxp1mJhP)O^YJ04>-qFHh70Bmz+T8#d z+FujecuZokGjHAztDI5RA)I=Fll^4Jm87)JfPF20hm%5Ib>eDH79#0(lkY=Ty>8)y z+vg29MRgl8F#lWv28YO-Li|Bs~4)XkpYq1cy@GSGU(RG zoA<(1j&8MhEq7}&_>;dc@K$6e-S~TDEG}u7zmRS@9JI^HtXF!IExM9)L8N5YtI%@{f;nCXy^*?)j68sZCgF->TeQj-hMjF{SZzzp}CQm8;oI~_0am`wL7$>({ z9oI5^h>k1hyEx!prC)drlF=mxiEg83r?HMkeQk2sTbFh$-t*-GSG zNM__OWJaZu2bI7FridAtB4)I2z>M|{n2}Z5grRkpFPs(W@mPrFVlunStN&zp#Rd;Q zjAo8^mntT$yL_*e(SHqg;q^I`10Y-CNZg_vx=_FHYRi=Uq0l_0Yb9VT9;%Uxsd?&{ zg(dpYY)e!MIoYil)oM^I?G))3i5kmAdVR^RU>UOb;4N2nT>&0{A?fu_VkvHDi&Jb6b-cO6v+M@pAPbMb=Ren?$mTRh&7;{*WE%>ZV7_M_I!}+l)po-0k zaj81LsUqEA8Lg8u155P zNQC_Jr_!0YVqQ%6H~E#yg9Ox@h<~&2Zxa5^!oNxQBOUl7-Pn(XCNcZLoA+AmB`x-w z!b%wa$Mi7#kI7iBx0Mhmo@~tFe^ya_N=rW@T5jbrOv<9(_If7ZtCe-$*H0Hy#Unxg zt|s~FbJkR~pbi0M+#l&}yW(PF3nW@d87vJvW1dXZ?D47DJKDHEtESTyc|~ynH!1Ef zT~)vT>2z)y66n7-*3;j1iVBC26-+!}d9jErMdzQ*JJh({#uj|EGH zi5U!}mfnzq`n*K|5G)^&=wY?Nc}~*rtSsH28U`IvT-+ZMp*s1KHr2s|sn}=OK|lJq zKdZ*Y{arRMu7lxAL}#8hUit4o2$NveP~N-uMRVo_zcKF?Xb!A-o|-~<-;^`Yz+Sah zfO9foIhG&y_l~!Uy3FLpXNddT_bp7soGVQToC1TZe?|dQu+B-E8ND9w!7!9B8ip#F zog!0+jPhA?X0R}= zwVKH%?`^#lvpgJT#5{?0krCn)xPg=2{U){jXW@75ybuQ#p(N|5IN4NDU>|uh?Di_W zivc7m3EJ;C3AGj{Z7eR@7+;*Ux2m0M)iRVse4n5_1ENDuBb0*yCG~D`Qf-Qhlj<@T zC+(wxw*B67CGHnFiRaZ7R0EkP*BRFR?q&SX3wl%#SqByA1g*f+Mj+&SfP8nVu#59-M4qk?+qnU~M9@)i$lR{} zgV!LrTz);<5e{L;K6Jfp2?dD+K>Cg2pcpDC8WI$q55*9m@UZ--Jh7!MG00S?(EP*} zhLZHbU_v*8aNoXdi9v>v1Tc1*Kg-oCmz0K49)L_%%EOZMhJFW4#uY=ir0!sQf|a;p zXt9itUL>^1Z&v1349&%zo;UuI^y;1vdwQ=)P>zS=a!jeR?dN#=wvyS zidIQ_Z+g4yUb>MQOd{QMN?I3~ZI$yu-A+*4svzn2!f4LCn10WgM0)(UD!>mcJ%!#l z-=7~WWIpa7^*30^{LVMQ`*^9Xl_iT@WAd}z)@NDwBDUBP=(Po@-DoF+S8 zDJp97r1$J=9cPaLDb96WA+TlMYy&nBqln_< zaiVd>d624|X4Qs@vu4yWm~T`;n@yadcKsMkc1NM&%o2l{hYu8k=@jSgj=`iA<6}m&ERf!JJ|E|Hk@5+ix2l9y=S&#b8oXyJ{7?Tj>`6A_mhTzq?~FrwDoI z`-~XO(8i9)WtgZK%wg$+Fb2~BnMbySCE*n3SYt2)7!iXxs1{PanplwHWFka})Ju9l z!GWSuoQT0>d-^e$Qk+z=ZPK`&Q=HXKaZ34mm;GAJ<2{Z;g0$2&D#xZcsRMmE?!j{) zMy5FVGhi`2+>7n3WC!y#SZaH=oj|0auy_~h59n~9H&2M%w;K5<~EdpIyu&$)?L zt!3cALk1L5j#3{v5*zcm@{+j7Y<-hP2m;gCN;$9Bs=G6h7-0 z!=`J~pj}p)p7OP~1m{8);#XViZ39ETb8LJV?ru9kp9G7T1RQw}NWd2(0iQ?$-9r*A zL2}6^UPXe%e84}hMqwgIz@*fAWz(~)+8vRgRwUpxLV_^SKPtkCS&ACkG-x*xaQL1t zHvmbX!Mx^Ej0Aj79~*B(Mt2G#l~$W#q-?sH?|$eFhsReQAGZx{ZUF>IbN{^fvn*Wx z{%GbHms>GugXDXxjQ(#j2Ivsvwcs8pYcj6J$un?=A$y>cN5019BisO#q~iQ!9Z+=> z5EzFRAXUYkz*5fiK4djg_usn$N!}C3nfm`a?*8mWwDDMgO~(36HN}c_*1jx~sVv;< z^ml1se(O^7gQs>htlUd z)DS{xHGcE`^$a250oD@XxD>r#d5Z2S@$2{)}x+*FphvAF2QAoPbSfJ1R7rsa=7A>SwB!VYRq?}Y2{i!I2C z^gv;v=3l50G0gT4ANPUu8^;+5eI-SG@iBfMpy<{@+Q7g_^yVjeRv`38Ju{ra_yabs zs37!bh}+u1nVlGN{I-SUP7G%9+icPM7{3=nz>t^14qkyQYv?%naYg?k%h5iKO zXz_>9LeZ_(nHmh9&7}AOBA#TA+?cw9tOKs)Kz`=O8T!+X1Y34A7w-`FrNho1;V((= z508oyyaWym(?CAjt5AmheM3YL4I~3{Sm)8ia%?GR(!1jT*LiS!6%6Dz9~%sa8AG&2mg3i_ zLB{tnL?l0ZOq{`ksf#pgr1m7-2B>(oI5H}*?Ew>YrfAH z_~j3%vHighm7RZD=uA8_N{DHJF~}D)2K6b7LES@RkSb-*iKJU7bm z4l6Rq3ln`elZx4MA}KuvT!7jkswP2C^K+(Cb%ChLYlNy{qCfAYV*b}oB)$8ck)D)m zZL>urzvsRzeemVcobf(5BO>{4KUM)2k$fI9jv*rXNB%ZH4W$2QB9cFAP|%J>MDo4{ zzxUWX2u{ncMkF8RgTv8LJR*QKZbar}k?iF*SnBB5-Cz75c@D6g|y-FgIZ~T$5>aIp4-*#x4JY<`?dAqA5 zW|LeP%^8=644dSSKXg37#SZ2Kl=s!&OsWjb;VZ!kJX=_k--XlR@xOE;>G^xP;bOG& zBWGJcr@5i9+EDN>#WnCjo&5GR!e;Y9J#w$LUW~9)qdDV*&G12$Spjab=v1t#3%q4> zu^gPF^w*Z)Jy&2_e4sk!_0~P}JK7q23v3O(n606YAbz@sw#FiSP_l_v%>gas1O9Oi zh=~P$tg*6Lcpay~rr@`7oqR=5;Z2y1gw%Q_2e8LNdY4FUFR%`xQXz$K`6!dF78ncg z`4)iB7Xx1(0esy<@Yz}=n|KxYOZecxXClC7Qfj@j=~=GhAuaNr!Jj}`fPaX-Vsb$0 z82A?p{Ea3;aBV9;83uDyyxMYdfX}x8e7+d?`Uv3b9)iCDA7FJVt^$8K9~}5h1o%wy z>)^9_zE%B9{-i@S)0KG6R{p|kM2Uxq2m@2rJ{7YH&sd#`E33AkRjf|MJAGbEw?p6D z>QuaQ60%)+i}|Yp<)Df1O#Wk9KmooO1@tK>pnFJxGJH_7iC0lz4Idl@m&t(XctwpfH zVyaoI_MkLeHsC#9Vfn;`Z)o|fEaj6psHT>1@X?7;UUMnhy0&~i|Y*ayWSdijN z({afaF1$u?2@^51uB=u}EuME2VbAXkmpVKVmui7f&vIhz!W6a(??JopC9Pfb9g(V4 zK?N*Gr#GhKk|$hvjo_lhN?yw=Pf=DYrh&EYAi|#C8!nA_A}(bDp^4?h+Jz~^h4%m# zz8Ee+yXZSHn+lrCf=YQ!$7Q;3;WdIwnCSM!aM8TYtaS$w_VWmgmh`vaiBaii;T|eB z7nRR6Zw&}ZKauO%y@aC;Q z&iS19>P};}Gnw6lc^}fb6u?d-?F8XCZ$1lmddlyei3cnNc)vkKL;T(jBzeDhlSty- zjJpN!BLZ4g%wQ2NT4^y-eBHbR&kjN+1Hz@ec`wXy5c1VR@FTwU<LD(uw7m5&hDuSQJ!`k^Pjt0^< zi*Us;bo>$ms2F%(-5jFqx`K{c`+~dP8Az)HJ}^bGv`kUBuYH3q+P=y40pfIzbphoE zrF8-PDa-uvfex>j?LIG>Io<`Rn6xh7k-LmX_C0`+*5XF3L9#e|4tb*-I-7tfp1oY_ z1z^7*rCbYcQ|sw4G;@nQg6P%LG1&5+!dXV;ijfD`i>#D$`wnxTBDd9h0-m+_kcp7l z0^Yov--A>Jz8sBLn=G}TqAS^G2J?5U{nb~;;u=P%J4f6Jj*K>cZC4;j{~Yy^X0_R7 zO5g)i)Obu$AUsqz-^VKGlbwgRmk4JU(ims7gu{nM}b4#>cuP+n0KdP6`px| zjj$au#vb^dZ>ld=;kp9MXs@+YzwqjO?{?6ytrlFrNWc2M7C7>w^vefc+$f0SF3FnT8F`K z{BG8ZV}EUnE*Fl^M37G)_23$u3+!l$wkpaNAnhpg2*9;RJ5C7Yz}# zcYu~_!KqsBVh9>=Ut2JBP0PyHasgdoeXuNVU>cXo6*dG3SeU0XC+pn8E-d21!mirP zg_MVvrIZHG)HE9C08rWcPhifz5 zaTHMoS=QkK%0$qDxpAxE&HJt$vS6=T57^{)yDSwvk9`7~$nfc=z!TpL z7=C4=cNG8xY5U&=%z_TLL}*_AE#skDpYHb;7u`Q;WnnhB%K(%QcLkoCI)rdB9%1R@ z+KG2{BTNDo%#idhzTHh1vuM!lankI2IND3T@l5h8M=rmb6?o3Zp-c6Rap*EUi-b%> zt;~U4@cdv#kmxPCh%VQV%L-tvu*ge~5C0WV3|7u8v%BH>ZixeV0WP!{VI z-Ix{#_Ryb>doS(*pZ4NJPoFKj$)`OyJ}O8^Auf^omUlZo?G&GOW%B74RC|MU0$Nqj z!HV;6;8e(`j};d^HbQeQ27!D!FTrzDubOiq9@|P6;o9dnCzC)?W=MKp`G#vw7LDda z%tVgYo6F|x%hptLk;@+>&%<*z&MMG1)=`{-XEi4iQ7iM~mgLRba1wr`k;K>dz6Y*3 z{qv5~C8B*}*qnXd62OacBKscPC~97GyNLt#J(!~!23=p~_B~)CmXPwN(i3n^h5H@| z`qA%uVAZ&N53W8yV1?@zu=+G(MEug%1!J&e62^4W`(QL@Uho@B%Gmc{lNI1x*$ctZ z9K_+g<0GF^7tBmYd%)xy;?|aZF z67U)!L73=I4;u+qi3F>0wE-xfUY>mqZk?LO+zc>CclW$)Ll)*<9L*VL?u>m8dT&z! zcFg9-ka2{458jD@aP=gIu{B}c;m;`s5{CYdji3mVpp+mXV4jK3<9j3A ztnTY}lWcd)=DIjSJZ3ZN-U#2hRU{KK72e0(0cL&|5DD?zSe(8$LY1nWZPkV$o=}CO z+#6xN3VP;iuJw0*Z-g9?;^o^LAy?&VZ-iz@lxsttOJX&*?4G?5zGC=0?pFjS!(Lp7 zr|pd}tol{0W_IBPL<)@sKg4r)?~O2|@?lnVq<6DT_{Ch?kv=9&)ZPdN-OIfuB$0Yaue;h=FW4J_?dkSL$T^)M72QZ^(^;Lf@D2f7Is_Al{$Kur zV{pGJ_VoTfnR1?WZ-jPy=*xKro&!y4;>@1`OQ(wacdrv?z6R6TSE6tTd1wPh9OH2-Ce7{ptD9AZSp)gV>u=^j zK2|)%EZmdc42!gKK@FolbbFcAA_ZFPO*Ig`j%`y=9o$AyZl(Qzz| z?MK%+Yao8;c7dz`s62Fv)ci}FHE=BMvS$Z?ql5W;qu3wg+NejfH4(MN#|Mc{`ND60&NUfK9MybKbD5M(&T=W8$J}R6$V0y z?jr9XLn#>RYfyvc@@0BmRZNL0Ed$8h7BJYA90;Wi|moD z5O*xwd)yA@3I=akH+)$11wj(bLLe(P$d2ZW_0%XMZP<3O72ta(vTyj%^pNkJSf(d9 zaM%y}f$1FK?b+}lB*8-J05=U27-UR*Ic8~&W@Rq$geGFT`>+N)wG%sVSusmcz>a2V zIL407(gXumZOu$izT19^gXQfVK|l1ocsF41kv4o-Rg#6re-zCebEPsAYUQ1AM5so>kC4IiGnA;gV{c-Q~cHIbHDW3`9+hY^mT|C#E) z$m$=-zj?EWrF?kZ20g}sWVIB8$Pti zENPWlLKCFVnI(j;Zvr>Ti70%BZjy(KTz?RC zlT3-`jCI+WZjv>wfWS?{wG)ArgRs8^=yrlp5Z>X9-S+KglDe z7r*0(CDiLr@(hyB1`d+}&Jb_jDLy!S#iV(}Ao{a};+IAOcj`FS0vfDr7Ql)ae=ILV z0H_Zu?H<7T!DYi}9CjiuGprL-~4hoyL&At)fQF+#``7rwPq zd@&bywk3Z_dQ+|yLOx%#f;GJh`q&Vdlb7h3^RJX`XpvO@sF3b_wW@U^T`UjhV5!(k zO|_)#=n*G7gtJ_G7x|m5QPo9?ke0(?P%7eZD?;lIl;W3t)qiWSS~57PEP>qMp<(Y2 z&j^jRiEU-#@U^-|mgNOPHU3r0KgAA*TEmPZ)$%XFl``24dZV~%Ir5%8swLF#6J52m zs0#^I%dqQ0YF!s%s^x)|u`WcaL4|?+|a36ze zdHy8_PNr(v8@pE|y{oQLJ)=}D#aD!|c6f&vth-mW>?81gYc15jyHv}}GiY*zs$~J* z(Ty*iihHP9?y{zcsg}vVAG2z?1ZOXSH^!n`W?2!Ls^xhY7brWXTGrShOW9RRlT1=) zn9W5nO(pl(Zb=nlEn_|H&z8XcY%%+@h4yDl#QtnADQcJfN!_bmuiFbKIxM1<_9ugF z8qECXQB!q6*BdkZU$2(_i_yFir<}r)D(rAjbOcaz7!)0Zq9X!DS4mNqpup-KgQ5#i zV6#IM(J3gZEovs+_|>el=AI+QZczZN$c`b8d+@sbj7*aTF7s}D!elQ|4V17}8e3%3#!h;l`nE|_!kW0*9dgW*au?$R ziOC`(on;t;;hiofpFrtIlbEn!)~b1&1vY-ff*QvrCdaD9reCIVASN|LIwB@r4)roa-HFNU zOZB~v{Z~UV>8Q&hCI^-jP0g9MQ9KJ#S@hcxMCF3fiptmioGB{rLFqdX73Xq#c{K_h zT~4E9b8&rGgul%QIRQn*;ba;m=PX}T=HQ9ON?#}{+ddOx7HO1oA0M@-JUBQ?jdJ}` z)vNxy*E<+Bj!jhNsm1zD03j-iiF8C%svPQbai^WefjeT;~HloO0IY9H?xSzYhZ;j?AWQ45oP6XI4CHqth_Li ztelF07vv%~NcjUw8Btay*whNf(il=7YRoo{{9jiKu9UGsU}LBGzpxrZ5x(XVorMmT zv1gbRv8bLsQ!5i`YNc2mL+Jl%avj4G*D*N%*F~;lu&I^bacbq@pHZrJd1_^q=eo$z z`@a?o7~lWZp*ODr_c8dt`v2s>$@G6=uAKg_PpY2L`oI1wgcbfTgLU`%zpyF@;QiKG zXt(*ldc_x^|7&`o8>u_K;4ewVobmbk6EjXBfauv!S!B)YXrUW_*eJnl~>QaN&)(d z=#>2`*MH2yod&1rl}|5{?D_qN^vXk<$D~)@`P{DRm9BHczPi<04lvLMdB+NzU7oVP z<=GMS3U)7mu)g&Zs%MmX<**2>9bW6hDr5KR73|Ug@UFKO+HHEJMtl+Kl`h8@WsWaQ zubgq75c2s#dgbocG3%9Sw~bk^bYM`#k;xXgmSa=)$Nefzuly(A^~WnTn_~0zuwm@Mqb@Lq`dr+@vHeSD$FRS}AKOp$F1}fu z8=q9c*nVm_wqNEQi4&2cWB6cZCHG4vQ#(Dga>CEk1Z5vPY-zktt2`vKUuH}+(FLW2 zJY!BU$1SzSEfkbrFNm><1m(#4M=dBDem_bjdTbpXzN4f`ZW&G}tB+KRUtA zi3`dCyvqrOdnhQ6pB2MCA}A|w+6h6K0g3?Q*BN}D;LO1v~)ZL^?eKLmqSA30<>%G1*5R`CI1@n)&!TjU0 z5uL@Y_r>KWm{_?T`{VnTS8S?&0EY_Thfq%LMG?N`HNrgoc#xA9MD@2C4^4DADFBO@ zoUC%pG7ER~s+5z@e>}!1l9QgMQOn6`-J_I~z2>Q2CnsM=jbpRCwyMRJne;(UYKU}1 zPP!cGWrn(wlQr{W*hl1KR{5^W$%Y?|ASYiRNltEgI89C}QN)OHGQm7w*l-tJ*e{LL zf-6zN@_QF-StT=zKY8I>nKB4E@{wt80q40H?L@d9VpJzqa};AGCI;7lC|#jI0R z&nP`#M@3-m@E-kv%J79|_XMjPEbvOLg?5|gYq9tu^n6u2zLdpUMVTwqgP%%Gb%0WKSI5-)%72BuKzH-@|6O>XpwI z2pFeV-U=|NSDvmXIJ>M@5eDD}#3P6}b|@U8%ifOYrkmG=w0BOQ3V zEmGw?+8d!>S%`Pq8@afLdS#n6h0hn7Q8^dBf4Zv1pjS5CAl?{@Ub)ta$kZ!|pQeph zp8B>LCHqYM_?c1pu$uWJA2JSN@Wez8Qz3WB|JCgHYN_#+{9h*uM}Gyn9K};`64EGV zR4#3G9n8+os2qNR>h=9!c7V|s{9p6bVpY}y(EmlGBjfrR=bK1%80xw_`uBaY(N zUn|bt{*20#cbfG1D~N*`mHVzXncC?YmAUt&2}&c1_6@KR9AM)ip6h&({Vm2s6VL$` zn|dq&kC>pWcHD9p?#=;rLw<}^Bq&ebF=|0M_2E$p%B16>g7P)gNTtRuY1gJ6m#D=) zYvM--7?F+$O1DG3!ccdDQgVC@`-q?%deu${$`5Ks5R}Hz3d##VN)wb6ir#^sj0aEg zl_L9)k#WKaN=Z?D&Nat0c1_CnbnUrh45to}_ zCgt4AMI~8Wv6+-@+S(v8lk!;D~(QfEv;ORK>6)VH)G zAGdBCwS4S%|0w07lQwTj>&8|~e>N*AUbRBuL>lADTMSHT`cq>JEmuFD=?seVc zsAo{Bj}$P@({(JsK)2uxf0f|uvZt%i2Pf0h^#cjT(?)_(db+mE4q@%^$^aw#blc#I zN09D@?Y{02cprA)?JiGOulOSLbj`TH4a*&0*bK@WjuJw?rwhJ?9PhGf>*~kg>AG&E zcw;P{u6!#Z)6@0tJET`);f{m12#xH{t_h}E9uPYmYYj7wRLg^cYlF$|2&(18OZKRi zSI;C$0lJLnT{R}va??G#s#-qyE&=0I%kOU1oA))` z$Dmqrd~h;V%g-bfHy*BfMyXo9^v)304(~{Vb@!^4p9?(CT4=XT&ew=9LeP6YwPOm$4Q{_ZPiG4dRb)wU1HrP2{UlMW(#tZr8``>^#cTZx6+_*Siii zj%{?`rxu%ModCUGL^|sIa;VS4JsjOHnH9r6vX9YYi^aV0d6cw$jHm>{D{g6BK)t7kP}^0TF5o#2y^^WXZ%7@`GB!(OjN#9F=|oC zsUM}N{OCWTqH-2$9Gj?YRg1mtP?bYR*y6aTEX2DUVYr8)a@^bWy^noFRDQQ;$D;D- z)Ci*T+0ly1JjH6q_h&f?rSCvg#=~670sC<6VVx0j0*Z>Gq1!}~Tw}BIj$f7M zBg)DIbA+9!<~hQcZ5%nmP7+)<8yf^8m-xP4?_0pOaopsO>G#aBOwc)&oQv2ogmWx& z@UBs*>ln-t_Q*l5V~9kl9C`z#dY9)|igB0@?E#&zGO8n0j-4)GoFlBWSZ`hx?qhI- z{mr%nu@hF}N2;7Ep}6jis%Mmru(H>Ouy%N}3|3!gcF!EkX#(#L)#xIhHps5^s!Uj^(%KhpHvEKg+w;O0|ShDmPuH zCd%#wn_zn7T=BxMtyRX6UO7*2L8Fu|gt?NHbuUwud z+4K7kMX5Y??U?k+QMNJDF6fn>1H-<$)msHHpr5=G1kNtc-EV|%Mrtl|g5_cf#XDcC zdPb>Nj*h_E;dNZ2GIp6MwEq`eX9l?8aGy)hN{P_LZ(8X@HKh4jij ztH!KX-gx?$^-9;rN6;%@Uz4U+J^*zK;+{aQyq*acUSsYW%s(q{Yj*x4%OJ8_uGn*CI-8{5xBjqDJ1eewNj zwb)+`8~VYBbYyHleTj)wyP@vJ_WK+V!~Vru2XBjY$gB_)clHVRI387TmJn2fA)j4}&%-~Tl=#wC)G zAR|?3u}4kv=>HoV{N(~l zNk(3?Dou~vi6TankqPGK`i+`pz{os~{9L~kTxS_vBlx-gaXcHw^|bzweb4;K1f4%A zR)-M!xtd&uu*7u;=I1K^_hibR`7o}oe{%W%#P~unDvw=kUHus5Po6kgjWL$_lUuBa%!R~%S}wg3i&2>e zkbTvX;p&=Ts^xEDhjrF4<4CpqU2qMXJdB`PZasF7YI*fcp%kFYh)&I~a$U$Q+-Yl? zYB}n~SQnxgm9h)Rq*?}wcU84~bttM@-Ul$KTK>71;Ow$$S>%J0sapOmp?JnfFiO?( zmlr}C-717^oEHu%@q=g(~4lu_nwZW~;?+FyW&E?9*{ES%7yrz;F-6JFlwxv>&B;4nSz^3GFV6VjzZnASSuq@7@)N zNyc0Xw8@BbDPJs%i%&3@a_Kunq0F$9H(r=2ChnxN@jm5vmWckW5pkl6NdY*-#AKD@ zm07r>OQo26%-GdJxSY{-`&pwFlh<82N-=rlxu}?2j2g!#CX3W!@BOn%g_zV3>4=zg zIn>JxbtfjLc_WF*z@fV)CYPK!f|z`IBr&=Ff=n?fL@6U^laei~0v`=R^rlr-!cuIS za^h>y#vN^m&cjYUaB5|uqdd_CH|%Hfyv8$Blp-z4lT%WOt`r;@5907W+@W7TlXqs) z%YRmMu*6hBF0v-QYoj^yg5Q|8E0t6J08?^M!kK3zy?^zofd13C^y!nxSf1#vOf<`M z&vi?gkk(w8s4q{nq_8duKqR~r7CG_34@L6IQO}kX!Sn>|mbJ;LcrN1=>A6Y=cvH5m zgzeFstW2~fy`xVO1uGM^<%vP0lqZH#_(OfQm5HkIL|rN|sA`6p%=)&b@Q12~S>IOG zH>~=$s=i^>hji43^jwwPWAt2-OrvKHOH8BZz%yCsd3ZEuoSr@D^!&CJ@W?}j<_K{;_NjmPK>MAO1Ajnwjkh@Y4IyQo<`4XE&k6xW@+&` z(VTI5X0&*d6|kKa-#d`;IcYN9IX?};Y%P9HHVD5G%^8OMvFiF zA9KwtiFR%iv#qUDKSF*)hPkRMh{M#Q%qi41jKjw)n zExtUOGfvNp79afGj#_+VJw7#B&q%iVO;$m?#ebfN;1-84qs2dN1z3y!2pM0=7XRkS zuV9Neof4r6>6xv?PwLLn;@3rU#_5^S;xGMn*IWFcXgwpf_}8q0c#HSgAwQKq4nnsz3v~NtgU+2vl#MI5 zrbD;6D<(G)D!yHyc1Eb!p7i?u?%-?>d>h>b5n7BSJ^y9Z#HHu!(VTHAW=PLlt$_ZI z)3=y(tR6Em5DldIL7MRNF`kRR3@6>-e^gB|9svdUL*HLOX%LHsZ6YclVj}e z4V3KM8>J_uku+PEnfvQ3jCoo#XPl%N0`%CgqD>zapm(8^3;}xauNeaL)QM?uW)q+# zR!zL=Z;$4T!8fIomV z0ZNif|A>R5u+;?E2fPY*A)1%U4{0rxi3Y9>MKT>>h)+}lTd*PO>!nAmPad&edBpnU z5$lyl4C(NQAwBTGwSYw-n`i&UkpL3lA;o$0P+wgoXP@igw^MzCbmOsNdFW8pAnO}a zeS@lRNc9b>KBS{Qq@y22$groXLfpD&PSoorKv+_S)E{OASkr$A z88e!GUD8YXj0rJxedj6BI!0>x$9|Coy8WX$G(A0vT2}FD?DgN z`8QglIpfe}Q1KKiAPW_1P)bHObofw4H*|KiHnw&)Dn9kIEUkS=G-n*n3@UE00*s1# z3$#osUiXiTZm8+FouJ}L*`T{Fnllbv1{GiG5PDgtcpgg0pyJ;%t)aYVZ6i_f7ON)S z+P|3-!7vVI1{Ke?0*s3HBV&d{!y3BCm*|ieuZY$$l0^UWu`F#oCz>-3T?Q4Ktbi<3 zoGwt)Y|3>nWbopnb~@4aCHjnPaITByjKi5h#XKv(sCW%BW}{+`-`|8(oE@!WBr4wX zXcj8|{rw}haRwEyumVKI8@9B=?hW{5Zh4}tvUC;JmX#-JQiV0CL|OS>sYFd1EINHx zv$3=eP$~UXV((r*cw-)f!GzCC~Kcw~Nc5F1D>~_47msbF z^Kh+pR5=BAV!~gN-sVRHPFteK2-{O$Dyop(e5m?plz}|Gnla5S8P2)t`cz`WIRcg&&f>+4rmQd8XoXuGDw9{vL~#YwzeQVJ zVf%aE@C)0D!fdYgxJ2)Yy|>Np9k?Mie}gq&O5i$?^9VE-h1CX9P?_9DK>;(@1}t7{ zEG`3#HeM}kJS{yzH5<}-cLvCmD&;l8yI~^5nMP(^TLOD7lQrw}6Ln%HIjh)d~~Q5wmDZR+qA;vJPQoq{|0j=v z)X4QC#NYKVDZO$*+`k3w;=On@o5b^Zr>4C06jaE1BwcE%N~I+$C4))tii_le)Pf~S zC4N}IoA(Xv6P8yge&$$P>A`SY$(5zE@ojl&0j^^mcSB;WuB12rpTg|LZfL13>X^bDWUD;tPIFkQu@IZd8eilO_Z;uK)#wxzM9yGO<+c!omxtYTBJhM#Z#BH z6wqlw#%h)>tJ7$$K3xV^6W>x^BQh8!LMosZ(S5fi+9@ySbMq6eltHjcgUMh!We`JA zsIk2Gx|OQ7M76D3!D@{Tc4T?p)}ta?pY}or(MVfoQSzWzI23KJTX`^=6Zl6)c^&9O zA7F~VZslYvp#KqYJ{Hdy=%6b2y)!@2HSMOq3z^1}-btk`E6)|hdo+|jf}%iHwods0 z??1`_90t?5=pv`x+_GQinwE(6zfdB2vk5+V9|Q2hZlld!1LvsVEgT%9n?}Jy7)gKw zadib_)Qo}$GYh^*1t0GhJV;?EgglVwlT(F_<((*DQs*zx>kpR{4ZFVm0Po>eM>_m~ z9*fwnn7S>|+5Z~0F$|4qRV@g`0}}6ODrSF@sAx;9t9L!gQtL?)6-jU3hg?C%ISuGk zg-sdOmj&awqmE2#&1~bjdt0)!=Fsd&&UkBPSbr<50Ex(1H*Bdw+X)ERYLt=eI;fU1 zQX7$xdL1VVd#{e{KpClrjMSwHYsuoY_tupssD!bpEz_-l{#j6lB}KX5B>+1az!tpN4R`~?5$z6*1@p0G+D!w(w8jMJ zd^HEU1XyH8aCulKIFB|}f?P@gY8Rh(Wb*lH@%fp)z<1D8oZkwwZf#;?*_8bUE>Y2t zsBTwuucQpZ+Utsj#|t9VlUek2D*D9-9Cdmq{-2<;2}LKpQ&;|*-g^R9T{e9N^ms(1 zY79+EPILboBsn!X)7H0?CH_=g^rxJa?-NuKY|wU%-wg-iJ?M)o4azx*jbYXmM>X|Q z>>_G>>ZPW}n@#wf8o$wRRpZKPr+!hHbg!?UhmBG0cy}733}@+9XK%{FD4&hyj5Eq` zI-?9UTLGWg>eST?S{Bm3h7foL^`b#&910QWFGJN0$Mj-aOrOF&wD0&JV_yaa3(B#P zM`}HjgOX!|uP>^Jr(6Hv6ue9$^$a#D1OTg0fUiUKA^_||_j9D9C@v`~&bcPHO`=GN z9@syXC@v`1dulxkGnL6sL*_`i21hAf(={w(5L2bRMtYAhv0Nh(SB&gd)`+oVeqzmv z*QE-}tmi?mzt^@z*}!w|OK`2DG?sb(W06R35-y+A^*54x$^QBD+>IjrCHT> zUwDl)vl1(LEuUZIw{dka)ZUPvsGhdw>uPVdrbbt4R@lA`DQGX;p+sue7EE2!vhuYY za1=K9olX6~G?)W41>A799vY1bEm7}!Mrc3ujCGkk<5wg$PdRC(fmefJADadAs98IG zFKEHC>FE46^q&n}@s?W8R^dqJUSf~I&L2P%nz46~CMBDeAr-Tw&#Oa_Ep6i(t;nWB zW;YnIa%}kB-wCJ?%EB4$P%uy&fF2sirw7yz)JZ3XkLFkv}bsURWAEG7Njv zY0MDtT`9R%U~jrU6q78jN~ji(#lmp((HZ2F2`$J$ht3v<4wAg>qBG=+L0_tHXc83j zaB4jvFdq?yva?e2ktCA_vrAL@T+RbcohyEiC_GP3=ChQ-zdIQlA>|cmxj>E2E(qNzLU_X0r!Y*h-g9F`W z<=Zh*s4SIYGf&WZa$-u)WKIKixzATZQD3O}vW#R`3D;C_GFA|1l}G zUfIlAB>$;Pao!sfgw^=Wft4sW8;zZ4aoCBjkypPASJ#OayG|5#7ITl#kJd@->hE=G zp$RR-IRV2OgFjTV&c`>g&eXy>RxPW<>F4T_qH3uH4q!C^t%h2tN)@hyf>n3Ws&Xq* zwv!JXy)yt4v~y*tRap!5%wlO7_|q72&_MUsIgF_FspXJ_>5i;g&d_2rt9E(#6C*T!op|`=<`(|)Lpc$;(QY&}h`<11h5Nh-Z)kxkT zN|nh;FlMwcpwXz+NVMo*_3>&hDQXtAxMzc?)eLIEEe3#yg<0MN?!t~CrPK4t%(%FTHv_muq zz#z0O(M^lk}p6DSL z_5@tmV|3-2?6wxf@k?JxQJ?7AOCV^R^ntFusX`8^Mb|!-YyMVKFf>c7vfX5s+%0;3 z;s=I~<91je(tFzLJupg)`-XfgHtd9)fDJJp*g4Set$Y(b@LiRO z8oB@BxatLiK#tHGx#el_iek*t$7DWu&Svc+@SfKG^hv}$t^MiK+8?9?bfjag(Nq+k z#1bIPS$s*(m`Y5UCbno%(4gkFB6GVHktIe!*xxX@dx-T7tG*%CH>~=GR3Fk&AJTJG zxEx9FP>6oeWTkYN%ej;)Y^B+|vIS$C$@OYwsLpLGyS$Av#27xoTipl*3$CP#DoyM8 z3xy80ufys3Y_{z;@6N(Te|%$v0fEx?*yutlVBp}O@BN`lV> zEc?_#z++9~F$^dhFv?8lF)9I@AB^x=n5a=JvNpH5Dd9v*exjK?28L}k9%})Qy%rdA z3`c(I0CeU!B#*7DOccu-+acEK0+;GR?FZU)vCX^H=3Q#@Znb%r+8pUrNt<3$$i^eT;FS|X; z+*9*L!`y48MU0D)*6AH!6$HJrd^8nzld1ufVuOmfJo2%dog#DNzDXd?iQRT z^y;*^*RC43%>DSSQRcpU-_bDlU-pTx=tySC3acQ_-1kIt?tr=9YXwA@dqB+nq%nPz zxyP|b?wP&G+^>*FuDQtgZJc=IF0T%GtjjwPl+Y4dbAj%_BUe6UCwMH+Dv0yg>Cv1! z;IUual5QOgiN~(KP3ch{YahQJx$ALo(W|oqP0b&-9cb11khxpEqxTw32UtM=$jOp8CQZqrA`{932ewFszr=LD< znfr;GqRf5O*3mHc-~UHnZ=boZu?phM-4xBa1LmG%1w@!TSIpgOOg}-G+xyq6mASus z{X#P4RgQ2zTQ4_Z?FpD%>CqWL@ai|+~->X5$2vQ=AOJxWlRv}J^&cM zI&JQA7LQxzp1C&4+|Bnx|wdxrM&bHC0foMF!yy=Kh$8WystmTc$hxK<}VdClyS=lK6c#C!Wt4xXS+x>wWAutao+4o#+3C zd=AWM-+K^CS=tiAaKK>I*KmGf>lG|$(!i1Y1~3n=%|)z=;$Vi?PT6bD13|c~Rk-)I z#PGnwYZK3FaaGBdIj-IixLj4T1q+U}6bF^-p}^7yvBYOGBEM~Shm{BOSCWd$new!p zX)2a8^}hu8(0YiM?y&QtxHzbADpv%Zj1mz;Je(@TDj`p=!>6aVCv1q(dWp)13FH|(p%AkFo%Ru|8#+?jqBkF5^1Uxeh96$fM{FRhjp?< z6EQW6TEN%6SYC7nR?a`N#xVww*1|#N#0Oijf>XN*^r!?Z9rR1cvk$m=AxpT?N^tbe z+no5HoM}Gp=a2C4`x-Vo%AMPSSmpMJw6OsmweAi2@6$uS{oYE(^J z-i(@*&N`5aYlY&pNIUEVQ&{1C=VI+hZ25fE^Z~0W00vP6Uq>A3Pl}6vlEaWNS7S7J z#qmuAh$$`CLN^OzT;*a+XW-7QB35AmU(!3YRIRnS^fJ8W^#5KVG8+hd1t2-TsYa!6 z*?pUqI`+6y%3LY@CFwn7E#{X}%@8oRqOZdu*APG1L0nq~_HzOMTDgh^g8Hx%tNZlf z3Vhhf58L@+r&x%K+MqxbklQ-#ruX`#_j1`OShV@wSh?;|6u5rRR{6YO>Lv6yc)zy#v z!chP4NcCUj7l$Z)+peYFuYa(lXfU(>V_b&9E{VXT&dCf0!?MUO<9-Y2-_Nzdz#ENR z7Qg&6ta7#=CaqOVzfz*|Dbe~WV~>|rR4!3Xxqj#4MmTrlO z%J2=_7nQ{-B@~qnu9UgBQ{YTgeh@EZe2dCeBI=Jm?|Sq;e{YKsMa43F!Ot*OQL*Aa z;1{=JQLzmBxC|3YREkCG(~Lb{R#CY@HT|*Jwd$xurA16m-CJ^;Llx6|3ns)%3%ntfKNzanVCr3@|0HIHswXOr9ui zORQ;f?7hs`J5ikU?*4x<3HiG0u3Fk%RkFK!nK@#;9kSdcq}_^e*4xGLQWnZG0^wy9 zXvYAUQ(b{M)fF|T6pzr25Q@O=!u~1^tPOL|7Kn}{y$rq=!g(a&YGn>2lIVW`~t$8nst!>i_? zsXB<;ss`_2v=tct)#5!Ek82QsnjTZ5NVn~6ayMHbXb%R4P6?+)cs-m1W;2DFCjPz`0nabxt<0?*sek0LhqmY*Lfna;NK7th9>{rn=09yYF0eiy;LK)Piit`@<~cXSFi7H)Z3pHfaZ zN=C>lS(zAKIzSZI3yy8SW@o=#tmJ2;9e zY&B-tYv5@ATlNAD_FfE}Ogh+$6rv*`V@)2I0;-JUqF66*-|y2JyDm#F@S!WRG+U*zzolaY;01oG~(bfj?cQ0-S$x zMokWmZ^Y(Imu%jfPm{dK-}(18C7MfSZ?6kIRa;_^I=d|~#2aj!{KOzscVcLBF^`7B z)?P#0f?0m)w!~KZXls6Am>+H3T+Dp}@zK_S{zo2Kw@!zL&hWl*@#LJ_r{b5U;mc`k z4kPE3D-N7`pRymwU!W8#6T`_f&+vZtX@Tu6W2RhYnvPFlCjq9J%mnK(Cv_lyQKms= zsX>H<}%8Q52zu^C~_x|y5 z9@V|@%9ay3QIL{2!2}l!nBtHhnBulJGQCRh7E|nY6XMow9b&))H#O7^Qewb@4bnrj zT5n&yw_0kz0nsW&1wqte7rmh6DnVF+>Md%c7A44uLIio16+|t92rAJ1e!pkt*+)N| zq~%`T_m8WOKC?4tX3jHn&Y77rXMWuxilYSU-0)2`-t{(6OOT_KC>?fjxY2>+C{ufm zcK%XD=?%=o0e|moX7ryXD_~DvmD_-^4dee3Xk`V8_r_GX3jD)n)2Lwh3|0YVOP_2@ zma^_9yz)W-zYMLI=5LIFcINk482n!W@|%+L&4)~i&uQ>SwPD?_GK2qR2n;2#7Y{-; z2fdSAEY%4phQjh+&tVd`Ki7Qh0sK_eeBACZ)y2|@Fz?y}R}<#7njqaMRUMH>3RKdS zN~#xH2noM*VW6Ca3KhwW)P7;0_pobsq)fCh06t7dAChVgZ3HU>i%~6EA$XgiaxHMz zP;wHLM%$X=4>*YlNsf99*bs6qF`Z4|FmwmXWS0_5vws0#;6=Rq>zDh&cd;RiwA`&Ar=HVX7C|JeZ3rI*C6)I>zkuP z$+1KOA9luE$~_^q%hKvV{48k&BI52`Q*LkjV@JgiDpv=x;uq^AmL(?aOy#P?g3^^9 z##ID>WP;;xa{<$2f_C_`=7M>Qfv8xRln@|Q*<2vm5;ZM7=xlO9J(C6HOK%)`^9Es3 zb}&j{lvM=r$rDkQ*RnJh=!&wu?Z#7?%Znod24M=>_CUj>ef2gn-S&o5_yyN=6i+c`2DC1_OD7l*61tgSF!FQWcfX+| zPaat9ZdFp=_=QZ1KJ`20R;s(dvgX=#4gu?iJ8^!+K{-}gz1Y(AZGS@!>yNvF>fbK0 zDqR+@PU$uS{#BY!+XZ;H2VC2t;*YTSY6aIrMhQaKP;M7~q`eYfQ!Kegk12XbjKroV^Y+l*zwl+4A9RT9)SGtpEMQj&NM8}z2cM-8?3?>lt6_`{M zAz~%up`yl#tNP=mx2*E+cXbRTg7tsC3G^GDGpH_xVp9K;osw zo^~}`y0HsX%D_x8tuO3QNoL><>GmjV)UycJ1%$FuGn7?&%+)t8C|&8{Y|b!T}0>|J|f%~0Qc+}dV zUGmQ!gc-^Lw^2ywW^_kjHlW`LoW5WJXE$Rh@5%y)PhI3bg?n^#i>2LV$x)MrJ=P69 z$geu6dJxr4!a@9AI9PuO$Isp(;V6FNeA@C{pLjY+l*z@-X%q8&sG>a6R+3 zF`2!FLs8m+pf7X1q6iW57+lIckl>51eb}=QU>-A+3%XNC=(;OJb!nPop1xqr+og2M zyE60esg(N^nYUZ%W~mM#=&5m7QG|&3 z3@&9p)aEa}Rn^VvDmAuTW+*fNh>*~A*Hg-L?wGGH81oyHPI*^mK0fuv=u@c3(xIY5 zLj~Q~P*DcjI#D(-N*u%2@RR^a2lHv2uD9Yf;%U1|QzJw&U3xs5JF0StN)jTL(+d&l z2_c$)lTqMa(zWiJt?eys>Dc-M_UaZ)l%ZX-3tp`KtZ%_QrBAe& zdc568lL`6(&E@%ds8(>jdi;B?kOF%3c(u>f7p12vwsi62l5AcH_?!^*;bdp&JFf5G zn_`U83t-2=eVl`Zb6mA)MFk_(_w`bJXOy-pi?@)BEPK1qBq)~9c#~Zc{bZMN$L{WY z#wRI)dEyO@0Ff_Pui4?TSda_st9@MDf)bnTTPnrBmkQ?&7!R>Nf%4VD0-+X?XFEsLVNKkOhN~|OtB7- zsqXzMPfRZb(l;8?(tWvLQiL4#h>yQ1Ib?uHn-C*19s$w^q7>n2-~3s`f#O`*Ny_D&1x%<8~C<+e9n~QM{^d`$UTE^0NsR< zo7*hWG8Rs=4j}jTKU_*~jNnt&WJ>qRgfT0Ffs6?+^UR&~CJb626jfc0G82aK&UvYP zdW%9g$UT(oBGsFlx-M+Eh)rVWnjD&3SLu5gnDB;*yA|KBZtguXq#pkQky5n{CmepBmExcQy5M z^zx>*MLFN@bM|8sC$95vOMbC+=VdwG4cxG%SczU(Pq5r*#T(GWPAXnyShTi-MzyGT z!_7^@@#2BQtNcfXt(B74+~N$Yl3p$ug|Wys3b0ogW!E;Q)-sB&&9B+b!bplz@bdmy zXIiAiT1(nmq?dWh$+tZ)hu3vv!)Du>2X(Pa87Su1wz!x_8(S^yU2gS!l5&f0$Jz;6 z7uE>TTBcmL#KysP0uVP1uhcCaO@$YG((o&IC@GiB;YMQ(-R@%=o);R|VXZOc9v%ZJ zQsG*A<5&cl7I9{1xkIU@NtPLrWg290_Qri_ypYpyyNEe1!yUSaad){SGUyuKN#&YA zuD*?^FBW8nk|Ueo^98``%E+4vv(w-=9|Hr1DPdzr!LLv8>t?XTZK;)|Bl;pr2tiCwIFK*Qr`|xbfj`$bdv*XY6U!0aT5ZIos?ZU9_46C>{xPlFL3bOP# z8tzo-d$8g|%JBqV*p{q@5I^pVh{`-|5p&7MvDXB~&)x9?j)ElPm@$D9W0Tgb#Ua``CDBK3#9--8R4>$Qc^eIvAuZ?=X4fkY|JznR59~YV9 zBYf%<!wPZ4s+5@o}y*6Pw0O*#sEkx#H1>j3G7wFs2 zaJhRUsb$U8j9Ji3t@N0^c!ZK6AwQCM_obk5F1H!}+pY;mVb=hun+u$f$MAdGs+?kQ{^5<{=#ahiaeWP!Oo$SHeN^a$7C*!cyY+>PD z=UawE+da(Jde1unOc&_Fw5!+U&h_zX|M6~Q%;bCEy6L#Sles_h;8PDZKbUyxo0(iM zliYI(?wR0Ya4WJ3Y`=%Oj=jXJ(A#B@fB$o`c_!a3!~7j6A2TG{a{Ot{v1DxlT`i?H zCd z=)VQb$lfE{!9D%R+gzZVc=vfvDQG79)wTsr8j3wlMn&X-y9y2b0x)>3?s9J%IrLpX zQ{kVP7+9XxfJbT~akFz5sc=6Y)BxK}C;f0#+o=8(|Bw}PpL(p~!OX)~>T-mSnQzqG_v4D6fe!zg`S%Py!(6Y@r}ddvmeVi6`3i?qX{{G2euKSg)buxo z{{mA6*bwz8n4F|Lv_FAQg}6Jx(>5~Pam-!@*@e64o10pza5Ttw=-j7~3O{s%>(E=d zTWxPkw4R-9--O*1+4M%ZtOBVWqttT@uRU_dqk8yY<#w~!R4wSY)Z$EHct6ngAK>*s z^-1%WfH_Wv#X2G(~``{Hfvw6!x6b?azu>WJ5E z4I;7rm2!2%erdiFiV8#BJD%Os9@Vm9cnvFvxp4H2RM=pjh_H7yH+9CbpC|15J@!tU z|FNsa%a444+V9O+5&Pv!uyYO<$9}%B|IA1LEd<&DUj0NSVDHNA>0SZ*j*Sg(ib~tp z+|(DxS0#L(_4xWQ<-=Q_hOalf2XC>uog^!kmJd&{&2!xD&$&lH24sDa9zs2X8vLM? zr2!~uIjuTjLI9=0saEz}6<^%uWB{%ySX0U~RaUU3o13O(;*e&}Y1niw(h*RQu#nJ zo6c(9y(auqpL`yvG8Jx{#5Qyy(s{<`(c@C*nSjTcIqquess}9^Q2eelEo*k8MlyCh zF%;~AA5n=uRD9tJ3ky%ez*i4gCchIdo=iqu8V|6dQ|g2_aW>!w9{T>n#YZQ9G?;8y zReFh98uLJn$>Mz}kjbT*JbMq}rS(`PWwG)sQyl+Uee0p`KlD}NOHU=!^YuVkZQo54 z`5K{16PCZY6VWU#Hn%^;gSsh>1XOG`)x&&!q4C?YJ@VCud`7<=ta10ko)e`nyHC(O z)p%kNg0C5Y9fE&5yJibIH7ntd2G>Mru>`{`cl`ByRX+4j)b32{+h@5!Z&RY;0!)RD{;# z=h97|t7zPcy!Fjt%`&3>>u$-QqqVpJ?xL=i6WzLf6`P@x-KC(+^0$R2Y*^KEQkRz_ zt_k075l`KG!sO=^!l;U94dZWJvaja&Cs8{X$of8${pKNB#j49zvD_F1I2eIT)e$>R z;DhOnfJ}ZAZgYWdqG6rIHP2iS47~gN=77)(vN`@__VnxJCbgZl;jjLdYiel490lwZ zT{}F3`S-_LlV5I2ez`UIK)UIHMB@eSg=!aWuyKn7UTEwL|C&)L$-RDfF&p!)6OI@yA3@HAJ*SE#d_m+afAF>~;THQIrS5Xa z`e9JdOm!6L@0N)V{#)vySO z`C#d58Zt(5!5qoT8R*m5>_R1?O~?-!>}Yf&gOGA2<3_u*g){%FWx1cnTf zC>6fuAva`zP}81nGf!*I+m_jb2f1vc=$^4`MfQeD%*!)-Cm#C#+2pwOfNRh}UU+uR zHdOxX&6B0IXV=u57bzx^lMgk0|JH2s`=_dJ#aADC$MiREo_pvW--qc&69)`H7x*cI z+Qj+ci(VHSe!dBgB*)Gse0RqV{uN*o1~1yZ9FFn&wxY zrpVY%9JwC%MN4tlwCqBujMtc3yDDr%_T~azSN#ja-}a~pU0i+W0>Li>nl8|-s0qG^ zdPlfuvAU~3cS(`IE^=)5c$p%;t;ZMH$ni4fFVKyXV=KaUX(P>wxX)hinJU~{;M&WR z9=DN$Sla@+@p>d0%4FY$xaI;~M~~|8H#}}ajUJ^Jt3Rp^-}$ThF7{sIz6!RYiW002 zYEHRe9m0M$4J~DUFeB-+dA4Zo(q#+>HF-3y$;a7{dHm=mE5Lu@Vcv}@#twW2g~l%3 zzq9&)1Bl4wSxRiAf{W&&V~3-!al|B$mIF4{V?NiWC_U#;vh87qHLybzAPe-F#g7~M zEHPoWOP4-u=wo+K4{t7D0(+n_s~tz|RTzU=q=iWa0aBGi+8Dym3~9R-ec0qH4Eu$x zTK)s@n^}t36!Lu(lZmo|#`>t5man1j&ACkqhlGKyqq? zv^D&)I`WX3-2=YAQw|V>dCGcDT9)+|xHdI5i;>NaTU_FmC&-5Wt%g1qXukn=mB6^- zwv8OmMg&V9H;v6Uog6QJp0*lI@@0?VB)?4(uTWck}&Tu$I4^Igs=(CMrK0G&LCRlq9!PLJ{guwi|p z8(S54qBhUM8W*vn;XrmzkK>+FwfGGUHE!*;*a-A)Z#cHDsH3?an^@SS7Ii&~FOce${e@dyoH9+*kyvv|Uju9U zz?xH7=f{*otf46&Bg=@?`+nFr#F_#B^+DK!#G1jSteKE({<7<7U@!t}2Fl+a)=fzx za2;#7wnc*tKm+GsjiG#ShlmOTjO2!vA1{w%R)4MPjhQ^!P61vl;3_?VE0a{|abM{P zR2s|hKs2sOhr){$-$|+%{yS5cF0c-<<^PaoDy?d{I-GNxOu5Ng9cru&P#sOL;e*CA zV5EeLM2B!)o82=*dP}mR*L7zQ3CVg63_8$p(glq~jemm2Wxb)-zVMkkB`AH$NV3|! zF+AJcH0#E_i^AWuG|=C@j%6)yPRyp3%?d9$cT>FmM+*ziszhrcluAe=X*r~a)y-EO z!D^jPL&8o8E+hT0NeI5;20|#BIQmo`7j`jLowyx^eHv6ttY_8Jc8s=#3jMCkC<%x)r94Ywpnit+drl*5kzxNdJd zY-rvf$$rK?IFAL*Rj&R_%@`>i^w>bA#6B)+5E`1A3x|6f=0sESYPKR6M0T-Y{uY~jz2U_%1t92_0IRXW~21%2Q-A*HEt}6^|5t= zmQN9I>@=l=J{}F)%ED<2RnAP;rW=?GT2eV6O{E)<5(3bMy-7JWaOUMMAtzxXCp|_^ zB_k4fqW&e_+>{m}IU0+QxGNwHDr$5#aKSsfYC|1tt1A+R+g5e3$Cq}n z|E>=9E5B|siG*kmtr1(b>s61^w!6;hxa(j$m~7<%-%#G}P}**F+eVJXBK1QZ90#3E z+-SxD$5B3c!mQ%l)uu6AkGo=^t=85Th-`KS97@+I8fdqGYt45X0$=~GoSiqK%F#`JbV1tSgOtFFw%a5X^puL(m)+Y( zlYFez;;ncl<$XgH_#p;tbd6q_AJG0fY+KW|5vo!H7`pm}r(fbUAj~~RfKMBpZJ$Ff z&#&5vEZ-u(`bt;*VMe*?H~L(IQF>NCIXILYR$ELC*ChwBP1_ENC5LS{@-TNJtNkT= zb2{TiO#=U@0~HhaShZeM5c4KVJ=SG7*e@o)hzKxZ1kkn?tlmTf7;A1C)7U+#h6MtQ zfdHezGb#dXRC}uT?P(liI`eZ)#y&ckO-`siO)hOu|DpEOxYf0%|N36P@?dW$U+hro zw2V!QSS+=tQ0=J)q;>@idgV7tLOWoTZBRo!)Sh@y7aYN6C$*=V@cq_QuzF@OY)@{Z z?R3$IXFIy0nxB1JcQ!)K z>Uks@DRJEJDGXX%tV8-K<)tP^%u|%q*gnQL3IDWSy`KSr9qo{4hAGWF&3%l(zsvCV zrou^RNWzcwIK$lgOq&ANr<>PBl=7EjR z#{S7g=T!JNu6-xxVgH2jvo-l-3CkGRfcRwjQs6_Vq6RentOdgc$RgLrVCC3CZdC@t zgI#6VMvR6#OoCwv*740Yu(P!~zO^QY(oI9Ub<7x6ZCgPM+)%CWu1yqIq1}nhqm%_U zRNN81=Ed@Mrw}0_!Os)`nb$$}Zd7zl@4I=MYV-=6PvWK$a2rP+Mm=*!$ZhoZV-Y~>Ov7*;w+F@T;pN<> zF|)xPZo7f z5FE(gtL}4^?KR!UcZg~k+Y z?>tr90U_gRERTj0G}|u7;+o~LPSZ9{la2@#Cp+3ytm#wf;WNS80YSA@HmG(o zKQ?R2pfe5BhF4u>?L=`lO?8IpM(en%DvEE$g1zUs!|ABR8BueAu0wcn_^{F4W=rne zrRyWom>;3l+XRUl%dDHY7@EK9CR%UC;Ock(Ek+g5s0)<-wLEpi?Me89IH7(UhRSW^Kq*!-Y#RUgu zv)-hW^AL`b-JTZcTX`cGI@n})L<`I=PWh_$k`^%Q^+fmQ^n~xcnP|zA?Yq zePd8lntq$5Q*cXf@!uFVZ87@BxcXF#7UQlS-1W6RIkx;8ck3G`{5Qtj>_e6Sd;`m6 zZ1eR{9AqApW_?NcQlEapNvw=8yP##_%!L!}OT&eixsp#>L-Bl>!YLG&XkGZQPc-F> zCI#Aa5)Ic<_%Vn``WrSPWGuYUHdPkqp+_v_XgetW8&wL+RufFIy-RaL*=cF=eF~d< zMm9O$XYC*cK{S^5E(wFmqKU+1;jj5J`knz?3n5wev#;Qwmf4_p_oF~^}e$FSpv7T%bJ`brstrZ)48!y8ngiBx#`;^7TB&+(nM9TKqfJHTHHx&H5oYW9EW0x?zA+}(v>&EE@ewle5JSr#UN3d>B&DVJy) z6ePNg?j(Zkj1YXHMKKJSh+UC2P(IDXW**liN8FG{ST@fr@fe6UA$BK{{MPX78)$oq zS>F8m)%>3KQWG5|vV+2~G4ey`H;&+!UCKr+YyUAq=>pwEP4KwMdM0RPT60;|b_K1f zC*>CeRqc#IQB?)XGnuc@3HVu6Wz91_9+TCLNEy3FNq$#VeS=l)K#t{AEvTy3nt-?~ znsfz`D>$lp92qf^bar7E_cl&)TLad#O>S#&8~o`4UDW*%U-vGA?YM=cr$<4nd!PJ* zpzi%qD5|?ac_#BUJOw}NuB>^+$7AfEL`Jp<^Siq18?1XTaxAa=msIy(aXo|*`74%G zeAK-g8Oi3gsx~XxrV6Xs)wFzRt(sCMc3Y9ED+`s~vZDpF=xQOmUq?rIqUw$VYc@Xy z*H>y3epZ*TY@YG)7&G#@V?Z+ax#~K**mhao7y8KWNTP3$BvpuCPLh8RNnX9tk%Wo-Qj&@f zk|Y50Bsu^4Mv~jr2Fle=G*la1Ru%sqi#+LqMh_)=KC-6^bmO$yfUvu)hvGtmyr&Jv z<*Y$Ko2^kO5*LB;Oy((YHTX1EMpc|(RwH|i|4r#MfL6e)5 z{DOcsH$|a{HUjBZ7*B!SNJQEws~tRZ62%y=f$fU?jyC!RX~UT1w0TgpS@i-(8zyr0 zVOw>9+|&c+Y4deEY`mjUv?*6RlAG1V_hC*JmzzIC_H==6oHqLrcKc^Yn}Z4(ZH~w< z2x!v~g(BJrq^YH+&0!=WZIm_7_;`%1BKny#(>mJd8>G!4z?ReIUqqYlY;d$;B0u+4 z@j)A^x}G+lv-8M14vRMBYC~>5hAEZF&FbQtGznw7ik}t(ZT{BxH^+d~G*#KHDbUv)q&&3uCmGFoMmBOOGgC2+*EVN<5pwNVKF;tU0&C3s;)nIzSR}C zw_r|S(_u`s(!PqLMQa*wQx)Hfa@v8qM8kX8Q*!m~CiaV3eY2CvoT#0orMgpA^^>qv z)Ang?wGVC?@Kq`2U_0iXoJV^ zf02dyJF3yQp66<`$U^OE^u;G)LZRZKMm?SZn4s;JNX$Ibe94IfQ{y6*?>LdL37Vle z$HZxoNF+*I{UiocT1r_1PTd~FuaO3`S^|r|j2YlUPTuFk>nC}_RrT}P4{!T-SN8C~ zYWyD2%#SxdOuCuhfSdW@4vc#)7c*Rm*W1d>tlyx{i-~7x{fHgOx;%X3xsHMJZo*h) z6UHH&aXnLsQl}P&V7J%JIjc)qta>z{{UkCl6gb|Y2 zTZ5m0=IH`mSeV|fMr(n)r_mn*r`Hg+5)p?48$F5FZ`2V4-`cHjF%%660_Arxu^SXQ z?r}&UEUP2I@fh3S<3~ECbwh%_!6AX8-tum;28B(94;lyDrct{w&lDUC3EPlSM!E%6 zneH_WZ%Y^CxpT95HrBNKK;tB#S2euaplfSd&H`GjQy0LfEj1swHVSONW2>d>tZ6yT zbeAH^_)}5r0>GGr@8j?}$zD6UB#pp0f#P5WvcLqzEk z8p?2B+1n|El`;NKIr?2yg_Ko23fS_hV(NmbX4ko@GLh{#a>Ybdsmrjc;TFtP@5b3d zF_MPhR;dN;j(;3$+u8kh;@1j~0j)D;cRs-Z4VLLnS8|%JG15YfIN{WScBus&%gc#* zG|Kt-rLOmY`T97&j{)ttXTu%;VQj$a1A7m?b1IML$c1R^u74@+GVaKP+of9c_*(R3 zVGTwt`tcjpf*VVGp--_EuqpRP04><{!gaOiQ7w9x*8+BQ)Z&+XEns+ta?!5qhJD#!-sQDuTooRU$~GQb0~}@9uu3@Y%QlKZT1(WUu5809+sN{=U9Ga+ zb%~?!hz!;=V`Kf%3Hmy-AiCLAo>VR$&J(Tu>57YOzICO5Mc&?HfC>YoeHABiI>({C z3K-I%KuqzAlho6uq^C`KJ&hf(rA~!y|LO)d!rU+wk(zYp8S|)ePEtV|NOF*2fk;ZRS+IW#`ssw_U zD#r*Gh_Fx?pRFT`#%i7y1coZZz+IP*Vp&Ctim1w5PBG`S1g8rca~tql!7?Ip&lQ0Q zH~#NJ(2e5pMNcd*fH6=&L^g7U?3odJrj0$Z6?@o|zvFkLn9_p$=hC+JPN04ntk_R3 zUa?P+(8-aZKVfA75IS!LImlR@e38|H- z{8{r+7J@@ai8WQa7$T`mx{%X#PF!S$@>>vdUd`Qm5rmMd<*b#(|G1ET@)MRz(zl`*0%WW@hjreFds4-3 zrwbN#Mj`8XV5t-67hs+Lkcivvx&xW;?Ja>N)_K?YKX+DrZt9zrn{o#?Ri3?P3yN-a zUsasOxpQClE>%e`1*=CvtGi6>20`8X6~p+b?gIS+tn(*T_l^r)U)qZ@oWnZr)Sg>o z%pFj<<+6gq3R(rn7q|+JsDgv#f}`ayGzr-(zaSvZ)ln#t z5P|Yc=1H>&ev(F6b#r_?#*|8LLuXn?8hwML(M;ga?d7EMX5`O`H2L!#X{5+X5q0Y% zAj5hf)41}KB!n(T2fk*UE-j>zu_qHmBOj9D%#y&_1tyWmkkC|bBA4AP?wvY038j+svyk^*Y72@&SeNMCQ3 z6o1*DHk>>+JhjFZX15B%gv9`wG_L!D7si_hwFbhmx3YLR9`OZ4c;cs!8Fv^Vkzd^) z#M>SA!H+3}X7f->&Gx`uYd0~GGZ0gD4F#^N{hAttJAow2fX9A-xSsiVO^(B6xB*2h zUJ@(kLFJaqR&&^bD)v$N1%Z$pi$al*2&B_AUPu~{h(e;QdB(?M%)H>I`AqACMBkv0 z906>(kUStExuw$ag^9eGMg<1}4*{lDb3TfmF3{axbN7|tjs>>7>(|V4Rl{@4b4|m= z#kGjHu4GN|FQJf|2J958HO2pnI=YQNuzTPi6vEu!`deBLc+`isgjOR7tPa@i7Og$B zb54xaiD*AuyRJ=z{XoZou(1br3@k<*UtZ&{s>bhFZ8hc+Mhm}>2~3M`3W<^=0__@g zwMv{!5w2JW94^0iO#JySgQQ}khjY^C?X}yj~$sU%tH@0i7C(B*euod(er;wi| z?p|KvQI+_Mt6Yh@WsNz>5_hu1X2bci<{mpJUEC?hox9uu?20!+vjd7Zir=VsJXqq3 zH_YPU#7eXkc^Kx1XScuYpH;jKzIcN)v*by+vK`^eED*}u??n{3D^%C z0Yl!(@P+wRG7?x4XJxq6=c{EtA4My}G~@*s2nPmQ8Q$#?n3T=9_gl`j3)|5b9b&>i z&4?ExD>HlMvRFsBz8bUditL`bw(Bm&F3@YUH_v5XTeZT4X0Nsq;&8~>1n$z=J9qYq z(#w%AdmYUHi!VQWj!S#<+}YKnw`1QG@VB90&(gbzeGv=hIyg$$>{31gDCg>ZxGCl0?9&wXBYgzlayS54Y^YU5GZ zlZ4SclOKc|%YnI&z1E#pz+iyGKa1Q+%=wG=^sr8){(M}f(JKzSzf zBXlMF9J`e@&-i!@cJ&aV=Yh=c#%_IsV|N1a%g2S^MDLIa|H`*YCc^RLa=|fnGo-Qm zgYcvabhqF6`{vnF(|i`vVS%e^TK)wDbAdabYo4_YZ#NHax9+~$|c{~$9leRl3x(;eRC9w_%4ucjPcy% zphUhaYo77(7}%}}QI~Fh$9H{$eBXfh<$V7G@%__3aosr+xqjb@55BYC$5^}LnnrA{ zXB&m$MUqw&f5-2|yBbNb20@oK-KwBTc)k3Bpr$*cP*hWa@=WII!y$n+RaRY|8ISRr z`!=CsT31tjgEeK$@|xbFn%-}`#Ofy!;lVK>QNdADhN7CXBXBi6ulP3Xy)&^ozvk|> z7sthFpTtTG-z98vNrseyMuz?J3j#76h(Zw=1j;j+uk1efNd{%jGd>>UULn#1$^4EC z`Uc5x6LKsk!ykzZUzl?YXCh3m;9{>QY8=1n0DeI!G z*^I&ThH2d{Z~7gD^bJy|0kGv1dWR@<;weWVCh|MSReTWSFklpvEx5nAHD1+*^AtKu;5Qk%pyuwcJSQ$gN6RwQ3e?N?Z5xG7Dyp3>DAXB+A_@ug3$P3y z6NT>hk)u!tN^%a%@DAI6bvII^3v}bc(4`v4r7-j;XjSc#Ul3HaKMF-v73ddW2)3$b zf9R^(i;|qf5WGWoyaw^Awmgbu0b~D~;)^l08PZ;D3=%d#460soNq`XrjR52F3jzX6 zM4^ZP0xjB}J%&VV4a%Blyl*Fru?^ksh6io#cCA6*U~3pfs^zWW1LAettRnyuIg_^T zl{YgnJBeY$_)g-62h>Tlw)_$`G^4=U;zno)cA+EYF-CzYl}s)vFs-0bV9xw>L4o-w z6j4ARy&&rAIg3Q3fU@QpACIy79^Dm9vOhZt=&Pi_400@|0F6qiu=NLy0!-v~g5NU< zzda>O3WNxG3jEIf%PDYyAN{GB7B2x2?51~+#i&t<2}11Q)oKNe8tdg31k~6Ng(7MQ zlxH$u=XLOt8p@hyd_2Z1nce`+w2m732B}dC*m7!QM2+|SyQ2mZxn<>h67aj?gBn!` zd1_oYu$&qfmR@Jd)Q(j+w^!$SNv}j>;>?P3;!GXes)>m+fyKX`1@4@@ABERkGosUt|K{k#XnWr@e)ZEfK-C*)b9pwmm8q6qI?rdUnGm-(vNgF= zFy)h#*mK!T2~s&xp4~`mw$gZcKCALPFyqR@M7FDJNTy=8NL*nKsM=<}9=>dDCsVCd z9wuB~p0}ygvfZb${jx6`qsu|f zWkn#9WZYcDB$lKtpc^MjqNZgns2nk@0r7UGI9|5DQ`s)|Wn&^|lC>S>o(PLxqlitg zZCZ^Jj}+fs*d~q3mg4xiF)tPV?f0$jc%Mnu;2{~1t-42%F{|^G%c@I?H&)xsngUb0 z!2HUn88S_DoGIgf`vXmQ6N8iR3Qfvka#83?3vKXi3vHfdZ9p^UZ}B7Zq#m24op=h` zWe{g;T`esO!cK+Lsh#hx!{HVUQ^B=H*7fjgR>LBc5LQn7=~#^){|7f1k$@B zny@k-=bVXV>J}MeJ22eAew*yDJ`cv~uGo&aleDd3&s>-5%Vj>6ar>n8-#~=UJ9%Px z&;6hnJ}~VVj*WHg{5bg3u4(<)2?lJt9dpy z{6P`8UE*sR-eh1*=|2Q$@t>k7P3f5xQ~EkU+X4pMl>Spp`_d>ar}TfJkc>Jt!M7OS z2d7PD9y@`Gqd<(VD1ICfeJz^Q_W&>y^uq0Mllr4>QqP!FnE0;fP{i$m8hm-g8~gIW z37Fl%i2-caBPRy&8*u`g?FT&J`^kxc*mnGW*ra7Ix3?mhpPcAh&WXpxiC-%@PW0)i z$sTf|H=0!>Kb>y+bfOU#^3woyp$uxc6b3_?#b949n89hMj*qM4qbfP<+oLS`Bz~ik zPr?Z3OFqt$Ph|H_Mu2C1HhfAYKW4O(H65z~cDs!q>udfQ%p9z>N08V=qGrTLkO;6x zkSbKAi)ABR{OAu`oolPFerj1;^}PO^WYLMmKOoT8E5>&r_mG}59&n8Ba*St8Dm*_l z#=jQ*R$Pc~?VC{klgi%-ciQD2b@>^S3WuJs{Hu|_uL=`4oO@N46L8lfOas!q%fgsc z*x|D9DlT;cxCo`C0hffh1u0w-(o*~$wx=%aX(@gizv+T(p$#v{ib%LW40zD5{d3}} zhar zbjkfF-W=aNy(?zvjSBg58My;n+4;GR+`Z(IjNF5cKVA5BM((G+Eq=P=2E*2Ep(g6((#FUjvaj2u_JRmN|w%W$U${a z`gO%l|6vR&ox0DBtBTtmXejS@;Bs>+yccI^wDVItj(LNh`)W7#AL|Z`ZjLcn&*AbS zFQ7%Ai3>JXd@;yS-sn+Uv3TDw)>C_QlN;4M|8yZWtDJ45=Siq)QjpJA_R_--*adFu z!!H@P$~UqAT`#brQ003UHei(STUbxwm==($V?L!_+x_HCA1U82^4dj$5f`XDSe{gP z{ij?*K+XY=2qVHEQ4A2ppim5eX~l1g$I=ejB?}=^43~L)6?u%7IV>IzQ*K=EIgEOG zYL7NIjq2vU5zpgM@EGf)hZDHji;XH;1k9oLyv!o*k#Fcm?#tQZ~O( zZ2r=eqs};MF;Qmoq^<*-g6r5k;n)n2ZU&2xwe0u{gjMF<&lvKE{ z+i`kYyPgR==f+~Up?TYX@t%ziJBPrX&b&qnTh!-QzCL)_JsXqi$9T`itn0_dTt9|= z(XV(+q;Q2h)LDzi+gb){g6E)5I`+Hw8tr+NuTKgn)l^a1I?7sgngF^P3X~F@^omXA%Z}Y z_~6HY=CfD+3(!mp%}n3rLNnvh{KLf4&}J5j0nr?K8PI%h@Q1HNSZL<@o+mVO9!*Px zrf&mcFwGfCc3%yjU8ZKc54M{e|5Xbl_6v;s1bswNi+uyv84AHDsC9<`R$Nzcv{5f_3 z)FtO{XM&0n-(6=9I@eacirM9@T(#|f9GJECWr*Vi0QiI z%=9be?($o|m*%gip`j{$fjnhq{#b4t(O#Ri)R%O_W{>x1#i#s92S&@CbIS zWUa{sJc<44+ISKI*%-SkX|-TI-+foW^SQU14)mm}q=HqfqrK z4s*2{4XZdBejkN4hJMQ)uHg-PIAeno8P`|R%u(MFJ{%>P8%m&CdOtmC zv+2?c1O&!3GVHpB9`>5dKQD9|Y@ImV?!JfdLWLrMb#$l-^1xZq6o)la7&xe~%~3kO z^N@txs;X^5%zy;b9K^VJNaG{up6R2><@e#nwT|_4LtVvzqUWy=Du6* zMC~KK(;(b>4}+thn|T%;2(J-k2eL8z#PvTXvlFGOeFuUuF5CqIG&jw=`{okiZLZ-j z=}uVgGSM{BJlB=vX~clJ(7~vx%lnuQ;Hr*ik_TcyPvbEx>1^r^!~YQs2u3SzjRZCS z>m$q43PweEgKNFdEEqqt_h>j;oNLT^dcpW3+;8*q3C7C|gAiyI}aeehPf22=@4X_MOpGmhO>8gd~bg4L$oUugql45ce8VVE5 zo=Imc(JT{5MHx!+;cQ@Ig-JvLd_FFGx#ce%Vgi)}LcRko zpTf*XKsGN|I2`e{u7`a5jfl^H5nrWr(J|uF5b|su7E^W|ns`>k?-%ju#)w}A`lCrk z{05d-YiAOE`Ra5*1BrhWv35G&h|e&IUx{Bktl?ijH>DdxL>VwD(Fa}J&VWQBnmpdzbX*3dR!Jt#Wgmw@sWq#EA233TCbcTi z7P!7Z?XHwunrf$t&y^`}ht$OkC*8#i80Wa^M2jFm?eOAW`@gW~E-&qyd>?J%RkvN1 z3Saxr>gB?J!&5d`?4seBZ&7lmMk>7ElNj&^Yb_Yvyr3JQSva5!K8OlrVSS{%PshMu z~<&ogH1?lO~Uq^_{PA!9YA(lMNV5$ zQaNoC!EW{2e#$is3&IkLC!}JvdI#3F5LI(Xe?W9a^PCImTF@sHCF#B*F+JxsYHumi!dOd_i4(5mxtsqcQA8GCFc!ll!K&Hj(xeHo{Z6fP0QoVgKz;<`~pUnlx38)x)5UzHO%GMEF|w zIj79ZAj#V{P+sV0K+m^$KJgD_uJ(qnv8Ts84W_+k4(e#s*5}BO88T!}44J_YoK0Ls zBfvbyP--`vF5{l8(0Y=#%Gw>PYdWZFwA$0ZcTM-jM%7-{#UA5vqvHf1cI9N$u?vI_ zTD!*3u`3LDuzNpUKHJ|!*Te^Xi$KUX4j=~vg_(~4yD!wXnz@dB6kv8){Pj|$fOS~} zv&+&i(6~{RTdA&3BECQ%;s#~{@f9W!3CL=r9ERHU2#|FAjY!9U zk&Zr+PQPW+Z3eixKv$$=SMNzjAV^10R{Qj9XO85yN97)Y>&tyLlKJ{@WV4pfFDm2* zV$(|HI(=AvTfecS8kh6i$~ac;PhW=hzptt93g3uFlH9g7H$b02$x`8^f9X0)2IHza zdrEYf+QEwv?_i{}W0W35THC+o2WnOmJ>{KeqMq{f4wNpe#b-6hS`*qO3Yh;Um7cCO zg)2&%qcIQ#pZ=;)72g>pLzgP`oBUN~@^`nQi5K0gEkU{a#r6T_FQiY&zmut413nP* zAEsZLWF$`l;d=)W#qTN1?-5`cv%ktqn2_|SVi+v{} zKUo}a<>am1W#Yy5I3P}eYK0f$Y&(C#&%VVePz+L?)hS&G4G}_U_7Vg&X&6DNN$kI& zCZz_;VsZ=x3yby$QTQ4BVr4$3Lj+JJT@iQ+);;YI*OabIg=dC@snpE-I+3-DLvFW* zT^2fDs}$_NL2T)NL8 z0NporR>A8&gr{;kT!D=&M_hAG3k5XyNcTC(7R_&)?o$!I&V4Sf`*1OTk?wQv0}-nl zTf*yJq2}y$Q0RE3$&Nt1w6+6fbcBo;BqK(|2q=7mTGQ4EV<^4l6UI2k7(Hclj%&<@ zvE#{F0XAl#_{r#Pqq6*84f+3y$v+PzLoHPo!&mRj6T(6ml`mxZCRx5v<(s6|3Gl)%fz%@|K4$zt(?wO6#OrGwS2=(O$gaLCJ?|hxH?F^7?$b>GRk< zdly73XV*YsfkCLWrHbNvxaV^ch zlnOU@RIn@FvC4{qb(^;2=UZ3FwshBYD;8yQIxh!B2it~BaQvCW1gqiA01SYHIy)#u zhhg@ObIhj~qA}JI37eh-LsuHQ1v zk0Jpc^nxpzH_(GWb}j^h<^*}X^gk<_9~aH(#%Nv!;sUD}&5r@=kcN4qc^ct5sS2by zLzuWDz0sUuzIFC(KyX}*SKs013I2HEw<-(Wi1-45Y%Rg2CEiQ_}8yYE@Mlz?tjXMuq1q(i1KkrChv(XD)RqkIA( zU#H8bF!K>$uj+AqMwO3llusb!8*up)WB^xjvd>38M>Wi<1_Oc}?@Q<7U#;jLegY(OPdapsuCNkuitV#cG0y8?lj^GHS} zC`@7!;Hy!qd~~CH0wG@lK;~1J`3Mjb=vg>TG~x6+A||jnWgT-JlGq8zh`Ry-aV4UN zSYaY2z!ym79vOY2d;%d~mCL6v^AVr|(X()xXu|g_DG;TCB{QiI$siT_1q#QcjYL$S zE2-E(kCO@l>%HYl*<{6%RO}ZUW`W(aVG~k&_H2gVEKr;b=&U2Egk9m~sS*GL0M@1FowAO~RFOOfyLdnLlg}yI?r%*rUQzrz*v})A5=!&o&nrRc zgSp@+@|tnYPkMH!I&wjhZLB_i6(&Okpob7qmk`djTpF0lEDby@!afbxbEzJQ{a1Iw zZ`L&7VQ?vz{uuVJzju{&@mT1=$r0s6xrnda;&&lb!jU^c5vx=YLmBHx#!0fQ_JJPpD= z1J`qEKN9<|9)RDO&d6v6mvZU|4is3)qj=+#@}gYCSLW0~gvcpD5vx=Yrx@#vi-#h= zDW`z>M#EhC zg3~TtgR5yd$jdOA*5Ni4z6XJ)LDu1ho_Xkmc&X9NkSPH+2gV)>_U>6qa0G}Ljh2_=?h8~mtRPQX-7`SJ5QfK%bG zpGD+gZJUCvQksh&LLGeZ8b~~|j>yibfui9enK#YyTY|wwmlQfXFmuo%eH6bsYt-V6 zt;YzFao4|4%=TgHf5D6JQM_^pfS;?em&05ht{<NlU7xj^=KMQcF=4_OQH_9!sK}sEuEb-v$}^JTC;mw zjl-@=zb(wQ_!P{u9&>LN$0BJ^Y5?Y5V(up9USaOe?(K%?Wv%pRvv&+uz*OFY~VMDdjcx{q;OP#GHK^SvRPF$Nd)v za)A|j5cW!98;lyU&Sq*EUr+nOTsnvmkmlVHrj57A%Y6@bs11XADtzwWx=!7FEvu8t zFqEogR-p*)vq3fdGTsrG3jgU&*B~0-y_oeT9(*O&i$?+(7N;@sn2n{GgJ0r7U<$i4 z?B{%a>*WtS@nF!2M@D_IT3d3=eTmzyC&ff=L6{^H$H|pRaRqi>oEN$(IiA7RNgg_! zfSHy17xs=?6L#Y93SeGbT&q$TEABM>i_=(@CSz%);8&FhM3tByKR@74_Iu7ETb~jn7ce_M zHLUoXcFnUZ=^Gd30l;wG9NcMym5Csq8q%grFSJaEKh%kIoI_j0wV#o|XhTUDK41?i zrJL5niu^;A-;I?GzuTrht2Oy#y6MS8<8N5cZYSx@`h~|#@g+Zmo`PS}MPMp?SEKK4 z`7GFzIM!e^N*824sAk41G!jgKI%{m-Pr844CE05>(+3tB!2h-TMD@o za|RRD)jU&Cgn#)I^@X3Zc5|;4Al^TkBy{7$z5(>ePYCw}>-Ni6*_%nWl@q!FZ0P74 zxY+`~pt_EseBp2GBW{DRokRJtJqTnuYb}FXJ8@{O1P2O$f%`<>Z3z5s&G1p=h3Ou# z3ytd*8f$aOFcq%(6|K;qTy4n>skY?$6v5oZlAK9}M?wnfM);$$-x)8#xyt^t?iI@Z znt0AjxgRd?ilr|cM zFlB&iHX4R$BwdGJ7{D0oCfXg4#n5k==v_$AT%aqWchcjCP9TU*kjG2Eh`y1Y zU~^fD0YpRyX7Zup0S9=Jwy`sxBgNpyxVO@eDgXP88<#4mbC#yV>C z(;v`{s3j1nbqYXIOJP!rfNWm5B-Vp}Z@rp&5Z6_pib= zn$uSo5K5Xegy|<-qdCK6nvXHo(R@-V=|(gc2-F&9CeU1AQi}k*ajhKmmuWsF7~P2G z0s+eefW)FOu@K;~&@Y-3snJ~ML390}xmc}S0=If0-#K^`yt&x+q4wSE%602aEF3fxJGmO>I5at8NxynT%$R|Tn$L!7s~)Q*w2mj^G5!79?TeE~l=)rSgxS|E_5rnDGY``xS8pfo;o4edV zWs3q;7^Sh@3~t0Mf$+Hmfc%`o{2T$ksa7i=-6)?x$XDs|Da?EXU^^b%I{CFIKoa;4 zcD)kNjp{5AkktanLMTjR1o%R1P(Hd*K7o*Loy(^%^AP~v!L5^DivnbTFT^G$a6SGO zC8ir876^zp1IPj?OvD7hga;R+kNm=fq&uRJ(FivW3zTOvZ-?9pKQ|;PYo77(7>t61 z1Xsf~KaCMEnx%m4 zTfiPhsXGKvrvd@LmVpaPW5{Gdhc<^?rJ+=Tk{h z6#W8)vsxcU0^GO;S3Tb$dhkcJiokkki}>*srC&W?f?N)6g6m6v1W}%*4a^b{LeWqt zvWOj399?K^k>6Rwl+-L@7AG7l&%eJRiTsOCh^M*Wq`27vjJ`x2!cI5hra+))D}dyK z!lWkwFm@^j{bg>R5R7hwMIc}~4j{28Oe_TWub)&tx=}uXkgwh4Q<(V(5I5;rI88L+ zH*Si!$zq9{^cXi)QqWevWo~vM0rWMvrmxZCxJe+m*@+)tQToNrZqY8y;3SkEwNHkY zw%jho(2cd+G7wj;B9mvuF#JQo2wWDylO;qLyTjo|WDy8t83mB!RG4HTz&EOC<)a(r z6A1anTt0=Fj{yI@8RerJglHLqK~zbXJh_ufhpby0IB7$b zY&`5ll{4x@`-F!s*5@O?>qM2*I#G+`_s(I&w6ERhzqYvaTHqrJ*)osC_{0TqvKM=_iSqx(0qN2)md(kncT?>#&Cg3PzsX(^bjJ>5~2kvOM`VOO9Ri0ug`zDklMAHVM!U;?A@BC;_T(%Txy4=9#t?9;j*w+(rq( zDWBjwWXQWeZ1B&g3!3ZHwEVT~*kdAUJwN5_Ejv{cxu`K?$TEe=DFNsqL@XmjEVDG= zl%;`ZQrP#$Shfp^acoWS-SA^N?C~(Tlx2^JWu+62WiE-aOxaO1A}F&gg%DXLC}Nc= zVi{wx77G_jSmbvsQ&MA@#RLD7u2t#p@07)5UH_`rR5b8>3sxxeIT%ti+6) zKt)fNeef?%W6ancOOt|M%pee4V1E4E!k_Rld%~+tL1RX-3Lo}$Zb#X?|D?)HH>$rt zsDB55tiQsnKLN1q(nb9lg8nNQUF_VGpDt8)`tx#S!u9oE%lfmoYM#Ri4No@X=4u32 z)dX)-TwDk_^kDjmN_pDsgnuR4Y>TDY0l#QNAc(^J_;~|=!moVA2`Yn*Hq%w*Qeb%} z_$11nF3?TX1dpjd+>F#P-2mhX*T)KK!8;C$>*dQO!lrddhArEvU)_kpVhLYG-UL@GcLb)wH@-#6DsCCS&&RNr z1dH82W|CPX@x@4RKb;=Yii#l+iZO>|EQZ1?1_4VBxp*{{LPIx_c7cFq-l0*LXb6Cv zmhS)lLoQX|1ZJ7|m@jHA3h61aPQ@mK(ymY>?dugs*PS%c2@ogkN@~)+p^Rf?X+Iww z4fa2@J83VM$V)phNZMz?9$&OM_$BQGroy+~B5B{Tn!6yDccr0nnix;Rzc`JF@nkH` z6#Non0wKT5kDnj#Cw$L<6JrLQ7=J=rS?mLwSY9{QZ&B^(MvNB-jNc3(Bdjxm|Ek+_zDzbaowyLkD;W#NaOG?PGj{SiKQ8ZU-c&t6=#0@ zJj$Q&JvJG`ZQ2O>`r|5g8{hmQDSIl+)R4qW)-e2H8G)(r?{0Q1Q*Ts8(wu@{^&=1!V}AU6nLpu2zU27JpsOF}df}Bn zS_QuCKp7X~HyU>$wWo0x{40^;gwkvhX->i~auA5e`0!FRW-6@@pvQI{_Ko33e?vVs zii*ZbnQZVP^E}n0_!0XKl%5V2aGxQ>|)pD8s^ORw``z zp#a4(j6c!#r01%69zCw8(ntG_YcZ!CUmXfM;C3S%)*z>yT3Wg_rd6dKu`AIB6;9Vc z-v9x|DHxRBjxG6O98p%fQ85HUF%AL9VkpdF5PBLdg-3SCU zhY>|I3KIxQ7UOw44PJ@2=w~;MS7=I9YccV0$piUN9l1|6@m5G^N1ghmwstg zhgIX<2>PO?4>=;i#p=#4av^Dq?vZM=iq0nQ8 zn45E0$ND)%(#3>?gRnOv^#SB7GYCKQWw=pg1VUx{0c2$qW@QL~)(+P{ZbnQnMc8#O zI{ji|iS@=&M&(DC*h$tf{9JD&3}*5rG43$5yX}Q(DFW{N4>_)w&T1sp1H-M)LbXRCE7s95SF3?@lUU(+SQ)dJGu;RmwN>Mc-h1Va)ROa;@4+ zro~a4iSSY}kyv}7m+i&+5K^NppxYX(hMO+XjoQl=Nzc^)dHQUF-;TpX^brV^-hwF7 zM`6;3fUKTMLwg~Ta(me!G<2i(A`sAQ1(0YICK>|VU14@}4$o2(owXPGD82eEx0js& zHy7xtz0}j=+6#g8P`U8q@zSsMvO_hlM9|lGm;6SF-OQp(Bl$&zqV|$f99<|Hk>9l! zCAIcqam0F#_F^0y`heqLxkSFb5QEywW)wCTI3~fb_CjDPyv!EgT(?N3wu!;kM%vU; zT7z!27rKeYTfIGtwuL`LhID~$MdNj5^7Z@pXzs=QMW0?L|0e%w0-=7}Dw~rq;%E~- z`&^qoYFc?@X?+Kem&lxkV@P^Ix zSB~OvM{`rRj$cGi+;rFL1PQOn8A_gH#c{5rE_tHiGMyheib`vfPO^0&d9w6)yxuTU zBNkVJNxDn~Ho$)-sDXK96JGOI zh#agv6Z{9L20Z-1um%@zdOAGHOpwo&3uYJ!XZ})|Ex7nLBsWQWwT=rdpP^mLTi-b?Nl@4#dtny3A$I_}Z;DM#s}x!@GV0gvxEmh@$leG%jO$dX>N1Q#w= z@$Q=jtoR~ zo?#^>SP8p0XTqoAg^N*DXPHV@0L`kZlQ^5Q>ndDwiQW25bE?pkuh1MSG^GX)q2VBYMXTJ>@ zO^!&$m=iL_6!;nAPk6l3$ryvW3v?94*Nt0F#EwU{DiwZ)@V+PMAjPshx^uK(57>s3NSFaO>1#JB5_muwi1o$wrd?I z-!`DG$|LA>ZrA|2Di&Dvp%ZZI@#w-XEJ@1{4Oi5HHKzs{&z!2&PObQSuqWWuIhgTK zVKB(WIas#UZJc;$bR@}je%KI}*bZl6JItuFVAwdtFgb-*f;mp1lSMv&&1Iv36$0Bm zII)mpi`ceujFTK=DrTHprUD2@w1dGhjCRJ=G$xL5Exbe07;aNL6sJN_5$4GFhYz@B zV<9--5xZkiIl|UztWje!z{#1e3qQpULz=k@f3!45H@L&jteI0cxWE8pc7r~)KDG`6 zISOpQPxOk%X(vF#W#any>;iB>qYK>NNAB!hV4C3 zWdc0NxGoTkBzm0fW`OZ$XqZ95s|it{p(KDi*MZYB!7;(3v4QuMyhizygnYDah=!h- zj|pZtEf9=kVy{EP<6{c-YJLX<^oxwnRK5(!<-2&5LQTC{j1g18Oe}J{V!CZp`C1Cf za^ASz!&l%wgInH0#|fq(aZT||JzAo-;|&b006Se;TvWD3p)3Rjpv&@*-7k)+x1)FW z$SURcJ+g**xBY^Gs^q8)FJ4bBd3M<@-kiF);!1QBdpK!v#Yzadk>fcZao?P^(MA z9bIA6I9rG4$<}F1**cBBoR%85Pbt6BhNMmWszv44*7!|RrH$cvzMNA;0Sz&o(-$F` zy~y1f3aY%*@M&~qY51y2+f-?5_=D%gtHP1ss{-NIZH){FT-F|R63K2M35!7dLyO#_ zuX_1a7r*M&S6$F57H|oDT3ZZY$#;|mi@%|aFw20l^t*jLgP)dd`)OY3^L;tcFKi!s zl5B{Xw1^x#ZlVDPvF$xYy=5v{T)vA0oBGh9Q^^$NOiL6dUU6a-m@Li!EZLmUT5*;7 zGVDA}5VW}EOBp%)th#8!BJ)8d&D94T#uayf)R;2KusgSy%!w7~&rFa$<2G7SMYVYn zCepz*BHiX>I~8eW!S?mdIRx9E2Inr=-faM$6l~~N?8Z+DwtWZ!R<-5k$33#wz6tFBH6bK9dN z-8|4xP1|g(F>h`Q+&H+SkD*1LhE}d`2wJ$ff$31zk&Y`oB+zpkGtHxQ6ml{_W9CsR zQJX^{Yg&wX>MKa zWO=Bn(pzP~xD)1WvV_|&L2c~y+H4>9phx|BS;;?^KcdbJhM>WvEt;TZxwaX+Eb++;YmOq+!d>uglE5}airUp9zA+|o z4xj&a~H1ad$5EkTGA4@dM+4`=+XU?Augbn07n`jHfD?!nz(5a|Ox~fM9>o&^hBiXeWQo zJXYqt#ldz%S3cRIcur7breWRnW&!ZS8dQ%o<_GW4tC$tO-YyZgTqmh(l^kG`(9E{aecVYjHx(j;lfuGh18a1$+GPwc0DmK#@;|8fj zwmq}<_5^*#4f+a$UUGxJ8tmQ1qYQ&Sx|z!~yJ4N5W~KTwD>$G*+^<1Aph4WPL5%c# z4jEp_=8^&EHz+_Dg@gK%c4pe@$sTphkJwoDc4#S1tJZlCgCLx9JP(f^2_Qs*W7Q{O zP-<#u*mXLi9j7D1r2RUrK1_T`0Yl2k&tMG^TMGWii@i4?N;xa4lFp`IR@i zF=Y+iY_sL0s=QeUoQn_BpW7)zGmnxtc#!d7`ssL1)Mut)`fmnc^q7d18aZ#X(KB)k zQ1W9qdNj&F_g{YyYv}37eYF)CaWLrs--+j(1?R#T&ex3b z@MW*s%JFV{WX;W`?oOzcHag$hi)X_+2Rj|d*$#Hg1HlV5QZmTqT2waXTDAZltt7H7CJeU6MTs!ESnh=dK@<0+ zfU;8H!L`-|t&vvMO07z#jkQupP^WFI37VyZH<}XONFm+Gw~lD-<=fgtv^Gz)b`T9w zImp>2ifsTb>|8ltXos&=Clx;cq&nx|b-@ciw_F&Y2C~XPVozw1VT@$p zE(B7AxMeALuHIpBlUimqu8}_G5r5SBn3WdO$7K0XCBt%`NG03B*)zZLm+!x4j(qvjI9k*3HuW&;r6{8Ym^rx;xH zi8+eF&)piM=ya%`m<#ny@tm`u9$utUBGg}vyjkSFYWEz;{lItUfODx88TAqMpZ0jp zS#Ul*hVwOJm{o=tw82+|p5uhsOi>Z%;xkTHujA)nz7~$KL%DUI+A1=^PZS1Wd>wL5 zNtmc+ECQkEnNXNeo;Qg8rbE#$kr8;u%0*g$K~lv#MC5{JY3#O z4y@vh#kA|1DLIEQsb^=!#3W}b(N4B-Gn*2IJ+jwWv;{*HDwQz_m$7_>Qdmp^pS2II zP`DgdPya3YlGlh@N&>Yg=}9d;lUhtj6Dq5aU;_4(MJ8bNO)~Ka!a?zlV%D0Od@dHj zz&!($gks3-Sd5-ojJTgduT8^HqY#`m3hy8@EkZlhDAbFvx(!z~%2wXEMqwfvg-I6D z?ShRFpQhy%7GvX34a)p%Zv{hp(Xkoh;Dj^PEkz(yIqv{M9^@UU<+r)L0|^P|KidfK z6UcB7Qc^nMoTB5NL!EGb1c46}&h^nDr}d_Q)DtB|LO7fn%eOU30g)y}t*sFXNJC9A z%4kr>D?r5&9AQPm#p98Hd!R|)1qOVl`A`h!v;DAdVwsGOa79uFlOwCek)hd<0ooM8 z$#aJ68OYHK#cuozc6%h8TNSz20e#5U93>TvgYCuGXzomaPLFsOx8w&(oup8goF$!d zmUO8)opP2SJ)fV@Sz`0$ZFUv`)79?g1m-~nIR1FG3aa&jnK~2%^Hmo(eASH^u5330 zJ}M&332b$Iiq&!SdOEhin)_1m5`B!d!2bDt76oC^zS8zgZyNS(GzNu41CqYMF+$lx zC}ZS(E^v9G#a^eKkFncKx zY5;}uY}5yq9^6UX=>LLlB8R6T9XU*T;mBdnk4`7~EWAwX-~7Pmaz4C#5O>cvV>#1_%gG6xh_NWz6#sGqFmf3rd3XmhqEja614h4vn|+*K zO{5_N7jD}o-*3@l$JK!!rE)F*WdYzPl0kDK{Mxv58{DfihXARe-bH2m8=_FiiJe~M z>&C>+&R42xpwLw5p727eXpD{(qGMGusEDQrez`M7jp=l`OAT(+5v3P3#&f3Aac?Fa zml=SVUJY+3Mqan|{*mL*d;ZmW@W%EG%IE6AzdcVMrBnX+c+PanXZ7IE8360Shauy^ z?7@GVc(gtEFRzIA;E#R7)gGJ!Tp64oM-N_NAIOomgP?5kLIMb%Rw(&(!mI#lv&M1DhGy+fr z$JGl##@&OEW4lGQyY7X$oxFU-_`Cy=k6hjvg0fp$oGlTw;MN=2_k6aA47rw7eb}jW_wpxpM z4hc}E0tm4^SdOWcW$;%o#WWDM5J9$t&5R|&AKk|>w%kvYxvA%=ug1FebZq_Fm%HH= z*FAm^&pFGW2n>MZ+>;=^`u$Ss0$5%l500OZZ}g!>RH`GDFWa$M+;qMim;UqCn#bC4 z=}aB2DvHL%iQUz=(44?3GF+o%EX<4&Woe)ncJu_D90nM$g+T|WgE0>4Y`An{I@pC} zbomNFGwX}$-^c#jO_jG#8bfzYF+S|3mCrC>Q=IiR9pC-@x|d(~>m?Qg;p<*;i!S39 zvKPAe)^UqL25WKY61U8evwN_JLx(vBWH!-WwDqi+6j-9l@*1N+Dv|6=)+W^Eo?w{p zF?I@rArfI2R+$lD7!fkpe?^kVo0XV|-3X{Yc7kTR`nfw(NG}spJC`ASYA3r>Qfw;` z!Vd>+cey>Lt3_2XbJl1|7z=kbW^17meXdA-+^Ixo0}U}5!o2GN;{`#r0WJNYVScRr^E0GYJRYF3j67{IW?w6)2F&2IR=m7Kx9q|#)s2KFA5*v`CUkaBC zXRx6N=hFe*lqZE6v z{sMIB@a`|M<FuW9C8>1G1$mI>`YH!rBMjkM07|P$t}ukdb5&(sJZE}Uvb3?j zH7X^|WI#u6LgSHQU1&TiK-8R?=sRha@1#k-lV4beb3d0?BfbeLO zwcN>%`XE(|{ln?e2V2jx^=>*n!2kQA1d0u=nC*5>k52T$GlQ;dr^hcfBwuL*SJq*N zp(l+Bqyy`gUbP3mQQ=(d>dP8p;aEw#CrW@4C0EaoE1de+nZe+6h4=YEivt$>W3&lX zd2lTlwiq4wjmn>c$7c+T)0Gcn8Rd^nSN=L*KEGT1)u4YtFh)!+5GBxI`sw=#8tM3v zQ|?TJeIAWlLub)c&^GewN5HEtXd8J2etqwOXP`{22s@=L;$!dm{2a!_gJ#qBZe(i)zqv~kCaPGIoF+g4oi+po+mKwKfZ7>Ur(x?{2TWik0<>AH*Q5Dbdy_$=N_5 zs*sQd$xx(1V&WdxM&pUlgBnI zc^YiY1CfVqT-rS4S}Ao9aMB(n)X*W^f~({DoSr!|XvyaK6B^#HUG2J4i&GU)sU|S` zsvT3{;bpscT~+cfyLrLlil3u_?BTSMLq=YN-czgWB z7Q`vdp^k8~B3~eM3z(n2zyX?r6vhLNn0+EO26QGrkO1@=>0DejF5Trd?YaP+i} zE>Vh#y)C5M<0#eOD8)C4aQ=%O{^%ockknDyy0y`ewsj-ir+n&yx)JVlzFpn5e0&~G z;6AM*?;~spPFMA4b@~cCLyz4wLHP4*ekKuq?sS8{gTvY;RpEV;vniaoiOTO_Qk%#z zR#}s>a6>3adBTtFV8Tr7396M7u_3*;eA`|PX?j33r1xS-Q(=L*r14C16ZV9s{ID+y z8rCqO?ZE(X_BvD`7zR*fLbd~DBle&jcs@6hG>`SY#h>bWYA>puiiZW$m|7Y`!2@APNgcWy6@AnZn<2K{cdZQ?q zGEy|hkzu5~=moABou;Chg7?I8qP8(DhSMi$GcJE#B>;|NH;7|%R+E&)Mpi)9?iNOO ztc<1QySt>DQ(cZ{<1r$kn*;|-<_q7ddN7Wy@7?QE^Qu#o?^;RVAIR@fPh)uugJ2?N z+}ZhRb||~eo05myzLF__Q6>-HOubQC+{So#D$#GgXkb#qheg|DWTEV5hC!@i`C7Xz zmM&YGCuSZ^oNupWXt`&$w(o@aJ4kQgC6Fkx+-@HF*4T-a0ro6kLpD?SH+A9m7h3nR&_0VH0j_8h@>6c=c&au*WsQ>B zhSkNOn81?UbbE5Z>1i$&WTrSJko82CFO&e`9SqC9=iCtOE4T4e^Y5S z3o9qUXs3qDcBz*^Bo>JgbFbZ=%3fSII!1gtekl_9CK3MI^VP&7XGtV7FGOM=%`PrpH z+f`@>u6tae?JN}XlW!8?TU?<#@>!_BoY=n>htT1%Y?nC9;)<7}?QDy-qt#1P+HjNxh&gS=q>fp)C0t9k6g>?n{dG zZLYru9lj_yfeu8xv{mO#zQ4HAYIZDP8!9*#CkFuqSFCpTmdBcjiDYFff5IPsT|3{~ zqg+$H=ymc~vqj(*{tt!wFuKSfGsuaqL^<#gU3Bb;BB-43ZQ=jy&{NDwYP{|+HpNQ*O7l=Mf=fQjv|Tt&Fw-yDWpWN*bwP3l9rT=Qq6%HT z7=E{QzyD1ejmVNx24pwptpQmue9!NX=5-ud!cn>0u88jQ|k_zWgNC- zDqa+CGcNONRo1?qKzkFy8CV$f(WBd6gRMm6(e0NCvfKXVk-H|)dTie z$LA-QHEET5y#*6G`Oi}WgdhC4b#yv@hXLKsL09?dTnHJ3g#@8?`5UW&WdJ&aB+-~m z^H2u)n4H?7oZ3i7<&lm>PK)4;Okm+-BK)fzMPakY=tEj#3Ik<=Y78|Gw<^*EV=912 zh7P=q_(PeKEO@U9o>akmRq&(=Mmh>cdcH4Z$a?C#uaEUN&PETh9WzXa$rU+z>KXBz zC^}|33<2>p)8ShN;K`o)=z8h}>ZvdBd?KT#zU2h#sr?^2Xg&2+CpdY-UU`svYR^aK z&{JQ1e2$))jOU!Crygzq)KkmHmWJ;|UQGsKD>sZ-%&dJ(Gi#VW&e!9+UZSLk5slnLt)YF*6ju)!aUn1J1Y-nKpP7-4Tkk`2}s@ zJpTna)39c26vPX5VPU=W;q8ru=1$Ou2hYe}XUBm3xIh{0iVBu6Mot=xXY0~$Q$PK< z=Mv+Z{a++*sNMcckB_h~5~CePT+!XnRa5N_2Jg9T_oahEAMT}Lx|jBtK!ST|c;v9=R@~ZF2Ru%41yX$J?emo-@5|vijS(24F7z?Gx&6KR?cun9<)JI@+br)Zb2u zV>Vq-t+Cx3HYt(pMyrMU$7{+ zwBVa%qB)d#2LWXnAxF){FKxSg7quHXlzx*gwcdwliHAe zO;~&G)rbb_6^N>CiV`?I2`5z0;Cys-l798sdPS2u=1Yvr&|AeAKl(v~T9ba4x%StR z{M3Y5n_^X3adjoMsD#$+5_s|^;=cS~gO%4@Q`~GODCqlwsiY_;?mY- znvR?O_L+_^#<|(?@to+V?i~&4EN=EW1K_yXRy0;p2iw_%pba#TLfmX2(F42UZ^X^` zVBCy%w_U&Eh-zw<+!5Fzh0g~&@(d*lVQJD&1pcN6X|sbl+a zVh?L!+|3S1vnvR~H>BG#eu0*>1l}-(4icr%N8-Lg{gsJRP<^UFDtIH45cK)k$&WEY zC^0E_U~;cMFfhweU}}oePF^e26ekI>f(UAnC2Z`{UbWtSoG{CA(_F?ZLV=8tP?;!8Hd75r;^g< zGtb3q&c3bX$2<7mOK`ri8Bl-z08@;$n8*cp(QwaZFx_G>KXSw{o)FE-f(WYtNxW=v z`P`bNCL$*y|OdxwTTB^rE_jm8gz#>+h#{K!pi?nnp}#}~TE zsZ&W7HkBk9r$p}X``cjoN*R#xo1fHip$K|^r;BZG5_*>lj;?OLfSnZc1(#R=27IDB z*m-Gn?BoD|;qm7JF+3W~JE?7iH7JWVbEP%oCZzR9C*mkI)v8d>+m?^uShiF|{Et<^ zw=7ZikrL$dBboP>lhcXj@Pxd=yd2+Hhgib(@Wo}m!LP=P(Pwb+dvQfP&Ce!o6-a*N zsIM|eeZI-2{!fJ54~}$o<40~v*mh3QAk~4qrI)!LK((ZnDuCLastr_?I$WJZtCd8n z%P#AuD(m&GEQVTD>6kLtz>sK!7$+q)5E6RiM|k0jr)8Wf9&Ybu>0`~V_(m1qlwJIQ ziog3AR#gOBbIpE(ogQi$2#fCtT2P>8uuxKbtSvku?bIf86j-}7kT$P*wG;-ei)$B1 zsBykjDiQ2cC?}oLS{{Sw=|NTJFkhW6A8y5toY7!VP2f%S4F>fF>Izh(S!1N{QV}gr zcN80>e+82dUV`}s3s`-sAT1*gtDV|J0>otx+exQfMKtUM`M#fRY)>j)86VU@_h(h zWsd6l{VL*WUxZiJMVA+->Tvh=(cSAT8n}D=Mjk{*n!2EGg$n-~|T7R3BbV(m}K;2~eoS5Q?4&g$W)C@2k&&QcIv_5ePi; z>lfcU|HgWJP`-;-Sp-xk*l%eOFcC_cGz^Cw?`093!kd_?moYSMX=h_893?eC^k|8G z%OL|peI^y_ZRT5{R3R$D8}ZiEO;d#VJbHKewt~FUOF<`hx~j!$In{+=p}IWJVz#Kd zoQ@Q!E~{_@)#Z#uYQ&M};i%VWUEWtwajbtkOs_^;S;XS%Pa!e3Y99wV!|Sn2vusNa$yX?y&6D; z4#68DMs{XUusC@MzD&xF@{8E551G2dYt$2!gbHmzBKwe@*@u`=3uI3wg zJ))kdBtR)~Q1nbFOz=>6ub#LWH`Wt*N841tQBMq}4Yt>JF4%q3NkZea*rO(m}}E|p4z zE6wAyrzZ#vkAk(F{dH%zjxmj8^6b_zO~;M*1QYhV;pQ>d`BloIHM>L7rL1`^tPP-pgFgIgPzjiIx)$K9fA&Yyg}*u97^af^X4>o_~R8 zXlh;~E~q5%FA8sRK|PayF`;G$iRr@7BQAJ~(s+%ypppP(1riBG&xFDR4~6&Qf&^+@ zP~gD@^&53(xmC({k-U<}6j$nFkjG3cazfW($JgrPi+Cd+o_X>z<#7cFQd7xmtf!|E z{ay(MhTWt`ih??_?h3_pDUa9St!=en@|e#IU_T1K5uwiIM^1Dkl!4cX^hyHJ)*_Ka z(=&<21k;SXmqd{8=|;WblaU@?ASLbCfTXxKLoX21Omm38@s8hh0<|7j=KxR{bO7*8 zwpIKzupsPzWTVDMh)Zch4bgZQa+-Np(M2S7QA|5X(p2*@lxQObX)sDGciVg zfHac=5&5inqJOe-fCWA}&4dU2g8BznF&P$~QcP-b>l&Z&(^iA&6%(uQx;!T!4uoQ2 zARn|&UE>sv2I3S`OiYvsI|fw_?4OF$FKG~|I1xrzxJM7O zE2Xj-_o5OLJ$cMGln9@ByrWVBUZ$%y9A0Uv4H;ETwc)^nYV)T56Z<5)D(wv)dYg5f zTiEeps*Ux6zdWpOsoIbadhtoX)s=O~;Rdn`yJt!?A^0kTJhN)^zYnT_NPUrN^YnPm zg6JI~WlacPZvdWjH9V1B4Sjz%iGF-sqVJSMfA>Sy1LLlSBQMV_(b+{4Vbvep2(cc! z35m|BknZ}3Npz}>(lAyL!bRa4!zU%tfALn6=-0$0`f(CA{WhFp5?uoQbrR?{Q2uEJ z`ZAE~v2`^p7mYXDAoq4U0%Ho!cQU#$vVNyK>7luNTeGa+CaUVRM4MrWGTMfY2+rLv zWHsV`fvjC~D4}Mwf?GUpsoe%?1rL>P8&cU?dcm@XPh865EL;Cc-fMKsL(6}}&5snwdEvIch%q`6JMBXa6s9lgQcVgpwN01(* zTL7zk9yso>)3(~Xi06;c&rTMa~(*ha|$QvG@Wv`3`(9!7c)1* zm)}H;?EH{H;|MtHb zC)^h|!>w-=;)C*Cyvof$tyByIZU!b6S%ip(E2WjpWHa8uIKvfN@Z*}PZPsGlD&k*o zjky_8iEs@otAT05eUByu#3^)FsJTkI8QS$Fzc)7npLtwB0>9PLs*UCt6f|m-!oVJK zGtV~lV17e-L**mmdrsFJxbIQ$k=3OO z&xLZtvMzjr^Bh;J3!hVU>E>JcN_<_I!n*J`stX@7>Z0%FQkQzwh1XbJQi;`-WyHae zq?e`2im|%%;ki)0KGua#HTvG_!e_dFuEp>C+bgf*Px$IfsKoT+-Upp5#eE_?;zvlK z?~;$zG5~Ar>RN}?gqr_)mx`GZVkY&4Z3OjY+XE3-*~tRJXQ3=I7UyjmLYlu1d9Tnh z8%M{Eo*Yf~oGRh_$3F?$$on8A?Mn{TVdUc=Q+^IICOB(R&R7eHuReqSX;iCuC{0W(bbk8*|`+1z4x-c^Cd)3HF$6yP_`D*1oQ@Cd8KvgHXS3lWdxph?hoD4McH~uY1Ye}ClIIZ2^iVFxrwI8K z4(GCT?V`esMdw@SV8n&_)+DRG1EKYslC10SLHRCTC0W<<2LCvr&cq_;uNi8^aN#=sjN`bz9q|Rk|oGfqmaYx;`dbxpEf1%Q&=(Z3sf+wgt_!FqLJdU$=CfP zP}e3MlE@U^I98?#(yq9Q^hVG^P-S9Hv$>e2ji&mhI}4CG?I6H~LSQ}6^oqg;-K$VH zg}@ZD$Bq2;inoOi=<4@qxeV`33AazBhr1(y1Op>A$JFPG)zLmR>PBe_BNJs7O=h6qcUg*4y&YZ&S0GHAxqsuW-}r7%x{N ze_VjB`Mprncwt%LFD`bPIeT5%E=uqP*k&24%~GKeR;$}=sEyVpD_4=y3~aP%<|de% zCPdJknn2c|fvX~$*m}{qKVH8Lnrr;Farm0sfCP>Fx>;Yt00!7b^@Qop7lOm2Ri-ER zIFQ-fTEqx+ZV0N9MhW_snQ8V0lk<2NtLs3~VjSp%N z$m+Y}0PfKk+^dDjXxBmhgg-7j(pwdyYB+A}ZZ-6i!joLCr9@zLcGgIeNG31RX&OQTo{tG`|l|0>AE8N9Z+{ z(93q~C9K(I|B=&X|4$))&YdeF;#3%ibjX!00LTq&9Xz@jw2AbX4Sl>b`+J<<<{t59 zsw3QD!z#Qu!HzJIt0Q!%B@;rZ6Zg4VyG`F%Yq#TGoPdc5OeNS)7k|Q6T<=<&k6O(= z>06ssMr&iI7p&Z)eQvEi?pwPK@6p;X`faMUC&Hh;My(z5l3Ts*_?f=LqQ$Gip(fZ6up4Z4SR?_~DhciBi;ByKZg0=`z_n{prd`<>!Vu39cON8}4aiL2ApXb*} zMIa=?ypI`McMVf-8ZNu1)J6?%>a{+D?dyUaysmYHNm5V~!50+PIFsNPZrt-xtZE$f zA(szoG3fn)1oag8rFGEP*Zn#*%*Vp;RmRjGLOVyc@GHc@erw}s^ef@V@DX^JC%{S- z-14n70xVbJCww9Zpp>MHC}6uv@28TP1Xzl65rEc?2*4DdA*nEvMEK@PSIgCSna15z z%avkn5cg3n-*!)`mJ{K8t7VLttyLBCTov2=P(h0nc!ZYl#sVmPl)5`pY-R>Fx;qC0 zJL&wnGq5iifV2oE_6iGu3FiTnDWxfPL$Y8`|96W@e$6m@gv|!oV1bgWB;=;DOAA-e z=>AHO3V1o*gzm_l8U@psY78b<^-2~@?J`xcHEZn_SMce0=fXx6vtis01>*yGJ=u3z zu%1~k6I3wahOb8vbl$jv`I0P9!^h054M+kbw2&SEFhMO=UcPH9UdqfOza{IUnZ?8+ zABC#yvQf;;!n^pskeQs4%ChNgF;1CEbURqelAFd%!c+&=DXm92#yHDHf9u&;EqYzV z#%jsNs>sG_#gD4Ww^ikF!_45ivTfJRD_!Ne7*tx@T$fy|p1JCnt6sTe5-t8Lb8Qc< zs|v0y+jeb?ab~OKl5M7z>yS?6y`gN|4Y3kiphQP_D#*2&C7MLkjFa%ZVS8|cD{*l} z2N~z<&LiJw^@9kCcD@!wU^TQGXKwdM4mHhffDvP6qeFFpu<4@6>tx{PTu#uWi$i)Y z>{`klmcld`OMIg+9GkX~(CSqw{g5>*Mf(EwYj>wmn!lqBVV<8><6zSO31DuUO z6ILtyECuq3@U%}ljeT9LOR?F_Tj&-L%XKFh!v;f{9j^>Oa-D_|-gD*Ua>8}|Gkm_^ z*O$!KGzp+DWu66s(?hgErKs7#GRX#aCYb-CaN}JmPS_ew2FCC2K>I}ee!ZCCUxxJI zXmj{ke1ti>q^+Li#xQ6%3SCmPOB8JrMd@&cxD_EGK;3p{6t1A?9=2O3itZ6bLs4{( zD2jAY6zTa%Eir|BMF)5C3#GKElm?a3s#3;O$^_@{D6c2U@=<`c6`WKl6Dnm=rA(+4 zq@xt1Te}e`D9Re(r#?M6e+z8KW2_j~co zM=c?vF%xgM(`4ynw_Ed_sdgI(i_TTM#U$8k)o5q`${OtpJ`Rzs?gJaEP^PZ{O}eDp z&Ctc;e)8opnKa${m}3o%NaY5vPJ|odInfA_{XiD!yxa-XhbO|2kXx(g$fqsmvn=$lsn?s4o z>{Q|$t()*OIDJgg#Ed9thSVLTs#1Gu`V4l7+WyQ>wrcU>3`JSa4Ht`Khx4$sl1oAho3bxYl@*Q zwt{C|BA}fqpk;~h3Jn0f-I$t2FqJF{Y3j{M5oa0XSU? z`@eUHDyncw3+sQ#Xcg0Q-W11aIz8uieK~6L+<4AeYIBPLaBAby@Gy_?ELzxYc2LmF zv|gJFyX)dPXTk0%Y1nNF{~z)~U?+LbHAXDVC746n^s_g~2)@3UafEpTh^#S&Euxe; zZwHNfqgi?r$)F#q*Ci$>xwpVLQX~Q=$eP=d+@_;FW+qLjyuDP-QQjn#3GDW~khf|* zDHB<{Kojy1`rwrX;XCcPpcF}E@IlvSPep&x5to1cQH};bJ)Se2q(eX!@r;XVc;xd% zn0{zC0ItC|g-0Xr!6fPDFFS}NJ;n}~nwg}Z`(X}}-uvQd)qyOMzS#gcl5P!qkoPeq zsd=_w38GCUGJ>{5_{u}HcQKN%sVcg!>%#xH!OYQ zRAaBt)rDW!n}go(j^~`E3;(G{03v$74tWngz4soPlis&qdJySd_@X(``+K+Np!d9Z z&ROVvjR6q7uNhlSTi8N2u>X^rf3EYpPSRUiM+PY$Yn^x^_EN%!RjK*sdhc6hoVa|e zwJG0ft-eNJ3A#^(si76*s1=0e)KK|Qd17~iyw8Y%Z!A*41IlTT$C+;KxQ9GbAEo!G z#zG~#7T*>wylogx@>HVpW6KK8CMvFDT3bd$;2RGYKy{TX`q?^VQ~Jv#Te>AY%Ys=ZGEfz9UCd6ob*wR0;< zgz~%e`x>dT%DTgLltoSTmLbq9e2+@r<0l8H{wBhj8>BX-_aSx%TUF3`)Oy`NqSrwa!lkI|Bf{1yMCbR zkMyvAFa*RLxE#tP+)vaoF`;ay_K9#ZI4%l*eOrofd%~+uGs4;EwK*`Gi_$6$$GqG| z81z_0?t@V~2Pma4>}A)_P{H0~g+(p`SrA`~=fs$C)&=ustuK6m0f^PV)9T-C_0L0v zpJcW*PcqwoU1qz4%=W`4&CG0n{owvE+b{1*@r>^9Jd~AUwuh+X3})Ngu>Z`q<>G%l zv*i{NiEwk*zB1eQbfyTmCp_ZBePy;ETB)2fGuuO~u!y0G*`6EEISaGx{*JJXG233N z|E*U47_+4^sRJo`!-XgTItAUTr_y^Ev?Rh8ueJ7v-&J!4k*^jmEVv%1!E(|Ow-Vq3 z;a~pUNaLa}!>{5Qrcw%MQz9Hb&jD?=d4R}Qt9UB~YuR+KKOp6%7|@x6G{f?3p;Wa! zsF$L3!y-CNh|V6WYMAnue>hV=qrkO5=9qq#O4Mu(vgSPdqucaMoc$4YJ&)D(;Y{>) zKe9oUb-`Q#T-9Sf1x9Nbj8=CN*HfV*VKm}HxEYb$fK3XDl~*?FBqybvE3q@>N}QxC zk-FJbX&1DqAN^0NpH75t12*#eS*5#8<7RU!&fa?|-JI=j>`#QNsX)HnOB)2CdC*Nj!jy!Yc<}QGKYy!@d|M?W*6RoV^z#UJ>`V>*f$%?% zcY}XU^9c7nXAXjCvlWm&_`e*_Im_Tb*#N`_|F1Ooe~y?gFsjtx=R86Q0H@C*eEnik zMcl3+isr~Mk8o5RCwZbNq%v%po7z=qdTn+ukI`Y4+FWV?oKJ3L_{v@q z=a>D=*K?5cuH#}k(@C1;2YO4ctGoAg&h>gQW^1~RjS*%#lAiaq z93;Iqo^uwG9%=v_Nw_`WaQ#7~_plxBGc{@*$1{rPy# zS?K*d10Z@|Gqyof3km1|&j0Ra7s}v7Hf!r}+|eny72k})f+?dc(~~&`Eet(1(}4Ma z3NxvYvw}J49c4~UC+NxNl;0Gy4ssRB{jEEA!0i_$x#@@6@@=)Utg5_aRa?ZxwL3}x zoHHHtgKtzdE@O&C-)BU`w8;z3Ys|_@CHnQS0u$8r1obQn(iyjCa8I24$m zu_tIURGSKeMxxqe#-yRzL{v=`ZB9qEnW#2LGZ4)-1JTSGh-NmkBmT6DPyx;@LREFP z@H*_aWtI~-vsxXh7O$~tr4l*G?=Vd*(TdGO^p|hzS1;&hbvYH%k6zHtK&T+KWm6xH z03#8)Fe7905M9__pYsrFA~f;J&I@woX*XLw1+36EE><+ ztT_Drvsm(gcjTwXt!Gach*87uuy1keKH%DVC(*P6jGP%GFTQ9%M}ER^!cRUv#CoPz z8pqUn0NFlFPX#)1hmWLfh-tfy?DyOTAwpopwECm40bL?|xK;EVc^}@JpGd*!9Nnq8 z4aP!gsk>T&tOIV01z$|H#6b92e;QGoy&&EXROwS?jC*n>Gim2$`9)QWEoX|M=bGF2 zWJ?Z){);6sRR^PSrn!w`0}!kKQmg-$t^P50+mqb>NpAlnx5vOe1;cj+Zm+qJ_u{Cd znYjJWhxdouf3`WrW7@+)cdU|e`v-C4&=Z5(_dX7|{R!fBi@#vp?$LAmXWpD@3B?~f0AciAc7-WbGA>xl$tK+Pb7oEM7ZI3lKd2;oW2=E>M-_keGRl6E+-m> zGJx75>T>e%SaoT~k5SjmaF2cXzj6@jyYZaqVv###rbS(zZ2+8IxiV}JS23_{Kg2wNluQM*#}w$IG0~H}bbXsJ!T!jH}7V1h_sOzL}Nh6gqWLBlc zS(%+$U=K7nH{)Y2#l9N9>{?1N%ZFzxW?Hs1TT+%SpEzB%lQ&a42`jw+wdxkAw@fx# zP1MMEI%B4>OM5hB?3#5-3r0IZ+2PZrFpR6>CUupNq=Bu1c{8<>S;LDm3P%4E24*XZ z9H_T`QG_$srrSMghmp@VklFz7{;UZqwwab%NUd2KddyNwCHljt1SY6=VS%u23xj&v zUJYh}n*rKD15_=@UHpx5ZLq+s;Si9RwPT2HEQGjmW7&!>206BaW{CX5q_4u`f@V^y zv>B@y!dDji2C_Z>t&C`S4}%_Ib74tPYI%=~8`QFFo)lEk#jiT~l@LQ3h@=uR<>wI@?g=!*j#>4>V3_;2z}6iyTYnD` z8HyQo4w2J5B19nk#??jpX;uQ+ss}!w1!oiDqWP+-X@8#@+_dtnaOkU z0%Fc2nygJW5v|QybOk2E+RUWTj?aifvirmE1wafEDE#Z8L~uMELDNG{0ZfnJD%@uy z$S*YCqcF-uxCa;u!PD^qNt!a`5s~mz7`)QR`q;j@RirQ(^9?a4l5WZ~rv4WE9x##AbjGwIX}!4b*`G4*`{+f|xt~x@VLu)Y zPw6Ra#xLx@bg42|k@Ql(-QB*3r1_RPTO|FcEJGxnZn)+WNyQ?{iJvs0WQe5lv87@6 zBdVYDRmAYYn4SLu$x)@i;zi2Y4=N=k1HX?<5Va`KS)SPP0s1aCFag2zaoP(A&PCxB ze>S+|^RnL!O-}y~(I}Mb<+<{GIQ`u3?=NdT3qQy*_L7W(pOmq=W$Z=g`38FI zWb9905i8?K89PTA+m#e!`NzxHGdv=av7ddAOft+R1ZdQG)1nCX*;ZAi+4oVbTHANC z@1|N&$jR8305KX)k4zH517!C7;WUR}w%NB`;^gj+snmTi`-W>$*pG)-18ZVmB<%N5 z#=Zb19)P5`&0NjC35!_Gma)(J_Y4`^Z^sAalCd=+$`3wjM9Gk`j}MV_**TsY9b}Qz z`?BCMbfQBo=%UQNLmvw<4KV;N0D^ubsE?Ic#+h6twTg2DgQ4AP$Zpy(*B5~ z!wfMelD=T)fQ9eC?*S7@Up#SIk@QJ%-}9=C`#yTJ?}AF@bY|bkpY#-d1;6`j_N|3| zxX&W#Fw2}Rl798P43Tt};hIY%eM&@mVU-ajLnP7cy8~we`Dslv`wp`ccxN*E`s^T~ zl-aj5tc<}iWAXdPtMbGjwj&L{znO8DG9N3_;XFP>q4b|UiM;$=K3BIhU~pH?P5^N$yi*L>I^A`v-)GlmYB)i(H?{SlGjhlH3DkrhCU zcF$TNcz~?7GdzOXR@>Jl4OVt!BI&g_KL(k`thQq8U=3A5Dbq~WJu52E&ATlPe~M#%y!B_f z4v*kWYqk9ZnNU>9`m;$t&F%fi40C&5nPF~^F*Za$*W6xWhIa*frq6fX{nNjDWPJK} zC;cho-G(F=h#@e*0x^fNE-DHt)TS?Khiox|V2JA(2ctE7gSIeEd)8~i85e0e?S3x+ zVf(%GE6Cc)9TOVk2m{l`wBx{G_4i7i6>Z73;7~4GdWGXN2o^(_DffeOg-!6h51tM( z;ZE#B=r#_fSWt{4#Np;VqtihC#l{%o^BgvLjNqN**_=2Tk+kVba%UR16U&BS^^a7P zZ?0uazkaViN)Kc|E}j$EGYnHm=Gc<$CIjHQa@0hFJ$dLZ2tvzfD+Xsy*H+xO^58Vl zA~n&??{jrO5KUwt6CUK;nrP=eb7-P9@5#|bSH*MA(nJrvTL3bfD5GT+xjfzmTUDS<8GLy=bBpeqaILA-6*>5ZIrYq( zN=PjHul%!*pt=NH2qF=_KQ9fJW+Zy(ErO^kAn^?$>X{IgKwOIWrm|Hz4VO0M)D=1S zhB@`joJv5uZ&tgn#_OKSHMm~QcJCZyySL*}?asH>?yGngKIN&gc2|-ifF6-vlMa0D zaqGl=O{K2DgKvnBo{5hVT)VU2a5HdFyRYP@?qIboy6?udrczgc=wcdv^-NGoz>TdE z(K_)OT}@%brvn6l8usFsi+uFVMLtYmH<{YWI~*^EYa+a=Agz7+qF3>~r`enNhN$%8 zmxl;g0^4Uf-&77Nr&VHz-`HNu$iX+vsZ{1vLSiA2xpJlDPlW${WEvvF0%xH22%N3} z!#4z{XM$4#5n0MNT9e}k=a_QpiX5TKsb}U?0&Z*+5giU9g2BnFi_`EKN1`ubLQr)D zRK6iTdL~pQ5T63R(aI8!&tB!!6*(qdPCYZH5*%SpwET&1NBU@{`sYC}q$a5Ckl8|f zLqwEHa7rK|i-gD`<=most_iTiZQ~Au5#+l|WqbRQ^)sG+bcaBd4y&!8gpQXXaD_Msux3^CXUy?x_SCQ;i(W4-9ZL zFGn7YX1=x2JkGoD%tK$Iz*SGH`&cKBfX@C|FV2EQ83N?`j8s}kobr?t;oexn13n3HdqQ>mlg? z`LT&;`si6Fa0WUdaJm8v-w>Rh2~G(_WKf8#S58A@gL3MM9DKu^dS*@~cxuA3a>JQ$ z65%HfOQXz2fwdwo6IfjVj&BH7&jhOkBGfO0E>})NXp?g4iX42yoO)(XC8UNk^C!aF zk4Qsgv%neXEdr-2!0-*h>6ze^Kty_lNQrV9B3qSHSLEOu=F~HDDj{t+6GS4s8{w2kv!!DlB{u#ccx@omBJj-~siyG%p%5X}Af#G7Qf*x6iCnF$N}F=EB3DeOVunO` z!r#+K(Vna{KpkAgiL5#}p+ouGkv~~kr*b-dIbB$1$?r1G*X`(2YgOUnp2}KWhuB)R zKP5%Dhi$TwudKDoco*J1^?&R?Mi?boS&8s}(^2g8IP~$XLloW1D)tG*UQd|ra6QTr zVYUK1&P((N58xyP=IUpz0p;rVxe#^%riffE27ruw*IpMou7QRQ{4dc65t1v?%O#U^kRYK$!AT4)9 z){yzfls{BCoAi3zmqY&*%Ngf)6Z&pEy&PspgwIVcXA;JT0PUrDhOCp!pE~F1u`{d2 z)LkxvJU6pyFT2a7IE!osv#RCcSdZC2ox+<{O=;DVt+cOZ)#1QF-6$blqZU_3qH^lH2|vuYWh z!z+Hwc5g>wPP3}*p;)`G!dGZ_B9I7M(reOzM2}l1?jMa=^-SQPc3+8%|5&qX#ey^` z-=|s`TK%e(uAna8kji={m6gEuS*}V9D(4p658?V~&8pYgnNYrohXu|+%YZU73JCBG z5qXTws>9N~C*#6rDa$qk%C5kJZ-~zXe#s0Ev{`j_`e@FR?o%K{7UKS(npGG5F>N## z2$w~|Wr=Xn6~y2h5=GA>iW1mc^7Qpm<+R?iOgVK$4!&VdJu{~gFq%)%Xr6=!F|%q7 zNAss}p4kj$)o=bD8_naCO5UuxJG~|=gpc92Quyc!JotwA=$ZH^A#PTk2OKn-Ly9-q zO1>Ab5-42(;uHr;&jh6e+#E2o>a|m8?XwyMn#Fan&8q73(X&p742wPq(L`6!gl|Y* zJ(DI%U`H9$*XxzjI?4v+)D=1ShB@`joJ#Q2%rvXkJd#G4jRI>$$bd343gGyLU>_^9 z>Rt2F817~v(yzL1!M!u1fB@eR5v8(zN+4x=^>vAI8fCUBr>@AsH_WML=2SwOCP)y8 zuzWO)C|3)jpdTQ!YMsVx2MRN@Y9q(&Z@*7PJ-1o)f{ECGZ6lK2tUA#)Qg$P2u4dJj zQI^JL3u!jHS#_Rp%P^~+{j%xIs`@kn&eg1XmPe{VNIhz^s&6FTY{3CDt2V2(s?=IE ztFC5iz4&` zzL0*yPhszM)T+Bs4eXIt*vRg3Xcq=0^wi6}U)#X$MM{lrU4$x4@;!c)N=B)KlnBYEl@1O>IEnB< z?sFcqf4szZ$tbT5AZ&{MkT-Z`eLcB`Qi_`_uwZwVc+z zudG#0U6JElms8Kosf3h&oB0!Ap7%x?BI}UJgH8yXt^mh3L`2U7rvxHWAw@VPvO&nDrcEAZeO;-hEcqlA=u zoB0#r@6$)~W`Q%%TLey5fZ-d0(=)*-frKd$A|=XcgxRW`x*`YPFsGiGQweFKnIID3 zL-(c;V%|wCjZIwT*d%I6V_HumOqv(Vo4%th-ozlbj%Es$PVf4lOW8+mx z$x4=$2>zc(smvX6o}Q~hx_lws*yEnxb@97yeb?A7h@{(@=`*;UPuJ^VU!y&4 zT)#pud;PaVHNjByEzk79?)B)NL;7}*9(zn3m~qcd{P*ySVgBOy`N_P+*M1WU*l3>r z0)!Y=TqrkEg<~AyrP|H%>GYBpPe$RRm|jKnXz|`C0fb?MxW$tqAXGu5!T91&bUn2n zJ8q@|Q!5p&^_2@W7U{sp4jMoYJu%$AaQ>PFB`c>cK;?kn!ZWcQHyXhD7dCPV23-RTx(4WS4FF0kQg_KO3>IxW6alw-+MDb3hq7L;R&MlF zV2SI$ocV~KFnD@BXD9@u?p@5nDO z9?G`;EwAM5W!wIqSMoyQa4&)0d(VTIHFNW2Ve=glPWIx5_~@S7c3(ONMj*s{gI0m zfQBvxHl%}YDkzI8q9FMS3zF9t995Vg&v#0cDM7ksZu+_mMVZ$&w&`ms(Va?Ux>!)v z6L2F{u)f;Dpo;qp*P3=@`wZ8P{_gh5tB8AqX!+#4ZTXfsf8^^6^76vQuTg!e^E2S9 z@OdKq@*6ZQ?+>4;r&8kfK&2LV=J!g^WD@p2r7niPXxl?$f7?6HRY%lxd|min0EfO} z)kfJRM~`lZ;`<-cD1O^oeKOkUsoH2$^|sroi}i1=!PI)tR1-8o>CtY=EO-0Df-2Q- zBt#IYFJ%7W%8!619$cGEvYSKFf$N}x0o?>M=Ru4Au+vnJv~s(3luj4*3}{Qmtw!DL z`2{?+RC*|I0O>AFgg<{!UC$x(x(K0UVqSGWRw&Ht|JfuWn1u&d8mKp64iEJJi?7+S z0XH^Jj?-~XIX(w`xz~D8FQrQ_+Q3Vz=;)t5b^w3$PoIv~?bD{plr#QhSpo+$^2LEq zX?`82y?A(FT0@c(LvA$%)^%t##W26ky_#bFQ@B9mmRGnoP8H~np&C|2SE6uNvMfaO z4MZa%F%e$BS3ajI4YZ^gZ4gB|3+Q|ZB8;dV8}TJ?C8dlSnxCh5_1KSEeqgh-lE$X!`IoQ(`7w#*2y1p>Z zo=yeuX|<@+)TGN_`p?0hR{rT2IKUfP)RL)CLVh7p!I#2H$^ybJ+Ex^I3@BH8P=Z48=g(Y{1esZ zEEKptIf3#s48|*HqNGg4)Zw4013{LR9A8t~TXQLN;e1ta50(M_r(vI0weYy9V9)3; zdjhG>P?rmXr6n)KZ%uIlyjgI3ElzVn6XDJ9B7#0u z3zAn%Uh+m~e=iMBy*ZQ6Z#XKA(9iv=e@uis|6tr8BKir){lq2up_}%H=x<5Sos;OF z%1!hRoc)#FyYKVcB3SQ!>K`+D_qUPbiA(4k-?l%5elR_EPC`%9yI<3kN$9JW`0gw= z()0)ah*4ydL#Z7!0_1+;5`EM zE}?II>;4e>n9I|0=Opwrz5Crb6)ByK-1PJ`LKjTfIB@Qc}J95#)H{68hfD_J`1Cy*Vv+PC`%9yFc-n zOhT_p@7*9PNGlKyNhr^;Gqe<^Dnsm_xqo<%EJ**=t8Lnjv#J0V8A2^)w^TPg>f-h)$1>E_o zZyR2KFB0Lk*Bb&Lgs>zrt1<5i3V~k@Ga3jn4f#JX`1wf0m&2Imzwn|&_}3K%T?A0H z3v=OvF@V<|dV>}k6agr(_k#{Vy8&=iU6j^kZay!g%iPkQ(Pb`t{X=#*+r`(6Edfax zY@?k|7;j^Hp#)3a`M$w2J73pMQms}*t;N+k+7;)YpNg~9Ym(iP*m9P`&kSqszI+!a zr1L(I-=jzYl4$gBo7OL?w&2|zoC$a5_Q3g9$(Rbz#-g5U6#Jav#k*w!jvHJ1nDXUW zsJ^aPek+iKgq^K$#S&~>)j+x{RBFj{Yi?wEO_JYt;J=G2T6kCW`nwiR>C@3Wu#OjR zK)k#TLijc>7Oq{rgHG4ohpa}3(NL0Z%H20IM1kJD;dzx^iz^RfWJ7U&DyBgJ!sWX* z5#l!Wzy7Kr$_}k|?Y_CQE zF2d%<65P{Ux|0N%+DSaZ&*y8);-MrLI9QDN?q!1xJwy#FZo#T|V!vX7c&@n%I;rEH z6+tboh8VsFRzYnxN+%@3ghMH)Rao*0l+MT(#f3zbM?wU>NwG1AooRB=8w9;EC-gu2 zA>3GvD4t6zYKrTvHpwOZHS=pOT4?>J+Io$Z>YAwHHE91S;W2U%semDr>I*o7d|R{Y z1@ptTzL;iPH`x&lyOoA_F;HpRuSM@>2&|p*X={PSDFdXhdK3*IbGN*868_ zRS~}g5s@t;A4WrZTp$G)UZXZTv0svoqK)ib<4LmN%plB0;gm%9>Ej)hLyD10Au<-F zI1FUR6;I7Y<#1^Y)wl61PDv(Ktu;5E1uR7h#E3iH8pm?Fv$DhW;2hB5>=BaHB<+pc zg%70@WiZ2hAnEvoU%_0acIgo(!tk<$|`D%uz%)qQ!@S2ZlNKdV!=kPex{`-g@}8U}|M1za;_NTK#wt+iUuMylg-F@p+hZb^PHV z_hXbi&zGE|A0JY{ivKXPKi__%`tx1k9QyE{x%ABFya zfKq+98O-S*^J1yu(z#>2IF)$ddGXSj`|zvwvkw<1!fzez8tCBiVw8NAFF8jazLD04 zVjIMZpLT=e#mlX0AF`6a_gWVR7ar`ww|*JK?$5Z7SLx#+nIc0;LY#qZ@0?4QKkg&3 zUOS!oamzDvclmpv7DMXUc$rI=-{=6jE?+*j61-ljTRsG(7vkeDg`+`>Ov1Y!NO?ad zic05?9wicvO_he>Q8xUCN<*x^fU|)MrLa7xc+c)&II`Sp;i!QJ=-As2;oZFO)zW3HB+=W^yRjdx5Z{WcCkstx+b5D_;Tw`g zsicMyc*7Ktg()J7eFL=Y8{Dj5Zd*C6Yi8Ze>gF}ZPL(KwygF%q7l8@NdV&g5M=J`0 zGOmrOFn5lvjj0&@ow@U5lGj4_=BnRX=z>~OI07qoG%x({hiI78`7fb5Lzi#i0u>~; z;y2Pcu{xy1tC-EyIa{z?Buc0WnzekT+3B2((m9(_I_GNe9t^%Kk4}Weo*y*9INyHw zXRbPY(e`6MjVrMLAE-|*`JRk)e1GA^Q>8FrlG=_S5gz>$xAkEGDJk=SHVfOHM8UG1 z3t%yD*$ycMt7U3u0ykK;v;65|Hn5teO6$VTZH^_GstpUAW;cx(n%E%F`;Q*^9ArsH z4DFlXj03wGt#O?Xt9NZFZx!|ZZm7IkxY+F|&?yRZWm8~TBD~l@Y1K`Kf#YzbP0=Q! zp_kaegy@aPKUh;d;HlkD@(u}%_;zAmDUixwt{>vj>-TBetuLd0p zXx#&irK0Jua2SKRK^(>ppxNPR2?AW?ageCHprfXE$olT~B^X>B;Z;k}9nct9-`K|W zjqOGWSQKp|S7CrmUC=i2UWq7lX?#@0k7}cjsz#oJjcKMXs2ce<{Q4G~pnZ(aLMu7W zhghKBZo^ntK2nmls|JH6^RHYUzVIs1Ev4Q~qF_DYm!|e|nA-nygd?tO5Ef;|2uqV^ zdhCNSDCq1tz9Y;@5I@cIzRUqm$-eOW0Hw*dg;S+VFiesGA{WOSv~3jd;UoPA4DS5W zgBT5P9&jnI4t-f3zBP^r7#P+LXIJO`!)K|^v2iHVS7&c#b*?wSk)W-M1TF98g*_|Ok8(66 zu<+&v+;$A=%YmL?a7bT56AWQa`jQ>=<}QA@Mqjq}1Z_q7vQ^8!&?+}~>r1x%&Aqtwy393W zy^t+Zuj-TZ(Kg7b0{M_@m*I}GBx_gE6IAu#4xMik;XaNp$)LgpM{Oef;3au^*L2sZ zzV(n|s&8{m&`e>}#7VAZO>#BK!G?OaByHblIe5+W#ZNPKIqn!DQKVV)NClXD+>?e( zLrx|DV100gvmb&c@e{oG6JBnVeD)jIacVq67hgh(v&ZD^`FCDiL6! z-}}C2X7}z&vJD@73eWS)CoseFt|YTs@f`ZKT;DNt$fc0q)B>XX&b6@qdlC66STzuGEP;TkSdNt6*KE4Jq~ni zrEbHYi}XmcNpGj5_v=>_qz8T{J^Si(!83QsqWh(hnp7L4yy#pUnHts*0Bv#_2dn^? zMl92=$3&@;v!^p#B(p7&*;f2+{d18SNj900%~ziLB>MS9JAF+WI)iuL;0Hr80i0mk8sE|;;E2?XU7M{AkNnB2 zn@j)+Hf1A|v0%scg0OmI0*v|7m;kv0PGbTlB%vLW5PO5UKY0mhRAbxhO-5uh7Hqht zAR{vY#{M5{0yuG1^vNkqK>2%UK-rNEs{5$-j$W&itf8UDWwTG7HuE1|3cR7BS<({7>t895o^pOx{2s}L$ zedKx3`T8pR>q?)m(h7jP{ZRCw(f~N{4>IW-!atFDCIN60u&(qK;B?c!w^=@BZgt>o zVE`P2j{vyk*fEI!IG)pWBCK;I>d?n+lc$wLSDZ6?Bq9U6|+M|JS12|CknKZ9^ox zvNP5qXd4vkOtt7W4g)++OU6kqrbYMv_7Bve+pXXqRf|#;xA+#HD!XOV@6#8-yyW{L zGROpMCiG30Oo}w?B1ugQ&$fs>@=$RR?%hLS& zF6+tiebH?0kJlG5a@6{wci3*v-%E>d_!YHieeQXDh^z;Yc@V3~d-*ZY&pJW-#9{ip8);8)<{laY|OsXy_x{ z))ohebs;W+JtlWBvkUHGF5B&o1s}2ol>3PC&vFqZaw)q=jyKKoOjYKQ4r4sHF8cX+ zw$4I#D*xO#vXM&#%f&(p@F*9c!izl`|x{d?McXiS_lH z@cSGb7x=uqjBkns&zlq2se_ORAZ>-{DX({1^23-J4d*U)NOKhkH%9fvr#`3V(YF<~ zHyE8ZWukSeY`sm@3$ZO$T_@dQAr=&{SUBew3or2m?MNPg*j5pq? z>b@i#6xYmZWL0# z{yYeM=PyMGhwfO#Vdngw0MX5OTfls(ZUVvE6U%Wp;RNa;!)#L8*`~(X^WIY6wG$s= z!BOAXXVoju9NMyCv?cmbyz!yx`Wnm=nu7I}cSE1J8zo%&Ln?jHmv+q|RhEbxx}ba+ zb)cB}L(vB}KMRdQt^D}I-$~XDbG!i(hv6}H5?QO(%mK)5K+)PAdN!>(BHE>%(^%}t zL7a~k`sRXVw<^vDJCh*wajHS?FEb4bvVA8V&W2owzeRpFLTK;;-1Up#e(M6Di6WrF zO`wDx0*VS^%3yS+On+ugS7&OXvj^)lOuN)pC>u|fh3e)@_z(-8_}@+sC0%y%rX>%= z8y}D!KH&6l#y6Xol~@*?rXG$z3Se?om}vqX`nkj5$E`HP z7Yiog!c0Dx1b5gGA%aL$BwgjkX)Wx6TRgYX7VCmr*b}yJPU<&@G&Qy<;=5J6A>z9Y zl5b7bwP4v^{K$PDiWw^9=OkVIx`Lz7Yuk++`nB^$-E{=f_Q7Ze5y7Ed6K!X3jN4lR ze%8-NJ90nrN56LF2Y@umo#du7&rPRsqd5W%N~gl7HcRsR@#}@s<)L-Mijehg*iy%N z4?<6)}7!i>O|JjkWP#@ zHI7RsxGbSv0OQaJM!Im_i#one2u8e^Cp=1+2rY?WT;s(YppVtCT4C=HGq?Cr%+t)f zxR}2!hQBytVz%(Hy6I&Ya?Kd-rn$0)$6@$5-!KzwvctEw!kEH#JnF{Bp?7t|qrC>` zpaIH#p(K5`L%=PN!>KF#(ZwHXL*!Grh0ZC|1yzEvPajsbuI!t-MXDZd;B1OXMd<%9SV&OZny^Lk>(NYyj_4Lq*y$oD%$!UeP#Dbr-=&QZbq-pEsHbBI{#)ip@ zg@tfK$=7pEG0h`|L$~0Ox+q){O5nZ`(t_}h_Zk3aY_>YPfaAlK)n9-<`NWnLxyU@a z?VqA?!faz`kdYahFtbb@ijHSmWQH)Tg$W#kXLKfbx$zT;Yxrt=F|9b)hO9WBYGg%NoNp*z!Tj@j%Z(3ednt3< z3N_7rVVh*rv3VXo%7y?43qH67cARP6aRBA)f|2l+mz=;dkwqM0Q~yK|*R zcD1tgv-uR*?1RW+wzWDmpjeJlvEZv1jG%(tCE#XcB`s_OMKDWKV{>?jXJu}8WpLOz zj}?_+j>Zqgw?aKznlD}lbg9Fnv#@2*KpHdkj}6m`E&SR%Gj$~j;Q9#`OAJ5;gNY&h zwo*?M6-w<_Y8JnpRL`O9RL>UZcG@nTN~>HftqW_>789;*_o0Lf0EO{juV2ggU~4Lp zK1^w|b=0DDEW_b=kcD)oCHNq~^R2Neq9gs^7jJxD1ap~{sH=RpJq-f++%;}-8UpD>w%A?3v@gUX?`I>Ky=TPsAcLTex6#H34?lNdqN9Wm8`*-Eqke_FRc zCv`8B6oiS;42dG0i1RJ@uUqo{7~{`eGS`s2I}uwdt{shaEm-9opt5Gn9ygfF( z+b%Zv_Xl!^yb``yBIYmlcjFf^=J=Ho{uS87_(ekJC$EIN`5e6KW~YSP@hWfZtlL7r z++ttPQh>j9RnKbNG;4Z@kW~m9-WIQib`}DrG;j-;9-f3A&fz);Ob?}pyM%(Vj>GCi z4CN#TMG!wDd!0%Lf54~-o97_u_x#xPo(>nbB&K!OGxcyA@Vjf35-~hWBus=JN*Z=U zQ7rhoc!?fvu}r*LC>FfTzWSSnW=s!1`SOr9Q8bL5EY-vHKUhQ$-yAMktcNqDdieA2 z3xG4M8^JTiBDLwm^j%Qd>5%w}e-`lJF{IfP^_L z$Dft_6P$CCQ#-zLH@w|+K~qpgQ_xOR@G^WOQ&nK;;0?P?g&`B|H?j!^4O+goCKh6|%omXTE%7Phqf@qoHky9Bn1z!Ln zf2%?FM*?->90I5d@8-Ot8(p{|>$axTt)>(1cbgh})rHe5r7pY|O$S>Ux;abZl!Jj* zHf}()tjT?&B-h6d4@fxYa;=9`DjI-j#`WUp5!H($3A43Dr*{8G;=0Ol7($n-!;Fd* z&jwUZzU;aPjQ|cwrCJj6XcuYy+L<7OIuJy?Pv15wLRN~v;?RJI{h3u`dgP!}1ioSt zXN_qmNhjh>UEL~O+WS)K5;i`RrBxidG>LrpGsZu`zrDlh5?}K( zo|Pz7q)Vk+3OGQx?YoQU(l@UNm4r}2y0l>Kc&!0&9Wza!#Vp(Caxg;WLO%>Omh>>< zRQ+{W{pDRbNUcak;~41U=Au$x6Wfnnsv7b&6%w_T3KP>#^lHQ-NbtzKk?#@sv>>?o zhGul8pM(n(BJmV*WVj7VfUb&l-&Lslo-_3lH9R5rocu8SC93^0s2-3^y$Mw3KfO$! zrd-RVn~naV^x?N46TAB5pzeH6-7X}WkEuj{=@_DEj!1xi@L3Kn6ucFtuT;*Q+@#dO zh2&gFgkAGaDD$YE{^;_NAb&CB3p$;@P4ybKrQBJ-60NQ32JuPF=**4{4 z!HzSvc?E9AB#L1lxLp7?qCw>-eqHMvcC8ahLrb(ybdeY;?S9ayd<$G#XpwMn*`+^{ z4E%qIyTlhfU$o=%4Xvn~H-E=z4l67iH!d)S2yGI9o9Cd3T2|GjkUU>H{b!n~a%VtZ?v1vA$@ihhTq<4spStuLgcN z6wUV^D2nYJ;gW@Kw0P`$izXkxfhUqJ>0_`{nb$2Lh}-KW&gN`o^ZgJ3R(8lI`tvsV z4flbWrn&Pg6Ys}I?94h8T}j`R_4~2lU+t`BZwA~sF5lQv!X6go7O=O|s4Hgg1L2az z>~YFa#NOi_dz@93)La&|NzONe`poVnIREgCc}04|5?Kyf7An%-C9=FSpM{E4+5BND zf1#6Tvw^Qy5)Oa8+ZP6jy3liZiLkULRx%NNHhky{bm2|mlEuPWu;cD$-!zHbM)I7Y zXz@N+4iSjaqxP9F zOL}tXyU7?t>7m#jx^L(bw~MtMg2Ug^K05=GpGxpI)MpnGlj>7pfc^1j`w7X6q+qkZ zOR38B1$%Yb3A5k3i|Ekx)qg{h_bgG?HaR*7jdCZV`DHXec#@~jx$@wd)2sE<=Ge1= z6h07IxVJ8{r@Pc&_qk?Li>&!(vRj{ScTLb;+7_2deKGQRlbRWIv~NJ74K7M5LMF9Y zc8fPCLbsYVrfe>ln%1VqR@to<$Vqmq6?O~O17npI*)5WGs>MJ03sZ6phAOF$Xq&G5 ziCAsux)!mmZKAQwXlxUWZ3P-Tni@MqW4ouZ12ne7gwg9q+saI5YpM(%aXz4-#Miy%4ODVk>#EplWMAzS(_QO?p9+YO zTVdkZzlg>9m-{5#;*M_W`Js|fg3w@}W49uU^>+qfYBPcZGVfhNV&(skH^?xC=nAdv zW#K+-M-jO3sB2im^tv{rWlW6mhTKpNlV0f>lCn$a+CFRl*1S!PFh*nym?8lNwWv;X z!KL7j{z=MOQ*T>7vWZmiHY1j@)(TS5{3>{*eYNQp=fg61pW7Ug7>$ZnQA-To3q}@^ zbz`_>v8+c+W&OLa3Bc3{2S43Q$h!0I^Rh-S9SL3l1RT(69f+Y6YHGzp4zXmraQtHg<~0UIW5EZ)C5t(vpR-7t9`88(*}@i;#ZWFk{`vS4 z%zya$JoAil3|<7>+OKE|$LOmbDcm1pW`BbeZmrSf6>e5*{N=H9ViY}mEa?9}dNcN3 zeASGd1EhC9uSA-Q4UjJU&qeg*%5ceIX)YKbef6s*vMzS5MZ*Tos^kpzHhcu+nR__z zE%-j1J4GGHVk4!$GaSWL-V-iaOyq)*(pm%H*GEArwtidSnYYWK{-;MKug6TD(mAz9 zDtc5nKfw=m_Q;+F^*^ zH7s$8yd#6rz9DJSAMA208rR^s6Bx>Ir~Ws9TUsHauWRL zD@KQJmVqR7SuV?Pv~UnanMb8m z!W$)F{)Wafg+#1@xw(RZ=lnn>RI9@xZP-W~7HPu;W1uCWw_`O0{il&O3erYWbub1a zB8_8eYz|e;jCov|dPDif3Xmq~@xz2SI^oR9xHBtA8e77w#3laAd|T{5_#?+Jfj?@O zV&V9OiwK;s)^$l?I-xLEe%UF^Ew*4~i~Jd=jlTqVnm$JKqiUR)G4*OO%8`?9K491~ z9einz8@Bv1^PMHKeB82>M}HY_{AC2Hb!}dMjDee7Ul0Y*P+h`*Pe(=CbjMc0c{wr@ zG3>ZsotK@RJJkV6WX6{u;Autxf~0DS!E+$&!EeDcY=ZNA1Sh^822WRV=D{VvpV;j> z_WH}X=zzsGiyW9czu~cfINvZEyy6>SXgO3zi3nW#%?)HGmcX*B1k0Sqvdm$b3(opx z7)xRymQ~hE0L%B6!19~ddtP2BUQQOUTq0gh29FJ639af|UEXC4J~wEmXoCh!n>ItX z>O}Kh@up}6mTg?ennA7;iJOoKT8gGu4$WE_e3cb4z%yKQj7w!=2OM~Q>shm9)ag^4 z`>=Oy&YyS0iG&}nweq~9Hk{#{Pk<{?KG;?^G>n6q*}9@F3qzQD)x3USEk%c0#fcy7 zHjaIZEu#34ep?bR2et8I{C!$w^S`2?z3i-CG4&J-iHuw=HkBuF>{)@$AHleRO*n)S zZ&OBYnNVLwNyyl6qQm1t{z&I(6(R*cBL(>N>k;H}6Y*I7Sg`+14joF3cp&h!jPlcU)cM18lKfPiGov#bLN3oKFD2h1da0&4N|KK=AsW}hiBppa7K1b9iMf;qrSrO`~ zmXoe^S_Jcn#AN`926;LE49YvKW{k>r9kNEO>X1`P2_H)bg!%%Uc32%b*z8hJtEM*3# z*FoOCr+K}Qg?gHESLAyd3v^aq?~`I>lWwZEJJGO~2R%N{`G*egCr!4>E6-SNl?85D z6n6NF^QyVPWeydrPcp3Nmh@#|&-4v7+$&DVhFkbt;XFo2gYF5nU{>WJRcKT2td_*j z(b>e0@%P1*?|wG=)5^P*hRp_(un6-LCa7g5oV<2UeGMf%7;R!O3#YjA@RI8TqU$qX zbaWl0Ak2lPn-dDVDg4a?w#h*gVH)64ysrRWHH^56aN~koT)lS-HM^Ob-6GAVQ!M!D zvpA<}wQC6uNrPcas?2kQaE3`W(4x=oo57C-&$!k#Bw%UtNMT&siLQ<4+J%n(Eg8ht zpchEhxfM670qgeBr+P ze_!Wl2bLa>6n3MRwD%BQuh3yiVzhS$GwT+mz1-7_I<{61A@k5Nul@XcR{#N_cJ z9@?u7@XoB$T8LOVRK(g%>}ub^orF%~P`wOgRqbsB6SaSC30slm8ATR*F>@-@ zu#j;%k%HJYj&ZXO2Iye zsop&yO#3cEL%$z9q?N5uAAIu#6gOAglZg&w!ax+i$warFm4ZIFC;w)HKlH&$I?Qao zr)BUW`(PD4%24AVTkBo!cs8K$1sA*=1hVu!qz1@Tv@oGK_GR)*=4a&J>^{yG=sVS>jM zXiUP8$sXhgw7HK@!eqdW_O~Nv(=q;PH)f0v_>WhhF%g1il5O&^>5+Vddxd{JKRJuH z0neVUjZBwUSVx5O6`Hv5cxcPtbEPPoj=CCD32;g%1>!af4u37q$NVzX#Cz=~B=|wF zW_q|*`BWCFxyS}X!}gVX9JXTWdD)$oan!YJ2WOs-9eC!{)ndD2R$;N=u9s?P;_GY+ zu=~2Cr_ZK1GEXHpYO?yd)tNVSTPZ;I;v`M1s zem_2y*8THT_s@qDO|6$%C@n%M)O|hQEKbelV|sRVuOe3W2b51`7q5H6_O;JBY{k^8 z?g>J5zX6;%$t5=8+3KFDsC!lgPQ2b)RQCs2RG+v(3je?d(>QgBbLwJmeAt0xxBcw= zdA&`o21t`39eUc%QrX<1ieHCMn$M}$wG;!`rSmyVnUt?Db(j^~bbPsUYjG5+#=&=B zkM>!0_h~xSmlrdZw;TJlQbCudRx0{y=_0G^W3V?@D%J`^hpX#or^nev_Z}UCU8VK= zeAVxDcbmkcT_l_yK^I2eor-qLOZa<)J{ZXJ9LO+Dx~j5A)mH^d9d(ISc(&?eDyokH zjRn7Xak%;rBdT<_-xy?;9BQoDQ#PHbKw)hJ&f2D6ax}m?9+ErV-gfUDQBZ8q-8(9I&z;L&av1;3GSTzU)0z7?tt^dXpew*rs z&X_4e<#C0_8KKIcz0cJGw)q@H_Nfm&%yz}crtESHCU==v25$|F843H ztd9yd`>f+G>x;u#Cz={3T-J+%NBOK1E^7v}?hpwKDR-G49ZX_Bqr^4oGN}}N zby=%|dwkZwW!=TBobO`hSq28Rd-l{$NjdPCHx@j!rD(!w0G66?7Aop~<8IN4y4!#A z73F58I}qM6n22HUgUXBJEK7Sr8hRJisC`AP!uHf64IW7RVkJq>JMfDRg}>-;_=Pq= z@9b%mz(y~}d}6P1^Vf!h$f_ia6n7#Ks}1(fc`FmR;&vAwbT}%p$AVAINQ*rIyO8J! z+l^-!ApQa}zmOQclNcq)yRNe^>2-O@OSNQUizLlIT?O5xr*@x!ZXkffeu7g9yq0>_ zF97ok5$K%=l)wkd6TVse%6~#p!If44FD##euTF^t5A^^N?Gv;I&rnGI0y4i4gWd^P z349=I42bZH#RA99s^GvCVRoMA*@+_?!d_LR8NaCnQ!ozHvwneuUx-Za#G!-&JL~a% zzG0OK-q<0?Snx>T*fFTBNc7m+@Qgt%e*u|ah(YfJtOPy~b}2ingHLV^v-9%DxY}t) zW^}G9(t%&N3-sKnXZ->RzYv+;i9-nmcGlqge8cK6I|LaEp6%H&s9i|(*t+oyR|tOr znO}%O?*yy_J`i>(JJrE=UJ_;}eu-nJ2bt4}l`7JUUwC2kd_>Rs1rmNCGQAUr5(@0B z!uR=x>M%P584Gs(*wv0f?L(r+mccUuO8E=O{6Y+RCtxM;fv`*2SreRJ#Lj0fcI@;c zGdevL$>JBmka`}_vwneuUx-Za#G!-&I~Djo->@dk4nf9(fBKPQ$Dj@&(PJCNb1I=< zK;{=>&^rMufe(aT%Ffzg^NYi^^ZhEv&WI4qon(NxVH6NYU<81xIs{6Y+RCtxM;fv`*2Sr`06G|bMUJv);^ zFfDchAz%u&D(P9jK*BFXrg!2{LV=xGl%H={7iNbbW5F*cUF{gu8Nk6lCSjWu2K@pu zzYv4o30MhyAna0h)(0Qj5@u)1qh0OH3BiPloD>44V22*;C?vyQAmJAx(>rk}p}>L8LbwAAr)C81WbXOLC^XH5`G~vy%UEL3ha!CosD63 z2oiVATL@k%VNllrPC8-O)(eAv0hwQjLGJ{t1U?XUDLb2k=Uf)9oo}sl>}(K%eihj$ z1WbXQ*Ry_sgkOkE@5G^m0y_g@XLFbxg2erY-*dHNP-_7voiJ=$gh9W6%rC^CcLG)d z9|*gYo!a1aFAB3$?%CNY1V>b4n-DMs#r3RTAmJAx(>rk}p}UO|MCk)#TVbCui^9wQPoq(0V2f{98XG`$D+AuqtDqZdD6oPIQ*(C%_LA<@5^$R5Y zLS%X;4kZ-W=@mO$!t4-aEO@ME$Dr;7oOHsl?Gpz50y4i4gWd^P349>zQg*fm11}7- zbNz*mo&7@4p(6D{z!WS9>sh}*!Y@Rocj8b&ft@a~vo*{PLB@iYKICf0pdJLAbi%O3 zg+af7%rC^CcLG)d9|*gYoo&H?zaY%c2ec4{5p}Z=w5mvp5HQ6%$6J{KB>X~TdM6Gg z6xeAOJKMtS5G3ZP4?1=XY8&9B6Naswux)J#kokoeluE!#-~(ZovJ(rQUc}BYmz+33 z=n#UqigXGAQ<7Q@gJhTjB>X~TdM6Gg6xeAIJFzf31Q`o@zw6jBsNH~*P8hZx!nSof zK;{=>P$~f{fe(aT%Fg!S70(aX&hO55?DPsjy^0(W0;ag7BU?ZM5`H1FKIR|}B^1~> zD0a4o*&)bS@ZE98jzP_!JX{mP)=yZr&IQQ)LJUeJU?uQ@uuIw55wvU$v-6jpovaY- zRgnQ9V2WRv8)6EO@C%XYoj8{51i2KUs2*?Fzj-k@xwLazQg(I)KY3o5owjqGvIRmA zQ;}&QU`kRusQd=WeMmOFM%3c(f?iGU_MDKTkFVD<|n{6b`9%t0JVD6q2) z<>woAhuI-WoNxAR#}4uM<0%YVg|O)tkjotgy%Vq!_(0gD?CcG;Z3@@UFSx+Po^2(- zU;(RO5jzL|IZ1Cd>+Xlk2RU|;>7h+H<0V{zIgk8$c{@~Nk4YRYI>wB!7jY3eZ zBAbPPDSk<+mMK8OFGQwy;!r|?owX=G->^T-4ng87oo~6?F{oRR4LgAG$$}S8znlcg zDR&Gru7YE#K6vQ=gxN_bL=fz36M`x$f@fPLEQ)ai8!>z#JKLESHm zLy)mxk40O1s5_7in+An#Ct)S@3&{LJ40GGLkR_T%7Ajd z;b52@f{X=&qfXg~2WwV{3?nK=DK> zotP2CR>hyUF_ax3TM4&~lE-6#&N*bovWfiMTcN(@;Us`qu-cKzJDS@))DA=>5?(vu z6>e{XK_Sv&-|St@r1RT<9j5aptW8mExQ@k;T}3x`E_oN4_bN||PQnX|lmKvogKfOP z8kd3?4Qemel1OJs5F;$=B6M=!bMTxZI={sg9nyIuofs3HeWwau_jFE(PQnY*NdU26 z_P@cAu5XB+AK-gClqz8guB=U6(C6`kXXWSm$cTHdWD42e#{3)4vevEbl+ zPM!$5pY%|JC4%P@gkY+T)1a%LC-yOHqlC#pe zqYw+x`0cW`R=VqreZN_N(5|;aqSlKm+};g$1W^|^igkb#?&84S!X9lE>&8~Gr?iW1 z?O^NINjh9fvlVQ&D$acy_+qQ#c@mKd65DM5VkwC`MIwJgBo-32h>W7#hYf6z+$z6g z>iQiBhQ_%X5VH;(K?A9YX6q|cbpvSAcI5a#Zb}jz#-cEm%6atkFi6$q^#mtgd?Og* z73|R8ac)J9j$3FJcS&Pc(AdJDtc=#iJ_E7>ii!&GPxMA+;3%KXx$`LfALv8)IKm$DKjAzh~GoFWdbLo&Bv=VtQPwY7e z2@Xc%Wq9$jKH}^i!sBJhf^R+&fe`FOE?TOXUBin%w5qY7`q^sS_L|>g`!1A%kPDmi z7u#dI;=N7|2!3abgj&Ita7l>7eIuj=du#{(NdW##+QKD9?Vn6rcx5cO+?wbAN?SOt zws7zJ{#b3n;N9Tioq1cR3b%z-r)mpd{_UyTLe;v(+QM5<>a=a)*S9Xx7B+@Uo~A8i z48WgBTR6|C{gY`6ufkQ@);#}L+QP8f!d)2MKvDh(cERB7@$k;PEvyZ|QD3;#ZM z>b6k+%*EQm8&K-BZQ-Y>McTr;aLLoO1srfdEUqnZV3OwUsSJiEi;R&n8i2U7xAOxK zq+$SK;c-2s0}#z!HG>TeKnjT(wP1|I5f4q9AQi?){Tw6pYK+u_G14Q4L~WY0t1Kn~ zi;$QViSCSpJc&pJi5UDHfuS!Yk=EH}z9A9|i5fAY=m5^RE*T@eIu=}N&C|67oLf4; zF%m{XeKtlK;ur}M9bwEIh6flcjrcLrMPn2xCjAJgPa_~uhY`>)M?k|< zuYqVXo2lu#WV}{tZer}SQ4i}vqod$k|6NdX&g^4p+~sZi{xLs#y3=ub8uDYGTTtY* zI(}}_@fRNZYz>!$S8+nArv{Sjz8@m7t!(E;gYA(@kyLRQP6Ry5ND3) zZE#r%7Kd<>^BB7>^d&XXQQqG&hWlHN<9PG2T<%2l>(%IbI3d$DYReifxVdo{x#N|G zaa{y&R*Tf1gIv#g_&UIwFnA302fT@z=wxNj}B-U zTZ?fZI|0GpcKgGP&B;2Qr&oU=-kWC5OJv_())Z|$FLh;W^2*tgYv2szXRVpI2_U<* z8F$6UmWz+4t^}dYZ+ycW-T=Sg!&CSEW_fbx-nl3FVD8~2@W*rBNjCL~=+|4Kcc!Cv!fN2GA04{<%b9%rM~|R`%i#a+Sn%Q}Tg^w0!$&t5?b?mv zFk0zor@mw28VjD{^Pu~52T?Ww+G$neJUH->Dc{9u>UTxBWZ~PQQ@<}Y6;z{XdSj+V zTu$SLw^lq=-c3EBkvJ6RL>MQ~rlUW=bb2rvh~-F#wJjsM4D!8O&6WjK-?JAFSt z19obRnqqd|5iWTec7Ah9F*}`kcDhQ~VT)hD&U1juP12(wcAB5GfSn)y>e*w_qQh(!6!g9j^MaFnqd%7CSra{+mU9F=dYm zmn^1i!P#N|WB{hvnPdh;3{OuR5-~x(*8lydXCS8NV#G9uOBNHez<*I@05nde5|8DD zGmfW2(TbMnkJHf~qk92~(%Y?o?khTg&d%Wfahyf>1Xs}*EjhhCIei8kG{qMY=kajK z({ON^0q`8;>jgtSbgIiBNG#aln~XD@f?y| z=NX-tdNn#vm}bY?)-*f#31qP0IXWzEJzs%LuCtra7@c?N(t>Dxh35detv2-BX?M>g zc-QWppjPfZfSly+9v&D2Mv@`3O890vLuM#Hhs;LDkf~&Y zlL%)Z8y;yYF)zM3%Rv5>2kEKNrk*)&>WL1BsG&5^({W06+fU9w$)5PGMU?Eia7j>q zs-f<88wJ4C#43#eP=zZYr{KAOg9brgf8F%;k-fE-RYq{w|9fv;PWys2ST&O1^Vk!E zcl9@p_6MfUfcDoJ>O6h2Qy&SJJPqwnE~34>YZ#XvLFJxsVg;X;1$Vr8eqM>%gHgXC zz)~B|yJ~BzOa2hlcddW^h1`LU^T$>M6CeJ~d{=)c;lrOnLIiMpj{7QpH{Z1~lo0lar_tybmTPR@`hxd22h7#WK#uAEn4vcT$$q8vGY75u0SLSDy&m2hZ8G{Pv6KwV; z6-M4&vc-7ViK-fmo@5h1^R9``-T2tlm1yQ@_PD6N?GS`HgZbKg^knWK$$Y2tAaAv| z{B4ir$=EjJwWi#ZjX@PqHN22ExboGHu&Td%9Zu34(Oj@R74HK^j9spRYFyf5>bS=@ z?TrPdcK;qs9rR2c_kK%3Q5iTCU)MuGOl5cBe&bsoOj}x8{%(}7|Dgr@KR2q(~vKUsuT=kolYIrBiI;*>*mJCVCJAxC9|ojHlBf2)dDw2 z?t8=++k)R@+njQ%g@OgNu0-J>smWwbbe#OzI@y@`n-G7K z#$Q|9I7_yb8Of>IQ#L=cxKAurI2OzCSN%*tdTT2@i%+(yAd7*qXgR0FB6^1z+T;R@ z2Z~t4+z~8(;T?`e4Swca0kSw7?j~o+qIHuqVsTC^p3Hqu{qi;F*@SfSA#`$BE&kTC zG#sqFd&H7qNYL@E`G7-Kp4z%DwPQUO4CcyQd6!KhFXL8(W{MU6*{Y^3Iv$w<_=a^|D7E{@${0CVyeL-el#E5`}1}we&7q zpFnh9ml?fgm20SaOSXtCypSkS%GO+W5wxCyVWX1Rj2c%foVMDz|UBtk?iC zwUGyN6PB(Aoe@pt^7;;(v80_k46F_caK9zF{Qz&4iLtdyX8% zAk->%i&gFyEH`P8a#-r?A#SP?QfoJ>_P%W(g8ko%L@*YjY4M*fZI|XEb$RZg;G@Ve zwH$$;1wC@8b{MLAszAb->Cre~fsD+q576&RcgTJ`LCSl#GlZT*`Q3p>ybIV zXZF>vd95G#glK&C`$S_)G#78oEo*o*KgF9t$f3yQvvh4~?oc$>68%ZM@hARsJp7p- zaK_Ae%borueN#gO_I6wWH(Qvxl^g^ zAdaIOQ8#?UNFLf(9{gz5!fX_(I9R(b{?8qe!P@l{K(OvX;81X&k7Qiw9%?JDj_K?W zjAUcM<|l|D`_`1*;P0f^j;|K1NOo2RwQm(+=uQeDidy5r49%sXdnX&bUTotH%58bg zQUDCjIWVF460j6@M2Kt&Qw5Ue#alY%!s|$b{enln?_$7XaPxN^0tUKBF!!wLkOs%D zzACt)NnbPZ|0pY0Yav|`tS-H-T_1>v1(UJO_Fxd!7a*JyhQOxnAyk(_s0~BdR)Fxu zTb7{VL0gnB(6Ge|KZecbWN!aB>(0VB7044S)Exy9!_gkd7YmZVv9kdzDpnDhb~Xt* zv3%es<5Uz{O4yv1E1yn5VM+@|!d4PvU>6+9;1j#RK3D}>*kM^XEaohE(QVDA`H`cO z={Emio9g`R`VyJ%vhODIg9VAb@8%*@yL_OjL;%b_LWlZ|h|n6n-?%PyUEC^~>AsrY z{@y%Ng`ie-%tzz7FBxVv>E__v2iOc-9JR4(PxfjjV@5p3f~Wo3$#^TphdZ0`5B+yD zM>(x>Z1BKLJj*%JOmQ;3f>~k`WJ61E|96U5W5?r!wcBIO&wSj6z5c^qNipk;cD~?2 z`)*R~ElBaoco8b}j%^+iI>`3HD2xT=*HIH~hrzq9W1;Xi+u}cnM9di_*OB{L7~4<* z+e7I1Xh;^cw7Ir?1*oO9fviXvNKgRs{xFbmWBY6=5E>Q(;$}LX3UBR7MY{&^$$!Lo zw7N60OEuGFUZ^frR#(9>)YH`1BQI1pOXki&Xjv_z0P6s*J4r88XHyn_mEPc?F>1;Y zC&w6$Co`R_a+!yXThu5_wcK>hl*DFqdUjbc#lro2$ch;dvlcf^o7WlfanA9iT6?T>&Ff^_k-Q*H zyH;cJ3{Kgz{@kWA!B@XUiDaE1w&HVnhEl``I{U(_W8vqkun9u)xf6H$@T5+|ACe+F zG-a`qiLuWG;)M|0LB+VB0RL=|=V)#AjsPZ0iGw#)-k$Qh@P_ zC18BM6b7+4Y4qdqXe(gcbMn^n%2OYtPNR;m3GVuOh+OY3g7v;L9!{qtYs|@+zAXB< z0TEpb+{WWKJ}y-^!QnJV&nWxwsLIYqCvp#l@gE`n``%N8|8I)%lVrhocDx8by0%G= zA6*-l1q}amO*A0>X?T-8{~@y@RdLzBu(H63LE%5XMt}-Ujm0u?j>2_R-=H=dwc;IT!ug6ywb@j! z%$=}&)z!g@*M|rijB|>_!Kjx;t;7`x6DU8!jL(4TDj6z6TyC7KvIFMAnUBu->PppO zwtaWFxyry>7vTgTttL76sN~gR_WKdbT_+4Pgdk-K9DSNE5GAcCyTwv z+g~UrwS3fDi^^_h*|3lLx9=|j_N-E1=KxsONXP^Iwg`%Zebh08pC2vzkfs8u+I2Rs z{OUU;nWL+G`g%*h%hENE+29TdLx+eiaLDzj_E6Fhx*o6kp7n%RhbjMv8WN|$uQQPB z-^Pw^^Y|cpx>cefe6?;2-ud2Rhw{T2yoybqMA9;t^nU7B9#yCf+#fns* z4ie!_z=Wav!|-Nml~^c-4v#XGdI>q@9A&HoX%l5 zX&4SW3?0JY5_fyb=5oi}bQq>!C0t?hfX~7q#&J`H7Kw`7`?K{=k>3i{e*SOb?f)I>j-{clwM8`z5kNFuc<{uXdm{Q!WQz8{eI_?2!-6{b7Uo$t)uBA7 zkiEnK*XVZfvDc3?n6!gHAe6aO*)6u{(UfI}V>wS*Ze^idfb1$ajoRQ^2G@6k=O#7A zvL&9gNp=nkBy&@*Ko4;!`jC^|R@DfZlL}TDqw-jdpT)IB-8Mu|Q56wZaD-N+;b8?v zXj8m^g&o(*VBkNcWK`ff3>a{eI7a#tTB?M;j%tuN$>Al=wu>}e40|&e0VOx_p|*@_ zmRqMpKB55CSZkloNs!(n_}bSH2zWl85i;K1lr6&;PQBFg93|8(l3QWqrZ7;TE8s@% zjTr#Duz9RkHSr3%iiiDZ#{o>(yajU z`$Jpo{-vR=rA%y?syYa_ts&LFJ}=p}I1Qon;&D8w6mRG`JZfO%Yvu5fdlssEo^7|LhbDSFB>IGw6iz*mT<~; zMu3aAvnSaAaEW$yu7`f6?JR_-q@CSuLoSO?SkTV8O552E`d)jfY>^cK)ej?gywI7k z;A%B^EtiN}espG6rxxh0-yaKRcUj-Y?O;Pe=a&d{SQzMLzA*#0I7ATqS-DxW@_q;~c@7-CC$$HWmy$#jP)7 zwb&6_nTx>gVcLm?4mqXVI^mGaoU9wa7uLTqn+%ELhp&}5a-T+JaIGI}4Wn$sC;eIj zdP5FFVC^u-N}vzG=!RngTWc5&ZbctL&%mBu?;RdMMI9agm|NNABtUgmf#0MC&w2$8 zyvqN~8m-c6wa>gtuWRhpFIKPhueMnIO#f<&)qi2HC*qglfhbSJarudR!rd#5jCF#% z-ZFCygk)^+ubcI{(Z6odYpuPm*o?nPol0$IQ?pkstToJEXumWjkx!k9lx;m+9(WTYZdL%XB4xo*wW*dGy-yvf3Hh;1RPF?gOn+>Wynt zX};O%0;pDfOI6)s2NiIEQYpDFgSwPoh)=d{bqsG2!#f2*zeNlW7-?jfA8G!}ZL&J@ z5loqauDp9DW=nzmZXoF_w=)9JD$KiXivmJm&i+ApeT^l0glpt`hr8p0d|T)qe1iFa zNDkfg^mPbAE?dAW=QXHk23UW=lhRyO$SJ+BDh?rgEI7K;G~Ha_D1T5~`0}g@I(4yG zQ$*7h%=a6gop*lgUOBDc#c^B^OZ$fPD|3|48+?Lwaq59A7r=KSTe2cGZHhP~;$l^}x>|WCi)~h|NR`!(Lt^kK6U4zjc6KPLPw2SNPJ*hf$ zxNTZz@1`0@dt9i*R*7Z1iRFyOEEHzFO6_#Q+#zB1reJxBg!y%&kYgZuPs>-BAFrQ& z&B((Tzz@I&rro`L4;x98*{Jmp!(dAmanfWqjajg4=CqU9q+}K>lo>pkklA0q(#b5a(ZC8rJuaDz zOJ;EIVTw0_$k0>C%)m|VaNx!%vsqV$GAo&qLuR&WJ0Y3PN@jDAne))xJUs^FN2|Nd z@L_QbnjUeMP4Q%SR!l) zdrhM3h&Q5-Q>|nCrnX|2I{>dOh1jd_eq^(7hyx3mRn)Vog=Ix+(wBwGf#5nQ$0e_@ z+EgaHdeD>0SsR-jl24bzsKeRSnoy z*;zF-^=|q7lvQIWR(TWxh~^A4t4DQ7ex;ViAFZU>t<*j)b!D?I`w%X6hjBIS=G+6J zT7W^mYUw#JA_dtaLH5e7G-WG}YFxM) zgG0A$x6$Um3&(O--6({V7Q`AO-7Agw-=m{q-85yl%d#FRu8ng|JcNJ5*M`~hEYYwo z!uONIg(TZPed zIJrerR10o}jlym-tRPYTS__2yN97mqm;6U0|53B+zrO%?iFWu%$2i?qjr)#d$S9%! z$GiZ|um@g%K|yV>STinJze)8JvUsr+BWLt}W zU9Hzv|5~lrHhc9`+jjqIQ`^J-)uy)pY_BKcx8VVGjqvTY_-$$H@cA%p$LsC(>WqI| zr+-~9lwJOHvtGO1tFyi`G*TGqB-$hKcAhIv7Q`Oh8^`n)ftfLT>NsYX=QRZMFF>wE3=69?FIlc z!L%}kgYXKNBZyCv0VcTKdD1_zNbnk>@bbg9GZwhr%1=g|F5bQzJ{1G81!*Nq!76kU&r&J1^k zy|<=)S(pp;=2<5#^v{r1|3Yb)b18!FtGYx%G=;+ibAb zcvwd$sv%c^UE5MS4Eofyg?AXNI0)7kSm*cK)NP@4{_Nk2eACUgtcfob?*eZwtrd@C zMron0q^*q~xPznJa$s+Zlm39DKVt4zh|gP^*BE~U>~<+w&QZaqF33KG+@V5RWJQON z3sIggby6Rtq$cuHRmF%*A`3`9?Op{9Mv`qKj_P4i9WWldsJZpLEH9$KH87L(o+e1V2VOMnWB(S%Y%?l%Ts|>#`(LB;A`+S&_YME!_SpoJ#w+vr+HO# zA9mP>rfhvu$8-n(`Wf=mPdcm!!@Y|6>A=TWaN=u@pH93cb=9q1atjIPj{wgS4%x^s z6Cao&ewZSDED!jxJjM?R2!3m(Ok6} z{BI>tKvf|J;RvMSsFjZ8Y{gM`89dcBPdE=Yfx*0NR}sPKucgPR6BKJ>hHzL3O5g)iR2xiDZCD=EhUKx^AOXSIpe0lraS9~g zL!7cX8SQR(I!hvS%({=P>qk!aTx+YqBlenX>nVIH%C=vN#rbT#g=`8wm3}=sY87i& z3=5aIj?Lc{!T59jF0vZjAX5M@RvD5~x=uZ1N5S8c%|kVPoGj?$Ke#EX(`n}P_aRGw zaq^T*Q~>6n4sgdScwCA18l~QNFr^!p?NE3ujQE?Gt$19;SE=}F{9187)#!wGsx#jf zs} z+R^MZ6a+=hUP}yAXeIE0Dbj4FNV6>uRKW6>X0O55U>#`rf70w>$!;BqP(bryn$54$ zY(AJ~s{o1BLte8tAVbqJ{z|jg^8x=+vzZ9ZW>V^~O4%9m1YJ15oq z{EX5RkvaWg_Lf3o&54X-fdLt>ppZ{B^6yf!`Q{G0r)F={s}+x{cnm3nauHkc?JCYx zYBt{%YWAhOjB98%0ZOx(lbTJ0MVgHv-43J$|AHRG&5NzAF4XM(((EssaGG5&&EAE= z&ZP{ECMasQQmG?K-~&^n*-VjUTOMe(Hn}vm7_Y&oZgXPN=ah9zdVj-OpW}`rX8uexH&A?Nn=`XYJ}S3*;=iZ zxwR(R!fiaQ3$?Z(yd=#H39Y%Waoziaj>nULz}-R7wngd`JAa^L(Kgj4GU+AcwrFbX z(B7GLlEJ+*9kq00)B#+3-oUyY@ts)aMr2@eRABBl z808oXa_H3DzPqxyfpfsR?tFPzm}r+`4z)aOn!FrNgA<6kL^(S%=R86HgS|N%X#-e@ zTI@|lyLs{p{`Ms4d+wpL`~a%!o}qt5`1*A?fs*?lJ{oE*ZXF*Ef}RwMaK+ax;`d`Y zTA@h&&KrT1V|XJn-WyRA4)wzt1BxRNxRXe=?^f<@0v+Sj+yTAzW1^4e#XUG5 z?Vh5U1vaPssR!7jqaPx+6?-+s9>)@{JD$_nv9TNCy{IhXra9x%94`4fq48Q}Y0d;0 zq~=UQa}Zw(aEPyULos*;CIxv-qK_SWA)rb0KghE^(?bbf- z5N|HX?oxNdFPE>|+*vkzi}ndry%I70;e7&Mza9zUvuswJDA{!I(1j)Y1YSP!>-nQw zKJK;!R3nTG^T)f*J92b~PhVr{A9CsSK7FmF|D&bLce2jiKEWo0c0-M#v#Vz?ia8_O z=aHId&yCghv=T<$krZ%zhI59F?d*?@UTYQwt_8aEg4ZzHwp=0 zTS32`WWtWSWaGjM9EKTT2n_87p0df@ zF-bp0rN%#?nGJcPNgTRU_qN!2JIK?mh~h=3EqRl z)B`AyjCSE$Q}!T~8Nxc(!O#>XGx6lNyA1K3Py{XXWnAlZmCk z5hQB2;2j*jmS6ue_(A@UM4N-2Bl2gM@tqlZ2}gWEODb;zV19y}q4R+`BEsGTdpa1NCmLlwtpqEHE1tuTwP z6+M=4S`45;c>kPE@tD>YIv#*Q=}$`f)47KZUHtxc;y}I&ZpSaF+)*J~DF|54SUTE< z|2twq3ilpkzo*VCrmZ-&gl8meQv|;^jr%d3gs+SRAKQ?ZuugY?gvTl2IWOTkJLmy) zAcFRCiv!>eHjAJg4YqyINw~#_5<&gxyQ8&G8+K)@ex0L+MfW>@1)ujN<-!=0 zQ-B(0?tvPmGUPO(p{Rb%%b}W*H;0v_au#w5Sk_c_sIK;f+sRJz|2VG}Tgxuo|Ic4lO-+pTMq4BH{9&l4e8XY&~cpj7!qNM%c_JuG0mDTQN za3?pi)#%E)8#kJZh;w|Vx|%-BXLo;|Z&BA+=)}D8<&Mhy%3pQu2dvibU`?^ccC*GR zkZKp)kvMY=mQ>nSRT_Uol~zb}ZWEU70Xs?UQWP+bUz2h#3~E;=nZ-@U;;I_ItUA7> z4(rznTGdq{Syjg`R&{ZKQ|;NR4lyz5`F^n!+krIm=Bgrx!H6nyln=qf z-*y$r*P<)^@)ap8sLQ_)SH|R8((Ng*tMdlsdjPUBMpq(R&}{err0!r%=1;?MP6`ftUScJuj-Kt>Ec(&P zyU_tdazmh#Jyk4tvgKl`?`V@KKo!{wzyUYACGC|*;=ZJrM1)%3+|IozuI1%7sq@#dEF>(GT+GQ zqi~^mPzgDTpb|{=D#2$9Qp}spH@TUQ@;Q~*fNa4Hx4A~nnqv*_!{6W;NX>^PG-WsY z199Xif!TBmZby)Jq4B&U#$?@f9jd`XqOIJy^)nYg=O7hD+Jl1qAaPKR1FJ#05NhPz zU=8vuby&X^mtkGOJ|wFK`Q;31uovW_2K)FYsQjwgUcLIbi`_(&uR-6sdE}t)!VWM8 zU#$z{7|uo6hw5=xELim{tH)0jycGz(7kn7xxHri0y!*mz@}0K8ui$%i&^v)3xa+X1 zJJ#9M+0L%+$4l@Ae6lzPwm%>3mkeL6ys+hMM@hRlJXCLm#H4OscK0u1)MUUo5^7`k z1MqbWMq$s{b#&H5+c*yGOx1P5#oQ0i$*M{1Y z9bLBH2CZyN4Etlh8}3>6#Dd!|HSuGrfI$6jjx}3362jG3c5Yb@93=Thv&no=4BfYp zP;+n@>;EAWGUyN2C<7q)_(M3LZcs9p+*@Hr|2e>n&6U=#45?nEWC-9rgGugRqz>?>)$+0(@&vpWv_ES@@U?KT39e%mpPJA3JI@} z=wgX6SdVs#SF}|4MS4wK2+-}JxGX@o+li|~;_7uf4o^88M?{#-mu)Q0X&W@N4bVYN zo**1Ed`B(&YYheR$$s>}PYPuAox4rft!Iz+4MsCYZKfvLM`|;vx(r*SRc@!K&A6%d z8IM45*Qoi&^TSVC6b(OV#h?TD&x69Dv!H?aKq-%# zd;3$QKhmc5;NtfF>!I4mZeCXZxT*KSJ(8cF-hlg`pRRnl6u~)f%HGTJ6Ua&! zHhu9ENSoAaU>7vrN^OL141`dPN-KH`QEN~as^~(ZwnCxk0E&8NMOM$gCv#p2RJ83! zqAP-}IID^taTTpHHq{^%B8O?=sm2j~$mYjYEBcUNBP&%jZMx}5dzQm!$$pR9xJ-K!6=sj!{)Cc7QBCr2^#(IcujPS=1&JQjeGM4Z-e=@=?Hk9 zEymB|NP9DX{lVpFSEC#p7bXzHz+_W{v#re3tDPf8${|+?6lVh2@-&tZ52qihA&VRZ zhe~MZ^yXOb-KXY>*EvPckdtLX7d8!r&MYG7H*Hbg`RH`+J^^MAR525RLI=T(=8-+ z0wbc}t*N~JF7PYvX~tHPg7#|~H zHh_mn2aewq}jWZ2@C-GNO zR|2KZ6iJ;alDg%A)Gd!meF9&D_k)&#)cul&lW)DFuV~@JeLLXAbwIMe<%xOjRcS72 zlFugoxq|pB))nDwg@}`i0t}-wXZN67%~lCBfK?+GI4gl~3oGFVoAYD@$e>DKPG1Sm zWjTwa;O`T}JBP<5tDy%UV?p!BTs8FK)jZ}F`p0S@C|1Ks!lCq)zz3$N8knMLuso;+ z%VX6*0)j__mQXcxQzTyh%_nP`uEDh*D_KoA&nzXKiqlK0`uN4_ydbPTdho^gwE9@n zlWz_OZPw|f&zwmYSZGj1j{NL{a+)IpVA0oJqg2)h-xk)#HE#VJyhM;e^}(F^`mmv0 z1(JdXnuwSFS6?4h?x7YlJ#|K1U=ruPe8km9H(q^gVHL}v9teu{p?6k;68OLr)dy2l zAC?F8VR@`RNI=j8T0-@arAYGi(JS^%H2hLh9~!>8>f*EN<8_ZOsgHp?5UY>vh5DFY zTZEiBz5Bd?)K&xRTtj3)eN=<+8oByeAADO_A79v%Cu0>ds6Lp}*N4%vuRzN#qh%qa zw-+FhD0j1o*ft=|1t5=K3dn|1AhdK==_@!*JK6&v_Zap7{nXFwx`p{@rZ_*v`cp z6Zq};HTL-A&a?q|zPU4P9QaRJZ!|AAe*yduN=v}0aBsye+H%#KW1j-vC5Sut>jcdC z;-F@SMggadHQJp|0rSm8KRODY=_%l+JOxe@+KR<#tGMqhPBcw;LpV{ZJ9~vnzaW&Z zhT=`_`;fBGi_cUNTCe;nF2Bi3Q?z8>Mj{x0z8 zzwlW~^!1BHa-mP34CR`@GaPqC2btHeaxmJIGum;YYZTC}Xl%x_0)q2y zy77S7JoY$tF(M8#olY<0>@%E@yBTI@eLH(Vk@zwD=+d3`U35?-e4=UJ@51u;>yPNs zepr-FUm_MttyhCPu{RuM)l1TjFapu3)+enj1FZ6-^@ycDPbnEwgjGKtz+pcltN^B; z@mCH^{wUXe4@S|BM?0xT(di;J>Uw*KH#aZL244grjK?y<7phU4)aZM+J2h&T8VxZL z25OYWNB~c;{&?i?kklwEH9|Vnh_`w}-t!Fu!L3E|vQXN*(GSR@t0O+Ej#?irk_&2d zGL%ab%DkiB++zhbQqJgzsnLj6Bh4)}!v)jhZl=q*CHzzqfDJL@?CUX#d4jy>?(O@nCpjv^%LscQHL-45t}mV!mwb zV|=PvF^b=Jtq8sepy|t(H4T)#`noUR@MLAat~_`x(m%qS>9SgceV(;q$8+(#bvE_r zWNbEdd0FyBWvR={lP@aImz=+V*#!iX?~gElvTRMT=|2!mtkQspr@ct$ljh{i$Wpb% zM7=2dodpJ0Fc*srig5UR9Vk9E%`L}OgcW!aP(k#}RDFbu)~I~r+SJ8_mXa{iFFh|^ zcG0GxM%-DPJick{;LkqBtRG_z6*A77o=;994V7f(mH!@ze2nk8$0f4$mn65WDa$kZ zdjGBI`Qowu3BG96AoATulFQb-08WSC9As@8s4|Ir83?gR2wnu^D}bjR=2Nd2;od0QNVME_-!R-CV-Dd9mu|#jKmub#tkPlgVjcDX4!ZiE||I+(pH5 z{}MU|^OZDBR{>?>fp?u7{0kB{jWu49c^ODQx*I=`L~{F@vfx8#*b`6X)F5(s5Jzr4uHHq1V6;_o59}zX}YTR-tR9z>tbo%OJ@f!n+3}VL9a+& zRfbK~EmxJFc+t7bLiAQpE-!%WST~t=V(AKD`T0e-9_VhwB%(H$^IGH#lYgT2cafkU z*f)(eJSDdxSW7~B@sr5D>!L6x@dLk$)K7$2&GZmiCWP!3AhY{2nqbGGt)B;Ag%rpdY0f1cCRwdZCqO5Cl3jTn48_g>2B}i}5-61#0zN z`q%USwk(lt*hsN_8E?rGd_S-@xf7y7jx7Nh&4-2$3mPw`%#fd%Se%`>29`t zWC&Ic^#!Zhurj%)7rKc!#mkdpi3i@kB10mZvQKQ9n0e+vddr$8B?p^+Ji};FAUq(k z;{x?Py*w-+GIhaOsCpFNT9Not{bPL~-CLH=w`_Ud{H8D0pLJR8XD7DQ%txAj zdtSq4h`anea*xVf)^fT7u_@U6{Ix%_Iv|y zz5{Tf1F*jUU|9&jTL@tG9s_WQ02+@ht6$CEo63dkyximPcX|DVxr~ zTaDlUo4X`4L5YUj)r(hB&HK`2SLa)I{J_abJx<#GHcr~c@9R!PzZ1dr;8JC<_Vo9l z&Z0fwP7-6MIHmjNilL+q%q8Y4o4X-B3M8hQ7KQssZDryRzF>d@uoaZxB~Ad8HuQ2W z2n`;95Sr#LsXreSCacy2zdeajv=vF#uPLX%nVs;DAnT@?%H|D(YPr9P+*51;$vxf4 zFC>1oh#Ej2lF_ausDQVd>TyYHF%fSCSbPf8Ok$b!^T>++;C!c8+emI*5Bjf)kQ##F zJmm=5V7bqxAkyzpQK1@epO54@J{KU8Gs$oB8)`igx#H~?CXXkwF6T=RYzco$9)Eb` z-nl0|`S?pW-PiD>S@ygqdSH3s9@pzudPy7}{?!iePMLIyT z(Z8cb5UJe-=X&5`{n%0;oi775}vU;pr}k zK*+)-lH2QAY}IPDDg`UP=X<3}aYd>L&}>v{qfiYPY_zoAxT%eT5FpR|KA)L;ckgb( zzyA6D-h2MZ-aGfqnKNh3%$zxM=FFrlZF9q6RO5i^=}~Kpxt@1p;-*ZU6{KWrm=dFA z^NvYLWh^CvbyykLNynZau=-o@7xQO-1FPDChnMY>aOm*N~d-J2Kdl2(3Ca)OWPcolqEh zGq%eLax&CPyIQ07S2ohhg9cy35Q>ynkfI9$`Y$`L6o&d$VlF!)u!XejGtn}L{Ho{< zrHNrnP4?!cSlnOwj)0D7p|3F~^9)u>)aYU8m>wG&@4vqR5!;|B$*}?{7lMfTkKLD% z#9mP_8o!GLn`f=ngQyKI4o_LZe5tRQduUjfG5Ad#0W#(3r^^t4tk(f(0yC5y?N9sl z7f~Br#8A1_N@WYLL3!UpSnjywp$3A0Y&cmqSiRrs{Hpd0p+i!nbZTqr4@;W##?(vdP;ls|2E8xcvB{GfxERXA<_Xjw zbgg-65^9yeTHk@Ez+`^UGkw2;-?6{~z>)z0MhO7Hx9bT|L=2@S4BsSTc(|6I%40w6 z!6$};tJr6d(}I-1b%Zk$@d{FX-^RHw#-G}x`h!qi?)H5f@4mwKZG!un&@F-4%rW0o zs24dxHwA8C`kkiqJDFY_Sj6;dQ+hemFA8{L;U_bFRA3d;A2z{fB0ca}Z0ca7vVWA? zuU34SssXuLZcf2xvwN8{Xs zLbH5F6Wo`CN&}6=(Qd-=I|y@VW?&!Fdrj%TX8Pp;>wh9W9e<4G{~6QI3}iBWk}16& z>Fn zEhf^w;8H-28{Z|0I|*PGUUw{ty9nVmp?EQZ;$1xUC-WfzAm+Po3DA$s6j_Go`Z=hO zY-mmoZ#JNyw*-$TWhu+BP96$a9P1L3dWB7?Xjg)Vf_!sd4r9=vd)ndCgh2ytm`}kU z!?SN9E+Fcd*fOZuJ?hP;h)guFj;s;nC_Omp?6)Q>!T0;9mbN>7`2o;|UIMzPk=?X% z#BkE;)dwtJmoemo=l&TdT$it)ItpGAcXvvJ- z+FlNcDfJ&zk2$zC&K=+WHV*%ia9qyx{t>settIsN-nLNbp*_d>y!*@DZ}0u|j~#n= zKkGStN&4Qlz^iP{?WWfJPpo%#YoC0@gS`_p6^HxGLWji;CY(O)o&T^{yi?Z+Ja%Jc{uI98nGLA<@hmc?Ye_FdEOF0p znVrTFWd^2e@cdG2-WqJt{seRY5#RCcKJ&L=^tZqM+LZ4<@Quj+&6EL*=ftK@D%GIF zC?@*LO~w~pJ7%YzS9=(n8{I<5a2-Gs`#Nb;0?k(KBEXwX8+uQpvBVhEv@=L+n)f>} zr46maUvq^QY>E&bP02189JC7}cx-DXVMu1Z_To!m2b*=5sad&mZPdv-^#wM9$F4O2 zL31MC;-b-eBH)H}ONHjH6M~vyhnk8wrXpbX7ikfzir9?F&X8ib2@_q7T`hykl#0yh&942(p5eI^*^|9T z;@ozcO7>fv?|Cvqrz=M$?oqlYwlHPTR?jfnL&P^Le&e9F?vGsz>D)22L{6?oBbn90 zs?)-1VbJR1@F!KmFLjj=Z1|^Q(pA-9K9;eVAM(@rBNPr46a8`E)L=gBM5mU;K!lM) zST2+lrPSI_dk*3%wSf>z1N<>cJx&&*)NrK+h827;U_l`y!dsIXw^$lr1}4=252KDk zB9=e{Rdj$4x(vgKMjfMJ9{`Pjy%IjT%n(c@6nb7CP~i#Q z9y%&7o~H6o)Q(7)5>5hZm?KwUsJTE*BR*N>=pB(#Y>E7JEnyV_BeMCeR17V?siFdM zQ>5qxY>M#Rv?(GOf!fYAzWJt#igHs#W;Jh$4BH69;@9h_bw@TuBuo9%;?^>!l1552 zC#ozsfr?l$-sFn5k~<=>Lt}QeOHQXg=`*&pWOvsqoGdttjSsRU+_Ik;_AChS=EjZw!1r128s=>3NKk?aQ+vT1-`{M?C;sbf zz9Y$t(+&m6M3|5hlw=9lz*rGalK1y32VBF0?#YoqEGC1T7FOyqZofc5u=QSqt2h=nN; zBE}rK0s}YQh))$;p1u??JCZ1apz z3+?Lc6m@3G#P=^PwhwA@TVJt+E(Ca8qdN&lbuvSuRmOp5(4KE$m+yNXJ+?6Q6-#b$ zswe)HxR`Au)Sg-?Y@XCCJkTs;(GPfY?NxW<4OMfqYLb$4ostw#l3Q#?;}xdl7N@wU zfsTB@uo$c7^3WxCR%hGPnKn{t9n?ff=5VJ2a+Hn@X{?v1g(NK_O9d(VZtCo4ZjTMK zag28g)Kqnvjoh|DKN%c;j$*1!%Yjv1`vDXzF`!Ym$j?8RA3wqIc%$gjYckO(9Gmjv zvm8bjH_QpPwfrXXi52JqtU$5S!T}_uV!K)c%Tq;aL&aOl!i}$|g5TaFiHn^LtvN$p zXNS&18qo&9VmVe6OKpZ*STF>P4i*!GC6p4BA417`iZ%>} zb>Gx+sD{O}SU(5H&8am2hkRt|`klRk)jNOyDatl@-5~6alAz4Cq8`d@J8GcJP7M~ObJ-RwB!j%c!c6&=#kc0d zahB%7@nVy^q40v{!fe3h;0t~x$e&5_XR`dsoVSF)NB z(YaW>>cUg=)`_KO=?vu^-{IuNqx4yCn3|*%&hRfS_nqvtr+nh830T~a@PKa##3ezw z0sSKJF03B)vBefT%{w#O7D^M9K_|+04;Bel@9o)#w8ONbrwN^8(n@vVMy1mHA8_)?)CUoEqZ3c+VM`R$a5Dy8i)QIPh+>G;5niGUD zL&zb_Ab+0_a!m+%mk{!93i%kyYs?mxT3DV?SOhCbxo_zLi|3j^IjLM=qVoK85W>k% zgFJor|Klf+FqR2WF8&JTB5)h?JZ#Ey!BwcqRox}a}) zxy5r4XVx33%Sxk)zwCgv39l%PkEh>@<$Lj*U~xG`Jv2+bseHQJ+n6~ATjb7VD{PLs zI(%~Oqy@i=*oGpzT3nv56qoB*77`)1Pm1U0De?D7y!u$P{HGR6GkQwC6{zqdhcjbw zCWbS0lseO@l&31C>FV5af9iE~PnkQ%f6W19+5tF3DG%CAazzEz1$`#W0xCwB$b3tS zES~ejb?wz!jk@+~7u^Gz3QN%yMP0|Lg+=*FVUeJ?S9{T@Lt&|&awU0FSgKAhRc9Ab zii#fX4XZg3E3#dkSp>I1=T)*0Cu?Z>zj54vBG(U zHlxkLN+9=y@Jdf{L$V^~M06!=X?YB*^@9*FIO0%PwwQ$F_P-(TwF}f~>6d}k-XYUc z(OI?=s@nwh(U;s3#CBT`zoc)9bfe$ki(0TinV+gGN{=$r2&yF!xcs>SeTVx#7_rjx ztW~*kw#o#iDP`T5;zHB(-zmBB{Sy5bp>|+lKrF(Edj_=YOQ$>#J*X**%0AbLWJEbZ0<2q ze7gg8GUM~6jPLywqKks;#)d?=D6y-^^4u3_cMpWwZ(ZSBWOLgk?k^>L45As3Qbqs} z3vQ*NLn+&*mZd6X@T^Q%D=_c2Diye8sf*4Ysgyv3^1}(qtLG?XExd3YEwr8_x0y&j z10-YW9pY;Bj7L`Ak_i@13AXe^r=o=o;y(dnlXm-VE}y%Uf(ao+K`Yk$N2y zbD5aDtQ(2Y9xRXGys

-Name